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Commit 964f078e authored by Yue Ma's avatar Yue Ma
Browse files

cnss2: Collect firmware dump after SMMU fault happens



Currently, after enabling SMMU stage 1, SMMU driver will panic by
default if there is a SMMU fault. Config SMMU driver not to panic
for WLAN so that CNSS driver is able to force device enter RDDM
mode and collect firmware dump after SMMU fault.

Change-Id: Ie457873210103eb4c4b5f4a68f0c08fe8a33fc80
Signed-off-by: default avatarYue Ma <yuem@codeaurora.org>
parent 51e8260d
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+21 −0
Original line number Diff line number Diff line
@@ -1998,6 +1998,25 @@ void cnss_pci_fw_boot_timeout_hdlr(struct cnss_pci_data *pci_priv)
			       CNSS_REASON_TIMEOUT);
}

static int cnss_pci_smmu_fault_handler(struct iommu_domain *domain,
				       struct device *dev, unsigned long iova,
				       int flags, void *handler_token)
{
	struct cnss_pci_data *pci_priv = handler_token;

	cnss_pr_err("SMMU fault happened with IOVA 0x%lx\n", iova);

	if (!pci_priv) {
		cnss_pr_err("pci_priv is NULL\n");
		return -ENODEV;
	}

	cnss_force_fw_assert(&pci_priv->pci_dev->dev);

	/* IOMMU driver requires non-zero return value to print debug info. */
	return -EINVAL;
}

static int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv)
{
	struct pci_dev *pci_dev = pci_priv->pci_dev;
@@ -2021,6 +2040,8 @@ static int cnss_pci_init_smmu(struct cnss_pci_data *pci_priv)
	if (!ret && !strcmp("fastmap", iommu_dma_type)) {
		cnss_pr_dbg("Enabling SMMU S1 stage\n");
		pci_priv->smmu_s1_enable = true;
		iommu_set_fault_handler(pci_priv->iommu_domain,
					cnss_pci_smmu_fault_handler, pci_priv);
	}

	ret = of_property_read_u32_array(of_node,  "qcom,iommu-dma-addr-pool",