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Commit 963fcd40 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

arm64: cpufeatures: Check ICC_EL1_SRE.SRE before enabling ARM64_HAS_SYSREG_GIC_CPUIF 



As the firmware (or the hypervisor) may have disabled SRE access,
check that SRE can actually be enabled before declaring that we
do have that capability.

Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 7cabd008

arch/arm64/kernel/cpufeature.c

+18 −1
Original line number Original line Diff line number Diff line
@@ -23,6 +23,8 @@ 
#include <asm/cpufeature.h>

#include <asm/cpufeature.h>

#include <asm/processor.h>

#include <asm/processor.h>





#include <linux/irqchip/arm-gic-v3.h>



static bool

static bool

feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)

feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)

{

{
@@ -45,11 +47,26 @@ __ID_FEAT_CHK(id_aa64pfr0); 
__ID_FEAT_CHK(id_aa64mmfr1);

__ID_FEAT_CHK(id_aa64mmfr1);

__ID_FEAT_CHK(id_aa64isar0);

__ID_FEAT_CHK(id_aa64isar0);





static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)

{

	bool has_sre;



	if (!has_id_aa64pfr0_feature(entry))

		return false;



	has_sre = gic_enable_sre();

	if (!has_sre)

		pr_warn_once("%s present but disabled by higher exception level\n",

			     entry->desc);



	return has_sre;

}



static const struct arm64_cpu_capabilities arm64_features[] = {

static const struct arm64_cpu_capabilities arm64_features[] = {

	{

	{

		.desc = "GIC system register CPU interface",

		.desc = "GIC system register CPU interface",

		.capability = ARM64_HAS_SYSREG_GIC_CPUIF,

		.capability = ARM64_HAS_SYSREG_GIC_CPUIF,

		.matches = has_id_aa64pfr0_feature,

		.matches = has_useable_gicv3_cpuif,

		.field_pos = 24,

		.field_pos = 24,

		.min_field_value = 1,

		.min_field_value = 1,

	},

	},