Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 96173a6c authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer Committed by Ralf Baechle
Browse files

[MIPS] IP27: misc fixes 



- fix PCI interrupt assignment by emulating ioc3 interrupt pin register
- use pci_probe_only mode
- select correct page size in bridge
- remove no longer needed ioc3_sio_init() code

[Ralf: Fix for 64kB or larger pagesizes]

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b32bb803

arch/mips/pci/ops-bridge.c

+18 −2
Original line number Diff line number Diff line
@@ -13,6 +13,22 @@ 
#include <asm/sn/intr.h>

#include <asm/sn/sn0/hub.h>



/*

 * Most of the IOC3 PCI config register aren't present

 * we emulate what is needed for a normal PCI enumeration

 */

static u32 emulate_ioc3_cfg(int where, int size)

{

	if (size == 1 && where == 0x3d)

		return 0x01;

	else if (size == 2 && where == 0x3c)

		return 0x0100;

	else if (size == 4 && where == 0x3c)

		return 0x00000100;



	return 0;

}



/*

 * The Bridge ASIC supports both type 0 and type 1 access.  Type 1 is

 * not really documented, so right now I can't write code which uses it.
@@ -64,7 +80,7 @@ static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn, 
	 * generic PCI code a chance to look at the wrong register.

	 */

	if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {

		*value = 0;

		*value = emulate_ioc3_cfg(where, size);

		return PCIBIOS_SUCCESSFUL;

	}
@@ -127,7 +143,7 @@ static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn, 
	 * generic PCI code a chance to look at the wrong register.

	 */

	if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) {

		*value = 0;

		*value = emulate_ioc3_cfg(where, size);

		return PCIBIOS_SUCCESSFUL;

	}

arch/mips/pci/pci-ip27.c

+8 −0
Original line number Diff line number Diff line
@@ -47,6 +47,9 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid) 
	static int num_bridges = 0;

	bridge_t *bridge;

	int slot;

	extern int pci_probe_only;



	pci_probe_only = 1;



	printk("a bridge\n");
@@ -100,6 +103,11 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid) 
	 */

	bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |

	                         BRIDGE_CTRL_MEM_SWAP;

#ifdef CONFIG_PAGE_SIZE_4KB

	bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;

#else /* 16kB or larger */

	bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;

#endif



	/*

	 * Hmm...  IRIX sets additional bits in the address which

arch/mips/sgi-ip27/ip27-init.c

+0 −22
Original line number Diff line number Diff line
@@ -161,27 +161,6 @@ cnodeid_t get_compact_nodeid(void) 
	return NASID_TO_COMPACT_NODEID(get_nasid());

}



/* Extracted from the IOC3 meta driver.  FIXME.  */

static inline void ioc3_sio_init(void)

{

	struct ioc3 *ioc3;

	nasid_t nid;

	long loops;



	nid = get_nasid();

	ioc3 = (struct ioc3 *) KL_CONFIG_CH_CONS_INFO(nid)->memory_base;



	ioc3->sscr_a = 0;			/* PIO mode for uarta.  */

	ioc3->sscr_b = 0;			/* PIO mode for uartb.  */

	ioc3->sio_iec = ~0;

	ioc3->sio_ies = (SIO_IR_SA_INT | SIO_IR_SB_INT);



	loops=1000000; while(loops--);

	ioc3->sregs.uarta.iu_fcr = 0;

	ioc3->sregs.uartb.iu_fcr = 0;

	loops=1000000; while(loops--);

}



static inline void ioc3_eth_init(void)

{

	struct ioc3 *ioc3;
@@ -234,7 +213,6 @@ void __init plat_mem_setup(void) 
		panic("Kernel compiled for N mode.");

#endif



	ioc3_sio_init();

	ioc3_eth_init();

	per_cpu_init();