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Commit 95175869 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: delete SMUM_SET_FIELD 



repeated defining in hwmgr.h

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f0f6e375

drivers/gpu/drm/amd/powerplay/inc/smumgr.h

+0 −5
Original line number Diff line number Diff line
@@ -170,11 +170,6 @@ extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr); 
#define SMUM_READ_FIELD(device, reg, field)                           \

		SMUM_GET_FIELD(cgs_read_register(device, mm##reg), reg, field)



#define SMUM_SET_FIELD(value, reg, field, field_val)                  \

		(((value) & ~SMUM_FIELD_MASK(reg, field)) |                    \

		(SMUM_FIELD_MASK(reg, field) & ((field_val) <<                 \

			SMUM_FIELD_SHIFT(reg, field))))



#define SMUM_READ_INDIRECT_FIELD(device, port, reg, field) \

	    SMUM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \

			   reg, field)

drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c

+6 −6
Original line number Diff line number Diff line
@@ -191,17 +191,17 @@ static int cz_load_mec_firmware(struct pp_hwmgr *hwmgr) 
	/* Disable MEC parsing/prefetching */

	tmp = cgs_read_register(hwmgr->device,

					mmCP_MEC_CNTL);

	tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);

	tmp = SMUM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);

	tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1);

	tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1);

	cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp);



	tmp = cgs_read_register(hwmgr->device,

					mmCP_CPC_IC_BASE_CNTL);



	tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

	tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);

	tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

	tmp = SMUM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);

	tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);

	tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ATC, 0);

	tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);

	tmp = PHM_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, MTYPE, 1);

	cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);



	reg_data = smu_lower_32_bits(info.mc_addr) &