Loading arch/ia64/Kconfig +19 −0 Original line number Diff line number Diff line Loading @@ -271,6 +271,25 @@ config SCHED_SMT Intel IA64 chips with MultiThreading at a cost of slightly increased overhead in some places. If unsure say N here. config PERMIT_BSP_REMOVE bool "Support removal of Bootstrap Processor" depends on HOTPLUG_CPU default n ---help--- Say Y here if your platform SAL will support removal of BSP with HOTPLUG_CPU support. config FORCE_CPEI_RETARGET bool "Force assumption that CPEI can be re-targetted" depends on PERMIT_BSP_REMOVE default n ---help--- Say Y if you need to force the assumption that CPEI can be re-targetted to any cpu in the system. This hint is available via ACPI 3.0 specifications. Tiger4 systems are capable of re-directing CPEI to any CPU other than BSP. This option it useful to enable this feature on older BIOS's as well. You can also enable this by using boot command line option force_cpei=1. config PREEMPT bool "Preemptible Kernel" help Loading arch/ia64/configs/tiger_defconfig +2 −0 Original line number Diff line number Diff line Loading @@ -116,6 +116,8 @@ CONFIG_FORCE_MAX_ZONEORDER=17 CONFIG_SMP=y CONFIG_NR_CPUS=4 CONFIG_HOTPLUG_CPU=y CONFIG_PERMIT_BSP_REMOVE=y CONFIG_FORCE_CPEI_RETARGET=y # CONFIG_SCHED_SMT is not set # CONFIG_PREEMPT is not set CONFIG_SELECT_MEMORY_MODEL=y Loading arch/ia64/kernel/acpi.c +10 −4 Original line number Diff line number Diff line Loading @@ -284,18 +284,23 @@ acpi_parse_plat_int_src(acpi_table_entry_header * header, return 0; } #ifdef CONFIG_HOTPLUG_CPU unsigned int can_cpei_retarget(void) { extern int cpe_vector; extern unsigned int force_cpei_retarget; /* * Only if CPEI is supported and the override flag * is present, otherwise return that its re-targettable * if we are in polling mode. */ if (cpe_vector > 0 && !acpi_cpei_override) return 0; if (cpe_vector > 0) { if (acpi_cpei_override || force_cpei_retarget) return 1; else return 0; } return 1; } Loading @@ -315,6 +320,7 @@ void set_cpei_target_cpu(unsigned int cpu) { acpi_cpei_phys_cpuid = cpu_physical_id(cpu); } #endif unsigned int get_cpei_target_cpu(void) { Loading arch/ia64/kernel/entry.S +0 −14 Original line number Diff line number Diff line Loading @@ -1102,9 +1102,6 @@ skip_rbs_switch: st8 [r2]=r8 st8 [r3]=r10 .work_pending: tbit.nz p6,p0=r31,TIF_SIGDELAYED // signal delayed from MCA/INIT/NMI/PMI context? (p6) br.cond.sptk.few .sigdelayed ;; tbit.z p6,p0=r31,TIF_NEED_RESCHED // current_thread_info()->need_resched==0? (p6) br.cond.sptk.few .notify #ifdef CONFIG_PREEMPT Loading @@ -1131,17 +1128,6 @@ skip_rbs_switch: (pLvSys)br.cond.sptk.few .work_pending_syscall_end br.cond.sptk.many .work_processed_kernel // don't re-check // There is a delayed signal that was detected in MCA/INIT/NMI/PMI context where // it could not be delivered. Deliver it now. The signal might be for us and // may set TIF_SIGPENDING, so redrive ia64_leave_* after processing the delayed // signal. .sigdelayed: br.call.sptk.many rp=do_sigdelayed cmp.eq p6,p0=r0,r0 // p6 <- 1, always re-check (pLvSys)br.cond.sptk.few .work_pending_syscall_end br.cond.sptk.many .work_processed_kernel // re-check .work_pending_syscall_end: adds r2=PT(R8)+16,r12 adds r3=PT(R10)+16,r12 Loading arch/ia64/kernel/iosapic.c +6 −0 Original line number Diff line number Diff line Loading @@ -631,6 +631,7 @@ get_target_cpu (unsigned int gsi, int vector) { #ifdef CONFIG_SMP static int cpu = -1; extern int cpe_vector; /* * In case of vector shared by multiple RTEs, all RTEs that Loading @@ -653,6 +654,11 @@ get_target_cpu (unsigned int gsi, int vector) if (!cpu_online(smp_processor_id())) return cpu_physical_id(smp_processor_id()); #ifdef CONFIG_ACPI if (cpe_vector > 0 && vector == IA64_CPEP_VECTOR) return get_cpei_target_cpu(); #endif #ifdef CONFIG_NUMA { int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0; Loading Loading
arch/ia64/Kconfig +19 −0 Original line number Diff line number Diff line Loading @@ -271,6 +271,25 @@ config SCHED_SMT Intel IA64 chips with MultiThreading at a cost of slightly increased overhead in some places. If unsure say N here. config PERMIT_BSP_REMOVE bool "Support removal of Bootstrap Processor" depends on HOTPLUG_CPU default n ---help--- Say Y here if your platform SAL will support removal of BSP with HOTPLUG_CPU support. config FORCE_CPEI_RETARGET bool "Force assumption that CPEI can be re-targetted" depends on PERMIT_BSP_REMOVE default n ---help--- Say Y if you need to force the assumption that CPEI can be re-targetted to any cpu in the system. This hint is available via ACPI 3.0 specifications. Tiger4 systems are capable of re-directing CPEI to any CPU other than BSP. This option it useful to enable this feature on older BIOS's as well. You can also enable this by using boot command line option force_cpei=1. config PREEMPT bool "Preemptible Kernel" help Loading
arch/ia64/configs/tiger_defconfig +2 −0 Original line number Diff line number Diff line Loading @@ -116,6 +116,8 @@ CONFIG_FORCE_MAX_ZONEORDER=17 CONFIG_SMP=y CONFIG_NR_CPUS=4 CONFIG_HOTPLUG_CPU=y CONFIG_PERMIT_BSP_REMOVE=y CONFIG_FORCE_CPEI_RETARGET=y # CONFIG_SCHED_SMT is not set # CONFIG_PREEMPT is not set CONFIG_SELECT_MEMORY_MODEL=y Loading
arch/ia64/kernel/acpi.c +10 −4 Original line number Diff line number Diff line Loading @@ -284,18 +284,23 @@ acpi_parse_plat_int_src(acpi_table_entry_header * header, return 0; } #ifdef CONFIG_HOTPLUG_CPU unsigned int can_cpei_retarget(void) { extern int cpe_vector; extern unsigned int force_cpei_retarget; /* * Only if CPEI is supported and the override flag * is present, otherwise return that its re-targettable * if we are in polling mode. */ if (cpe_vector > 0 && !acpi_cpei_override) return 0; if (cpe_vector > 0) { if (acpi_cpei_override || force_cpei_retarget) return 1; else return 0; } return 1; } Loading @@ -315,6 +320,7 @@ void set_cpei_target_cpu(unsigned int cpu) { acpi_cpei_phys_cpuid = cpu_physical_id(cpu); } #endif unsigned int get_cpei_target_cpu(void) { Loading
arch/ia64/kernel/entry.S +0 −14 Original line number Diff line number Diff line Loading @@ -1102,9 +1102,6 @@ skip_rbs_switch: st8 [r2]=r8 st8 [r3]=r10 .work_pending: tbit.nz p6,p0=r31,TIF_SIGDELAYED // signal delayed from MCA/INIT/NMI/PMI context? (p6) br.cond.sptk.few .sigdelayed ;; tbit.z p6,p0=r31,TIF_NEED_RESCHED // current_thread_info()->need_resched==0? (p6) br.cond.sptk.few .notify #ifdef CONFIG_PREEMPT Loading @@ -1131,17 +1128,6 @@ skip_rbs_switch: (pLvSys)br.cond.sptk.few .work_pending_syscall_end br.cond.sptk.many .work_processed_kernel // don't re-check // There is a delayed signal that was detected in MCA/INIT/NMI/PMI context where // it could not be delivered. Deliver it now. The signal might be for us and // may set TIF_SIGPENDING, so redrive ia64_leave_* after processing the delayed // signal. .sigdelayed: br.call.sptk.many rp=do_sigdelayed cmp.eq p6,p0=r0,r0 // p6 <- 1, always re-check (pLvSys)br.cond.sptk.few .work_pending_syscall_end br.cond.sptk.many .work_processed_kernel // re-check .work_pending_syscall_end: adds r2=PT(R8)+16,r12 adds r3=PT(R10)+16,r12 Loading
arch/ia64/kernel/iosapic.c +6 −0 Original line number Diff line number Diff line Loading @@ -631,6 +631,7 @@ get_target_cpu (unsigned int gsi, int vector) { #ifdef CONFIG_SMP static int cpu = -1; extern int cpe_vector; /* * In case of vector shared by multiple RTEs, all RTEs that Loading @@ -653,6 +654,11 @@ get_target_cpu (unsigned int gsi, int vector) if (!cpu_online(smp_processor_id())) return cpu_physical_id(smp_processor_id()); #ifdef CONFIG_ACPI if (cpe_vector > 0 && vector == IA64_CPEP_VECTOR) return get_cpei_target_cpu(); #endif #ifdef CONFIG_NUMA { int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0; Loading