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Commit 9473c8f4 authored by Vijay Purushothaman's avatar Vijay Purushothaman Committed by Daniel Vetter
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drm/i915: Set aux clk to 100MHz for Valleyview 



Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
This enables the aux transactions in Valleyview.

Signed-off-by: default avatarVijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: default avatarBen Widawsky <benjamin.widawsky@intel.com>
Acked-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3bcedbe5

drivers/gpu/drm/i915/intel_dp.c

+7 −1
Original line number Diff line number Diff line
@@ -286,6 +286,10 @@ intel_hrawclk(struct drm_device *dev) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	uint32_t clkcfg;



	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */

	if (IS_VALLEYVIEW(dev))

		return 200;



	clkcfg = I915_READ(CLKCFG);

	switch (clkcfg & CLKCFG_FSB_MASK) {

	case CLKCFG_FSB_400:
@@ -366,7 +370,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, 
	 * clock divider.

	 */

	if (is_cpu_edp(intel_dp)) {

		if (IS_GEN6(dev) || IS_GEN7(dev))

		if (IS_VALLEYVIEW(dev))

			aux_clock_divider = 100;

		else if (IS_GEN6(dev) || IS_GEN7(dev))

			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */

		else

			aux_clock_divider = 225; /* eDP input clock at 450Mhz */