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Commit 944a3f32 authored by Dave Airlie's avatar Dave Airlie
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Merge branch 'topic-arcpgu-v6' of...

Merge branch 'topic-arcpgu-v6' of https://github.com/foss-for-synopsys-dwc-arc-processors/linux into drm-next

This is DRM driver for ARC PGU - simple bitstreamer used on
Synopsys ARC SDP boards (both AXS101 and AXS103).

* 'topic-arcpgu-v6' of https://github.com/foss-for-synopsys-dwc-arc-processors/linux:
  arc: axs10x - add support of ARC PGU
  MAINTAINERS: Add maintainer for ARC PGU display controller
  drm: Add DT bindings documentation for ARC PGU display controller
  drm: Add support of ARC PGU display controller
parents 33f0fca6 b8c1eca1
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+35 −0
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ARC PGU

This is a display controller found on several development boards produced
by Synopsys. The ARC PGU is an RGB streamer that reads the data from a
framebuffer and sends it to a single digital encoder (usually HDMI).

Required properties:
  - compatible: "snps,arcpgu"
  - reg: Physical base address and length of the controller's registers.
  - clocks: A list of phandle + clock-specifier pairs, one for each
    entry in 'clock-names'.
  - clock-names: A list of clock names. For ARC PGU it should contain:
      - "pxlclk" for the clock feeding the output PLL of the controller.

Required sub-nodes:
  - port: The PGU connection to an encoder chip.

Example:

/ {
	...

	pgu@XXXXXXXX {
		compatible = "snps,arcpgu";
		reg = <0xXXXXXXXX 0x400>;
		clocks = <&clock_node>;
		clock-names = "pxlclk";

		port {
			pgu_output: endpoint {
				remote-endpoint = <&hdmi_enc_input>;
			};
		};
	};
};
+6 −0
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@@ -847,6 +847,12 @@ S: Maintained
F:	drivers/net/arcnet/
F:	include/uapi/linux/if_arcnet.h

ARC PGU DRM DRIVER
M:	Alexey Brodkin <abrodkin@synopsys.com>
S:	Supported
F:	drivers/gpu/drm/arc/
F:	Documentation/devicetree/bindings/display/snps,arcpgu.txt

ARM HDLCD DRM DRIVER
M:	Liviu Dudau <liviu.dudau@arm.com>
S:	Supported
+61 −0
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@@ -34,6 +34,12 @@
				clock-frequency = <50000000>;
				#clock-cells = <0>;
			};

			pguclk: pguclk {
				#clock-cells = <0>;
				compatible = "fixed-clock";
				clock-frequency = <74440000>;
			};
		};

		ethernet@0x18000 {
@@ -155,6 +161,37 @@
			clocks = <&i2cclk>;
			interrupts = <16>;

			adv7511:adv7511@39{
				compatible="adi,adv7511";
				reg = <0x39>;
				interrupts = <23>;
				adi,input-depth = <8>;
				adi,input-colorspace = "rgb";
				adi,input-clock = "1x";
				adi,clock-delay = <0x03>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					/* RGB/YUV input */
					port@0 {
						reg = <0>;
						adv7511_input:endpoint {
						remote-endpoint = <&pgu_output>;
						};
					};

					/* HDMI output */
					port@1 {
						reg = <1>;
						adv7511_output: endpoint {
							remote-endpoint = <&hdmi_connector_in>;
						};
					};
				};
			};

			eeprom@0x54{
				compatible = "24c01";
				reg = <0x54>;
@@ -168,6 +205,16 @@
			};
		};

		hdmi0: connector {
			compatible = "hdmi-connector";
			type = "a";
			port {
				hdmi_connector_in: endpoint {
					remote-endpoint = <&adv7511_output>;
				};
			};
		};

		gpio0:gpio@13000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0x13000 0x1000>;
@@ -229,5 +276,19 @@
				reg = <2>;
			};
		};

		pgu@17000 {
			compatible = "snps,arcpgu";
			reg = <0x17000 0x400>;
			encoder-slave = <&adv7511>;
			clocks = <&pguclk>;
			clock-names = "pxlclk";

			port {
				pgu_output: endpoint {
					remote-endpoint = <&adv7511_input>;
				};
			};
		};
	};
};
+2 −0
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@@ -281,3 +281,5 @@ source "drivers/gpu/drm/imx/Kconfig"
source "drivers/gpu/drm/vc4/Kconfig"

source "drivers/gpu/drm/etnaviv/Kconfig"

source "drivers/gpu/drm/arc/Kconfig"
+1 −0
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@@ -78,3 +78,4 @@ obj-y += panel/
obj-y			+= bridge/
obj-$(CONFIG_DRM_FSL_DCU) += fsl-dcu/
obj-$(CONFIG_DRM_ETNAVIV) += etnaviv/
obj-$(CONFIG_DRM_ARCPGU)+= arc/
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