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Commit 9435373e authored by Rodrigo Vivi's avatar Rodrigo Vivi Committed by Daniel Vetter
Browse files

drm/i915: Report enabled slices on Haswell GT3 



Batchbuffers constructed by userspace can conditionalise their URB
allocations through the use of the MI_SET_PREDICATE command. This
command can read the MI_PREDICATE_RESULT_2 register to see how many
slices are enabled on GT3, and by virtue of the result, scale their
memory allocations to fit enabled memory.

Of course, this only works if the kernel sets the appropriate bit in the
register first.

v2: Better commit subject and message by Chris Wilson.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Credits-to: Yejun Guo <yejun.guo@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 3e33a840

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -1603,6 +1603,8 @@ struct drm_i915_file_private { 
				 ((dev)->pci_device & 0xFF00) == 0x0C00)

				 ((dev)->pci_device & 0xFF00) == 0x0C00)

#define IS_ULT(dev)		(IS_HASWELL(dev) && \

#define IS_ULT(dev)		(IS_HASWELL(dev) && \

				 ((dev)->pci_device & 0xFF00) == 0x0A00)

				 ((dev)->pci_device & 0xFF00) == 0x0A00)

#define IS_HSW_GT3(dev)		(IS_HASWELL(dev) && \

				 ((dev)->pci_device & 0x00F0) == 0x0020)





/*

/*

 * The genX designation typically refers to the render engine, so render

 * The genX designation typically refers to the render engine, so render

drivers/gpu/drm/i915/i915_gem.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -4331,6 +4331,11 @@ i915_gem_init_hw(struct drm_device *dev) 
	if (dev_priv->ellc_size)

	if (dev_priv->ellc_size)

		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));

		I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));





	if (IS_HSW_GT3(dev))

		I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED);

	else

		I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED);



	if (HAS_PCH_NOP(dev)) {

	if (HAS_PCH_NOP(dev)) {

		u32 temp = I915_READ(GEN7_MSG_CTL);

		u32 temp = I915_READ(GEN7_MSG_CTL);

		temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);

		temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);

drivers/gpu/drm/i915/i915_reg.h

+5 −0
Original line number Original line Diff line number Diff line
@@ -264,6 +264,11 @@ 
#define  MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */

#define  MI_SEMAPHORE_SYNC_VVE	    (1<<16) /* VECS wait for VCS  (VEVSYNC) */

#define  MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */

#define  MI_SEMAPHORE_SYNC_RVE	    (2<<16) /* VECS wait for RCS  (VERSYNC) */

#define  MI_SEMAPHORE_SYNC_INVALID  (3<<16)

#define  MI_SEMAPHORE_SYNC_INVALID  (3<<16)



#define MI_PREDICATE_RESULT_2	(0x2214)

#define  LOWER_SLICE_ENABLED	(1<<0)

#define  LOWER_SLICE_DISABLED	(0<<0)



/*

/*

 * 3D instructions used by the kernel

 * 3D instructions used by the kernel

 */

 */