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Commit 93985477 authored by Swathi Sridhar's avatar Swathi Sridhar
Browse files

iommu: arm-smmu: Enable io-coherency in bypass mode 



Support io-coherency on a per context bank basis when
in bypass mode. The SCTLR register provides the ability
to override the shareability and cacheability attributes
when translations are disabled for a particular context
bank i.e in bypass mode. Hence if the client/dev associated
with the context bank is io-coherent, then set the
appropriate SCTLR register attributes to enable io-coherency
If the client/dev is not io-coherent, then force bypass
transactions for them to be non-shareable.

Change-Id: I621bc369fb4206f3a7edf342ea50fcf5a2f869e9
Signed-off-by: default avatarSwathi Sridhar <swatsrid@codeaurora.org>
parent b058dd78

drivers/iommu/arm-smmu-regs.h

+7 −0
Original line number Diff line number Diff line
@@ -192,9 +192,16 @@ enum arm_smmu_s2cr_privcfg { 
#define ARM_SMMU_CB_ATS1PR		0x800

#define ARM_SMMU_CB_ATSR		0x8f0



#define SCTLR_MEM_ATTR_SHIFT		16

#define SCTLR_SHCFG_SHIFT		22

#define SCTLR_RACFG_SHIFT		24

#define SCTLR_WACFG_SHIFT		26

#define SCTLR_SHCFG_MASK		0x3

#define SCTLR_SHCFG_NSH			0x3

#define SCTLR_RACFG_RA			0x2

#define SCTLR_WACFG_WA			0x2

#define SCTLR_MEM_ATTR_OISH_WB_CACHE	0xf

#define SCTLR_MTCFG			(1 << 20)

#define SCTLR_S1_ASIDPNE		(1 << 12)

#define SCTLR_CFCFG			(1 << 7)

#define SCTLR_HUPCF			(1 << 8)

drivers/iommu/arm-smmu.c

+26 −3
Original line number Diff line number Diff line
@@ -431,6 +431,12 @@ static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom) 
	return container_of(dom, struct arm_smmu_domain, domain);

}



static struct arm_smmu_domain*

cb_cfg_to_smmu_domain(struct arm_smmu_cfg *cfg)

{

	return container_of(cfg, struct arm_smmu_domain, cfg);

}



static void parse_driver_options(struct arm_smmu_device *smmu)

{

	int i = 0;
@@ -1554,6 +1560,7 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx, 
	bool stage1;

	struct arm_smmu_cb *cb = &smmu->cbs[idx];

	struct arm_smmu_cfg *cfg = cb->cfg;

	struct arm_smmu_domain *smmu_domain = NULL;

	void __iomem *cb_base, *gr1_base;



	cb_base = ARM_SMMU_CB(smmu, idx);
@@ -1627,7 +1634,23 @@ static void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx, 
	/* SCTLR */

	reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE;



	/* Ensure bypass transactions are Non-shareable */

	/*

	 * Ensure bypass transactions are Non-shareable only for clients

	 * who are not io-coherent.

	 */

	smmu_domain = cb_cfg_to_smmu_domain(cfg);



	/*

	 * Override cacheability, shareability, r/w allocation for

	 * clients who are io-coherent

	 */

	if (of_dma_is_coherent(smmu_domain->dev->of_node)) {



		reg |= SCTLR_RACFG_RA << SCTLR_RACFG_SHIFT;

		reg |= SCTLR_WACFG_WA << SCTLR_WACFG_SHIFT;

		reg |= SCTLR_MTCFG;

		reg |= SCTLR_MEM_ATTR_OISH_WB_CACHE << SCTLR_MEM_ATTR_SHIFT;

	} else

		reg |= SCTLR_SHCFG_NSH << SCTLR_SHCFG_SHIFT;



	if (attributes & (1 << DOMAIN_ATTR_CB_STALL_DISABLE)) {