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Commit 937b81f5 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Adding Refgen vote for DSI Ctrl"

parents ce08f4c0 eb579253

arch/arm64/boot/dts/qcom/kona-sde.dtsi

+30 −0
Original line number Diff line number Diff line
@@ -531,6 +531,7 @@ 
		interrupt-parent = <&mdss_mdp>;

		interrupts = <4 0>;

		vdda-1p2-supply = <&pm8150_l9>;

		refgen-supply = <&refgen>;

		clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,

			<&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,

			<&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
@@ -553,6 +554,20 @@ 
				qcom,supply-disable-load = <0>;

			};

		};



		qcom,core-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,core-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "refgen";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



	mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
@@ -565,6 +580,7 @@ 
		interrupt-parent = <&mdss_mdp>;

		interrupts = <5 0>;

		vdda-1p2-supply = <&pm8150_l9>;

		refgen-supply = <&refgen>;

		clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>,

			<&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,

			<&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
@@ -586,6 +602,20 @@ 
				qcom,supply-disable-load = <0>;

			};

		};



		qcom,core-supply-entries {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,core-supply-entry@0 {

				reg = <0>;

				qcom,supply-name = "refgen";

				qcom,supply-min-voltage = <0>;

				qcom,supply-max-voltage = <0>;

				qcom,supply-enable-load = <0>;

				qcom,supply-disable-load = <0>;

			};

		};

	};



	mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 {