RISC-V: __test_and_op_bit_ord should be strongly ordered



I mis-read the documentation.  After looking at it again the
documentation is actually as clear as it can be, it's just that I didn't
actually read it in order and therefor did the wrong thing.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

parent 3343eb68

arch/riscv/include/asm/bitops.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -67,7 +67,7 @@
	: "memory");		: "memory");

	#define __test_and_op_bit(op, mod, nr, addr) \		#define __test_and_op_bit(op, mod, nr, addr) \
	__test_and_op_bit_ord(op, mod, nr, addr, )		__test_and_op_bit_ord(op, mod, nr, addr, .aqrl)
	#define __op_bit(op, mod, nr, addr) \		#define __op_bit(op, mod, nr, addr) \
	__op_bit_ord(op, mod, nr, addr, )		__op_bit_ord(op, mod, nr, addr, )