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Commit 9346dba5 authored by Mike Frysinger's avatar Mike Frysinger
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Blackfin: standardize DMAC traffic control MMRs & MDMA MMRs 



Use the same naming convention for DMA traffic MMRs (most were legacy
anyways) so we can avoid useless ifdef trees.

Same goes for MDMA names -- this actually allows us to undo a bunch of
ifdef redirects that existed for this purpose alone.

Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent 6c8e75a0

arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h

+4 −10
Original line number Diff line number Diff line
@@ -377,16 +377,10 @@ 




/* DMA Traffic Control Registers													*/

#define bfin_read_DMA_TC_PER()			bfin_read16(DMA_TC_PER)

#define bfin_write_DMA_TC_PER(val)		bfin_write16(DMA_TC_PER, val)

#define bfin_read_DMA_TC_CNT()			bfin_read16(DMA_TC_CNT)

#define bfin_write_DMA_TC_CNT(val)		bfin_write16(DMA_TC_CNT, val)



/* Alternate deprecated register names (below) provided for backwards code compatibility */

#define bfin_read_DMA_TCPER()			bfin_read16(DMA_TCPER)

#define bfin_write_DMA_TCPER(val)		bfin_write16(DMA_TCPER, val)

#define bfin_read_DMA_TCCNT()			bfin_read16(DMA_TCCNT)

#define bfin_write_DMA_TCCNT(val)		bfin_write16(DMA_TCCNT, val)

#define bfin_read_DMAC_TC_PER()			bfin_read16(DMAC_TC_PER)

#define bfin_write_DMAC_TC_PER(val)		bfin_write16(DMAC_TC_PER, val)

#define bfin_read_DMAC_TC_CNT()			bfin_read16(DMAC_TC_CNT)

#define bfin_write_DMAC_TC_CNT(val)		bfin_write16(DMAC_TC_CNT, val)



/* DMA Controller																	*/

#define bfin_read_DMA0_CONFIG()			bfin_read16(DMA0_CONFIG)

arch/blackfin/mach-bf518/include/mach/defBF51x_base.h

+2 −6
Original line number Diff line number Diff line
@@ -215,12 +215,8 @@ 
#define EBIU_SDSTAT			0xFFC00A1C	/* SDRAM Status Register						*/



/* DMA Traffic Control Registers													*/

#define DMA_TC_PER			0xFFC00B0C	/* Traffic Control Periods Register			*/

#define DMA_TC_CNT			0xFFC00B10	/* Traffic Control Current Counts Register	*/



/* Alternate deprecated register names (below) provided for backwards code compatibility */

#define DMA_TCPER			0xFFC00B0C	/* Traffic Control Periods Register			*/

#define DMA_TCCNT			0xFFC00B10	/* Traffic Control Current Counts Register	*/

#define DMAC_TC_PER			0xFFC00B0C	/* Traffic Control Periods Register			*/

#define DMAC_TC_CNT			0xFFC00B10	/* Traffic Control Current Counts Register	*/



/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)															*/

#define DMA0_NEXT_DESC_PTR		0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register		*/

arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h

+4 −10
Original line number Diff line number Diff line
@@ -394,16 +394,10 @@ 




/* DMA Traffic Control Registers													*/

#define bfin_read_DMA_TC_PER()			bfin_read16(DMA_TC_PER)

#define bfin_write_DMA_TC_PER(val)		bfin_write16(DMA_TC_PER, val)

#define bfin_read_DMA_TC_CNT()			bfin_read16(DMA_TC_CNT)

#define bfin_write_DMA_TC_CNT(val)		bfin_write16(DMA_TC_CNT, val)



/* Alternate deprecated register names (below) provided for backwards code compatibility */

#define bfin_read_DMA_TCPER()			bfin_read16(DMA_TCPER)

#define bfin_write_DMA_TCPER(val)		bfin_write16(DMA_TCPER, val)

#define bfin_read_DMA_TCCNT()			bfin_read16(DMA_TCCNT)

#define bfin_write_DMA_TCCNT(val)		bfin_write16(DMA_TCCNT, val)

#define bfin_read_DMAC_TC_PER()			bfin_read16(DMAC_TC_PER)

#define bfin_write_DMAC_TC_PER(val)		bfin_write16(DMAC_TC_PER, val)

#define bfin_read_DMAC_TC_CNT()			bfin_read16(DMAC_TC_CNT)

#define bfin_write_DMAC_TC_CNT(val)		bfin_write16(DMAC_TC_CNT, val)



/* DMA Controller																	*/

#define bfin_read_DMA0_CONFIG()			bfin_read16(DMA0_CONFIG)

arch/blackfin/mach-bf527/include/mach/defBF52x_base.h

+2 −6
Original line number Diff line number Diff line
@@ -215,12 +215,8 @@ 




/* DMA Traffic Control Registers													*/

#define DMA_TC_PER			0xFFC00B0C	/* Traffic Control Periods Register			*/

#define DMA_TC_CNT			0xFFC00B10	/* Traffic Control Current Counts Register	*/



/* Alternate deprecated register names (below) provided for backwards code compatibility */

#define DMA_TCPER			0xFFC00B0C	/* Traffic Control Periods Register			*/

#define DMA_TCCNT			0xFFC00B10	/* Traffic Control Current Counts Register	*/

#define DMAC_TC_PER			0xFFC00B0C	/* Traffic Control Periods Register			*/

#define DMAC_TC_CNT			0xFFC00B10	/* Traffic Control Current Counts Register	*/



/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)															*/

#define DMA0_NEXT_DESC_PTR		0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register		*/

arch/blackfin/mach-bf533/include/mach/cdefBF532.h

+4 −10
Original line number Diff line number Diff line
@@ -66,16 +66,10 @@ 
#define bfin_write_RTC_PREN(val)             bfin_write16(RTC_PREN,val)



/* DMA Traffic controls */

#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)

#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)

#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)

#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)



/* Alternate deprecated register names (below) provided for backwards code compatibility */

#define bfin_read_DMA_TC_PER()               bfin_read16(DMA_TC_PER)

#define bfin_write_DMA_TC_PER(val)           bfin_write16(DMA_TC_PER,val)

#define bfin_read_DMA_TC_CNT()               bfin_read16(DMA_TC_CNT)

#define bfin_write_DMA_TC_CNT(val)           bfin_write16(DMA_TC_CNT,val)

#define bfin_read_DMAC_TC_PER()              bfin_read16(DMAC_TC_PER)

#define bfin_write_DMAC_TC_PER(val)          bfin_write16(DMAC_TC_PER,val)

#define bfin_read_DMAC_TC_CNT()              bfin_read16(DMAC_TC_CNT)

#define bfin_write_DMAC_TC_CNT(val)          bfin_write16(DMAC_TC_CNT,val)



/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */

#define bfin_read_FIO_DIR()                  bfin_read16(FIO_DIR)