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Commit 932f8c77 authored by David S. Miller's avatar David S. Miller
Browse files

Merge tag 'mlx5-fixes-2017-12-19' of git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux 



Saeed Mahameed says:

===================
Mellanox, mlx5 fixes 2017-12-19

The follwoing series includes some fixes for mlx5 core and etherent
driver.

Please pull and let me know if there is any problem.

This series doesn't introduce any conflict with the ongoing mlx5 for-next
submission.

For -stable:

kernels >= v4.7.y
    ("net/mlx5e: Fix possible deadlock of VXLAN lock")
    ("net/mlx5e: Add refcount to VXLAN structure")
    ("net/mlx5e: Prevent possible races in VXLAN control flow")
    ("net/mlx5e: Fix features check of IPv6 traffic")

kernels >= v4.9.y
    ("net/mlx5: Fix error flow in CREATE_QP command")
    ("net/mlx5: Fix rate limit packet pacing naming and struct")

kernels >= v4.13.y
    ("net/mlx5: FPGA, return -EINVAL if size is zero")

kernels >= v4.14.y
    ("Revert "mlx5: move affinity hints assignments to generic code")

All above patches apply and compile with no issues on corresponding -stable.
===================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents a8fcefe8 a2fba188

drivers/net/ethernet/mellanox/mlx5/core/cmd.c

+2 −2
Original line number Diff line number Diff line
@@ -362,7 +362,7 @@ static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op, 
	case MLX5_CMD_OP_QUERY_VPORT_COUNTER:

	case MLX5_CMD_OP_ALLOC_Q_COUNTER:

	case MLX5_CMD_OP_QUERY_Q_COUNTER:

	case MLX5_CMD_OP_SET_RATE_LIMIT:

	case MLX5_CMD_OP_SET_PP_RATE_LIMIT:

	case MLX5_CMD_OP_QUERY_RATE_LIMIT:

	case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:

	case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
@@ -505,7 +505,7 @@ const char *mlx5_command_str(int command) 
	MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);

	MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);

	MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);

	MLX5_COMMAND_STR_CASE(SET_RATE_LIMIT);

	MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);

	MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);

	MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);

	MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);

drivers/net/ethernet/mellanox/mlx5/core/en.h

+7 −2
Original line number Diff line number Diff line
@@ -82,6 +82,9 @@ 
	max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)

#define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev)       MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)

#define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)

#define MLX5E_MPWQE_STRIDE_SZ(mdev, cqe_cmprs) \

	(cqe_cmprs ? MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) : \

	MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev))



#define MLX5_MPWRQ_LOG_WQE_SZ			18

#define MLX5_MPWRQ_WQE_PAGE_ORDER  (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
@@ -590,6 +593,7 @@ struct mlx5e_channel { 
	struct mlx5_core_dev      *mdev;

	struct hwtstamp_config    *tstamp;

	int                        ix;

	int                        cpu;

};



struct mlx5e_channels {
@@ -935,8 +939,9 @@ void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, 
				 u8 cq_period_mode);

void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,

				 u8 cq_period_mode);

void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,

			      struct mlx5e_params *params, u8 rq_type);

void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,

			       struct mlx5e_params *params,

			       u8 rq_type);



static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev)

{

drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c

+7 −3
Original line number Diff line number Diff line
@@ -274,6 +274,7 @@ int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets) 
static int mlx5e_dbcnl_validate_ets(struct net_device *netdev,

				    struct ieee_ets *ets)

{

	bool have_ets_tc = false;

	int bw_sum = 0;

	int i;
@@ -288,11 +289,14 @@ static int mlx5e_dbcnl_validate_ets(struct net_device *netdev, 
	}



	/* Validate Bandwidth Sum */

	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)

		if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS)

	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {

		if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) {

			have_ets_tc = true;

			bw_sum += ets->tc_tx_bw[i];

		}

	}



	if (bw_sum != 0 && bw_sum != 100) {

	if (have_ets_tc && bw_sum != 100) {

		netdev_err(netdev,

			   "Failed to validate ETS: BW sum is illegal\n");

		return -EINVAL;

drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c

+8 −2
Original line number Diff line number Diff line
@@ -1523,8 +1523,10 @@ int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val 
	new_channels.params = priv->channels.params;

	MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);



	mlx5e_set_rq_type_params(priv->mdev, &new_channels.params,

				 new_channels.params.rq_wq_type);

	new_channels.params.mpwqe_log_stride_sz =

		MLX5E_MPWQE_STRIDE_SZ(priv->mdev, new_val);

	new_channels.params.mpwqe_log_num_strides =

		MLX5_MPWRQ_LOG_WQE_SZ - new_channels.params.mpwqe_log_stride_sz;



	if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {

		priv->channels.params = new_channels.params;
@@ -1536,6 +1538,10 @@ int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val 
		return err;



	mlx5e_switch_priv_channels(priv, &new_channels, NULL);

	mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",

		  MLX5E_GET_PFLAG(&priv->channels.params,

				  MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");



	return 0;

}

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

+31 −32
Original line number Diff line number Diff line
@@ -71,11 +71,6 @@ struct mlx5e_channel_param { 
	struct mlx5e_cq_param      icosq_cq;

};



static int mlx5e_get_node(struct mlx5e_priv *priv, int ix)

{

	return pci_irq_get_node(priv->mdev->pdev, MLX5_EQ_VEC_COMP_BASE + ix);

}



static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)

{

	return MLX5_CAP_GEN(mdev, striding_rq) &&
@@ -83,7 +78,7 @@ static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev) 
		MLX5_CAP_ETH(mdev, reg_umr_sq);

}



void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,

void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,

			       struct mlx5e_params *params, u8 rq_type)

{

	params->rq_wq_type = rq_type;
@@ -93,10 +88,8 @@ void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev, 
		params->log_rq_size = is_kdump_kernel() ?

			MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :

			MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;

		params->mpwqe_log_stride_sz =

			MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?

			MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :

			MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);

		params->mpwqe_log_stride_sz = MLX5E_MPWQE_STRIDE_SZ(mdev,

			MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));

		params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -

			params->mpwqe_log_stride_sz;

		break;
@@ -120,13 +113,14 @@ void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev, 
		       MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));

}



static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)

static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev,

				struct mlx5e_params *params)

{

	u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&

		    !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?

		    MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :

		    MLX5_WQ_TYPE_LINKED_LIST;

	mlx5e_set_rq_type_params(mdev, params, rq_type);

	mlx5e_init_rq_type_params(mdev, params, rq_type);

}



static void mlx5e_update_carrier(struct mlx5e_priv *priv)
@@ -444,17 +438,16 @@ static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, 
	int wq_sz = mlx5_wq_ll_get_size(&rq->wq);

	int mtt_sz = mlx5e_get_wqe_mtt_sz();

	int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;

	int node = mlx5e_get_node(c->priv, c->ix);

	int i;



	rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),

					GFP_KERNEL, node);

				      GFP_KERNEL, cpu_to_node(c->cpu));

	if (!rq->mpwqe.info)

		goto err_out;



	/* We allocate more than mtt_sz as we will align the pointer */

	rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz,

					GFP_KERNEL, node);

	rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,

					cpu_to_node(c->cpu));

	if (unlikely(!rq->mpwqe.mtt_no_align))

		goto err_free_wqe_info;
@@ -562,7 +555,7 @@ static int mlx5e_alloc_rq(struct mlx5e_channel *c, 
	int err;

	int i;



	rqp->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);

	rqp->wq.db_numa_node = cpu_to_node(c->cpu);



	err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,

				&rq->wq_ctrl);
@@ -629,8 +622,7 @@ static int mlx5e_alloc_rq(struct mlx5e_channel *c, 
	default: /* MLX5_WQ_TYPE_LINKED_LIST */

		rq->wqe.frag_info =

			kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),

				     GFP_KERNEL,

				     mlx5e_get_node(c->priv, c->ix));

				     GFP_KERNEL, cpu_to_node(c->cpu));

		if (!rq->wqe.frag_info) {

			err = -ENOMEM;

			goto err_rq_wq_destroy;
@@ -1000,13 +992,13 @@ static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c, 
	sq->uar_map   = mdev->mlx5e_res.bfreg.map;

	sq->min_inline_mode = params->tx_min_inline_mode;



	param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);

	param->wq.db_numa_node = cpu_to_node(c->cpu);

	err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);

	if (err)

		return err;

	sq->wq.db = &sq->wq.db[MLX5_SND_DBR];



	err = mlx5e_alloc_xdpsq_db(sq, mlx5e_get_node(c->priv, c->ix));

	err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));

	if (err)

		goto err_sq_wq_destroy;
@@ -1053,13 +1045,13 @@ static int mlx5e_alloc_icosq(struct mlx5e_channel *c, 
	sq->channel   = c;

	sq->uar_map   = mdev->mlx5e_res.bfreg.map;



	param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);

	param->wq.db_numa_node = cpu_to_node(c->cpu);

	err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);

	if (err)

		return err;

	sq->wq.db = &sq->wq.db[MLX5_SND_DBR];



	err = mlx5e_alloc_icosq_db(sq, mlx5e_get_node(c->priv, c->ix));

	err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));

	if (err)

		goto err_sq_wq_destroy;
@@ -1126,13 +1118,13 @@ static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, 
	if (MLX5_IPSEC_DEV(c->priv->mdev))

		set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);



	param->wq.db_numa_node = mlx5e_get_node(c->priv, c->ix);

	param->wq.db_numa_node = cpu_to_node(c->cpu);

	err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);

	if (err)

		return err;

	sq->wq.db    = &sq->wq.db[MLX5_SND_DBR];



	err = mlx5e_alloc_txqsq_db(sq, mlx5e_get_node(c->priv, c->ix));

	err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));

	if (err)

		goto err_sq_wq_destroy;
@@ -1504,8 +1496,8 @@ static int mlx5e_alloc_cq(struct mlx5e_channel *c, 
	struct mlx5_core_dev *mdev = c->priv->mdev;

	int err;



	param->wq.buf_numa_node = mlx5e_get_node(c->priv, c->ix);

	param->wq.db_numa_node  = mlx5e_get_node(c->priv, c->ix);

	param->wq.buf_numa_node = cpu_to_node(c->cpu);

	param->wq.db_numa_node  = cpu_to_node(c->cpu);

	param->eq_ix   = c->ix;



	err = mlx5e_alloc_cq_common(mdev, param, cq);
@@ -1604,6 +1596,11 @@ static void mlx5e_close_cq(struct mlx5e_cq *cq) 
	mlx5e_free_cq(cq);

}



static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)

{

	return cpumask_first(priv->mdev->priv.irq_info[ix].mask);

}



static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,

			     struct mlx5e_params *params,

			     struct mlx5e_channel_param *cparam)
@@ -1752,12 +1749,13 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, 
{

	struct mlx5e_cq_moder icocq_moder = {0, 0};

	struct net_device *netdev = priv->netdev;

	int cpu = mlx5e_get_cpu(priv, ix);

	struct mlx5e_channel *c;

	unsigned int irq;

	int err;

	int eqn;



	c = kzalloc_node(sizeof(*c), GFP_KERNEL, mlx5e_get_node(priv, ix));

	c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));

	if (!c)

		return -ENOMEM;
@@ -1765,6 +1763,7 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, 
	c->mdev     = priv->mdev;

	c->tstamp   = &priv->tstamp;

	c->ix       = ix;

	c->cpu      = cpu;

	c->pdev     = &priv->mdev->pdev->dev;

	c->netdev   = priv->netdev;

	c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
@@ -1853,8 +1852,7 @@ static void mlx5e_activate_channel(struct mlx5e_channel *c) 
	for (tc = 0; tc < c->num_tc; tc++)

		mlx5e_activate_txqsq(&c->sq[tc]);

	mlx5e_activate_rq(&c->rq);

	netif_set_xps_queue(c->netdev,

		mlx5_get_vector_affinity(c->priv->mdev, c->ix), c->ix);

	netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);

}



static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
@@ -3679,6 +3677,7 @@ static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv, 
						     struct sk_buff *skb,

						     netdev_features_t features)

{

	unsigned int offset = 0;

	struct udphdr *udph;

	u8 proto;

	u16 port;
@@ -3688,7 +3687,7 @@ static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv, 
		proto = ip_hdr(skb)->protocol;

		break;

	case htons(ETH_P_IPV6):

		proto = ipv6_hdr(skb)->nexthdr;

		proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);

		break;

	default:

		goto out;