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Commit 92e2d508 authored by Ingo Molnar's avatar Ingo Molnar
Browse files

Merge branch 'x86/urgent' into core/percpu 

Conflicts:
	arch/x86/kernel/acpi/boot.c
parents 5d96218b d315760f

Documentation/kernel-parameters.txt

+2 −0
Original line number Diff line number Diff line
@@ -937,6 +937,8 @@ and is between 256 and 4096 characters. It is defined in the file 




	intel_iommu=	[DMAR] Intel IOMMU driver (DMAR) option

		on

			Enable intel iommu driver.

		off

			Disable intel iommu driver.

		igfx_off [Default Off]

arch/x86/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -1806,6 +1806,17 @@ config DMAR 
	  and include PCI device scope covered by these DMA

	  remapping devices.



config DMAR_DEFAULT_ON

	def_bool n

	prompt "Enable DMA Remapping Devices by default"

	depends on DMAR

	help

	  Selecting this option will enable a DMAR device at boot time if

	  one is found. If this option is not selected, DMAR support can

	  be enabled by passing intel_iommu=on to the kernel. It is

	  recommended you say N here while the DMAR code remains

	  experimental.



config DMAR_GFX_WA

	def_bool y

	prompt "Support for Graphics workaround"

arch/x86/Kconfig.cpu

+15 −13
Original line number Diff line number Diff line
@@ -167,9 +167,9 @@ config MK7 
config MK8

	bool "Opteron/Athlon64/Hammer/K8"

	help

	  Select this for an AMD Opteron or Athlon64 Hammer-family processor.  Enables

	  use of some extended instructions, and passes appropriate optimization

	  flags to GCC.

	  Select this for an AMD Opteron or Athlon64 Hammer-family processor.

	  Enables use of some extended instructions, and passes appropriate

	  optimization flags to GCC.



config MCRUSOE

	bool "Crusoe"
@@ -256,9 +256,11 @@ config MPSC 
config MCORE2

	bool "Core 2/newer Xeon"

	help

	  Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and 53xx)

	  CPUs. You can distinguish newer from older Xeons by the CPU family

	  in /proc/cpuinfo. Newer ones have 6 and older ones 15 (not a typo)



	  Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and

	  53xx) CPUs. You can distinguish newer from older Xeons by the CPU

	  family in /proc/cpuinfo. Newer ones have 6 and older ones 15

	  (not a typo)



config GENERIC_CPU

	bool "Generic-x86-64"
@@ -318,14 +320,14 @@ config X86_PPRO_FENCE 
	bool "PentiumPro memory ordering errata workaround"

	depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1

	help

	  Old PentiumPro multiprocessor systems had errata that could cause memory

	  operations to violate the x86 ordering standard in rare cases. Enabling this

	  option will attempt to work around some (but not all) occurances of

	  this problem, at the cost of much heavier spinlock and memory barrier

	  operations.

	  Old PentiumPro multiprocessor systems had errata that could cause

	  memory operations to violate the x86 ordering standard in rare cases.

	  Enabling this option will attempt to work around some (but not all)

	  occurances of this problem, at the cost of much heavier spinlock and

	  memory barrier operations.



	  If unsure, say n here. Even distro kernels should think twice before enabling

	  this: there are few systems, and an unlikely bug.

	  If unsure, say n here. Even distro kernels should think twice before

	  enabling this: there are few systems, and an unlikely bug.



config X86_F00F_BUG

	def_bool y

arch/x86/include/asm/a.out-core.h

+1 −3
Original line number Diff line number Diff line
@@ -23,8 +23,6 @@ 
 */

static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)

{

	u16 gs;



/* changed the size calculations - should hopefully work better. lbt */

	dump->magic = CMAGIC;

	dump->start_code = 0;
@@ -57,7 +55,7 @@ static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) 
	dump->regs.ds = (u16)regs->ds;

	dump->regs.es = (u16)regs->es;

	dump->regs.fs = (u16)regs->fs;

	savesegment(gs, gs);

	savesegment(gs, dump->regs.gs);

	dump->regs.orig_ax = regs->orig_ax;

	dump->regs.ip = regs->ip;

	dump->regs.cs = (u16)regs->cs;

arch/x86/include/asm/cpufeature.h

+1 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ 
#define X86_FEATURE_XTOPOLOGY	(3*32+22) /* cpu topology enum extensions */

#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */

#define X86_FEATURE_NONSTOP_TSC	(3*32+24) /* TSC does not stop in C states */

#define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */



/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */

#define X86_FEATURE_XMM3	(4*32+ 0) /* "pni" SSE-3 */