[ARM] 2887/1: OMAP 2/4: Update files common to omap1 and omap2, take 2 (92105bb7) · Commits · e / devices / android_kernel_fairphone_FP4

arch/arm/plat-omap/Kconfig

+16 −0

Original line number	Original line	Diff line number	Diff line
	@@ -91,6 +91,13 @@ config OMAP_32K_TIMER_HZ
	Kernel internal timer frequency should be a divisor of 32768,		Kernel internal timer frequency should be a divisor of 32768,
	such as 64 or 128.		such as 64 or 128.

			config OMAP_DM_TIMER
			bool "Use dual-mode timer"
			default n
			depends on ARCH_OMAP16XX
			help
			Select this option if you want to use OMAP Dual-Mode timers.

	choice		choice
	prompt "Low-level debug console UART"		prompt "Low-level debug console UART"
	depends on ARCH_OMAP		depends on ARCH_OMAP
	@@ -107,6 +114,15 @@ config OMAP_LL_DEBUG_UART3

	endchoice		endchoice

			config OMAP_SERIAL_WAKE
			bool "Enable wake-up events for serial ports"
			depends OMAP_MUX
			default y
			help
			Select this option if you want to have your system wake up
			to data on the serial RX line. This allows you to wake the
			system from serial console.

	endmenu		endmenu

	endif		endif

arch/arm/plat-omap/Makefile

+3 −1

Original line number	Original line	Diff line number	Diff line
	@@ -3,7 +3,7 @@
	#		#

	# Common support		# Common support
	obj-y := common.o dma.o clock.o mux.o gpio.o mcbsp.o usb.o		obj-y := common.o sram.o sram-fn.o clock.o dma.o mux.o gpio.o mcbsp.o usb.o
	obj-m :=		obj-m :=
	obj-n :=		obj-n :=
	obj- :=		obj- :=
	@@ -15,3 +15,5 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
	obj-$(CONFIG_PM) += pm.o sleep.o		obj-$(CONFIG_PM) += pm.o sleep.o

	obj-$(CONFIG_CPU_FREQ) += cpu-omap.o		obj-$(CONFIG_CPU_FREQ) += cpu-omap.o
			obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o

arch/arm/plat-omap/clock.c

+27 −12

Original line number	Original line	Diff line number	Diff line
	@@ -21,6 +21,7 @@
	#include <asm/arch/usb.h>		#include <asm/arch/usb.h>

	#include "clock.h"		#include "clock.h"
			#include "sram.h"

	static LIST_HEAD(clocks);		static LIST_HEAD(clocks);
	static DECLARE_MUTEX(clocks_sem);		static DECLARE_MUTEX(clocks_sem);
	@@ -141,7 +142,7 @@ static struct clk arm_ck = {
	static struct clk armper_ck = {		static struct clk armper_ck = {
	.name = "armper_ck",		.name = "armper_ck",
	.parent = &ck_dpll1,		.parent = &ck_dpll1,
	.flags = CLOCK_IN_OMAP730 \| CLOCK_IN_OMAP1510 \| CLOCK_IN_OMAP16XX \|		.flags = CLOCK_IN_OMAP1510 \| CLOCK_IN_OMAP16XX \|
	RATE_CKCTL,		RATE_CKCTL,
	.enable_reg = ARM_IDLECT2,		.enable_reg = ARM_IDLECT2,
	.enable_bit = EN_PERCK,		.enable_bit = EN_PERCK,
	@@ -385,7 +386,8 @@ static struct clk uart2_ck = {
	.name = "uart2_ck",		.name = "uart2_ck",
	/* Direct from ULPD, no parent */		/* Direct from ULPD, no parent */
	.rate = 12000000,		.rate = 12000000,
	.flags = CLOCK_IN_OMAP1510 \| CLOCK_IN_OMAP16XX \| ENABLE_REG_32BIT,		.flags = CLOCK_IN_OMAP1510 \| CLOCK_IN_OMAP16XX \| ENABLE_REG_32BIT \|
			ALWAYS_ENABLED,
	.enable_reg = MOD_CONF_CTRL_0,		.enable_reg = MOD_CONF_CTRL_0,
	.enable_bit = 30, /* Chooses between 12MHz and 48MHz */		.enable_bit = 30, /* Chooses between 12MHz and 48MHz */
	.set_rate = &set_uart_rate,		.set_rate = &set_uart_rate,
	@@ -443,6 +445,15 @@ static struct clk usb_hhc_ck16xx = {
	.enable_bit = 8 /* UHOST_EN */,		.enable_bit = 8 /* UHOST_EN */,
	};		};

			static struct clk usb_dc_ck = {
			.name = "usb_dc_ck",
			/* Direct from ULPD, no parent */
			.rate = 48000000,
			.flags = CLOCK_IN_OMAP16XX \| RATE_FIXED,
			.enable_reg = SOFT_REQ_REG,
			.enable_bit = 4,
			};

	static struct clk mclk_1510 = {		static struct clk mclk_1510 = {
	.name = "mclk",		.name = "mclk",
	/* Direct from ULPD, no parent. May be enabled by ext hardware. */		/* Direct from ULPD, no parent. May be enabled by ext hardware. */
	@@ -552,6 +563,7 @@ static struct clk * onchip_clks[] = {
	&uart3_16xx,		&uart3_16xx,
	&usb_clko,		&usb_clko,
	&usb_hhc_ck1510, &usb_hhc_ck16xx,		&usb_hhc_ck1510, &usb_hhc_ck16xx,
			&usb_dc_ck,
	&mclk_1510, &mclk_16xx,		&mclk_1510, &mclk_16xx,
	&bclk_1510, &bclk_16xx,		&bclk_1510, &bclk_16xx,
	&mmc1_ck,		&mmc1_ck,
	@@ -946,14 +958,13 @@ static int select_table_rate(struct clk * clk, unsigned long rate)
	if (!ptr->rate)		if (!ptr->rate)
	return -EINVAL;		return -EINVAL;

	if (!ptr->rate)		/*
	return -EINVAL;		* In most cases we should not need to reprogram DPLL.
			* Reprogramming the DPLL is tricky, it must be done from SRAM.
			*/
			omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);

	if (unlikely(ck_dpll1.rate == 0)) {
	omap_writew(ptr->dpllctl_val, DPLL_CTL);
	ck_dpll1.rate = ptr->pll_rate;		ck_dpll1.rate = ptr->pll_rate;
	}
	omap_writew(ptr->ckctl_val, ARM_CKCTL);
	propagate_rate(&ck_dpll1);		propagate_rate(&ck_dpll1);
	return 0;		return 0;
	}		}
	@@ -1224,9 +1235,11 @@ int __init clk_init(void)
	#endif		#endif
	/* Cache rates for clocks connected to ck_ref (not dpll1) */		/* Cache rates for clocks connected to ck_ref (not dpll1) */
	propagate_rate(&ck_ref);		propagate_rate(&ck_ref);
	printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld/%ld MHz\n",		printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
			"%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
	ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,		ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
	ck_dpll1.rate, arm_ck.rate);		ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
			arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);

	#ifdef CONFIG_MACH_OMAP_PERSEUS2		#ifdef CONFIG_MACH_OMAP_PERSEUS2
	/* Select slicer output as OMAP input clock */		/* Select slicer output as OMAP input clock */
	@@ -1271,7 +1284,9 @@ static int __init omap_late_clk_reset(void)
	struct clk *p;		struct clk *p;
	__u32 regval32;		__u32 regval32;

	omap_writew(0, SOFT_REQ_REG);		/* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
			regval32 = omap_readw(SOFT_REQ_REG) & (1 << 4);
			omap_writew(regval32, SOFT_REQ_REG);
	omap_writew(0, SOFT_REQ_REG2);		omap_writew(0, SOFT_REQ_REG2);

	list_for_each_entry(p, &clocks, node) {		list_for_each_entry(p, &clocks, node) {

arch/arm/plat-omap/common.c

+4 −3

Original line number	Original line	Diff line number	Diff line
	@@ -26,6 +26,7 @@
	#include <asm/hardware/clock.h>		#include <asm/hardware/clock.h>
	#include <asm/io.h>		#include <asm/io.h>
	#include <asm/mach-types.h>		#include <asm/mach-types.h>
			#include <asm/setup.h>

	#include <asm/arch/board.h>		#include <asm/arch/board.h>
	#include <asm/arch/mux.h>		#include <asm/arch/mux.h>
	@@ -35,11 +36,11 @@

	#define NO_LENGTH_CHECK 0xffffffff		#define NO_LENGTH_CHECK 0xffffffff

	extern int omap_bootloader_tag_len;		unsigned char omap_bootloader_tag[512];
	extern u8 omap_bootloader_tag[];		int omap_bootloader_tag_len;

	struct omap_board_config_kernel *omap_board_config;		struct omap_board_config_kernel *omap_board_config;
	int omap_board_config_size = 0;		int omap_board_config_size;

	static const void get_config(u16 tag, size_t len, int skip, size_t len_out)		static const void get_config(u16 tag, size_t len, int skip, size_t len_out)
	{		{

arch/arm/plat-omap/dma.c

+18 −7

Original line number	Original line	Diff line number	Diff line
	@@ -425,7 +425,7 @@ static int dma_handle_ch(int ch)
	dma_chan[ch + 6].saved_csr = csr >> 7;		dma_chan[ch + 6].saved_csr = csr >> 7;
	csr &= 0x7f;		csr &= 0x7f;
	}		}
	if (!csr)		if ((csr & 0x3f) == 0)
	return 0;		return 0;
	if (unlikely(dma_chan[ch].dev_id == -1)) {		if (unlikely(dma_chan[ch].dev_id == -1)) {
	printk(KERN_WARNING "Spurious interrupt from DMA channel %d (CSR %04x)\n",		printk(KERN_WARNING "Spurious interrupt from DMA channel %d (CSR %04x)\n",
	@@ -890,11 +890,11 @@ void omap_enable_lcd_dma(void)
	w \|= 1 << 8;		w \|= 1 << 8;
	omap_writew(w, OMAP1610_DMA_LCD_CTRL);		omap_writew(w, OMAP1610_DMA_LCD_CTRL);

			lcd_dma.active = 1;

	w = omap_readw(OMAP1610_DMA_LCD_CCR);		w = omap_readw(OMAP1610_DMA_LCD_CCR);
	w \|= 1 << 7;		w \|= 1 << 7;
	omap_writew(w, OMAP1610_DMA_LCD_CCR);		omap_writew(w, OMAP1610_DMA_LCD_CCR);

	lcd_dma.active = 1;
	}		}

	void omap_setup_lcd_dma(void)		void omap_setup_lcd_dma(void)
	@@ -965,8 +965,8 @@ void omap_clear_dma(int lch)
	*/		*/
	dma_addr_t omap_get_dma_src_pos(int lch)		dma_addr_t omap_get_dma_src_pos(int lch)
	{		{
	return (dma_addr_t) (OMAP_DMA_CSSA_L(lch) \|		return (dma_addr_t) (omap_readw(OMAP_DMA_CSSA_L(lch)) \|
	(OMAP_DMA_CSSA_U(lch) << 16));		(omap_readw(OMAP_DMA_CSSA_U(lch)) << 16));
	}		}

	/*		/*
	@@ -979,8 +979,18 @@ dma_addr_t omap_get_dma_src_pos(int lch)
	*/		*/
	dma_addr_t omap_get_dma_dst_pos(int lch)		dma_addr_t omap_get_dma_dst_pos(int lch)
	{		{
	return (dma_addr_t) (OMAP_DMA_CDSA_L(lch) \|		return (dma_addr_t) (omap_readw(OMAP_DMA_CDSA_L(lch)) \|
	(OMAP_DMA_CDSA_U(lch) << 16));		(omap_readw(OMAP_DMA_CDSA_U(lch)) << 16));
			}

			/*
			* Returns current source transfer counting for the given DMA channel.
			* Can be used to monitor the progress of a transfer inside a block.
			* It must be called with disabled interrupts.
			*/
			int omap_get_dma_src_addr_counter(int lch)
			{
			return (dma_addr_t) omap_readw(OMAP_DMA_CSAC(lch));
	}		}

	int omap_dma_running(void)		int omap_dma_running(void)
	@@ -1076,6 +1086,7 @@ arch_initcall(omap_init_dma);

	EXPORT_SYMBOL(omap_get_dma_src_pos);		EXPORT_SYMBOL(omap_get_dma_src_pos);
	EXPORT_SYMBOL(omap_get_dma_dst_pos);		EXPORT_SYMBOL(omap_get_dma_dst_pos);
			EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
	EXPORT_SYMBOL(omap_clear_dma);		EXPORT_SYMBOL(omap_clear_dma);
	EXPORT_SYMBOL(omap_set_dma_priority);		EXPORT_SYMBOL(omap_set_dma_priority);
	EXPORT_SYMBOL(omap_request_dma);		EXPORT_SYMBOL(omap_request_dma);