Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 91e66700 authored by Tuomas Tynkkynen's avatar Tuomas Tynkkynen Committed by Felipe Balbi
Browse files

Documentation: New DT parameters for tegra30-usb-phy



Document the new device tree parameters for Tegra30 USB PHY.

Signed-off-by: default avatarTuomas Tynkkynen <ttynkkynen@nvidia.com>
Tested-by: default avatarStephen Warren <swarren@nvidia.com>
Reviewed-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent 3e635202
Loading
Loading
Loading
Loading
+12 −3
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ Tegra SOC USB PHY
The device node for Tegra SOC USB PHY:

Required properties :
 - compatible : Should be "nvidia,tegra20-usb-phy".
 - compatible : Should be "nvidia,tegra<chip>-usb-phy".
 - reg : Defines the following set of registers, in the order listed:
   - The PHY's own register set.
     Always present.
@@ -24,17 +24,26 @@ Required properties :
Required properties for phy_type == ulpi:
  - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.

Required PHY timing params for utmi phy:
Required PHY timing params for utmi phy, for all chips:
  - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before
    start of sync launches RxActive
  - nvidia,elastic-limit : Variable FIFO Depth of elastic input store
  - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait
    before declare IDLE.
  - nvidia,term-range-adj : Range adjusment on terminations
  - nvidia,xcvr-setup : HS driver output control
  - Either one of the following for HS driver output control:
    - nvidia,xcvr-setup : integer, uses the provided value.
    - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read
      from the on-chip fuses
    If both are provided, nvidia,xcvr-setup-use-fuses takes precedence.
  - nvidia,xcvr-lsfslew : LS falling slew rate control.
  - nvidia,xcvr-lsrslew :  LS rising slew rate control.

Required PHY timing params for utmi phy, only on Tegra30 and above:
  - nvidia,xcvr-hsslew : HS slew rate control.
  - nvidia,hssquelch-level : HS squelch detector level.
  - nvidia,hsdiscon-level : HS disconnect detector level.

Optional properties:
  - nvidia,has-legacy-mode : boolean indicates whether this controller can
    operate in legacy mode (as APX 2500 / 2600). In legacy mode some