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Commit 9134c6d7 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
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drm/amdgpu: Add gfx_off support in smu through pp_set_powergating_by_smu



we can take gfx off feature as gfx power gate. gfx off feature is also
controled by smu. so add gfx_off support in pp_set_powergating_by_smu.

Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a214e1c4
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+7 −12
Original line number Diff line number Diff line
@@ -1730,16 +1730,11 @@ static int amdgpu_device_ip_late_set_cg_state(struct amdgpu_device *adev)
		}
	}

	if (adev->powerplay.pp_feature & PP_GFXOFF_MASK) {
	if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
		/* enable gfx powergating */
		amdgpu_device_ip_set_powergating_state(adev,
						       AMD_IP_BLOCK_TYPE_GFX,
						       AMD_PG_STATE_GATE);
		/* enable gfxoff */
		amdgpu_device_ip_set_powergating_state(adev,
						       AMD_IP_BLOCK_TYPE_SMC,
						       AMD_PG_STATE_GATE);
	}

	return 0;
}
@@ -1812,6 +1807,8 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev)
					  adev->ip_blocks[i].version->funcs->name, r);
				return r;
			}
			if (adev->powerplay.pp_funcs->set_powergating_by_smu)
				amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false);
			r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
			/* XXX handle errors */
			if (r) {
@@ -1921,12 +1918,6 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
	if (amdgpu_sriov_vf(adev))
		amdgpu_virt_request_full_gpu(adev, false);

	/* ungate SMC block powergating */
	if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
		amdgpu_device_ip_set_powergating_state(adev,
						       AMD_IP_BLOCK_TYPE_SMC,
						       AMD_PG_STATE_UNGATE);

	/* ungate SMC block first */
	r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
						   AMD_CG_STATE_UNGATE);
@@ -1934,6 +1925,10 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
		DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
	}

	/* call smu to disable gfx off feature first when suspend */
	if (adev->powerplay.pp_funcs->set_powergating_by_smu)
		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false);

	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
		if (!adev->ip_blocks[i].status.valid)
			continue;
+4 −0
Original line number Diff line number Diff line
@@ -3714,6 +3714,10 @@ static int gfx_v9_0_set_powergating_state(void *handle,

		/* update mgcg state */
		gfx_v9_0_update_gfx_mg_power_gating(adev, enable);

		/* set gfx off through smu */
		if (enable && adev->powerplay.pp_funcs->set_powergating_by_smu)
			amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true);
		break;
	default:
		break;
+0 −16
Original line number Diff line number Diff line
@@ -221,23 +221,7 @@ static int pp_sw_reset(void *handle)
static int pp_set_powergating_state(void *handle,
				    enum amd_powergating_state state)
{
	struct amdgpu_device *adev = handle;
	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
	int ret;

	if (!hwmgr || !hwmgr->pm_en)
	return 0;

	if (hwmgr->hwmgr_func->gfx_off_control) {
		/* Enable/disable GFX off through SMU */
		ret = hwmgr->hwmgr_func->gfx_off_control(hwmgr,
							 state == AMD_PG_STATE_GATE);
		if (ret)
			pr_err("gfx off control failed!\n");
	}

	return 0;

}

static int pp_suspend(void *handle)