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Commit 910a17e5 authored by Kirill A. Shutemov's avatar Kirill A. Shutemov Committed by Russell King
Browse files

ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size 



Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5.
It's not true at least for CPUs based on Cortex-A8.

List of CPUs with cache line size != 32 should be expanded later.

Signed-off-by: default avatarKirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 59fcf48f

arch/arm/include/asm/cache.h

+1 −1
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
#ifndef __ASMARM_CACHE_H

#define __ASMARM_CACHE_H



#define L1_CACHE_SHIFT		5

#define L1_CACHE_SHIFT		CONFIG_ARM_L1_CACHE_SHIFT

#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)



/*

arch/arm/mm/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -771,3 +771,8 @@ config CACHE_XSC3L2 
	select OUTER_CACHE

	help

	  This option enables the L2 cache on XScale3.



config ARM_L1_CACHE_SHIFT

	int

	default 6 if ARCH_OMAP3

	default 5