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Commit 90218ac7 authored by Kyle Huey's avatar Kyle Huey Committed by Thomas Gleixner
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x86/cpufeature: Detect CPUID faulting support 

Intel supports faulting on the CPUID instruction beginning with Ivy Bridge.
When enabled, the processor will fault on attempts to execute the CPUID
instruction with CPL>0. This will allow a ptracer to emulate the CPUID
instruction.

Bit 31 of MSR_PLATFORM_INFO advertises support for this feature. It is
documented in detail in Section 2.3.2 of
https://bugzilla.kernel.org/attachment.cgi?id=243991



Detect support for this feature and expose it as X86_FEATURE_CPUID_FAULT.

Signed-off-by: default avatarKyle Huey <khuey@kylehuey.com>
Reviewed-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
Cc: kvm@vger.kernel.org
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Andi Kleen <andi@firstfloor.org>
Cc: linux-kselftest@vger.kernel.org
Cc: Nadav Amit <nadav.amit@gmail.com>
Cc: Robert O'Callahan <robert@ocallahan.org>
Cc: Richard Weinberger <richard@nod.at>
Cc: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Len Brown <len.brown@intel.com>
Cc: Shuah Khan <shuah@kernel.org>
Cc: user-mode-linux-devel@lists.sourceforge.net
Cc: Jeff Dike <jdike@addtoit.com>
Cc: Alexander Viro <viro@zeniv.linux.org.uk>
Cc: user-mode-linux-user@lists.sourceforge.net
Cc: David Matlack <dmatlack@google.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Dmitry Safonov <dsafonov@virtuozzo.com>
Cc: linux-fsdevel@vger.kernel.org
Cc: Paolo Bonzini <pbonzini@redhat.com>
Link: http://lkml.kernel.org/r/20170320081628.18952-8-khuey@kylehuey.com


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 79170fda

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -187,6 +187,7 @@ 
 * Reuse free bits when adding new feature flags!

 */

#define X86_FEATURE_RING3MWAIT	( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */

#define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */

#define X86_FEATURE_CPB		( 7*32+ 2) /* AMD Core Performance Boost */

#define X86_FEATURE_EPB		( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */

#define X86_FEATURE_CAT_L3	( 7*32+ 4) /* Cache Allocation Technology L3 */

arch/x86/include/asm/msr-index.h

+2 −0
Original line number Diff line number Diff line
@@ -45,6 +45,8 @@ 
#define MSR_IA32_PERFCTR1		0x000000c2

#define MSR_FSB_FREQ			0x000000cd

#define MSR_PLATFORM_INFO		0x000000ce

#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT	31

#define MSR_PLATFORM_INFO_CPUID_FAULT		BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)



#define MSR_PKG_CST_CONFIG_CONTROL	0x000000e2

#define NHM_C3_AUTO_DEMOTE		(1UL << 25)

arch/x86/kernel/cpu/intel.c

+23 −1
Original line number Diff line number Diff line
@@ -488,6 +488,28 @@ static void intel_bsp_resume(struct cpuinfo_x86 *c) 
	init_intel_energy_perf(c);

}



static void init_cpuid_fault(struct cpuinfo_x86 *c)

{

	u64 msr;



	if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {

		if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)

			set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);

	}

}



static void init_intel_misc_features(struct cpuinfo_x86 *c)

{

	u64 msr;



	if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))

		return;



	/* Check features and update capabilities */

	init_cpuid_fault(c);

	probe_xeon_phi_r3mwait(c);

}



static void init_intel(struct cpuinfo_x86 *c)

{

	unsigned int l2 = 0;
@@ -602,7 +624,7 @@ static void init_intel(struct cpuinfo_x86 *c) 


	init_intel_energy_perf(c);



	probe_xeon_phi_r3mwait(c);

	init_intel_misc_features(c);

}



#ifdef CONFIG_X86_32