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Commit 90007bca authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

drm/i915/cnl: Introduce initial Cannonlake Workarounds. 



Let's inherit workarounds from previous platforms that
according to wa_database and BSpec are still valid for
Cannonlake.

v2: Add missed workarounds.
v3: Rebase
v4: Remove bad chunk that was added to rc6 disable. (Ander)
    Also remove A0 W/a that are not needed anymore.
v5: Rebase on top of CFL.
v6: Remove empty gen9_init_perctx_bb and gen9_init_indirectctx_bb
    since they don't carry any gen10 related W/a. (by Oscar).
    Also Remove A0 exclusive workaround.
v7: Remove more A0 exclusive workarounds. As pointed out by Oscar
    many workarounds were changed to be A0 only so let's remove
    them.

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarOscar Mateo <oscar.mateo@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170815231651.975-1-rodrigo.vivi@intel.com
parent 64f09f00

drivers/gpu/drm/i915/i915_gem_gtt.c

+2 −2
Original line number Diff line number Diff line
@@ -1885,12 +1885,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) 
	 * called on driver load and after a GPU reset, so you can place

	 * workarounds here even if they get overwritten by GPU reset.

	 */

	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl */

	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */

	if (IS_BROADWELL(dev_priv))

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);

	else if (IS_CHERRYVIEW(dev_priv))

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);

	else if (IS_GEN9_BC(dev_priv))

	else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);

	else if (IS_GEN9_LP(dev_priv))

		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);

drivers/gpu/drm/i915/i915_reg.h

+6 −0
Original line number Diff line number Diff line
@@ -3806,6 +3806,12 @@ enum { 
#define   PWM2_GATING_DIS		(1 << 14)

#define   PWM1_GATING_DIS		(1 << 13)



/*

 * GEN10 clock gating regs

 */

#define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)

#define  SARBUNIT_CLKGATE_DIS		(1 << 5)



/*

 * Display engine regs

 */

drivers/gpu/drm/i915/intel_engine_cs.c

+19 −0
Original line number Diff line number Diff line
@@ -1065,6 +1065,23 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine) 
	return 0;

}



static int cnl_init_workarounds(struct intel_engine_cs *engine)

{

	struct drm_i915_private *dev_priv = engine->i915;

	int ret;



	/* WaInPlaceDecompressionHang:cnl */

	WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,

		   GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);



	/* WaEnablePreemptionGranularityControlByUMD:cnl */

	ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);

	if (ret)

		return ret;



	return 0;

}



static int kbl_init_workarounds(struct intel_engine_cs *engine)

{

	struct drm_i915_private *dev_priv = engine->i915;
@@ -1185,6 +1202,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine) 
		err =  glk_init_workarounds(engine);

	else if (IS_COFFEELAKE(dev_priv))

		err = cfl_init_workarounds(engine);

	else if (IS_CANNONLAKE(dev_priv))

		err = cnl_init_workarounds(engine);

	else

		err = 0;

	if (err)

drivers/gpu/drm/i915/intel_lrc.c

+2 −0
Original line number Diff line number Diff line
@@ -1175,6 +1175,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine) 
		return -EINVAL;



	switch (INTEL_GEN(engine->i915)) {

	case 10:

		return 0;

	case 9:

		wa_bb_fn[0] = gen9_init_indirectctx_bb;

		wa_bb_fn[1] = gen9_init_perctx_bb;

drivers/gpu/drm/i915/intel_pm.c

+20 −1
Original line number Diff line number Diff line
@@ -8263,6 +8263,23 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, 
	I915_WRITE(GEN7_MISCCPCTL, misccpctl);

}



static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)

{

	/* WaEnableChickenDCPR:cnl */

	I915_WRITE(GEN8_CHICKEN_DCPR_1,

		   I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);



	/* WaFbcWakeMemOn:cnl */

	I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |

		   DISP_FBC_MEMORY_WAKE);



	/* WaSarbUnitClockGatingDisable:cnl (pre-prod) */

	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))

		I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE,

			   I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |

			   SARBUNIT_CLKGATE_DIS);

}



static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)

{

	gen9_init_clock_gating(dev_priv);
@@ -8743,7 +8760,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) 
 */

void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)

{

	if (IS_SKYLAKE(dev_priv))

	if (IS_CANNONLAKE(dev_priv))

		dev_priv->display.init_clock_gating = cannonlake_init_clock_gating;

	else if (IS_SKYLAKE(dev_priv))

		dev_priv->display.init_clock_gating = skylake_init_clock_gating;

	else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))

		dev_priv->display.init_clock_gating = kabylake_init_clock_gating;