Commit 8fede296 authored Jul 22, 2020 by Matthew Howell Committed by Greg Kroah-Hartman Jul 29, 2020

serial: exar: Fix GPIO configuration for Sealevel cards based on XR17V35X



[ Upstream commit 5fdbe136ae19ab751daaa4d08d9a42f3e30d17f9 ]

Sealevel XR17V35X based devices are inoperable on kernel versions
4.11 and above due to a change in the GPIO preconfiguration introduced in
commit
7dea8165. This patch fixes this by preconfiguring the GPIO on Sealevel
cards to the value (0x00) used prior to commit 7dea8165

With GPIOs preconfigured as per commit 7dea8165 all ports on
Sealevel XR17V35X based devices become stuck in high impedance
mode, regardless of dip-switch or software configuration. This
causes the device to become effectively unusable. This patch (in
various forms) has been distributed to our customers and no issues
related to it have been reported.

Fixes: 7dea8165 ("serial: exar: Preconfigure xr17v35x MPIOs as output")
Signed-off-by: Matthew Howell <matthew.howell@sealevel.com>
Link: https://lore.kernel.org/r/alpine.DEB.2.21.2007221605270.13247@tstest-VirtualBox


Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

parent 6ca307f3

drivers/tty/serial/8250/8250_exar.c

+11 −1

Original line number	Diff line number	Diff line
		@@ -227,7 +227,17 @@ static void setup_gpio(struct pci_dev pcidev, u8 __iomem p)
		* devices will export them as GPIOs, so we pre-configure them safely
		* as inputs.
		*/
		u8 dir = pcidev->vendor == PCI_VENDOR_ID_EXAR ? 0xff : 0x00;

		u8 dir = 0x00;

		if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
		(pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
		// Configure GPIO as inputs for Commtech adapters
		dir = 0xff;
		} else {
		// Configure GPIO as outputs for SeaLevel adapters
		dir = 0x00;
		}

		writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
		writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);