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Commit 8f72b316 authored by Linux Build Service Account's avatar Linux Build Service Account
Browse files

Merge 1e664b6f on remote branch

Change-Id: If9ccb19627ac5fda1c847945ffcb729491ef2790
parents 03f772a4 1e664b6f
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+4 −0
Original line number Diff line number Diff line
@@ -19,6 +19,10 @@ static void init_codecs(struct venus_core *core)
	struct venus_caps *caps = core->caps, *cap;
	unsigned long bit;

	if (hweight_long(core->dec_codecs) +
		hweight_long(core->enc_codecs) > MAX_CODEC_NUM)
		return;

	for_each_set_bit(bit, &core->dec_codecs, MAX_CODEC_NUM) {
		cap = &caps[core->codecs_count++];
		cap->codec = BIT(bit);
+42 −21
Original line number Diff line number Diff line
// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
 *
 * drivers/mmc/host/sdhci-msm.c - Qualcomm Technologies, Inc. MSM SDHCI Platform
 * driver source file
@@ -5042,6 +5042,44 @@ static int sdhci_msm_notify_load(struct sdhci_host *host, enum mmc_load state)
	return 0;
}

static int sdhci_msm_gcc_reset(struct device *dev, struct sdhci_host *host)
{

	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
	struct sdhci_msm_host *msm_host = pltfm_host->priv;
	struct reset_control *reset = msm_host->core_reset;
	int ret = -EOPNOTSUPP;

	if (!reset) {
		dev_err(dev, "unable to acquire core_reset\n");
		goto out;
	}

	ret = reset_control_assert(reset);
	if (ret) {
		dev_err(dev, "core_reset assert failed %d\n", ret);
		goto out;
	}

	/*
	 * The hardware requirement for delay between assert/deassert
	 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
	 * ~125us (4/32768). To be on the safe side add 200us delay.
	 */
	usleep_range(200, 210);

	ret = reset_control_deassert(reset);
	if (ret) {
		dev_err(dev, "core_reset deassert failed %d\n", ret);
		goto out;
	}

	usleep_range(200, 210);

out:
	return ret;
}

static void sdhci_msm_hw_reset(struct sdhci_host *host)
{
	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -5063,28 +5101,10 @@ static void sdhci_msm_hw_reset(struct sdhci_host *host)
		host->mmc->cqe_enabled = false;
	}

	ret = reset_control_assert(msm_host->core_reset);
	if (ret) {
		dev_err(&pdev->dev, "%s: core_reset assert failed, err = %d\n",
				__func__, ret);
		goto out;
	}

	/*
	 * The hardware requirement for delay between assert/deassert
	 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
	 * ~125us (4/32768). To be on the safe side add 200us delay.
	 */
	usleep_range(200, 210);

	ret = reset_control_deassert(msm_host->core_reset);
	if (ret)
		dev_err(&pdev->dev, "%s: core_reset deassert failed, err = %d\n",
				__func__, ret);

	sdhci_msm_gcc_reset(&pdev->dev, host);
	sdhci_msm_registers_restore(host);
	msm_host->reg_store = false;
out:

	return;
}

@@ -5411,6 +5431,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
		goto pltfm_free;
	}

	sdhci_msm_gcc_reset(&pdev->dev, host);
	/* Setup Clocks */

	/* Setup SDCC bus voter clock. */
+10 −0
Original line number Diff line number Diff line
@@ -2665,6 +2665,13 @@ cnss_use_nv_mac(struct cnss_plat_data *plat_priv)
				     "use-nv-mac");
}

static inline int cnss_get_cal_duration(struct cnss_plat_data *plat_priv)
{
	return of_property_read_u32(plat_priv->plat_dev->dev.of_node,
				    "qcom,cnss-cal-duration",
				    &plat_priv->cal_duration);
}

static int cnss_probe(struct platform_device *plat_dev)
{
	int ret = 0;
@@ -2698,6 +2705,9 @@ static int cnss_probe(struct platform_device *plat_dev)
	plat_priv->device_id = device_id->driver_data;
	plat_priv->bus_type = cnss_get_bus_type(plat_priv->device_id);
	plat_priv->use_nv_mac = cnss_use_nv_mac(plat_priv);
	if (cnss_get_cal_duration(plat_priv) != 0)
		plat_priv->cal_duration = CNSS_INVALID_CAL_DURATION;

	plat_priv->use_fw_path_with_prefix =
		cnss_use_fw_path_with_prefix(plat_priv);
	cnss_set_plat_priv(plat_dev, plat_priv);
+2 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@
#define CNSS_RAMDUMP_MAGIC		0x574C414E
#define CNSS_RAMDUMP_VERSION		0
#define MAX_FIRMWARE_NAME_LEN		20
#define CNSS_INVALID_CAL_DURATION       0xFFFFFFFF

#define CNSS_EVENT_SYNC   BIT(0)
#define CNSS_EVENT_UNINTERRUPTIBLE BIT(1)
@@ -397,6 +398,7 @@ struct cnss_plat_data {
	u32 diag_reg_read_len;
	u8 *diag_reg_read_buf;
	u8 cal_done;
	u32 cal_duration;
	u8 powered_on;
	u8 use_fw_path_with_prefix;
	char firmware_name[MAX_FIRMWARE_NAME_LEN];
+9 −0
Original line number Diff line number Diff line
@@ -228,6 +228,15 @@ static int cnss_wlfw_host_cap_send_sync(struct cnss_plat_data *plat_priv)
	req->cal_done = plat_priv->cal_done;
	cnss_pr_dbg("Calibration done is %d\n", plat_priv->cal_done);

	if (plat_priv->cal_duration != CNSS_INVALID_CAL_DURATION) {
		req->cal_duration_valid = 1;
		req->cal_duration = plat_priv->cal_duration;
		cnss_pr_dbg("Calibration duration: %u",
			    plat_priv->cal_duration);
	} else {
		cnss_pr_dbg("Calibration duration not valid");
	}

	if (!cnss_bus_get_iova(plat_priv, &iova_start, &iova_size) &&
	    !cnss_bus_get_iova_ipa(plat_priv, &iova_ipa_start,
				   &iova_ipa_size)) {
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