From dcfc8ec63d9f7b25e1e32362e244dad53703b7ee Mon Sep 17 00:00:00 2001
From: Ruchika Ashtankar <quic_rashtank@quicinc.com>
Date: Wed, 26 Apr 2023 20:51:47 +0530
Subject: [PATCH 001/298] video: driver: Return proper error code

Return correct error code when session is not
supported and when max mbpf limit is
reached.

Change-Id: I25c720356c372b8d7d3e461589493395710669eb

Signed-off-by: Ruchika Ashtankar <quic_rashtank@quicinc.com>
---
 msm/vidc/msm_vidc_common.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/msm/vidc/msm_vidc_common.c b/msm/vidc/msm_vidc_common.c
index 9872a3e05800..4a2be60aa062 100644
--- a/msm/vidc/msm_vidc_common.c
+++ b/msm/vidc/msm_vidc_common.c
@@ -5818,7 +5818,7 @@ static int msm_vidc_check_mbpf_supported(struct msm_vidc_inst *inst)
 
 	if (mbpf > core->resources.max_mbpf) {
 		msm_vidc_print_running_insts(inst->core);
-		return -EBUSY;
+		return -ENOMEM;
 	}
 
 	return 0;
-- 
GitLab


From c7eadc2670cb23c0d2ca49e8787d69ecc3f83e6e Mon Sep 17 00:00:00 2001
From: Uma Mehta <quic_umamehta@quicinc.com>
Date: Tue, 9 May 2023 11:12:21 +0530
Subject: [PATCH 002/298] video: driver: Return proper error code

Return correct error code when session is not
supported and when max memory limit is
reached.

Change-Id: I5ed3770ff4333b8828accbbb11b740ca316440b5
Signed-off-by: Uma Mehta <quic_umamehta@quicinc.com>
---
 msm/vidc/msm_vidc_common.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/msm/vidc/msm_vidc_common.c b/msm/vidc/msm_vidc_common.c
index 4a2be60aa062..3e968fc92def 100644
--- a/msm/vidc/msm_vidc_common.c
+++ b/msm/vidc/msm_vidc_common.c
@@ -5915,7 +5915,7 @@ int msm_comm_check_memory_supported(struct msm_vidc_inst *vidc_inst)
 			"%s: video mem overshoot - reached %llu MB, max_limit %llu MB\n",
 			__func__, total_mem_size >> 20, memory_limit_mbytes);
 		msm_comm_print_insts_info(core);
-		return -EBUSY;
+		return -ENOMEM;
 	}
 
 	if (!is_secure_session(vidc_inst)) {
@@ -5930,7 +5930,7 @@ int msm_comm_check_memory_supported(struct msm_vidc_inst *vidc_inst)
 				"%s: insufficient device addr space, required %llu, available %llu\n",
 				__func__, non_sec_mem_size, non_sec_cb_size);
 			msm_comm_print_insts_info(core);
-			return -EINVAL;
+			return -ENOMEM;
 		}
 	}
 
-- 
GitLab


From b1c558a8c922c47608cfd54509ac9786cb170aae Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sun, 25 Jun 2023 06:01:08 -0700
Subject: [PATCH 003/298] fw-api: CL 23581168 - update fw common interface
 files

add WMI_SERVICE_BRIDGE_VDEV_SUPPORT def

Change-Id: Ic1a0ca508c0432f76fbce5948498ded97d99fa82
CRs-Fixed: 2262693
---
 fw/wmi_services.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 016c7c25e08a..bb8f28064834 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -634,6 +634,7 @@ typedef  enum  {
     WMI_SERVICE_N_LINK_MLO_SUPPORT = 381,  /* Indicate FW supports N MLO link & vdev re-purpose between links */
     WMI_SERVICE_ATF_MAX_CLIENT_512_SUPPORT = 382, /* Indicates FW supports maximum of 512 clients when ATF is enabled */
     WMI_SERVICE_FISA_DYNAMIC_MSDU_AGGR_SIZE_SUPPORT = 383, /* Indicates FW support for FISA aggregation size up to 64 instead of only 16 */
+    WMI_SERVICE_BRIDGE_VDEV_SUPPORT = 384, /* Indicated FW supports Bridge VDEV */
 
     WMI_MAX_EXT2_SERVICE
 
-- 
GitLab


From 4d563e07cd6abfd2d54f72d5fa70b0763f5dfa09 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 27 Jun 2023 12:01:06 -0700
Subject: [PATCH 004/298] fw-api: CL 23606285 - update fw common interface
 files

add WMI_VDEV_PARAM_WIFI_STANDARD_VERSION def

Change-Id: Ia21f0bbd4d4f49b3546b4692a2a258e787008552
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 6 ++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 781425119ca2..d853a19ce3d9 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -18084,6 +18084,12 @@ typedef enum {
      */
     WMI_VDEV_PARAM_RTT_11AZ_TB_MAX_SESSION_EXPIRY,        /* 0xBD */
 
+    /*
+     * WiFi Standard version to be supported.
+     * Value is from enum WMI_WIFI_STANDARD
+     */
+    WMI_VDEV_PARAM_WIFI_STANDARD_VERSION,                 /* 0xBE */
+
 
     /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE ===
      * The below vdev param types are used for prototyping, and are
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index cd7766461b8a..308abca1e342 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1357
+#define __WMI_REVISION_ 1358
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From eed8d8104c12b967d8a56fce32eb4464c2213057 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 27 Jun 2023 12:01:59 -0700
Subject: [PATCH 005/298] fw-api: CL 23606322 - update fw common interface
 files

add WMI_SERVICE_MLO_MODE1_RECOVERY_SUPPORTED WMI svc flag def

Change-Id: Ic08a7b1e5ffd4ebf6557d0a330e2f36ddbabae9b
CRs-Fixed: 2262693
---
 fw/wmi_services.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index bb8f28064834..81cf32b97237 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -635,6 +635,7 @@ typedef  enum  {
     WMI_SERVICE_ATF_MAX_CLIENT_512_SUPPORT = 382, /* Indicates FW supports maximum of 512 clients when ATF is enabled */
     WMI_SERVICE_FISA_DYNAMIC_MSDU_AGGR_SIZE_SUPPORT = 383, /* Indicates FW support for FISA aggregation size up to 64 instead of only 16 */
     WMI_SERVICE_BRIDGE_VDEV_SUPPORT = 384, /* Indicated FW supports Bridge VDEV */
+    WMI_SERVICE_MLO_MODE1_RECOVERY_SUPPORTED = 385, /* Indicate fw support for mlo mode1 recovery */
 
     WMI_MAX_EXT2_SERVICE
 
-- 
GitLab


From 889bda9da75942e718cec029aa321617f20ac55a Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 29 Jun 2023 06:01:31 -0700
Subject: [PATCH 006/298] fw-api: CL 23627777 - update fw common interface
 files

add WMI_PDEV_PARAM_ATF_[VI,VO]_DEDICATED_TIME defs

Change-Id: I52b3f8d0bb032e9937fbe46a080b49da9510b47b
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 21 +++++++++++++++++++++
 fw/wmi_version.h |  2 +-
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index d853a19ce3d9..8fcfb04fd7e8 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -9241,6 +9241,27 @@ typedef enum {
      *  units are microseconds
      */
     WMI_PDEV_PARAM_SLOT_TIME,
+
+    /** VO dedicated time -
+     * allocate dedicated time slots for VO access category across all
+     * ATF groups in a pdev.
+     *   Note :
+     *   1.  Per AC airtime per group is already available through
+     *       ATF WMM WMI commands
+     *   2.  The dedicated time slot is applicable per second
+     *   3.  Units are in milli-seconds
+     */
+    WMI_PDEV_PARAM_ATF_VO_DEDICATED_TIME,
+
+    /** VI dedicated time -
+     * allocate dedicated time slots for VI access category across all
+     * ATF groups in a pdev.
+     *   Note :
+     *   1.  Per AC airtime per group is already given through ATF WMM WMI cmds
+     *   2.  The dedicated time slot is applicable per second
+     *   3.  Units are in milli-seconds
+     */
+    WMI_PDEV_PARAM_ATF_VI_DEDICATED_TIME,
 } WMI_PDEV_PARAM;
 
 #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 308abca1e342..398e3140f133 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1358
+#define __WMI_REVISION_ 1359
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 0132c4f4ba975585c6a11beb49fd16063837b5d1 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 29 Jun 2023 12:01:27 -0700
Subject: [PATCH 007/298] fw-api: CL 23629843 - update fw common interface
 files

add hw_prot_dur_us field in htt_ppdu_stats_user_cmpltn_common TLV

Change-Id: I4cae12b0244903b62af650c0d85a9952652ac7e6
CRs-Fixed: 2262693
---
 fw/htt_ppdu_stats.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h
index 54dd0b67c1fd..29fac3666355 100644
--- a/fw/htt_ppdu_stats.h
+++ b/fw/htt_ppdu_stats.h
@@ -2479,6 +2479,11 @@ typedef struct {
      * for BW supported by Smart Antenna - 320 MHZ
      */
     A_UINT32 max_rates_ext;
+
+    /* hw_prot_dur_us:
+     * hw protection frame's FES duration in micro seconds.
+     */
+    A_UINT32 hw_prot_dur_us;
 } htt_ppdu_stats_user_cmpltn_common_tlv;
 
 #define HTT_PPDU_STATS_USER_CMPLTN_BA_BITMAP_TLV_TID_NUM_M     0x000000ff
-- 
GitLab


From fbba0a745b71780d7772fea5496ece4da710715b Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 29 Jun 2023 12:02:28 -0700
Subject: [PATCH 008/298] fw-api: CL 23631091 - update fw common interface
 files

add wmi_sta_ps_enable_opm enum def

Change-Id: I26273bd3dffbc499217e7f42ac014004c12da76d
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 15 ++++++++++++++-
 fw/wmi_version.h |  2 +-
 2 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 8fcfb04fd7e8..7fb511b04d4c 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -19103,6 +19103,12 @@ enum wmi_sta_ps_param_uapsd {
     WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7),
 };
 
+enum wmi_sta_ps_scheme_cfg {
+    WMI_STA_PS_OPM_CONSERVATIVE = 0,
+    WMI_STA_PS_OPM_AGGRESSIVE = 1,
+    WMI_STA_PS_USER_DEF = 2,
+};
+
 enum wmi_sta_powersave_param {
 /**
  * Controls how frames are retrievd from AP while STA is sleeping
@@ -19148,9 +19154,10 @@ WMI_STA_PS_PARAM_UAPSD = 4,
 WMI_STA_PS_PARAM_QPOWER_PSPOLL_COUNT = 5,
 
 /**
- * Enable QPower
+ * Enable OPM
  */
 WMI_STA_PS_ENABLE_QPOWER = 6,
+    WMI_STA_PS_ENABLE_OPM = WMI_STA_PS_ENABLE_QPOWER, /* alias */
 
 /**
  * Number of TX frames before the entering the Active state
@@ -19179,6 +19186,12 @@ WMI_STA_PS_PARAM_MAX_RESET_ITO_COUNT_ON_TIM_NO_TXRX = 10,
  * in WOW
  */
 WMI_STA_PS_PARAM_ENABLE_PS_OPT_IN_WOW = 11,
+
+/**
+ *  Speculative interval in ms
+ */
+WMI_STA_PS_PARAM_SPEC_WAKE_INTERVAL = 12,
+
 };
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 398e3140f133..358002bd0ebf 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1359
+#define __WMI_REVISION_ 1360
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 8b63dd984462c5aa60d0d1eeef85f7383ff4235e Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 30 Jun 2023 06:01:22 -0700
Subject: [PATCH 009/298] fw-api: CL 23638576 - update fw common interface
 files

HTT stats: add use_ppe and src_info bitfields in peer_details TLV

Change-Id: I326e6dca11f9d76e5dc5eaadfe2204d3739dee91
CRs-Fixed: 2262693
---
 fw/htt_stats.h | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 11e67bc1ff6a..800ee6e9d56d 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -1636,6 +1636,13 @@ typedef struct {
 #define HTT_PEER_DETAILS_ML_PEER_ID_S         1
 #define HTT_PEER_DETAILS_LINK_IDX_M           0x001fe000
 #define HTT_PEER_DETAILS_LINK_IDX_S           13
+#define HTT_PEER_DETAILS_USE_PPE_M            0x00200000
+#define HTT_PEER_DETAILS_USE_PPE_S            21
+
+
+#define HTT_PEER_DETAILS_SRC_INFO_M           0x00000fff
+#define HTT_PEER_DETAILS_SRC_INFO_S           0
+
 
 #define HTT_PEER_DETAILS_SET(word, httsym, val)  \
     do {                                         \
@@ -1664,7 +1671,11 @@ typedef struct {
     A_UINT32     ml_peer_id_valid  : 1,   /* [0:0] */
                  ml_peer_id        : 12,  /* [12:1] */
                  link_idx          : 8,   /* [20:13] */
-                 rsvd              : 11;  /* [31:21] */
+                 use_ppe           : 1,   /* [21:21] */
+                 rsvd0             : 10;  /* [31:22] */
+    /* Dword 9 */
+    A_UINT32     src_info          : 12,  /* [11:0] */
+                 rsvd1             : 20;  /* [31:12] */
 } htt_peer_details_tlv;
 
 typedef struct {
-- 
GitLab


From 41ef4ae7421602fbd503616d37b505b881e5ee1a Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 30 Jun 2023 06:02:35 -0700
Subject: [PATCH 010/298] fw-api: CL 23639466 - update fw common interface
 files

Change-Id: Iaeb4c05220748d84be6406f71e1e3bf5f339260c
WMI: flip the sense of the link_status values in mlo_vdev_link_info TLV
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 2 +-
 fw/wmi_version.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 7fb511b04d4c..ace32763bac6 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -45646,7 +45646,7 @@ typedef struct {
         struct {
             A_UINT32 vdev_id:8,     /* vdev id for this link */
                      link_id:8,     /* link id defined as in 802.11 BE spec. */
-                     link_status:2, /* link_status - 0: active, 1: inactive  */
+                     link_status:2, /* link_status - 0: inactive, 1: active  */
                      reserved:14;
         };
         A_UINT32 link_info;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 358002bd0ebf..ff4ab6839b01 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1360
+#define __WMI_REVISION_ 1361
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 59b20e6616bb4c2ca1ef864f1f1cb85768430ab3 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 4 Jul 2023 12:01:41 -0700
Subject: [PATCH 011/298] fw-api: CL 23675183 - update fw common interface
 files

Change-Id: Ifd599d030bb0744f91fc95f5218a2640dc187cd0
WMI: add ctrl_path_sta_rrm_stats in CTRL_PATH_STATS_EVENT msg
CRs-Fixed: 2262693
---
 fw/wmi_tlv_defs.h |  3 ++-
 fw/wmi_unified.h  | 13 +++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 624b8449afe2..988f0df05bae 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -6916,7 +6916,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_t2lm_stats_struct,  ctrl_path_t2lm_stats, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_blanking_stats_struct,  ctrl_path_blanking_stats, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_peer_stats_struct,  ctrl_path_peer_stats, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_vdev_stats_struct,  ctrl_path_vdev_stats, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_vdev_stats_struct,  ctrl_path_vdev_stats, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_sta_rrm_stats_struct,  ctrl_path_sta_rrm_stats, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID);
 
 /*
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index ace32763bac6..b130cf54e0fd 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -15696,6 +15696,18 @@ typedef struct {
 #define WMI_VDEV_STATS_IS_MULTI_GROUP_KEY_ENABLED_GET(flag) \
     WMI_GET_BITS(flag, 31, 1)
 
+typedef struct {
+    /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_sta_rrm_stats_struct */
+    A_UINT32 tlv_header;
+    A_UINT32 dot11GroupTransmittedFrameCount;
+    A_UINT32 dot11GroupReceivedFrameCount;
+    A_UINT32 dot11TransmittedFrameCount;
+    A_UINT32 dot11AckFailureCount;
+    A_UINT32 dot11FailedCount;
+    A_UINT32 dot11FCSErrorCount;
+    A_UINT32 dot11RTSSuccessCount;
+    A_UINT32 dot11RTSFailureCount;
+} wmi_ctrl_path_sta_rrm_stats_struct;
 
 /**
  *  peer statistics.
@@ -34664,6 +34676,7 @@ typedef enum {
     WMI_REQUEST_CTRL_PATH_BLANKING_STAT     = 15,
     WMI_REQUEST_CTRL_PATH_PEER_STAT         = 16,
     WMI_REQUEST_CTRL_PATH_VDEV_DEBUG_STAT   = 17,
+    WMI_REQUEST_CTRL_STA_RRM_STAT           = 18,
 } wmi_ctrl_path_stats_id;
 
 typedef enum {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index ff4ab6839b01..b323d691f53c 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1361
+#define __WMI_REVISION_ 1362
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 1a7f0651933b56740a117ba9eae5ee08828f4bf4 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 12 Jul 2023 06:01:21 -0700
Subject: [PATCH 012/298] fw-api: CL 23772239 - update fw common interface
 files

HTT PPDU stats: add is_min_rate flag in user_rate TLV

Change-Id: I39750c66c95a415bd4cb26bdcc04bc8135ca07c5
CRs-Fixed: 2262693
---
 fw/htt_ppdu_stats.h | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h
index 29fac3666355..1799410381d6 100644
--- a/fw/htt_ppdu_stats.h
+++ b/fw/htt_ppdu_stats.h
@@ -1819,6 +1819,19 @@ typedef enum HTT_PPDU_STATS_RESP_PPDU_TYPE HTT_PPDU_STATS_RESP_PPDU_TYPE;
         ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_S)); \
     } while (0)
 
+#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_M  0x00020000
+#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_S          17
+
+#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_GET(_var) \
+    (((_var) & HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_M) >> \
+    HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_S)
+
+#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_SET (_var , _val) \
+    do { \
+        HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE, _val); \
+        ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_S)); \
+    } while (0)
+
 typedef enum HTT_PPDU_STATS_RU_SIZE {
     HTT_PPDU_STATS_RU_26,
     HTT_PPDU_STATS_RU_52,
@@ -2009,7 +2022,8 @@ typedef struct {
      */
     A_UINT32 punc_pattern_bitmap: 16,
              extra_eht_ltf:       1,
-             reserved4:           15;
+             is_min_rate:         1,
+             reserved4:           14;
 } htt_ppdu_stats_user_rate_tlv;
 
 #define HTT_PPDU_STATS_USR_RATE_VALID_M     0x80000000
-- 
GitLab


From 078c19b0eb55989b1fda8bb2d5095da2c0e03fc8 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 12 Jul 2023 06:02:30 -0700
Subject: [PATCH 013/298] fw-api: CL 23772256 - update fw common interface
 files

add WMI_VDEV_PARAM_DISABLE_2G_TWT def

Change-Id: I614d124b7e06cc9d4b6b793db749630f5295f04c
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 6 ++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index b130cf54e0fd..df70de4947d5 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -18123,6 +18123,12 @@ typedef enum {
      */
     WMI_VDEV_PARAM_WIFI_STANDARD_VERSION,                 /* 0xBE */
 
+    /*
+     * Allow to disable TWT on 2G channel
+     * if corresponding INI is set
+     */
+    WMI_VDEV_PARAM_DISABLE_2G_TWT,                        /* 0xBF */
+
 
     /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE ===
      * The below vdev param types are used for prototyping, and are
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index b323d691f53c..758fa6c35efc 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1362
+#define __WMI_REVISION_ 1363
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From ced8b2ba4167e610eaa432e55620d12d5699fa2c Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 13 Jul 2023 06:01:17 -0700
Subject: [PATCH 014/298] fw-api: CL 23782068 - update fw common interface
 files

Change-Id: Ifcc4d1c1a0c4dd621b4bd9f87ab94717a5822ed2
WMI: add PDEV_ENHANCED_AOA_PHASEDELTA_EVENT msg def
CRs-Fixed: 2262693
---
 fw/wmi_tlv_defs.h |  13 +++++
 fw/wmi_unified.h  | 127 ++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |   2 +-
 3 files changed, 141 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 988f0df05bae..1ea989ef35cd 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1392,6 +1392,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_aux_dev_capabilities,
     WMITLV_TAG_STRUC_wmi_nan_oem_data_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_nan_oem_data_event_fixed_param,
+    WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param,
+    WMITLV_TAG_STRUC_wmi_enhanced_aoa_gain_phase_data_hdr,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2241,6 +2243,7 @@ typedef enum {
     OP(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID) \
     OP(WMI_MLO_LINK_SWITCH_REQUEST_EVENTID) \
     OP(WMI_NAN_OEM_DATA_EVENTID) \
+    OP(WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -7432,6 +7435,16 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_primary_link_peer_migration_status, primary_link_peer_migration_status, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID);
 
+/*
+ * Update AOA Phase delta values for all gain tables event
+ * Below definition shows TLV packing of AOA Phase delta values for all gain tables event
+ */
+#define WMITLV_TABLE_WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID(id, op, buf, len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param, wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_gain_phase_data_hdr, aoa_data_hdr, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, aoa_data_buf, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID);
+
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index df70de4947d5..f2a13940bbaf 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -1748,6 +1748,8 @@ typedef enum {
     /* Event to indicate completion on RF path */
     WMI_PDEV_SET_RF_PATH_RESP_EVENTID,
 
+    /* Event to get AOA phasedelta values for all gain tables from HALPHY */
+    WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID,
 
     /* VDEV specific events */
     /** VDEV started event in response to VDEV_START request */
@@ -40444,6 +40446,131 @@ typedef struct {
     A_UINT32 perChainIbfCalVal[WMI_MAX_CHAINS_FOR_AOA_RCC];
 } wmi_pdev_aoa_phasedelta_evt_fixed_param;
 
+#define WMI_AOA_MAX_SUPPORTED_CHAINS_GET(chain_data) \
+    WMI_GET_BITS(chain_data, 0, 16)
+#define WMI_AOA_MAX_SUPPORTED_CHAINS_SET(chain_data, value) \
+    WMI_SET_BITS(chain_data, 0, 16, value)
+
+#define WMI_AOA_SUPPORTED_CHAINMASK_GET(chain_data) \
+    WMI_GET_BITS(chain_data, 16, 16)
+#define WMI_AOA_SUPPORTED_CHAINMASK_SET(chain_data, value) \
+    WMI_SET_BITS(chain_data, 16, 16, value)
+
+typedef struct {
+    /** TLV tag and len; tag equals
+      * WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_eventid */
+    A_UINT32 tlv_header;
+    /* Current Operating Channel Frequency in MHz */
+    A_UINT32 freq;
+    /** pdev_id:
+     * Identify the MAC.
+     * See macros starting with WMI_PDEV_ID_ for values.
+     * In non-DBDC case host should set it to 0.
+     */
+    A_UINT32 pdev_id;
+    /** chain_info:
+     * B0 -- B15 : Max number of chains supported
+     * B16 --B31 : Data shared for chainmask -
+     *             indicates the chains to which the data shared.
+     */
+    union {
+        struct {
+            A_UINT32 max_supported_chains:16,
+                     data_for_chainmask:16;
+        };
+        A_UINT32 chain_info;
+    };
+    /** XBAR configuration to get RF2BB/BB2RF chain mapping
+     * Samples of xbar_config,
+     * If xbar_config is 0xFAC688(hex):
+     *     RF chains 0-7 are connected to BB chains 0-7
+     *     here,
+     *         bits 0 to 2 = 0, maps BB chain 0 for RF chain 0
+     *         bits 3 to 5 = 1, maps BB chain 1 for RF chain 1
+     *         bits 6 to 8 = 2, maps BB chain 2 for RF chain 2
+     *         bits 9 to 11 = 3, maps BB chain 3 for RF chain 3
+     *         bits 12 to 14 = 4, maps BB chain 4 for RF chain 4
+     *         bits 15 to 17 = 5, maps BB chain 5 for RF chain 5
+     *         bits 18 to 20 = 6, maps BB chain 6 for RF chain 6
+     *         bits 21 to 23 = 7, maps BB chain 7 for RF chain 7
+     *
+     * If xbar_config is 0x688FAC(hex):
+     *     RF chains 0-3 are connected to BB chains 4-7
+     *     RF chains 4-7 are connected to BB chains 0-3
+     *     here,
+     *         bits 0 to 2 = 4, maps BB chain 4 for RF chain 0
+     *         bits 3 to 5 = 5, maps BB chain 5 for RF chain 1
+     *         bits 6 to 8 = 6, maps BB chain 6 for RF chain 2
+     *         bits 9 to 11 = 7, maps BB chain 7 for RF chain 3
+     *         bits 12 to 14 = 0, maps BB chain 0 for RF chain 4
+     *         bits 15 to 17 = 1, maps BB chain 1 for RF chain 5
+     *         bits 18 to 20 = 2, maps BB chain 2 for RF chain 6
+     *         bits 21 to 23 = 3, maps BB chain 3 for RF chain 7
+     */
+    A_UINT32 xbar_config;
+    /**
+     * IBF cal values:
+     * Used for final AoA calculation
+     * [AoAPhase =  ( PhaseDeltaValue + IBFcalValue )   %   1024]
+     */
+    A_UINT32 per_chain_ibf_cal_val[WMI_MAX_CHAINS];
+    /**
+     * This TLV is followed by TLV arrays containing
+     * different types of data header and data buffer TLVs:
+     * 1.  wmi_enhanced_aoa_gain_phase_data_hdr.
+     *     This TLV contains the array of structure fields which indicate
+     *     the type and format of data carried in the following data buffer
+     *     TLV.
+     * 2.  aoa_data_buf[] - Data buffer TLV.
+     *     TLV header contains the total buffer size.
+     *     Data buffer contains the phase_delta_array[Chains][GainEntries]
+     *     in absolute phase values ranging 0-1024 and
+     *     gain_delta_array[Chains][GainEntries] are gain index values.
+     */
+} wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param;
+
+#define WMI_AOA_DATA_TYPE_GET(data_info) \
+    WMI_GET_BITS(data_info, 0, 8)
+#define WMI_AOA_DATA_TYPE_SET(data_info,value) \
+    WMI_SET_BITS(data_info, 0, 8, value)
+
+#define WMI_AOA_NUM_ENTIRES_GET(data_info) \
+    WMI_GET_BITS(data_info, 8, 8)
+#define WMI_AOA_NUM_DATA_ENTRIES_SET(data_info,value) \
+    WMI_SET_BITS(data_info, 8, 8, value)
+
+typedef enum _WMI_AOA_EVENT_DATA_TYPE {
+    WMI_PHASE_DELTA_ARRAY = 0x0,
+    WMI_GAIN_GROUP_STOP_ARRAY = 0x1,
+    /* add new types here */
+    WMI_MAX_DATA_TYPE_ARRAY,
+} WMI_AOA_EVENT_DATA_TYPE;
+
+typedef struct {
+    /** TLV tag and len; tag equals
+      * WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_eventid */
+    A_UINT32 tlv_header;
+    /** data_info:
+     * Data follows the LSB first and MSB second order in a 32bit word
+     * bit mapping:
+     * B0 -- B7  : Data type
+     * B8 -- B15 : Number of entries to be parsed in terms of 32bit word
+     *
+     * If data is Phase delta values - Data type is 0x0
+     * group stop gain index values - Data type is 0x1
+     *
+     * num_entries - Total number of data entries in uint32
+     */
+    union {
+        struct {
+            A_UINT32 data_type:8,
+                     num_entries:8,
+                     reserved:16;
+        };
+        A_UINT32 data_info;
+    };
+} wmi_enhanced_aoa_gain_phase_data_hdr;
+
 /* WMI_HALPHY_CAL_LIST:
  *
  * Below is the list of HALPHY online CAL currently enabled in
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 758fa6c35efc..bf78f1013fd6 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1363
+#define __WMI_REVISION_ 1364
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 09878460c5148cff988266ead7d6dd2752bc9744 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 14 Jul 2023 06:01:18 -0700
Subject: [PATCH 015/298] fw-api: CL 23799210 - update fw common interface
 files

Change-Id: I0d28df3a8bf99276cd5603bbe597d3b20a6d1318
WMI: add [active,inactive] link bitmap fields in MLO_LINK_SET_ACTIVE_RESP_EVENT
CRs-Fixed: 2262693
---
 fw/wmi_tlv_defs.h | 4 +++-
 fw/wmi_unified.h  | 4 ++++
 fw/wmi_version.h  | 2 +-
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 1ea989ef35cd..90df76a79e8f 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -7228,7 +7228,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_TWT_SESSION_STATS_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_active_vdev_bitmap, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_inactive_vdev_bitmap, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_active_ieee_link_id_bitmap, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_inactive_ieee_link_id_bitmap, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_inactive_ieee_link_id_bitmap, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, current_active_ieee_link_id_bitmap, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, current_inactive_ieee_link_id_bitmap, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_ACTIVE_RESP_EVENTID);
 
 /* Get DPD status Event */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index f2a13940bbaf..7cf448ec4153 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -44320,6 +44320,10 @@ typedef struct wmi_mlo_link_set_active_resp_event
  * If use_ieee_link_id_bitmap equals 1, ieee_link_id_bitmap[] are valid.
  *     A_UINT32 force_active_ieee_link_id_bitmap[];
  *     A_UINT32 force_inactive_ieee_link_id_bitmap[];
+ *---
+ *  current active ieee link id bitmap & inactive ieee link id bitmap
+ *     A_UINT32 current_active_ieee_link_id_bitmap[];
+ *     A_UINT32 current_inactive_ieee_link_id_bitmap[];
  */
 } wmi_mlo_link_set_active_resp_event_fixed_param;
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index bf78f1013fd6..f6a072c21452 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1364
+#define __WMI_REVISION_ 1365
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From d47254c57877873b89d3802b8142a53041e0350c Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 15 Jul 2023 18:01:26 -0700
Subject: [PATCH 016/298] fw-api: CL 23810815 - update fw common interface
 files

add WMI_UNIFIED_VDEV_START_MLO_REPURPOSE_VAP def

Change-Id: I22b612169041c23abb4b72f78c8612468ac587e4
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 6 ++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 7cf448ec4153..befd15ce2523 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -16203,6 +16203,12 @@ typedef enum {
  *  If SW encryption is enabled, key plumbing will not happen in FW.
  */
 #define WMI_UNIFIED_VDEV_START_HW_ENCRYPTION_DISABLED  (1<<4)
+/** Indicates VAP is used for MLO repurpose.
+ *  This Indicates that vap can be brought up as 11ax or 11be and can be
+ *  repurposed based on the above stack on the fly to change from MLO to
+ *  non MLO, currently we support only 11ax and 11be transition.
+ */
+#define WMI_UNIFIED_VDEV_START_MLO_REPURPOSE_VAP (1<<5)
 
 /* BSS color 0-6 */
 #define WMI_HEOPS_COLOR_GET_D2(he_ops) WMI_GET_BITS(he_ops, 0, 6)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index f6a072c21452..d272a80a24f6 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1365
+#define __WMI_REVISION_ 1366
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 4e4fb82793162bdf4d47a4ce42a0c4b80e6857eb Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 19 Jul 2023 06:01:22 -0700
Subject: [PATCH 017/298] fw-api: CL 23852898 - update fw common interface
 files

add WMI_SERVICE_TX_PWR_PER_PPDU_STATS_SUPPORT def

Change-Id: I1f0197e96b365d13200aea55100ead6bd0a33a9e
CRs-Fixed: 2262693
---
 fw/wmi_services.h | 1 +
 fw/wmi_version.h  | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 81cf32b97237..aff03e214736 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -636,6 +636,7 @@ typedef  enum  {
     WMI_SERVICE_FISA_DYNAMIC_MSDU_AGGR_SIZE_SUPPORT = 383, /* Indicates FW support for FISA aggregation size up to 64 instead of only 16 */
     WMI_SERVICE_BRIDGE_VDEV_SUPPORT = 384, /* Indicated FW supports Bridge VDEV */
     WMI_SERVICE_MLO_MODE1_RECOVERY_SUPPORTED = 385, /* Indicate fw support for mlo mode1 recovery */
+    WMI_SERVICE_TX_PWR_PER_PPDU_STATS_SUPPORT = 386, /* FW support to check tx power stats per PPDU */
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index d272a80a24f6..9881f74da9fd 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1366
+#define __WMI_REVISION_ 1367
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 4273cb269aa1f4086374b3ab41b97aa4345678f7 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 20 Jul 2023 06:01:38 -0700
Subject: [PATCH 018/298] fw-api: CL 23872196 - update fw common interface
 files

Change-Id: Icfd5cc2cbb821f6e3d5c8fcb9401d04132fea43c
WMI: DISABLE_WDS_PEER svc flag + DISABLE_WDS_PEER flag for MAP_UNMAP_EVENT
CRs-Fixed: 2262693
---
 fw/wmi_services.h |  1 +
 fw/wmi_unified.h  | 16 +++++++++++++++-
 fw/wmi_version.h  |  2 +-
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index aff03e214736..80e30b975c5d 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -637,6 +637,7 @@ typedef  enum  {
     WMI_SERVICE_BRIDGE_VDEV_SUPPORT = 384, /* Indicated FW supports Bridge VDEV */
     WMI_SERVICE_MLO_MODE1_RECOVERY_SUPPORTED = 385, /* Indicate fw support for mlo mode1 recovery */
     WMI_SERVICE_TX_PWR_PER_PPDU_STATS_SUPPORT = 386, /* FW support to check tx power stats per PPDU */
+    WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT = 387, /* Indicate FW support to disable wds peer map/unmap events */
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index befd15ce2523..088fa78e6fc2 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -4480,8 +4480,17 @@ typedef struct {
      *      0 - Primary
      *      1 - Secondary
      *      Refer to WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_GET/SET macros.
+     * Bit 18 - disable_wds_peer_map_unmap_event
+     *      Flag to indicate whether the WDS peer map/unmap event should be
+     *      processed or ignored.
+     *      0 - leave the WDS peer map/unmap event enabled
+     *      1 - disable the WDS peer map/unmap event
+     *      This flag shall only be set if the target has set the
+     *      WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT flag.
+     *      Refer to WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_GET
+     *      and _SET macros.
      *
-     *  Bits 31:18 - Reserved
+     *  Bits 31:19 - Reserved
      */
     A_UINT32 flags2;
     /** @brief host_service_flags - can be used by Host to indicate
@@ -4947,6 +4956,11 @@ typedef struct {
 #define WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_SET(flags2, value) \
     WMI_SET_BITS(flags2, 17, 1, value)
 
+#define WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_GET(flags2) \
+    WMI_GET_BITS(flags2, 18, 1)
+#define WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SET(flags2, value) \
+    WMI_SET_BITS(flags2, 18, 1, value)
+
 
 #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET(host_service_flags) \
     WMI_GET_BITS(host_service_flags, 0, 1)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 9881f74da9fd..25f2dc073797 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1367
+#define __WMI_REVISION_ 1368
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From f4e54fd877b03a224d372419a00e5c339f5bcebf Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 20 Jul 2023 06:02:42 -0700
Subject: [PATCH 019/298] fw-api: CL 23874450 - update fw common interface
 files

HTT PPDU stats: add is_smart_ulofdma_basic_trig flag

Change-Id: I62cddf908ab86ec662ce13d44c7566956a874736
CRs-Fixed: 2262693
---
 fw/htt_ppdu_stats.h | 27 +++++++++++++++++++++++----
 1 file changed, 23 insertions(+), 4 deletions(-)

diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h
index 1799410381d6..fed6e2d63975 100644
--- a/fw/htt_ppdu_stats.h
+++ b/fw/htt_ppdu_stats.h
@@ -1057,6 +1057,20 @@ typedef struct {
          ((_var) |= ((_val) << HTT_PPDU_STATS_USER_COMMON_TLV_CHAIN_ENABLE_BITS_S)); \
      } while (0)
 
+#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_M  0x00010000
+#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_S          16
+
+#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_GET(_var) \
+    (((_var) & HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_M) >> \
+    HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_S)
+
+#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_SET(_var, _val) \
+     do { \
+         HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG, _val); \
+         ((_var) |= ((_val) << HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_S)); \
+     } while (0)
+
+
 #define HTT_PPDU_STATS_USER_COMMON_TLV_TX_PWR_CHAINS_PER_U32 4
 #define HTT_PPDU_STATS_USER_COMMON_TLV_TX_PWR_MASK 0x000000ff
 
@@ -1194,10 +1208,15 @@ typedef struct {
      * Default value: 1
      * tx_pwr[0] value is used for all chains if chain_enable_bits field
      * is set to 1.
-     */
-    A_UINT32 tx_pwr_multiplier  : 8,
-             chain_enable_bits  : 8,
-             reserved2          : 16;
+     *
+     * is_smart_ulofdma_basic_trig:
+     * To check if user grouped in UL OFDMA Basic Trigger Frame is
+     * due to Smart Basic Trigger.
+     */
+    A_UINT32 tx_pwr_multiplier          :  8,
+             chain_enable_bits          :  8,
+             is_smart_ulofdma_basic_trig:  1,
+             reserved2                  : 15;
 
     /*
      * Transmit powers (signed values packed into unsigned bitfields)
-- 
GitLab


From 45525c758a8a433b5cd9b1f67ba62616b565e684 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 20 Jul 2023 18:01:31 -0700
Subject: [PATCH 020/298] fw-api: CL 23887001 - update fw common interface
 files

add WOW_REASON_VDEV_REPURPOSE def

Change-Id: Ib8fcb568c958ae2b9c639fd934fc5e1c4d275537
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 2 ++
 fw/wmi_version.h | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 088fa78e6fc2..b6c960851079 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -23282,6 +23282,8 @@ typedef enum wake_reason_e {
     WOW_REASON_XGAP,
     /* COEX channel avoid event */
     WOW_REASON_COEX_CHAVD,
+    /* vdev repurpose request event */
+    WOW_REASON_VDEV_REPURPOSE,
 
     /* add new WOW_REASON_ defs before this line */
     WOW_REASON_MAX,
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 25f2dc073797..cf57eb712337 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1368
+#define __WMI_REVISION_ 1369
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From ac337aa24a2a32ea2758c0fd986adb00692bb3c3 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 21 Jul 2023 12:01:48 -0700
Subject: [PATCH 021/298] fw-api: CL 23894107 - update fw common interface
 files

add WMI_VENDOR_OUI_ACTION_SEND_SMPS_FRAME_WITH_OMN def

Change-Id: Iad32aa61e31e3f287b7feec67efcdf53b260af8f
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 7 +++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index b6c960851079..4562ac83526c 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -24935,6 +24935,13 @@ typedef enum
      */
     WMI_VENDOR_OUI_ACTION_ENABLE_CTS2SELF_WITH_QOS_NULL = 11,
 
+    /*
+     * Send SMPS frame following OMN frame on VHT conncection if specific
+     * vendor OUI received in beacon.
+     */
+    WMI_VENDOR_OUI_ACTION_SEND_SMPS_FRAME_WITH_OMN = 12,
+
+
     /* Add any action before this line */
     WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID
 } wmi_vendor_oui_action_id;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index cf57eb712337..02c7f0567126 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1369
+#define __WMI_REVISION_ 1370
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From a266f4009f3f36d010b2c559dfe121c4bd50ccfd Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 22 Jul 2023 06:01:46 -0700
Subject: [PATCH 022/298] fw-api: CL 23907437 - update fw common interface
 files

HTT stats: add CV correlation stats

Change-Id: I0a646178d10132e757685a688504ea2c57d6f6b3
CRs-Fixed: 2262693
---
 fw/htt_stats.h | 68 +++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 65 insertions(+), 3 deletions(-)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 800ee6e9d56d..7296a29db63f 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -6507,12 +6507,15 @@ typedef enum {
 } htt_txbf_sound_steer_modes;
 
 typedef enum {
-    HTT_TX_AC_SOUNDING_MODE = 0,
-    HTT_TX_AX_SOUNDING_MODE = 1,
-    HTT_TX_BE_SOUNDING_MODE = 2,
+    HTT_TX_AC_SOUNDING_MODE  = 0,
+    HTT_TX_AX_SOUNDING_MODE  = 1,
+    HTT_TX_BE_SOUNDING_MODE  = 2,
     HTT_TX_CMN_SOUNDING_MODE = 3,
+    HTT_TX_CV_CORR_MODE      = 4,
 } htt_stats_sounding_tx_mode;
 
+#define HTT_TX_CV_CORR_MAX_NUM_COLUMNS 8
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     A_UINT32      tx_sounding_mode; /* HTT_TX_XX_SOUNDING_MODE */
@@ -6625,6 +6628,65 @@ typedef struct {
     A_UINT32 adaptive_snd_kicked_in;
     /** Total number of times we switched back to normal sounding interval */
     A_UINT32 adaptive_snd_back_to_default;
+
+    /**
+     * Below are CV correlation feature related stats.
+     * This feature is used for DL MU MIMO, but is not available
+     * from certain legacy targets.
+     */
+
+    /** number of CV Correlation triggers for online mode */
+    A_UINT32 cv_corr_trigger_online_mode;
+    /** number of CV Correlation triggers for offline mode */
+    A_UINT32 cv_corr_trigger_offline_mode;
+    /** number of CV Correlation triggers for hybrid mode */
+    A_UINT32 cv_corr_trigger_hybrid_mode;
+    /** number of CV Correlation triggers with computation level 0 */
+    A_UINT32 cv_corr_trigger_computation_level_0;
+    /** number of CV Correlation triggers with computation level 1 */
+    A_UINT32 cv_corr_trigger_computation_level_1;
+    /** number of CV Correlation triggers with computation level 2 */
+    A_UINT32 cv_corr_trigger_computation_level_2;
+    /** number of users for which CV Correlation was triggered */
+    A_UINT32 cv_corr_trigger_num_users[HTT_TX_CV_CORR_MAX_NUM_COLUMNS];
+    /** number of streams for which CV Correlation was triggered */
+    A_UINT32 cv_corr_trigger_num_streams[HTT_TX_CV_CORR_MAX_NUM_COLUMNS];
+    /** number of CV Correlation buffers received through IPC tickle */
+    A_UINT32 cv_corr_upload_total_buf_received;
+    /** number of CV Correlation buffers fed back to the IPC ring */
+    A_UINT32 cv_corr_upload_total_buf_fed_back;
+    /** number of CV Correlation buffers for which processing failed */
+    A_UINT32 cv_corr_upload_total_processing_failed;
+    /**
+     * number of CV Correlation buffers for which processing failed,
+     * due to no users being present in parsed buffer
+     */
+    A_UINT32 cv_corr_upload_failed_total_users_zero;
+    /**
+     * number of CV Correlation buffers for which processing failed,
+     * due to number of users present in parsed buffer exceeded
+     * CV_CORR_MAX_NUM_COLUMNS
+     */
+    A_UINT32 cv_corr_upload_failed_total_users_exceeded;
+    /**
+     * number of CV Correlation buffers for which processing failed,
+     * due to peer pointer for parsed peer not available
+     */
+    A_UINT32 cv_corr_upload_failed_peer_not_found;
+    /**
+     * number of CV Correlation buffers for which processing encountered,
+     * Nss of peer exceeding SCHED_ALGO_MAX_SUPPORTED_MUMIMO_NSS
+     */
+    A_UINT32 cv_corr_upload_user_nss_exceeded;
+    /**
+     * number of CV Correlation buffers for which processing encountered,
+     * invalid reverse look up index for fetching CV correlation results
+     */
+    A_UINT32 cv_corr_upload_invalid_lookup_index;
+    /** number of users present in uploaded CV Correlation results buffer */
+    A_UINT32 cv_corr_upload_total_num_users[HTT_TX_CV_CORR_MAX_NUM_COLUMNS];
+    /** number of streams present in uploaded CV Correlation results buffer */
+    A_UINT32 cv_corr_upload_total_num_streams[HTT_TX_CV_CORR_MAX_NUM_COLUMNS];
 } htt_tx_sounding_stats_tlv;
 
 /* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SOUNDING_INFO
-- 
GitLab


From d45ced86032be4731fd2037fa8306d4fb510e0f3 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sun, 23 Jul 2023 06:01:41 -0700
Subject: [PATCH 023/298] fw-api: CL 23911002 - update fw common interface
 files

Change-Id: I3ade6f49b50bda753436369ea0290c48e49f7cc8
WMI: add ie_data TLV to MGMT_RX_EVENT
CRs-Fixed: 2262693
---
 fw/wmi_tlv_defs.h | 3 ++-
 fw/wmi_version.h  | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 90df76a79e8f..625642da77c0 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -5728,7 +5728,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STA_KICKOUT_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bpcc_bufp, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_is_my_mgmt_frame, my_frame, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_removal_tbtt_count, link_removal_tbtt_count, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_bcast_t2lm_info, mlo_bcast_t2lm_info, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_bcast_t2lm_info, mlo_bcast_t2lm_info, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_RX_EVENTID);
 
 /* Management Rx FW Consumed Event */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 02c7f0567126..674c005579f3 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1370
+#define __WMI_REVISION_ 1371
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 5c4b083b97ae5c90b152fb46a975b80b55dd6455 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Mon, 24 Jul 2023 06:01:46 -0700
Subject: [PATCH 024/298] fw-api: CL 23915932 - update fw common interface
 files

add WMI_PEER_PARAM_DMS_SUPPORT def

Change-Id: I9f950ed25ceac0bae23ca374c33e53c35e266de8
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 2 ++
 fw/wmi_version.h | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 4562ac83526c..d5bbcda18092 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -20227,6 +20227,8 @@ typedef struct {
 
 #define WMI_PEER_FT_ROAMING_PEER_UPDATE                0x29
 
+#define WMI_PEER_PARAM_DMS_SUPPORT                     0x2A
+
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param */
     /** unique id identifying the VDEV, generated by the caller */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 674c005579f3..76f698a42c7a 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1371
+#define __WMI_REVISION_ 1372
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 854ca0a3b9e47b08a0021fad65e171ec09970436 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 25 Jul 2023 06:02:05 -0700
Subject: [PATCH 025/298] fw-api: CL 23933290 - update fw common interface
 files

Change-Id: Ia41a0294a5048451595d6e80e383256d935e9592
WMI: revert recent change of WMI_VDEV_PARAM_CHWIDTH_WITH_NOTIFY interpretation
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 20 +-------------------
 fw/wmi_version.h |  2 +-
 2 files changed, 2 insertions(+), 20 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index d5bbcda18092..3dc40369efa7 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -10572,20 +10572,6 @@ typedef enum {
     WMI_CHAN_WIDTH_MAX,
 } wmi_channel_width;
 
-/* channel width switch type */
-typedef enum {
-    WMI_CHAN_WIDTH_SWITCH_TYPE_TXRX   = 0,
-    WMI_CHAN_WIDTH_SWITCH_TYPE_TXONLY = 1,
-
-    WMI_CHAN_WIDTH_SWITCH_TYPE_MAX,
-} wmi_chan_width_switch_type;
-
-#define WMI_VDEV_CHAN_WIDTH_NOTIFY_GET_CHAN_WIDTH(chwidth_notify)              WMI_GET_BITS(chwidth_notify, 0, 8)
-#define WMI_VDEV_CHAN_WIDTH_NOTIFY_SET_CHAN_WIDTH(chwidth_notify, value)       WMI_SET_BITS(chwidth_notify, 0, 8, value)
-
-#define WMI_VDEV_CHAN_WIDTH_NOTIFY_GET_SWITCH_TYPE(chwidth_notify)             WMI_GET_BITS(chwidth_notify, 8, 2)
-#define WMI_VDEV_CHAN_WIDTH_NOTIFY_SET_SWITCH_TYPE(chwidth_notify, value)      WMI_SET_BITS(chwidth_notify, 8, 2, value)
-
 /* Clear stats */
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_clear_link_stats_cmd_fixed_param */
@@ -18113,11 +18099,7 @@ typedef enum {
      * Please note incase of STA VDEV only BSS peer gets updated,
      * associated TDLS peer bandwidth won't be impacted.
      *
-     * bit 7:0   the updated bandwidth is specified with
-     *           a wmi_channel_width value
-     * bit 9:8   the updated bandwidth switch type is specified with
-     *           a wmi_chan_width_switch_type value
-     * bit 31:10 reserved
+     * The updated bandwidth is specified with a wmi_channel_width value.
      */
     WMI_VDEV_PARAM_CHWIDTH_WITH_NOTIFY,                   /* 0xBA */
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 76f698a42c7a..75634fa185ba 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1372
+#define __WMI_REVISION_ 1373
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 211a65173a1118f0dd60c200661574b6c0d57a47 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 25 Jul 2023 06:03:02 -0700
Subject: [PATCH 026/298] fw-api: CL 23935724 - update fw common interface
 files

HTT stats: add smart basic trigger interval histogram

Change-Id: I3f0d2e53b75914e0ddb257f7e1f27791929bae78
CRs-Fixed: 2262693
---
 fw/htt_stats.h | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 7296a29db63f..68f8a93a5dbc 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -2428,6 +2428,8 @@ typedef enum {
 #define HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS \
     (HTT_STATS_MAX_MUMIMO_GRP_SZ * HTT_STATS_MAX_INVALID_REASON_CODE)
 
+#define HTT_MAX_NUM_SBT_INTR 4
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
 
@@ -2480,6 +2482,19 @@ typedef struct {
     /** 11AX HE MU Standalone Freq. BSRP Trigger completed with error(s) */
     A_UINT32 standalone_ax_bsr_trigger_err[HTT_NUM_AC_WMM];
 /* END DEPRECATED FIELDS */
+    /** smart_basic_trig_sch_histogram:
+     * Count how many times the interval between predictive basic triggers
+     * sent to a given STA based on analysis of that STA's traffic patterns
+     * is within a given range:
+     *
+     * smart_basic_trig_sch_histogram[0]: SBT interval <= 10 ms
+     * smart_basic_trig_sch_histogram[1]: 10 ms < SBT interval <= 20 ms
+     * smart_basic_trig_sch_histogram[2]: 20 ms < SBT interval <= 30 ms
+     * smart_basic_trig_sch_histogram[3]: 30 ms < SBT interval <= 40 ms
+     *
+     * (Smart basic triggers are only used with intervals <= 40 ms.)
+     */
+    A_UINT32 smart_basic_trig_sch_histogram[HTT_MAX_NUM_SBT_INTR];
 } htt_tx_selfgen_cmn_stats_tlv;
 
 typedef struct {
-- 
GitLab


From 57122144ea892ed8b08ecd934d2a42c96bcd8809 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 25 Jul 2023 06:03:57 -0700
Subject: [PATCH 027/298] fw-api: CL 23935730 - update fw common interface
 files

add HTT_RXDATA_ERR_INVALID_PEER def

Change-Id: Ie936cf743ffc196615bea93ba9977c745d8a8073
CRs-Fixed: 2262693
---
 fw/htt.h | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/fw/htt.h b/fw/htt.h
index 37e9514f8014..e19ec757edaf 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -251,9 +251,10 @@
  * 3.123 Add HTT_OPTION_TLV_TCL_METADATA_V21 def.
  * 3.124 Add HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT def.
  * 3.125 Expand fisa_aggr_limit bits in fisa_control_bits_v2.
+ * 3.126 Add HTT_RXDATA_ERR_INVALID_PEER def.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 125
+#define HTT_CURRENT_VERSION_MINOR 126
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -21383,6 +21384,12 @@ typedef enum htt_t2h_rx_data_msdu_err {
      */
     HTT_RXDATA_ERR_ZERO_LEN_MSDU    = 7,
 
+    /* ERR_INVALID_PEER:
+     * FW sets this error flag when MSDU is recived from invalid PEER
+     * HOST decides to send DEAUTH or not, recyles buffer.
+     */
+    HTT_RXDATA_ERR_INVALID_PEER     = 8,
+
     /* add new error codes here */
 
     HTT_RXDATA_ERR_MAX              = 32
-- 
GitLab


From 91137dfaeaaa558e5b630536130669418546040c Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 26 Jul 2023 22:57:57 -0700
Subject: [PATCH 028/298] fw-api: CL 23966557 - update fw common interface
 files

Change-Id: I2d2f51b9378b3758cc1549e88fe139bc07cc1bb4
WMI: add LINK_SWITCH_IN_PROGRESS,UNSUPPORTED_MODE_MLMR ADD_TWT status codes
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 2 ++
 fw/wmi_version.h | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 3dc40369efa7..da1d23624859 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -38459,6 +38459,8 @@ typedef enum _WMI_ADD_TWT_STATUS_T {
     WMI_ADD_TWT_STATUS_DIALOG_ID_BUSY,      /* FW is in the process of handling this dialog */
     WMI_ADD_TWT_STATUS_BTWT_NOT_ENBABLED,   /* Broadcast TWT is not enabled */
     WMI_ADD_TWT_STATUS_RTWT_NOT_ENBABLED,   /* Restricted TWT is not enabled */
+    WMI_ADD_TWT_STATUS_LINK_SWITCH_IN_PROGRESS, /* Link switch is ongoing */
+    WMI_ADD_TWT_STATUS_UNSUPPORTED_MODE_MLMR,   /* Unsupported in MLMR mode */
 } WMI_ADD_TWT_STATUS_T;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 75634fa185ba..23b0ddbc91f3 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1373
+#define __WMI_REVISION_ 1374
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 731781a2458cca0cfa180bc4821b9e7021d7a053 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 28 Jul 2023 02:37:27 -0700
Subject: [PATCH 029/298] fw-api: CL 23981866 - update fw common interface
 files

Change-Id: I62da9d2b25e4904615c3bd06e37291892290018a
WMI: add PDEV_WSI_STATS_INFO_CMD msg def
CRs-Fixed: 2262693
---
 fw/wmi_services.h |  1 +
 fw/wmi_tlv_defs.h |  8 ++++++++
 fw/wmi_unified.h  | 13 +++++++++++++
 fw/wmi_version.h  |  2 +-
 4 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 80e30b975c5d..5f7b6616cd86 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -638,6 +638,7 @@ typedef  enum  {
     WMI_SERVICE_MLO_MODE1_RECOVERY_SUPPORTED = 385, /* Indicate fw support for mlo mode1 recovery */
     WMI_SERVICE_TX_PWR_PER_PPDU_STATS_SUPPORT = 386, /* FW support to check tx power stats per PPDU */
     WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT = 387, /* Indicate FW support to disable wds peer map/unmap events */
+    WMI_SERVICE_PDEV_WSI_STATS_INFO_SUPPORT = 388, /* Support for WSI Stats Info. */
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 625642da77c0..0f6d8929d3e3 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1394,6 +1394,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_nan_oem_data_event_fixed_param,
     WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param,
     WMITLV_TAG_STRUC_wmi_enhanced_aoa_gain_phase_data_hdr,
+    WMITLV_TAG_STRUC_wmi_ctrl_path_sta_rrm_stats_struct,
+    WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -1928,6 +1930,7 @@ typedef enum {
     OP(WMI_MLO_LINK_SET_BSS_PARAMS_CMDID) \
     OP(WMI_MLO_LINK_SWITCH_CONF_CMDID) \
     OP(WMI_NAN_OEM_DATA_CMDID) \
+    OP(WMI_PDEV_WSI_STATS_INFO_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -5455,6 +5458,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_BSS_PARAMS_CMDID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_cnf_fixed_param, wmi_mlo_link_switch_cnf_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SWITCH_CONF_CMDID);
 
+/* WMI CMD used to send WSI stats info. */
+#define WMITLV_TABLE_WMI_PDEV_WSI_STATS_INFO_CMDID(id,op,buf,len) \
+        WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param, wmi_pdev_wsi_stats_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_WSI_STATS_INFO_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index da1d23624859..522d9d9b5be0 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -512,6 +512,8 @@ typedef enum {
     WMI_PDEV_SET_TGTR2P_TABLE_CMDID,
     /* WMI cmd to set RF path for PHY */
     WMI_PDEV_SET_RF_PATH_CMDID,
+    /** WSI stats info WMI command */
+    WMI_PDEV_WSI_STATS_INFO_CMDID,
 
 
     /* VDEV (virtual device) specific commands */
@@ -36822,6 +36824,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID);
         WMI_RETURN_STRING(WMI_MLO_LINK_RECOMMENDATION_CMDID);
         WMI_RETURN_STRING(WMI_NAN_OEM_DATA_CMDID);
+        WMI_RETURN_STRING(WMI_PDEV_WSI_STATS_INFO_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -46401,6 +46404,16 @@ typedef struct {
     A_UINT32 emlsr_pdev_id_map;
 } wmi_aux_dev_capabilities;
 
+typedef struct {
+    /** TLV tag and len; tag equals
+      * WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param
+      */
+    A_UINT32 tlv_header;
+    A_UINT32 pdev_id; /* for identifying the MAC */
+    A_UINT32 wsi_ingress_load_info;
+    A_UINT32 wsi_egress_load_info;
+} wmi_pdev_wsi_stats_info_cmd_fixed_param;
+
 
 
 /* ADD NEW DEFS HERE */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 23b0ddbc91f3..a3ecaa7fe379 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1374
+#define __WMI_REVISION_ 1375
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 5bbd356e5399c3763734c47ad93ed9d82ae1803c Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 28 Jul 2023 02:38:25 -0700
Subject: [PATCH 030/298] fw-api: CL 23981895 - update fw common interface
 files

HTT stats: add IDs for ODD BE OFDMA + MU MIMO stats

Change-Id: I11c26abdf3636a983b1d79d19f228096abc1f8af
CRs-Fixed: 2262693
---
 fw/htt_stats.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 68f8a93a5dbc..650d422b1088 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -555,6 +555,34 @@ enum htt_dbg_ext_stats_type {
      */
     HTT_DBG_CODEL_STATS = 58,
 
+    /** HTT_DBG_ODD_PDEV_BE_TX_MU_OFDMA_STATS
+     * PARAMS:
+     *   - No Params
+     * RESP MSG:
+     *   - htt_tx_pdev_mpdu_stats_tlv
+     */
+    HTT_DBG_ODD_PDEV_BE_TX_MU_OFDMA_STATS = 59,
+
+    /** HTT_DBG_EXT_STATS_PDEV_UL_TRIGGER
+     * PARAMS:
+     *   - No Params
+     * RESP MSG:
+     *   - htt_rx_pdev_be_ul_ofdma_user_stats_tlv
+     */
+    HTT_DBG_ODD_UL_BE_OFDMA_STATS = 60,
+
+    /** HTT_DBG_ODD_BE_TXBF_OFDMA_STATS
+     */
+    HTT_DBG_ODD_BE_TXBF_OFDMA_STATS = 61,
+
+    /** HTT_DBG_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG_STATS
+     * PARAMS:
+     *   - No Params
+     * RESP MSG:
+     *   - htt_rx_pdev_be_ul_ofdma_user_stats_tlv
+     */
+    HTT_DBG_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG_STATS = 62,
+
 
     /* keep this last */
     HTT_DBG_NUM_EXT_STATS = 256,
-- 
GitLab


From e9f199a40290db294c68b6765f1df56fda2e3ca3 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 28 Jul 2023 18:01:34 -0700
Subject: [PATCH 031/298] fw-api: CL 23995783 - update fw common interface
 files

Change-Id: I57fc71c53dbd98420d35e720acf49afc708a9cf4
WMI: add MLD ID bitfield in start_scan_cmd_fixed_param TLV struct
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 8 ++++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 522d9d9b5be0..c00fcf5393a8 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -5594,6 +5594,9 @@ typedef struct {
 /* NOTE: This constant cannot be changed without breaking WMI compatibility */
 #define WMI_IE_BITMAP_SIZE             8
 
+#define WMI_SCAN_MLD_PARAM_MLD_ID_GET(mld_param) WMI_GET_BITS(mld_param, 0, 8)
+#define WMI_SCAN_MLD_PARAM_MLD_ID_SET(mld_param, val) WMI_SET_BITS(mld_param, 0, 8, val)
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_start_scan_cmd_fixed_param */
     /** Scan ID (lower 16 bits) MSB 4 bits is used to identify scan client based on enum WMI_SCAN_CLIENT_ID */
@@ -5685,6 +5688,11 @@ typedef struct {
      * dwell time in msec for 6 GHz channel of spectral scan channel list
      */
     A_UINT32 dwell_time_spectral_ch;
+    /**
+     * B0-B7: mld id to be inserted in ML probe request
+     * B8-B31: reserved
+     */
+    A_UINT32 mld_parameter;
 
 /**
  * TLV (tag length value) parameters follow the scan_cmd
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index a3ecaa7fe379..7b7159003f20 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1375
+#define __WMI_REVISION_ 1376
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 6db4245bf3c60c83dad8e89d07f31127a77f4116 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 29 Jul 2023 06:01:05 -0700
Subject: [PATCH 032/298] fw-api: CL 23998194 - update fw common interface
 files

add WMI_SERVICE_MULTIPLE_RF_PATH_SOC_SUPPORT def

Change-Id: I69e8d8e1bd5a8fda16a6486334aa23e08ceb7976
CRs-Fixed: 2262693
---
 fw/wmi_services.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 5f7b6616cd86..3b2f28904763 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -639,6 +639,7 @@ typedef  enum  {
     WMI_SERVICE_TX_PWR_PER_PPDU_STATS_SUPPORT = 386, /* FW support to check tx power stats per PPDU */
     WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT = 387, /* Indicate FW support to disable wds peer map/unmap events */
     WMI_SERVICE_PDEV_WSI_STATS_INFO_SUPPORT = 388, /* Support for WSI Stats Info. */
+    WMI_SERVICE_MULTIPLE_RF_PATH_SOC_SUPPORT = 389, /* Indicates FW supports Multiple RF Path on SOC Level */
 
     WMI_MAX_EXT2_SERVICE
 
-- 
GitLab


From 3e8b9ccb6648a0971777f53cbf1b7d1c4ef2d210 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Mon, 31 Jul 2023 03:36:03 -0700
Subject: [PATCH 033/298] fw-api: CL 24006951 - update fw common interface
 files

Change-Id: I5d9f4263a88223680b349335c9a89ea79be669c9
WMI: add enhanced_aoa_gain_table_capabilities in SERVICE_READY_EXT2_EVENT msg
CRs-Fixed: 2262693
---
 fw/wmi_tlv_defs.h |  6 ++-
 fw/wmi_unified.h  | 98 +++++++++++++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 104 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 0f6d8929d3e3..50be005e9af5 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1396,6 +1396,8 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_enhanced_aoa_gain_phase_data_hdr,
     WMITLV_TAG_STRUC_wmi_ctrl_path_sta_rrm_stats_struct,
     WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param,
+    WMITLV_TAG_STRUC_wmi_enhanced_aoa_caps_param,
+    WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -5519,7 +5521,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_sw_cal_ver_cap, sw_cal_ver_cap, WMITLV_SIZE_VAR) \
     WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_INT32, A_INT32, hw_tx_power_signed, WMITLV_SIZE_FIX, WMI_HW_TX_POWER_CAPS_MAX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_COEX_FIX_CHANNEL_CAPABILITIES, coex_fix_channel_caps, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_aux_dev_capabilities, aux_dev_caps, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_aux_dev_capabilities, aux_dev_caps, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_caps_param, aoa_caps_param, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_per_band_caps_param, aoa_per_band_caps_param, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID);
 
 #define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index c00fcf5393a8..94a6f819a3fe 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -40597,6 +40597,104 @@ typedef struct {
     };
 } wmi_enhanced_aoa_gain_phase_data_hdr;
 
+typedef enum _WMI_AGC_GAIN_TABLE_IDX {
+    WMI_AGC_DG_TABLE_IDX = 0,
+    WMI_AGC_LG_TABLE_IDX,
+    WMI_AGC_VLG_TABLE_IDX,
+    WMI_AGC_MAX_GAIN_TABLE_IDX = 8,
+} WMI_AGC_GAIN_TABLE_IDX;
+
+#define WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD 4
+#define WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD 2
+#define WMI_AOA_NUM_BYTES_FOR_BDF_GAIN_TBL_ELEM 1
+#define WMI_AOA_NUM_BYTES_FOR_GAIN_TBL_ELEM 2
+
+/* Number of words required to store max number of gain table elements = ((max number of gain table elements)/(number of gain table elements per word)) */
+/* 2 bytes (at most)used to store each gain table elements */
+#define WMI_AOA_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS (WMI_AGC_MAX_GAIN_TABLE_IDX / WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD)
+
+/* 1 byte (at most) used to store each gain table elements obtained from BDF  */
+#define WMI_AOA_BDF_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS (WMI_AGC_MAX_GAIN_TABLE_IDX / WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD)
+
+typedef enum {
+    WMI_AOA_2G = 0,
+    WMI_AOA_5G,
+    WMI_AOA_6G,
+    WMI_AOA_MAX_BAND,
+} WMI_AOA_SUPPORTED_BANDS;
+
+#define WMI_AOA_MAX_AGC_GAIN_GET(pcap_var, tbl_idx, output) \
+    do { \
+        A_UINT8 word_idx = 0; \
+        A_UINT8 bit_index = 0; \
+        A_UINT8 nth_byte = 0; \
+        word_idx = tbl_idx >> 1; \
+        nth_byte = (tbl_idx % WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD); \
+        bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_GAIN_TBL_ELEM; \
+        output = WMI_GET_BITS(*(pcap_var + word_idx), bit_index, 16); \
+    } while (0)
+
+#define WMI_AOA_MAX_AGC_GAIN_SET(pcap_var, tbl_idx, value) \
+    do { \
+        A_UINT8 word_idx = 0; \
+        A_UINT8 bit_index = 0; \
+        A_UINT8 nth_byte = 0; \
+        word_idx = tbl_idx >> 1; \
+        nth_byte = (tbl_idx % WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD); \
+        bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_GAIN_TBL_ELEM; \
+        WMI_SET_BITS(*(pcap_var+word_idx), bit_index, 16, value); \
+    } while (0)
+
+#define WMI_AOA_MAX_BDF_ENTRIES_GET(pcap_var, tbl_idx, output) \
+    do { \
+        A_UINT8 word_idx = 0; \
+        A_UINT8 bit_index = 0; \
+        A_UINT8 nth_byte = 0; \
+        word_idx = tbl_idx >> 2; \
+        nth_byte = (tbl_idx % WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD); \
+        bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_BDF_GAIN_TBL_ELEM; \
+        output = WMI_GET_BITS(*(pcap_var+word_idx), bit_index, 8); \
+    } while (0)
+
+#define WMI_AOA_MAX_BDF_ENTRIES_SET(pcap_var, tbl_idx, value) \
+    do { \
+        A_UINT8 word_idx = 0; \
+        A_UINT8 nth_byte = 0; \
+        A_UINT8 bit_index = 0; \
+        word_idx = tbl_idx >> 2; \
+        nth_byte = (tbl_idx % WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD); \
+        bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_BDF_GAIN_TBL_ELEM; \
+        WMI_SET_BITS(*(pcap_var+word_idx), bit_index, 8, value); \
+    } while (0)
+
+typedef struct {
+    /** TLV tag and len; tag equals
+      * WMITLV_TAG_STRUC_wmi_enhanced_aoa_caps_param */
+    A_UINT32 tlv_header;
+
+    /* Maximum number of Rx AGC gain tables supported */
+    A_UINT32 max_agc_gain_tbls;
+
+    /* 1 byte is used to store bdf max number of elements in each gain tables */
+    A_UINT32 max_bdf_gain_entries[WMI_AOA_BDF_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS];
+
+    /** This TLV is followed by TLV array - wmi_enhanced_aoa_per_band_caps_param
+     * containing band specifc agc gain table information.
+     */
+} wmi_enhanced_aoa_caps_param;
+
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param */
+    A_UINT32 tlv_header;
+
+    /* Band information - WMI_AOA_SUPPORTED_BANDS */
+    A_UINT32 band_info;
+
+    /* 2 bytes are used to store agc max number of elements in each gain tables */
+    A_UINT32 max_agc_gain[WMI_AOA_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS];
+} wmi_enhanced_aoa_per_band_caps_param;
+
 /* WMI_HALPHY_CAL_LIST:
  *
  * Below is the list of HALPHY online CAL currently enabled in
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 7b7159003f20..0512f840d496 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1376
+#define __WMI_REVISION_ 1377
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 6b7badbd8aafb81ec2630831d1378b1fcafce62c Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Wed, 2 Aug 2023 18:01:08 -0700
Subject: [PATCH 034/298] fw-api: CL 24056101 - update fw common interface
 files

Change-Id: Id194f689da1b5b08289705e68bd57efe00cba714
WMI: add recommended_max_num_simultaneous_links for MLO params
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 6 ++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 94a6f819a3fe..eba35f664307 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -20542,6 +20542,9 @@ typedef struct {
     A_UINT32 max_num_simultaneous_links;
     /** NSTR indication bitmap received in assoc req */
     A_UINT32 nstr_indication_bitmap;
+
+    /** max num of active links recommended by AP or applications */
+    A_UINT32 recommended_max_num_simultaneous_links;
 } wmi_peer_assoc_mlo_params;
 
 typedef struct {
@@ -46292,6 +46295,9 @@ typedef struct {
     A_UINT32 tlv_header;
     wmi_mac_addr ap_mld_macaddr;
 
+    /* max num of active links recommended by AP or applications */
+    A_UINT32 recommended_max_num_simultaneous_links;
+
     /*
      * The TLVs listed below follow this fixed_param TLV:
      * wmi_mlo_link_bss_param link_bss_params[]:
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 0512f840d496..482019a67908 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1377
+#define __WMI_REVISION_ 1378
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From f9d60b0c6b22d5907de75a90c520bfc962aeea5f Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 10 Aug 2023 06:02:15 -0700
Subject: [PATCH 035/298] fw-api: CL 24140579 - update fw common interface
 files

Change-Id: Iab6d61dd4d9db60128a9cd32ab883693d9b7d01a
WMI: add radar_flags TLV in PDEV_DFS_RADAR_DETECTION_EVENT msg
CRs-Fixed: 2262693
---
 fw/wmi_services.h |  1 +
 fw/wmi_tlv_defs.h |  4 +++-
 fw/wmi_unified.h  | 39 ++++++++++++++++++++++++++++++++++++++-
 fw/wmi_version.h  |  2 +-
 4 files changed, 43 insertions(+), 3 deletions(-)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 3b2f28904763..9344ceb1fdd1 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -640,6 +640,7 @@ typedef  enum  {
     WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT = 387, /* Indicate FW support to disable wds peer map/unmap events */
     WMI_SERVICE_PDEV_WSI_STATS_INFO_SUPPORT = 388, /* Support for WSI Stats Info. */
     WMI_SERVICE_MULTIPLE_RF_PATH_SOC_SUPPORT = 389, /* Indicates FW supports Multiple RF Path on SOC Level */
+    WMI_SERVICE_RADAR_FLAGS_SUPPORT = 390, /* Indicates FW supports radar flags, such as full bandwidth need put to NOL */
 
     WMI_MAX_EXT2_SERVICE
 
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 50be005e9af5..06ae0217a8a7 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1398,6 +1398,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param,
     WMITLV_TAG_STRUC_wmi_enhanced_aoa_caps_param,
     WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param,
+    WMITLV_TAG_STRUC_WMI_RADAR_FLAGS,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -6255,7 +6256,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_OPER_MODE_CHANGE_EVENTID);
 WMITLV_CREATE_PARAM_STRUC(WMI_DFS_RADAR_EVENTID);
 
 #define WMITLV_TABLE_WMI_PDEV_DFS_RADAR_DETECTION_EVENTID(id,op,buf,len) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_radar_detection_event_fixed_param, wmi_pdev_dfs_radar_detection_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_radar_detection_event_fixed_param, wmi_pdev_dfs_radar_detection_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_RADAR_FLAGS, radar_flags, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DFS_RADAR_DETECTION_EVENTID);
 
 #define WMITLV_TABLE_WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID(id,op,buf,len) \
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index eba35f664307..30395b42f660 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -4591,7 +4591,15 @@ typedef struct {
      *      Refer to the below definitions of the
      *      WMI_RSRC_CFG_HOST_SERVICE_FLAG_BANG_RADAR_320M_SUPPORT_GET
      *      and _SET macros.
-     *  Bits 31:14 - Reserved
+     *  Bit 14
+     *      This bit will be set when host wants to enable/disable
+     *      full BW NOL feature.
+     *      When set to 1: Enable full BW NOL feature.
+     *      When set to 0: Disable the full BW NOL feature.
+     *      Refer to the below definitions of the
+     *      WMI_RSRC_CFG_HOST_SERVICE_FLAG_RADAR_FLAGS_FULL_BW_NOL_GET
+     *      and _SET macros.
+     *  Bits 31:15 - Reserved
      */
     A_UINT32 host_service_flags;
 
@@ -5034,6 +5042,11 @@ typedef struct {
 #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_BANG_RADAR_320M_SUPPORT_SET(host_service_flags, val) \
     WMI_SET_BITS(host_service_flags, 13, 1, val)
 
+#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_RADAR_FLAGS_FULL_BW_NOL_GET(host_service_flags) \
+    WMI_GET_BITS(host_service_flags, 14, 1)
+#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_RADAR_FLAGS_FULL_BW_NOL_SET(host_service_flags, val) \
+    WMI_SET_BITS(host_service_flags, 14, 1, val)
+
 
 #define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_GET(carrier_config) \
     WMI_GET_BITS(carrier_config, 0, 1)
@@ -25558,6 +25571,30 @@ typedef struct {
     A_INT32  sidx; /* segment index (where was the radar within the channel) */
 } wmi_pdev_dfs_radar_detection_event_fixed_param;
 
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_RADAR_FLAGS */
+    /*
+     * Bit 0:
+     *     0 - need check sub channel marking
+     *     1 - full bandwidth need put to NOL
+     *     Refer to WMI_RADAR_FLAGS_FULL_BW_NOL_GET and _SET macros
+     * [1:31] reserved
+     */
+    A_UINT32 flags;
+}  WMI_RADAR_FLAGS;
+
+#define WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS    0
+#define WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS  1
+
+#define WMI_RADAR_FLAGS_FULL_BW_NOL_GET(flag) \
+    WMI_GET_BITS(flag, \
+        WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \
+        WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS)
+#define WMI_RADAR_FLAGS_FULL_BW_NOL_SET(flag, val) \
+    WMI_GET_BITS(flag, \
+        WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \
+        WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS, val)
+
 typedef enum {
     OCAC_COMPLETE = 0,
     OCAC_ABORT,
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 482019a67908..0b8e8d130c23 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1378
+#define __WMI_REVISION_ 1379
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 5ca6a0a0a9b8eb8aac7bcc7caa3c06177cec7702 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 17 Aug 2023 06:01:43 -0700
Subject: [PATCH 036/298] fw-api: CL 24229660 - update fw common interface
 files

Change-Id: Ic61e1b5c7cda7fb7c3614cf586b901aaf72597b0
WMI: specify MLO band of trigger rx + mgmt frm tx
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 60 +++++++++++++++++++++++++++++++++++++++++++++---
 fw/wmi_version.h |  2 +-
 2 files changed, 58 insertions(+), 4 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 30395b42f660..110be780fe0f 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -39528,6 +39528,16 @@ typedef struct {
 #define WMI_GET_BTCONNECT_STATUS(flags)      WMI_GET_BITS(flags, 0, 1)
 #define WMI_SET_BTCONNECT_STATUS(flags, val) WMI_SET_BITS(flags, 0, 1, val)
 
+#define WMI_GET_MLO_BAND(flags)      WMI_GET_BITS(flags, 1, 3)
+#define WMI_SET_MLO_BAND(flags, val) WMI_SET_BITS(flags, 1, 3, val)
+
+typedef enum wmi_mlo_band_info {
+    WMI_MLO_BAND_NO_MLO = 0,
+    WMI_MLO_BAND_2GHZ_MLO,
+    WMI_MLO_BAND_5GHZ_MLO,
+    WMI_MLO_BAND_6GHZ_MLO,
+} wmi_mlo_band_info_t;
+
 typedef struct {
     A_UINT32 tlv_header;     /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_info_tlv_param */
     /* roam_scan_type:
@@ -39551,7 +39561,10 @@ typedef struct {
     /*
      * Flags capturing factors involved during roam scan:
      * Bit 0    : Bluetooth connect status, 0(not connected) or 1(connected).
-     * Bit 1-31 : reserved for future use.
+     * Bit 1-3  : Indicates which link triggered roaming in MLD cases.
+     *            The value is one of the wmi_mlo_band_info_t enum constants.
+     *            Refer to WMI_[GET,SET]_MLO_BAND macros.
+     * Bit 4-31 : reserved for future use.
      */
     A_UINT32 flags;
 } wmi_roam_scan_info;
@@ -39566,6 +39579,9 @@ typedef struct {
                              */
 } wmi_roam_scan_channel_info;
 
+#define WMI_GET_AP_INFO_MLO_STATUS(flags)      WMI_GET_BITS(flags, 0, 1)
+#define WMI_SET_AP_INFO_MLO_STATUS(flags, val) WMI_SET_BITS(flags, 0, 1, val)
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_ap_info_tlv_param */
     /*
@@ -39601,6 +39617,12 @@ typedef struct {
     A_UINT32 bl_timestamp;
     /* Original timeout value in milli seconds when AP added to BL */
     A_UINT32 bl_original_timeout;
+    /* flags:
+     * bit 0:    MLD AP FLAG -> 1: MLD AP, 0: non-MLD AP
+     *           Refer to WMI_[GET,SET]_AP_INFO_MLO_STATUS macros.
+     * bit 1-31: reserved.
+     */
+    A_UINT32 flags;
 } wmi_roam_ap_info;
 
 typedef enum {
@@ -39678,6 +39700,8 @@ typedef struct {
 #define WMI_ROAM_NEIGHBOR_REPORT_INFO_RESPONSE_TOKEN_SET(detail,val)    WMI_SET_BITS(detail, 8, 8, val)
 #define WMI_ROAM_NEIGHBOR_REPORT_INFO_NUM_OF_NRIE_GET(detail)           WMI_GET_BITS(detail, 16, 8)
 #define WMI_ROAM_NEIGHBOR_REPORT_INFO_NUM_OF_NRIE_SET(detail,val)       WMI_SET_BITS(detail, 16, 8, val)
+#define WMI_ROAM_NEIGHBOR_REPORT_INFO_MLO_BAND_INFO_GET(detail)         WMI_GET_BITS(detail, 24, 3)
+#define WMI_ROAM_NEIGHBOR_REPORT_INFO_MLO_BAND_INFO_SET(detail,val)     WMI_SET_BITS(detail, 24, 3, val)
 
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_neighbor_report_info_tlv_param */
@@ -39708,13 +39732,20 @@ typedef struct {
      * [7:0]     : neighbor report request token
      * [15:8]    : neighbor report response token
      * [23:16]   : the number of neighbor report elements in response frame
-     * [31:24]   : reserved
+     * [26:24]   : band on which frame is sent; the value will be one of the
+     *             wmi_mlo_band_info enum constants
+     *             Refer to WMI_ROAM_NEIGHBOR_REPORT_INFO_MLO_BAND_INFO_GET,SET
+     *             macros.
+     * [31:27]   : reserved
      * Refer to the above WMI_ROAM_NEIGHBOR_REPORT_INFO_*_GET,_SET macros for
      * reading and writing these bitfields.
      */
     A_UINT32 neighbor_report_detail;
 } wmi_roam_neighbor_report_info;
 
+#define WMI_ROAM_BTM_RESP_MLO_BAND_INFO_GET(detail)         WMI_GET_BITS(detail, 0, 3)
+#define WMI_ROAM_BTM_RESP_MLO_BAND_INFO_SET(detail,val)     WMI_SET_BITS(detail, 0, 3, val)
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_btm_response_info_tlv_param */
 
@@ -39748,6 +39779,13 @@ typedef struct {
      * that the responding STA requests the BSS to delay termination.
      */
     A_UINT32 btm_resp_bss_termination_delay;
+    /* info:
+     * Bit[0:2]   - band on which frame is sent, band value will be one of the
+     *              wmi_mlo_band_info_t enum constants
+     *              Refer to WMI_ROAM_BTM_RESP_MLO_BAND_INFO_GET,SET macros.
+     * Bit[3:31]  - reserved.
+     */
+    A_UINT32 info;
 } wmi_roam_btm_response_info;
 
 typedef struct {
@@ -39764,6 +39802,15 @@ typedef struct {
 #define WMI_GET_ASSOC_ID(frame_info_ext)      WMI_GET_BITS(frame_info_ext, 0, 16)
 #define WMI_SET_ASSOC_ID(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 0, 16, val)
 
+#define WMI_GET_MLO_BITMAP_BAND_INFO(frame_info_ext)      WMI_GET_BITS(frame_info_ext, 16, 5)
+#define WMI_SET_MLO_BITMAP_BAND_INFO(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 16, 5, val)
+
+#define WMI_GET_RX_INDICATE(frame_info_ext)      WMI_GET_BITS(frame_info_ext, 21, 1)
+#define WMI_SET_RX_INDICATE(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 21, 1, val)
+
+#define WMI_GET_TX_FAILED_REASON(frame_info_ext)         WMI_GET_BITS(frame_info_ext, 22, 4)
+#define WMI_SET_TX_FAILED_REASON(frame_info_ext, val)    WMI_SET_BITS(frame_info_ext, 22, 4, val)
+
 typedef struct {
     A_UINT32 tlv_header;     /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_frame_info_tlv_param */
     /* timestamp is the absolute time w.r.t host timer which is synchronized between the host and target */
@@ -39811,7 +39858,14 @@ typedef struct {
      * frame_info_ext captures below fields:
      * Bit 0-15  : (re)assoc id of (re)association response frame,
      *             section 9.4.1.8 AID field.
-     * Bit 16~31 : reserved for future use.
+     * Bit 16-20 : MLO bitmap band info,
+     *             bit0: 2GHz, bit1: 5GHz, bit2: 6GHz, bits 3-4: reserved
+     *             Refer to WMI_[GET,SET]_MLO_BITMAP_BAND_INFO macros.
+     * Bit 21    : indicate whether this frame is rx :0-not rx; 1-rx
+     *             Refer to WMI_[GET,SET]_RX_INDICATE macros.
+     * Bit 22-25 : opaque tx failure reason
+     *             Refer to WMI_[GET,SET]_TX_FAILED_REASON macros.
+     * Bit 26-31 : reserved for future use.
      */
     A_UINT32 frame_info_ext;
 } wmi_roam_frame_info;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 0b8e8d130c23..1c802447006d 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1379
+#define __WMI_REVISION_ 1380
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From eb237421bd403f197629ef3a8dc242d5c802274f Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 18 Aug 2023 06:01:23 -0700
Subject: [PATCH 037/298] fw-api: CL 24245865 - update fw common interface
 files

HTT stats: add pre_rx_frame_usec field in pdev_stats_cca_counters TLV

Change-Id: If70a821e672537a852659c31dc7c2ce2f40541fa
CRs-Fixed: 2262693
---
 fw/htt_stats.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 650d422b1088..2d9690b8275e 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -6275,6 +6275,7 @@ typedef struct {
     A_UINT32 med_rx_idle_usec;
     A_UINT32 med_tx_idle_global_usec;
     A_UINT32 cca_obss_usec;
+    A_UINT32 pre_rx_frame_usec;
 } htt_pdev_stats_cca_counters_tlv;
 
 /* NOTE: THIS htt_pdev_cca_stats_hist_tlv STRUCTURE IS DEPRECATED,
-- 
GitLab


From 1d3f39feabf2f4b6ff81c3fc4ac9bda397632fd8 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 18 Aug 2023 18:01:09 -0700
Subject: [PATCH 038/298] fw-api: CL 24258897 - update fw common interface
 files

HTT stats: add MLO sched stats

Change-Id: If79724011339c98977c9a79a73398c5402dabe57
CRs-Fixed: 2262693
---
 fw/htt.h       |  1 +
 fw/htt_stats.h | 32 ++++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+)

diff --git a/fw/htt.h b/fw/htt.h
index e19ec757edaf..e1256c8567ce 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -808,6 +808,7 @@ typedef enum {
     HTT_STATS_PDEV_TDMA_TAG                        = 187, /* htt_pdev_tdma_stats_tlv */
     HTT_STATS_CODEL_SVC_CLASS_TAG                  = 188, /* htt_codel_svc_class_stats_tlv */
     HTT_STATS_CODEL_MSDUQ_TAG                      = 189, /* htt_codel_msduq_stats_tlv */
+    HTT_STATS_MLO_SCHED_STATS_TAG                  = 190, /* htt_mlo_sched_stats_tlv */
 
 
     HTT_STATS_MAX_TAG,
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 2d9690b8275e..bc2dbce2eafc 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -583,6 +583,14 @@ enum htt_dbg_ext_stats_type {
      */
     HTT_DBG_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG_STATS = 62,
 
+    /** HTT_DBG_MLO_SCHED_STATS
+     * PARAMS:
+     *    - No Params
+     * RESP MSG:
+     *    - htt_dbg_mlo_sched_stats_tlv
+     */
+    HTT_DBG_MLO_SCHED_STATS = 63,
+
 
     /* keep this last */
     HTT_DBG_NUM_EXT_STATS = 256,
@@ -9764,4 +9772,28 @@ typedef struct {
     };
 } htt_codel_msduq_stats_tlv;
 
+/*===================== start SCHED ALGO + MLO stats ====================*/
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    A_UINT32 pref_link_num_sec_link_sched;
+    A_UINT32 pref_link_num_pref_link_timeout;
+    A_UINT32 pref_link_num_pref_link_sch_delay_ipc;
+    A_UINT32 pref_link_num_pref_link_timeout_ipc;
+} htt_mlo_sched_stats_tlv;
+
+/* STATS_TYPE : HTT_DBG_MLO_SCHED_STATS
+ * TLV_TAGS:
+ *   - HTT_STATS_MLO_SCHED_STATS_TAG
+ */
+/* NOTE:
+ * This structure is for documentation, and cannot be safely used directly.
+ * Instead, use the constituent TLV structures to fill/parse.
+ */
+typedef struct _htt_mlo_sched_stats {
+    htt_mlo_sched_stats_tlv  preferred_link_stats;
+} htt_mlo_sched_stats_t;
+
+/*===================== end SCHED ALGO + MLO stats ======================*/
+
 #endif /* __HTT_STATS_H__ */
-- 
GitLab


From d868e3af1058d1a834a9823f6893e02f0de8de72 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 22 Aug 2023 07:06:02 -0700
Subject: [PATCH 039/298] fw-api: CL 24263097 - update fw common interface
 files

WMI: add optional cqi_meta_data in PDEV_DMA_RING_BUF_RELEASE_EVENT msg
Change-Id: Ieebc6f3ca7e488406e19f195ae57bdd309d233ec
CRs-Fixed: 2262693
---
 fw/wmi_tlv_defs.h |   4 +-
 fw/wmi_unified.h  | 104 +++++++++++++++++++++++++++++++++++-----------
 fw/wmi_version.h  |   2 +-
 3 files changed, 84 insertions(+), 26 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 06ae0217a8a7..5d050bacecdf 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1399,6 +1399,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_enhanced_aoa_caps_param,
     WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param,
     WMITLV_TAG_STRUC_WMI_RADAR_FLAGS,
+    WMITLV_TAG_STRUC_wmi_dma_buf_release_cqi_upload_meta_data,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -7011,7 +7012,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_CFG_RSP_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dma_buf_release_fixed_param, wmi_dma_buf_release_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_entry, entries, WMITLV_SIZE_VAR) \
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_spectral_meta_data, meta_data, WMITLV_SIZE_VAR) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cv_upload_meta_data, cv_meta_data, WMITLV_SIZE_VAR)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cv_upload_meta_data, cv_meta_data, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cqi_upload_meta_data, cqi_meta_data, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID);
 
 /* ctl failsafe check event */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 110be780fe0f..4d41520d973a 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -98,6 +98,8 @@ extern "C" {
 
 #define WMI_MAX_PN_LEN 8
 
+#define MAX_NUM_CQI_USERS_IN_STANDALONE_SND 3
+
 /*
  * These don't necessarily belong here; but as the MS/SM macros require
  * ar6000_internal.h to be included, it may not be defined as yet.
@@ -38900,6 +38902,8 @@ typedef struct {
      * wmi_dma_buf_release_entry entries[num_buf_release_entry];
      * wmi_dma_buf_release_spectral_meta_data meta_datat[num_meta_data_entry];
      * wmi_dma_buf_release_cv_upload_meta_data cv_meta_data[num_meta_data_entry]
+     * wmi_dma_buf_release_cqi_upload_meta_data
+     *     cqi_meta_data[num_meta_data_entry]
      */
 } wmi_dma_buf_release_fixed_param;
 
@@ -46097,6 +46101,9 @@ typedef struct {
 } wmi_vdev_set_manual_su_trig_cmd_fixed_param;
 
 
+#define CQI_UPLOAD_META_DATA_NC_IDX(idx) \
+    (MAX_NUM_CQI_USERS_IN_STANDALONE_SND + (idx * 2))
+
 #define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_ASNR_LENGTH(asnr_params, value) \
         WMI_SET_BITS(asnr_params, 0, 16, value)
 #define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_ASNR_LENGTH(asnr_params) \
@@ -46127,26 +46134,46 @@ typedef struct {
 #define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_FB_PARAMS_NSS_NUM(fb_params) \
         WMI_GET_BITS(fb_params, 2, 2)
 
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_DDR_BUF_IDX(ddr_buffer_idx, value) \
+        WMI_SET_BITS(ddr_buffer_idx, 4, 2, value)
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_DDR_BUF_IDX(ddr_buffer_idx) \
+        WMI_GET_BITS(ddr_buffer_idx, 4, 2)
+
 
 #define WMI_SET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params, value) \
-        WMI_SET_BITS(snd_params, 0, 1, value)
+        WMI_SET_BITS(snd_params, 0, 2, value)
 #define WMI_GET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params) \
-        WMI_GET_BITS(snd_params, 0, 1)
+        WMI_GET_BITS(snd_params, 0, 2)
 
 #define WMI_SET_STANDALONE_SOUND_PARAMS_NG(snd_params, value) \
-        WMI_SET_BITS(snd_params, 1, 2, value)
+        WMI_SET_BITS(snd_params, 2, 2, value)
 #define WMI_GET_STANDALONE_SOUND_PARAMS_NG(snd_params) \
-        WMI_GET_BITS(snd_params, 1, 2)
+        WMI_GET_BITS(snd_params, 2, 2)
 
 #define WMI_SET_STANDALONE_SOUND_PARAMS_CB(snd_params, value) \
-        WMI_SET_BITS(snd_params, 3, 1, value)
+        WMI_SET_BITS(snd_params, 4, 1, value)
 #define WMI_GET_STANDALONE_SOUND_PARAMS_CB(snd_params) \
-        WMI_GET_BITS(snd_params, 3, 1)
+        WMI_GET_BITS(snd_params, 4, 1)
 
 #define WMI_SET_STANDALONE_SOUND_PARAMS_BW(snd_params, value) \
-        WMI_SET_BITS(snd_params, 4, 3, value)
+        WMI_SET_BITS(snd_params, 5, 3, value)
 #define WMI_GET_STANDALONE_SOUND_PARAMS_BW(snd_params) \
-        WMI_GET_BITS(snd_params, 4, 3)
+        WMI_GET_BITS(snd_params, 5, 3)
+
+#define WMI_SET_STANDALONE_SOUND_PARAMS_CQI_TYPE(snd_params, value) \
+        WMI_SET_BITS(snd_params, 8, 1, value)
+#define WMI_GET_STANDALONE_SOUND_PARAMS_CQI_TYPE(snd_params) \
+        WMI_GET_BITS(snd_params, 8, 1)
+
+#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_SET_FB_PARAMS_IS_VALID(fb_params_cqi, value, idx) \
+        WMI_SET_BITS(fb_params_cqi, idx, 1, value)
+#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_GET_FB_PARAMS_IS_VALID(fb_params_cqi, idx) \
+        WMI_GET_BITS(fb_params_cqi, idx, 1)
+
+#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_SET_FB_PARAMS_NC(fb_params_cqi, value, idx) \
+        WMI_SET_BITS(fb_params_cqi, CQI_UPLOAD_META_DATA_NC_IDX(idx), 2, value)
+#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_GET_FB_PARAMS_NC(fb_params_cqi, idx) \
+        WMI_GET_BITS(fb_params_cqi, CQI_UPLOAD_META_DATA_NC_IDX(idx), 2)
 
 
 typedef enum _WMI_STANDALONE_SOUND_STATUS_T {
@@ -46183,34 +46210,63 @@ typedef struct {
     /**
     * [1:0] Nc
     * [3:2] nss_num
+    * [4:5] ddr_buffer_idx
     */
-    A_UINT32 fb_params;
+    A_UINT32 fb_params:       4,
+             ddr_buffer_idx:  2,
+             reserved:       26;
 } wmi_dma_buf_release_cv_upload_meta_data;
 
+typedef struct {
+    /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_dma_buf_release_cqi_upload_meta_data */
+    A_UINT32 tlv_header;
+
+    /**
+     * [15:0] ASNR length
+     * [31:16] ASNR offset
+     */
+    A_UINT32 asnr_params;
+
+    /** Peer mac address */
+    wmi_mac_addr peer_mac_address[MAX_NUM_CQI_USERS_IN_STANDALONE_SND];
+
+    /**
+     * [0] is_user0_valid
+     * [1] is_user1_valid
+     * [2] is_user2_valid
+     * [4:3] User0_Nc
+     * [6:5] User1_Nc
+     * [8:7] User2_Nc
+     */
+    A_UINT32 fb_params_cqi         : 9,
+             reserved              : 23;
+} wmi_dma_buf_release_cqi_upload_meta_data;
+
 typedef struct {
     A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param */
     /** vdev identifier */
     A_UINT32 vdev_id;
     /** sounding_params:
-    * [0] Feedback type
-    * [2:1] Ng
-    * [3] Codebook
-    * [6:4] BW
-    *     0 = 20 MHz
-    *     1 = 40 MHz
-    *     2 = 80 MHz
-    *     3 = 160 MHz
-    *     4 = 320 MHz
-    * [31:7] Reserved
-    */
+     * [1:0] Feedback type
+     * [3:2] Ng
+     * [4] Codebook
+     * [7:5] BW
+     *     0 = 20 MHz
+     *     1 = 40 MHz
+     *     2 = 80 MHz
+     *     3 = 160 MHz
+     *     4 = 320 MHz
+     * [8] Triggered/Non-Triggered CQI
+     * [31:9] Reserved
+     */
     A_UINT32 sounding_params;
     /** The number of sounding repeats */
     A_UINT32 num_sounding_repeats;
     /**
-    * TLV (tag length value) parameters follow the
-    * structure. The TLV's are:
-    * wmi_mac_addr peer_list[num_peers];
-    */
+     * TLV (tag length value) parameters follow the
+     * structure. The TLV's are:
+     * wmi_mac_addr peer_list[num_peers];
+     */
 } wmi_standalone_sounding_cmd_fixed_param;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 1c802447006d..caa08f7218ea 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1380
+#define __WMI_REVISION_ 1381
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 222ac4615f138fdc2d72167367cdea9ad0a34e3d Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 22 Aug 2023 07:07:01 -0700
Subject: [PATCH 040/298] fw-api: CL 24263101 - update fw common interface
 files

HTT: add transmit count field in tx_wbm_completion structs
Change-Id: Id32dbf9ea0c17a2c04b490dfa5b1a2173c47d6d3
CRs-Fixed: 2262693
---
 fw/htt.h | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 62 insertions(+), 5 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index e1256c8567ce..f98366326492 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -252,9 +252,10 @@
  * 3.124 Add HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT def.
  * 3.125 Expand fisa_aggr_limit bits in fisa_control_bits_v2.
  * 3.126 Add HTT_RXDATA_ERR_INVALID_PEER def.
+ * 3.127 Add transmit_count fields in htt_tx_wbm_completion_vX structs.
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 126
+#define HTT_CURRENT_VERSION_MINOR 127
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -2878,7 +2879,8 @@ PREPACK struct htt_tx_wbm_completion_v2 {
         tx_status:              4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */
         reinject_reason:        4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */
         exception_frame:        1,
-        rsvd0:                 12, /* For future use */
+        transmit_count:         7, /* Refer to struct wbm_release_ring */
+        rsvd0:                  5, /* For future use */
         used_by_hw4:            1, /* wbm_internal_error bit being used by HW */
         rsvd1:                  1; /* For future use */
     A_UINT32
@@ -2904,6 +2906,8 @@ PREPACK struct htt_tx_wbm_completion_v2 {
 #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S           13
 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_M                 0x00020000
 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S                 17
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M            0x01FC0000
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S            18
 
 /* DWORD 3 */
 #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(_var) \
@@ -2936,6 +2940,16 @@ PREPACK struct htt_tx_wbm_completion_v2 {
          ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S)); \
      } while (0)
 
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_GET(_var) \
+     (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M) >> \
+    HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S)
+
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_SET(_var, _val) \
+     do { \
+         HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT, _val); \
+         ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S)); \
+     } while (0)
+
 /**
  * @brief HTT TX WBM Completion from firmware to host (V3)
  * @details
@@ -2961,7 +2975,8 @@ PREPACK struct htt_tx_wbm_completion_v3 {
     A_UINT32
         reinject_reason:       4,  /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */
         exception_frame:       1,
-        rsvd0:                 27; /* For future use */
+        transmit_count:        7, /* Refer to struct wbm_release_ring */
+        rsvd0:                 20; /* For future use */
     A_UINT32
         data0:                 32; /* data0,1 and 2 changes based on tx_status type
                                     * if HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP
@@ -2978,13 +2993,17 @@ PREPACK struct htt_tx_wbm_completion_v3 {
         used_by_hw4:           12; /* Refer to struct wbm_release_ring */
 } POSTPACK;
 
-
+/* DWORD 3 */
 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_M                 0x0001E000
 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S                 13
+
+/* DWORD 4 */
 #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_M           0x0000000F
 #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S           0
 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_M                 0x00000010
 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S                 4
+#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M            0x00000FE0
+#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S            5
 
 
 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(_var) \
@@ -3017,6 +3036,16 @@ PREPACK struct htt_tx_wbm_completion_v3 {
          ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S)); \
      } while (0)
 
+#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_GET(_var) \
+    (((_var) & HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M) >> \
+    HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S)
+
+#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_SET(_var, _val) \
+     do { \
+         HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT, _val); \
+         ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S)); \
+     } while (0)
+
 
 typedef enum {
     TX_FRAME_TYPE_UNDEFINED = 0,
@@ -3057,7 +3086,11 @@ PREPACK struct htt_tx_wbm_transmit_status {
                               * contains valid data.
                               */
        frame_type:       4,  /* holds htt_tx_wbm_status_frame_type value */
-       reserved:         4;
+       transmit_count_valid: 1, /* If this "transmit_count_valid" is set, the
+                                 * transmit_count field in struct
+                                 * htt_tx_wbm_completion_vx has valid data.
+                                 */
+       reserved:         3;
    A_UINT32
        ppdu_start_tsf:  32;  /* PPDU Start timestamp added for multicast
                               * packets in the wbm completion path
@@ -3081,6 +3114,10 @@ PREPACK struct htt_tx_wbm_transmit_status {
 #define HTT_TX_WBM_COMPLETION_V2_MCAST_S               22
 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_M         0x00800000
 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S         23
+#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M          0x0F000000
+#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S          24
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M  0x10000000
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S  28
 
 /* DWORD 4 */
 #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(_var) \
@@ -3154,6 +3191,26 @@ PREPACK struct htt_tx_wbm_transmit_status {
          ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S)); \
      } while (0)
 
+#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_GET(_var) \
+    (((_var) & HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M) >> \
+    HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S)
+
+#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_SET(_var, _val) \
+     do { \
+         HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE, _val); \
+         ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S)); \
+
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_GET(_var) \
+    (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M) >> \
+    HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S)
+
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_SET(_var, _val) \
+     do { \
+         HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST_VALID, _val); \
+         ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S)); \
+     } while (0)
+
+
 /**
  * @brief HTT TX WBM reinject status from firmware to host
  * @details
-- 
GitLab


From c4506fca7375b53d13164122b91cbbffd3268a8e Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 22 Aug 2023 07:08:12 -0700
Subject: [PATCH 041/298] fw-api: CL 24269688 - update fw common interface
 files

HTT: add H2T TX_LATENCY_STATS_CFG def
Change-Id: I66bb997d9aa5a5e1b938f0bba89a34fdcc15c4e2
CRs-Fixed: 2262693
---
 fw/htt.h | 224 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 223 insertions(+), 1 deletion(-)

diff --git a/fw/htt.h b/fw/htt.h
index f98366326492..84a9619bf2bb 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -253,9 +253,11 @@
  * 3.125 Expand fisa_aggr_limit bits in fisa_control_bits_v2.
  * 3.126 Add HTT_RXDATA_ERR_INVALID_PEER def.
  * 3.127 Add transmit_count fields in htt_tx_wbm_completion_vX structs.
+ * 3.128 Add H2T TX_LATENCY_STATS_CFG + T2H TX_LATENCY_STATS_PERIODIC_IND
+ *       msg defs
  */
 #define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 127
+#define HTT_CURRENT_VERSION_MINOR 128
 
 #define HTT_NUM_TX_FRAG_DESC  1024
 
@@ -882,6 +884,7 @@ enum htt_h2t_msg_type {
     HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET = 0x22,
     HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23,
     HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP = 0x24,
+    HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG  = 0x25,
 
     /* keep this last */
     HTT_H2T_NUM_MSGS
@@ -10773,6 +10776,88 @@ typedef struct {
         } while (0)
 
 
+/**
+ * @brief host -> tgt msg to configure params for PPDU tx latency stats report
+ *
+ * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG
+ *
+ * @details
+ *    HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG message is sent by the host to
+ *    configure the parameters needed for FW to report PPDU tx latency stats
+ *    for latency prediction in user space.
+ *
+ *    The message would appear as follows:
+ *    |31       28|27               12|11|10    8|7            0|
+ *    |-----------+-------------------+--+-------+--------------|
+ *    |granularity| periodic interval | E|vdev ID|   msg type   |
+ *    |-----------+-------------------+--+-------+--------------|
+ * Where: E = enable
+ *
+ * The message is interpreted as follows:
+ * dword0 - b'0:7   - msg_type: This will be set to 0x25
+ *                    (HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG)
+ *          b'8:10  - vdev_id: Indicate which vdev is configuration is for
+ *          b'11    - enable:  Indicate this message is to enable/disable
+ *                    PPDU latency report from FW
+ *          b'12:27 - periodic_interval: Indicate the report interval in MS
+ *          b'28:31 - granularity: Indicate the granularity of the latency
+ *                    stats report, in ms
+ */
+
+/* HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG */
+PREPACK struct htt_h2t_tx_latency_stats_cfg {
+    A_UINT32 msg_type          :8,
+             vdev_id           :3,
+             enable            :1,
+             periodic_interval :16,
+             granularity       :4;
+} POSTPACK;
+
+#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M                       0x00000700
+#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S                       8
+#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_GET(_var) \
+        (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M) >> \
+                HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S)
+#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_SET(_var, _val) \
+    do {                                                     \
+        HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID, _val);  \
+        ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S)); \
+    } while (0)
+
+#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M                        0x00000800
+#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S                        11
+#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_GET(_var) \
+        (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M) >> \
+                HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S)
+#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_SET(_var, _val) \
+    do {                                                     \
+        HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE, _val);  \
+        ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S)); \
+    } while (0)
+
+#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M             0x0FFFF000
+#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S             12
+#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_GET(_var) \
+        (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M) >> \
+                HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S)
+#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_SET(_var, _val) \
+    do {                                                     \
+        HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL, _val);  \
+        ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S)); \
+    } while (0)
+
+#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M                   0xF0000000
+#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S                   28
+#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_GET(_var) \
+        (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M) >> \
+                HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S)
+#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_SET(_var, _val) \
+    do {                                                     \
+        HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY, _val);  \
+        ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S)); \
+    } while (0)
+
+
 
 /*=== target -> host messages ===============================================*/
 
@@ -10843,6 +10928,7 @@ enum htt_t2h_msg_type {
     HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND = 0x37,
     HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND   = 0x38,
     HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT           = 0x39,
+    HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND = 0x3a,
 
 
     HTT_T2H_MSG_TYPE_TEST,
@@ -21990,5 +22076,141 @@ typedef struct {
 #define HTT_PEER_AST_OVERRIDE_INDEX_IND_BYTES             16
 
 
+/**
+ * @brief target -> periodic report of tx latency to host
+ *
+ * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND
+ *
+ * @details
+ * The message starts with a message header followed by one or more
+ * htt_t2h_peer_tx_latency_stats structs, one for each peer within the vdev.
+ * After each upload, these tx latency stats will be reset.
+ *
+ *      |31        24|23        16|15 14|13 10|9 8|7        0|
+ *      +-------------------------+-----+-----+---+----------|
+ * hdr  |            |pyld elem sz|     |  GR | P | msg type |
+ *-    -|=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-|
+ * pyld |                        peer ID                     |
+ *      |----------------------------------------------------|
+ *      |                   peer_tx_latency[0]               |
+ *      |----------------------------------------------------|
+ * 1st  |                   peer_tx_latency[1]               |
+ * peer |----------------------------------------------------|
+ *      |                   peer_tx_latency[2]               |
+ *      |----------------------------------------------------|
+ *      |                   peer_tx_latency[3]               |
+ *      |----------------------------------------------------|
+ *      |                      avg latency                   |
+ *      |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-|
+ *      |                        peer ID                     |
+ *      |----------------------------------------------------|
+ *      |                   peer_tx_latency[0]               |
+ *      |----------------------------------------------------|
+ * 2nd  |                   peer_tx_latency[1]               |
+ * peer |----------------------------------------------------|
+ *      |                   peer_tx_latency[2]               |
+ *      |----------------------------------------------------|
+ *      |                   peer_tx_latency[3]               |
+ *      |----------------------------------------------------|
+ *      |                      avg latency                   |
+ *      |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-|
+ * Where:
+ *     P  = pdev ID
+ *     GR = granularity
+ *
+ * @details
+ * htt_t2h_tx_latency_stats_periodic_hdr_t:
+ *   - msg_type
+ *     Bits 7:0
+ *     Purpose: identifies this as a tx latency report message
+ *     Value: 0x3a (HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND)
+ *   - pdev_id
+ *     Bits 9:8
+ *     Purpose: Indicates which pdev this message is associated with.
+ *   - granularity
+ *     Bits 13:10
+ *     Purpose: specifies the granulairty of each tx latency bucket in MS.
+ *         There are 4 buckets in total. E.g. if granularity is set to 5 ms,
+ *         then the ranges for the 4 latency histogram buckets will be
+ *         0-5ms, 5ms-10ms, 10ms-15ms, 15ms-max, respectively.
+ *   - payload_elem_size
+ *     Bits 23:16
+ *     Purpose: specifies the size of each element within the msg's payload
+ *         In other words, this field specified the value of
+ *         sizeof(htt_t2h_peer_tx_latency_stats) based on the target's
+ *         revision of the htt_t2h_peer_tx_latency_stats definition.
+ *         If the payload_elem_size reported in the message exceeds the
+ *         sizeof(htt_t2h_peer_tx_latency_stats) based on the host's
+ *         revision of the htt_t2h_peer_tx_latency_stats definition,
+ *         the host shall ignore the excess data.
+ *         Conversely, if the payload_elem_size reported in the message is
+ *         less than sizeof(htt_t2h_peer_tx_latency_stats) based on the host's
+ *         revision of the htt_t2h_peer_tx_latency_stats definition,
+ *         the host shall use 0x0 values for the portion of the data not
+ *         provided by the target.
+ *         The host can compare the payload_elem_size to the total size of
+ *         the message minus the size of the message header to determine
+ *         how many peer payload elements are present in the message.
+ *   - sw_peer_id
+ *     Purpose: The peer to which the following stats belong
+ *   - peer_tx_latency
+ *     Purpose: tx latency histogram for this peer, with 4 buckets whose
+ *         size (in milliseconds) is specified by the granularity field
+ *   - avg_latency
+ *     Purpose: average tx latency (in ms) for this peer in this report interval
+*/
+typedef struct {
+    A_UINT32 msg_type:          8,
+             pdev_id:           2,
+             granularity:       4,
+             reserved1:         2,
+             payload_elem_size: 8,
+             reserved2:         8;
+} htt_t2h_tx_latency_stats_periodic_hdr_t;
+
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_HDR_SIZE \
+    (sizeof(htt_t2h_tx_latency_stats_periodic_hdr_t))
+#define HTT_PEER_TX_LATENCY_REPORT_BINS 4
+
+typedef struct _htt_tx_latency_stats {
+    A_UINT32 peer_id;
+    A_UINT32 peer_tx_latency[HTT_PEER_TX_LATENCY_REPORT_BINS];
+    A_UINT32 avg_latency;
+} htt_t2h_peer_tx_latency_stats;
+
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M              0x00000300
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S              8
+
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_GET(_var) \
+    (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S)
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_SET(_var, _val) \
+    do {                                                   \
+        HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID, _val);  \
+        ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S)); \
+    } while (0)
+
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M          0x00003C00
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S          10
+
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_GET(_var) \
+    (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S)
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_SET(_var, _val) \
+    do {                                                   \
+        HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY, _val);  \
+        ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S)); \
+    } while (0)
+
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M    0xFFFFC000
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S    14
+
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_GET(_var) \
+    (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S)
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_SET(_var, _val) \
+    do {                                                   \
+        HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE, _val);  \
+        ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S)); \
+    } while (0)
+
+
 
 #endif
-- 
GitLab


From b948f690568d19f25cc41c1e5718a9e25fa9b715 Mon Sep 17 00:00:00 2001
From: Soumya Managoli <quic_c_smanag@quicinc.com>
Date: Wed, 13 Sep 2023 10:22:00 +0530
Subject: [PATCH 042/298] dsp: Correct copyright info

Correct the copyright info.

Change-Id: I9a023165deb1e6daccd3813a83500057e255b89a
Signed-off-by: Soumya Managoli <quic_c_smanag@quicinc.com>
---
 dsp/msm_audio_ion.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/dsp/msm_audio_ion.c b/dsp/msm_audio_ion.c
index af30856a9840..a60d31391938 100644
--- a/dsp/msm_audio_ion.c
+++ b/dsp/msm_audio_ion.c
@@ -1,12 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
-<<<<<<< HEAD   (df9a24 dsp: q6lsm: Add check for payload buffer)
  * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
-=======
- * Copyright (c) 2013-2019, 2020, The Linux Foundation. All rights reserved.
- *
  * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
->>>>>>> CHANGE (b0c91b dsp: add lock in ion free to avoid use after free)
  */
 
 #include <linux/init.h>
-- 
GitLab


From 1c307a4d600d6b73b79ca1a425fdd9a2e242404a Mon Sep 17 00:00:00 2001
From: Ravi Kumar Bokka <quic_c_rbokka@quicinc.com>
Date: Tue, 5 Sep 2023 14:05:00 +0530
Subject: [PATCH 043/298] securemsm-kernel: Fix multiple listener registration
 on same fd

Currently, multiple listeners can register on same fd which
could lead to potential vulnerabilities of use after free
while unregistering the listener. Add check to prevent more
than one listener registration on a fd.

Change-Id: Ia2973853943b5619bcf2047629b9c193f6a8c5cf
Signed-off-by: Pawan Rai <quic_pawarai@quicinc.com>
Signed-off-by: Ravi Kumar Bokka <quic_c_rbokka@quicinc.com>
---
 drivers/misc/qseecom.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c
index 0c5dfee9b71a..d7e8e349862c 100644
--- a/drivers/misc/qseecom.c
+++ b/drivers/misc/qseecom.c
@@ -3,7 +3,7 @@
  * QTI Secure Execution Environment Communicator (QSEECOM) driver
  *
  * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #define pr_fmt(fmt) "QSEECOM: %s: " fmt, __func__
@@ -375,7 +375,7 @@ struct qseecom_client_handle {
 
 struct qseecom_listener_handle {
 	u32               id;
-	bool              unregister_pending;
+	bool              register_pending;
 	bool              release_called;
 };
 
@@ -1525,6 +1525,11 @@ static int qseecom_register_listener(struct qseecom_dev_handle *data,
 	struct qseecom_registered_listener_list *new_entry;
 	struct qseecom_registered_listener_list *ptr_svc;
 
+	if (data->listener.register_pending) {
+		pr_err("Already a listner registration is in process on this FD\n");
+		return -EINVAL;
+	}
+
 	ret = copy_from_user(&rcvd_lstnr, argp, sizeof(rcvd_lstnr));
 	if (ret) {
 		pr_err("copy_from_user failed\n");
@@ -1534,6 +1539,13 @@ static int qseecom_register_listener(struct qseecom_dev_handle *data,
 			rcvd_lstnr.sb_size))
 		return -EFAULT;
 
+	ptr_svc = __qseecom_find_svc(data->listener.id);
+	if (ptr_svc) {
+		pr_err("Already a listener registered on this data: lid=%d\n",
+			data->listener.id);
+		return -EINVAL;
+	}
+
 	ptr_svc = __qseecom_find_svc(rcvd_lstnr.listener_id);
 	if (ptr_svc) {
 		if (!ptr_svc->unregister_pending) {
@@ -1577,13 +1589,16 @@ static int qseecom_register_listener(struct qseecom_dev_handle *data,
 	new_entry->svc.listener_id = rcvd_lstnr.listener_id;
 	new_entry->sb_length = rcvd_lstnr.sb_size;
 	new_entry->user_virt_sb_base = rcvd_lstnr.virt_sb_base;
+	data->listener.register_pending = true;
 	if (__qseecom_set_sb_memory(new_entry, data, &rcvd_lstnr)) {
 		pr_err("qseecom_set_sb_memory failed for listener %d, size %d\n",
 				rcvd_lstnr.listener_id, rcvd_lstnr.sb_size);
 		__qseecom_free_tzbuf(&new_entry->sglistinfo_shm);
 		kzfree(new_entry);
+		data->listener.register_pending = false;
 		return -ENOMEM;
 	}
+	data->listener.register_pending = false;
 
 	init_waitqueue_head(&new_entry->rcv_req_wq);
 	init_waitqueue_head(&new_entry->listener_block_app_wq);
-- 
GitLab


From 22a5b9ed3babd4ad364e0236bdcda7eb69013d9b Mon Sep 17 00:00:00 2001
From: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
Date: Thu, 8 Oct 2020 22:37:23 +0900
Subject: [PATCH 044/298] block: ratelimit handle_bad_sector() message

[ Upstream commit f4ac712e4fe009635344b9af5d890fe25fcc8c0d ]

syzbot is reporting unkillable task [1], for the caller is failing to
handle a corrupted filesystem image which attempts to access beyond
the end of the device. While we need to fix the caller, flooding the
console with handle_bad_sector() message is unlikely useful.

[1] https://syzkaller.appspot.com/bug?id=f1f49fb971d7a3e01bd8ab8cff2ff4572ccf3092

Signed-off-by: Tetsuo Handa <penguin-kernel@I-love.SAKURA.ne.jp>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Git-commit: b3a0ed411008c921cc009e5d613f92d6e09bd269
Git-repo: https://android.googlesource.com/kernel/common/
Change-Id: I7ea4c8794a0ad7baeb093b468ba0a49ecfef38af
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
---
 block/blk-core.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/block/blk-core.c b/block/blk-core.c
index d3a6da3012a4..08ef009f28e4 100644
--- a/block/blk-core.c
+++ b/block/blk-core.c
@@ -2133,11 +2133,11 @@ static void handle_bad_sector(struct bio *bio, sector_t maxsector)
 {
 	char b[BDEVNAME_SIZE];
 
-	printk(KERN_INFO "attempt to access beyond end of device\n");
-	printk(KERN_INFO "%s: rw=%d, want=%Lu, limit=%Lu\n",
-			bio_devname(bio, b), bio->bi_opf,
-			(unsigned long long)bio_end_sector(bio),
-			(long long)maxsector);
+	pr_info_ratelimited("attempt to access beyond end of device\n"
+			    "%s: rw=%d, want=%Lu, limit=%Lu\n",
+			    bio_devname(bio, b), bio->bi_opf,
+			    (unsigned long long)bio_end_sector(bio),
+			    (long long)maxsector);
 }
 
 #ifdef CONFIG_FAIL_MAKE_REQUEST
-- 
GitLab


From 2cc80b1e40df4f0d7036d1291975e339b3e4bfd9 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 22 Aug 2023 12:01:27 -0700
Subject: [PATCH 045/298] fw-api: CL 24285962 - update fw common interface
 files

WMI: add SAR version constants
Change-Id: I051d1d418c7198ab774505dc3508d16f00f1c928
CRs-Fixed: 2262693
---
 fw/htt.h         |  4 ++--
 fw/wmi_unified.h | 14 +++++++++++++-
 fw/wmi_version.h |  2 +-
 3 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 84a9619bf2bb..9908951b0dce 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -22200,8 +22200,8 @@ typedef struct _htt_tx_latency_stats {
         ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S)); \
     } while (0)
 
-#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M    0xFFFFC000
-#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S    14
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M    0x00FF0000
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S    16
 
 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_GET(_var) \
     (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S)
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 4d41520d973a..de29b51c350d 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -35845,10 +35845,22 @@ typedef struct {
      **************************************************************************/
 } WMI_OEM_DMA_RING_CAPABILITIES;
 
+typedef enum {
+    WMI_SAR_VERSION_0_ORIGINAL    = 0x00,
+    WMI_SAR_VERSION_1_FULL_TABLE  = 0x01,
+    WMI_SAR_VERSION_2_DBS_SAR     = 0x02,
+    WMI_SAR_VERSION_3_SBS_SAR     = 0x03,
+
+    WMI_SAR_VERSION_SMART_TX      = 0x04,
+    WMI_SAR_VERSION_TAS           = 0x05,
+
+    WMI_SAR_VERSION_INVALID       = 0x80
+} wmi_sar_version_t;
+
 typedef struct {
     A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_SAR_CAPABILITIES*/
     /* sar version in bdf */
-    A_UINT32 active_version;
+    A_UINT32 active_version; /* contains a wmi_sar_version_t value */
 
     /**************************************************************************
      * DON'T ADD ANY FURTHER FIELDS HERE -
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index caa08f7218ea..4dedacedadff 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1381
+#define __WMI_REVISION_ 1382
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 257be38e3e3c5c390a6c2fa9b71b0c46e3d535a1 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Thu, 24 Aug 2023 06:01:15 -0700
Subject: [PATCH 046/298] fw-api: CL 24309540 - update fw common interface
 files

WMI: add CSA_EVENT_STATUS_INDICATION_CMD msg def
Change-Id: If28bf8093085cf7c264a8f573ac539b74880acd2
CRs-Fixed: 2262693
---
 fw/wmi_tlv_defs.h |  7 +++++++
 fw/wmi_unified.h  | 14 ++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 5d050bacecdf..10c0d670f3d5 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1400,6 +1400,7 @@ typedef enum {
     WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param,
     WMITLV_TAG_STRUC_WMI_RADAR_FLAGS,
     WMITLV_TAG_STRUC_wmi_dma_buf_release_cqi_upload_meta_data,
+    WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -1935,6 +1936,7 @@ typedef enum {
     OP(WMI_MLO_LINK_SWITCH_CONF_CMDID) \
     OP(WMI_NAN_OEM_DATA_CMDID) \
     OP(WMI_PDEV_WSI_STATS_INFO_CMDID) \
+    OP(WMI_CSA_EVENT_STATUS_INDICATION_CMDID) \
     /* add new CMD_LIST elements above this line */
 
 
@@ -5467,6 +5469,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SWITCH_CONF_CMDID);
         WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param, wmi_pdev_wsi_stats_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_WSI_STATS_INFO_CMDID);
 
+/* CSA status indication  command to inform FW about host accepting or rejecting csa event*/
+#define WMITLV_TABLE_WMI_CSA_EVENT_STATUS_INDICATION_CMDID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param ,  wmi_csa_event_status_ind_fixed_param,fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_CSA_EVENT_STATUS_INDICATION_CMDID);
+
 
 
 /************************** TLV definitions of WMI events *******************************/
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index de29b51c350d..8254449b11ae 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -627,6 +627,10 @@ typedef enum {
     /** pause vdev's Tx, Rx, or both for a specific duration */
     WMI_VDEV_PAUSE_CMDID,
 
+    /** WMI Command to set status of CSA event from HOST */
+    WMI_CSA_EVENT_STATUS_INDICATION_CMDID,
+
+
     /* peer specific commands */
 
     /** create a peer */
@@ -36887,6 +36891,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
         WMI_RETURN_STRING(WMI_MLO_LINK_RECOMMENDATION_CMDID);
         WMI_RETURN_STRING(WMI_NAN_OEM_DATA_CMDID);
         WMI_RETURN_STRING(WMI_PDEV_WSI_STATS_INFO_CMDID);
+        WMI_RETURN_STRING(WMI_CSA_EVENT_STATUS_INDICATION_CMDID);
     }
 
     return (A_UINT8 *) "Invalid WMI cmd";
@@ -46685,6 +46690,15 @@ typedef struct {
     A_UINT32 wsi_egress_load_info;
 } wmi_pdev_wsi_stats_info_cmd_fixed_param;
 
+typedef struct {
+    /** TLV tag and len; tag equals
+     * WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param
+     */
+    A_UINT32 tlv_header;
+    A_UINT32 vdev_id;
+    A_UINT32 status; /* accept: 1 reject : 0 */
+} wmi_csa_event_status_ind_fixed_param;
+
 
 
 /* ADD NEW DEFS HERE */
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 4dedacedadff..9a9802ad859f 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1382
+#define __WMI_REVISION_ 1383
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 17e9a9cce1fce4081ee7c70143cdf6029a6636bc Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 25 Aug 2023 06:01:21 -0700
Subject: [PATCH 047/298] fw-api: CL 24317964 - update fw common interface
 files

HTT stats: add txbf_ofdma_ineligibility array in pdev_sched_algo_ofdma TLV
Change-Id: I0d3a793b1a94815ff6b74be78d31d38810e42885
CRs-Fixed: 2262693
---
 fw/htt_stats.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index bc2dbce2eafc..afbc25ff59ec 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -8839,6 +8839,18 @@ typedef struct _htt_odd_mandatory_muofdma_pdev_stats_tlv {
         ((_var) |= ((_val) << HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_S)); \
     } while (0)
 
+typedef enum {
+    HTT_STATS_SCHED_OFDMA_TXBF = 0,                                    /* 0 */
+    HTT_STATS_SCHED_OFDMA_TXBF_IS_SANITY_FAILED,                       /* 1 */
+    HTT_STATS_SCHED_OFDMA_TXBF_IS_EBF_ALLOWED_FAILIED,                 /* 2 */
+    HTT_STATS_SCHED_OFDMA_TXBF_RU_ALLOC_BW_DROP_COUNT,                 /* 3 */
+    HTT_STATS_SCHED_OFDMA_TXBF_INVALID_CV_QUERY_COUNT,                 /* 4 */
+    HTT_STATS_SCHED_OFDMA_TXBF_AVG_TXTIME_LESS_THAN_TXBF_SND_THERHOLD, /* 5 */
+    HTT_STATS_SCHED_OFDMA_TXBF_IS_CANDIDATE_KICKED_OUT,                /* 6 */
+    HTT_STATS_SCHED_OFDMA_TXBF_CV_IMAGE_BUF_INVALID,                   /* 7 */
+    HTT_STATS_SCHED_OFDMA_TXBF_INELIGIBILITY_MAX,
+} htt_stats_sched_ofdma_txbf_ineligibility_t;
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
     /**
@@ -8881,6 +8893,7 @@ typedef struct {
     A_UINT32 dlofdma_disabled_consec_no_mpdus_tried[HTT_NUM_AC_WMM];
     /** Num of instances where dl ofdma is disabled because there are consecutive mpdu failure */
     A_UINT32 dlofdma_disabled_consec_no_mpdus_success[HTT_NUM_AC_WMM];
+    A_UINT32 txbf_ofdma_ineligibility_stat[HTT_STATS_SCHED_OFDMA_TXBF_INELIGIBILITY_MAX];
 } htt_pdev_sched_algo_ofdma_stats_tlv;
 
 typedef struct {
-- 
GitLab


From 88452b3c8af793105f77a17fece25aa04dd13cce Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 25 Aug 2023 06:02:35 -0700
Subject: [PATCH 048/298] fw-api: CL 24331558 - update fw common interface
 files

HTT stats: add pdev_mlo_ipc_stats TLV, add fields in rx_pdev_be_ul_trigger
Change-Id: I66f6f53ba035d348879b88f21321998c2adabe3a
CRs-Fixed: 2262693
---
 fw/htt.h       |  1 +
 fw/htt_stats.h | 40 +++++++++++++++++++++++++++++++++++++---
 2 files changed, 38 insertions(+), 3 deletions(-)

diff --git a/fw/htt.h b/fw/htt.h
index 9908951b0dce..0b6c085ad623 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -812,6 +812,7 @@ typedef enum {
     HTT_STATS_CODEL_SVC_CLASS_TAG                  = 188, /* htt_codel_svc_class_stats_tlv */
     HTT_STATS_CODEL_MSDUQ_TAG                      = 189, /* htt_codel_msduq_stats_tlv */
     HTT_STATS_MLO_SCHED_STATS_TAG                  = 190, /* htt_mlo_sched_stats_tlv */
+    HTT_STATS_PDEV_MLO_IPC_STATS_TAG               = 191, /* htt_pdev_mlo_ipc_stats_tlv */
 
 
     HTT_STATS_MAX_TAG,
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index afbc25ff59ec..7305a4a10748 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -587,10 +587,18 @@ enum htt_dbg_ext_stats_type {
      * PARAMS:
      *    - No Params
      * RESP MSG:
-     *    - htt_dbg_mlo_sched_stats_tlv
+     *    - htt_pdev_mlo_sched_stats_tlv
      */
     HTT_DBG_MLO_SCHED_STATS = 63,
 
+    /** HTT_DBG_PDEV_MLO_IPC_STATS
+     * PARAMS:
+     *    - No Params
+     * RESP MSG:
+     *    - htt_pdev_mlo_ipc_stats_tlv
+     */
+    HTT_DBG_PDEV_MLO_IPC_STATS = 64,
+
 
     /* keep this last */
     HTT_DBG_NUM_EXT_STATS = 256,
@@ -5683,6 +5691,12 @@ typedef struct {
      * response to basic trigger. Typically a data response is expected.
      */
     A_UINT32 be_ul_ofdma_basic_trigger_rx_qos_null_only;
+
+    /* UL MLO Queue Depth Sharing Stats */
+    A_UINT32 ul_mlo_send_qdepth_params_count;
+    A_UINT32 ul_mlo_proc_qdepth_params_count;
+    A_UINT32 ul_mlo_proc_accepted_qdepth_params_count;
+    A_UINT32 ul_mlo_proc_discarded_qdepth_params_count;
 } htt_rx_pdev_be_ul_trigger_stats_tlv;
 
 /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS
@@ -9785,7 +9799,7 @@ typedef struct {
     };
 } htt_codel_msduq_stats_tlv;
 
-/*===================== start SCHED ALGO + MLO stats ====================*/
+/*===================== start MLO stats ====================*/
 
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
@@ -9807,6 +9821,26 @@ typedef struct _htt_mlo_sched_stats {
     htt_mlo_sched_stats_tlv  preferred_link_stats;
 } htt_mlo_sched_stats_t;
 
-/*===================== end SCHED ALGO + MLO stats ======================*/
+#define HTT_STATS_HWMLO_MAX_LINKS 6
+#define HTT_STATS_MLO_MAX_IPC_RINGS 7
+
+typedef struct {
+    htt_tlv_hdr_t tlv_hdr;
+    A_UINT32 mlo_ipc_ring_full_cnt[HTT_STATS_HWMLO_MAX_LINKS][HTT_STATS_MLO_MAX_IPC_RINGS];
+} htt_pdev_mlo_ipc_stats_tlv;
+
+/* STATS_TYPE : HTT_DBG_MLO_IPC_STATS
+ * TLV_TAGS:
+ *   - HTT_STATS_PDEV_MLO_IPC_STATS_TAG
+ */
+/* NOTE:
+ * This structure is for documentation, and cannot be safely used directly.
+ * Instead, use the constituent TLV structures to fill/parse.
+ */
+typedef struct _htt_mlo_ipc_stats {
+    htt_pdev_mlo_ipc_stats_tlv  mlo_ipc_stats;
+} htt_pdev_mlo_ipc_stats_t;
+
+/*===================== end MLO stats ======================*/
 
 #endif /* __HTT_STATS_H__ */
-- 
GitLab


From acb137663d86e8843d689ae945cb8fc9095c9d51 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 29 Aug 2023 06:01:39 -0700
Subject: [PATCH 049/298] fw-api: CL 24374793 - update fw common interface
 files

add WMI_MLO_TEARDOWN_REASON_STANDBY_DOWN def

Change-Id: I64446ddbbd75b041b00e4f7ff84d1abf0958273a
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 10 ++++++++--
 fw/wmi_version.h |  2 +-
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 8254449b11ae..f6a8d33a967c 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -44603,8 +44603,14 @@ typedef struct {
 } wmi_mlo_ready_cmd_fixed_param;
 
 typedef enum wmi_mlo_tear_down_reason_code_type {
-    WMI_MLO_TEARDOWN_SSR_REASON,
-    WMI_MLO_TEARDOWN_HOST_INITIATED_REASON,
+    WMI_MLO_TEARDOWN_REASON_SSR,
+        /* keep old name as alias for new name */
+        WMI_MLO_TEARDOWN_SSR_REASON = WMI_MLO_TEARDOWN_REASON_SSR,
+    WMI_MLO_TEARDOWN_REASON_HOST_INITIATED,
+        /* keep old name as alias for new name */
+        WMI_MLO_TEARDOWN_HOST_INITIATED_REASON =
+            WMI_MLO_TEARDOWN_REASON_HOST_INITIATED,
+    WMI_MLO_TEARDOWN_REASON_STANDBY_DOWN,
 } WMI_MLO_TEARDOWN_REASON_TYPE;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 9a9802ad859f..8dd71f75d4f1 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1383
+#define __WMI_REVISION_ 1384
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From cf6c4fc0f0e109ddfd507f874265c6b79055f6b3 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 1 Sep 2023 06:02:20 -0700
Subject: [PATCH 050/298] fw-api: CL 24417305 - update fw common interface
 files

WMI: change ddr_buffer_idx back to a full word in dma_buf_release_cv_upload
Change-Id: I09a727a482f40fbb782672a9c7cca845e23b4be1
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 11 ++++++-----
 fw/wmi_version.h |  2 +-
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index f6a8d33a967c..8246fd4f91e4 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -46230,14 +46230,15 @@ typedef struct {
     A_UINT32 dsnr_params;
     /** Peer mac address */
     wmi_mac_addr peer_mac_address;
-    /**
+    /** fb_params:
     * [1:0] Nc
+    *       Refer to WMI_DMA_BUF_RELEASE_CV_UPLOAD_[SET,GET]_FB_PARAMS_NC
     * [3:2] nss_num
-    * [4:5] ddr_buffer_idx
+    *       Refer to WMI_DMA_BUF_RELEASE_CV_UPLOAD_[SET,GET]_FB_PARAMS_NSS_NUM
+    * [5:4] ddr_buffer_idx
+    *       Refer to WMI_DMA_BUF_RELEASE_CV_UPLOAD_[SET,GET]_DDR_BUF_IDX
     */
-    A_UINT32 fb_params:       4,
-             ddr_buffer_idx:  2,
-             reserved:       26;
+    A_UINT32 fb_params;
 } wmi_dma_buf_release_cv_upload_meta_data;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 8dd71f75d4f1..a19a38c4172f 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1384
+#define __WMI_REVISION_ 1385
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 413535a78d07d392d1dabd641b63a199e3070d62 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 1 Sep 2023 06:03:27 -0700
Subject: [PATCH 051/298] fw-api: CL 24431228 - update fw common interface
 files

add WMI_SERVICE_XPAN_SUPPORT def

Change-Id: I3f72d23c8911cca20dcee672e8e09aad0f22b71e
CRs-Fixed: 2262693
---
 fw/wmi_services.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 9344ceb1fdd1..53be26388e6f 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -641,6 +641,7 @@ typedef  enum  {
     WMI_SERVICE_PDEV_WSI_STATS_INFO_SUPPORT = 388, /* Support for WSI Stats Info. */
     WMI_SERVICE_MULTIPLE_RF_PATH_SOC_SUPPORT = 389, /* Indicates FW supports Multiple RF Path on SOC Level */
     WMI_SERVICE_RADAR_FLAGS_SUPPORT = 390, /* Indicates FW supports radar flags, such as full bandwidth need put to NOL */
+    WMI_SERVICE_XPAN_SUPPORT = 391, /* Indicate FW support XPAN configuration */
 
     WMI_MAX_EXT2_SERVICE
 
-- 
GitLab


From 3fc46d579dcd8d7f826e4811cb4eb05d2113abfe Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 1 Sep 2023 06:04:23 -0700
Subject: [PATCH 052/298] fw-api: CL 24431840 - update fw common interface
 files

WMI: add MLO_LINK_STATE_SWITCH_EVENT msg def
Change-Id: I8077896fbe9511c94021c84b0c92dae64d5d93f7
CRs-Fixed: 2262693
---
 fw/wmi_tlv_defs.h |  9 +++++++++
 fw/wmi_unified.h  | 38 ++++++++++++++++++++++++++++++++++++--
 fw/wmi_version.h  |  2 +-
 3 files changed, 46 insertions(+), 3 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 10c0d670f3d5..cfe418c9a509 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1401,6 +1401,8 @@ typedef enum {
     WMITLV_TAG_STRUC_WMI_RADAR_FLAGS,
     WMITLV_TAG_STRUC_wmi_dma_buf_release_cqi_upload_meta_data,
     WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param,
+    WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_req_evt_fixed_param,
+    WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_trigger_reason_tlv_param,
 } WMITLV_TAG_ID;
 /*
  * IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -2253,6 +2255,7 @@ typedef enum {
     OP(WMI_MLO_LINK_SWITCH_REQUEST_EVENTID) \
     OP(WMI_NAN_OEM_DATA_EVENTID) \
     OP(WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID) \
+    OP(WMI_MLO_LINK_STATE_SWITCH_EVENTID) \
     /* add new EVT_LIST elements above this line */
 
 
@@ -7471,6 +7474,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID);
     WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, aoa_data_buf, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID);
 
+/* MLO Link State Switch Event */
+#define WMITLV_TABLE_WMI_MLO_LINK_STATE_SWITCH_EVENTID(id,op,buf,len) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_req_evt_fixed_param, wmi_mlo_link_state_switch_req_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_state_switch_trigger_reason, switch_trigger_reason, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_STATE_SWITCH_EVENTID);
+
 
 #ifdef __cplusplus
 }
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 8246fd4f91e4..4e4c335104e4 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -2418,6 +2418,8 @@ typedef enum {
     WMI_MLO_LINK_SWITCH_REQUEST_EVENTID,
     /** Response event for WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID */
     WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID,
+    /** WMI Event to spcify reason for link state switch */
+    WMI_MLO_LINK_STATE_SWITCH_EVENTID,
 
     /* WMI event specific to Quiet handling */
     WMI_QUIET_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_QUIET_OFL),
@@ -46512,10 +46514,42 @@ typedef struct {
     A_UINT32 tlv_header;
 
     A_UINT32 vdev_id;
-    A_UINT32 status;  /*see definition of WMI_LINK_SWITCH_CNF_STATUS*/
-    A_UINT32 reason;  /*see definition of WMI_LINK_SWITCH_CNF_REASON*/
+    A_UINT32 status;  /* see definition of WMI_LINK_SWITCH_CNF_STATUS */
+    A_UINT32 reason;  /* see definition of WMI_LINK_SWITCH_CNF_REASON */
 } wmi_mlo_link_switch_cnf_fixed_param;
 
+typedef struct {
+    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_req_evt_fixed_param */
+    A_UINT32 link_state_switch_count; /* Number of link state switch event pending, MAX 5 iteration */
+} wmi_mlo_link_state_switch_req_evt_fixed_param;
+
+typedef struct {
+    A_UINT32 tlv_header;               /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_trigger_reason_tlv_param */
+    A_UINT32 cur_active_ieee_bitmap;   /* current active ieee linkbitmap */
+    A_UINT32 prev_active_ieee_bitmap;  /* previous active iee linkbitmap */
+    A_UINT32 host_ref_fw_timestamp_ms; /* fw time stamp on refrence of TIME_STAMP_SYNC_CMD */
+    A_UINT32 reason_code;              /* reason for link state switch trigger -
+                                        * refer to WMI_LINK_STATE_SWITCH_REASON
+                                        */
+    wmi_mac_addr  ml_bssid;  /* mac address of mld device */
+} wmi_mlo_link_state_switch_trigger_reason;
+
+typedef enum _WMI_LINK_STATE_SWITCH_REASON {
+    WMI_MLO_PS_LINK_STATE_SWITCH_REASON_VDEV_READY = 0,
+    WMI_MLO_PS_LINK_STATE_SWITCH_REASON_ULL_MODE = 1,
+    WMI_MLO_PS_LINK_STATE_SWITCH_REASON_T2LM_ENABLED = 2,
+    WMI_MLO_PS_LINK_STATE_SWITCH_REASON_T2LM_DISABLED = 3,
+    WMI_MLO_PS_LINK_STATE_SWITCH_REASON_FORCE_ENABLED = 4,
+    WMI_MLO_PS_LINK_STATE_SWITCH_REASON_FORCE_DISABLED = 5,
+    WMI_MLO_PS_LINK_STATE_SWITCH_REASON_LINK_QUALITY = 6,
+    WMI_MLO_PS_LINK_STATE_SWITCH_REASON_LINK_CAPACITY = 7,
+    WMI_MLO_PS_LINK_STATE_SWITCH_REASON_RSSI = 8,
+    WMI_MLO_PS_LINK_STATE_SWITCH_REASON_BMISS = 9,
+    WMI_MLO_PS_LINK_STATE_SWITCH_REASON_BT_STATUS = 10,
+
+    WMI_MLO_PS_LINK_STATE_SWITCH_REASON_MAX,
+} WMI_LINK_STATE_SWITCH_REASON;
+
 #define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_ML_PEER_ID_GET(new_link_info) WMI_GET_BITS(new_link_info, 0, 16)
 #define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_ML_PEER_ID_SET(new_link_info, value) WMI_SET_BITS(new_link_info, 0, 16, value)
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index a19a38c4172f..4a8da555633e 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1385
+#define __WMI_REVISION_ 1386
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 450c91974b39e5d79d8a1e6620e897acecc4716a Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sun, 3 Sep 2023 06:05:06 -0700
Subject: [PATCH 053/298] fw-api: CL 24448911 - update fw common interface
 files

add WMI_PDEV_PARAM_SET_SAP_RFA_TOGGLE def

Change-Id: I7044bf142752c815bef6c3deddccf36b1e6ea106
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 3 +++
 fw/wmi_version.h | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 4e4c335104e4..2354601f5158 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -9309,6 +9309,9 @@ typedef enum {
      *   3.  Units are in milli-seconds
      */
     WMI_PDEV_PARAM_ATF_VI_DEDICATED_TIME,
+
+    /** Parameter used for enabling/disabling RFA toggle for SAP mode */
+    WMI_PDEV_PARAM_SET_SAP_RFA_TOGGLE,
 } WMI_PDEV_PARAM;
 
 #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 4a8da555633e..7f6694c479dd 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1386
+#define __WMI_REVISION_ 1387
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From e1d30c9500e386e0be262ef6d642286bdc59fe42 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sun, 10 Sep 2023 06:01:07 -0700
Subject: [PATCH 054/298] fw-api: CL 24528979 - update fw common interface
 files

add WMI_COEX_SET_TRAFFIC_SHAPING_MODE def

Change-Id: I2ad4619251a64984b7b7620d477c319dc4b0fe6d
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 12 ++++++++++++
 fw/wmi_version.h |  2 +-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 2354601f5158..ff2931a0b49d 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -34543,6 +34543,13 @@ typedef enum wmi_coex_config_type {
      * config BT RX PER threshold
      */
     WMI_COEX_CONFIG_BT_RX_PER_THRESHOLD = 49,
+    /* WMI_COEX_SET_TRAFFIC_SHAPING_MODE
+     * arg1: 0 (WMI_COEX_TRAFFIC_SHAPING_MODE_DISABLED)
+     *         Disable coex policies and set fixed arbitration config.
+     *       1 (WMI_COEX_TRAFFIC_SHAPING_MODE_ENABLED)
+     *         Enable all coex policies.
+     */
+    WMI_COEX_SET_TRAFFIC_SHAPING_MODE = 50,
 } WMI_COEX_CONFIG_TYPE;
 
 typedef struct {
@@ -34563,6 +34570,11 @@ typedef enum wmi_coex_dbam_mode_type {
     WMI_COEX_DBAM_FORCED = 2,
 } WMI_COEX_DBAM_MODE_TYPE;
 
+typedef enum {
+    WMI_COEX_TRAFFIC_SHAPING_MODE_DISABLED = 0,
+    WMI_COEX_TRAFFIC_SHAPING_MODE_ENABLED = 1,
+} WMI_COEX_TRAFFIC_SHAPING_MODE;
+
 typedef struct {
     A_UINT32 tlv_header;
     A_UINT32 vdev_id;
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 7f6694c479dd..8918fa58c909 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1387
+#define __WMI_REVISION_ 1388
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From c7f47419021769f5027a8c2dc08d43ced94c4ec2 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Tue, 12 Sep 2023 06:01:15 -0700
Subject: [PATCH 055/298] fw-api: CL 24551836 - update fw common interface
 files

HTT stats: add HTT_CTRL_PATH_STATS_CAL_TYPE enums
Change-Id: I7e140409add047f9af953caa2e89184e3dac00fd
CRs-Fixed: 2262693
---
 fw/htt_stats.h | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 7305a4a10748..fc232a4e903c 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -9843,4 +9843,85 @@ typedef struct _htt_mlo_ipc_stats {
 
 /*===================== end MLO stats ======================*/
 
+typedef enum {
+    HTT_CTRL_PATH_STATS_CAL_TYPE_ADC                     = 0x0,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_DAC                     = 0x1,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_PROCESS                 = 0x2,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR             = 0x3,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO                   = 0x4,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ     = 0x5,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_TXLO                    = 0x6,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_TXIQ                    = 0x7,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_RXIQ                    = 0x8,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_IM2                     = 0x9,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_LNA                     = 0xa,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO            = 0xb,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ             = 0xc,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS          = 0xd,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY              = 0xe,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_IBF                     = 0xf,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL            = 0x10,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ                = 0x11,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM              = 0x12,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL                 = 0x13,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ             = 0x14,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_BWFILTER                = 0x15,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_PEF                     = 0x16,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP                 = 0x17,
+    HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC              = 0x18,
+
+    /* add new cal types above this line */
+    HTT_CTRL_PATH_STATS_CAL_TYPE_INVALID                 = 0xFF
+} htt_ctrl_path_stats_cal_type_ids;
+
+#define HTT_RETURN_STRING(str) case ((str)): return (A_UINT8 *)(# str);
+
+#define HTT_GET_BITS(_val, _index, _num_bits) \
+    (((_val) >> (_index)) & ((1 << (_num_bits)) - 1))
+
+#define HTT_CTRL_PATH_CALIBRATION_STATS_CAL_TYPE_GET(cal_info) \
+    HTT_GET_BITS(cal_info, 0, 8)
+
+/*
+ * Used by some hosts to print names of cal type, based on
+ * htt_ctrl_path_cal_type_ids values specified in
+ * htt_ctrl_path_calibration_stats_struct in ctrl_path_stats event msg.
+ */
+#ifdef HTT_CTRL_PATH_STATS_CAL_TYPE_STRINGS
+static INLINE A_UINT8 *htt_ctrl_path_cal_type_id_to_name(A_UINT32 cal_type_id)
+{
+    switch (cal_type_id)
+    {
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_ADC);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DAC);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PROCESS);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TXLO);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TXIQ);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXIQ);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_IM2);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_LNA);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_IBF);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_BWFILTER);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PEF);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP);
+        HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC);
+    }
+
+    return (A_UINT8 *) "HTT_CTRL_PATH_STATS_CAL_TYPE_UNKNOWN";
+}
+#endif /* HTT_CTRL_PATH_STATS_CAL_TYPE_STRINGS */
+
+
 #endif /* __HTT_STATS_H__ */
-- 
GitLab


From 502351e2bec1705e4299bcbcd740597bbb937876 Mon Sep 17 00:00:00 2001
From: Soumya Managoli <quic_c_smanag@quicinc.com>
Date: Wed, 21 Jun 2023 17:17:03 +0530
Subject: [PATCH 056/298] ASoC: msm-lsm-client: Integer overflow check

Added integer overflow check for lsm_params_get_info size.

Change-Id: I1130b5294f5de65eb8c595030c4db221337b1c8a
Signed-off-by: Soumya Managoli <quic_c_smanag@quicinc.com>
(cherry picked from commit 5473dea653d4dc57c1901479e10a4518dac14229)
---
 asoc/msm-lsm-client.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/asoc/msm-lsm-client.c b/asoc/msm-lsm-client.c
index 43b8dab7cda5..f4a8dbdce4fd 100644
--- a/asoc/msm-lsm-client.c
+++ b/asoc/msm-lsm-client.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 #include <linux/init.h>
 #include <linux/err.h>
@@ -2430,6 +2431,15 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream,
 			err = -EFAULT;
 			goto done;
 		}
+
+		if (temp_p_info.param_size > 0 &&
+			((INT_MAX - sizeof(temp_p_info)) <
+				temp_p_info.param_size)) {
+			pr_err("%s: Integer overflow\n", __func__);
+			err = -EINVAL;
+			goto done;
+		}
+
 		size = sizeof(temp_p_info) + temp_p_info.param_size;
 		p_info = kzalloc(size, GFP_KERNEL);
 
-- 
GitLab


From 24b476d771959257a1e8eeb168a73eab159e0a01 Mon Sep 17 00:00:00 2001
From: Sandhya Mutha Naga Venkata <quic_smuthana@quicinc.com>
Date: Thu, 3 Aug 2023 14:57:16 +0530
Subject: [PATCH 057/298] dsp: q6afe: Add check for fbsp state

Added check for fbsp state in get_calib_data functions
to avoid OOB read issues

Change-Id: I6e818892a6b76497aa41241db3849802f394160a
Signed-off-by: Soumya Managoli <quic_c_smanag@quicinc.com>
(cherry picked from commit 88a57c69ac216868ec15ccdbeee0272fe116b41d)
---
 dsp/q6afe.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/dsp/q6afe.c b/dsp/q6afe.c
index 7f7508fb62a3..a5ac4b094511 100644
--- a/dsp/q6afe.c
+++ b/dsp/q6afe.c
@@ -9611,6 +9611,7 @@ static int afe_spv4_get_calib_data(
 	struct param_hdr_v3 param_hdr;
 	int port = SLIMBUS_4_TX;
 	int ret = -EINVAL;
+	uint32_t th_vi_ca_state;
 
 	if (!calib_resp) {
 		pr_err("%s: Invalid params\n", __func__);
@@ -9632,6 +9633,12 @@ static int afe_spv4_get_calib_data(
 		       __func__, port, param_hdr.param_id, ret);
 		goto get_params_fail;
 	}
+	th_vi_ca_state = this_afe.spv4_calib_data.res_cfg.th_vi_ca_state;
+	if (th_vi_ca_state < FBSP_INCORRECT_OP_MODE ||
+		th_vi_ca_state > MAX_FBSP_STATE) {
+		pr_err("%s: invalid fbsp state %d\n", __func__, th_vi_ca_state);
+		goto get_params_fail;
+	}
 	memcpy(&calib_resp->res_cfg, &this_afe.spv4_calib_data.res_cfg,
 		sizeof(this_afe.calib_data.res_cfg));
 	pr_info("%s: state %s resistance %d %d\n", __func__,
@@ -9650,6 +9657,7 @@ int afe_spk_prot_get_calib_data(struct afe_spkr_prot_get_vi_calib *calib_resp)
 	struct param_hdr_v3 param_hdr;
 	int port = SLIMBUS_4_TX;
 	int ret = -EINVAL;
+	uint32_t th_vi_ca_state;
 
 	if (!calib_resp) {
 		pr_err("%s: Invalid params\n", __func__);
@@ -9671,6 +9679,12 @@ int afe_spk_prot_get_calib_data(struct afe_spkr_prot_get_vi_calib *calib_resp)
 		       __func__, port, param_hdr.param_id, ret);
 		goto get_params_fail;
 	}
+	th_vi_ca_state = this_afe.calib_data.res_cfg.th_vi_ca_state;
+	if (th_vi_ca_state < FBSP_INCORRECT_OP_MODE ||
+		th_vi_ca_state > MAX_FBSP_STATE) {
+		pr_err("%s: invalid fbsp state %d\n", __func__, th_vi_ca_state);
+		goto get_params_fail;
+	}
 	memcpy(&calib_resp->res_cfg, &this_afe.calib_data.res_cfg,
 		sizeof(this_afe.calib_data.res_cfg));
 	pr_info("%s: state %s resistance %d %d\n", __func__,
-- 
GitLab


From 7f9379607fc27dd19d5e964988bc6930407a41af Mon Sep 17 00:00:00 2001
From: Sandhya Mutha Naga Venkata <quic_smuthana@quicinc.com>
Date: Tue, 13 Jun 2023 16:08:57 +0530
Subject: [PATCH 058/298] ASoC: msm-audio-effects-q6-v2: Add BPF order check

Added check for bandpassfilter order in order to avoid
coeff len going out of bounds thereby leading to
memory overflow issues.

Change-Id: I401f5f38a3d54d9d6af66e770d03629ed5e1a2bd
Signed-off-by: Soumya Managoli <quic_c_smanag@quicinc.com>
(cherry picked from commit a225b1346d434fb0ceec5c81718879f402d31373)
(cherry picked from commit 83eea8aa0fd343f103d19168f31314717fa5f3aa)
(cherry picked from commit 2e063ef232cc29c773fab2a1508673bbedf38347)
---
 asoc/msm-audio-effects-q6-v2.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/asoc/msm-audio-effects-q6-v2.c b/asoc/msm-audio-effects-q6-v2.c
index db3bd87ebc0e..f415e699fb43 100644
--- a/asoc/msm-audio-effects-q6-v2.c
+++ b/asoc/msm-audio-effects-q6-v2.c
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/slab.h>
@@ -1002,6 +1003,14 @@ int msm_audio_effects_pbe_handler(struct audio_client *ac,
 			pbe->config.reserved =
 				GET_NEXT(values, param_max_offset, rc);
 
+			if ((pbe->config.bandpass_filter_order > 3) ||
+				(pbe->config.bandpass_filter_order < 1)) {
+				pr_err("%s: Invalid BPF order\n",
+					__func__);
+				rc = -EINVAL;
+				goto invalid_config;
+			}
+
 			p_coeffs = &pbe->config.p1LowPassCoeffs[0];
 			lpf_len = (pbe->config.xover_filter_order == 3) ? 10 : 5;
 			hpf_len = (pbe->config.xover_filter_order == 3) ? 10 : 5;
-- 
GitLab


From b55e526628056e10af83cfc819e32282f259f490 Mon Sep 17 00:00:00 2001
From: Sairam Peri <quic_peri@quicinc.com>
Date: Fri, 4 Aug 2023 14:49:34 +0530
Subject: [PATCH 059/298] dsp: q6asm: Add check for ADSP payload size

There is no check for the ADSP returned payload size
for ASM_SESSION_CMD_GET_MTMX_STRTR_PARAMS_V2 cmd response.
This can lead to buffer overread. Fix is to address this.

Change-Id: I0bd6ee7f19823addc5dde1dfbb32b8a9b102a725
Signed-off-by: Sairam Peri<quic_peri@quicinc.com>
(cherry picked from commit 016b80ca87c3ccf9067e7bde3e4862ccd3724bcf)
---
 dsp/q6asm.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/dsp/q6asm.c b/dsp/q6asm.c
index 4effafb90629..32579d8ead45 100644
--- a/dsp/q6asm.c
+++ b/dsp/q6asm.c
@@ -2405,7 +2405,16 @@ static int32_t q6asm_callback(struct apr_client_data *data, void *priv)
 				__func__, data->payload_size);
 		break;
 	case ASM_SESSION_CMDRSP_GET_MTMX_STRTR_PARAMS_V2:
-		q6asm_process_mtmx_get_param_rsp(ac, (void *) payload);
+		payload_size = sizeof(struct asm_mtmx_strtr_get_params_cmdrsp);
+		if (data->payload_size < payload_size) {
+			pr_err("%s: insufficient payload size = %d\n",
+				__func__, data->payload_size);
+			spin_unlock_irqrestore(
+				&(session[session_id].session_lock), flags);
+			return -EINVAL;
+		}
+		q6asm_process_mtmx_get_param_rsp(ac,
+			(struct asm_mtmx_strtr_get_params_cmdrsp *) payload);
 		break;
 	case ASM_STREAM_PP_EVENT:
 	case ASM_STREAM_CMD_ENCDEC_EVENTS:
-- 
GitLab


From 2d29d9afc7efb53a45926b5f9d2533f511c10dc9 Mon Sep 17 00:00:00 2001
From: Prakash Manjunathappa <quic_prakashp@quicinc.com>
Date: Mon, 19 Dec 2022 13:50:51 -0800
Subject: [PATCH 060/298] fw-api: peach: E3.0: E3R44: WCSS_VERSION 2544 Add
 peach hw header files

Add HW header files to bring-in support for Peach WIFI.

Change-Id: I73ee0a2c4f22a90013b441ecd5e666d673d77ae0
CRs-Fixed: 3580269
---
 hw/peach/v1/HALcomdef.h                       |   49 +
 hw/peach/v1/HALhwio.h                         |  301 +++
 hw/peach/v1/ack_report.h                      |   64 +
 hw/peach/v1/beryllium_top_reg.h               |   23 +
 hw/peach/v1/buffer_addr_info.h                |   57 +
 hw/peach/v1/ce_src_desc.h                     |  134 +
 hw/peach/v1/ce_stat_desc.h                    |  127 +
 hw/peach/v1/coex_rx_status.h                  |  141 +
 hw/peach/v1/coex_tx_req.h                     |  190 ++
 hw/peach/v1/coex_tx_status.h                  |  120 +
 hw/peach/v1/com_dtypes.h                      |  178 ++
 hw/peach/v1/eht_sig_usr_mu_mimo_info.h        |  106 +
 hw/peach/v1/eht_sig_usr_ofdma_info.h          |  120 +
 hw/peach/v1/eht_sig_usr_su_info.h             |   85 +
 hw/peach/v1/expected_response.h               |  204 ++
 hw/peach/v1/he_sig_a_mu_dl_info.h             |  183 ++
 hw/peach/v1/he_sig_a_mu_ul_info.h             |  113 +
 hw/peach/v1/he_sig_a_su_info.h                |  218 ++
 hw/peach/v1/he_sig_b1_mu_info.h               |   50 +
 hw/peach/v1/he_sig_b2_mu_info.h               |  106 +
 hw/peach/v1/he_sig_b2_ofdma_info.h            |  106 +
 hw/peach/v1/ht_sig_info.h                     |  141 +
 hw/peach/v1/l_sig_a_info.h                    |   92 +
 hw/peach/v1/l_sig_b_info.h                    |   57 +
 hw/peach/v1/macrx_abort_request_info.h        |   43 +
 hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h       |   87 +
 hw/peach/v1/mactx_eht_sig_usr_ofdma.h         |   97 +
 hw/peach/v1/mactx_eht_sig_usr_su.h            |   72 +
 hw/peach/v1/mactx_he_sig_a_mu_dl.h            |  142 +
 hw/peach/v1/mactx_he_sig_a_mu_ul.h            |   92 +
 hw/peach/v1/mactx_he_sig_a_su.h               |  167 ++
 hw/peach/v1/mactx_he_sig_b1_mu.h              |   47 +
 hw/peach/v1/mactx_he_sig_b2_mu.h              |   87 +
 hw/peach/v1/mactx_he_sig_b2_ofdma.h           |   87 +
 hw/peach/v1/mactx_ht_sig.h                    |  112 +
 hw/peach/v1/mactx_l_sig_a.h                   |   77 +
 hw/peach/v1/mactx_l_sig_b.h                   |   52 +
 hw/peach/v1/mactx_phy_desc.h                  |  365 +++
 hw/peach/v1/mactx_u_sig_eht_su_mu.h           |  132 +
 hw/peach/v1/mactx_u_sig_eht_tb.h              |  107 +
 hw/peach/v1/mactx_user_desc_common.h          |  478 ++++
 hw/peach/v1/mactx_user_desc_per_user.h        |  190 ++
 hw/peach/v1/mactx_vht_sig_a.h                 |  122 +
 hw/peach/v1/mactx_vht_sig_b_mu160.h           |  192 ++
 hw/peach/v1/mactx_vht_sig_b_mu20.h            |   57 +
 hw/peach/v1/mactx_vht_sig_b_mu40.h            |   77 +
 hw/peach/v1/mactx_vht_sig_b_mu80.h            |  112 +
 hw/peach/v1/mactx_vht_sig_b_su160.h           |  232 ++
 hw/peach/v1/mactx_vht_sig_b_su20.h            |   57 +
 hw/peach/v1/mactx_vht_sig_b_su40.h            |   82 +
 hw/peach/v1/mactx_vht_sig_b_su80.h            |  132 +
 hw/peach/v1/mlo_sta_id_details.h              |   64 +
 hw/peach/v1/mon_buffer_addr.h                 |   78 +
 hw/peach/v1/mon_destination_ring.h            |  106 +
 hw/peach/v1/mon_drop.h                        |   71 +
 hw/peach/v1/mon_ingress_ring.h                |   66 +
 hw/peach/v1/msmhwiobase.h                     |  187 ++
 hw/peach/v1/msmhwioreg.h                      |  112 +
 hw/peach/v1/no_ack_report.h                   |  120 +
 hw/peach/v1/ofdma_trigger_details.h           |  834 ++++++
 hw/peach/v1/pcu_ppdu_setup_init.h             | 2282 +++++++++++++++++
 hw/peach/v1/pdg_response.h                    |  473 ++++
 hw/peach/v1/pdg_response_rate_setting.h       |  414 +++
 hw/peach/v1/pdg_tx_req.h                      |   99 +
 hw/peach/v1/phyrx_abort_request_info.h        |   99 +
 hw/peach/v1/phyrx_common_user_info.h          |  176 ++
 hw/peach/v1/phyrx_he_sig_a_mu_dl.h            |  142 +
 hw/peach/v1/phyrx_he_sig_a_mu_ul.h            |   92 +
 hw/peach/v1/phyrx_he_sig_a_su.h               |  167 ++
 hw/peach/v1/phyrx_he_sig_b1_mu.h              |   47 +
 hw/peach/v1/phyrx_he_sig_b2_mu.h              |   87 +
 hw/peach/v1/phyrx_he_sig_b2_ofdma.h           |   87 +
 hw/peach/v1/phyrx_ht_sig.h                    |  112 +
 hw/peach/v1/phyrx_l_sig_a.h                   |   77 +
 hw/peach/v1/phyrx_l_sig_b.h                   |   52 +
 hw/peach/v1/phyrx_location.h                  |  347 +++
 .../v1/phyrx_other_receive_info_ru_details.h  |   50 +
 hw/peach/v1/phyrx_pkt_end.h                   |  432 ++++
 hw/peach/v1/phyrx_pkt_end_info.h              |  457 ++++
 hw/peach/v1/phyrx_rssi_legacy.h               |  811 ++++++
 hw/peach/v1/phyrx_user_info.h                 |  202 ++
 hw/peach/v1/phyrx_vht_sig_a.h                 |  122 +
 hw/peach/v1/phytx_abort_request_info.h        |   50 +
 hw/peach/v1/phytx_pkt_end.h                   |  241 ++
 hw/peach/v1/phytx_ppdu_header_info_request.h  |   52 +
 hw/peach/v1/receive_pkt_start_info.h          |   99 +
 hw/peach/v1/receive_rssi_info.h               |  477 ++++
 hw/peach/v1/receive_user_info.h               |  269 ++
 hw/peach/v1/received_response_user_15_8.h     | 1126 ++++++++
 hw/peach/v1/received_response_user_23_16.h    | 1126 ++++++++
 hw/peach/v1/received_response_user_31_24.h    | 1126 ++++++++
 hw/peach/v1/received_response_user_36_32.h    |  715 ++++++
 hw/peach/v1/received_response_user_7_0.h      | 1126 ++++++++
 hw/peach/v1/received_response_user_info.h     |  218 ++
 hw/peach/v1/received_trigger_info.h           |  127 +
 hw/peach/v1/received_trigger_info_details.h   |  162 ++
 .../reo_descriptor_threshold_reached_status.h |  274 ++
 hw/peach/v1/reo_destination_ring.h            |  275 ++
 hw/peach/v1/reo_destination_ring_with_pn.h    |  233 ++
 hw/peach/v1/reo_entrance_ring.h               |  252 ++
 hw/peach/v1/reo_flush_cache.h                 |  159 ++
 hw/peach/v1/reo_flush_cache_status.h          |  302 +++
 hw/peach/v1/reo_flush_queue.h                 |  124 +
 hw/peach/v1/reo_flush_queue_status.h          |  246 ++
 hw/peach/v1/reo_flush_timeout_list.h          |  117 +
 hw/peach/v1/reo_flush_timeout_list_status.h   |  260 ++
 hw/peach/v1/reo_get_queue_stats.h             |  117 +
 hw/peach/v1/reo_get_queue_stats_status.h      |  323 +++
 hw/peach/v1/reo_unblock_cache.h               |  117 +
 hw/peach/v1/reo_unblock_cache_status.h        |  253 ++
 hw/peach/v1/reo_update_rx_reo_queue.h         |  425 +++
 hw/peach/v1/reo_update_rx_reo_queue_status.h  |  239 ++
 hw/peach/v1/response_end_status.h             |  294 +++
 hw/peach/v1/response_start_status.h           |   73 +
 hw/peach/v1/ru_allocation_160_info.h          |  127 +
 hw/peach/v1/rx_attention.h                    |  379 +++
 hw/peach/v1/rx_flow_search_entry.h            |  225 ++
 hw/peach/v1/rx_frame_1k_bitmap_ack.h          |  337 +++
 hw/peach/v1/rx_frame_bitmap_ack.h             |  183 ++
 hw/peach/v1/rx_frame_bitmap_req.h             |   78 +
 hw/peach/v1/rx_location_info.h                |  470 ++++
 hw/peach/v1/rx_mpdu_desc_info.h               |  113 +
 hw/peach/v1/rx_mpdu_details.h                 |  115 +
 hw/peach/v1/rx_mpdu_end.h                     |  192 ++
 hw/peach/v1/rx_mpdu_info.h                    |  835 ++++++
 hw/peach/v1/rx_mpdu_link_ptr.h                |   52 +
 hw/peach/v1/rx_mpdu_start.h                   |  617 +++++
 hw/peach/v1/rx_msdu_desc_info.h               |  143 ++
 hw/peach/v1/rx_msdu_details.h                 |  168 ++
 hw/peach/v1/rx_msdu_end.h                     | 1097 ++++++++
 hw/peach/v1/rx_msdu_ext_desc_info.h           |   71 +
 hw/peach/v1/rx_msdu_link.h                    |  917 +++++++
 hw/peach/v1/rx_msdu_start.h                   |  309 +++
 hw/peach/v1/rx_ppdu_ack_report.h              |   57 +
 hw/peach/v1/rx_ppdu_end_user_stats.h          |  703 +++++
 hw/peach/v1/rx_ppdu_end_user_stats_ext.h      |  143 ++
 hw/peach/v1/rx_ppdu_no_ack_report.h           |   97 +
 hw/peach/v1/rx_ppdu_start.h                   |   78 +
 hw/peach/v1/rx_ppdu_start_user_info.h         |  202 ++
 hw/peach/v1/rx_preamble.h                     |   57 +
 hw/peach/v1/rx_reo_queue.h                    |  514 ++++
 hw/peach/v1/rx_reo_queue_1k.h                 |  269 ++
 hw/peach/v1/rx_reo_queue_ext.h                |  390 +++
 hw/peach/v1/rx_response_required_info.h       |  700 +++++
 .../v1/rx_rxpcu_classification_overview.h     |  106 +
 hw/peach/v1/rx_start_param.h                  |   50 +
 hw/peach/v1/rx_timing_info.h                  |   71 +
 hw/peach/v1/rx_trig_info.h                    |   64 +
 hw/peach/v1/rxpcu_early_rx_indication.h       |   64 +
 hw/peach/v1/rxpcu_ppdu_end_info.h             |  861 +++++++
 hw/peach/v1/rxpcu_ppdu_end_layout_info.h      |  332 +++
 hw/peach/v1/rxpt_classify_info.h              |  134 +
 hw/peach/v1/seq_hwio.h                        |   53 +
 hw/peach/v1/tcl_data_cmd.h                    |  290 +++
 hw/peach/v1/tcl_gse_cmd.h                     |  155 ++
 hw/peach/v1/tcl_status_ring.h                 |  141 +
 hw/peach/v1/tlv_hdr.h                         |  416 +++
 hw/peach/v1/tlv_tag_def.h                     |  510 ++++
 hw/peach/v1/tx_cbf_info.h                     |  458 ++++
 hw/peach/v1/tx_fes_setup.h                    |  511 ++++
 hw/peach/v1/tx_fes_status_1k_ba.h             |  323 +++
 hw/peach/v1/tx_fes_status_ack_or_ba.h         |  155 ++
 hw/peach/v1/tx_fes_status_end.h               |  649 +++++
 hw/peach/v1/tx_fes_status_prot.h              |  159 ++
 hw/peach/v1/tx_fes_status_start.h             |  127 +
 hw/peach/v1/tx_fes_status_start_ppdu.h        |  169 ++
 hw/peach/v1/tx_fes_status_start_prot.h        |  162 ++
 hw/peach/v1/tx_fes_status_user_ppdu.h         |  204 ++
 hw/peach/v1/tx_fes_status_user_response.h     |   68 +
 hw/peach/v1/tx_flush_req.h                    |   64 +
 hw/peach/v1/tx_mpdu_start.h                   |  295 +++
 hw/peach/v1/tx_msdu_extension.h               |  372 +++
 hw/peach/v1/tx_msdu_start.h                   |  253 ++
 hw/peach/v1/tx_peer_entry.h                   |  289 +++
 hw/peach/v1/tx_queue_extension.h              |  316 +++
 hw/peach/v1/tx_rate_stats_info.h              |  106 +
 hw/peach/v1/tx_raw_or_native_frame_setup.h    |  274 ++
 hw/peach/v1/txpcu_buffer_basics.h             |   50 +
 hw/peach/v1/txpcu_buffer_status.h             |   68 +
 hw/peach/v1/txpcu_user_buffer_status.h        |   75 +
 hw/peach/v1/u_sig_eht_su_mu_info.h            |  169 ++
 hw/peach/v1/u_sig_eht_tb_info.h               |  134 +
 hw/peach/v1/unallocated_ru_160_info.h         |   57 +
 hw/peach/v1/uniform_descriptor_header.h       |   57 +
 hw/peach/v1/uniform_reo_cmd_header.h          |   50 +
 hw/peach/v1/uniform_reo_status_header.h       |   64 +
 hw/peach/v1/vht_sig_a_info.h                  |  155 ++
 hw/peach/v1/vht_sig_b_mu160_info.h            |  253 ++
 hw/peach/v1/vht_sig_b_mu20_info.h             |   64 +
 hw/peach/v1/vht_sig_b_mu40_info.h             |   92 +
 hw/peach/v1/vht_sig_b_mu80_info.h             |  141 +
 hw/peach/v1/vht_sig_b_su160_info.h            |  309 +++
 hw/peach/v1/vht_sig_b_su20_info.h             |   64 +
 hw/peach/v1/vht_sig_b_su40_info.h             |   99 +
 hw/peach/v1/vht_sig_b_su80_info.h             |  169 ++
 hw/peach/v1/wbm2sw_completion_ring_rx.h       |  301 +++
 hw/peach/v1/wbm2sw_completion_ring_tx.h       |  255 ++
 hw/peach/v1/wbm_buffer_ring.h                 |   52 +
 hw/peach/v1/wbm_link_descriptor_ring.h        |   52 +
 hw/peach/v1/wbm_release_ring.h                |  129 +
 hw/peach/v1/wbm_release_ring_rx.h             |  310 +++
 hw/peach/v1/wbm_release_ring_tx.h             |  271 ++
 hw/peach/v1/wcss_seq_hwiobase.h               |  111 +
 hw/peach/v1/wcss_seq_hwioreg_umac.h           | 2264 ++++++++++++++++
 hw/peach/v1/wcss_version.h                    |   16 +
 205 files changed, 49594 insertions(+)
 create mode 100644 hw/peach/v1/HALcomdef.h
 create mode 100644 hw/peach/v1/HALhwio.h
 create mode 100644 hw/peach/v1/ack_report.h
 create mode 100644 hw/peach/v1/beryllium_top_reg.h
 create mode 100644 hw/peach/v1/buffer_addr_info.h
 create mode 100644 hw/peach/v1/ce_src_desc.h
 create mode 100644 hw/peach/v1/ce_stat_desc.h
 create mode 100644 hw/peach/v1/coex_rx_status.h
 create mode 100644 hw/peach/v1/coex_tx_req.h
 create mode 100644 hw/peach/v1/coex_tx_status.h
 create mode 100644 hw/peach/v1/com_dtypes.h
 create mode 100644 hw/peach/v1/eht_sig_usr_mu_mimo_info.h
 create mode 100644 hw/peach/v1/eht_sig_usr_ofdma_info.h
 create mode 100644 hw/peach/v1/eht_sig_usr_su_info.h
 create mode 100644 hw/peach/v1/expected_response.h
 create mode 100644 hw/peach/v1/he_sig_a_mu_dl_info.h
 create mode 100644 hw/peach/v1/he_sig_a_mu_ul_info.h
 create mode 100644 hw/peach/v1/he_sig_a_su_info.h
 create mode 100644 hw/peach/v1/he_sig_b1_mu_info.h
 create mode 100644 hw/peach/v1/he_sig_b2_mu_info.h
 create mode 100644 hw/peach/v1/he_sig_b2_ofdma_info.h
 create mode 100644 hw/peach/v1/ht_sig_info.h
 create mode 100644 hw/peach/v1/l_sig_a_info.h
 create mode 100644 hw/peach/v1/l_sig_b_info.h
 create mode 100644 hw/peach/v1/macrx_abort_request_info.h
 create mode 100644 hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h
 create mode 100644 hw/peach/v1/mactx_eht_sig_usr_ofdma.h
 create mode 100644 hw/peach/v1/mactx_eht_sig_usr_su.h
 create mode 100644 hw/peach/v1/mactx_he_sig_a_mu_dl.h
 create mode 100644 hw/peach/v1/mactx_he_sig_a_mu_ul.h
 create mode 100644 hw/peach/v1/mactx_he_sig_a_su.h
 create mode 100644 hw/peach/v1/mactx_he_sig_b1_mu.h
 create mode 100644 hw/peach/v1/mactx_he_sig_b2_mu.h
 create mode 100644 hw/peach/v1/mactx_he_sig_b2_ofdma.h
 create mode 100644 hw/peach/v1/mactx_ht_sig.h
 create mode 100644 hw/peach/v1/mactx_l_sig_a.h
 create mode 100644 hw/peach/v1/mactx_l_sig_b.h
 create mode 100644 hw/peach/v1/mactx_phy_desc.h
 create mode 100644 hw/peach/v1/mactx_u_sig_eht_su_mu.h
 create mode 100644 hw/peach/v1/mactx_u_sig_eht_tb.h
 create mode 100644 hw/peach/v1/mactx_user_desc_common.h
 create mode 100644 hw/peach/v1/mactx_user_desc_per_user.h
 create mode 100644 hw/peach/v1/mactx_vht_sig_a.h
 create mode 100644 hw/peach/v1/mactx_vht_sig_b_mu160.h
 create mode 100644 hw/peach/v1/mactx_vht_sig_b_mu20.h
 create mode 100644 hw/peach/v1/mactx_vht_sig_b_mu40.h
 create mode 100644 hw/peach/v1/mactx_vht_sig_b_mu80.h
 create mode 100644 hw/peach/v1/mactx_vht_sig_b_su160.h
 create mode 100644 hw/peach/v1/mactx_vht_sig_b_su20.h
 create mode 100644 hw/peach/v1/mactx_vht_sig_b_su40.h
 create mode 100644 hw/peach/v1/mactx_vht_sig_b_su80.h
 create mode 100644 hw/peach/v1/mlo_sta_id_details.h
 create mode 100644 hw/peach/v1/mon_buffer_addr.h
 create mode 100644 hw/peach/v1/mon_destination_ring.h
 create mode 100644 hw/peach/v1/mon_drop.h
 create mode 100644 hw/peach/v1/mon_ingress_ring.h
 create mode 100644 hw/peach/v1/msmhwiobase.h
 create mode 100644 hw/peach/v1/msmhwioreg.h
 create mode 100644 hw/peach/v1/no_ack_report.h
 create mode 100644 hw/peach/v1/ofdma_trigger_details.h
 create mode 100644 hw/peach/v1/pcu_ppdu_setup_init.h
 create mode 100644 hw/peach/v1/pdg_response.h
 create mode 100644 hw/peach/v1/pdg_response_rate_setting.h
 create mode 100644 hw/peach/v1/pdg_tx_req.h
 create mode 100644 hw/peach/v1/phyrx_abort_request_info.h
 create mode 100644 hw/peach/v1/phyrx_common_user_info.h
 create mode 100644 hw/peach/v1/phyrx_he_sig_a_mu_dl.h
 create mode 100644 hw/peach/v1/phyrx_he_sig_a_mu_ul.h
 create mode 100644 hw/peach/v1/phyrx_he_sig_a_su.h
 create mode 100644 hw/peach/v1/phyrx_he_sig_b1_mu.h
 create mode 100644 hw/peach/v1/phyrx_he_sig_b2_mu.h
 create mode 100644 hw/peach/v1/phyrx_he_sig_b2_ofdma.h
 create mode 100644 hw/peach/v1/phyrx_ht_sig.h
 create mode 100644 hw/peach/v1/phyrx_l_sig_a.h
 create mode 100644 hw/peach/v1/phyrx_l_sig_b.h
 create mode 100644 hw/peach/v1/phyrx_location.h
 create mode 100644 hw/peach/v1/phyrx_other_receive_info_ru_details.h
 create mode 100644 hw/peach/v1/phyrx_pkt_end.h
 create mode 100644 hw/peach/v1/phyrx_pkt_end_info.h
 create mode 100644 hw/peach/v1/phyrx_rssi_legacy.h
 create mode 100644 hw/peach/v1/phyrx_user_info.h
 create mode 100644 hw/peach/v1/phyrx_vht_sig_a.h
 create mode 100644 hw/peach/v1/phytx_abort_request_info.h
 create mode 100644 hw/peach/v1/phytx_pkt_end.h
 create mode 100644 hw/peach/v1/phytx_ppdu_header_info_request.h
 create mode 100644 hw/peach/v1/receive_pkt_start_info.h
 create mode 100644 hw/peach/v1/receive_rssi_info.h
 create mode 100644 hw/peach/v1/receive_user_info.h
 create mode 100644 hw/peach/v1/received_response_user_15_8.h
 create mode 100644 hw/peach/v1/received_response_user_23_16.h
 create mode 100644 hw/peach/v1/received_response_user_31_24.h
 create mode 100644 hw/peach/v1/received_response_user_36_32.h
 create mode 100644 hw/peach/v1/received_response_user_7_0.h
 create mode 100644 hw/peach/v1/received_response_user_info.h
 create mode 100644 hw/peach/v1/received_trigger_info.h
 create mode 100644 hw/peach/v1/received_trigger_info_details.h
 create mode 100644 hw/peach/v1/reo_descriptor_threshold_reached_status.h
 create mode 100644 hw/peach/v1/reo_destination_ring.h
 create mode 100644 hw/peach/v1/reo_destination_ring_with_pn.h
 create mode 100644 hw/peach/v1/reo_entrance_ring.h
 create mode 100644 hw/peach/v1/reo_flush_cache.h
 create mode 100644 hw/peach/v1/reo_flush_cache_status.h
 create mode 100644 hw/peach/v1/reo_flush_queue.h
 create mode 100644 hw/peach/v1/reo_flush_queue_status.h
 create mode 100644 hw/peach/v1/reo_flush_timeout_list.h
 create mode 100644 hw/peach/v1/reo_flush_timeout_list_status.h
 create mode 100644 hw/peach/v1/reo_get_queue_stats.h
 create mode 100644 hw/peach/v1/reo_get_queue_stats_status.h
 create mode 100644 hw/peach/v1/reo_unblock_cache.h
 create mode 100644 hw/peach/v1/reo_unblock_cache_status.h
 create mode 100644 hw/peach/v1/reo_update_rx_reo_queue.h
 create mode 100644 hw/peach/v1/reo_update_rx_reo_queue_status.h
 create mode 100644 hw/peach/v1/response_end_status.h
 create mode 100644 hw/peach/v1/response_start_status.h
 create mode 100644 hw/peach/v1/ru_allocation_160_info.h
 create mode 100644 hw/peach/v1/rx_attention.h
 create mode 100644 hw/peach/v1/rx_flow_search_entry.h
 create mode 100644 hw/peach/v1/rx_frame_1k_bitmap_ack.h
 create mode 100644 hw/peach/v1/rx_frame_bitmap_ack.h
 create mode 100644 hw/peach/v1/rx_frame_bitmap_req.h
 create mode 100644 hw/peach/v1/rx_location_info.h
 create mode 100644 hw/peach/v1/rx_mpdu_desc_info.h
 create mode 100644 hw/peach/v1/rx_mpdu_details.h
 create mode 100644 hw/peach/v1/rx_mpdu_end.h
 create mode 100644 hw/peach/v1/rx_mpdu_info.h
 create mode 100644 hw/peach/v1/rx_mpdu_link_ptr.h
 create mode 100644 hw/peach/v1/rx_mpdu_start.h
 create mode 100644 hw/peach/v1/rx_msdu_desc_info.h
 create mode 100644 hw/peach/v1/rx_msdu_details.h
 create mode 100644 hw/peach/v1/rx_msdu_end.h
 create mode 100644 hw/peach/v1/rx_msdu_ext_desc_info.h
 create mode 100644 hw/peach/v1/rx_msdu_link.h
 create mode 100644 hw/peach/v1/rx_msdu_start.h
 create mode 100644 hw/peach/v1/rx_ppdu_ack_report.h
 create mode 100644 hw/peach/v1/rx_ppdu_end_user_stats.h
 create mode 100644 hw/peach/v1/rx_ppdu_end_user_stats_ext.h
 create mode 100644 hw/peach/v1/rx_ppdu_no_ack_report.h
 create mode 100644 hw/peach/v1/rx_ppdu_start.h
 create mode 100644 hw/peach/v1/rx_ppdu_start_user_info.h
 create mode 100644 hw/peach/v1/rx_preamble.h
 create mode 100644 hw/peach/v1/rx_reo_queue.h
 create mode 100644 hw/peach/v1/rx_reo_queue_1k.h
 create mode 100644 hw/peach/v1/rx_reo_queue_ext.h
 create mode 100644 hw/peach/v1/rx_response_required_info.h
 create mode 100644 hw/peach/v1/rx_rxpcu_classification_overview.h
 create mode 100644 hw/peach/v1/rx_start_param.h
 create mode 100644 hw/peach/v1/rx_timing_info.h
 create mode 100644 hw/peach/v1/rx_trig_info.h
 create mode 100644 hw/peach/v1/rxpcu_early_rx_indication.h
 create mode 100644 hw/peach/v1/rxpcu_ppdu_end_info.h
 create mode 100644 hw/peach/v1/rxpcu_ppdu_end_layout_info.h
 create mode 100644 hw/peach/v1/rxpt_classify_info.h
 create mode 100644 hw/peach/v1/seq_hwio.h
 create mode 100644 hw/peach/v1/tcl_data_cmd.h
 create mode 100644 hw/peach/v1/tcl_gse_cmd.h
 create mode 100644 hw/peach/v1/tcl_status_ring.h
 create mode 100644 hw/peach/v1/tlv_hdr.h
 create mode 100644 hw/peach/v1/tlv_tag_def.h
 create mode 100644 hw/peach/v1/tx_cbf_info.h
 create mode 100644 hw/peach/v1/tx_fes_setup.h
 create mode 100644 hw/peach/v1/tx_fes_status_1k_ba.h
 create mode 100644 hw/peach/v1/tx_fes_status_ack_or_ba.h
 create mode 100644 hw/peach/v1/tx_fes_status_end.h
 create mode 100644 hw/peach/v1/tx_fes_status_prot.h
 create mode 100644 hw/peach/v1/tx_fes_status_start.h
 create mode 100644 hw/peach/v1/tx_fes_status_start_ppdu.h
 create mode 100644 hw/peach/v1/tx_fes_status_start_prot.h
 create mode 100644 hw/peach/v1/tx_fes_status_user_ppdu.h
 create mode 100644 hw/peach/v1/tx_fes_status_user_response.h
 create mode 100644 hw/peach/v1/tx_flush_req.h
 create mode 100644 hw/peach/v1/tx_mpdu_start.h
 create mode 100644 hw/peach/v1/tx_msdu_extension.h
 create mode 100644 hw/peach/v1/tx_msdu_start.h
 create mode 100644 hw/peach/v1/tx_peer_entry.h
 create mode 100644 hw/peach/v1/tx_queue_extension.h
 create mode 100644 hw/peach/v1/tx_rate_stats_info.h
 create mode 100644 hw/peach/v1/tx_raw_or_native_frame_setup.h
 create mode 100644 hw/peach/v1/txpcu_buffer_basics.h
 create mode 100644 hw/peach/v1/txpcu_buffer_status.h
 create mode 100644 hw/peach/v1/txpcu_user_buffer_status.h
 create mode 100644 hw/peach/v1/u_sig_eht_su_mu_info.h
 create mode 100644 hw/peach/v1/u_sig_eht_tb_info.h
 create mode 100644 hw/peach/v1/unallocated_ru_160_info.h
 create mode 100644 hw/peach/v1/uniform_descriptor_header.h
 create mode 100644 hw/peach/v1/uniform_reo_cmd_header.h
 create mode 100644 hw/peach/v1/uniform_reo_status_header.h
 create mode 100644 hw/peach/v1/vht_sig_a_info.h
 create mode 100644 hw/peach/v1/vht_sig_b_mu160_info.h
 create mode 100644 hw/peach/v1/vht_sig_b_mu20_info.h
 create mode 100644 hw/peach/v1/vht_sig_b_mu40_info.h
 create mode 100644 hw/peach/v1/vht_sig_b_mu80_info.h
 create mode 100644 hw/peach/v1/vht_sig_b_su160_info.h
 create mode 100644 hw/peach/v1/vht_sig_b_su20_info.h
 create mode 100644 hw/peach/v1/vht_sig_b_su40_info.h
 create mode 100644 hw/peach/v1/vht_sig_b_su80_info.h
 create mode 100644 hw/peach/v1/wbm2sw_completion_ring_rx.h
 create mode 100644 hw/peach/v1/wbm2sw_completion_ring_tx.h
 create mode 100644 hw/peach/v1/wbm_buffer_ring.h
 create mode 100644 hw/peach/v1/wbm_link_descriptor_ring.h
 create mode 100644 hw/peach/v1/wbm_release_ring.h
 create mode 100644 hw/peach/v1/wbm_release_ring_rx.h
 create mode 100644 hw/peach/v1/wbm_release_ring_tx.h
 create mode 100644 hw/peach/v1/wcss_seq_hwiobase.h
 create mode 100644 hw/peach/v1/wcss_seq_hwioreg_umac.h
 create mode 100644 hw/peach/v1/wcss_version.h

diff --git a/hw/peach/v1/HALcomdef.h b/hw/peach/v1/HALcomdef.h
new file mode 100644
index 000000000000..307eb8d09aa6
--- /dev/null
+++ b/hw/peach/v1/HALcomdef.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef HAL_COMDEF_H
+#define HAL_COMDEF_H
+
+#ifndef _ARM_ASM_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "com_dtypes.h"
+
+#ifndef _BOOL32_DEFINED
+typedef  unsigned long int  bool32;
+#define _BOOL32_DEFINED
+#endif
+
+#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
+
+  #define inp(port)         (*((volatile byte *) (port)))
+  #define inpw(port)        (*((volatile word *) (port)))
+  #define inpdw(port)       (*((volatile dword *)(port)))
+
+  #define outp(port, val)   (*((volatile byte *) (port)) = ((byte) (val)))
+  #define outpw(port, val)  (*((volatile word *) (port)) = ((word) (val)))
+  #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
diff --git a/hw/peach/v1/HALhwio.h b/hw/peach/v1/HALhwio.h
new file mode 100644
index 000000000000..1fce6d0729b2
--- /dev/null
+++ b/hw/peach/v1/HALhwio.h
@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef HAL_HWIO_H
+#define HAL_HWIO_H
+
+#include "HALcomdef.h"
+
+#define HWIO_BASE_PTR(base) base##_BASE_PTR
+
+#ifdef __ARMCC_VERSION
+  #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
+#else
+  #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
+#endif
+
+#define HWIO_ADDR(hwiosym)                               __msmhwio_addr(hwiosym)
+#define HWIO_ADDRI(hwiosym, index)                       __msmhwio_addri(hwiosym, index)
+#define HWIO_ADDRI2(hwiosym, index1, index2)             __msmhwio_addri2(hwiosym, index1, index2)
+#define HWIO_ADDRI3(hwiosym, index1, index2, index3)     __msmhwio_addri3(hwiosym, index1, index2, index3)
+
+#define HWIO_ADDRX(base, hwiosym)                           __msmhwio_addrx(base, hwiosym)
+#define HWIO_ADDRXI(base, hwiosym, index)                   __msmhwio_addrxi(base, hwiosym, index)
+#define HWIO_ADDRXI2(base, hwiosym, index1, index2)         __msmhwio_addrxi2(base, hwiosym, index1, index2)
+#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_PHYS(hwiosym)                               __msmhwio_phys(hwiosym)
+#define HWIO_PHYSI(hwiosym, index)                       __msmhwio_physi(hwiosym, index)
+#define HWIO_PHYSI2(hwiosym, index1, index2)             __msmhwio_physi2(hwiosym, index1, index2)
+#define HWIO_PHYSI3(hwiosym, index1, index2, index3)     __msmhwio_physi3(hwiosym, index1, index2, index3)
+
+#define HWIO_PHYSX(base, hwiosym)                           __msmhwio_physx(base, hwiosym)
+#define HWIO_PHYSXI(base, hwiosym, index)                   __msmhwio_physxi(base, hwiosym, index)
+#define HWIO_PHYSXI2(base, hwiosym, index1, index2)         __msmhwio_physxi2(base, hwiosym, index1, index2)
+#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_OFFS(hwiosym)                               __msmhwio_offs(hwiosym)
+#define HWIO_OFFSI(hwiosym, index)                       __msmhwio_offsi(hwiosym, index)
+#define HWIO_OFFSI2(hwiosym, index1, index2)             __msmhwio_offsi2(hwiosym, index1, index2)
+#define HWIO_OFFSI3(hwiosym, index1, index2, index3)     __msmhwio_offsi3(hwiosym, index1, index2, index3)
+
+#define HWIO_IN(hwiosym)                                         __msmhwio_in(hwiosym)
+#define HWIO_INI(hwiosym, index)                                 __msmhwio_ini(hwiosym, index)
+#define HWIO_INI2(hwiosym, index1, index2)                       __msmhwio_ini2(hwiosym, index1, index2)
+#define HWIO_INI3(hwiosym, index1, index2, index3)               __msmhwio_ini3(hwiosym, index1, index2, index3)
+
+#define HWIO_INM(hwiosym, mask)                                  __msmhwio_inm(hwiosym, mask)
+#define HWIO_INMI(hwiosym, index, mask)                          __msmhwio_inmi(hwiosym, index, mask)
+#define HWIO_INMI2(hwiosym, index1, index2, mask)                __msmhwio_inmi2(hwiosym, index1, index2, mask)
+#define HWIO_INMI3(hwiosym, index1, index2, index3, mask)        __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INF(io, field)                                      (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI(io, index, field)                              (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI2(io, index1, index2, field)                    (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI3(io, index1, index2, index3, field)            (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_INX(base, hwiosym)                                  __msmhwio_inx(base, hwiosym)
+#define HWIO_INXI(base, hwiosym, index)                          __msmhwio_inxi(base, hwiosym, index)
+#define HWIO_INXI2(base, hwiosym, index1, index2)                __msmhwio_inxi2(base, hwiosym, index1, index2)
+#define HWIO_INXI3(base, hwiosym, index1, index2, index3)        __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_INXM(base, hwiosym, mask)                           __msmhwio_inxm(base, hwiosym, mask)
+#define HWIO_INXMI(base, hwiosym, index, mask)                   __msmhwio_inxmi(base, hwiosym, index, mask)
+#define HWIO_INXMI2(base, hwiosym, index1, index2, mask)         __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
+#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INXF(base, io, field)                               (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI(base, io, index, field)                       (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI2(base, io, index1, index2, field)             (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI3(base, io, index1, index2, index3, field)     (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_OUT(hwiosym, val)                                   __msmhwio_out(hwiosym, val)
+#define HWIO_OUTI(hwiosym, index, val)                           __msmhwio_outi(hwiosym, index, val)
+#define HWIO_OUTI2(hwiosym, index1, index2, val)                 __msmhwio_outi2(hwiosym, index1, index2, val)
+#define HWIO_OUTI3(hwiosym, index1, index2, index3, val)         __msmhwio_outi3(hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTM(hwiosym, mask, val)                            __msmhwio_outm(hwiosym, mask, val)
+#define HWIO_OUTMI(hwiosym, index, mask, val)                    __msmhwio_outmi(hwiosym, index, mask, val)
+#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val)          __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
+#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val)  __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTF(io, field, val)                                HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI(io, index, field, val)                        HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI2(io, index1, index2, field, val)              HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI3(io, index1, index2, index3, field, val)      HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTV(io, field, val)                                HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI(io, index, field, val)                        HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI2(io, index1, index2, field, val)              HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI3(io, index1, index2, index3, field, val)      HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTX(base, hwiosym, val)                                   __msmhwio_outx(base, hwiosym, val)
+#define HWIO_OUTXI(base, hwiosym, index, val)                           __msmhwio_outxi(base, hwiosym, index, val)
+#define HWIO_OUTXI2(base, hwiosym, index1, index2, val)                 __msmhwio_outxi2(base, hwiosym, index1, index2, val)
+#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val)         __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTXM(base, hwiosym, mask, val)                            __msmhwio_outxm(base, hwiosym, mask, val)
+#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2)  __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
+#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
+#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
+#define HWIO_OUTXMI(base, hwiosym, index, mask, val)                    __msmhwio_outxmi(base, hwiosym, index, mask, val)
+#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val)          __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
+#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val)  __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTXF(base, io, field, val)                                HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTX2F(base, io, field1, field2, val1, val2)                                HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
+#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3)                                HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
+#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4)                                HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),  HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
+
+#define HWIO_OUTXFI(base, io, index, field, val)                        HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI2(base, io, index1, index2, field, val)              HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val)      HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTXV(base, io, field, val)                                HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI(base, io, index, field, val)                        HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI2(base, io, index1, index2, field, val)              HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val)      HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_RMSK(hwiosym)                               __msmhwio_rmsk(hwiosym)
+#define HWIO_RMSKI(hwiosym, index)                       __msmhwio_rmski(hwiosym, index)
+#define HWIO_RSHFT(hwiosym)                              __msmhwio_rshft(hwiosym)
+#define HWIO_SHFT(hwio_regsym, hwio_fldsym)              __msmhwio_shft(hwio_regsym, hwio_fldsym)
+#define HWIO_FMSK(hwio_regsym, hwio_fldsym)              __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
+#define HWIO_VAL(io, field, val)                         __msmhwio_val(io, field, val)
+#define HWIO_FVAL(io, field, val)                        (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+#define HWIO_FVALV(io, field, val)                       (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+
+#define HWIO_SHDW(hwiosym)                               __msmhwio_shdw(hwiosym)
+#define HWIO_SHDWI(hwiosym, index)                       __msmhwio_shdwi(hwiosym, index)
+
+#define __msmhwio_in(hwiosym)                                   HWIO_##hwiosym##_IN
+#define __msmhwio_ini(hwiosym, index)                           HWIO_##hwiosym##_INI(index)
+#define __msmhwio_ini2(hwiosym, index1, index2)                 HWIO_##hwiosym##_INI2(index1, index2)
+#define __msmhwio_ini3(hwiosym, index1, index2, index3)         HWIO_##hwiosym##_INI3(index1, index2, index3)
+#define __msmhwio_inm(hwiosym, mask)                            HWIO_##hwiosym##_INM(mask)
+#define __msmhwio_inmi(hwiosym, index, mask)                    HWIO_##hwiosym##_INMI(index, mask)
+#define __msmhwio_inmi2(hwiosym, index1, index2, mask)          HWIO_##hwiosym##_INMI2(index1, index2, mask)
+#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)  HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
+#define __msmhwio_out(hwiosym, val)                             HWIO_##hwiosym##_OUT(val)
+#define __msmhwio_outi(hwiosym, index, val)                     HWIO_##hwiosym##_OUTI(index,val)
+#define __msmhwio_outi2(hwiosym, index1, index2, val)           HWIO_##hwiosym##_OUTI2(index1, index2, val)
+#define __msmhwio_outi3(hwiosym, index1, index2, index3, val)   HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
+#define __msmhwio_outm(hwiosym, mask, val)                      HWIO_##hwiosym##_OUTM(mask, val)
+#define __msmhwio_outmi(hwiosym, index, mask, val)              HWIO_##hwiosym##_OUTMI(index, mask, val)
+#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val)        HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
+#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val)  HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
+#define __msmhwio_addr(hwiosym)                                 HWIO_##hwiosym##_ADDR
+#define __msmhwio_addri(hwiosym, index)                         HWIO_##hwiosym##_ADDR(index)
+#define __msmhwio_addri2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_ADDR(idx1, idx2)
+#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
+#define __msmhwio_phys(hwiosym)                                 HWIO_##hwiosym##_PHYS
+#define __msmhwio_physi(hwiosym, index)                         HWIO_##hwiosym##_PHYS(index)
+#define __msmhwio_physi2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_PHYS(idx1, idx2)
+#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
+#define __msmhwio_offs(hwiosym)                                 HWIO_##hwiosym##_OFFS
+#define __msmhwio_offsi(hwiosym, index)                         HWIO_##hwiosym##_OFFS(index)
+#define __msmhwio_offsi2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_OFFS(idx1, idx2)
+#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
+#define __msmhwio_rmsk(hwiosym)                                 HWIO_##hwiosym##_RMSK
+#define __msmhwio_rmski(hwiosym, index)                         HWIO_##hwiosym##_RMSK(index)
+#define __msmhwio_fmsk(hwiosym, hwiofldsym)                     HWIO_##hwiosym##_##hwiofldsym##_BMSK
+#define __msmhwio_rshft(hwiosym)                                HWIO_##hwiosym##_SHFT
+#define __msmhwio_shft(hwiosym, hwiofldsym)                     HWIO_##hwiosym##_##hwiofldsym##_SHFT
+#define __msmhwio_shdw(hwiosym)                                 HWIO_##hwiosym##_shadow
+#define __msmhwio_shdwi(hwiosym, index)                         HWIO_##hwiosym##_SHDW(index)
+#define __msmhwio_val(hwiosym, hwiofld, hwioval)                HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
+
+#define __msmhwio_inx(base, hwiosym)                                  HWIO_##hwiosym##_IN(base)
+#define __msmhwio_inxi(base, hwiosym, index)                          HWIO_##hwiosym##_INI(base, index)
+#define __msmhwio_inxi2(base, hwiosym, index1, index2)                HWIO_##hwiosym##_INI2(base, index1, index2)
+#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3)        HWIO_##hwiosym##_INI3(base, index1, index2, index3)
+#define __msmhwio_inxm(base, hwiosym, mask)                           HWIO_##hwiosym##_INM(base, mask)
+#define __msmhwio_inxmi(base, hwiosym, index, mask)                   HWIO_##hwiosym##_INMI(base, index, mask)
+#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)         HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
+#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
+#define __msmhwio_outx(base, hwiosym, val)                            HWIO_##hwiosym##_OUT(base, val)
+#define __msmhwio_outxi(base, hwiosym, index, val)                    HWIO_##hwiosym##_OUTI(base, index,val)
+#define __msmhwio_outxi2(base, hwiosym, index1, index2, val)          HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
+#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)  HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
+#define __msmhwio_outxm(base, hwiosym, mask, val)                     HWIO_##hwiosym##_OUTM(base, mask, val)
+#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)  { \
+                                                                        static unsigned int   Readdata, Val_temp, Val;\
+									Readdata = HWIO_INX(base, hwiosym); \
+									Val_temp = Readdata & ~mask1 & ~mask2; \
+									Val = Val_temp | val1 | val2; \
+									HWIO_##hwiosym##_OUT(base, Val); \
+									}
+
+#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3,  val1, val2, val3) { \
+                                                                                        static unsigned int   Readdata1, Val_temp1, Val1;\
+			                                                                Readdata1 = HWIO_INX(base, hwiosym); \
+											Val_temp1 = Readdata1 & ~mask1 & ~mask2 & ~mask3; \
+											Val1 = Val_temp1 | val1 | val2 | val3; \
+											HWIO_##hwiosym##_OUT(base, Val1); \
+                                                                               }
+
+#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
+                                                                                        static unsigned int   Readdata2, Val_temp2, Val2;\
+			                                                                Readdata2 = HWIO_INX(base, hwiosym); \
+											Val_temp2 = Readdata2 & ~mask1 & ~mask2 & ~mask3 & ~mask4; \
+											Val2 = Val_temp2 | val1 | val2 | val3 | val4; \
+											HWIO_##hwiosym##_OUT(base, Val2); \
+                                                                               }
+
+#define __msmhwio_outxmi(base, hwiosym, index, mask, val)             HWIO_##hwiosym##_OUTMI(base, index, mask, val)
+#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val)       HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
+#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
+#define __msmhwio_addrx(base, hwiosym)                                HWIO_##hwiosym##_ADDR(base)
+#define __msmhwio_addrxi(base, hwiosym, index)                        HWIO_##hwiosym##_ADDR(base, index)
+#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2)                  HWIO_##hwiosym##_ADDR(base, idx1, idx2)
+#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3)            HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
+#define __msmhwio_physx(base, hwiosym)                                HWIO_##hwiosym##_PHYS(base)
+#define __msmhwio_physxi(base, hwiosym, index)                        HWIO_##hwiosym##_PHYS(base, index)
+#define __msmhwio_physxi2(base, hwiosym, idx1, idx2)                  HWIO_##hwiosym##_PHYS(base, idx1, idx2)
+#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3)            HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
+
+#define HWIO_INTLOCK()
+#define HWIO_INTFREE()
+
+#define __inp(port)         (*((volatile uint8 *) (port)))
+#define __inpw(port)        (*((volatile uint16 *) (port)))
+#define __inpdw(port)       (*((volatile uint32 *) (port)))
+#define __outp(port, val)   (*((volatile uint8 *) (port)) = ((uint8) (val)))
+#define __outpw(port, val)  (*((volatile uint16 *) (port)) = ((uint16) (val)))
+#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
+
+#ifdef HAL_HWIO_EXTERNAL
+
+#undef  __inp
+#undef  __inpw
+#undef  __inpdw
+#undef  __outp
+#undef  __outpw
+#undef  __outpdw
+
+#define  __inp(port)          __inp_extern(port)
+#define  __inpw(port)         __inpw_extern(port)
+#define  __inpdw(port)        __inpdw_extern(port)
+#define  __outp(port, val)    __outp_extern(port, val)
+#define  __outpw(port, val)   __outpw_extern(port, val)
+#define  __outpdw(port, val)  __outpdw_extern(port, val)
+
+extern uint8   __inp_extern      ( uint32 nAddr );
+extern uint16  __inpw_extern     ( uint32 nAddr );
+extern uint32  __inpdw_extern    ( uint32 nAddr );
+extern void    __outp_extern     ( uint32 nAddr, uint8  nData );
+extern void    __outpw_extern    ( uint32 nAddr, uint16 nData );
+extern void    __outpdw_extern   ( uint32 nAddr, uint32 nData );
+
+#endif
+
+#define in_byte(addr)               (__inp(addr))
+#define in_byte_masked(addr, mask)  (__inp(addr) & (mask))
+#define out_byte(addr, val)         __outp(addr,val)
+#define out_byte_masked(io, mask, val, shadow)  \
+  HWIO_INTLOCK();    \
+  out_byte( io, shadow); \
+  shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
+  HWIO_INTFREE()
+#define out_byte_masked_ns(io, mask, val, current_reg_content)  \
+  out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
+                ((uint16)((val) & (mask)))) )
+
+#define in_word(addr)              (__inpw(addr))
+#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
+#define out_word(addr, val)        __outpw(addr,val)
+#define out_word_masked(io, mask, val, shadow)  \
+  HWIO_INTLOCK( ); \
+  shadow = (shadow & (uint16)(~(mask))) |  ((uint16)((val) & (mask))); \
+  out_word( io, shadow); \
+  HWIO_INTFREE( )
+#define out_word_masked_ns(io, mask, val, current_reg_content)  \
+  out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
+                ((uint16)((val) & (mask)))) )
+
+#define in_dword(addr)              (__inpdw(addr))
+#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
+#define out_dword(addr, val)        __outpdw(addr,val)
+#define out_dword_masked(io, mask, val, shadow)  \
+   HWIO_INTLOCK(); \
+   shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
+   out_dword( io, shadow); \
+   HWIO_INTFREE()
+#define out_dword_masked_ns(io, mask, val, current_reg_content) \
+  out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
+                 ((uint32)((val) & (mask)))) )
+
+#endif
+
diff --git a/hw/peach/v1/ack_report.h b/hw/peach/v1/ack_report.h
new file mode 100644
index 000000000000..6b00b2ee99f0
--- /dev/null
+++ b/hw/peach/v1/ack_report.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ACK_REPORT_H_
+#define _ACK_REPORT_H_
+
+#define NUM_OF_DWORDS_ACK_REPORT 1
+
+struct ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t selfgen_response_reason                                 :  4,
+                      ax_trigger_type                                         :  4,
+                      sr_ppdu                                                 :  1,
+                      reserved                                                :  7,
+                      frame_control                                           : 16;
+#else
+             uint32_t frame_control                                           : 16,
+                      reserved                                                :  7,
+                      sr_ppdu                                                 :  1,
+                      ax_trigger_type                                         :  4,
+                      selfgen_response_reason                                 :  4;
+#endif
+};
+
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET                                   0x00000000
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB                                      0
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB                                      3
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK                                     0x0000000f
+
+#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET                                           0x00000000
+#define ACK_REPORT_AX_TRIGGER_TYPE_LSB                                              4
+#define ACK_REPORT_AX_TRIGGER_TYPE_MSB                                              7
+#define ACK_REPORT_AX_TRIGGER_TYPE_MASK                                             0x000000f0
+
+#define ACK_REPORT_SR_PPDU_OFFSET                                                   0x00000000
+#define ACK_REPORT_SR_PPDU_LSB                                                      8
+#define ACK_REPORT_SR_PPDU_MSB                                                      8
+#define ACK_REPORT_SR_PPDU_MASK                                                     0x00000100
+
+#define ACK_REPORT_RESERVED_OFFSET                                                  0x00000000
+#define ACK_REPORT_RESERVED_LSB                                                     9
+#define ACK_REPORT_RESERVED_MSB                                                     15
+#define ACK_REPORT_RESERVED_MASK                                                    0x0000fe00
+
+#define ACK_REPORT_FRAME_CONTROL_OFFSET                                             0x00000000
+#define ACK_REPORT_FRAME_CONTROL_LSB                                                16
+#define ACK_REPORT_FRAME_CONTROL_MSB                                                31
+#define ACK_REPORT_FRAME_CONTROL_MASK                                               0xffff0000
+
+#endif
diff --git a/hw/peach/v1/beryllium_top_reg.h b/hw/peach/v1/beryllium_top_reg.h
new file mode 100644
index 000000000000..5477be24828e
--- /dev/null
+++ b/hw/peach/v1/beryllium_top_reg.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef BERYLLIUM_TOP_REG_H
+#define BERYLLIUM_TOP_REG_H
+
+#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C)
+#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050)
+
+#endif
diff --git a/hw/peach/v1/buffer_addr_info.h b/hw/peach/v1/buffer_addr_info.h
new file mode 100644
index 000000000000..4a8c064ecd16
--- /dev/null
+++ b/hw/peach/v1/buffer_addr_info.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _BUFFER_ADDR_INFO_H_
+#define _BUFFER_ADDR_INFO_H_
+
+#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
+
+struct buffer_addr_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t buffer_addr_31_0                                        : 32;
+             uint32_t buffer_addr_39_32                                       :  8,
+                      return_buffer_manager                                   :  4,
+                      sw_buffer_cookie                                        : 20;
+#else
+             uint32_t buffer_addr_31_0                                        : 32;
+             uint32_t sw_buffer_cookie                                        : 20,
+                      return_buffer_manager                                   :  4,
+                      buffer_addr_39_32                                       :  8;
+#endif
+};
+
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET                                    0x00000000
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB                                       0
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB                                       31
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK                                      0xffffffff
+
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET                                   0x00000004
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB                                      0
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB                                      7
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK                                     0x000000ff
+
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET                               0x00000004
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB                                  8
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB                                  11
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK                                 0x00000f00
+
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET                                    0x00000004
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB                                       12
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB                                       31
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK                                      0xfffff000
+
+#endif
diff --git a/hw/peach/v1/ce_src_desc.h b/hw/peach/v1/ce_src_desc.h
new file mode 100644
index 000000000000..3aa8b5850fea
--- /dev/null
+++ b/hw/peach/v1/ce_src_desc.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _CE_SRC_DESC_H_
+#define _CE_SRC_DESC_H_
+
+#define NUM_OF_DWORDS_CE_SRC_DESC 4
+
+struct ce_src_desc {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t src_buffer_low                                          : 32;
+             uint32_t src_buffer_high                                         :  8,
+                      toeplitz_en                                             :  1,
+                      src_swap                                                :  1,
+                      dest_swap                                               :  1,
+                      gather                                                  :  1,
+                      ce_res_0                                                :  1,
+                      barrier_read                                            :  1,
+                      ce_res_1                                                :  2,
+                      length                                                  : 16;
+             uint32_t fw_metadata                                             : 16,
+                      ce_res_2                                                : 16;
+             uint32_t ce_res_3                                                : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t src_buffer_low                                          : 32;
+             uint32_t length                                                  : 16,
+                      ce_res_1                                                :  2,
+                      barrier_read                                            :  1,
+                      ce_res_0                                                :  1,
+                      gather                                                  :  1,
+                      dest_swap                                               :  1,
+                      src_swap                                                :  1,
+                      toeplitz_en                                             :  1,
+                      src_buffer_high                                         :  8;
+             uint32_t ce_res_2                                                : 16,
+                      fw_metadata                                             : 16;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      ce_res_3                                                : 20;
+#endif
+};
+
+#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET                                           0x00000000
+#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB                                              0
+#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB                                              31
+#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK                                             0xffffffff
+
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET                                          0x00000004
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB                                             0
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB                                             7
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK                                            0x000000ff
+
+#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET                                              0x00000004
+#define CE_SRC_DESC_TOEPLITZ_EN_LSB                                                 8
+#define CE_SRC_DESC_TOEPLITZ_EN_MSB                                                 8
+#define CE_SRC_DESC_TOEPLITZ_EN_MASK                                                0x00000100
+
+#define CE_SRC_DESC_SRC_SWAP_OFFSET                                                 0x00000004
+#define CE_SRC_DESC_SRC_SWAP_LSB                                                    9
+#define CE_SRC_DESC_SRC_SWAP_MSB                                                    9
+#define CE_SRC_DESC_SRC_SWAP_MASK                                                   0x00000200
+
+#define CE_SRC_DESC_DEST_SWAP_OFFSET                                                0x00000004
+#define CE_SRC_DESC_DEST_SWAP_LSB                                                   10
+#define CE_SRC_DESC_DEST_SWAP_MSB                                                   10
+#define CE_SRC_DESC_DEST_SWAP_MASK                                                  0x00000400
+
+#define CE_SRC_DESC_GATHER_OFFSET                                                   0x00000004
+#define CE_SRC_DESC_GATHER_LSB                                                      11
+#define CE_SRC_DESC_GATHER_MSB                                                      11
+#define CE_SRC_DESC_GATHER_MASK                                                     0x00000800
+
+#define CE_SRC_DESC_CE_RES_0_OFFSET                                                 0x00000004
+#define CE_SRC_DESC_CE_RES_0_LSB                                                    12
+#define CE_SRC_DESC_CE_RES_0_MSB                                                    12
+#define CE_SRC_DESC_CE_RES_0_MASK                                                   0x00001000
+
+#define CE_SRC_DESC_BARRIER_READ_OFFSET                                             0x00000004
+#define CE_SRC_DESC_BARRIER_READ_LSB                                                13
+#define CE_SRC_DESC_BARRIER_READ_MSB                                                13
+#define CE_SRC_DESC_BARRIER_READ_MASK                                               0x00002000
+
+#define CE_SRC_DESC_CE_RES_1_OFFSET                                                 0x00000004
+#define CE_SRC_DESC_CE_RES_1_LSB                                                    14
+#define CE_SRC_DESC_CE_RES_1_MSB                                                    15
+#define CE_SRC_DESC_CE_RES_1_MASK                                                   0x0000c000
+
+#define CE_SRC_DESC_LENGTH_OFFSET                                                   0x00000004
+#define CE_SRC_DESC_LENGTH_LSB                                                      16
+#define CE_SRC_DESC_LENGTH_MSB                                                      31
+#define CE_SRC_DESC_LENGTH_MASK                                                     0xffff0000
+
+#define CE_SRC_DESC_FW_METADATA_OFFSET                                              0x00000008
+#define CE_SRC_DESC_FW_METADATA_LSB                                                 0
+#define CE_SRC_DESC_FW_METADATA_MSB                                                 15
+#define CE_SRC_DESC_FW_METADATA_MASK                                                0x0000ffff
+
+#define CE_SRC_DESC_CE_RES_2_OFFSET                                                 0x00000008
+#define CE_SRC_DESC_CE_RES_2_LSB                                                    16
+#define CE_SRC_DESC_CE_RES_2_MSB                                                    31
+#define CE_SRC_DESC_CE_RES_2_MASK                                                   0xffff0000
+
+#define CE_SRC_DESC_CE_RES_3_OFFSET                                                 0x0000000c
+#define CE_SRC_DESC_CE_RES_3_LSB                                                    0
+#define CE_SRC_DESC_CE_RES_3_MSB                                                    19
+#define CE_SRC_DESC_CE_RES_3_MASK                                                   0x000fffff
+
+#define CE_SRC_DESC_RING_ID_OFFSET                                                  0x0000000c
+#define CE_SRC_DESC_RING_ID_LSB                                                     20
+#define CE_SRC_DESC_RING_ID_MSB                                                     27
+#define CE_SRC_DESC_RING_ID_MASK                                                    0x0ff00000
+
+#define CE_SRC_DESC_LOOPING_COUNT_OFFSET                                            0x0000000c
+#define CE_SRC_DESC_LOOPING_COUNT_LSB                                               28
+#define CE_SRC_DESC_LOOPING_COUNT_MSB                                               31
+#define CE_SRC_DESC_LOOPING_COUNT_MASK                                              0xf0000000
+
+#endif
diff --git a/hw/peach/v1/ce_stat_desc.h b/hw/peach/v1/ce_stat_desc.h
new file mode 100644
index 000000000000..199c25775c0c
--- /dev/null
+++ b/hw/peach/v1/ce_stat_desc.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _CE_STAT_DESC_H_
+#define _CE_STAT_DESC_H_
+
+#define NUM_OF_DWORDS_CE_STAT_DESC 4
+
+struct ce_stat_desc {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ce_res_5                                                :  8,
+                      toeplitz_en                                             :  1,
+                      src_swap                                                :  1,
+                      dest_swap                                               :  1,
+                      gather                                                  :  1,
+                      barrier_read                                            :  1,
+                      ce_res_6                                                :  3,
+                      length                                                  : 16;
+             uint32_t toeplitz_hash_0                                         : 32;
+             uint32_t toeplitz_hash_1                                         : 32;
+             uint32_t fw_metadata                                             : 16,
+                      ce_res_7                                                :  4,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t length                                                  : 16,
+                      ce_res_6                                                :  3,
+                      barrier_read                                            :  1,
+                      gather                                                  :  1,
+                      dest_swap                                               :  1,
+                      src_swap                                                :  1,
+                      toeplitz_en                                             :  1,
+                      ce_res_5                                                :  8;
+             uint32_t toeplitz_hash_0                                         : 32;
+             uint32_t toeplitz_hash_1                                         : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      ce_res_7                                                :  4,
+                      fw_metadata                                             : 16;
+#endif
+};
+
+#define CE_STAT_DESC_CE_RES_5_OFFSET                                                0x00000000
+#define CE_STAT_DESC_CE_RES_5_LSB                                                   0
+#define CE_STAT_DESC_CE_RES_5_MSB                                                   7
+#define CE_STAT_DESC_CE_RES_5_MASK                                                  0x000000ff
+
+#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET                                             0x00000000
+#define CE_STAT_DESC_TOEPLITZ_EN_LSB                                                8
+#define CE_STAT_DESC_TOEPLITZ_EN_MSB                                                8
+#define CE_STAT_DESC_TOEPLITZ_EN_MASK                                               0x00000100
+
+#define CE_STAT_DESC_SRC_SWAP_OFFSET                                                0x00000000
+#define CE_STAT_DESC_SRC_SWAP_LSB                                                   9
+#define CE_STAT_DESC_SRC_SWAP_MSB                                                   9
+#define CE_STAT_DESC_SRC_SWAP_MASK                                                  0x00000200
+
+#define CE_STAT_DESC_DEST_SWAP_OFFSET                                               0x00000000
+#define CE_STAT_DESC_DEST_SWAP_LSB                                                  10
+#define CE_STAT_DESC_DEST_SWAP_MSB                                                  10
+#define CE_STAT_DESC_DEST_SWAP_MASK                                                 0x00000400
+
+#define CE_STAT_DESC_GATHER_OFFSET                                                  0x00000000
+#define CE_STAT_DESC_GATHER_LSB                                                     11
+#define CE_STAT_DESC_GATHER_MSB                                                     11
+#define CE_STAT_DESC_GATHER_MASK                                                    0x00000800
+
+#define CE_STAT_DESC_BARRIER_READ_OFFSET                                            0x00000000
+#define CE_STAT_DESC_BARRIER_READ_LSB                                               12
+#define CE_STAT_DESC_BARRIER_READ_MSB                                               12
+#define CE_STAT_DESC_BARRIER_READ_MASK                                              0x00001000
+
+#define CE_STAT_DESC_CE_RES_6_OFFSET                                                0x00000000
+#define CE_STAT_DESC_CE_RES_6_LSB                                                   13
+#define CE_STAT_DESC_CE_RES_6_MSB                                                   15
+#define CE_STAT_DESC_CE_RES_6_MASK                                                  0x0000e000
+
+#define CE_STAT_DESC_LENGTH_OFFSET                                                  0x00000000
+#define CE_STAT_DESC_LENGTH_LSB                                                     16
+#define CE_STAT_DESC_LENGTH_MSB                                                     31
+#define CE_STAT_DESC_LENGTH_MASK                                                    0xffff0000
+
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET                                         0x00000004
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB                                            0
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB                                            31
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK                                           0xffffffff
+
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET                                         0x00000008
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB                                            0
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB                                            31
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK                                           0xffffffff
+
+#define CE_STAT_DESC_FW_METADATA_OFFSET                                             0x0000000c
+#define CE_STAT_DESC_FW_METADATA_LSB                                                0
+#define CE_STAT_DESC_FW_METADATA_MSB                                                15
+#define CE_STAT_DESC_FW_METADATA_MASK                                               0x0000ffff
+
+#define CE_STAT_DESC_CE_RES_7_OFFSET                                                0x0000000c
+#define CE_STAT_DESC_CE_RES_7_LSB                                                   16
+#define CE_STAT_DESC_CE_RES_7_MSB                                                   19
+#define CE_STAT_DESC_CE_RES_7_MASK                                                  0x000f0000
+
+#define CE_STAT_DESC_RING_ID_OFFSET                                                 0x0000000c
+#define CE_STAT_DESC_RING_ID_LSB                                                    20
+#define CE_STAT_DESC_RING_ID_MSB                                                    27
+#define CE_STAT_DESC_RING_ID_MASK                                                   0x0ff00000
+
+#define CE_STAT_DESC_LOOPING_COUNT_OFFSET                                           0x0000000c
+#define CE_STAT_DESC_LOOPING_COUNT_LSB                                              28
+#define CE_STAT_DESC_LOOPING_COUNT_MSB                                              31
+#define CE_STAT_DESC_LOOPING_COUNT_MASK                                             0xf0000000
+
+#endif
diff --git a/hw/peach/v1/coex_rx_status.h b/hw/peach/v1/coex_rx_status.h
new file mode 100644
index 000000000000..86db6aad1116
--- /dev/null
+++ b/hw/peach/v1/coex_rx_status.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _COEX_RX_STATUS_H_
+#define _COEX_RX_STATUS_H_
+
+#define NUM_OF_DWORDS_COEX_RX_STATUS 2
+
+struct coex_rx_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rx_mac_frame_status                                     :  2,
+                      rx_with_tx_response                                     :  1,
+                      rx_rate                                                 :  5,
+                      rx_bw                                                   :  3,
+                      single_mpdu                                             :  1,
+                      filter_status                                           :  1,
+                      ampdu                                                   :  1,
+                      directed                                                :  1,
+                      reserved_0                                              :  1,
+                      rx_nss                                                  :  3,
+                      rx_rssi                                                 :  8,
+                      rx_type                                                 :  3,
+                      retry_bit_setting                                       :  1,
+                      more_data_bit_setting                                   :  1;
+             uint32_t remain_rx_packet_time                                   : 16,
+                      rx_remaining_fes_time                                   : 16;
+#else
+             uint32_t more_data_bit_setting                                   :  1,
+                      retry_bit_setting                                       :  1,
+                      rx_type                                                 :  3,
+                      rx_rssi                                                 :  8,
+                      rx_nss                                                  :  3,
+                      reserved_0                                              :  1,
+                      directed                                                :  1,
+                      ampdu                                                   :  1,
+                      filter_status                                           :  1,
+                      single_mpdu                                             :  1,
+                      rx_bw                                                   :  3,
+                      rx_rate                                                 :  5,
+                      rx_with_tx_response                                     :  1,
+                      rx_mac_frame_status                                     :  2;
+             uint32_t rx_remaining_fes_time                                   : 16,
+                      remain_rx_packet_time                                   : 16;
+#endif
+};
+
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET                                   0x00000000
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB                                      0
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB                                      1
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK                                     0x00000003
+
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET                                   0x00000000
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB                                      2
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB                                      2
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK                                     0x00000004
+
+#define COEX_RX_STATUS_RX_RATE_OFFSET                                               0x00000000
+#define COEX_RX_STATUS_RX_RATE_LSB                                                  3
+#define COEX_RX_STATUS_RX_RATE_MSB                                                  7
+#define COEX_RX_STATUS_RX_RATE_MASK                                                 0x000000f8
+
+#define COEX_RX_STATUS_RX_BW_OFFSET                                                 0x00000000
+#define COEX_RX_STATUS_RX_BW_LSB                                                    8
+#define COEX_RX_STATUS_RX_BW_MSB                                                    10
+#define COEX_RX_STATUS_RX_BW_MASK                                                   0x00000700
+
+#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET                                           0x00000000
+#define COEX_RX_STATUS_SINGLE_MPDU_LSB                                              11
+#define COEX_RX_STATUS_SINGLE_MPDU_MSB                                              11
+#define COEX_RX_STATUS_SINGLE_MPDU_MASK                                             0x00000800
+
+#define COEX_RX_STATUS_FILTER_STATUS_OFFSET                                         0x00000000
+#define COEX_RX_STATUS_FILTER_STATUS_LSB                                            12
+#define COEX_RX_STATUS_FILTER_STATUS_MSB                                            12
+#define COEX_RX_STATUS_FILTER_STATUS_MASK                                           0x00001000
+
+#define COEX_RX_STATUS_AMPDU_OFFSET                                                 0x00000000
+#define COEX_RX_STATUS_AMPDU_LSB                                                    13
+#define COEX_RX_STATUS_AMPDU_MSB                                                    13
+#define COEX_RX_STATUS_AMPDU_MASK                                                   0x00002000
+
+#define COEX_RX_STATUS_DIRECTED_OFFSET                                              0x00000000
+#define COEX_RX_STATUS_DIRECTED_LSB                                                 14
+#define COEX_RX_STATUS_DIRECTED_MSB                                                 14
+#define COEX_RX_STATUS_DIRECTED_MASK                                                0x00004000
+
+#define COEX_RX_STATUS_RESERVED_0_OFFSET                                            0x00000000
+#define COEX_RX_STATUS_RESERVED_0_LSB                                               15
+#define COEX_RX_STATUS_RESERVED_0_MSB                                               15
+#define COEX_RX_STATUS_RESERVED_0_MASK                                              0x00008000
+
+#define COEX_RX_STATUS_RX_NSS_OFFSET                                                0x00000000
+#define COEX_RX_STATUS_RX_NSS_LSB                                                   16
+#define COEX_RX_STATUS_RX_NSS_MSB                                                   18
+#define COEX_RX_STATUS_RX_NSS_MASK                                                  0x00070000
+
+#define COEX_RX_STATUS_RX_RSSI_OFFSET                                               0x00000000
+#define COEX_RX_STATUS_RX_RSSI_LSB                                                  19
+#define COEX_RX_STATUS_RX_RSSI_MSB                                                  26
+#define COEX_RX_STATUS_RX_RSSI_MASK                                                 0x07f80000
+
+#define COEX_RX_STATUS_RX_TYPE_OFFSET                                               0x00000000
+#define COEX_RX_STATUS_RX_TYPE_LSB                                                  27
+#define COEX_RX_STATUS_RX_TYPE_MSB                                                  29
+#define COEX_RX_STATUS_RX_TYPE_MASK                                                 0x38000000
+
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET                                     0x00000000
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB                                        30
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB                                        30
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK                                       0x40000000
+
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET                                 0x00000000
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB                                    31
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB                                    31
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK                                   0x80000000
+
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET                                 0x00000004
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB                                    0
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB                                    15
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK                                   0x0000ffff
+
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET                                 0x00000004
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB                                    16
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB                                    31
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK                                   0xffff0000
+
+#endif
diff --git a/hw/peach/v1/coex_tx_req.h b/hw/peach/v1/coex_tx_req.h
new file mode 100644
index 000000000000..a116adb2a132
--- /dev/null
+++ b/hw/peach/v1/coex_tx_req.h
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _COEX_TX_REQ_H_
+#define _COEX_TX_REQ_H_
+
+#define NUM_OF_DWORDS_COEX_TX_REQ 4
+
+struct coex_tx_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_pwr                                                  :  8,
+                      min_tx_pwr                                              :  8,
+                      nss                                                     :  3,
+                      tx_chain_mask                                           :  8,
+                      bw                                                      :  3,
+                      reserved_0                                              :  2;
+             uint32_t alt_tx_pwr                                              :  8,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_nss                                                 :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_bw                                                  :  3,
+                      reserved_1                                              :  2;
+             uint32_t tx_pwr_1                                                :  8,
+                      alt_tx_pwr_1                                            :  8,
+                      wlan_request_duration                                   : 16;
+             uint32_t wlan_pkt_type                                           :  4,
+                      coex_tx_reason                                          :  2,
+                      response_frame_type                                     :  5,
+                      wlan_low_priority_slicing_allowed                       :  1,
+                      wlan_high_priority_slicing_allowed                      :  1,
+                      sch_tx_burst_ongoing                                    :  1,
+                      coex_tx_priority                                        :  4,
+                      reserved_3a                                             : 14;
+#else
+             uint32_t reserved_0                                              :  2,
+                      bw                                                      :  3,
+                      tx_chain_mask                                           :  8,
+                      nss                                                     :  3,
+                      min_tx_pwr                                              :  8,
+                      tx_pwr                                                  :  8;
+             uint32_t reserved_1                                              :  2,
+                      alt_bw                                                  :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_nss                                                 :  3,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_tx_pwr                                              :  8;
+             uint32_t wlan_request_duration                                   : 16,
+                      alt_tx_pwr_1                                            :  8,
+                      tx_pwr_1                                                :  8;
+             uint32_t reserved_3a                                             : 14,
+                      coex_tx_priority                                        :  4,
+                      sch_tx_burst_ongoing                                    :  1,
+                      wlan_high_priority_slicing_allowed                      :  1,
+                      wlan_low_priority_slicing_allowed                       :  1,
+                      response_frame_type                                     :  5,
+                      coex_tx_reason                                          :  2,
+                      wlan_pkt_type                                           :  4;
+#endif
+};
+
+#define COEX_TX_REQ_TX_PWR_OFFSET                                                   0x00000000
+#define COEX_TX_REQ_TX_PWR_LSB                                                      0
+#define COEX_TX_REQ_TX_PWR_MSB                                                      7
+#define COEX_TX_REQ_TX_PWR_MASK                                                     0x000000ff
+
+#define COEX_TX_REQ_MIN_TX_PWR_OFFSET                                               0x00000000
+#define COEX_TX_REQ_MIN_TX_PWR_LSB                                                  8
+#define COEX_TX_REQ_MIN_TX_PWR_MSB                                                  15
+#define COEX_TX_REQ_MIN_TX_PWR_MASK                                                 0x0000ff00
+
+#define COEX_TX_REQ_NSS_OFFSET                                                      0x00000000
+#define COEX_TX_REQ_NSS_LSB                                                         16
+#define COEX_TX_REQ_NSS_MSB                                                         18
+#define COEX_TX_REQ_NSS_MASK                                                        0x00070000
+
+#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET                                            0x00000000
+#define COEX_TX_REQ_TX_CHAIN_MASK_LSB                                               19
+#define COEX_TX_REQ_TX_CHAIN_MASK_MSB                                               26
+#define COEX_TX_REQ_TX_CHAIN_MASK_MASK                                              0x07f80000
+
+#define COEX_TX_REQ_BW_OFFSET                                                       0x00000000
+#define COEX_TX_REQ_BW_LSB                                                          27
+#define COEX_TX_REQ_BW_MSB                                                          29
+#define COEX_TX_REQ_BW_MASK                                                         0x38000000
+
+#define COEX_TX_REQ_RESERVED_0_OFFSET                                               0x00000000
+#define COEX_TX_REQ_RESERVED_0_LSB                                                  30
+#define COEX_TX_REQ_RESERVED_0_MSB                                                  31
+#define COEX_TX_REQ_RESERVED_0_MASK                                                 0xc0000000
+
+#define COEX_TX_REQ_ALT_TX_PWR_OFFSET                                               0x00000004
+#define COEX_TX_REQ_ALT_TX_PWR_LSB                                                  0
+#define COEX_TX_REQ_ALT_TX_PWR_MSB                                                  7
+#define COEX_TX_REQ_ALT_TX_PWR_MASK                                                 0x000000ff
+
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET                                           0x00000004
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB                                              8
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB                                              15
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK                                             0x0000ff00
+
+#define COEX_TX_REQ_ALT_NSS_OFFSET                                                  0x00000004
+#define COEX_TX_REQ_ALT_NSS_LSB                                                     16
+#define COEX_TX_REQ_ALT_NSS_MSB                                                     18
+#define COEX_TX_REQ_ALT_NSS_MASK                                                    0x00070000
+
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET                                        0x00000004
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB                                           19
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB                                           26
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK                                          0x07f80000
+
+#define COEX_TX_REQ_ALT_BW_OFFSET                                                   0x00000004
+#define COEX_TX_REQ_ALT_BW_LSB                                                      27
+#define COEX_TX_REQ_ALT_BW_MSB                                                      29
+#define COEX_TX_REQ_ALT_BW_MASK                                                     0x38000000
+
+#define COEX_TX_REQ_RESERVED_1_OFFSET                                               0x00000004
+#define COEX_TX_REQ_RESERVED_1_LSB                                                  30
+#define COEX_TX_REQ_RESERVED_1_MSB                                                  31
+#define COEX_TX_REQ_RESERVED_1_MASK                                                 0xc0000000
+
+#define COEX_TX_REQ_TX_PWR_1_OFFSET                                                 0x00000008
+#define COEX_TX_REQ_TX_PWR_1_LSB                                                    0
+#define COEX_TX_REQ_TX_PWR_1_MSB                                                    7
+#define COEX_TX_REQ_TX_PWR_1_MASK                                                   0x000000ff
+
+#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET                                             0x00000008
+#define COEX_TX_REQ_ALT_TX_PWR_1_LSB                                                8
+#define COEX_TX_REQ_ALT_TX_PWR_1_MSB                                                15
+#define COEX_TX_REQ_ALT_TX_PWR_1_MASK                                               0x0000ff00
+
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET                                    0x00000008
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB                                       16
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB                                       31
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK                                      0xffff0000
+
+#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET                                            0x0000000c
+#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB                                               0
+#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB                                               3
+#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK                                              0x0000000f
+
+#define COEX_TX_REQ_COEX_TX_REASON_OFFSET                                           0x0000000c
+#define COEX_TX_REQ_COEX_TX_REASON_LSB                                              4
+#define COEX_TX_REQ_COEX_TX_REASON_MSB                                              5
+#define COEX_TX_REQ_COEX_TX_REASON_MASK                                             0x00000030
+
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET                                      0x0000000c
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB                                         6
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB                                         10
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK                                        0x000007c0
+
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET                        0x0000000c
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB                           11
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB                           11
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK                          0x00000800
+
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET                       0x0000000c
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB                          12
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB                          12
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK                         0x00001000
+
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET                                     0x0000000c
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB                                        13
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB                                        13
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK                                       0x00002000
+
+#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET                                         0x0000000c
+#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB                                            14
+#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB                                            17
+#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK                                           0x0003c000
+
+#define COEX_TX_REQ_RESERVED_3A_OFFSET                                              0x0000000c
+#define COEX_TX_REQ_RESERVED_3A_LSB                                                 18
+#define COEX_TX_REQ_RESERVED_3A_MSB                                                 31
+#define COEX_TX_REQ_RESERVED_3A_MASK                                                0xfffc0000
+
+#endif
diff --git a/hw/peach/v1/coex_tx_status.h b/hw/peach/v1/coex_tx_status.h
new file mode 100644
index 000000000000..7331ea9094b0
--- /dev/null
+++ b/hw/peach/v1/coex_tx_status.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _COEX_TX_STATUS_H_
+#define _COEX_TX_STATUS_H_
+
+#define NUM_OF_DWORDS_COEX_TX_STATUS 3
+
+struct coex_tx_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             :  7,
+                      tx_bw                                                   :  3,
+                      tx_status_reason                                        :  3,
+                      tx_wait_ack                                             :  1,
+                      fes_tx_is_gen_frame                                     :  1,
+                      sch_tx_burst_ongoing                                    :  1,
+                      current_tx_duration                                     : 16;
+             uint32_t next_rx_active_time                                     : 16,
+                      remaining_fes_time                                      : 16;
+             uint32_t tx_antenna_mask                                         :  8,
+                      shared_ant_tx_pwr                                       :  8,
+                      other_ant_tx_pwr                                        :  8,
+                      reserved_2                                              :  8;
+#else
+             uint32_t current_tx_duration                                     : 16,
+                      sch_tx_burst_ongoing                                    :  1,
+                      fes_tx_is_gen_frame                                     :  1,
+                      tx_wait_ack                                             :  1,
+                      tx_status_reason                                        :  3,
+                      tx_bw                                                   :  3,
+                      reserved_0a                                             :  7;
+             uint32_t remaining_fes_time                                      : 16,
+                      next_rx_active_time                                     : 16;
+             uint32_t reserved_2                                              :  8,
+                      other_ant_tx_pwr                                        :  8,
+                      shared_ant_tx_pwr                                       :  8,
+                      tx_antenna_mask                                         :  8;
+#endif
+};
+
+#define COEX_TX_STATUS_RESERVED_0A_OFFSET                                           0x00000000
+#define COEX_TX_STATUS_RESERVED_0A_LSB                                              0
+#define COEX_TX_STATUS_RESERVED_0A_MSB                                              6
+#define COEX_TX_STATUS_RESERVED_0A_MASK                                             0x0000007f
+
+#define COEX_TX_STATUS_TX_BW_OFFSET                                                 0x00000000
+#define COEX_TX_STATUS_TX_BW_LSB                                                    7
+#define COEX_TX_STATUS_TX_BW_MSB                                                    9
+#define COEX_TX_STATUS_TX_BW_MASK                                                   0x00000380
+
+#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET                                      0x00000000
+#define COEX_TX_STATUS_TX_STATUS_REASON_LSB                                         10
+#define COEX_TX_STATUS_TX_STATUS_REASON_MSB                                         12
+#define COEX_TX_STATUS_TX_STATUS_REASON_MASK                                        0x00001c00
+
+#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET                                           0x00000000
+#define COEX_TX_STATUS_TX_WAIT_ACK_LSB                                              13
+#define COEX_TX_STATUS_TX_WAIT_ACK_MSB                                              13
+#define COEX_TX_STATUS_TX_WAIT_ACK_MASK                                             0x00002000
+
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET                                   0x00000000
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB                                      14
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB                                      14
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK                                     0x00004000
+
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET                                  0x00000000
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB                                     15
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB                                     15
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK                                    0x00008000
+
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET                                   0x00000000
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB                                      16
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB                                      31
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK                                     0xffff0000
+
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET                                   0x00000004
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB                                      0
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB                                      15
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK                                     0x0000ffff
+
+#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET                                    0x00000004
+#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB                                       16
+#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB                                       31
+#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK                                      0xffff0000
+
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET                                       0x00000008
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB                                          0
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB                                          7
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK                                         0x000000ff
+
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET                                     0x00000008
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB                                        8
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB                                        15
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK                                       0x0000ff00
+
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET                                      0x00000008
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB                                         16
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB                                         23
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK                                        0x00ff0000
+
+#define COEX_TX_STATUS_RESERVED_2_OFFSET                                            0x00000008
+#define COEX_TX_STATUS_RESERVED_2_LSB                                               24
+#define COEX_TX_STATUS_RESERVED_2_MSB                                               31
+#define COEX_TX_STATUS_RESERVED_2_MASK                                              0xff000000
+
+#endif
diff --git a/hw/peach/v1/com_dtypes.h b/hw/peach/v1/com_dtypes.h
new file mode 100644
index 000000000000..dc2da8338fcf
--- /dev/null
+++ b/hw/peach/v1/com_dtypes.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef COM_DTYPES_H
+#define COM_DTYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef T_WINNT
+   #ifndef WIN32
+      #define WIN32
+   #endif
+   #include <stdlib.h>
+#endif
+
+#ifdef TRUE
+#undef TRUE
+#endif
+
+#ifdef FALSE
+#undef FALSE
+#endif
+
+#define TRUE   1
+#define FALSE  0
+
+#define  ON   1
+#define  OFF  0
+
+#ifndef NULL
+  #define NULL  0
+#endif
+
+#ifndef _ARM_ASM_
+#ifndef _BOOLEAN_DEFINED
+
+typedef  unsigned char      boolean;
+#define _BOOLEAN_DEFINED
+#endif
+
+#if defined(DALSTDDEF_H)
+#define _BOOLEAN_DEFINED
+#define _UINT32_DEFINED
+#define _UINT16_DEFINED
+#define _UINT8_DEFINED
+#define _INT32_DEFINED
+#define _INT16_DEFINED
+#define _INT8_DEFINED
+#define _UINT64_DEFINED
+#define _INT64_DEFINED
+#define _BYTE_DEFINED
+#endif
+
+#ifndef _UINT32_DEFINED
+
+typedef  unsigned int  uint32;
+#define _UINT32_DEFINED
+#endif
+
+#ifndef _UINT16_DEFINED
+
+typedef  unsigned short     uint16;
+#define _UINT16_DEFINED
+#endif
+
+#ifndef _UINT8_DEFINED
+
+typedef  unsigned char      uint8;
+#define _UINT8_DEFINED
+#endif
+
+#ifndef _INT32_DEFINED
+
+typedef  signed int    int32;
+#define _INT32_DEFINED
+#endif
+
+#ifndef _INT16_DEFINED
+
+typedef  signed short       int16;
+#define _INT16_DEFINED
+#endif
+
+#ifndef _INT8_DEFINED
+
+typedef  signed char        int8;
+#define _INT8_DEFINED
+#endif
+
+#ifndef _BYTE_DEFINED
+
+typedef  unsigned char      byte;
+#define  _BYTE_DEFINED
+#endif
+
+typedef  unsigned short     word;
+
+typedef  unsigned long      dword;
+
+typedef  unsigned char      uint1;
+
+typedef  unsigned short     uint2;
+
+typedef  unsigned long      uint4;
+
+typedef  signed char        int1;
+
+typedef  signed short       int2;
+
+typedef  long int           int4;
+
+typedef  signed long        sint31;
+
+typedef  signed short       sint15;
+
+typedef  signed char        sint7;
+
+typedef uint16 UWord16 ;
+typedef uint32 UWord32 ;
+typedef int32  Word32 ;
+typedef int16  Word16 ;
+typedef uint8  UWord8 ;
+typedef int8   Word8 ;
+typedef int32  Vect32 ;
+
+#if (! defined T_WINNT) && (! defined __GNUC__)
+
+  #ifndef _INT64_DEFINED
+
+    typedef long long     int64;
+    #define _INT64_DEFINED
+  #endif
+  #ifndef _UINT64_DEFINED
+
+    typedef  unsigned long long  uint64;
+    #define _UINT64_DEFINED
+  #endif
+#else
+
+  #if (defined __GNUC__)
+    #ifndef _INT64_DEFINED
+      typedef long long           int64;
+      #define _INT64_DEFINED
+    #endif
+    #ifndef _UINT64_DEFINED
+      typedef unsigned long long  uint64;
+      #define _UINT64_DEFINED
+    #endif
+  #else
+    typedef  __int64              int64;
+    #ifndef _UINT64_DEFINED
+      typedef  unsigned __int64   uint64;
+      #define _UINT64_DEFINED
+    #endif
+  #endif
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/peach/v1/eht_sig_usr_mu_mimo_info.h b/hw/peach/v1/eht_sig_usr_mu_mimo_info.h
new file mode 100644
index 000000000000..c83784ae4b62
--- /dev/null
+++ b/hw/peach/v1/eht_sig_usr_mu_mimo_info.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_
+#define _EHT_SIG_USR_MU_MIMO_INFO_H_
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2
+
+struct eht_sig_usr_mu_mimo_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_mcs                                                 :  4,
+                      sta_coding                                              :  1,
+                      sta_spatial_config                                      :  6,
+                      reserved_0a                                             :  1,
+                      rx_integrity_check_passed                               :  1,
+                      subband80_cc_mask                                       :  8;
+             uint32_t user_order_subband80_0                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_3                                  :  8;
+#else
+             uint32_t subband80_cc_mask                                       :  8,
+                      rx_integrity_check_passed                               :  1,
+                      reserved_0a                                             :  1,
+                      sta_spatial_config                                      :  6,
+                      sta_coding                                              :  1,
+                      sta_mcs                                                 :  4,
+                      sta_id                                                  : 11;
+             uint32_t user_order_subband80_3                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_0                                  :  8;
+#endif
+};
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET                                      0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB                                         0
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB                                         10
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK                                        0x000007ff
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET                                     0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB                                        11
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB                                        14
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK                                       0x00007800
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET                                  0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB                                     15
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB                                     15
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK                                    0x00008000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET                          0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB                             16
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB                             21
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK                            0x003f0000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET                                 0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB                                    22
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB                                    22
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK                                   0x00400000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                   0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                      23
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                      23
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                     0x00800000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET                           0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB                              24
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB                              31
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK                             0xff000000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB                         0
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB                         7
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK                        0x000000ff
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB                         8
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB                         15
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK                        0x0000ff00
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB                         16
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB                         23
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK                        0x00ff0000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET                      0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB                         24
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB                         31
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK                        0xff000000
+
+#endif
diff --git a/hw/peach/v1/eht_sig_usr_ofdma_info.h b/hw/peach/v1/eht_sig_usr_ofdma_info.h
new file mode 100644
index 000000000000..8455629f5b27
--- /dev/null
+++ b/hw/peach/v1/eht_sig_usr_ofdma_info.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _EHT_SIG_USR_OFDMA_INFO_H_
+#define _EHT_SIG_USR_OFDMA_INFO_H_
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2
+
+struct eht_sig_usr_ofdma_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_mcs                                                 :  4,
+                      validate_0a                                             :  1,
+                      nss                                                     :  4,
+                      txbf                                                    :  1,
+                      sta_coding                                              :  1,
+                      reserved_0b                                             :  1,
+                      rx_integrity_check_passed                               :  1,
+                      subband80_cc_mask                                       :  8;
+             uint32_t user_order_subband80_0                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_3                                  :  8;
+#else
+             uint32_t subband80_cc_mask                                       :  8,
+                      rx_integrity_check_passed                               :  1,
+                      reserved_0b                                             :  1,
+                      sta_coding                                              :  1,
+                      txbf                                                    :  1,
+                      nss                                                     :  4,
+                      validate_0a                                             :  1,
+                      sta_mcs                                                 :  4,
+                      sta_id                                                  : 11;
+             uint32_t user_order_subband80_3                                  :  8,
+                      user_order_subband80_2                                  :  8,
+                      user_order_subband80_1                                  :  8,
+                      user_order_subband80_0                                  :  8;
+#endif
+};
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET                                        0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB                                           0
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB                                           10
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK                                          0x000007ff
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET                                       0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB                                          11
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB                                          14
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK                                         0x00007800
+
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET                                   0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB                                      15
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB                                      15
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK                                     0x00008000
+
+#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET                                           0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB                                              16
+#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB                                              19
+#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK                                             0x000f0000
+
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET                                          0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB                                             20
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB                                             20
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK                                            0x00100000
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET                                    0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB                                       21
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB                                       21
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK                                      0x00200000
+
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET                                   0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB                                      22
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB                                      22
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK                                     0x00400000
+
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                     0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                        23
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                        23
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                       0x00800000
+
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET                             0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB                                24
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB                                31
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK                               0xff000000
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB                           0
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB                           7
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK                          0x000000ff
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB                           8
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB                           15
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK                          0x0000ff00
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB                           16
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB                           23
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK                          0x00ff0000
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET                        0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB                           24
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB                           31
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK                          0xff000000
+
+#endif
diff --git a/hw/peach/v1/eht_sig_usr_su_info.h b/hw/peach/v1/eht_sig_usr_su_info.h
new file mode 100644
index 000000000000..29127112fa53
--- /dev/null
+++ b/hw/peach/v1/eht_sig_usr_su_info.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _EHT_SIG_USR_SU_INFO_H_
+#define _EHT_SIG_USR_SU_INFO_H_
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1
+
+struct eht_sig_usr_su_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_mcs                                                 :  4,
+                      validate_0a                                             :  1,
+                      nss                                                     :  4,
+                      txbf                                                    :  1,
+                      sta_coding                                              :  1,
+                      reserved_0b                                             :  9,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_0b                                             :  9,
+                      sta_coding                                              :  1,
+                      txbf                                                    :  1,
+                      nss                                                     :  4,
+                      validate_0a                                             :  1,
+                      sta_mcs                                                 :  4,
+                      sta_id                                                  : 11;
+#endif
+};
+
+#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET                                           0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_ID_LSB                                              0
+#define EHT_SIG_USR_SU_INFO_STA_ID_MSB                                              10
+#define EHT_SIG_USR_SU_INFO_STA_ID_MASK                                             0x000007ff
+
+#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET                                          0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB                                             11
+#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB                                             14
+#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK                                            0x00007800
+
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET                                      0x00000000
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB                                         15
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB                                         15
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK                                        0x00008000
+
+#define EHT_SIG_USR_SU_INFO_NSS_OFFSET                                              0x00000000
+#define EHT_SIG_USR_SU_INFO_NSS_LSB                                                 16
+#define EHT_SIG_USR_SU_INFO_NSS_MSB                                                 19
+#define EHT_SIG_USR_SU_INFO_NSS_MASK                                                0x000f0000
+
+#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET                                             0x00000000
+#define EHT_SIG_USR_SU_INFO_TXBF_LSB                                                20
+#define EHT_SIG_USR_SU_INFO_TXBF_MSB                                                20
+#define EHT_SIG_USR_SU_INFO_TXBF_MASK                                               0x00100000
+
+#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET                                       0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB                                          21
+#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB                                          21
+#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK                                         0x00200000
+
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET                                      0x00000000
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB                                         22
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB                                         30
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK                                        0x7fc00000
+
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000000
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
+
+#endif
diff --git a/hw/peach/v1/expected_response.h b/hw/peach/v1/expected_response.h
new file mode 100644
index 000000000000..fe18eca09123
--- /dev/null
+++ b/hw/peach/v1/expected_response.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _EXPECTED_RESPONSE_H_
+#define _EXPECTED_RESPONSE_H_
+
+#define NUM_OF_DWORDS_EXPECTED_RESPONSE 5
+
+struct expected_response {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_ad2_31_0                                             : 32;
+             uint32_t tx_ad2_47_32                                            : 16,
+                      expected_response_type                                  :  5,
+                      response_to_response                                    :  3,
+                      su_ba_user_number                                       :  1,
+                      response_info_part2_required                            :  1,
+                      transmitted_bssid_check_en                              :  1,
+                      reserved_1                                              :  5;
+             uint32_t ndp_sta_partial_aid_2_8_0                               : 11,
+                      reserved_2                                              : 10,
+                      ndp_sta_partial_aid1_8_0                                : 11;
+             uint32_t ast_index                                               : 16,
+                      capture_ack_ba_sounding                                 :  1,
+                      capture_sounding_1str_20mhz                             :  1,
+                      capture_sounding_1str_40mhz                             :  1,
+                      capture_sounding_1str_80mhz                             :  1,
+                      capture_sounding_1str_160mhz                            :  1,
+                      capture_sounding_1str_240mhz                            :  1,
+                      capture_sounding_1str_320mhz                            :  1,
+                      reserved_3a                                             :  9;
+             uint32_t fcs                                                     :  9,
+                      reserved_4a                                             :  1,
+                      crc                                                     :  4,
+                      scrambler_seed                                          :  7,
+                      reserved_4b                                             : 11;
+#else
+             uint32_t tx_ad2_31_0                                             : 32;
+             uint32_t reserved_1                                              :  5,
+                      transmitted_bssid_check_en                              :  1,
+                      response_info_part2_required                            :  1,
+                      su_ba_user_number                                       :  1,
+                      response_to_response                                    :  3,
+                      expected_response_type                                  :  5,
+                      tx_ad2_47_32                                            : 16;
+             uint32_t ndp_sta_partial_aid1_8_0                                : 11,
+                      reserved_2                                              : 10,
+                      ndp_sta_partial_aid_2_8_0                               : 11;
+             uint32_t reserved_3a                                             :  9,
+                      capture_sounding_1str_320mhz                            :  1,
+                      capture_sounding_1str_240mhz                            :  1,
+                      capture_sounding_1str_160mhz                            :  1,
+                      capture_sounding_1str_80mhz                             :  1,
+                      capture_sounding_1str_40mhz                             :  1,
+                      capture_sounding_1str_20mhz                             :  1,
+                      capture_ack_ba_sounding                                 :  1,
+                      ast_index                                               : 16;
+             uint32_t reserved_4b                                             : 11,
+                      scrambler_seed                                          :  7,
+                      crc                                                     :  4,
+                      reserved_4a                                             :  1,
+                      fcs                                                     :  9;
+#endif
+};
+
+#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET                                        0x00000000
+#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB                                           0
+#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB                                           31
+#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK                                          0xffffffff
+
+#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET                                       0x00000004
+#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB                                          0
+#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB                                          15
+#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK                                         0x0000ffff
+
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET                             0x00000004
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB                                16
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB                                20
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK                               0x001f0000
+
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET                               0x00000004
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB                                  21
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB                                  23
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK                                 0x00e00000
+
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET                                  0x00000004
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB                                     24
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB                                     24
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK                                    0x01000000
+
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET                       0x00000004
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB                          25
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB                          25
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK                         0x02000000
+
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET                         0x00000004
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB                            26
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB                            26
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK                           0x04000000
+
+#define EXPECTED_RESPONSE_RESERVED_1_OFFSET                                         0x00000004
+#define EXPECTED_RESPONSE_RESERVED_1_LSB                                            27
+#define EXPECTED_RESPONSE_RESERVED_1_MSB                                            31
+#define EXPECTED_RESPONSE_RESERVED_1_MASK                                           0xf8000000
+
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET                          0x00000008
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB                             0
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB                             10
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK                            0x000007ff
+
+#define EXPECTED_RESPONSE_RESERVED_2_OFFSET                                         0x00000008
+#define EXPECTED_RESPONSE_RESERVED_2_LSB                                            11
+#define EXPECTED_RESPONSE_RESERVED_2_MSB                                            20
+#define EXPECTED_RESPONSE_RESERVED_2_MASK                                           0x001ff800
+
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET                           0x00000008
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB                              21
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB                              31
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK                             0xffe00000
+
+#define EXPECTED_RESPONSE_AST_INDEX_OFFSET                                          0x0000000c
+#define EXPECTED_RESPONSE_AST_INDEX_LSB                                             0
+#define EXPECTED_RESPONSE_AST_INDEX_MSB                                             15
+#define EXPECTED_RESPONSE_AST_INDEX_MASK                                            0x0000ffff
+
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET                            0x0000000c
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB                               16
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB                               16
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK                              0x00010000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET                        0x0000000c
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB                           17
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB                           17
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK                          0x00020000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET                        0x0000000c
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB                           18
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB                           18
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK                          0x00040000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET                        0x0000000c
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB                           19
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB                           19
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK                          0x00080000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET                       0x0000000c
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB                          20
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB                          20
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK                         0x00100000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET                       0x0000000c
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB                          21
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB                          21
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK                         0x00200000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET                       0x0000000c
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB                          22
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB                          22
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK                         0x00400000
+
+#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET                                        0x0000000c
+#define EXPECTED_RESPONSE_RESERVED_3A_LSB                                           23
+#define EXPECTED_RESPONSE_RESERVED_3A_MSB                                           31
+#define EXPECTED_RESPONSE_RESERVED_3A_MASK                                          0xff800000
+
+#define EXPECTED_RESPONSE_FCS_OFFSET                                                0x00000010
+#define EXPECTED_RESPONSE_FCS_LSB                                                   0
+#define EXPECTED_RESPONSE_FCS_MSB                                                   8
+#define EXPECTED_RESPONSE_FCS_MASK                                                  0x000001ff
+
+#define EXPECTED_RESPONSE_RESERVED_4A_OFFSET                                        0x00000010
+#define EXPECTED_RESPONSE_RESERVED_4A_LSB                                           9
+#define EXPECTED_RESPONSE_RESERVED_4A_MSB                                           9
+#define EXPECTED_RESPONSE_RESERVED_4A_MASK                                          0x00000200
+
+#define EXPECTED_RESPONSE_CRC_OFFSET                                                0x00000010
+#define EXPECTED_RESPONSE_CRC_LSB                                                   10
+#define EXPECTED_RESPONSE_CRC_MSB                                                   13
+#define EXPECTED_RESPONSE_CRC_MASK                                                  0x00003c00
+
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET                                     0x00000010
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB                                        14
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB                                        20
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK                                       0x001fc000
+
+#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET                                        0x00000010
+#define EXPECTED_RESPONSE_RESERVED_4B_LSB                                           21
+#define EXPECTED_RESPONSE_RESERVED_4B_MSB                                           31
+#define EXPECTED_RESPONSE_RESERVED_4B_MASK                                          0xffe00000
+
+#endif
diff --git a/hw/peach/v1/he_sig_a_mu_dl_info.h b/hw/peach/v1/he_sig_a_mu_dl_info.h
new file mode 100644
index 000000000000..6c5c1c293aa5
--- /dev/null
+++ b/hw/peach/v1/he_sig_a_mu_dl_info.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _HE_SIG_A_MU_DL_INFO_H_
+#define _HE_SIG_A_MU_DL_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2
+
+struct he_sig_a_mu_dl_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t dl_ul_flag                                              :  1,
+                      mcs_of_sig_b                                            :  3,
+                      dcm_of_sig_b                                            :  1,
+                      bss_color_id                                            :  6,
+                      spatial_reuse                                           :  4,
+                      transmit_bw                                             :  3,
+                      num_sig_b_symbols                                       :  4,
+                      comp_mode_sig_b                                         :  1,
+                      cp_ltf_size                                             :  2,
+                      doppler_indication                                      :  1,
+                      reserved_0a                                             :  6;
+             uint32_t txop_duration                                           :  7,
+                      reserved_1a                                             :  1,
+                      num_ltf_symbols                                         :  3,
+                      ldpc_extra_symbol                                       :  1,
+                      stbc                                                    :  1,
+                      packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_1b                                             :  5,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0a                                             :  6,
+                      doppler_indication                                      :  1,
+                      cp_ltf_size                                             :  2,
+                      comp_mode_sig_b                                         :  1,
+                      num_sig_b_symbols                                       :  4,
+                      transmit_bw                                             :  3,
+                      spatial_reuse                                           :  4,
+                      bss_color_id                                            :  6,
+                      dcm_of_sig_b                                            :  1,
+                      mcs_of_sig_b                                            :  3,
+                      dl_ul_flag                                              :  1;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1b                                             :  5,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2,
+                      stbc                                                    :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      num_ltf_symbols                                         :  3,
+                      reserved_1a                                             :  1,
+                      txop_duration                                           :  7;
+#endif
+};
+
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET                                       0x00000000
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB                                          0
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB                                          0
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK                                         0x00000001
+
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB                                        1
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB                                        3
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK                                       0x0000000e
+
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB                                        4
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB                                        4
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK                                       0x00000010
+
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB                                        5
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB                                        10
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK                                       0x000007e0
+
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET                                    0x00000000
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB                                       11
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB                                       14
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK                                      0x00007800
+
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB                                         15
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB                                         17
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK                                        0x00038000
+
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET                                0x00000000
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB                                   18
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB                                   21
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK                                  0x003c0000
+
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET                                  0x00000000
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB                                     22
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB                                     22
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK                                    0x00400000
+
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB                                         23
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB                                         24
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK                                        0x01800000
+
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET                               0x00000000
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB                                  25
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB                                  25
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK                                 0x02000000
+
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB                                         26
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB                                         31
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK                                        0xfc000000
+
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET                                    0x00000004
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB                                       0
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB                                       6
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK                                      0x0000007f
+
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB                                         7
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB                                         7
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK                                        0x00000080
+
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET                                  0x00000004
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB                                     8
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB                                     10
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK                                    0x00000700
+
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET                                0x00000004
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB                                   11
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB                                   11
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK                                  0x00000800
+
+#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET                                             0x00000004
+#define HE_SIG_A_MU_DL_INFO_STBC_LSB                                                12
+#define HE_SIG_A_MU_DL_INFO_STBC_MSB                                                12
+#define HE_SIG_A_MU_DL_INFO_STBC_MASK                                               0x00001000
+
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET                        0x00000004
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB                           13
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB                           14
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK                          0x00006000
+
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET                 0x00000004
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                    15
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                    15
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                   0x00008000
+
+#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET                                              0x00000004
+#define HE_SIG_A_MU_DL_INFO_CRC_LSB                                                 16
+#define HE_SIG_A_MU_DL_INFO_CRC_MSB                                                 19
+#define HE_SIG_A_MU_DL_INFO_CRC_MASK                                                0x000f0000
+
+#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET                                             0x00000004
+#define HE_SIG_A_MU_DL_INFO_TAIL_LSB                                                20
+#define HE_SIG_A_MU_DL_INFO_TAIL_MSB                                                25
+#define HE_SIG_A_MU_DL_INFO_TAIL_MASK                                               0x03f00000
+
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB                                         26
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB                                         30
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK                                        0x7c000000
+
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000004
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
+
+#endif
diff --git a/hw/peach/v1/he_sig_a_mu_ul_info.h b/hw/peach/v1/he_sig_a_mu_ul_info.h
new file mode 100644
index 000000000000..947a6f8e2cba
--- /dev/null
+++ b/hw/peach/v1/he_sig_a_mu_ul_info.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _HE_SIG_A_MU_UL_INFO_H_
+#define _HE_SIG_A_MU_UL_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
+
+struct he_sig_a_mu_ul_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t format_indication                                       :  1,
+                      bss_color_id                                            :  6,
+                      spatial_reuse                                           : 16,
+                      reserved_0a                                             :  1,
+                      transmit_bw                                             :  2,
+                      reserved_0b                                             :  6;
+             uint32_t txop_duration                                           :  7,
+                      reserved_1a                                             :  9,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_1b                                             :  5,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0b                                             :  6,
+                      transmit_bw                                             :  2,
+                      reserved_0a                                             :  1,
+                      spatial_reuse                                           : 16,
+                      bss_color_id                                            :  6,
+                      format_indication                                       :  1;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1b                                             :  5,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      reserved_1a                                             :  9,
+                      txop_duration                                           :  7;
+#endif
+};
+
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET                                0x00000000
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB                                   0
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB                                   0
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK                                  0x00000001
+
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET                                     0x00000000
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB                                        1
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB                                        6
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK                                       0x0000007e
+
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET                                    0x00000000
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB                                       7
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB                                       22
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK                                      0x007fff80
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB                                         23
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB                                         23
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK                                        0x00800000
+
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB                                         24
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB                                         25
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK                                        0x03000000
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET                                      0x00000000
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB                                         26
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB                                         31
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK                                        0xfc000000
+
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET                                    0x00000004
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB                                       0
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB                                       6
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK                                      0x0000007f
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB                                         7
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB                                         15
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK                                        0x0000ff80
+
+#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET                                              0x00000004
+#define HE_SIG_A_MU_UL_INFO_CRC_LSB                                                 16
+#define HE_SIG_A_MU_UL_INFO_CRC_MSB                                                 19
+#define HE_SIG_A_MU_UL_INFO_CRC_MASK                                                0x000f0000
+
+#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET                                             0x00000004
+#define HE_SIG_A_MU_UL_INFO_TAIL_LSB                                                20
+#define HE_SIG_A_MU_UL_INFO_TAIL_MSB                                                25
+#define HE_SIG_A_MU_UL_INFO_TAIL_MASK                                               0x03f00000
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET                                      0x00000004
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB                                         26
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB                                         30
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK                                        0x7c000000
+
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                        0x00000004
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                           31
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                           31
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                          0x80000000
+
+#endif
diff --git a/hw/peach/v1/he_sig_a_su_info.h b/hw/peach/v1/he_sig_a_su_info.h
new file mode 100644
index 000000000000..c82cc61e966d
--- /dev/null
+++ b/hw/peach/v1/he_sig_a_su_info.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _HE_SIG_A_SU_INFO_H_
+#define _HE_SIG_A_SU_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2
+
+struct he_sig_a_su_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t format_indication                                       :  1,
+                      beam_change                                             :  1,
+                      dl_ul_flag                                              :  1,
+                      transmit_mcs                                            :  4,
+                      dcm                                                     :  1,
+                      bss_color_id                                            :  6,
+                      reserved_0a                                             :  1,
+                      spatial_reuse                                           :  4,
+                      transmit_bw                                             :  2,
+                      cp_ltf_size                                             :  2,
+                      nsts                                                    :  3,
+                      reserved_0b                                             :  6;
+             uint32_t txop_duration                                           :  7,
+                      coding                                                  :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      stbc                                                    :  1,
+                      txbf                                                    :  1,
+                      packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      reserved_1a                                             :  1,
+                      doppler_indication                                      :  1,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_ext_ru_size                                     :  3,
+                      rx_ndp                                                  :  1,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0b                                             :  6,
+                      nsts                                                    :  3,
+                      cp_ltf_size                                             :  2,
+                      transmit_bw                                             :  2,
+                      spatial_reuse                                           :  4,
+                      reserved_0a                                             :  1,
+                      bss_color_id                                            :  6,
+                      dcm                                                     :  1,
+                      transmit_mcs                                            :  4,
+                      dl_ul_flag                                              :  1,
+                      beam_change                                             :  1,
+                      format_indication                                       :  1;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      rx_ndp                                                  :  1,
+                      dot11ax_ext_ru_size                                     :  3,
+                      dot11ax_su_extended                                     :  1,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      doppler_indication                                      :  1,
+                      reserved_1a                                             :  1,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2,
+                      txbf                                                    :  1,
+                      stbc                                                    :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      coding                                                  :  1,
+                      txop_duration                                           :  7;
+#endif
+};
+
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET                                   0x00000000
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB                                      0
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB                                      0
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK                                     0x00000001
+
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB                                            1
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB                                            1
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK                                           0x00000002
+
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET                                          0x00000000
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB                                             2
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB                                             2
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK                                            0x00000004
+
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET                                        0x00000000
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB                                           3
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB                                           6
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK                                          0x00000078
+
+#define HE_SIG_A_SU_INFO_DCM_OFFSET                                                 0x00000000
+#define HE_SIG_A_SU_INFO_DCM_LSB                                                    7
+#define HE_SIG_A_SU_INFO_DCM_MSB                                                    7
+#define HE_SIG_A_SU_INFO_DCM_MASK                                                   0x00000080
+
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET                                        0x00000000
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB                                           8
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB                                           13
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK                                          0x00003f00
+
+#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK                                           0x00004000
+
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET                                       0x00000000
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB                                          15
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB                                          18
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK                                         0x00078000
+
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB                                            19
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB                                            20
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK                                           0x00180000
+
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB                                            21
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB                                            22
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK                                           0x00600000
+
+#define HE_SIG_A_SU_INFO_NSTS_OFFSET                                                0x00000000
+#define HE_SIG_A_SU_INFO_NSTS_LSB                                                   23
+#define HE_SIG_A_SU_INFO_NSTS_MSB                                                   25
+#define HE_SIG_A_SU_INFO_NSTS_MASK                                                  0x03800000
+
+#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET                                         0x00000000
+#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB                                            26
+#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB                                            31
+#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK                                           0xfc000000
+
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET                                       0x00000004
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB                                          0
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB                                          6
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK                                         0x0000007f
+
+#define HE_SIG_A_SU_INFO_CODING_OFFSET                                              0x00000004
+#define HE_SIG_A_SU_INFO_CODING_LSB                                                 7
+#define HE_SIG_A_SU_INFO_CODING_MSB                                                 7
+#define HE_SIG_A_SU_INFO_CODING_MASK                                                0x00000080
+
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET                                   0x00000004
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB                                      8
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB                                      8
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK                                     0x00000100
+
+#define HE_SIG_A_SU_INFO_STBC_OFFSET                                                0x00000004
+#define HE_SIG_A_SU_INFO_STBC_LSB                                                   9
+#define HE_SIG_A_SU_INFO_STBC_MSB                                                   9
+#define HE_SIG_A_SU_INFO_STBC_MASK                                                  0x00000200
+
+#define HE_SIG_A_SU_INFO_TXBF_OFFSET                                                0x00000004
+#define HE_SIG_A_SU_INFO_TXBF_LSB                                                   10
+#define HE_SIG_A_SU_INFO_TXBF_MSB                                                   10
+#define HE_SIG_A_SU_INFO_TXBF_MASK                                                  0x00000400
+
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET                           0x00000004
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB                              11
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB                              12
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK                             0x00001800
+
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET                    0x00000004
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                       13
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                       13
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                      0x00002000
+
+#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET                                         0x00000004
+#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB                                            14
+#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK                                           0x00004000
+
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET                                  0x00000004
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB                                     15
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB                                     15
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK                                    0x00008000
+
+#define HE_SIG_A_SU_INFO_CRC_OFFSET                                                 0x00000004
+#define HE_SIG_A_SU_INFO_CRC_LSB                                                    16
+#define HE_SIG_A_SU_INFO_CRC_MSB                                                    19
+#define HE_SIG_A_SU_INFO_CRC_MASK                                                   0x000f0000
+
+#define HE_SIG_A_SU_INFO_TAIL_OFFSET                                                0x00000004
+#define HE_SIG_A_SU_INFO_TAIL_LSB                                                   20
+#define HE_SIG_A_SU_INFO_TAIL_MSB                                                   25
+#define HE_SIG_A_SU_INFO_TAIL_MASK                                                  0x03f00000
+
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET                                 0x00000004
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB                                    26
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB                                    26
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK                                   0x04000000
+
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET                                 0x00000004
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB                                    27
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB                                    29
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK                                   0x38000000
+
+#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET                                              0x00000004
+#define HE_SIG_A_SU_INFO_RX_NDP_LSB                                                 30
+#define HE_SIG_A_SU_INFO_RX_NDP_MSB                                                 30
+#define HE_SIG_A_SU_INFO_RX_NDP_MASK                                                0x40000000
+
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                           0x00000004
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                              31
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                              31
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                             0x80000000
+
+#endif
diff --git a/hw/peach/v1/he_sig_b1_mu_info.h b/hw/peach/v1/he_sig_b1_mu_info.h
new file mode 100644
index 000000000000..2cb4633311a5
--- /dev/null
+++ b/hw/peach/v1/he_sig_b1_mu_info.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _HE_SIG_B1_MU_INFO_H_
+#define _HE_SIG_B1_MU_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
+
+struct he_sig_b1_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ru_allocation                                           :  8,
+                      reserved_0                                              : 23,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_0                                              : 23,
+                      ru_allocation                                           :  8;
+#endif
+};
+
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET                                      0x00000000
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB                                         0
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB                                         7
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK                                        0x000000ff
+
+#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET                                         0x00000000
+#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB                                            8
+#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB                                            30
+#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK                                           0x7fffff00
+
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000000
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
+
+#endif
diff --git a/hw/peach/v1/he_sig_b2_mu_info.h b/hw/peach/v1/he_sig_b2_mu_info.h
new file mode 100644
index 000000000000..8f198333aa7e
--- /dev/null
+++ b/hw/peach/v1/he_sig_b2_mu_info.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _HE_SIG_B2_MU_INFO_H_
+#define _HE_SIG_B2_MU_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2
+
+struct he_sig_b2_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      sta_spatial_config                                      :  4,
+                      sta_mcs                                                 :  4,
+                      reserved_set_to_1                                       :  1,
+                      sta_coding                                              :  1,
+                      reserved_0a                                             :  7,
+                      nsts                                                    :  3,
+                      rx_integrity_check_passed                               :  1;
+             uint32_t user_order                                              :  8,
+                      cc_mask                                                 :  8,
+                      reserved_1a                                             : 16;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      nsts                                                    :  3,
+                      reserved_0a                                             :  7,
+                      sta_coding                                              :  1,
+                      reserved_set_to_1                                       :  1,
+                      sta_mcs                                                 :  4,
+                      sta_spatial_config                                      :  4,
+                      sta_id                                                  : 11;
+             uint32_t reserved_1a                                             : 16,
+                      cc_mask                                                 :  8,
+                      user_order                                              :  8;
+#endif
+};
+
+#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET                                             0x00000000
+#define HE_SIG_B2_MU_INFO_STA_ID_LSB                                                0
+#define HE_SIG_B2_MU_INFO_STA_ID_MSB                                                10
+#define HE_SIG_B2_MU_INFO_STA_ID_MASK                                               0x000007ff
+
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET                                 0x00000000
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB                                    11
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB                                    14
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK                                   0x00007800
+
+#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET                                            0x00000000
+#define HE_SIG_B2_MU_INFO_STA_MCS_LSB                                               15
+#define HE_SIG_B2_MU_INFO_STA_MCS_MSB                                               18
+#define HE_SIG_B2_MU_INFO_STA_MCS_MASK                                              0x00078000
+
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET                                  0x00000000
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB                                     19
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB                                     19
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK                                    0x00080000
+
+#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET                                         0x00000000
+#define HE_SIG_B2_MU_INFO_STA_CODING_LSB                                            20
+#define HE_SIG_B2_MU_INFO_STA_CODING_MSB                                            20
+#define HE_SIG_B2_MU_INFO_STA_CODING_MASK                                           0x00100000
+
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET                                        0x00000000
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB                                           21
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB                                           27
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK                                          0x0fe00000
+
+#define HE_SIG_B2_MU_INFO_NSTS_OFFSET                                               0x00000000
+#define HE_SIG_B2_MU_INFO_NSTS_LSB                                                  28
+#define HE_SIG_B2_MU_INFO_NSTS_MSB                                                  30
+#define HE_SIG_B2_MU_INFO_NSTS_MASK                                                 0x70000000
+
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000000
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
+
+#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET                                         0x00000004
+#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB                                            0
+#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB                                            7
+#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK                                           0x000000ff
+
+#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET                                            0x00000004
+#define HE_SIG_B2_MU_INFO_CC_MASK_LSB                                               8
+#define HE_SIG_B2_MU_INFO_CC_MASK_MSB                                               15
+#define HE_SIG_B2_MU_INFO_CC_MASK_MASK                                              0x0000ff00
+
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET                                        0x00000004
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB                                           16
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB                                           31
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK                                          0xffff0000
+
+#endif
diff --git a/hw/peach/v1/he_sig_b2_ofdma_info.h b/hw/peach/v1/he_sig_b2_ofdma_info.h
new file mode 100644
index 000000000000..9cb9d4228ebf
--- /dev/null
+++ b/hw/peach/v1/he_sig_b2_ofdma_info.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _HE_SIG_B2_OFDMA_INFO_H_
+#define _HE_SIG_B2_OFDMA_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2
+
+struct he_sig_b2_ofdma_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sta_id                                                  : 11,
+                      nsts                                                    :  3,
+                      txbf                                                    :  1,
+                      sta_mcs                                                 :  4,
+                      sta_dcm                                                 :  1,
+                      sta_coding                                              :  1,
+                      reserved_0                                              : 10,
+                      rx_integrity_check_passed                               :  1;
+             uint32_t user_order                                              :  8,
+                      cc_mask                                                 :  8,
+                      reserved_1a                                             : 16;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_0                                              : 10,
+                      sta_coding                                              :  1,
+                      sta_dcm                                                 :  1,
+                      sta_mcs                                                 :  4,
+                      txbf                                                    :  1,
+                      nsts                                                    :  3,
+                      sta_id                                                  : 11;
+             uint32_t reserved_1a                                             : 16,
+                      cc_mask                                                 :  8,
+                      user_order                                              :  8;
+#endif
+};
+
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET                                          0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB                                             0
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB                                             10
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK                                            0x000007ff
+
+#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET                                            0x00000000
+#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB                                               11
+#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB                                               13
+#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK                                              0x00003800
+
+#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET                                            0x00000000
+#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB                                               14
+#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB                                               14
+#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK                                              0x00004000
+
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET                                         0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB                                            15
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB                                            18
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK                                           0x00078000
+
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET                                         0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB                                            19
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB                                            19
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK                                           0x00080000
+
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET                                      0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB                                         20
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB                                         20
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK                                        0x00100000
+
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET                                      0x00000000
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB                                         21
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB                                         30
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK                                        0x7fe00000
+
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                       0x00000000
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                          31
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                          31
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                         0x80000000
+
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET                                      0x00000004
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB                                         0
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB                                         7
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK                                        0x000000ff
+
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET                                         0x00000004
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB                                            8
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB                                            15
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK                                           0x0000ff00
+
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET                                     0x00000004
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB                                        16
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB                                        31
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK                                       0xffff0000
+
+#endif
diff --git a/hw/peach/v1/ht_sig_info.h b/hw/peach/v1/ht_sig_info.h
new file mode 100644
index 000000000000..faf40148e6f4
--- /dev/null
+++ b/hw/peach/v1/ht_sig_info.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _HT_SIG_INFO_H_
+#define _HT_SIG_INFO_H_
+
+#define NUM_OF_DWORDS_HT_SIG_INFO 2
+
+struct ht_sig_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mcs                                                     :  7,
+                      cbw                                                     :  1,
+                      length                                                  : 16,
+                      reserved_0                                              :  8;
+             uint32_t smoothing                                               :  1,
+                      not_sounding                                            :  1,
+                      ht_reserved                                             :  1,
+                      aggregation                                             :  1,
+                      stbc                                                    :  2,
+                      fec_coding                                              :  1,
+                      short_gi                                                :  1,
+                      num_ext_sp_str                                          :  2,
+                      crc                                                     :  8,
+                      signal_tail                                             :  6,
+                      reserved_1                                              :  7,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0                                              :  8,
+                      length                                                  : 16,
+                      cbw                                                     :  1,
+                      mcs                                                     :  7;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1                                              :  7,
+                      signal_tail                                             :  6,
+                      crc                                                     :  8,
+                      num_ext_sp_str                                          :  2,
+                      short_gi                                                :  1,
+                      fec_coding                                              :  1,
+                      stbc                                                    :  2,
+                      aggregation                                             :  1,
+                      ht_reserved                                             :  1,
+                      not_sounding                                            :  1,
+                      smoothing                                               :  1;
+#endif
+};
+
+#define HT_SIG_INFO_MCS_OFFSET                                                      0x00000000
+#define HT_SIG_INFO_MCS_LSB                                                         0
+#define HT_SIG_INFO_MCS_MSB                                                         6
+#define HT_SIG_INFO_MCS_MASK                                                        0x0000007f
+
+#define HT_SIG_INFO_CBW_OFFSET                                                      0x00000000
+#define HT_SIG_INFO_CBW_LSB                                                         7
+#define HT_SIG_INFO_CBW_MSB                                                         7
+#define HT_SIG_INFO_CBW_MASK                                                        0x00000080
+
+#define HT_SIG_INFO_LENGTH_OFFSET                                                   0x00000000
+#define HT_SIG_INFO_LENGTH_LSB                                                      8
+#define HT_SIG_INFO_LENGTH_MSB                                                      23
+#define HT_SIG_INFO_LENGTH_MASK                                                     0x00ffff00
+
+#define HT_SIG_INFO_RESERVED_0_OFFSET                                               0x00000000
+#define HT_SIG_INFO_RESERVED_0_LSB                                                  24
+#define HT_SIG_INFO_RESERVED_0_MSB                                                  31
+#define HT_SIG_INFO_RESERVED_0_MASK                                                 0xff000000
+
+#define HT_SIG_INFO_SMOOTHING_OFFSET                                                0x00000004
+#define HT_SIG_INFO_SMOOTHING_LSB                                                   0
+#define HT_SIG_INFO_SMOOTHING_MSB                                                   0
+#define HT_SIG_INFO_SMOOTHING_MASK                                                  0x00000001
+
+#define HT_SIG_INFO_NOT_SOUNDING_OFFSET                                             0x00000004
+#define HT_SIG_INFO_NOT_SOUNDING_LSB                                                1
+#define HT_SIG_INFO_NOT_SOUNDING_MSB                                                1
+#define HT_SIG_INFO_NOT_SOUNDING_MASK                                               0x00000002
+
+#define HT_SIG_INFO_HT_RESERVED_OFFSET                                              0x00000004
+#define HT_SIG_INFO_HT_RESERVED_LSB                                                 2
+#define HT_SIG_INFO_HT_RESERVED_MSB                                                 2
+#define HT_SIG_INFO_HT_RESERVED_MASK                                                0x00000004
+
+#define HT_SIG_INFO_AGGREGATION_OFFSET                                              0x00000004
+#define HT_SIG_INFO_AGGREGATION_LSB                                                 3
+#define HT_SIG_INFO_AGGREGATION_MSB                                                 3
+#define HT_SIG_INFO_AGGREGATION_MASK                                                0x00000008
+
+#define HT_SIG_INFO_STBC_OFFSET                                                     0x00000004
+#define HT_SIG_INFO_STBC_LSB                                                        4
+#define HT_SIG_INFO_STBC_MSB                                                        5
+#define HT_SIG_INFO_STBC_MASK                                                       0x00000030
+
+#define HT_SIG_INFO_FEC_CODING_OFFSET                                               0x00000004
+#define HT_SIG_INFO_FEC_CODING_LSB                                                  6
+#define HT_SIG_INFO_FEC_CODING_MSB                                                  6
+#define HT_SIG_INFO_FEC_CODING_MASK                                                 0x00000040
+
+#define HT_SIG_INFO_SHORT_GI_OFFSET                                                 0x00000004
+#define HT_SIG_INFO_SHORT_GI_LSB                                                    7
+#define HT_SIG_INFO_SHORT_GI_MSB                                                    7
+#define HT_SIG_INFO_SHORT_GI_MASK                                                   0x00000080
+
+#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET                                           0x00000004
+#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB                                              8
+#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB                                              9
+#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK                                             0x00000300
+
+#define HT_SIG_INFO_CRC_OFFSET                                                      0x00000004
+#define HT_SIG_INFO_CRC_LSB                                                         10
+#define HT_SIG_INFO_CRC_MSB                                                         17
+#define HT_SIG_INFO_CRC_MASK                                                        0x0003fc00
+
+#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET                                              0x00000004
+#define HT_SIG_INFO_SIGNAL_TAIL_LSB                                                 18
+#define HT_SIG_INFO_SIGNAL_TAIL_MSB                                                 23
+#define HT_SIG_INFO_SIGNAL_TAIL_MASK                                                0x00fc0000
+
+#define HT_SIG_INFO_RESERVED_1_OFFSET                                               0x00000004
+#define HT_SIG_INFO_RESERVED_1_LSB                                                  24
+#define HT_SIG_INFO_RESERVED_1_MSB                                                  30
+#define HT_SIG_INFO_RESERVED_1_MASK                                                 0x7f000000
+
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                                0x00000004
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                   31
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                   31
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                                  0x80000000
+
+#endif
diff --git a/hw/peach/v1/l_sig_a_info.h b/hw/peach/v1/l_sig_a_info.h
new file mode 100644
index 000000000000..f6b1fbff5190
--- /dev/null
+++ b/hw/peach/v1/l_sig_a_info.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _L_SIG_A_INFO_H_
+#define _L_SIG_A_INFO_H_
+
+#define NUM_OF_DWORDS_L_SIG_A_INFO 1
+
+struct l_sig_a_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rate                                                    :  4,
+                      lsig_reserved                                           :  1,
+                      length                                                  : 12,
+                      parity                                                  :  1,
+                      tail                                                    :  6,
+                      pkt_type                                                :  4,
+                      captured_implicit_sounding                              :  1,
+                      reserved                                                :  2,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved                                                :  2,
+                      captured_implicit_sounding                              :  1,
+                      pkt_type                                                :  4,
+                      tail                                                    :  6,
+                      parity                                                  :  1,
+                      length                                                  : 12,
+                      lsig_reserved                                           :  1,
+                      rate                                                    :  4;
+#endif
+};
+
+#define L_SIG_A_INFO_RATE_OFFSET                                                    0x00000000
+#define L_SIG_A_INFO_RATE_LSB                                                       0
+#define L_SIG_A_INFO_RATE_MSB                                                       3
+#define L_SIG_A_INFO_RATE_MASK                                                      0x0000000f
+
+#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET                                           0x00000000
+#define L_SIG_A_INFO_LSIG_RESERVED_LSB                                              4
+#define L_SIG_A_INFO_LSIG_RESERVED_MSB                                              4
+#define L_SIG_A_INFO_LSIG_RESERVED_MASK                                             0x00000010
+
+#define L_SIG_A_INFO_LENGTH_OFFSET                                                  0x00000000
+#define L_SIG_A_INFO_LENGTH_LSB                                                     5
+#define L_SIG_A_INFO_LENGTH_MSB                                                     16
+#define L_SIG_A_INFO_LENGTH_MASK                                                    0x0001ffe0
+
+#define L_SIG_A_INFO_PARITY_OFFSET                                                  0x00000000
+#define L_SIG_A_INFO_PARITY_LSB                                                     17
+#define L_SIG_A_INFO_PARITY_MSB                                                     17
+#define L_SIG_A_INFO_PARITY_MASK                                                    0x00020000
+
+#define L_SIG_A_INFO_TAIL_OFFSET                                                    0x00000000
+#define L_SIG_A_INFO_TAIL_LSB                                                       18
+#define L_SIG_A_INFO_TAIL_MSB                                                       23
+#define L_SIG_A_INFO_TAIL_MASK                                                      0x00fc0000
+
+#define L_SIG_A_INFO_PKT_TYPE_OFFSET                                                0x00000000
+#define L_SIG_A_INFO_PKT_TYPE_LSB                                                   24
+#define L_SIG_A_INFO_PKT_TYPE_MSB                                                   27
+#define L_SIG_A_INFO_PKT_TYPE_MASK                                                  0x0f000000
+
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET                              0x00000000
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB                                 28
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB                                 28
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK                                0x10000000
+
+#define L_SIG_A_INFO_RESERVED_OFFSET                                                0x00000000
+#define L_SIG_A_INFO_RESERVED_LSB                                                   29
+#define L_SIG_A_INFO_RESERVED_MSB                                                   30
+#define L_SIG_A_INFO_RESERVED_MASK                                                  0x60000000
+
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                               0x00000000
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                  31
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                  31
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                                 0x80000000
+
+#endif
diff --git a/hw/peach/v1/l_sig_b_info.h b/hw/peach/v1/l_sig_b_info.h
new file mode 100644
index 000000000000..c6f0f3a0cadc
--- /dev/null
+++ b/hw/peach/v1/l_sig_b_info.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _L_SIG_B_INFO_H_
+#define _L_SIG_B_INFO_H_
+
+#define NUM_OF_DWORDS_L_SIG_B_INFO 1
+
+struct l_sig_b_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rate                                                    :  4,
+                      length                                                  : 12,
+                      reserved                                                : 15,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved                                                : 15,
+                      length                                                  : 12,
+                      rate                                                    :  4;
+#endif
+};
+
+#define L_SIG_B_INFO_RATE_OFFSET                                                    0x00000000
+#define L_SIG_B_INFO_RATE_LSB                                                       0
+#define L_SIG_B_INFO_RATE_MSB                                                       3
+#define L_SIG_B_INFO_RATE_MASK                                                      0x0000000f
+
+#define L_SIG_B_INFO_LENGTH_OFFSET                                                  0x00000000
+#define L_SIG_B_INFO_LENGTH_LSB                                                     4
+#define L_SIG_B_INFO_LENGTH_MSB                                                     15
+#define L_SIG_B_INFO_LENGTH_MASK                                                    0x0000fff0
+
+#define L_SIG_B_INFO_RESERVED_OFFSET                                                0x00000000
+#define L_SIG_B_INFO_RESERVED_LSB                                                   16
+#define L_SIG_B_INFO_RESERVED_MSB                                                   30
+#define L_SIG_B_INFO_RESERVED_MASK                                                  0x7fff0000
+
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                               0x00000000
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                  31
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                  31
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                                 0x80000000
+
+#endif
diff --git a/hw/peach/v1/macrx_abort_request_info.h b/hw/peach/v1/macrx_abort_request_info.h
new file mode 100644
index 000000000000..197f4e5d41ee
--- /dev/null
+++ b/hw/peach/v1/macrx_abort_request_info.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACRX_ABORT_REQUEST_INFO_H_
+#define _MACRX_ABORT_REQUEST_INFO_H_
+
+#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1
+
+struct macrx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t macrx_abort_reason                                      :  8,
+                      reserved_0                                              :  8;
+#else
+             uint16_t reserved_0                                              :  8,
+                      macrx_abort_reason                                      :  8;
+#endif
+};
+
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET                          0x00000000
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB                             0
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB                             7
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK                            0x000000ff
+
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET                                  0x00000000
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB                                     8
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB                                     15
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK                                    0x0000ff00
+
+#endif
diff --git a/hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h b/hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h
new file mode 100644
index 000000000000..c9c7f41822f9
--- /dev/null
+++ b/hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_
+#define _MACTX_EHT_SIG_USR_MU_MIMO_H_
+
+#include "eht_sig_usr_mu_mimo_info.h"
+#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2
+
+struct mactx_eht_sig_usr_mu_mimo {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   eht_sig_usr_mu_mimo_info                                  mactx_eht_sig_usr_mu_mimo_info_details;
+#else
+             struct   eht_sig_usr_mu_mimo_info                                  mactx_eht_sig_usr_mu_mimo_info_details;
+#endif
+};
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x000007ff
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x00007800
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x00008000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x003f0000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x00400000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0xff000000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 0
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 7
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 8
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 15
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 16
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 23
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 24
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 31
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff000000
+
+#endif
diff --git a/hw/peach/v1/mactx_eht_sig_usr_ofdma.h b/hw/peach/v1/mactx_eht_sig_usr_ofdma.h
new file mode 100644
index 000000000000..98d98d500a9f
--- /dev/null
+++ b/hw/peach/v1/mactx_eht_sig_usr_ofdma.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_
+#define _MACTX_EHT_SIG_USR_OFDMA_H_
+
+#include "eht_sig_usr_ofdma_info.h"
+#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2
+
+struct mactx_eht_sig_usr_ofdma {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   eht_sig_usr_ofdma_info                                    mactx_eht_sig_usr_ofdma_info_details;
+#else
+             struct   eht_sig_usr_ofdma_info                                    mactx_eht_sig_usr_ofdma_info_details;
+#endif
+};
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET  0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB     0
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB     10
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK    0x000007ff
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB    11
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB    14
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK   0x00007800
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x00008000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET     0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB        16
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB        19
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK       0x000f0000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET    0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB       20
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB       20
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK      0x00100000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00200000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x00400000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0xff000000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 0
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 7
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 8
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 15
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 16
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 23
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 24
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 31
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff000000
+
+#endif
diff --git a/hw/peach/v1/mactx_eht_sig_usr_su.h b/hw/peach/v1/mactx_eht_sig_usr_su.h
new file mode 100644
index 000000000000..aaef05617272
--- /dev/null
+++ b/hw/peach/v1/mactx_eht_sig_usr_su.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_EHT_SIG_USR_SU_H_
+#define _MACTX_EHT_SIG_USR_SU_H_
+
+#include "eht_sig_usr_su_info.h"
+#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 1
+
+struct mactx_eht_sig_usr_su {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   eht_sig_usr_su_info                                       mactx_eht_sig_usr_su_info_details;
+#else
+             struct   eht_sig_usr_su_info                                       mactx_eht_sig_usr_su_info_details;
+#endif
+};
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET        0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB           0
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB           10
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK          0x000007ff
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET       0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB          11
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB          14
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK         0x00007800
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET   0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB      15
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB      15
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK     0x00008000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET           0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB              16
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB              19
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK             0x000f0000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET          0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB             20
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB             20
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK            0x00100000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET    0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB       21
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB       21
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK      0x00200000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET   0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB      22
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB      30
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK     0x7fc00000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/hw/peach/v1/mactx_he_sig_a_mu_dl.h b/hw/peach/v1/mactx_he_sig_a_mu_dl.h
new file mode 100644
index 000000000000..19db380bb473
--- /dev/null
+++ b/hw/peach/v1/mactx_he_sig_a_mu_dl.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_HE_SIG_A_MU_DL_H_
+#define _MACTX_HE_SIG_A_MU_DL_H_
+
+#include "he_sig_a_mu_dl_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2
+
+struct mactx_he_sig_a_mu_dl {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_dl_info                                       mactx_he_sig_a_mu_dl_info_details;
+#else
+             struct   he_sig_a_mu_dl_info                                       mactx_he_sig_a_mu_dl_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET    0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB       0
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB       0
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK      0x00000001
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET  0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB     1
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB     3
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK    0x0000000e
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET  0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB     4
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB     4
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK    0x00000010
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB     5
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB     10
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x000007e0
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB    11
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB    14
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x00007800
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB      15
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB      17
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK     0x00038000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB  22
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB  22
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET   0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB      23
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB      24
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK     0x01800000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET   0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB      26
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB      31
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK     0xfc000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB    0
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB    6
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET   0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB      7
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB      7
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK     0x00000080
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB  8
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB  10
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 11
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET          0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB             12
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB             12
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK            0x00001000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 14
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET           0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB              16
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB              19
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK             0x000f0000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET          0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB             20
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB             25
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK            0x03f00000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET   0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB      26
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB      30
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK     0x7c000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/hw/peach/v1/mactx_he_sig_a_mu_ul.h b/hw/peach/v1/mactx_he_sig_a_mu_ul.h
new file mode 100644
index 000000000000..ddc528393428
--- /dev/null
+++ b/hw/peach/v1/mactx_he_sig_a_mu_ul.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_HE_SIG_A_MU_UL_H_
+#define _MACTX_HE_SIG_A_MU_UL_H_
+
+#include "he_sig_a_mu_ul_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2
+
+struct mactx_he_sig_a_mu_ul {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_ul_info                                       mactx_he_sig_a_mu_ul_info_details;
+#else
+             struct   he_sig_a_mu_ul_info                                       mactx_he_sig_a_mu_ul_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x00000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB     1
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB     6
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x0000007e
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB    7
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB    22
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x007fff80
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET   0x00000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB      23
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB      23
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK     0x00800000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x00000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB      24
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB      25
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK     0x03000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET   0x00000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB      26
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB      31
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK     0xfc000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB    0
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB    6
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET   0x00000004
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB      7
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB      15
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK     0x0000ff80
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET           0x00000004
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB              16
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB              19
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK             0x000f0000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET          0x00000004
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB             20
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB             25
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK            0x03f00000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET   0x00000004
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB      26
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB      30
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK     0x7c000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/hw/peach/v1/mactx_he_sig_a_su.h b/hw/peach/v1/mactx_he_sig_a_su.h
new file mode 100644
index 000000000000..449e9bc875c4
--- /dev/null
+++ b/hw/peach/v1/mactx_he_sig_a_su.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_HE_SIG_A_SU_H_
+#define _MACTX_HE_SIG_A_SU_H_
+
+#include "he_sig_a_su_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2
+
+struct mactx_he_sig_a_su {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_su_info                                          mactx_he_sig_a_su_info_details;
+#else
+             struct   he_sig_a_su_info                                          mactx_he_sig_a_su_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET   0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB      0
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB      0
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK     0x00000001
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET         0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB            1
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB            1
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK           0x00000002
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET          0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB             2
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB             2
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK            0x00000004
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET        0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB           3
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB           6
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK          0x00000078
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET                 0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB                    7
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB                    7
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK                   0x00000080
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET        0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB           8
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB           13
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK          0x00003f00
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET         0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB            14
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB            14
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK           0x00004000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET       0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB          15
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB          18
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK         0x00078000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET         0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB            19
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB            20
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK           0x00180000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET         0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB            21
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB            22
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK           0x00600000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET                0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB                   23
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB                   25
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK                  0x03800000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET         0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB            26
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB            31
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK           0xfc000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET       0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB          0
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB          6
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK         0x0000007f
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET              0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB                 7
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB                 7
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK                0x00000080
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET   0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB      8
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB      8
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK     0x00000100
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET                0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB                   9
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB                   9
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK                  0x00000200
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET                0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB                   10
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB                   10
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK                  0x00000400
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 12
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET         0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB            14
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB            14
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK           0x00004000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET  0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB     15
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB     15
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK    0x00008000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET                 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB                    16
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB                    19
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK                   0x000f0000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET                0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB                   20
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB                   25
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK                  0x03f00000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB    26
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB    26
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK   0x04000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB    27
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB    29
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK   0x38000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET              0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB                 30
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB                 30
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK                0x40000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/hw/peach/v1/mactx_he_sig_b1_mu.h b/hw/peach/v1/mactx_he_sig_b1_mu.h
new file mode 100644
index 000000000000..177d7666b641
--- /dev/null
+++ b/hw/peach/v1/mactx_he_sig_b1_mu.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_HE_SIG_B1_MU_H_
+#define _MACTX_HE_SIG_B1_MU_H_
+
+#include "he_sig_b1_mu_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 1
+
+struct mactx_he_sig_b1_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b1_mu_info                                         mactx_he_sig_b1_mu_info_details;
+#else
+             struct   he_sig_b1_mu_info                                         mactx_he_sig_b1_mu_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET     0x00000000
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB        0
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB        7
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK       0x000000ff
+
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET        0x00000000
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB           8
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB           30
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK          0x7fffff00
+
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/hw/peach/v1/mactx_he_sig_b2_mu.h b/hw/peach/v1/mactx_he_sig_b2_mu.h
new file mode 100644
index 000000000000..6439af73ecb2
--- /dev/null
+++ b/hw/peach/v1/mactx_he_sig_b2_mu.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_HE_SIG_B2_MU_H_
+#define _MACTX_HE_SIG_B2_MU_H_
+
+#include "he_sig_b2_mu_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2
+
+struct mactx_he_sig_b2_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_mu_info                                         mactx_he_sig_b2_mu_info_details;
+#else
+             struct   he_sig_b2_mu_info                                         mactx_he_sig_b2_mu_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET            0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB               0
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB               10
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK              0x000007ff
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB   11
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB   14
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK  0x00007800
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET           0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB              15
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB              18
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK             0x00078000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB    19
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB    19
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK   0x00080000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET        0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB           20
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB           20
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK          0x00100000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET       0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB          21
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB          27
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK         0x0fe00000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET              0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB                 28
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB                 30
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK                0x70000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET        0x00000004
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB           0
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB           7
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK          0x000000ff
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET           0x00000004
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB              8
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB              15
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK             0x0000ff00
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET       0x00000004
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB          16
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB          31
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK         0xffff0000
+
+#endif
diff --git a/hw/peach/v1/mactx_he_sig_b2_ofdma.h b/hw/peach/v1/mactx_he_sig_b2_ofdma.h
new file mode 100644
index 000000000000..b1563803a0ec
--- /dev/null
+++ b/hw/peach/v1/mactx_he_sig_b2_ofdma.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_HE_SIG_B2_OFDMA_H_
+#define _MACTX_HE_SIG_B2_OFDMA_H_
+
+#include "he_sig_b2_ofdma_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2
+
+struct mactx_he_sig_b2_ofdma {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_ofdma_info                                      mactx_he_sig_b2_ofdma_info_details;
+#else
+             struct   he_sig_b2_ofdma_info                                      mactx_he_sig_b2_ofdma_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET      0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB         0
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB         10
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK        0x000007ff
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET        0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB           11
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB           13
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK          0x00003800
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET        0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB           14
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB           14
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK          0x00004000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET     0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB        15
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB        18
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK       0x00078000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET     0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB        19
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB        19
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK       0x00080000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET  0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB     20
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB     20
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK    0x00100000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET  0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB     21
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB     30
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK    0x7fe00000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET  0x00000004
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB     0
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB     7
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK    0x000000ff
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET     0x00000004
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB        8
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB        15
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK       0x0000ff00
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB    16
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB    31
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK   0xffff0000
+
+#endif
diff --git a/hw/peach/v1/mactx_ht_sig.h b/hw/peach/v1/mactx_ht_sig.h
new file mode 100644
index 000000000000..96f653ce831a
--- /dev/null
+++ b/hw/peach/v1/mactx_ht_sig.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_HT_SIG_H_
+#define _MACTX_HT_SIG_H_
+
+#include "ht_sig_info.h"
+#define NUM_OF_DWORDS_MACTX_HT_SIG 2
+
+struct mactx_ht_sig {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   ht_sig_info                                               mactx_ht_sig_info_details;
+#else
+             struct   ht_sig_info                                               mactx_ht_sig_info_details;
+#endif
+};
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET                           0x00000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB                              0
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB                              6
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK                             0x0000007f
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET                           0x00000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB                              7
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB                              7
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK                             0x00000080
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET                        0x00000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB                           8
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB                           23
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK                          0x00ffff00
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET                    0x00000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB                       24
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB                       31
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK                      0xff000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET                     0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB                        0
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB                        0
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK                       0x00000001
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET                  0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB                     1
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB                     1
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK                    0x00000002
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET                   0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB                      2
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB                      2
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK                     0x00000004
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET                   0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB                      3
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB                      3
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK                     0x00000008
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET                          0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB                             4
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB                             5
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK                            0x00000030
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET                    0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB                       6
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB                       6
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK                      0x00000040
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET                      0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB                         7
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB                         7
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK                        0x00000080
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET                0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB                   8
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB                   9
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK                  0x00000300
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET                           0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB                              10
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB                              17
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK                             0x0003fc00
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET                   0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB                      18
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB                      23
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK                     0x00fc0000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET                    0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB                       24
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB                       30
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK                      0x7f000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET     0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB        31
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB        31
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK       0x80000000
+
+#endif
diff --git a/hw/peach/v1/mactx_l_sig_a.h b/hw/peach/v1/mactx_l_sig_a.h
new file mode 100644
index 000000000000..5ba28f73ec8c
--- /dev/null
+++ b/hw/peach/v1/mactx_l_sig_a.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_L_SIG_A_H_
+#define _MACTX_L_SIG_A_H_
+
+#include "l_sig_a_info.h"
+#define NUM_OF_DWORDS_MACTX_L_SIG_A 1
+
+struct mactx_l_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_a_info                                              mactx_l_sig_a_info_details;
+#else
+             struct   l_sig_a_info                                              mactx_l_sig_a_info_details;
+#endif
+};
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET                        0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB                           0
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB                           3
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK                          0x0000000f
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET               0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB                  4
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB                  4
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK                 0x00000010
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET                      0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB                         5
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB                         16
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK                        0x0001ffe0
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET                      0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB                         17
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB                         17
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK                        0x00020000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET                        0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB                           18
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB                           23
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK                          0x00fc0000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET                    0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB                       24
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB                       27
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK                      0x0f000000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET  0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB     28
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB     28
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK    0x10000000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET                    0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB                       29
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB                       30
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK                      0x60000000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x80000000
+
+#endif
diff --git a/hw/peach/v1/mactx_l_sig_b.h b/hw/peach/v1/mactx_l_sig_b.h
new file mode 100644
index 000000000000..4e05a7b71b19
--- /dev/null
+++ b/hw/peach/v1/mactx_l_sig_b.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_L_SIG_B_H_
+#define _MACTX_L_SIG_B_H_
+
+#include "l_sig_b_info.h"
+#define NUM_OF_DWORDS_MACTX_L_SIG_B 1
+
+struct mactx_l_sig_b {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_b_info                                              mactx_l_sig_b_info_details;
+#else
+             struct   l_sig_b_info                                              mactx_l_sig_b_info_details;
+#endif
+};
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET                        0x00000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB                           0
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB                           3
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK                          0x0000000f
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET                      0x00000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB                         4
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB                         15
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK                        0x0000fff0
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET                    0x00000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB                       16
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB                       30
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK                      0x7fff0000
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x00000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x80000000
+
+#endif
diff --git a/hw/peach/v1/mactx_phy_desc.h b/hw/peach/v1/mactx_phy_desc.h
new file mode 100644
index 000000000000..a7f61e8108d7
--- /dev/null
+++ b/hw/peach/v1/mactx_phy_desc.h
@@ -0,0 +1,365 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_PHY_DESC_H_
+#define _MACTX_PHY_DESC_H_
+
+#define NUM_OF_DWORDS_MACTX_PHY_DESC 4
+
+struct mactx_phy_desc {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             : 16,
+                      bf_type                                                 :  2,
+                      wait_sifs                                               :  2,
+                      dot11b_preamble_type                                    :  1,
+                      pkt_type                                                :  4,
+                      su_or_mu                                                :  2,
+                      mu_type                                                 :  1,
+                      bandwidth                                               :  3,
+                      channel_capture                                         :  1;
+             uint32_t mcs                                                     :  4,
+                      global_ofdma_mimo_enable                                :  1,
+                      reserved_1a                                             :  1,
+                      stbc                                                    :  1,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_trigger_frame_embedded                          :  1,
+                      tx_pwr_shared                                           :  8,
+                      tx_pwr_unshared                                         :  8,
+                      measure_power                                           :  1,
+                      tpc_glut_self_cal                                       :  1,
+                      back_to_back_transmission_expected                      :  1,
+                      heavy_clip_nss                                          :  3,
+                      txbf_per_packet_no_csd_no_walsh                         :  1;
+             uint32_t ndp                                                     :  2,
+                      ul_flag                                                 :  1,
+                      triggered                                               :  1,
+                      ap_pkt_bw                                               :  3,
+                      ru_position_start                                       :  8,
+                      pcu_ppdu_setup_start_reason                             :  3,
+                      tlv_source                                              :  1,
+                      reserved_2a                                             :  2,
+                      nss                                                     :  3,
+                      stream_offset                                           :  3,
+                      reserved_2b                                             :  2,
+                      clpc_enable                                             :  1,
+                      mu_ndp                                                  :  1,
+                      response_expected                                       :  1;
+             uint32_t rx_chain_mask                                           :  8,
+                      rx_chain_mask_valid                                     :  1,
+                      ant_sel_valid                                           :  1,
+                      ant_sel                                                 :  1,
+                      cp_setting                                              :  2,
+                      he_ppdu_subtype                                         :  2,
+                      active_channel                                          :  3,
+                      generate_phyrx_tx_start_timing                          :  1,
+                      ltf_size                                                :  2,
+                      ru_size_updated_v2                                      :  4,
+                      reserved_3c                                             :  1,
+                      u_sig_puncture_pattern_encoding                         :  6;
+#else
+             uint32_t channel_capture                                         :  1,
+                      bandwidth                                               :  3,
+                      mu_type                                                 :  1,
+                      su_or_mu                                                :  2,
+                      pkt_type                                                :  4,
+                      dot11b_preamble_type                                    :  1,
+                      wait_sifs                                               :  2,
+                      bf_type                                                 :  2,
+                      reserved_0a                                             : 16;
+             uint32_t txbf_per_packet_no_csd_no_walsh                         :  1,
+                      heavy_clip_nss                                          :  3,
+                      back_to_back_transmission_expected                      :  1,
+                      tpc_glut_self_cal                                       :  1,
+                      measure_power                                           :  1,
+                      tx_pwr_unshared                                         :  8,
+                      tx_pwr_shared                                           :  8,
+                      dot11ax_trigger_frame_embedded                          :  1,
+                      dot11ax_su_extended                                     :  1,
+                      stbc                                                    :  1,
+                      reserved_1a                                             :  1,
+                      global_ofdma_mimo_enable                                :  1,
+                      mcs                                                     :  4;
+             uint32_t response_expected                                       :  1,
+                      mu_ndp                                                  :  1,
+                      clpc_enable                                             :  1,
+                      reserved_2b                                             :  2,
+                      stream_offset                                           :  3,
+                      nss                                                     :  3,
+                      reserved_2a                                             :  2,
+                      tlv_source                                              :  1,
+                      pcu_ppdu_setup_start_reason                             :  3,
+                      ru_position_start                                       :  8,
+                      ap_pkt_bw                                               :  3,
+                      triggered                                               :  1,
+                      ul_flag                                                 :  1,
+                      ndp                                                     :  2;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_3c                                             :  1,
+                      ru_size_updated_v2                                      :  4,
+                      ltf_size                                                :  2,
+                      generate_phyrx_tx_start_timing                          :  1,
+                      active_channel                                          :  3,
+                      he_ppdu_subtype                                         :  2,
+                      cp_setting                                              :  2,
+                      ant_sel                                                 :  1,
+                      ant_sel_valid                                           :  1,
+                      rx_chain_mask_valid                                     :  1,
+                      rx_chain_mask                                           :  8;
+#endif
+};
+
+#define MACTX_PHY_DESC_RESERVED_0A_OFFSET                                           0x00000000
+#define MACTX_PHY_DESC_RESERVED_0A_LSB                                              0
+#define MACTX_PHY_DESC_RESERVED_0A_MSB                                              15
+#define MACTX_PHY_DESC_RESERVED_0A_MASK                                             0x0000ffff
+
+#define MACTX_PHY_DESC_BF_TYPE_OFFSET                                               0x00000000
+#define MACTX_PHY_DESC_BF_TYPE_LSB                                                  16
+#define MACTX_PHY_DESC_BF_TYPE_MSB                                                  17
+#define MACTX_PHY_DESC_BF_TYPE_MASK                                                 0x00030000
+
+#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET                                             0x00000000
+#define MACTX_PHY_DESC_WAIT_SIFS_LSB                                                18
+#define MACTX_PHY_DESC_WAIT_SIFS_MSB                                                19
+#define MACTX_PHY_DESC_WAIT_SIFS_MASK                                               0x000c0000
+
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET                                  0x00000000
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB                                     20
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB                                     20
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK                                    0x00100000
+
+#define MACTX_PHY_DESC_PKT_TYPE_OFFSET                                              0x00000000
+#define MACTX_PHY_DESC_PKT_TYPE_LSB                                                 21
+#define MACTX_PHY_DESC_PKT_TYPE_MSB                                                 24
+#define MACTX_PHY_DESC_PKT_TYPE_MASK                                                0x01e00000
+
+#define MACTX_PHY_DESC_SU_OR_MU_OFFSET                                              0x00000000
+#define MACTX_PHY_DESC_SU_OR_MU_LSB                                                 25
+#define MACTX_PHY_DESC_SU_OR_MU_MSB                                                 26
+#define MACTX_PHY_DESC_SU_OR_MU_MASK                                                0x06000000
+
+#define MACTX_PHY_DESC_MU_TYPE_OFFSET                                               0x00000000
+#define MACTX_PHY_DESC_MU_TYPE_LSB                                                  27
+#define MACTX_PHY_DESC_MU_TYPE_MSB                                                  27
+#define MACTX_PHY_DESC_MU_TYPE_MASK                                                 0x08000000
+
+#define MACTX_PHY_DESC_BANDWIDTH_OFFSET                                             0x00000000
+#define MACTX_PHY_DESC_BANDWIDTH_LSB                                                28
+#define MACTX_PHY_DESC_BANDWIDTH_MSB                                                30
+#define MACTX_PHY_DESC_BANDWIDTH_MASK                                               0x70000000
+
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET                                       0x00000000
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB                                          31
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB                                          31
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK                                         0x80000000
+
+#define MACTX_PHY_DESC_MCS_OFFSET                                                   0x00000004
+#define MACTX_PHY_DESC_MCS_LSB                                                      0
+#define MACTX_PHY_DESC_MCS_MSB                                                      3
+#define MACTX_PHY_DESC_MCS_MASK                                                     0x0000000f
+
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET                              0x00000004
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB                                 4
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB                                 4
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK                                0x00000010
+
+#define MACTX_PHY_DESC_RESERVED_1A_OFFSET                                           0x00000004
+#define MACTX_PHY_DESC_RESERVED_1A_LSB                                              5
+#define MACTX_PHY_DESC_RESERVED_1A_MSB                                              5
+#define MACTX_PHY_DESC_RESERVED_1A_MASK                                             0x00000020
+
+#define MACTX_PHY_DESC_STBC_OFFSET                                                  0x00000004
+#define MACTX_PHY_DESC_STBC_LSB                                                     6
+#define MACTX_PHY_DESC_STBC_MSB                                                     6
+#define MACTX_PHY_DESC_STBC_MASK                                                    0x00000040
+
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET                                   0x00000004
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB                                      7
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB                                      7
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK                                     0x00000080
+
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET                        0x00000004
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB                           8
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB                           8
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK                          0x00000100
+
+#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET                                         0x00000004
+#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB                                            9
+#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB                                            16
+#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK                                           0x0001fe00
+
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET                                       0x00000004
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB                                          17
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB                                          24
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK                                         0x01fe0000
+
+#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET                                         0x00000004
+#define MACTX_PHY_DESC_MEASURE_POWER_LSB                                            25
+#define MACTX_PHY_DESC_MEASURE_POWER_MSB                                            25
+#define MACTX_PHY_DESC_MEASURE_POWER_MASK                                           0x02000000
+
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET                                     0x00000004
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB                                        26
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB                                        26
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK                                       0x04000000
+
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET                    0x00000004
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB                       27
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB                       27
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK                      0x08000000
+
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET                                        0x00000004
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB                                           28
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB                                           30
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK                                          0x70000000
+
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET                       0x00000004
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB                          31
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB                          31
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK                         0x80000000
+
+#define MACTX_PHY_DESC_NDP_OFFSET                                                   0x00000008
+#define MACTX_PHY_DESC_NDP_LSB                                                      0
+#define MACTX_PHY_DESC_NDP_MSB                                                      1
+#define MACTX_PHY_DESC_NDP_MASK                                                     0x00000003
+
+#define MACTX_PHY_DESC_UL_FLAG_OFFSET                                               0x00000008
+#define MACTX_PHY_DESC_UL_FLAG_LSB                                                  2
+#define MACTX_PHY_DESC_UL_FLAG_MSB                                                  2
+#define MACTX_PHY_DESC_UL_FLAG_MASK                                                 0x00000004
+
+#define MACTX_PHY_DESC_TRIGGERED_OFFSET                                             0x00000008
+#define MACTX_PHY_DESC_TRIGGERED_LSB                                                3
+#define MACTX_PHY_DESC_TRIGGERED_MSB                                                3
+#define MACTX_PHY_DESC_TRIGGERED_MASK                                               0x00000008
+
+#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET                                             0x00000008
+#define MACTX_PHY_DESC_AP_PKT_BW_LSB                                                4
+#define MACTX_PHY_DESC_AP_PKT_BW_MSB                                                6
+#define MACTX_PHY_DESC_AP_PKT_BW_MASK                                               0x00000070
+
+#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET                                     0x00000008
+#define MACTX_PHY_DESC_RU_POSITION_START_LSB                                        7
+#define MACTX_PHY_DESC_RU_POSITION_START_MSB                                        14
+#define MACTX_PHY_DESC_RU_POSITION_START_MASK                                       0x00007f80
+
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET                           0x00000008
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB                              15
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB                              17
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK                             0x00038000
+
+#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET                                            0x00000008
+#define MACTX_PHY_DESC_TLV_SOURCE_LSB                                               18
+#define MACTX_PHY_DESC_TLV_SOURCE_MSB                                               18
+#define MACTX_PHY_DESC_TLV_SOURCE_MASK                                              0x00040000
+
+#define MACTX_PHY_DESC_RESERVED_2A_OFFSET                                           0x00000008
+#define MACTX_PHY_DESC_RESERVED_2A_LSB                                              19
+#define MACTX_PHY_DESC_RESERVED_2A_MSB                                              20
+#define MACTX_PHY_DESC_RESERVED_2A_MASK                                             0x00180000
+
+#define MACTX_PHY_DESC_NSS_OFFSET                                                   0x00000008
+#define MACTX_PHY_DESC_NSS_LSB                                                      21
+#define MACTX_PHY_DESC_NSS_MSB                                                      23
+#define MACTX_PHY_DESC_NSS_MASK                                                     0x00e00000
+
+#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET                                         0x00000008
+#define MACTX_PHY_DESC_STREAM_OFFSET_LSB                                            24
+#define MACTX_PHY_DESC_STREAM_OFFSET_MSB                                            26
+#define MACTX_PHY_DESC_STREAM_OFFSET_MASK                                           0x07000000
+
+#define MACTX_PHY_DESC_RESERVED_2B_OFFSET                                           0x00000008
+#define MACTX_PHY_DESC_RESERVED_2B_LSB                                              27
+#define MACTX_PHY_DESC_RESERVED_2B_MSB                                              28
+#define MACTX_PHY_DESC_RESERVED_2B_MASK                                             0x18000000
+
+#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET                                           0x00000008
+#define MACTX_PHY_DESC_CLPC_ENABLE_LSB                                              29
+#define MACTX_PHY_DESC_CLPC_ENABLE_MSB                                              29
+#define MACTX_PHY_DESC_CLPC_ENABLE_MASK                                             0x20000000
+
+#define MACTX_PHY_DESC_MU_NDP_OFFSET                                                0x00000008
+#define MACTX_PHY_DESC_MU_NDP_LSB                                                   30
+#define MACTX_PHY_DESC_MU_NDP_MSB                                                   30
+#define MACTX_PHY_DESC_MU_NDP_MASK                                                  0x40000000
+
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET                                     0x00000008
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB                                        31
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB                                        31
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK                                       0x80000000
+
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET                                         0x0000000c
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB                                            0
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB                                            7
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK                                           0x000000ff
+
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET                                   0x0000000c
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB                                      8
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB                                      8
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK                                     0x00000100
+
+#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET                                         0x0000000c
+#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB                                            9
+#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB                                            9
+#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK                                           0x00000200
+
+#define MACTX_PHY_DESC_ANT_SEL_OFFSET                                               0x0000000c
+#define MACTX_PHY_DESC_ANT_SEL_LSB                                                  10
+#define MACTX_PHY_DESC_ANT_SEL_MSB                                                  10
+#define MACTX_PHY_DESC_ANT_SEL_MASK                                                 0x00000400
+
+#define MACTX_PHY_DESC_CP_SETTING_OFFSET                                            0x0000000c
+#define MACTX_PHY_DESC_CP_SETTING_LSB                                               11
+#define MACTX_PHY_DESC_CP_SETTING_MSB                                               12
+#define MACTX_PHY_DESC_CP_SETTING_MASK                                              0x00001800
+
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET                                       0x0000000c
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB                                          13
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB                                          14
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK                                         0x00006000
+
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET                                        0x0000000c
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB                                           15
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB                                           17
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK                                          0x00038000
+
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET                        0x0000000c
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB                           18
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB                           18
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK                          0x00040000
+
+#define MACTX_PHY_DESC_LTF_SIZE_OFFSET                                              0x0000000c
+#define MACTX_PHY_DESC_LTF_SIZE_LSB                                                 19
+#define MACTX_PHY_DESC_LTF_SIZE_MSB                                                 20
+#define MACTX_PHY_DESC_LTF_SIZE_MASK                                                0x00180000
+
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET                                    0x0000000c
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB                                       21
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB                                       24
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK                                      0x01e00000
+
+#define MACTX_PHY_DESC_RESERVED_3C_OFFSET                                           0x0000000c
+#define MACTX_PHY_DESC_RESERVED_3C_LSB                                              25
+#define MACTX_PHY_DESC_RESERVED_3C_MSB                                              25
+#define MACTX_PHY_DESC_RESERVED_3C_MASK                                             0x02000000
+
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET                       0x0000000c
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                          26
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                          31
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                         0xfc000000
+
+#endif
diff --git a/hw/peach/v1/mactx_u_sig_eht_su_mu.h b/hw/peach/v1/mactx_u_sig_eht_su_mu.h
new file mode 100644
index 000000000000..6ccc7d2e2548
--- /dev/null
+++ b/hw/peach/v1/mactx_u_sig_eht_su_mu.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_U_SIG_EHT_SU_MU_H_
+#define _MACTX_U_SIG_EHT_SU_MU_H_
+
+#include "u_sig_eht_su_mu_info.h"
+#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2
+
+struct mactx_u_sig_eht_su_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   u_sig_eht_su_mu_info                                      mactx_u_sig_eht_su_mu_info_details;
+#else
+             struct   u_sig_eht_su_mu_info                                      mactx_u_sig_eht_su_mu_info_details;
+#endif
+};
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB    0
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB    2
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK   0x00000007
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB    3
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB    5
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK   0x00000038
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET  0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB     6
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB     6
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK    0x00000040
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB   7
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB   12
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK  0x00001f80
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB  13
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB  19
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x000fe000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB   20
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB   24
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK  0x01f00000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB    25
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB    25
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK   0x02000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB    26
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB    31
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK   0xfc000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 0
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 1
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB    2
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB    2
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK   0x00000004
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 3
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 7
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB    8
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB    8
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK   0x00000100
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 9
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 10
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x00000600
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 11
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 15
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET         0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB            16
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB            19
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK           0x000f0000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET        0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB           20
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB           25
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK          0x03f00000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB    27
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB    29
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK   0x38000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET      0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB         30
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB         30
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK        0x40000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/hw/peach/v1/mactx_u_sig_eht_tb.h b/hw/peach/v1/mactx_u_sig_eht_tb.h
new file mode 100644
index 000000000000..a305e5640a0d
--- /dev/null
+++ b/hw/peach/v1/mactx_u_sig_eht_tb.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_U_SIG_EHT_TB_H_
+#define _MACTX_U_SIG_EHT_TB_H_
+
+#include "u_sig_eht_tb_info.h"
+#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2
+
+struct mactx_u_sig_eht_tb {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   u_sig_eht_tb_info                                         mactx_u_sig_eht_tb_info_details;
+#else
+             struct   u_sig_eht_tb_info                                         mactx_u_sig_eht_tb_info_details;
+#endif
+};
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET       0x00000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB          0
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB          2
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK         0x00000007
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET       0x00000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB          3
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB          5
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK         0x00000038
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET        0x00000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB           6
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB           6
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK          0x00000040
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET      0x00000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB         7
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB         12
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK        0x00001f80
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET     0x00000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB        13
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB        19
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK       0x000fe000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET      0x00000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB         20
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB         25
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK        0x03f00000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET       0x00000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB          26
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB          31
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK         0xfc000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 0
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 1
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET       0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB          2
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB          2
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK         0x00000004
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET     0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB        3
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB        10
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK       0x000007f8
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET      0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB         11
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB         15
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK        0x0000f800
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET               0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB                  16
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB                  19
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK                 0x000f0000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET              0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB                 20
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB                 25
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK                0x03f00000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET       0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB          26
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB          30
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK         0x7c000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/hw/peach/v1/mactx_user_desc_common.h b/hw/peach/v1/mactx_user_desc_common.h
new file mode 100644
index 000000000000..6ccbfc2e57fe
--- /dev/null
+++ b/hw/peach/v1/mactx_user_desc_common.h
@@ -0,0 +1,478 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_USER_DESC_COMMON_H_
+#define _MACTX_USER_DESC_COMMON_H_
+
+#include "unallocated_ru_160_info.h"
+#include "ru_allocation_160_info.h"
+#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16
+
+struct mactx_user_desc_common {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t num_users                                               :  6,
+                      reserved_0b                                             :  5,
+                      ltf_size                                                :  2,
+                      reserved_0c                                             :  3,
+                      he_stf_long                                             :  1,
+                      reserved_0d                                             :  7,
+                      num_users_he_sigb_band0                                 :  8;
+             uint32_t num_ltf_symbols                                         :  3,
+                      reserved_1a                                             :  5,
+                      num_users_he_sigb_band1                                 :  8,
+                      reserved_1b                                             : 16;
+             uint32_t packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension                                        :  3,
+                      reserved                                                :  2,
+                      he_sigb_dcm                                             :  1,
+                      reserved_2b                                             :  7,
+                      he_sigb_compression                                     :  1,
+                      reserved_2c                                             : 15;
+             uint32_t he_sigb_0_mcs                                           :  3,
+                      reserved_3a                                             : 13,
+                      num_he_sigb_sym                                         :  5,
+                      center_ru_0                                             :  1,
+                      center_ru_1                                             :  1,
+                      reserved_3b                                             :  1,
+                      ftm_en                                                  :  1,
+                      pe_nss                                                  :  3,
+                      pe_ltf_size                                             :  2,
+                      pe_content                                              :  1,
+                      pe_chain_csd_en                                         :  1;
+             struct   ru_allocation_160_info                                    ru_allocation_0123_details;
+             struct   ru_allocation_160_info                                    ru_allocation_4567_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_0_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_1_details;
+             uint32_t num_data_symbols                                        : 16,
+                      ndp_ru_tone_set_index                                   :  7,
+                      ndp_feedback_status                                     :  1,
+                      doppler_indication                                      :  1,
+                      reserved_14a                                            :  7;
+             uint32_t spatial_reuse                                           : 16,
+                      reserved_15a                                            : 16;
+#else
+             uint32_t num_users_he_sigb_band0                                 :  8,
+                      reserved_0d                                             :  7,
+                      he_stf_long                                             :  1,
+                      reserved_0c                                             :  3,
+                      ltf_size                                                :  2,
+                      reserved_0b                                             :  5,
+                      num_users                                               :  6;
+             uint32_t reserved_1b                                             : 16,
+                      num_users_he_sigb_band1                                 :  8,
+                      reserved_1a                                             :  5,
+                      num_ltf_symbols                                         :  3;
+             uint32_t reserved_2c                                             : 15,
+                      he_sigb_compression                                     :  1,
+                      reserved_2b                                             :  7,
+                      he_sigb_dcm                                             :  1,
+                      reserved                                                :  2,
+                      packet_extension                                        :  3,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2;
+             uint32_t pe_chain_csd_en                                         :  1,
+                      pe_content                                              :  1,
+                      pe_ltf_size                                             :  2,
+                      pe_nss                                                  :  3,
+                      ftm_en                                                  :  1,
+                      reserved_3b                                             :  1,
+                      center_ru_1                                             :  1,
+                      center_ru_0                                             :  1,
+                      num_he_sigb_sym                                         :  5,
+                      reserved_3a                                             : 13,
+                      he_sigb_0_mcs                                           :  3;
+             struct   ru_allocation_160_info                                    ru_allocation_0123_details;
+             struct   ru_allocation_160_info                                    ru_allocation_4567_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_0_details;
+             struct   unallocated_ru_160_info                                   ru_allocation_160_1_details;
+             uint32_t reserved_14a                                            :  7,
+                      doppler_indication                                      :  1,
+                      ndp_feedback_status                                     :  1,
+                      ndp_ru_tone_set_index                                   :  7,
+                      num_data_symbols                                        : 16;
+             uint32_t reserved_15a                                            : 16,
+                      spatial_reuse                                           : 16;
+#endif
+};
+
+#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET                                     0x00000000
+#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB                                        0
+#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB                                        5
+#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK                                       0x0000003f
+
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET                                   0x00000000
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB                                      6
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB                                      10
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK                                     0x000007c0
+
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET                                      0x00000000
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB                                         11
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB                                         12
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK                                        0x00001800
+
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET                                   0x00000000
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB                                      13
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB                                      15
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK                                     0x0000e000
+
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET                                   0x00000000
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB                                      16
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB                                      16
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK                                     0x00010000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET                                   0x00000000
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB                                      17
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB                                      23
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK                                     0x00fe0000
+
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET                       0x00000000
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB                          24
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB                          31
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK                         0xff000000
+
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET                               0x00000004
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB                                  0
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB                                  2
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK                                 0x00000007
+
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET                                   0x00000004
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB                                      3
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB                                      7
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK                                     0x000000f8
+
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET                       0x00000004
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB                          8
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB                          15
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK                         0x0000ff00
+
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET                                   0x00000004
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB                                      16
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB                                      31
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK                                     0xffff0000
+
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET                     0x00000008
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB                        0
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB                        1
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK                       0x00000003
+
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET              0x00000008
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                 2
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                 2
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                0x00000004
+
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET                              0x00000008
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB                                 3
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB                                 5
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK                                0x00000038
+
+#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET                                      0x00000008
+#define MACTX_USER_DESC_COMMON_RESERVED_LSB                                         6
+#define MACTX_USER_DESC_COMMON_RESERVED_MSB                                         7
+#define MACTX_USER_DESC_COMMON_RESERVED_MASK                                        0x000000c0
+
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET                                   0x00000008
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB                                      8
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB                                      8
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK                                     0x00000100
+
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET                                   0x00000008
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB                                      9
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB                                      15
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK                                     0x0000fe00
+
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET                           0x00000008
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB                              16
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB                              16
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK                             0x00010000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET                                   0x00000008
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB                                      17
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB                                      31
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK                                     0xfffe0000
+
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET                                 0x0000000c
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB                                    0
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB                                    2
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK                                   0x00000007
+
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET                                   0x0000000c
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB                                      3
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB                                      15
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK                                     0x0000fff8
+
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET                               0x0000000c
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB                                  16
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB                                  20
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK                                 0x001f0000
+
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET                                   0x0000000c
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB                                      21
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB                                      21
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK                                     0x00200000
+
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET                                   0x0000000c
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB                                      22
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB                                      22
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK                                     0x00400000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET                                   0x0000000c
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB                                      23
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB                                      23
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK                                     0x00800000
+
+#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET                                        0x0000000c
+#define MACTX_USER_DESC_COMMON_FTM_EN_LSB                                           24
+#define MACTX_USER_DESC_COMMON_FTM_EN_MSB                                           24
+#define MACTX_USER_DESC_COMMON_FTM_EN_MASK                                          0x01000000
+
+#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET                                        0x0000000c
+#define MACTX_USER_DESC_COMMON_PE_NSS_LSB                                           25
+#define MACTX_USER_DESC_COMMON_PE_NSS_MSB                                           27
+#define MACTX_USER_DESC_COMMON_PE_NSS_MASK                                          0x0e000000
+
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET                                   0x0000000c
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB                                      28
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB                                      29
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK                                     0x30000000
+
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET                                    0x0000000c
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB                                       30
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB                                       30
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK                                      0x40000000
+
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET                               0x0000000c
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB                                  31
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB                                  31
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK                                 0x80000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x00000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x00000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET        0x00000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB           23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK          0x00fc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x00000014
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x00000014
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET        0x00000014
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB           31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK          0xfffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x00000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x00000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET        0x00000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB           31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK          0xfffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000001c
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000001c
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET        0x0000001c
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB           31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK          0xfffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x00000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x00000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET        0x00000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB           23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK          0x00fc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x00000024
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x00000024
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET        0x00000024
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB           31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK          0xfffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x00000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x00000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET        0x00000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB           31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK          0xfffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000002c
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000002c
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET        0x0000002c
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB           18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB           31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK          0xfffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET   0x00000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB      0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB      7
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK     0x000000ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET   0x00000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB      8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB      15
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK     0x0000ff00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET   0x00000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB      16
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB      23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK     0x00ff0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET   0x00000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB      24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB      31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK     0xff000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET   0x00000034
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB      0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB      7
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK     0x000000ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET   0x00000034
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB      8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB      15
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK     0x0000ff00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET   0x00000034
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB      16
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB      23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK     0x00ff0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET   0x00000034
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB      24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB      31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK     0xff000000
+
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET                              0x00000038
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB                                 0
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB                                 15
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK                                0x0000ffff
+
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET                         0x00000038
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB                            16
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB                            22
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK                           0x007f0000
+
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET                           0x00000038
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB                              23
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB                              23
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK                             0x00800000
+
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET                            0x00000038
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB                               24
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB                               24
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK                              0x01000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET                                  0x00000038
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB                                     25
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB                                     31
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK                                    0xfe000000
+
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET                                 0x0000003c
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB                                    0
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB                                    15
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK                                   0x0000ffff
+
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET                                  0x0000003c
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB                                     16
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB                                     31
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK                                    0xffff0000
+
+#endif
diff --git a/hw/peach/v1/mactx_user_desc_per_user.h b/hw/peach/v1/mactx_user_desc_per_user.h
new file mode 100644
index 000000000000..7e70429874b0
--- /dev/null
+++ b/hw/peach/v1/mactx_user_desc_per_user.h
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_USER_DESC_PER_USER_H_
+#define _MACTX_USER_DESC_PER_USER_H_
+
+#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4
+
+struct mactx_user_desc_per_user {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t psdu_length                                             : 24,
+                      reserved_0a                                             :  8;
+             uint32_t ru_start_index                                          :  8,
+                      ru_size                                                 :  4,
+                      reserved_1b                                             :  4,
+                      ofdma_mu_mimo_enabled                                   :  1,
+                      nss                                                     :  3,
+                      stream_offset                                           :  3,
+                      reserved_1c                                             :  1,
+                      mcs                                                     :  4,
+                      dcm                                                     :  1,
+                      reserved_1d                                             :  3;
+             uint32_t fec_type                                                :  1,
+                      reserved_2a                                             :  7,
+                      user_bf_type                                            :  2,
+                      reserved_2b                                             :  6,
+                      drop_user_cbf                                           :  1,
+                      reserved_2c                                             :  7,
+                      ldpc_extra_symbol                                       :  1,
+                      force_extra_symbol                                      :  1,
+                      reserved_2d                                             :  6;
+             uint32_t sw_peer_id                                              : 16,
+                      per_user_subband_mask                                   : 16;
+#else
+             uint32_t reserved_0a                                             :  8,
+                      psdu_length                                             : 24;
+             uint32_t reserved_1d                                             :  3,
+                      dcm                                                     :  1,
+                      mcs                                                     :  4,
+                      reserved_1c                                             :  1,
+                      stream_offset                                           :  3,
+                      nss                                                     :  3,
+                      ofdma_mu_mimo_enabled                                   :  1,
+                      reserved_1b                                             :  4,
+                      ru_size                                                 :  4,
+                      ru_start_index                                          :  8;
+             uint32_t reserved_2d                                             :  6,
+                      force_extra_symbol                                      :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      reserved_2c                                             :  7,
+                      drop_user_cbf                                           :  1,
+                      reserved_2b                                             :  6,
+                      user_bf_type                                            :  2,
+                      reserved_2a                                             :  7,
+                      fec_type                                                :  1;
+             uint32_t per_user_subband_mask                                   : 16,
+                      sw_peer_id                                              : 16;
+#endif
+};
+
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET                                 0x00000000
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB                                    0
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB                                    23
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK                                   0x00ffffff
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET                                 0x00000000
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB                                    24
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB                                    31
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK                                   0xff000000
+
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET                              0x00000004
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB                                 0
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB                                 7
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK                                0x000000ff
+
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET                                     0x00000004
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB                                        8
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB                                        11
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK                                       0x00000f00
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET                                 0x00000004
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB                                    12
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB                                    15
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK                                   0x0000f000
+
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET                       0x00000004
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB                          16
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB                          16
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK                         0x00010000
+
+#define MACTX_USER_DESC_PER_USER_NSS_OFFSET                                         0x00000004
+#define MACTX_USER_DESC_PER_USER_NSS_LSB                                            17
+#define MACTX_USER_DESC_PER_USER_NSS_MSB                                            19
+#define MACTX_USER_DESC_PER_USER_NSS_MASK                                           0x000e0000
+
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET                               0x00000004
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB                                  20
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB                                  22
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK                                 0x00700000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET                                 0x00000004
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB                                    23
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB                                    23
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK                                   0x00800000
+
+#define MACTX_USER_DESC_PER_USER_MCS_OFFSET                                         0x00000004
+#define MACTX_USER_DESC_PER_USER_MCS_LSB                                            24
+#define MACTX_USER_DESC_PER_USER_MCS_MSB                                            27
+#define MACTX_USER_DESC_PER_USER_MCS_MASK                                           0x0f000000
+
+#define MACTX_USER_DESC_PER_USER_DCM_OFFSET                                         0x00000004
+#define MACTX_USER_DESC_PER_USER_DCM_LSB                                            28
+#define MACTX_USER_DESC_PER_USER_DCM_MSB                                            28
+#define MACTX_USER_DESC_PER_USER_DCM_MASK                                           0x10000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET                                 0x00000004
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB                                    29
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB                                    31
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK                                   0xe0000000
+
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET                                    0x00000008
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB                                       0
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB                                       0
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK                                      0x00000001
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET                                 0x00000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB                                    1
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB                                    7
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK                                   0x000000fe
+
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET                                0x00000008
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB                                   8
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB                                   9
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK                                  0x00000300
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET                                 0x00000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB                                    10
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB                                    15
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK                                   0x0000fc00
+
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET                               0x00000008
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB                                  16
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB                                  16
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK                                 0x00010000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET                                 0x00000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB                                    17
+#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB                                    23
+#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK                                   0x00fe0000
+
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET                           0x00000008
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB                              24
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB                              24
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK                             0x01000000
+
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET                          0x00000008
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB                             25
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB                             25
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK                            0x02000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET                                 0x00000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB                                    26
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB                                    31
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK                                   0xfc000000
+
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET                                  0x0000000c
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB                                     0
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB                                     15
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK                                    0x0000ffff
+
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET                       0x0000000c
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB                          16
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB                          31
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK                         0xffff0000
+
+#endif
diff --git a/hw/peach/v1/mactx_vht_sig_a.h b/hw/peach/v1/mactx_vht_sig_a.h
new file mode 100644
index 000000000000..3252a84ea556
--- /dev/null
+++ b/hw/peach/v1/mactx_vht_sig_a.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_A_H_
+#define _MACTX_VHT_SIG_A_H_
+
+#include "vht_sig_a_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2
+
+struct mactx_vht_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_a_info                                            mactx_vht_sig_a_info_details;
+#else
+             struct   vht_sig_a_info                                            mactx_vht_sig_a_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET               0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB                  0
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB                  1
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK                 0x00000003
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET         0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB            2
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB            2
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK           0x00000004
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET                    0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB                       3
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB                       3
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK                      0x00000008
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET                0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB                   4
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB                   9
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK                  0x000003f0
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET                   0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB                      10
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB                      21
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK                     0x003ffc00
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET     0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB        22
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB        22
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK       0x00400000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET        0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB           23
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB           23
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK          0x00800000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET              0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB                 24
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB                 31
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK                0xff000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET              0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB                 0
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB                 1
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK                0x00000003
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET            0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB               2
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB               2
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK              0x00000004
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET       0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB          3
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB          3
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK         0x00000008
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET                     0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB                        4
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB                        7
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK                       0x000000f0
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET              0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB                 8
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB                 8
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK                0x00000100
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET         0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB            9
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB            9
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK           0x00000200
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET                     0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB                        10
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB                        17
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK                       0x0003fc00
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET                    0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB                       18
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB                       23
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK                      0x00fc0000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET              0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB                 24
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB                 30
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK                0x7f000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB  31
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB  31
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/hw/peach/v1/mactx_vht_sig_b_mu160.h b/hw/peach/v1/mactx_vht_sig_b_mu160.h
new file mode 100644
index 000000000000..b26ede5f8f3b
--- /dev/null
+++ b/hw/peach/v1/mactx_vht_sig_b_mu160.h
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_MU160_H_
+#define _MACTX_VHT_SIG_B_MU160_H_
+
+#include "vht_sig_b_mu160_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8
+
+struct mactx_vht_sig_b_mu160 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu160_info                                      mactx_vht_sig_b_mu160_info_details;
+#else
+             struct   vht_sig_b_mu160_info                                      mactx_vht_sig_b_mu160_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET      0x00000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB         0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB         18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK        0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET         0x00000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB            19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB            22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK           0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET        0x00000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB           23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB           28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK          0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET  0x00000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK    0xe0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET  0x00000004
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK    0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK   0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET  0x00000004
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK    0xe0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET  0x00000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK    0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK   0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET  0x00000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK    0xe0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET  0x0000000c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK    0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK   0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET  0x0000000c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK    0xe0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x00000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET  0x00000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK    0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x00000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK   0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET  0x00000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK    0xe0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x00000014
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET  0x00000014
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK    0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x00000014
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK   0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET  0x00000014
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK    0xe0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET  0x00000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK    0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK   0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000001c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB  0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB  18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET  0x0000001c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB     19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB     22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK    0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000001c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB    23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB    28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK   0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET  0x0000001c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB     29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB     31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK    0xe0000000
+
+#endif
diff --git a/hw/peach/v1/mactx_vht_sig_b_mu20.h b/hw/peach/v1/mactx_vht_sig_b_mu20.h
new file mode 100644
index 000000000000..994a1ae4c235
--- /dev/null
+++ b/hw/peach/v1/mactx_vht_sig_b_mu20.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_MU20_H_
+#define _MACTX_VHT_SIG_B_MU20_H_
+
+#include "vht_sig_b_mu20_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 1
+
+struct mactx_vht_sig_b_mu20 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu20_info                                       mactx_vht_sig_b_mu20_info_details;
+#else
+             struct   vht_sig_b_mu20_info                                       mactx_vht_sig_b_mu20_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET        0x00000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB           15
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK          0x0000ffff
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET           0x00000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB              16
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB              19
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK             0x000f0000
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET          0x00000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB             20
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB             25
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK            0x03f00000
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB   26
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB   28
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK  0x1c000000
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET    0x00000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB       29
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB       31
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK      0xe0000000
+
+#endif
diff --git a/hw/peach/v1/mactx_vht_sig_b_mu40.h b/hw/peach/v1/mactx_vht_sig_b_mu40.h
new file mode 100644
index 000000000000..bdbe562d6ad9
--- /dev/null
+++ b/hw/peach/v1/mactx_vht_sig_b_mu40.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_MU40_H_
+#define _MACTX_VHT_SIG_B_MU40_H_
+
+#include "vht_sig_b_mu40_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2
+
+struct mactx_vht_sig_b_mu40 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu40_info                                       mactx_vht_sig_b_mu40_info_details;
+#else
+             struct   vht_sig_b_mu40_info                                       mactx_vht_sig_b_mu40_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET        0x00000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB           16
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK          0x0001ffff
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET           0x00000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB              17
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB              20
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK             0x001e0000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET          0x00000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB             21
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB             26
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK            0x07e00000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET    0x00000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB       27
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB       28
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK      0x18000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB   29
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB   31
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK  0xe0000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET   0x00000004
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB      0
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB      16
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK     0x0001ffff
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET      0x00000004
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB         17
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB         20
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK        0x001e0000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET     0x00000004
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB        21
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB        26
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK       0x07e00000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET    0x00000004
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB       27
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB       31
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK      0xf8000000
+
+#endif
diff --git a/hw/peach/v1/mactx_vht_sig_b_mu80.h b/hw/peach/v1/mactx_vht_sig_b_mu80.h
new file mode 100644
index 000000000000..e150bf89b643
--- /dev/null
+++ b/hw/peach/v1/mactx_vht_sig_b_mu80.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_MU80_H_
+#define _MACTX_VHT_SIG_B_MU80_H_
+
+#include "vht_sig_b_mu80_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4
+
+struct mactx_vht_sig_b_mu80 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_mu80_info                                       mactx_vht_sig_b_mu80_info_details;
+#else
+             struct   vht_sig_b_mu80_info                                       mactx_vht_sig_b_mu80_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET        0x00000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB           18
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK          0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET           0x00000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB              19
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB              22
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK             0x00780000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET          0x00000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB             23
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB             28
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK            0x1f800000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET    0x00000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB       29
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB       31
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK      0xe0000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB    0
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB    18
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK   0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET    0x00000004
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB       19
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB       22
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK      0x00780000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET   0x00000004
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB      23
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB      28
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK     0x1f800000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET    0x00000004
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB       29
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB       31
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK      0xe0000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB    0
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB    18
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK   0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET    0x00000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB       19
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB       22
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK      0x00780000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET   0x00000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB      23
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB      28
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK     0x1f800000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB   29
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB   31
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK  0xe0000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB    0
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB    18
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK   0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET    0x0000000c
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB       19
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB       22
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK      0x00780000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET   0x0000000c
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB      23
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB      28
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK     0x1f800000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET    0x0000000c
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB       29
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB       31
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK      0xe0000000
+
+#endif
diff --git a/hw/peach/v1/mactx_vht_sig_b_su160.h b/hw/peach/v1/mactx_vht_sig_b_su160.h
new file mode 100644
index 000000000000..edde887c102b
--- /dev/null
+++ b/hw/peach/v1/mactx_vht_sig_b_su160.h
@@ -0,0 +1,232 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_SU160_H_
+#define _MACTX_VHT_SIG_B_SU160_H_
+
+#include "vht_sig_b_su160_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8
+
+struct mactx_vht_sig_b_su160 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su160_info                                      mactx_vht_sig_b_su160_info_details;
+#else
+             struct   vht_sig_b_su160_info                                      mactx_vht_sig_b_su160_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET      0x00000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB         0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB         20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK        0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB  21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB  22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET        0x00000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB           23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB           28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK          0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET  0x00000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK    0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET      0x00000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB         31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB         31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK        0x80000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK   0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET  0x00000004
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK    0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK   0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET  0x00000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK    0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK   0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET  0x0000000c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK    0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x00000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x00000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x00000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK   0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET  0x00000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK    0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x00000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x00000014
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x00000014
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x00000014
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK   0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET  0x00000014
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK    0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x00000014
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK   0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET  0x00000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK    0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000001c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB  0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB  20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000001c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB    23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB    28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK   0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET  0x0000001c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB     29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB     30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK    0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000001c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB  31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x80000000
+
+#endif
diff --git a/hw/peach/v1/mactx_vht_sig_b_su20.h b/hw/peach/v1/mactx_vht_sig_b_su20.h
new file mode 100644
index 000000000000..3543c7f70575
--- /dev/null
+++ b/hw/peach/v1/mactx_vht_sig_b_su20.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_SU20_H_
+#define _MACTX_VHT_SIG_B_SU20_H_
+
+#include "vht_sig_b_su20_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 1
+
+struct mactx_vht_sig_b_su20 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su20_info                                       mactx_vht_sig_b_su20_info_details;
+#else
+             struct   vht_sig_b_su20_info                                       mactx_vht_sig_b_su20_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET        0x00000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB           16
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK          0x0001ffff
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB    17
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB    19
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK   0x000e0000
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET          0x00000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB             20
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB             25
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK            0x03f00000
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET      0x00000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB         26
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB         30
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK        0x7c000000
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET        0x00000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB           31
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB           31
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK          0x80000000
+
+#endif
diff --git a/hw/peach/v1/mactx_vht_sig_b_su40.h b/hw/peach/v1/mactx_vht_sig_b_su40.h
new file mode 100644
index 000000000000..f9136e2a6c21
--- /dev/null
+++ b/hw/peach/v1/mactx_vht_sig_b_su40.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_SU40_H_
+#define _MACTX_VHT_SIG_B_SU40_H_
+
+#include "vht_sig_b_su40_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2
+
+struct mactx_vht_sig_b_su40 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su40_info                                       mactx_vht_sig_b_su40_info_details;
+#else
+             struct   vht_sig_b_su40_info                                       mactx_vht_sig_b_su40_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET        0x00000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB           18
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK          0x0007ffff
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB    19
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB    20
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK   0x00180000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET          0x00000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB             21
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB             26
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK            0x07e00000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET      0x00000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB         27
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB         30
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK        0x78000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET        0x00000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB           31
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB           31
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK          0x80000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET   0x00000004
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB      0
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB      18
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK     0x0007ffff
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 19
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 20
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x00180000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET     0x00000004
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB        21
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB        26
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK       0x07e00000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB    27
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB    30
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK   0x78000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET   0x00000004
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB      31
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB      31
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK     0x80000000
+
+#endif
diff --git a/hw/peach/v1/mactx_vht_sig_b_su80.h b/hw/peach/v1/mactx_vht_sig_b_su80.h
new file mode 100644
index 000000000000..881918cbb865
--- /dev/null
+++ b/hw/peach/v1/mactx_vht_sig_b_su80.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_SU80_H_
+#define _MACTX_VHT_SIG_B_SU80_H_
+
+#include "vht_sig_b_su80_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4
+
+struct mactx_vht_sig_b_su80 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_b_su80_info                                       mactx_vht_sig_b_su80_info_details;
+#else
+             struct   vht_sig_b_su80_info                                       mactx_vht_sig_b_su80_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET        0x00000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB           0
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB           20
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK          0x001fffff
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB    21
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB    22
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK   0x00600000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET          0x00000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB             23
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB             28
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK            0x1f800000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET    0x00000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB       29
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB       30
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK      0x60000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET        0x00000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB           31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB           31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK          0x80000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB    0
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB    20
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK   0x001fffff
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 21
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 22
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET   0x00000004
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB      23
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB      28
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK     0x1f800000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET    0x00000004
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB       29
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB       30
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK      0x60000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB    31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB    31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK   0x80000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB    0
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB    20
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK   0x001fffff
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET   0x00000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB      23
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB      28
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK     0x1f800000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET    0x00000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB       29
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB       30
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK      0x60000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB    31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB    31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK   0x80000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB    0
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB    20
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK   0x001fffff
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 21
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 22
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET   0x0000000c
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB      23
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB      28
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK     0x1f800000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET    0x0000000c
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB       29
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB       30
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK      0x60000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB    31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB    31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK   0x80000000
+
+#endif
diff --git a/hw/peach/v1/mlo_sta_id_details.h b/hw/peach/v1/mlo_sta_id_details.h
new file mode 100644
index 000000000000..50448cc4e075
--- /dev/null
+++ b/hw/peach/v1/mlo_sta_id_details.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MLO_STA_ID_DETAILS_H_
+#define _MLO_STA_ID_DETAILS_H_
+
+#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1
+
+struct mlo_sta_id_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t nstr_mlo_sta_id                                         : 10,
+                      block_self_ml_sync                                      :  1,
+                      block_partner_ml_sync                                   :  1,
+                      nstr_mlo_sta_id_valid                                   :  1,
+                      reserved_0a                                             :  3;
+#else
+             uint16_t reserved_0a                                             :  3,
+                      nstr_mlo_sta_id_valid                                   :  1,
+                      block_partner_ml_sync                                   :  1,
+                      block_self_ml_sync                                      :  1,
+                      nstr_mlo_sta_id                                         : 10;
+#endif
+};
+
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET                                   0x00000000
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB                                      0
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB                                      9
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK                                     0x000003ff
+
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET                                0x00000000
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB                                   10
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB                                   10
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK                                  0x00000400
+
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET                             0x00000000
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB                                11
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB                                11
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK                               0x00000800
+
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET                             0x00000000
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB                                12
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB                                12
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK                               0x00001000
+
+#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET                                       0x00000000
+#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB                                          13
+#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB                                          15
+#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK                                         0x0000e000
+
+#endif
diff --git a/hw/peach/v1/mon_buffer_addr.h b/hw/peach/v1/mon_buffer_addr.h
new file mode 100644
index 000000000000..7c3c60a57d8f
--- /dev/null
+++ b/hw/peach/v1/mon_buffer_addr.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MON_BUFFER_ADDR_H_
+#define _MON_BUFFER_ADDR_H_
+
+#define NUM_OF_DWORDS_MON_BUFFER_ADDR 3
+
+struct mon_buffer_addr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t dma_length                                              : 12,
+                      reserved_2a                                             :  4,
+                      msdu_continuation                                       :  1,
+                      truncated                                               :  1,
+                      reserved_2b                                             : 14;
+#else
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t reserved_2b                                             : 14,
+                      truncated                                               :  1,
+                      msdu_continuation                                       :  1,
+                      reserved_2a                                             :  4,
+                      dma_length                                              : 12;
+#endif
+};
+
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET                                0x00000000
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB                                   0
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB                                   31
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK                                  0xffffffff
+
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET                               0x00000004
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB                                  0
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB                                  31
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK                                 0xffffffff
+
+#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET                                           0x00000008
+#define MON_BUFFER_ADDR_DMA_LENGTH_LSB                                              0
+#define MON_BUFFER_ADDR_DMA_LENGTH_MSB                                              11
+#define MON_BUFFER_ADDR_DMA_LENGTH_MASK                                             0x00000fff
+
+#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET                                          0x00000008
+#define MON_BUFFER_ADDR_RESERVED_2A_LSB                                             12
+#define MON_BUFFER_ADDR_RESERVED_2A_MSB                                             15
+#define MON_BUFFER_ADDR_RESERVED_2A_MASK                                            0x0000f000
+
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET                                    0x00000008
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB                                       16
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB                                       16
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK                                      0x00010000
+
+#define MON_BUFFER_ADDR_TRUNCATED_OFFSET                                            0x00000008
+#define MON_BUFFER_ADDR_TRUNCATED_LSB                                               17
+#define MON_BUFFER_ADDR_TRUNCATED_MSB                                               17
+#define MON_BUFFER_ADDR_TRUNCATED_MASK                                              0x00020000
+
+#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET                                          0x00000008
+#define MON_BUFFER_ADDR_RESERVED_2B_LSB                                             18
+#define MON_BUFFER_ADDR_RESERVED_2B_MSB                                             31
+#define MON_BUFFER_ADDR_RESERVED_2B_MASK                                            0xfffc0000
+
+#endif
diff --git a/hw/peach/v1/mon_destination_ring.h b/hw/peach/v1/mon_destination_ring.h
new file mode 100644
index 000000000000..e1feca4d70fd
--- /dev/null
+++ b/hw/peach/v1/mon_destination_ring.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MON_DESTINATION_RING_H_
+#define _MON_DESTINATION_RING_H_
+
+#define NUM_OF_DWORDS_MON_DESTINATION_RING 4
+
+struct mon_destination_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t stat_buf_virt_addr_31_0                                 : 32;
+             uint32_t stat_buf_virt_addr_63_32                                : 32;
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t end_offset                                              : 12,
+                      reserved_3a                                             :  2,
+                      link_info                                               :  2,
+                      end_reason                                              :  2,
+                      initiator                                               :  1,
+                      empty_descriptor                                        :  1,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t stat_buf_virt_addr_31_0                                 : 32;
+             uint32_t stat_buf_virt_addr_63_32                                : 32;
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      empty_descriptor                                        :  1,
+                      initiator                                               :  1,
+                      end_reason                                              :  2,
+                      link_info                                               :  2,
+                      reserved_3a                                             :  2,
+                      end_offset                                              : 12;
+#endif
+};
+
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET                         0x00000000
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB                            0
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB                            31
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK                           0xffffffff
+
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET                        0x00000004
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB                           0
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB                           31
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK                          0xffffffff
+
+#define MON_DESTINATION_RING_PPDU_ID_OFFSET                                         0x00000008
+#define MON_DESTINATION_RING_PPDU_ID_LSB                                            0
+#define MON_DESTINATION_RING_PPDU_ID_MSB                                            31
+#define MON_DESTINATION_RING_PPDU_ID_MASK                                           0xffffffff
+
+#define MON_DESTINATION_RING_END_OFFSET_OFFSET                                      0x0000000c
+#define MON_DESTINATION_RING_END_OFFSET_LSB                                         0
+#define MON_DESTINATION_RING_END_OFFSET_MSB                                         11
+#define MON_DESTINATION_RING_END_OFFSET_MASK                                        0x00000fff
+
+#define MON_DESTINATION_RING_RESERVED_3A_OFFSET                                     0x0000000c
+#define MON_DESTINATION_RING_RESERVED_3A_LSB                                        12
+#define MON_DESTINATION_RING_RESERVED_3A_MSB                                        13
+#define MON_DESTINATION_RING_RESERVED_3A_MASK                                       0x00003000
+
+#define MON_DESTINATION_RING_LINK_INFO_OFFSET                                       0x0000000c
+#define MON_DESTINATION_RING_LINK_INFO_LSB                                          14
+#define MON_DESTINATION_RING_LINK_INFO_MSB                                          15
+#define MON_DESTINATION_RING_LINK_INFO_MASK                                         0x0000c000
+
+#define MON_DESTINATION_RING_END_REASON_OFFSET                                      0x0000000c
+#define MON_DESTINATION_RING_END_REASON_LSB                                         16
+#define MON_DESTINATION_RING_END_REASON_MSB                                         17
+#define MON_DESTINATION_RING_END_REASON_MASK                                        0x00030000
+
+#define MON_DESTINATION_RING_INITIATOR_OFFSET                                       0x0000000c
+#define MON_DESTINATION_RING_INITIATOR_LSB                                          18
+#define MON_DESTINATION_RING_INITIATOR_MSB                                          18
+#define MON_DESTINATION_RING_INITIATOR_MASK                                         0x00040000
+
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET                                0x0000000c
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB                                   19
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB                                   19
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK                                  0x00080000
+
+#define MON_DESTINATION_RING_RING_ID_OFFSET                                         0x0000000c
+#define MON_DESTINATION_RING_RING_ID_LSB                                            20
+#define MON_DESTINATION_RING_RING_ID_MSB                                            27
+#define MON_DESTINATION_RING_RING_ID_MASK                                           0x0ff00000
+
+#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET                                   0x0000000c
+#define MON_DESTINATION_RING_LOOPING_COUNT_LSB                                      28
+#define MON_DESTINATION_RING_LOOPING_COUNT_MSB                                      31
+#define MON_DESTINATION_RING_LOOPING_COUNT_MASK                                     0xf0000000
+
+#endif
diff --git a/hw/peach/v1/mon_drop.h b/hw/peach/v1/mon_drop.h
new file mode 100644
index 000000000000..99d782f9f585
--- /dev/null
+++ b/hw/peach/v1/mon_drop.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MON_DROP_H_
+#define _MON_DROP_H_
+
+#define NUM_OF_DWORDS_MON_DROP 2
+
+struct mon_drop {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t ppdu_drop_cnt                                           : 10,
+                      mpdu_drop_cnt                                           : 10,
+                      tlv_drop_cnt                                            : 10,
+                      end_of_ppdu_seen                                        :  1,
+                      reserved_1a                                             :  1;
+#else
+             uint32_t ppdu_id                                                 : 32;
+             uint32_t reserved_1a                                             :  1,
+                      end_of_ppdu_seen                                        :  1,
+                      tlv_drop_cnt                                            : 10,
+                      mpdu_drop_cnt                                           : 10,
+                      ppdu_drop_cnt                                           : 10;
+#endif
+};
+
+#define MON_DROP_PPDU_ID_OFFSET                                                     0x00000000
+#define MON_DROP_PPDU_ID_LSB                                                        0
+#define MON_DROP_PPDU_ID_MSB                                                        31
+#define MON_DROP_PPDU_ID_MASK                                                       0xffffffff
+
+#define MON_DROP_PPDU_DROP_CNT_OFFSET                                               0x00000004
+#define MON_DROP_PPDU_DROP_CNT_LSB                                                  0
+#define MON_DROP_PPDU_DROP_CNT_MSB                                                  9
+#define MON_DROP_PPDU_DROP_CNT_MASK                                                 0x000003ff
+
+#define MON_DROP_MPDU_DROP_CNT_OFFSET                                               0x00000004
+#define MON_DROP_MPDU_DROP_CNT_LSB                                                  10
+#define MON_DROP_MPDU_DROP_CNT_MSB                                                  19
+#define MON_DROP_MPDU_DROP_CNT_MASK                                                 0x000ffc00
+
+#define MON_DROP_TLV_DROP_CNT_OFFSET                                                0x00000004
+#define MON_DROP_TLV_DROP_CNT_LSB                                                   20
+#define MON_DROP_TLV_DROP_CNT_MSB                                                   29
+#define MON_DROP_TLV_DROP_CNT_MASK                                                  0x3ff00000
+
+#define MON_DROP_END_OF_PPDU_SEEN_OFFSET                                            0x00000004
+#define MON_DROP_END_OF_PPDU_SEEN_LSB                                               30
+#define MON_DROP_END_OF_PPDU_SEEN_MSB                                               30
+#define MON_DROP_END_OF_PPDU_SEEN_MASK                                              0x40000000
+
+#define MON_DROP_RESERVED_1A_OFFSET                                                 0x00000004
+#define MON_DROP_RESERVED_1A_LSB                                                    31
+#define MON_DROP_RESERVED_1A_MSB                                                    31
+#define MON_DROP_RESERVED_1A_MASK                                                   0x80000000
+
+#endif
diff --git a/hw/peach/v1/mon_ingress_ring.h b/hw/peach/v1/mon_ingress_ring.h
new file mode 100644
index 000000000000..f284a530bb58
--- /dev/null
+++ b/hw/peach/v1/mon_ingress_ring.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MON_INGRESS_RING_H_
+#define _MON_INGRESS_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_MON_INGRESS_RING 4
+
+struct mon_ingress_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+#else
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+#endif
+};
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET           0x00000000
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB              0
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB              31
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK             0xffffffff
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET          0x00000004
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB             0
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB             7
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK            0x000000ff
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET      0x00000004
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB         8
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB         11
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK        0x00000f00
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET           0x00000004
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB              12
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB              31
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK             0xfffff000
+
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET                               0x00000008
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB                                  0
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB                                  31
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK                                 0xffffffff
+
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET                              0x0000000c
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB                                 0
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB                                 31
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK                                0xffffffff
+
+#endif
diff --git a/hw/peach/v1/msmhwiobase.h b/hw/peach/v1/msmhwiobase.h
new file mode 100644
index 000000000000..a251141f304a
--- /dev/null
+++ b/hw/peach/v1/msmhwiobase.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef __MSMHWIOBASE_H__
+#define __MSMHWIOBASE_H__
+
+#define WCSS_WCSS_BASE                                              0x00000000
+#define WCSS_WCSS_BASE_SIZE                                         0x01000000
+#define WCSS_WCSS_BASE_PHYS                                         0x00000000
+
+#define QDSS_STM_SIZE_BASE                                          0x00100000
+#define QDSS_STM_SIZE_BASE_SIZE                                     0x100000000
+#define QDSS_STM_SIZE_BASE_PHYS                                     0x00100000
+
+#define BOOT_ROM_SIZE_BASE                                          0x00200000
+#define BOOT_ROM_SIZE_BASE_SIZE                                     0x100000000
+#define BOOT_ROM_SIZE_BASE_PHYS                                     0x00200000
+
+#define SYSTEM_IRAM_SIZE_BASE                                       0x00400000
+#define SYSTEM_IRAM_SIZE_BASE_SIZE                                  0x100000000
+#define SYSTEM_IRAM_SIZE_BASE_PHYS                                  0x00400000
+
+#define BOOT_ROM_START_ADDRESS_BASE                                 0x01200000
+#define BOOT_ROM_START_ADDRESS_BASE_SIZE                            0x100000000
+#define BOOT_ROM_START_ADDRESS_BASE_PHYS                            0x01200000
+
+#define BOOT_ROM_END_ADDRESS_BASE                                   0x013fffff
+#define BOOT_ROM_END_ADDRESS_BASE_SIZE                              0x100000000
+#define BOOT_ROM_END_ADDRESS_BASE_PHYS                              0x013fffff
+
+#define SYSTEM_IRAM_START_ADDRESS_BASE                              0x01400000
+#define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE                         0x100000000
+#define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS                         0x01400000
+
+#define SYSTEM_IRAM_END_ADDRESS_BASE                                0x017fffff
+#define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE                           0x100000000
+#define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS                           0x017fffff
+
+#define QDSS_STM_BASE                                               0x01800000
+#define QDSS_STM_BASE_SIZE                                          0x100000000
+#define QDSS_STM_BASE_PHYS                                          0x01800000
+
+#define QDSS_STM_END_BASE                                           0x018fffff
+#define QDSS_STM_END_BASE_SIZE                                      0x100000000
+#define QDSS_STM_END_BASE_PHYS                                      0x018fffff
+
+#define TLMM_BASE                                                   0x01900000
+#define TLMM_BASE_SIZE                                              0x00200000
+#define TLMM_BASE_PHYS                                              0x01900000
+
+#define CORE_TOP_CSR_BASE                                           0x01b00000
+#define CORE_TOP_CSR_BASE_SIZE                                      0x00040000
+#define CORE_TOP_CSR_BASE_PHYS                                      0x01b00000
+
+#define BLSP1_BLSP_BASE                                             0x01b40000
+#define BLSP1_BLSP_BASE_SIZE                                        0x00040000
+#define BLSP1_BLSP_BASE_PHYS                                        0x01b40000
+
+#define SOC_WFSS_CE_REG_BASE                                        0x01b80000
+#define SOC_WFSS_CE_REG_BASE_SIZE                                   0x0001c000
+#define SOC_WFSS_CE_REG_BASE_PHYS                                   0x01b80000
+
+#define WL_TLMM_BASE                                                0x01bc0000
+#define WL_TLMM_BASE_SIZE                                           0x00020000
+#define WL_TLMM_BASE_PHYS                                           0x01bc0000
+
+#define MEMSS_CSR_BASE                                              0x01be0000
+#define MEMSS_CSR_BASE_SIZE                                         0x0000001c
+#define MEMSS_CSR_BASE_PHYS                                         0x01be0000
+
+#define TSENS_SROT_BASE                                             0x01bf0000
+#define TSENS_SROT_BASE_SIZE                                        0x00001000
+#define TSENS_SROT_BASE_PHYS                                        0x01bf0000
+
+#define TSENS_TM_BASE                                               0x01bf1000
+#define TSENS_TM_BASE_SIZE                                          0x00001000
+#define TSENS_TM_BASE_PHYS                                          0x01bf1000
+
+#define QDSS_APB_DEC_QDSS_APB_BASE                                  0x01c00000
+#define QDSS_APB_DEC_QDSS_APB_BASE_SIZE                             0x00080000
+#define QDSS_APB_DEC_QDSS_APB_BASE_PHYS                             0x01c00000
+
+#define QDSS_WRAPPER_TOP_BASE                                       0x01c80000
+#define QDSS_WRAPPER_TOP_BASE_SIZE                                  0x0007fffd
+#define QDSS_WRAPPER_TOP_BASE_PHYS                                  0x01c80000
+
+#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE                 0x01d00000
+#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE            0x00100000
+#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS            0x01d00000
+
+#define PCIE_PCIE_TOP_WRAPPER_BASE                                  0x01e00000
+#define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE                             0x00020000
+#define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS                             0x01e00000
+
+#define SECURITY_CONTROL_WLAN_BASE                                  0x01e20000
+#define SECURITY_CONTROL_WLAN_BASE_SIZE                             0x00008000
+#define SECURITY_CONTROL_WLAN_BASE_PHYS                             0x01e20000
+
+#define EDPD_CAL_ACC_BASE                                           0x01e28000
+#define EDPD_CAL_ACC_BASE_SIZE                                      0x00003000
+#define EDPD_CAL_ACC_BASE_PHYS                                      0x01e28000
+
+#define CPR_CX_CPR3_BASE                                            0x01e30000
+#define CPR_CX_CPR3_BASE_SIZE                                       0x00004000
+#define CPR_CX_CPR3_BASE_PHYS                                       0x01e30000
+
+#define CPR_MX_CPR3_BASE                                            0x01e34000
+#define CPR_MX_CPR3_BASE_SIZE                                       0x00004000
+#define CPR_MX_CPR3_BASE_PHYS                                       0x01e34000
+
+#define GCC_GCC_BASE                                                0x01e40000
+#define GCC_GCC_BASE_SIZE                                           0x000003e8
+#define GCC_GCC_BASE_PHYS                                           0x01e40000
+
+#define PRNG_PRNG_TOP_BASE                                          0x01e50000
+#define PRNG_PRNG_TOP_BASE_SIZE                                     0x00010000
+#define PRNG_PRNG_TOP_BASE_PHYS                                     0x01e50000
+
+#define PCNOC_0_BUS_TIMEOUT_BASE                                    0x01e60000
+#define PCNOC_0_BUS_TIMEOUT_BASE_SIZE                               0x00001000
+#define PCNOC_0_BUS_TIMEOUT_BASE_PHYS                               0x01e60000
+
+#define PCNOC_1_BUS_TIMEOUT_BASE                                    0x01e61000
+#define PCNOC_1_BUS_TIMEOUT_BASE_SIZE                               0x00001000
+#define PCNOC_1_BUS_TIMEOUT_BASE_PHYS                               0x01e61000
+
+#define PCNOC_2_BUS_TIMEOUT_BASE                                    0x01e62000
+#define PCNOC_2_BUS_TIMEOUT_BASE_SIZE                               0x00001000
+#define PCNOC_2_BUS_TIMEOUT_BASE_PHYS                               0x01e62000
+
+#define PCNOC_3_BUS_TIMEOUT_BASE                                    0x01e63000
+#define PCNOC_3_BUS_TIMEOUT_BASE_SIZE                               0x00001000
+#define PCNOC_3_BUS_TIMEOUT_BASE_PHYS                               0x01e63000
+
+#define RRI_PREFETCH_REG_BASE                                       0x01e70000
+#define RRI_PREFETCH_REG_BASE_SIZE                                  0x00010000
+#define RRI_PREFETCH_REG_BASE_PHYS                                  0x01e70000
+
+#define SYSTEM_NOC_BASE                                             0x01e80000
+#define SYSTEM_NOC_BASE_SIZE                                        0x0000a000
+#define SYSTEM_NOC_BASE_PHYS                                        0x01e80000
+
+#define PC_NOC_BASE                                                 0x01f00000
+#define PC_NOC_BASE_SIZE                                            0x00003880
+#define PC_NOC_BASE_PHYS                                            0x01f00000
+
+#define WLAON_WL_AON_REG_BASE                                       0x01f80000
+#define WLAON_WL_AON_REG_BASE_SIZE                                  0x000007c8
+#define WLAON_WL_AON_REG_BASE_PHYS                                  0x01f80000
+
+#define SYSPM_SYSPM_REG_BASE                                        0x01f82000
+#define SYSPM_SYSPM_REG_BASE_SIZE                                   0x00001000
+#define SYSPM_SYSPM_REG_BASE_PHYS                                   0x01f82000
+
+#define PMU_WLAN_PMU_TOP_BASE                                       0x01f88000
+#define PMU_WLAN_PMU_TOP_BASE_SIZE                                  0x00000340
+#define PMU_WLAN_PMU_TOP_BASE_PHYS                                  0x01f88000
+
+#define PMU_NOC_BASE                                                0x01f8a000
+#define PMU_NOC_BASE_SIZE                                           0x00000080
+#define PMU_NOC_BASE_PHYS                                           0x01f8a000
+
+#define PCIE_ATU_REGION_BASE                                        0x04000000
+#define PCIE_ATU_REGION_BASE_SIZE                                   0x100000000
+#define PCIE_ATU_REGION_BASE_PHYS                                   0x04000000
+
+#define PCIE_ATU_REGION_SIZE_BASE                                   0x40000000
+#define PCIE_ATU_REGION_SIZE_BASE_SIZE                              0x100000000
+#define PCIE_ATU_REGION_SIZE_BASE_PHYS                              0x40000000
+
+#define PCIE_ATU_REGION_END_BASE                                    0x43ffffff
+#define PCIE_ATU_REGION_END_BASE_SIZE                               0x100000000
+#define PCIE_ATU_REGION_END_BASE_PHYS                               0x43ffffff
+
+#endif
diff --git a/hw/peach/v1/msmhwioreg.h b/hw/peach/v1/msmhwioreg.h
new file mode 100644
index 000000000000..4953fc29e482
--- /dev/null
+++ b/hw/peach/v1/msmhwioreg.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __MSMHWIOREG_H__
+#define __MSMHWIOREG_H__
+
+#include "msmhwiobase.h"
+
+#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x00001000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR                                                         (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000408)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK                                                    0xffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT                                                       0x0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
+#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK								0xfffffffc
+#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT								0x2
+#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR                                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK                                                   0xffffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                0xffffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                       0x0
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR                                                   (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000004)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK                                                     0xffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK                                           0xffff00
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT                                                0x8
+#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE                                                                      (SOC_WFSS_CE_REG_BASE      + 0x00003000)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR                                                         (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE      + 0x00000400)
+#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE                                                                   (SOC_WFSS_CE_REG_BASE      + 0x00002000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK                                                     0xffffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK                                  0xffffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT                                         0x0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR                                                     (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000004)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK                                                       0xffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN          \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m)      \
+        in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v)      \
+        out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
+        out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK                                             0xffff00
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT                                                  0x8
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                        0xff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                         0x0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR                                                           (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000400)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR                                                   (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE      + 0x00000058)
+
+
+#endif
diff --git a/hw/peach/v1/no_ack_report.h b/hw/peach/v1/no_ack_report.h
new file mode 100644
index 000000000000..c80f32fe47d2
--- /dev/null
+++ b/hw/peach/v1/no_ack_report.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _NO_ACK_REPORT_H_
+#define _NO_ACK_REPORT_H_
+
+#define NUM_OF_DWORDS_NO_ACK_REPORT 4
+
+struct no_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t no_ack_transmit_reason                                  :  4,
+                      macrx_abort_reason                                      :  4,
+                      phyrx_abort_reason                                      :  8,
+                      frame_control                                           : 16;
+             uint32_t rx_ppdu_duration                                        : 24,
+                      sr_ppdu_during_obss                                     :  1,
+                      selfgen_response_reason_to_sr_ppdu                      :  4,
+                      reserved_1                                              :  3;
+             uint32_t pre_bt_broadcast_status_details                         : 12,
+                      first_bt_broadcast_status_details                       : 12,
+                      reserved_2                                              :  8;
+             uint32_t second_bt_broadcast_status_details                      : 12,
+                      reserved_3                                              : 20;
+#else
+             uint32_t frame_control                                           : 16,
+                      phyrx_abort_reason                                      :  8,
+                      macrx_abort_reason                                      :  4,
+                      no_ack_transmit_reason                                  :  4;
+             uint32_t reserved_1                                              :  3,
+                      selfgen_response_reason_to_sr_ppdu                      :  4,
+                      sr_ppdu_during_obss                                     :  1,
+                      rx_ppdu_duration                                        : 24;
+             uint32_t reserved_2                                              :  8,
+                      first_bt_broadcast_status_details                       : 12,
+                      pre_bt_broadcast_status_details                         : 12;
+             uint32_t reserved_3                                              : 20,
+                      second_bt_broadcast_status_details                      : 12;
+#endif
+};
+
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET                                 0x00000000
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB                                    0
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB                                    3
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK                                   0x0000000f
+
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET                                     0x00000000
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB                                        4
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB                                        7
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK                                       0x000000f0
+
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET                                     0x00000000
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB                                        8
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB                                        15
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK                                       0x0000ff00
+
+#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET                                          0x00000000
+#define NO_ACK_REPORT_FRAME_CONTROL_LSB                                             16
+#define NO_ACK_REPORT_FRAME_CONTROL_MSB                                             31
+#define NO_ACK_REPORT_FRAME_CONTROL_MASK                                            0xffff0000
+
+#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET                                       0x00000004
+#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB                                          0
+#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB                                          23
+#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK                                         0x00ffffff
+
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET                                    0x00000004
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB                                       24
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB                                       24
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK                                      0x01000000
+
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET                     0x00000004
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB                        25
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB                        28
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK                       0x1e000000
+
+#define NO_ACK_REPORT_RESERVED_1_OFFSET                                             0x00000004
+#define NO_ACK_REPORT_RESERVED_1_LSB                                                29
+#define NO_ACK_REPORT_RESERVED_1_MSB                                                31
+#define NO_ACK_REPORT_RESERVED_1_MASK                                               0xe0000000
+
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET                        0x00000008
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB                           0
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB                           11
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK                          0x00000fff
+
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET                      0x00000008
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB                         12
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB                         23
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK                        0x00fff000
+
+#define NO_ACK_REPORT_RESERVED_2_OFFSET                                             0x00000008
+#define NO_ACK_REPORT_RESERVED_2_LSB                                                24
+#define NO_ACK_REPORT_RESERVED_2_MSB                                                31
+#define NO_ACK_REPORT_RESERVED_2_MASK                                               0xff000000
+
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET                     0x0000000c
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB                        0
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB                        11
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK                       0x00000fff
+
+#define NO_ACK_REPORT_RESERVED_3_OFFSET                                             0x0000000c
+#define NO_ACK_REPORT_RESERVED_3_LSB                                                12
+#define NO_ACK_REPORT_RESERVED_3_MSB                                                31
+#define NO_ACK_REPORT_RESERVED_3_MASK                                               0xfffff000
+
+#endif
diff --git a/hw/peach/v1/ofdma_trigger_details.h b/hw/peach/v1/ofdma_trigger_details.h
new file mode 100644
index 000000000000..e842d347bb56
--- /dev/null
+++ b/hw/peach/v1/ofdma_trigger_details.h
@@ -0,0 +1,834 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _OFDMA_TRIGGER_DETAILS_H_
+#define _OFDMA_TRIGGER_DETAILS_H_
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22
+
+struct ofdma_trigger_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ax_trigger_source                                       :  1,
+                      rx_trigger_frame_user_source                            :  2,
+                      received_bandwidth                                      :  3,
+                      txop_duration_all_ones                                  :  1,
+                      eht_trigger_response                                    :  1,
+                      pre_rssi_comb                                           :  8,
+                      rssi_comb                                               :  8,
+                      rxpcu_pcie_l0_req_duration                              :  8;
+             uint32_t he_trigger_ul_ppdu_length                               :  5,
+                      he_trigger_ru_allocation                                :  8,
+                      he_trigger_dl_tx_power                                  :  5,
+                      he_trigger_ul_target_rssi                               :  5,
+                      he_trigger_ul_mcs                                       :  2,
+                      he_trigger_reserved                                     :  1,
+                      bss_color                                               :  6;
+             uint32_t trigger_type                                            :  4,
+                      lsig_response_length                                    : 12,
+                      cascade_indication                                      :  1,
+                      carrier_sense                                           :  1,
+                      bandwidth                                               :  2,
+                      cp_ltf_size                                             :  2,
+                      mu_mimo_ltf_mode                                        :  1,
+                      number_of_ltfs                                          :  3,
+                      stbc                                                    :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      ap_tx_power_lsb_part                                    :  4;
+             uint32_t ap_tx_power_msb_part                                    :  2,
+                      packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      spatial_reuse                                           : 16,
+                      doppler                                                 :  1,
+                      he_siga_reserved                                        :  9,
+                      reserved_3b                                             :  1;
+             uint32_t aid12                                                   : 12,
+                      ru_allocation                                           :  9,
+                      mcs                                                     :  4,
+                      dcm                                                     :  1,
+                      start_spatial_stream                                    :  3,
+                      number_of_spatial_stream                                :  3;
+             uint32_t target_rssi                                             :  7,
+                      coding_type                                             :  1,
+                      mpdu_mu_spacing_factor                                  :  2,
+                      tid_aggregation_limit                                   :  3,
+                      reserved_5b                                             :  1,
+                      prefered_ac                                             :  2,
+                      bar_control_ack_policy                                  :  1,
+                      bar_control_multi_tid                                   :  1,
+                      bar_control_compressed_bitmap                           :  1,
+                      bar_control_reserved                                    :  9,
+                      bar_control_tid_info                                    :  4;
+             uint32_t nr0_per_tid_info_reserved                               : 12,
+                      nr0_per_tid_info_tid_value                              :  4,
+                      nr0_start_seq_ctrl_frag_number                          :  4,
+                      nr0_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr1_per_tid_info_reserved                               : 12,
+                      nr1_per_tid_info_tid_value                              :  4,
+                      nr1_start_seq_ctrl_frag_number                          :  4,
+                      nr1_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr2_per_tid_info_reserved                               : 12,
+                      nr2_per_tid_info_tid_value                              :  4,
+                      nr2_start_seq_ctrl_frag_number                          :  4,
+                      nr2_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr3_per_tid_info_reserved                               : 12,
+                      nr3_per_tid_info_tid_value                              :  4,
+                      nr3_start_seq_ctrl_frag_number                          :  4,
+                      nr3_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr4_per_tid_info_reserved                               : 12,
+                      nr4_per_tid_info_tid_value                              :  4,
+                      nr4_start_seq_ctrl_frag_number                          :  4,
+                      nr4_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr5_per_tid_info_reserved                               : 12,
+                      nr5_per_tid_info_tid_value                              :  4,
+                      nr5_start_seq_ctrl_frag_number                          :  4,
+                      nr5_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr6_per_tid_info_reserved                               : 12,
+                      nr6_per_tid_info_tid_value                              :  4,
+                      nr6_start_seq_ctrl_frag_number                          :  4,
+                      nr6_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t nr7_per_tid_info_reserved                               : 12,
+                      nr7_per_tid_info_tid_value                              :  4,
+                      nr7_start_seq_ctrl_frag_number                          :  4,
+                      nr7_start_seq_ctrl_start_seq_number                     : 12;
+             uint32_t fb_segment_retransmission_bitmap                        :  8,
+                      reserved_14a                                            :  2,
+                      u_sig_puncture_pattern_encoding                         :  6,
+                      dot11be_puncture_bitmap                                 : 16;
+             uint32_t rx_chain_mask                                           :  8,
+                      rx_duration_field                                       : 16,
+                      scrambler_seed                                          :  7,
+                      rx_chain_mask_type                                      :  1;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint16_t normalized_pre_rssi_comb                                :  8,
+                      normalized_rssi_comb                                    :  8;
+             uint32_t sw_peer_id                                              : 16,
+                      response_tx_duration                                    : 16;
+             uint32_t __reserved_g_0005_trigger_subtype                                 :  4,
+                      tbr_trigger_common_info_79_68                           : 12,
+                      tbr_trigger_sound_reserved_20_12                        :  9,
+                      i2r_rep                                                 :  3,
+                      tbr_trigger_sound_reserved_25_24                        :  2,
+                      reserved_18a                                            :  1,
+                      qos_null_only_response_tx                               :  1;
+             uint32_t tbr_trigger_sound_sac                                   : 16,
+                      reserved_19a                                            :  8,
+                      u_sig_reserved2                                         :  5,
+                      reserved_19b                                            :  3;
+             uint32_t eht_special_aid12                                       : 12,
+                      phy_version                                             :  3,
+                      bandwidth_ext                                           :  2,
+                      eht_spatial_reuse                                       :  8,
+                      u_sig_reserved1                                         :  7;
+             uint32_t eht_trigger_special_user_info_71_40                     : 32;
+#else
+             uint32_t rxpcu_pcie_l0_req_duration                              :  8,
+                      rssi_comb                                               :  8,
+                      pre_rssi_comb                                           :  8,
+                      eht_trigger_response                                    :  1,
+                      txop_duration_all_ones                                  :  1,
+                      received_bandwidth                                      :  3,
+                      rx_trigger_frame_user_source                            :  2,
+                      ax_trigger_source                                       :  1;
+             uint32_t bss_color                                               :  6,
+                      he_trigger_reserved                                     :  1,
+                      he_trigger_ul_mcs                                       :  2,
+                      he_trigger_ul_target_rssi                               :  5,
+                      he_trigger_dl_tx_power                                  :  5,
+                      he_trigger_ru_allocation                                :  8,
+                      he_trigger_ul_ppdu_length                               :  5;
+             uint32_t ap_tx_power_lsb_part                                    :  4,
+                      ldpc_extra_symbol                                       :  1,
+                      stbc                                                    :  1,
+                      number_of_ltfs                                          :  3,
+                      mu_mimo_ltf_mode                                        :  1,
+                      cp_ltf_size                                             :  2,
+                      bandwidth                                               :  2,
+                      carrier_sense                                           :  1,
+                      cascade_indication                                      :  1,
+                      lsig_response_length                                    : 12,
+                      trigger_type                                            :  4;
+             uint32_t reserved_3b                                             :  1,
+                      he_siga_reserved                                        :  9,
+                      doppler                                                 :  1,
+                      spatial_reuse                                           : 16,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2,
+                      ap_tx_power_msb_part                                    :  2;
+             uint32_t number_of_spatial_stream                                :  3,
+                      start_spatial_stream                                    :  3,
+                      dcm                                                     :  1,
+                      mcs                                                     :  4,
+                      ru_allocation                                           :  9,
+                      aid12                                                   : 12;
+             uint32_t bar_control_tid_info                                    :  4,
+                      bar_control_reserved                                    :  9,
+                      bar_control_compressed_bitmap                           :  1,
+                      bar_control_multi_tid                                   :  1,
+                      bar_control_ack_policy                                  :  1,
+                      prefered_ac                                             :  2,
+                      reserved_5b                                             :  1,
+                      tid_aggregation_limit                                   :  3,
+                      mpdu_mu_spacing_factor                                  :  2,
+                      coding_type                                             :  1,
+                      target_rssi                                             :  7;
+             uint32_t nr0_start_seq_ctrl_start_seq_number                     : 12,
+                      nr0_start_seq_ctrl_frag_number                          :  4,
+                      nr0_per_tid_info_tid_value                              :  4,
+                      nr0_per_tid_info_reserved                               : 12;
+             uint32_t nr1_start_seq_ctrl_start_seq_number                     : 12,
+                      nr1_start_seq_ctrl_frag_number                          :  4,
+                      nr1_per_tid_info_tid_value                              :  4,
+                      nr1_per_tid_info_reserved                               : 12;
+             uint32_t nr2_start_seq_ctrl_start_seq_number                     : 12,
+                      nr2_start_seq_ctrl_frag_number                          :  4,
+                      nr2_per_tid_info_tid_value                              :  4,
+                      nr2_per_tid_info_reserved                               : 12;
+             uint32_t nr3_start_seq_ctrl_start_seq_number                     : 12,
+                      nr3_start_seq_ctrl_frag_number                          :  4,
+                      nr3_per_tid_info_tid_value                              :  4,
+                      nr3_per_tid_info_reserved                               : 12;
+             uint32_t nr4_start_seq_ctrl_start_seq_number                     : 12,
+                      nr4_start_seq_ctrl_frag_number                          :  4,
+                      nr4_per_tid_info_tid_value                              :  4,
+                      nr4_per_tid_info_reserved                               : 12;
+             uint32_t nr5_start_seq_ctrl_start_seq_number                     : 12,
+                      nr5_start_seq_ctrl_frag_number                          :  4,
+                      nr5_per_tid_info_tid_value                              :  4,
+                      nr5_per_tid_info_reserved                               : 12;
+             uint32_t nr6_start_seq_ctrl_start_seq_number                     : 12,
+                      nr6_start_seq_ctrl_frag_number                          :  4,
+                      nr6_per_tid_info_tid_value                              :  4,
+                      nr6_per_tid_info_reserved                               : 12;
+             uint32_t nr7_start_seq_ctrl_start_seq_number                     : 12,
+                      nr7_start_seq_ctrl_frag_number                          :  4,
+                      nr7_per_tid_info_tid_value                              :  4,
+                      nr7_per_tid_info_reserved                               : 12;
+             uint32_t dot11be_puncture_bitmap                                 : 16,
+                      u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_14a                                            :  2,
+                      fb_segment_retransmission_bitmap                        :  8;
+             uint32_t rx_chain_mask_type                                      :  1,
+                      scrambler_seed                                          :  7,
+                      rx_duration_field                                       : 16,
+                      rx_chain_mask                                           :  8;
+             uint32_t normalized_rssi_comb                                    :  8,
+                      normalized_pre_rssi_comb                                :  8;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint32_t response_tx_duration                                    : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t qos_null_only_response_tx                               :  1,
+                      reserved_18a                                            :  1,
+                      tbr_trigger_sound_reserved_25_24                        :  2,
+                      i2r_rep                                                 :  3,
+                      tbr_trigger_sound_reserved_20_12                        :  9,
+                      tbr_trigger_common_info_79_68                           : 12,
+                      __reserved_g_0005_trigger_subtype                                 :  4;
+             uint32_t reserved_19b                                            :  3,
+                      u_sig_reserved2                                         :  5,
+                      reserved_19a                                            :  8,
+                      tbr_trigger_sound_sac                                   : 16;
+             uint32_t u_sig_reserved1                                         :  7,
+                      eht_spatial_reuse                                       :  8,
+                      bandwidth_ext                                           :  2,
+                      phy_version                                             :  3,
+                      eht_special_aid12                                       : 12;
+             uint32_t eht_trigger_special_user_info_71_40                     : 32;
+#endif
+};
+
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET                              0x00000000
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB                                 0
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB                                 0
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK                                0x00000001
+
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET                   0x00000000
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB                      1
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB                      2
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK                     0x00000006
+
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET                             0x00000000
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB                                3
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB                                5
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK                               0x00000038
+
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET                         0x00000000
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB                            6
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB                            6
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK                           0x00000040
+
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET                           0x00000000
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB                              7
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB                              7
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK                             0x00000080
+
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET                                  0x00000000
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB                                     8
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB                                     15
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK                                    0x0000ff00
+
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET                                      0x00000000
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB                                         16
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB                                         23
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK                                        0x00ff0000
+
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET                     0x00000000
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB                        24
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB                        31
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK                       0xff000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET                      0x00000004
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB                         4
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK                        0x0000001f
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET                       0x00000004
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB                          5
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB                          12
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK                         0x00001fe0
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET                         0x00000004
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB                            13
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB                            17
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK                           0x0003e000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET                      0x00000004
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB                         18
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB                         22
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK                        0x007c0000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET                              0x00000004
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB                                 23
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB                                 24
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK                                0x01800000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET                            0x00000004
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB                               25
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB                               25
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK                              0x02000000
+
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET                                      0x00000004
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB                                         26
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB                                         31
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK                                        0xfc000000
+
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET                                   0x00000008
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB                                      0
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB                                      3
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK                                     0x0000000f
+
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET                           0x00000008
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB                              4
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB                              15
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK                             0x0000fff0
+
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET                             0x00000008
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB                                16
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB                                16
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK                               0x00010000
+
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET                                  0x00000008
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB                                     17
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB                                     17
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK                                    0x00020000
+
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET                                      0x00000008
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB                                         18
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB                                         19
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK                                        0x000c0000
+
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET                                    0x00000008
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB                                       20
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB                                       21
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK                                      0x00300000
+
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET                               0x00000008
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB                                  22
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB                                  22
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK                                 0x00400000
+
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET                                 0x00000008
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB                                    23
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB                                    25
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK                                   0x03800000
+
+#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET                                           0x00000008
+#define OFDMA_TRIGGER_DETAILS_STBC_LSB                                              26
+#define OFDMA_TRIGGER_DETAILS_STBC_MSB                                              26
+#define OFDMA_TRIGGER_DETAILS_STBC_MASK                                             0x04000000
+
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET                              0x00000008
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB                                 27
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB                                 27
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK                                0x08000000
+
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET                           0x00000008
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB                              28
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB                              31
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK                             0xf0000000
+
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET                           0x0000000c
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB                              0
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB                              1
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK                             0x00000003
+
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET                      0x0000000c
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB                         2
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB                         3
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK                        0x0000000c
+
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET               0x0000000c
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                  4
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                  4
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                 0x00000010
+
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET                                  0x0000000c
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB                                     5
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB                                     20
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK                                    0x001fffe0
+
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET                                        0x0000000c
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB                                           21
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB                                           21
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK                                          0x00200000
+
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET                               0x0000000c
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB                                  22
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB                                  30
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK                                 0x7fc00000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET                                    0x0000000c
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB                                       31
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB                                       31
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK                                      0x80000000
+
+#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET                                          0x00000010
+#define OFDMA_TRIGGER_DETAILS_AID12_LSB                                             0
+#define OFDMA_TRIGGER_DETAILS_AID12_MSB                                             11
+#define OFDMA_TRIGGER_DETAILS_AID12_MASK                                            0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET                                  0x00000010
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB                                     12
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB                                     20
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK                                    0x001ff000
+
+#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET                                            0x00000010
+#define OFDMA_TRIGGER_DETAILS_MCS_LSB                                               21
+#define OFDMA_TRIGGER_DETAILS_MCS_MSB                                               24
+#define OFDMA_TRIGGER_DETAILS_MCS_MASK                                              0x01e00000
+
+#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET                                            0x00000010
+#define OFDMA_TRIGGER_DETAILS_DCM_LSB                                               25
+#define OFDMA_TRIGGER_DETAILS_DCM_MSB                                               25
+#define OFDMA_TRIGGER_DETAILS_DCM_MASK                                              0x02000000
+
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET                           0x00000010
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB                              26
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB                              28
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK                             0x1c000000
+
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET                       0x00000010
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB                          29
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB                          31
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK                         0xe0000000
+
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET                                    0x00000014
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB                                       0
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB                                       6
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK                                      0x0000007f
+
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET                                    0x00000014
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB                                       7
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB                                       7
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK                                      0x00000080
+
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET                         0x00000014
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB                            8
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB                            9
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK                           0x00000300
+
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET                          0x00000014
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB                             10
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB                             12
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK                            0x00001c00
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET                                    0x00000014
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB                                       13
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB                                       13
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK                                      0x00002000
+
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET                                    0x00000014
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB                                       14
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB                                       15
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK                                      0x0000c000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET                         0x00000014
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB                            16
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB                            16
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK                           0x00010000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET                          0x00000014
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB                             17
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB                             17
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK                            0x00020000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET                  0x00000014
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB                     18
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB                     18
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK                    0x00040000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET                           0x00000014
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB                              19
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB                              27
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK                             0x0ff80000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET                           0x00000014
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB                              28
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB                              31
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK                             0xf0000000
+
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET                      0x00000018
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK                        0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET                     0x00000018
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK                       0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x00000018
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x00000018
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET                      0x0000001c
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK                        0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000001c
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK                       0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000001c
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000001c
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET                      0x00000020
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK                        0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET                     0x00000020
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK                       0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x00000020
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x00000020
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET                      0x00000024
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK                        0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET                     0x00000024
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK                       0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x00000024
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x00000024
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET                      0x00000028
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK                        0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET                     0x00000028
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK                       0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x00000028
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x00000028
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET                      0x0000002c
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK                        0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET                     0x0000002c
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK                       0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x0000002c
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x0000002c
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET                      0x00000030
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK                        0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET                     0x00000030
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK                       0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x00000030
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x00000030
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET                      0x00000034
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB                         0
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB                         11
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK                        0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET                     0x00000034
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB                        12
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB                        15
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK                       0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET                 0x00000034
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB                    16
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB                    19
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK                   0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET            0x00000034
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB               20
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB               31
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK              0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET               0x00000038
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB                  0
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB                  7
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK                 0x000000ff
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET                                   0x00000038
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB                                      8
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB                                      9
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK                                     0x00000300
+
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET                0x00000038
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                   10
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                   15
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                  0x0000fc00
+
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET                        0x00000038
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB                           16
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB                           31
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK                          0xffff0000
+
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET                                  0x0000003c
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB                                     0
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB                                     7
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK                                    0x000000ff
+
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET                              0x0000003c
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB                                 8
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB                                 23
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK                                0x00ffff00
+
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET                                 0x0000003c
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB                                    24
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB                                    30
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK                                   0x7f000000
+
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET                             0x0000003c
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB                                31
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB                                31
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK                               0x80000000
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET          0x00000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB             0
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB             9
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK            0x000003ff
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET       0x00000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB          10
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB          10
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK         0x00000400
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET    0x00000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB       11
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB       11
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK      0x00000800
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET    0x00000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB       12
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB       12
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK      0x00001000
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET              0x00000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB                 13
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB                 15
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK                0x0000e000
+
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET                       0x00000040
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB                          16
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB                          23
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK                         0x00ff0000
+
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET                           0x00000040
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB                              24
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB                              31
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK                             0xff000000
+
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET                                     0x00000044
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB                                        0
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB                                        15
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK                                       0x0000ffff
+
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET                           0x00000044
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB                              16
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB                              31
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK                             0xffff0000
+
+#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET                        0x00000048
+#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB                           0
+#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB                           3
+#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK                          0x0000000f
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET                  0x00000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB                     4
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB                     15
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK                    0x0000fff0
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET               0x00000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB                  16
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB                  24
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK                 0x01ff0000
+
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET                                        0x00000048
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB                                           25
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB                                           27
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK                                          0x0e000000
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET               0x00000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB                  28
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB                  29
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK                 0x30000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET                                   0x00000048
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB                                      30
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB                                      30
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK                                     0x40000000
+
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET                      0x00000048
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB                         31
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB                         31
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK                        0x80000000
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET                          0x0000004c
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB                             0
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB                             15
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK                            0x0000ffff
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET                                   0x0000004c
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB                                      16
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB                                      23
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK                                     0x00ff0000
+
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET                                0x0000004c
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB                                   24
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB                                   28
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK                                  0x1f000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET                                   0x0000004c
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB                                      29
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB                                      31
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK                                     0xe0000000
+
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET                              0x00000050
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB                                 0
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB                                 11
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK                                0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET                                    0x00000050
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB                                       12
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB                                       14
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK                                      0x00007000
+
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET                                  0x00000050
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB                                     15
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB                                     16
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK                                    0x00018000
+
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET                              0x00000050
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB                                 17
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB                                 24
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK                                0x01fe0000
+
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET                                0x00000050
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB                                   25
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB                                   31
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK                                  0xfe000000
+
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET            0x00000054
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB               0
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB               31
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK              0xffffffff
+
+#endif
diff --git a/hw/peach/v1/pcu_ppdu_setup_init.h b/hw/peach/v1/pcu_ppdu_setup_init.h
new file mode 100644
index 000000000000..90d022543c27
--- /dev/null
+++ b/hw/peach/v1/pcu_ppdu_setup_init.h
@@ -0,0 +1,2282 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PCU_PPDU_SETUP_INIT_H_
+#define _PCU_PPDU_SETUP_INIT_H_
+
+#include "pdg_response_rate_setting.h"
+#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58
+
+struct pcu_ppdu_setup_init {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t medium_prot_type                                        :  3,
+                      response_type                                           :  5,
+                      response_info_part2_required                            :  1,
+                      response_to_response                                    :  3,
+                      mba_user_order                                          :  2,
+                      expected_mba_size                                       : 11,
+                      required_ul_mu_resp_user_count                          :  6,
+                      transmitted_bssid_check_en                              :  1;
+             uint32_t mprot_required_bw1                                      :  1,
+                      mprot_required_bw20                                     :  1,
+                      mprot_required_bw40                                     :  1,
+                      mprot_required_bw80                                     :  1,
+                      mprot_required_bw160                                    :  1,
+                      mprot_required_bw240                                    :  1,
+                      mprot_required_bw320                                    :  1,
+                      ppdu_allowed_bw1                                        :  1,
+                      ppdu_allowed_bw20                                       :  1,
+                      ppdu_allowed_bw40                                       :  1,
+                      ppdu_allowed_bw80                                       :  1,
+                      ppdu_allowed_bw160                                      :  1,
+                      ppdu_allowed_bw240                                      :  1,
+                      ppdu_allowed_bw320                                      :  1,
+                      set_fc_pwr_mgt                                          :  1,
+                      use_cts_duration_for_data_tx                            :  1,
+                      update_timestamp_64                                     :  1,
+                      update_timestamp_32_lower                               :  1,
+                      update_timestamp_32_upper                               :  1,
+                      reserved_1a                                             : 13;
+             uint32_t insert_timestamp_offset_0                               : 16,
+                      insert_timestamp_offset_1                               : 16;
+             uint32_t max_bw40_try_count                                      :  4,
+                      max_bw80_try_count                                      :  4,
+                      max_bw160_try_count                                     :  4,
+                      max_bw240_try_count                                     :  4,
+                      max_bw320_try_count                                     :  4,
+                      insert_wur_timestamp_offset                             :  6,
+                      update_wur_timestamp                                    :  1,
+                      wur_embedded_bssid_present                              :  1,
+                      insert_wur_fcs                                          :  1,
+                      reserved_3b                                             :  3;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw20;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw40;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw80;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw160;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw240;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw320;
+             uint32_t r2r_hw_response_tx_duration                             : 16,
+                      r2r_rx_duration_field                                   : 16;
+             uint32_t r2r_group_id                                            :  6,
+                      r2r_response_frame_type                                 :  4,
+                      r2r_sta_partial_aid                                     : 11,
+                      use_address_fields_for_protection                       :  1,
+                      r2r_set_required_response_time                          :  1,
+                      reserved_29a                                            :  3,
+                      r2r_bw20_active_channel                                 :  3,
+                      r2r_bw40_active_channel                                 :  3;
+             uint32_t r2r_bw80_active_channel                                 :  3,
+                      r2r_bw160_active_channel                                :  3,
+                      r2r_bw240_active_channel                                :  3,
+                      r2r_bw320_active_channel                                :  3,
+                      r2r_bw20                                                :  3,
+                      r2r_bw40                                                :  3,
+                      r2r_bw80                                                :  3,
+                      r2r_bw160                                               :  3,
+                      r2r_bw240                                               :  3,
+                      r2r_bw320                                               :  3,
+                      reserved_30a                                            :  2;
+             uint32_t mu_response_expected_bitmap_31_0                        : 32;
+             uint32_t mu_response_expected_bitmap_36_32                       :  5,
+                      mu_expected_response_cbf_count                          :  6,
+                      mu_expected_response_sta_count                          :  6,
+                      transmit_includes_multidestination                      :  1,
+                      insert_prev_tx_start_timing_info                        :  1,
+                      insert_current_tx_start_timing_info                     :  1,
+                      tx_start_transmit_time_byte_offset                      : 12;
+             uint32_t protection_frame_ad1_31_0                               : 32;
+             uint32_t protection_frame_ad1_47_32                              : 16,
+                      protection_frame_ad2_15_0                               : 16;
+             uint32_t protection_frame_ad2_47_16                              : 32;
+             uint32_t dynamic_medium_prot_threshold                           : 24,
+                      dynamic_medium_prot_type                                :  1,
+                      reserved_54a                                            :  7;
+             uint32_t protection_frame_ad3_31_0                               : 32;
+             uint32_t protection_frame_ad3_47_32                              : 16,
+                      protection_frame_ad4_15_0                               : 16;
+             uint32_t protection_frame_ad4_47_16                              : 32;
+#else
+             uint32_t transmitted_bssid_check_en                              :  1,
+                      required_ul_mu_resp_user_count                          :  6,
+                      expected_mba_size                                       : 11,
+                      mba_user_order                                          :  2,
+                      response_to_response                                    :  3,
+                      response_info_part2_required                            :  1,
+                      response_type                                           :  5,
+                      medium_prot_type                                        :  3;
+             uint32_t reserved_1a                                             : 13,
+                      update_timestamp_32_upper                               :  1,
+                      update_timestamp_32_lower                               :  1,
+                      update_timestamp_64                                     :  1,
+                      use_cts_duration_for_data_tx                            :  1,
+                      set_fc_pwr_mgt                                          :  1,
+                      ppdu_allowed_bw320                                      :  1,
+                      ppdu_allowed_bw240                                      :  1,
+                      ppdu_allowed_bw160                                      :  1,
+                      ppdu_allowed_bw80                                       :  1,
+                      ppdu_allowed_bw40                                       :  1,
+                      ppdu_allowed_bw20                                       :  1,
+                      ppdu_allowed_bw1                                        :  1,
+                      mprot_required_bw320                                    :  1,
+                      mprot_required_bw240                                    :  1,
+                      mprot_required_bw160                                    :  1,
+                      mprot_required_bw80                                     :  1,
+                      mprot_required_bw40                                     :  1,
+                      mprot_required_bw20                                     :  1,
+                      mprot_required_bw1                                      :  1;
+             uint32_t insert_timestamp_offset_1                               : 16,
+                      insert_timestamp_offset_0                               : 16;
+             uint32_t reserved_3b                                             :  3,
+                      insert_wur_fcs                                          :  1,
+                      wur_embedded_bssid_present                              :  1,
+                      update_wur_timestamp                                    :  1,
+                      insert_wur_timestamp_offset                             :  6,
+                      max_bw320_try_count                                     :  4,
+                      max_bw240_try_count                                     :  4,
+                      max_bw160_try_count                                     :  4,
+                      max_bw80_try_count                                      :  4,
+                      max_bw40_try_count                                      :  4;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw20;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw40;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw80;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw160;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw240;
+             struct   pdg_response_rate_setting                                 response_to_response_rate_info_bw320;
+             uint32_t r2r_rx_duration_field                                   : 16,
+                      r2r_hw_response_tx_duration                             : 16;
+             uint32_t r2r_bw40_active_channel                                 :  3,
+                      r2r_bw20_active_channel                                 :  3,
+                      reserved_29a                                            :  3,
+                      r2r_set_required_response_time                          :  1,
+                      use_address_fields_for_protection                       :  1,
+                      r2r_sta_partial_aid                                     : 11,
+                      r2r_response_frame_type                                 :  4,
+                      r2r_group_id                                            :  6;
+             uint32_t reserved_30a                                            :  2,
+                      r2r_bw320                                               :  3,
+                      r2r_bw240                                               :  3,
+                      r2r_bw160                                               :  3,
+                      r2r_bw80                                                :  3,
+                      r2r_bw40                                                :  3,
+                      r2r_bw20                                                :  3,
+                      r2r_bw320_active_channel                                :  3,
+                      r2r_bw240_active_channel                                :  3,
+                      r2r_bw160_active_channel                                :  3,
+                      r2r_bw80_active_channel                                 :  3;
+             uint32_t mu_response_expected_bitmap_31_0                        : 32;
+             uint32_t tx_start_transmit_time_byte_offset                      : 12,
+                      insert_current_tx_start_timing_info                     :  1,
+                      insert_prev_tx_start_timing_info                        :  1,
+                      transmit_includes_multidestination                      :  1,
+                      mu_expected_response_sta_count                          :  6,
+                      mu_expected_response_cbf_count                          :  6,
+                      mu_response_expected_bitmap_36_32                       :  5;
+             uint32_t protection_frame_ad1_31_0                               : 32;
+             uint32_t protection_frame_ad2_15_0                               : 16,
+                      protection_frame_ad1_47_32                              : 16;
+             uint32_t protection_frame_ad2_47_16                              : 32;
+             uint32_t reserved_54a                                            :  7,
+                      dynamic_medium_prot_type                                :  1,
+                      dynamic_medium_prot_threshold                           : 24;
+             uint32_t protection_frame_ad3_31_0                               : 32;
+             uint32_t protection_frame_ad4_15_0                               : 16,
+                      protection_frame_ad3_47_32                              : 16;
+             uint32_t protection_frame_ad4_47_16                              : 32;
+#endif
+};
+
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET                                 0x00000000
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB                                    0
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB                                    2
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK                                   0x00000007
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET                                    0x00000000
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB                                       3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB                                       7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK                                      0x000000f8
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET                     0x00000000
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB                        8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB                        8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK                       0x00000100
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET                             0x00000000
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB                                9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB                                11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK                               0x00000e00
+
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET                                   0x00000000
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB                                      12
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB                                      13
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK                                     0x00003000
+
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET                                0x00000000
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB                                   14
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB                                   24
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK                                  0x01ffc000
+
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET                   0x00000000
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB                      25
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB                      30
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK                     0x7e000000
+
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET                       0x00000000
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB                          31
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB                          31
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK                         0x80000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET                               0x00000004
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB                                  0
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB                                  0
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK                                 0x00000001
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET                              0x00000004
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB                                 1
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB                                 1
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK                                0x00000002
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET                              0x00000004
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB                                 2
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB                                 2
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK                                0x00000004
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET                              0x00000004
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB                                 3
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB                                 3
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK                                0x00000008
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET                             0x00000004
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB                                4
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB                                4
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK                               0x00000010
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET                             0x00000004
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB                                5
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB                                5
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK                               0x00000020
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET                             0x00000004
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB                                6
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB                                6
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK                               0x00000040
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET                                 0x00000004
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB                                    7
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB                                    7
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK                                   0x00000080
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET                                0x00000004
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB                                   8
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB                                   8
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK                                  0x00000100
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET                                0x00000004
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB                                   9
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB                                   9
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK                                  0x00000200
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET                                0x00000004
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB                                   10
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB                                   10
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK                                  0x00000400
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET                               0x00000004
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB                                  11
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB                                  11
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK                                 0x00000800
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET                               0x00000004
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB                                  12
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB                                  12
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK                                 0x00001000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET                               0x00000004
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB                                  13
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB                                  13
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK                                 0x00002000
+
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET                                   0x00000004
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB                                      14
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB                                      14
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK                                     0x00004000
+
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET                     0x00000004
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB                        15
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB                        15
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK                       0x00008000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET                              0x00000004
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB                                 16
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB                                 16
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK                                0x00010000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET                        0x00000004
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB                           17
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB                           17
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK                          0x00020000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET                        0x00000004
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB                           18
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB                           18
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK                          0x00040000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET                                      0x00000004
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB                                         19
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB                                         31
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK                                        0xfff80000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET                        0x00000008
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB                           0
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB                           15
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK                          0x0000ffff
+
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET                        0x00000008
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB                           16
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB                           31
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK                          0xffff0000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET                               0x0000000c
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB                                  0
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB                                  3
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK                                 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET                               0x0000000c
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB                                  4
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB                                  7
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK                                 0x000000f0
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET                              0x0000000c
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB                                 8
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB                                 11
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK                                0x00000f00
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET                              0x0000000c
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB                                 12
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB                                 15
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK                                0x0000f000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET                              0x0000000c
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB                                 16
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB                                 19
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK                                0x000f0000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET                      0x0000000c
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB                         20
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB                         25
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK                        0x03f00000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET                             0x0000000c
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB                                26
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB                                26
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK                               0x04000000
+
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET                       0x0000000c
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB                          27
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB                          27
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK                         0x08000000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET                                   0x0000000c
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB                                      28
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB                                      28
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK                                     0x10000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET                                      0x0000000c
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB                                         29
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB                                         31
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK                                        0xe0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET  0x00000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK    0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET     0x00000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB        25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB        28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK       0x1e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET    0x00000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK      0x20000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET         0x00000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK           0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET         0x00000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK           0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET   0x00000014
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB      0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK     0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x00000014
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB  8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB  15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET      0x00000014
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB         16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB         18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK        0x00070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x00000014
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET       0x00000014
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB          27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB          29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK         0x38000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x00000014
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x00000014
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x00000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB    3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK   0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET          0x00000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB             4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB             6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK            0x00000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET   0x00000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK     0x00000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET       0x00000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB          8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB          15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK         0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET   0x00000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB      16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB      23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK     0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x00000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK  0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET  0x0000001c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK    0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET          0x0000001c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB             8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB             9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK            0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET     0x0000001c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB        10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB        13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK       0x00003c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_OFFSET  0x0000001c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_LSB     14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MSB     15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MASK    0x0000c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET     0x0000001c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB        16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB        23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK       0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000001c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB    24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB    31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK   0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET  0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK    0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET  0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK    0x00002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x00008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB  18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB  20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x00200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x04000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET  0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB     27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB     31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK    0xf8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET  0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB     10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB     10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK    0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB   11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB   13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK  0x00003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET  0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB     20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB     25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK    0x03f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x00000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET  0x0000002c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK    0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000002c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET     0x0000002c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB        25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB        28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK       0x1e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET    0x0000002c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK      0x20000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET         0x0000002c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK           0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET         0x0000002c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK           0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET   0x00000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB      0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK     0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x00000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB  8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB  15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET      0x00000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB         16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB         18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK        0x00070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x00000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET       0x00000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB          27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB          29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK         0x38000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x00000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x00000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x00000034
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB    3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK   0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET          0x00000034
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB             4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB             6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK            0x00000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET   0x00000034
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK     0x00000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET       0x00000034
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB          8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB          15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK         0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET   0x00000034
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB      16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB      23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK     0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x00000034
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK  0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET  0x00000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK    0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET          0x00000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB             8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB             9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK            0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET     0x00000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB        10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB        13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK       0x00003c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_OFFSET  0x00000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_LSB     14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MSB     15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MASK    0x0000c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET     0x00000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB        16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB        23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK       0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x00000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB    24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB    31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK   0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET  0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK    0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET  0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK    0x00002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x00008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB  18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB  20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x00200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x04000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET  0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB     27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB     31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK    0xf8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET  0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB     10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB     10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK    0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB   11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB   13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK  0x00003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x0007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET  0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB     20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB     25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK    0x03f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000044
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000044
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000044
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000044
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000044
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x00000044
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000044
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET  0x00000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK    0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET     0x00000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB        25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB        28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK       0x1e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET    0x00000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB       29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK      0x20000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET         0x00000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB            30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK           0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET         0x00000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB            31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK           0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET   0x0000004c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB      0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK     0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000004c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB  8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB  15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET      0x0000004c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB         16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB         18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK        0x00070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000004c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET       0x0000004c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB          27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB          29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK         0x38000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000004c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000004c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x00000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB    3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK   0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET          0x00000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB             4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB             6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK            0x00000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET   0x00000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB      7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK     0x00000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET       0x00000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB          8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB          15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK         0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET   0x00000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB      16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB      23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK     0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x00000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK  0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET  0x00000054
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK    0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET          0x00000054
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB             8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB             9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK            0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET     0x00000054
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB        10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB        13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK       0x00003c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_OFFSET  0x00000054
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_LSB     14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MSB     15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MASK    0x0000c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET     0x00000054
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB        16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB        23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK       0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x00000054
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB    24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB    31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK   0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET  0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK    0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET  0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB     13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK    0x00002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x00008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB  18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB  20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x00200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x04000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET  0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB     27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB     31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK    0xf8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET  0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB     10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB     10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK    0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB   11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB   13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK  0x00003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET  0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB     20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB     25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK    0x03f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x00000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x00000064
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK   0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000064
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET    0x00000064
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB       25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB       28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK      0x1e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET   0x00000064
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB      29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB      29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK     0x20000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET        0x00000064
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB           30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB           30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK          0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET        0x00000064
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB           31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB           31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK          0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET  0x00000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK    0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x00000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET     0x00000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB        16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB        18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK       0x00070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x00000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET      0x00000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB         27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB         29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK        0x38000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x00000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x00000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000006c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB   0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB   3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK  0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET         0x0000006c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB            4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB            6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK           0x00000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET  0x0000006c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK    0x00000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET      0x0000006c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB         8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB         15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK        0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET  0x0000006c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB     16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB     23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK    0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000006c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB  24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB  31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x00000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB    7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK   0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET         0x00000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB            8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB            9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK           0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET    0x00000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB       10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB       13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK      0x00003c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_OFFSET 0x00000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_LSB    14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MSB    15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MASK   0x0000c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET    0x00000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB       16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB       23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK      0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x00000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK  0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK   0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB    13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB    13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK   0x00002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x00008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x00200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x04000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB    27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB    31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK   0xf8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK   0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB  11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB  13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x00003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x0007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB    20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB    25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK   0x03f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000007c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000007c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000007c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000007c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000007c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000007c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000007c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x00000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK   0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET    0x00000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB       25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB       28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK      0x1e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET   0x00000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB      29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB      29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK     0x20000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET        0x00000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB           30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB           30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK          0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET        0x00000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB           31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB           31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK          0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET  0x00000084
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK    0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x00000084
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET     0x00000084
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB        16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB        18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK       0x00070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x00000084
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET      0x00000084
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB         27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB         29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK        0x38000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x00000084
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x00000084
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x00000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB   0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB   3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK  0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET         0x00000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB            4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB            6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK           0x00000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET  0x00000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK    0x00000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET      0x00000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB         8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB         15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK        0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET  0x00000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB     16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB     23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK    0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x00000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB  24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB  31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000008c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB    7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK   0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET         0x0000008c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB            8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB            9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK           0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET    0x0000008c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB       10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB       13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK      0x00003c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_OFFSET 0x0000008c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_LSB    14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MSB    15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MASK   0x0000c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET    0x0000008c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB       16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB       23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK      0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000008c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK  0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK   0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB    13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB    13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK   0x00002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x00008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x00200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x04000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB    27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB    31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK   0xf8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK   0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB  11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB  13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x00003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB    20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB    25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK   0x03f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x00000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000009c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK   0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000009c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET    0x0000009c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB       25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB       28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK      0x1e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET   0x0000009c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB      29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB      29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK     0x20000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET        0x0000009c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB           30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB           30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK          0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET        0x0000009c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB           31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB           31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK          0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET  0x000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB     0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK    0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET     0x000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB        16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB        18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK       0x00070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET      0x000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB         27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB         29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK        0x38000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x000000a4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB   0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB   3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK  0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET         0x000000a4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB            4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB            6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK           0x00000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET  0x000000a4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB     7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK    0x00000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET      0x000000a4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB         8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB         15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK        0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET  0x000000a4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB     16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB     23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK    0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x000000a4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB  24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB  31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB    7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK   0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET         0x000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB            8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB            9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK           0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET    0x000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB       10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB       13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK      0x00003c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_OFFSET 0x000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_LSB    14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MSB    15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MASK   0x0000c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET    0x000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB       16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB       23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK      0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB   24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB   31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK  0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB    0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK   0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB    13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB    13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK   0x00002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x00008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x00200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x04000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB    27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB    31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK   0xf8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB    10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK   0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB  11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB  13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x00003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x0007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB    20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB    25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK   0x03f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x000000b4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x000000b4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x000000b4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x000000b4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x000000b4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x000000b4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x000000b4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET                      0x000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB                         0
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB                         15
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK                        0x0000ffff
+
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET                            0x000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB                               16
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB                               31
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK                              0xffff0000
+
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET                                     0x000000bc
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB                                        0
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB                                        5
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK                                       0x0000003f
+
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET                          0x000000bc
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB                             6
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB                             9
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK                            0x000003c0
+
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET                              0x000000bc
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB                                 10
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB                                 20
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK                                0x001ffc00
+
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET                0x000000bc
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB                   21
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB                   21
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK                  0x00200000
+
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET                   0x000000bc
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB                      22
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB                      22
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK                     0x00400000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET                                     0x000000bc
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB                                        23
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB                                        25
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK                                       0x03800000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET                          0x000000bc
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB                             26
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB                             28
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK                            0x1c000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET                          0x000000bc
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB                             29
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB                             31
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK                            0xe0000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET                          0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB                             0
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB                             2
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK                            0x00000007
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET                         0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB                            3
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB                            5
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK                           0x00000038
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET                         0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB                            6
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB                            8
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK                           0x000001c0
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET                         0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB                            9
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB                            11
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK                           0x00000e00
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET                                         0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB                                            12
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB                                            14
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK                                           0x00007000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET                                         0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB                                            15
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB                                            17
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK                                           0x00038000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET                                         0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB                                            18
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB                                            20
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK                                           0x001c0000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET                                        0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB                                           21
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB                                           23
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK                                          0x00e00000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET                                        0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB                                           24
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB                                           26
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK                                          0x07000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET                                        0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB                                           27
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB                                           29
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK                                          0x38000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_30A_OFFSET                                     0x000000c0
+#define PCU_PPDU_SETUP_INIT_RESERVED_30A_LSB                                        30
+#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MSB                                        31
+#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MASK                                       0xc0000000
+
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET                 0x000000c4
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB                    0
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB                    31
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK                   0xffffffff
+
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET                0x000000c8
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB                   0
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB                   4
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK                  0x0000001f
+
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET                   0x000000c8
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB                      5
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB                      10
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK                     0x000007e0
+
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET                   0x000000c8
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB                      11
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB                      16
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK                     0x0001f800
+
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET               0x000000c8
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB                  17
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB                  17
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK                 0x00020000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET                 0x000000c8
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB                    18
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB                    18
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK                   0x00040000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET              0x000000c8
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB                 19
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB                 19
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK                0x00080000
+
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET               0x000000c8
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB                  20
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB                  31
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK                 0xfff00000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET                        0x000000cc
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB                           0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB                           31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK                          0xffffffff
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET                       0x000000d0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB                          0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB                          15
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK                         0x0000ffff
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET                        0x000000d0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB                           16
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB                           31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK                          0xffff0000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET                       0x000000d4
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB                          0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB                          31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK                         0xffffffff
+
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET                    0x000000d8
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB                       0
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB                       23
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK                      0x00ffffff
+
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET                         0x000000d8
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB                            24
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB                            24
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK                           0x01000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET                                     0x000000d8
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB                                        25
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB                                        31
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK                                       0xfe000000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET                        0x000000dc
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB                           0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB                           31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK                          0xffffffff
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET                       0x000000e0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB                          0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB                          15
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK                         0x0000ffff
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET                        0x000000e0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB                           16
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB                           31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK                          0xffff0000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET                       0x000000e4
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB                          0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB                          31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK                         0xffffffff
+
+#endif
diff --git a/hw/peach/v1/pdg_response.h b/hw/peach/v1/pdg_response.h
new file mode 100644
index 000000000000..7060494a33e7
--- /dev/null
+++ b/hw/peach/v1/pdg_response.h
@@ -0,0 +1,473 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PDG_RESPONSE_H_
+#define _PDG_RESPONSE_H_
+
+#include "pdg_response_rate_setting.h"
+#define NUM_OF_DWORDS_PDG_RESPONSE 12
+
+struct pdg_response {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   pdg_response_rate_setting                                 hw_response_rate_info;
+             uint32_t hw_response_tx_duration                                 : 16,
+                      rx_duration_field                                       : 16;
+             uint32_t punctured_response_transmission                         :  1,
+                      cca_subband_channel_bonding_mask                        : 16,
+                      scrambler_seed_override                                 :  2,
+                      response_density_valid                                  :  1,
+                      response_density                                        :  5,
+                      more_data                                               :  1,
+                      duration_indication                                     :  1,
+                      relayed_frame                                           :  1,
+                      address_indicator                                       :  1,
+                      bandwidth                                               :  3;
+             uint32_t ack_id                                                  : 16,
+                      block_ack_bitmap                                        : 16;
+             uint32_t response_frame_type                                     :  4,
+                      ack_id_ext                                              : 10,
+                      ftm_en                                                  :  1,
+                      group_id                                                :  6,
+                      sta_partial_aid                                         : 11;
+             uint32_t ndp_ba_start_seq_ctrl                                   : 12,
+                      active_channel                                          :  3,
+                      txop_duration_all_ones                                  :  1,
+                      frame_length                                            : 16;
+#else
+             struct   pdg_response_rate_setting                                 hw_response_rate_info;
+             uint32_t rx_duration_field                                       : 16,
+                      hw_response_tx_duration                                 : 16;
+             uint32_t bandwidth                                               :  3,
+                      address_indicator                                       :  1,
+                      relayed_frame                                           :  1,
+                      duration_indication                                     :  1,
+                      more_data                                               :  1,
+                      response_density                                        :  5,
+                      response_density_valid                                  :  1,
+                      scrambler_seed_override                                 :  2,
+                      cca_subband_channel_bonding_mask                        : 16,
+                      punctured_response_transmission                         :  1;
+             uint32_t block_ack_bitmap                                        : 16,
+                      ack_id                                                  : 16;
+             uint32_t sta_partial_aid                                         : 11,
+                      group_id                                                :  6,
+                      ftm_en                                                  :  1,
+                      ack_id_ext                                              : 10,
+                      response_frame_type                                     :  4;
+             uint32_t frame_length                                            : 16,
+                      txop_duration_all_ones                                  :  1,
+                      active_channel                                          :  3,
+                      ndp_ba_start_seq_ctrl                                   : 12;
+#endif
+};
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET                       0x00000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK                         0x00000001
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET            0x00000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB               1
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB               24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK              0x01fffffe
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET                          0x00000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB                             25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB                             28
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK                            0x1e000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET                         0x00000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB                            29
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB                            29
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK                           0x20000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET                              0x00000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB                                 30
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB                                 30
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK                                0x40000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET                              0x00000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB                                 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB                                 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK                                0x80000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET                        0x00000004
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB                           0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB                           7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK                          0x000000ff
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET                    0x00000004
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB                       8
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB                       15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK                      0x0000ff00
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET                           0x00000004
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB                              16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB                              18
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK                             0x00070000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET                 0x00000004
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB                    19
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB                    26
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK                   0x07f80000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET                            0x00000004
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB                               27
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB                               29
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK                              0x38000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET                 0x00000004
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB                    30
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB                    30
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK                   0x40000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET                0x00000004
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB                   31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB                   31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK                  0x80000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET                      0x00000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB                         0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB                         3
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK                        0x0000000f
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET                               0x00000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB                                  4
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB                                  6
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK                                 0x00000070
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET                        0x00000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB                           7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB                           7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK                          0x00000080
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET                            0x00000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB                               8
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB                               15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK                              0x0000ff00
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET                        0x00000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB                           16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB                           23
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK                          0x00ff0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET                     0x00000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB                        24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB                        31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK                       0xff000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET                       0x0000000c
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB                          7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK                         0x000000ff
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET                               0x0000000c
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB                                  8
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB                                  9
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK                                 0x00000300
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET                          0x0000000c
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB                             10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB                             13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK                            0x00003c00
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET                       0x0000000c
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB                          14
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB                          15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK                         0x0000c000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET                          0x0000000c
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB                             16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB                             23
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK                            0x00ff0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET                      0x0000000c
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB                         24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB                         31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK                        0xff000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET                       0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB                          0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK                         0x00000001
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET              0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB                 1
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB                 6
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK                0x0000007e
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET             0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB                7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB                10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK               0x00000780
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET               0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB                  11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB                  12
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK                 0x00001800
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET                       0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB                          13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB                          13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK                         0x00002000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET        0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB           14
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB           14
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK          0x00004000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET               0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB                  15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB                  15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK                 0x00008000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET      0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB         16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB         17
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK        0x00030000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET                    0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB                       18
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB                       20
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK                      0x001c0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET                0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB                   21
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB                   21
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK                  0x00200000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET               0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB                  22
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB                  23
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK                 0x00c00000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET              0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB                 24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB                 24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK                0x01000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET           0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB              25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB              25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK             0x02000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET                0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB                   26
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB                   26
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK                  0x04000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET                       0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB                          27
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB                          31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK                         0xf8000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET        0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB           0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB           3
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK          0x0000000f
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET               0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB                  4
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB                  7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK                 0x000000f0
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET                0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB                   8
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB                   9
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK                  0x00000300
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET                       0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB                          10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB                          10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK                         0x00000400
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET                     0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB                        11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB                        13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK                       0x00003800
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET                   0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB                      14
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB                      18
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK                     0x0007c000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET     0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB        19
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB        19
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK       0x00080000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET                       0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB                          20
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB                          25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK                         0x03f00000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET   0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB      26
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB      31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK     0xfc000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB    13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB    15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK   0x0000e000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET            0x00000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB               16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB               27
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK              0x0fff0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET        0x00000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB           28
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB           31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK          0xf0000000
+
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET                                 0x0000001c
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB                                    0
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB                                    15
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK                                   0x0000ffff
+
+#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET                                       0x0000001c
+#define PDG_RESPONSE_RX_DURATION_FIELD_LSB                                          16
+#define PDG_RESPONSE_RX_DURATION_FIELD_MSB                                          31
+#define PDG_RESPONSE_RX_DURATION_FIELD_MASK                                         0xffff0000
+
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET                         0x00000020
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB                            0
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB                            0
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK                           0x00000001
+
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET                        0x00000020
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB                           1
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB                           16
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK                          0x0001fffe
+
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET                                 0x00000020
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB                                    17
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB                                    18
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK                                   0x00060000
+
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET                                  0x00000020
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB                                     19
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB                                     19
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK                                    0x00080000
+
+#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET                                        0x00000020
+#define PDG_RESPONSE_RESPONSE_DENSITY_LSB                                           20
+#define PDG_RESPONSE_RESPONSE_DENSITY_MSB                                           24
+#define PDG_RESPONSE_RESPONSE_DENSITY_MASK                                          0x01f00000
+
+#define PDG_RESPONSE_MORE_DATA_OFFSET                                               0x00000020
+#define PDG_RESPONSE_MORE_DATA_LSB                                                  25
+#define PDG_RESPONSE_MORE_DATA_MSB                                                  25
+#define PDG_RESPONSE_MORE_DATA_MASK                                                 0x02000000
+
+#define PDG_RESPONSE_DURATION_INDICATION_OFFSET                                     0x00000020
+#define PDG_RESPONSE_DURATION_INDICATION_LSB                                        26
+#define PDG_RESPONSE_DURATION_INDICATION_MSB                                        26
+#define PDG_RESPONSE_DURATION_INDICATION_MASK                                       0x04000000
+
+#define PDG_RESPONSE_RELAYED_FRAME_OFFSET                                           0x00000020
+#define PDG_RESPONSE_RELAYED_FRAME_LSB                                              27
+#define PDG_RESPONSE_RELAYED_FRAME_MSB                                              27
+#define PDG_RESPONSE_RELAYED_FRAME_MASK                                             0x08000000
+
+#define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET                                       0x00000020
+#define PDG_RESPONSE_ADDRESS_INDICATOR_LSB                                          28
+#define PDG_RESPONSE_ADDRESS_INDICATOR_MSB                                          28
+#define PDG_RESPONSE_ADDRESS_INDICATOR_MASK                                         0x10000000
+
+#define PDG_RESPONSE_BANDWIDTH_OFFSET                                               0x00000020
+#define PDG_RESPONSE_BANDWIDTH_LSB                                                  29
+#define PDG_RESPONSE_BANDWIDTH_MSB                                                  31
+#define PDG_RESPONSE_BANDWIDTH_MASK                                                 0xe0000000
+
+#define PDG_RESPONSE_ACK_ID_OFFSET                                                  0x00000024
+#define PDG_RESPONSE_ACK_ID_LSB                                                     0
+#define PDG_RESPONSE_ACK_ID_MSB                                                     15
+#define PDG_RESPONSE_ACK_ID_MASK                                                    0x0000ffff
+
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET                                        0x00000024
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB                                           16
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB                                           31
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK                                          0xffff0000
+
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET                                     0x00000028
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB                                        0
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB                                        3
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK                                       0x0000000f
+
+#define PDG_RESPONSE_ACK_ID_EXT_OFFSET                                              0x00000028
+#define PDG_RESPONSE_ACK_ID_EXT_LSB                                                 4
+#define PDG_RESPONSE_ACK_ID_EXT_MSB                                                 13
+#define PDG_RESPONSE_ACK_ID_EXT_MASK                                                0x00003ff0
+
+#define PDG_RESPONSE_FTM_EN_OFFSET                                                  0x00000028
+#define PDG_RESPONSE_FTM_EN_LSB                                                     14
+#define PDG_RESPONSE_FTM_EN_MSB                                                     14
+#define PDG_RESPONSE_FTM_EN_MASK                                                    0x00004000
+
+#define PDG_RESPONSE_GROUP_ID_OFFSET                                                0x00000028
+#define PDG_RESPONSE_GROUP_ID_LSB                                                   15
+#define PDG_RESPONSE_GROUP_ID_MSB                                                   20
+#define PDG_RESPONSE_GROUP_ID_MASK                                                  0x001f8000
+
+#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET                                         0x00000028
+#define PDG_RESPONSE_STA_PARTIAL_AID_LSB                                            21
+#define PDG_RESPONSE_STA_PARTIAL_AID_MSB                                            31
+#define PDG_RESPONSE_STA_PARTIAL_AID_MASK                                           0xffe00000
+
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET                                   0x0000002c
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB                                      0
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB                                      11
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK                                     0x00000fff
+
+#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET                                          0x0000002c
+#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB                                             12
+#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB                                             14
+#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK                                            0x00007000
+
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET                                  0x0000002c
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB                                     15
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB                                     15
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK                                    0x00008000
+
+#define PDG_RESPONSE_FRAME_LENGTH_OFFSET                                            0x0000002c
+#define PDG_RESPONSE_FRAME_LENGTH_LSB                                               16
+#define PDG_RESPONSE_FRAME_LENGTH_MSB                                               31
+#define PDG_RESPONSE_FRAME_LENGTH_MASK                                              0xffff0000
+
+#endif
diff --git a/hw/peach/v1/pdg_response_rate_setting.h b/hw/peach/v1/pdg_response_rate_setting.h
new file mode 100644
index 000000000000..7a187717bf40
--- /dev/null
+++ b/hw/peach/v1/pdg_response_rate_setting.h
@@ -0,0 +1,414 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PDG_RESPONSE_RATE_SETTING_H_
+#define _PDG_RESPONSE_RATE_SETTING_H_
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7
+
+struct pdg_response_rate_setting {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             :  1,
+                      tx_antenna_sector_ctrl                                  : 24,
+                      pkt_type                                                :  4,
+                      smoothing                                               :  1,
+                      ldpc                                                    :  1,
+                      stbc                                                    :  1;
+             uint32_t alt_tx_pwr                                              :  8,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_nss                                                 :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_bw                                                  :  3,
+                      stf_ltf_3db_boost                                       :  1,
+                      force_extra_symbol                                      :  1;
+             uint32_t alt_rate_mcs                                            :  4,
+                      nss                                                     :  3,
+                      dpd_enable                                              :  1,
+                      tx_pwr                                                  :  8,
+                      min_tx_pwr                                              :  8,
+                      tx_chain_mask                                           :  8;
+             uint32_t reserved_3a                                             :  8,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  4,
+                      reserved_3b                                             :  2,
+                      tx_pwr_1                                                :  8,
+                      alt_tx_pwr_1                                            :  8;
+             uint32_t aggregation                                             :  1,
+                      dot11ax_bss_color_id                                    :  6,
+                      dot11ax_spatial_reuse                                   :  4,
+                      dot11ax_cp_ltf_size                                     :  2,
+                      dot11ax_dcm                                             :  1,
+                      dot11ax_doppler_indication                              :  1,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_min_packet_extension                            :  2,
+                      dot11ax_pe_nss                                          :  3,
+                      dot11ax_pe_content                                      :  1,
+                      dot11ax_pe_ltf_size                                     :  2,
+                      dot11ax_chain_csd_en                                    :  1,
+                      dot11ax_pe_chain_csd_en                                 :  1,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      reserved_4a                                             :  5;
+             uint32_t dot11ax_ext_ru_start_index                              :  4,
+                      dot11ax_ext_ru_size                                     :  4,
+                      eht_duplicate_mode                                      :  2,
+                      he_sigb_dcm                                             :  1,
+                      he_sigb_0_mcs                                           :  3,
+                      num_he_sigb_sym                                         :  5,
+                      required_response_time_source                           :  1,
+                      reserved_5a                                             :  6,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint16_t required_response_time                                  : 12,
+                      dot11be_params_placeholder                              :  4;
+#else
+             uint32_t stbc                                                    :  1,
+                      ldpc                                                    :  1,
+                      smoothing                                               :  1,
+                      pkt_type                                                :  4,
+                      tx_antenna_sector_ctrl                                  : 24,
+                      reserved_0a                                             :  1;
+             uint32_t force_extra_symbol                                      :  1,
+                      stf_ltf_3db_boost                                       :  1,
+                      alt_bw                                                  :  3,
+                      alt_tx_chain_mask                                       :  8,
+                      alt_nss                                                 :  3,
+                      alt_min_tx_pwr                                          :  8,
+                      alt_tx_pwr                                              :  8;
+             uint32_t tx_chain_mask                                           :  8,
+                      min_tx_pwr                                              :  8,
+                      tx_pwr                                                  :  8,
+                      dpd_enable                                              :  1,
+                      nss                                                     :  3,
+                      alt_rate_mcs                                            :  4;
+             uint32_t alt_tx_pwr_1                                            :  8,
+                      tx_pwr_1                                                :  8,
+                      reserved_3b                                             :  2,
+                      rate_mcs                                                :  4,
+                      sgi                                                     :  2,
+                      reserved_3a                                             :  8;
+             uint32_t reserved_4a                                             :  5,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      dot11ax_pe_chain_csd_en                                 :  1,
+                      dot11ax_chain_csd_en                                    :  1,
+                      dot11ax_pe_ltf_size                                     :  2,
+                      dot11ax_pe_content                                      :  1,
+                      dot11ax_pe_nss                                          :  3,
+                      dot11ax_min_packet_extension                            :  2,
+                      dot11ax_su_extended                                     :  1,
+                      dot11ax_doppler_indication                              :  1,
+                      dot11ax_dcm                                             :  1,
+                      dot11ax_cp_ltf_size                                     :  2,
+                      dot11ax_spatial_reuse                                   :  4,
+                      dot11ax_bss_color_id                                    :  6,
+                      aggregation                                             :  1;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_5a                                             :  6,
+                      required_response_time_source                           :  1,
+                      num_he_sigb_sym                                         :  5,
+                      he_sigb_0_mcs                                           :  3,
+                      he_sigb_dcm                                             :  1,
+                      eht_duplicate_mode                                      :  2,
+                      dot11ax_ext_ru_size                                     :  4,
+                      dot11ax_ext_ru_start_index                              :  4;
+             uint32_t dot11be_params_placeholder                              :  4,
+                      required_response_time                                  : 12;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+#endif
+};
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET                                0x00000000
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK                                  0x00000001
+
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET                     0x00000000
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB                        1
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB                        24
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK                       0x01fffffe
+
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET                                   0x00000000
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB                                      25
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB                                      28
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK                                     0x1e000000
+
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET                                  0x00000000
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB                                     29
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB                                     29
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK                                    0x20000000
+
+#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET                                       0x00000000
+#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB                                          30
+#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB                                          30
+#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK                                         0x40000000
+
+#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET                                       0x00000000
+#define PDG_RESPONSE_RATE_SETTING_STBC_LSB                                          31
+#define PDG_RESPONSE_RATE_SETTING_STBC_MSB                                          31
+#define PDG_RESPONSE_RATE_SETTING_STBC_MASK                                         0x80000000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET                                 0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB                                    0
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB                                    7
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK                                   0x000000ff
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET                             0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB                                8
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB                                15
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK                               0x0000ff00
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET                                    0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB                                       16
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB                                       18
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK                                      0x00070000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET                          0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB                             19
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB                             26
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK                            0x07f80000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET                                     0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB                                        27
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB                                        29
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK                                       0x38000000
+
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET                          0x00000004
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB                             30
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB                             30
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK                            0x40000000
+
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET                         0x00000004
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB                            31
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB                            31
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK                           0x80000000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET                               0x00000008
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB                                  0
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB                                  3
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK                                 0x0000000f
+
+#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET                                        0x00000008
+#define PDG_RESPONSE_RATE_SETTING_NSS_LSB                                           4
+#define PDG_RESPONSE_RATE_SETTING_NSS_MSB                                           6
+#define PDG_RESPONSE_RATE_SETTING_NSS_MASK                                          0x00000070
+
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET                                 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB                                    7
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB                                    7
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK                                   0x00000080
+
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET                                     0x00000008
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB                                        8
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB                                        15
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK                                       0x0000ff00
+
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET                                 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB                                    16
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB                                    23
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK                                   0x00ff0000
+
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET                              0x00000008
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB                                 24
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB                                 31
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK                                0xff000000
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET                                0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB                                   7
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK                                  0x000000ff
+
+#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET                                        0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_SGI_LSB                                           8
+#define PDG_RESPONSE_RATE_SETTING_SGI_MSB                                           9
+#define PDG_RESPONSE_RATE_SETTING_SGI_MASK                                          0x00000300
+
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET                                   0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB                                      10
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB                                      13
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK                                     0x00003c00
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET                                0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB                                   14
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB                                   15
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK                                  0x0000c000
+
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET                                   0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB                                      16
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB                                      23
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK                                     0x00ff0000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET                               0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB                                  24
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB                                  31
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK                                 0xff000000
+
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET                                0x00000010
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB                                   0
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK                                  0x00000001
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET                       0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB                          1
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB                          6
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK                         0x0000007e
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET                      0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB                         7
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB                         10
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK                        0x00000780
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET                        0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB                           11
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB                           12
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK                          0x00001800
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET                                0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB                                   13
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB                                   13
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK                                  0x00002000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET                 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB                    14
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB                    14
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK                   0x00004000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET                        0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB                           15
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB                           15
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK                          0x00008000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET               0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB                  16
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB                  17
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK                 0x00030000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET                             0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB                                18
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB                                20
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK                               0x001c0000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET                         0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB                            21
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB                            21
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK                           0x00200000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET                        0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB                           22
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB                           23
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK                          0x00c00000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET                       0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB                          24
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB                          24
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK                         0x01000000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET                    0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB                       25
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB                       25
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK                      0x02000000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET                         0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB                            26
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB                            26
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK                           0x04000000
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET                                0x00000010
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB                                   27
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB                                   31
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK                                  0xf8000000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET                 0x00000014
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB                    0
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB                    3
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK                   0x0000000f
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET                        0x00000014
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB                           4
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB                           7
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK                          0x000000f0
+
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET                         0x00000014
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB                            8
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB                            9
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK                           0x00000300
+
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET                                0x00000014
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB                                   10
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB                                   10
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK                                  0x00000400
+
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET                              0x00000014
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB                                 11
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB                                 13
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK                                0x00003800
+
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET                            0x00000014
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB                               14
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB                               18
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK                              0x0007c000
+
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET              0x00000014
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB                 19
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB                 19
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK                0x00080000
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET                                0x00000014
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB                                   20
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB                                   25
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK                                  0x03f00000
+
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET            0x00000014
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB               26
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB               31
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK              0xfc000000
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET      0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB         0
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB         9
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK        0x000003ff
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET   0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB      10
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB      10
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK     0x00000400
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB   11
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB   11
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK  0x00000800
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB   12
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB   12
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK  0x00001000
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET          0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB             13
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB             15
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK            0x0000e000
+
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET                     0x00000018
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB                        16
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB                        27
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK                       0x0fff0000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET                 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB                    28
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB                    31
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK                   0xf0000000
+
+#endif
diff --git a/hw/peach/v1/pdg_tx_req.h b/hw/peach/v1/pdg_tx_req.h
new file mode 100644
index 000000000000..82333c6a21c5
--- /dev/null
+++ b/hw/peach/v1/pdg_tx_req.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PDG_TX_REQ_H_
+#define _PDG_TX_REQ_H_
+
+#define NUM_OF_DWORDS_PDG_TX_REQ 2
+
+struct pdg_tx_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_reason                                               :  2,
+                      use_puncture_pattern                                    :  2,
+                      req_bw                                                  :  3,
+                      puncture_pattern_number                                 :  6,
+                      reserved_0b                                             :  1,
+                      req_paprd                                               :  1,
+                      duration_field_boundary_valid                           :  1,
+                      duration_field_boundary                                 : 16;
+             uint32_t puncture_subband_mask                                   : 16,
+                      reserved_0c                                             : 16;
+#else
+             uint32_t duration_field_boundary                                 : 16,
+                      duration_field_boundary_valid                           :  1,
+                      req_paprd                                               :  1,
+                      reserved_0b                                             :  1,
+                      puncture_pattern_number                                 :  6,
+                      req_bw                                                  :  3,
+                      use_puncture_pattern                                    :  2,
+                      tx_reason                                               :  2;
+             uint32_t reserved_0c                                             : 16,
+                      puncture_subband_mask                                   : 16;
+#endif
+};
+
+#define PDG_TX_REQ_TX_REASON_OFFSET                                                 0x00000000
+#define PDG_TX_REQ_TX_REASON_LSB                                                    0
+#define PDG_TX_REQ_TX_REASON_MSB                                                    1
+#define PDG_TX_REQ_TX_REASON_MASK                                                   0x00000003
+
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET                                      0x00000000
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB                                         2
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB                                         3
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK                                        0x0000000c
+
+#define PDG_TX_REQ_REQ_BW_OFFSET                                                    0x00000000
+#define PDG_TX_REQ_REQ_BW_LSB                                                       4
+#define PDG_TX_REQ_REQ_BW_MSB                                                       6
+#define PDG_TX_REQ_REQ_BW_MASK                                                      0x00000070
+
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET                                   0x00000000
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB                                      7
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB                                      12
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK                                     0x00001f80
+
+#define PDG_TX_REQ_RESERVED_0B_OFFSET                                               0x00000000
+#define PDG_TX_REQ_RESERVED_0B_LSB                                                  13
+#define PDG_TX_REQ_RESERVED_0B_MSB                                                  13
+#define PDG_TX_REQ_RESERVED_0B_MASK                                                 0x00002000
+
+#define PDG_TX_REQ_REQ_PAPRD_OFFSET                                                 0x00000000
+#define PDG_TX_REQ_REQ_PAPRD_LSB                                                    14
+#define PDG_TX_REQ_REQ_PAPRD_MSB                                                    14
+#define PDG_TX_REQ_REQ_PAPRD_MASK                                                   0x00004000
+
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET                             0x00000000
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB                                15
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB                                15
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK                               0x00008000
+
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET                                   0x00000000
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB                                      16
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB                                      31
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK                                     0xffff0000
+
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET                                     0x00000004
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB                                        0
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB                                        15
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK                                       0x0000ffff
+
+#define PDG_TX_REQ_RESERVED_0C_OFFSET                                               0x00000004
+#define PDG_TX_REQ_RESERVED_0C_LSB                                                  16
+#define PDG_TX_REQ_RESERVED_0C_MSB                                                  31
+#define PDG_TX_REQ_RESERVED_0C_MASK                                                 0xffff0000
+
+#endif
diff --git a/hw/peach/v1/phyrx_abort_request_info.h b/hw/peach/v1/phyrx_abort_request_info.h
new file mode 100644
index 000000000000..76d5ef73c2b9
--- /dev/null
+++ b/hw/peach/v1/phyrx_abort_request_info.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_ABORT_REQUEST_INFO_H_
+#define _PHYRX_ABORT_REQUEST_INFO_H_
+
+#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1
+
+struct phyrx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phyrx_abort_reason                                      :  8,
+                      phy_enters_nap_state                                    :  1,
+                      phy_enters_defer_state                                  :  1,
+                      gain_change_by_main                                     :  1,
+                      gain_change_by_bt                                       :  1,
+                      main_tx_indication                                      :  1,
+                      bt_tx_indication                                        :  1,
+                      concurrent_mode                                         :  1,
+                      reserved_0                                              :  1,
+                      receive_duration                                        : 16;
+#else
+             uint32_t receive_duration                                        : 16,
+                      reserved_0                                              :  1,
+                      concurrent_mode                                         :  1,
+                      bt_tx_indication                                        :  1,
+                      main_tx_indication                                      :  1,
+                      gain_change_by_bt                                       :  1,
+                      gain_change_by_main                                     :  1,
+                      phy_enters_defer_state                                  :  1,
+                      phy_enters_nap_state                                    :  1,
+                      phyrx_abort_reason                                      :  8;
+#endif
+};
+
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET                          0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB                             0
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB                             7
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK                            0x000000ff
+
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET                        0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB                           8
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB                           8
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK                          0x00000100
+
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET                      0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB                         9
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB                         9
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK                        0x00000200
+
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET                         0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB                            10
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB                            10
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK                           0x00000400
+
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET                           0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB                              11
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB                              11
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK                             0x00000800
+
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET                          0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB                             12
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB                             12
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK                            0x00001000
+
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET                            0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB                               13
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB                               13
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK                              0x00002000
+
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET                             0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB                                14
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB                                14
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK                               0x00004000
+
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET                                  0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB                                     15
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB                                     15
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK                                    0x00008000
+
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET                            0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB                               16
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB                               31
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK                              0xffff0000
+
+#endif
diff --git a/hw/peach/v1/phyrx_common_user_info.h b/hw/peach/v1/phyrx_common_user_info.h
new file mode 100644
index 000000000000..eeb21a463ecd
--- /dev/null
+++ b/hw/peach/v1/phyrx_common_user_info.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_COMMON_USER_INFO_H_
+#define _PHYRX_COMMON_USER_INFO_H_
+
+#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4
+
+struct phyrx_common_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t receive_duration                                        : 16,
+                      reserved_0a                                             : 16;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_1a                                             :  9,
+                      obss_nav_update_enable                                  :  1,
+                      obss_nav_value                                          : 16;
+             uint32_t eht_ppdu_type                                           :  2,
+                      bss_color_id                                            :  6,
+                      dl_ul_flag                                              :  1,
+                      txop_duration                                           :  7,
+                      cp_setting                                              :  2,
+                      ltf_size                                                :  2,
+                      spatial_reuse                                           :  4,
+                      rx_ndp                                                  :  1,
+                      dot11be_su_extended                                     :  1,
+                      reserved_2a                                             :  6;
+             uint32_t eht_duplicate                                           :  2,
+                      eht_sig_cmn_field_type                                  :  2,
+                      doppler_indication                                      :  1,
+                      sta_id                                                  : 11,
+                      puncture_bitmap                                         : 16;
+#else
+             uint32_t reserved_0a                                             : 16,
+                      receive_duration                                        : 16;
+             uint32_t obss_nav_value                                          : 16,
+                      obss_nav_update_enable                                  :  1,
+                      reserved_1a                                             :  9,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             uint32_t reserved_2a                                             :  6,
+                      dot11be_su_extended                                     :  1,
+                      rx_ndp                                                  :  1,
+                      spatial_reuse                                           :  4,
+                      ltf_size                                                :  2,
+                      cp_setting                                              :  2,
+                      txop_duration                                           :  7,
+                      dl_ul_flag                                              :  1,
+                      bss_color_id                                            :  6,
+                      eht_ppdu_type                                           :  2;
+             uint32_t puncture_bitmap                                         : 16,
+                      sta_id                                                  : 11,
+                      doppler_indication                                      :  1,
+                      eht_sig_cmn_field_type                                  :  2,
+                      eht_duplicate                                           :  2;
+#endif
+};
+
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET                              0x00000000
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB                                 0
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB                                 15
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK                                0x0000ffff
+
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET                                   0x00000000
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB                                      16
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB                                      31
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK                                     0xffff0000
+
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET               0x00000004
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                  0
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                  5
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                 0x0000003f
+
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET                                   0x00000004
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB                                      6
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB                                      14
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK                                     0x00007fc0
+
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET                        0x00000004
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB                           15
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB                           15
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK                          0x00008000
+
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET                                0x00000004
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB                                   16
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB                                   31
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK                                  0xffff0000
+
+#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_OFFSET                                 0x00000008
+#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_LSB                                    0
+#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MSB                                    1
+#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MASK                                   0x00000003
+
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET                                  0x00000008
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB                                     2
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB                                     7
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK                                    0x000000fc
+
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET                                    0x00000008
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB                                       8
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB                                       8
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK                                      0x00000100
+
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET                                 0x00000008
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB                                    9
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB                                    15
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK                                   0x0000fe00
+
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET                                    0x00000008
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB                                       16
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB                                       17
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK                                      0x00030000
+
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET                                      0x00000008
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB                                         18
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB                                         19
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK                                        0x000c0000
+
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET                                 0x00000008
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB                                    20
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB                                    23
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK                                   0x00f00000
+
+#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET                                        0x00000008
+#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB                                           24
+#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB                                           24
+#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK                                          0x01000000
+
+#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_OFFSET                           0x00000008
+#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_LSB                              25
+#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MSB                              25
+#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MASK                             0x02000000
+
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET                                   0x00000008
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB                                      26
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB                                      31
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK                                     0xfc000000
+
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET                                 0x0000000c
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB                                    0
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB                                    1
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK                                   0x00000003
+
+#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_OFFSET                        0x0000000c
+#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_LSB                           2
+#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MSB                           3
+#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MASK                          0x0000000c
+
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET                            0x0000000c
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB                               4
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB                               4
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK                              0x00000010
+
+#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET                                        0x0000000c
+#define PHYRX_COMMON_USER_INFO_STA_ID_LSB                                           5
+#define PHYRX_COMMON_USER_INFO_STA_ID_MSB                                           15
+#define PHYRX_COMMON_USER_INFO_STA_ID_MASK                                          0x0000ffe0
+
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET                               0x0000000c
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB                                  16
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB                                  31
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK                                 0xffff0000
+
+#endif
diff --git a/hw/peach/v1/phyrx_he_sig_a_mu_dl.h b/hw/peach/v1/phyrx_he_sig_a_mu_dl.h
new file mode 100644
index 000000000000..d1c2b1e1b8e4
--- /dev/null
+++ b/hw/peach/v1/phyrx_he_sig_a_mu_dl.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_HE_SIG_A_MU_DL_H_
+#define _PHYRX_HE_SIG_A_MU_DL_H_
+
+#include "he_sig_a_mu_dl_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2
+
+struct phyrx_he_sig_a_mu_dl {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_dl_info                                       phyrx_he_sig_a_mu_dl_info_details;
+#else
+             struct   he_sig_a_mu_dl_info                                       phyrx_he_sig_a_mu_dl_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET    0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB       0
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB       0
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK      0x00000001
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET  0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB     1
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB     3
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK    0x0000000e
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET  0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB     4
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB     4
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK    0x00000010
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB     5
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB     10
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x000007e0
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB    11
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB    14
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x00007800
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB      15
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB      17
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK     0x00038000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB  22
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB  22
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET   0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB      23
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB      24
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK     0x01800000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET   0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB      26
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB      31
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK     0xfc000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB    0
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB    6
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET   0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB      7
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB      7
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK     0x00000080
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB  8
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB  10
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 11
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET          0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB             12
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB             12
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK            0x00001000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 14
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET           0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB              16
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB              19
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK             0x000f0000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET          0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB             20
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB             25
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK            0x03f00000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET   0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB      26
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB      30
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK     0x7c000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/hw/peach/v1/phyrx_he_sig_a_mu_ul.h b/hw/peach/v1/phyrx_he_sig_a_mu_ul.h
new file mode 100644
index 000000000000..fdf4307f5ff7
--- /dev/null
+++ b/hw/peach/v1/phyrx_he_sig_a_mu_ul.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_HE_SIG_A_MU_UL_H_
+#define _PHYRX_HE_SIG_A_MU_UL_H_
+
+#include "he_sig_a_mu_ul_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2
+
+struct phyrx_he_sig_a_mu_ul {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_mu_ul_info                                       phyrx_he_sig_a_mu_ul_info_details;
+#else
+             struct   he_sig_a_mu_ul_info                                       phyrx_he_sig_a_mu_ul_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET  0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB     1
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB     6
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK    0x0000007e
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB    7
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB    22
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK   0x007fff80
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET   0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB      23
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB      23
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK     0x00800000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET   0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB      24
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB      25
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK     0x03000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET   0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB      26
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB      31
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK     0xfc000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB    0
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB    6
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK   0x0000007f
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET   0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB      7
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB      15
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK     0x0000ff80
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET           0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB              16
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB              19
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK             0x000f0000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET          0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB             20
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB             25
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK            0x03f00000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET   0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB      26
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB      30
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK     0x7c000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/hw/peach/v1/phyrx_he_sig_a_su.h b/hw/peach/v1/phyrx_he_sig_a_su.h
new file mode 100644
index 000000000000..387503c0d79d
--- /dev/null
+++ b/hw/peach/v1/phyrx_he_sig_a_su.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_HE_SIG_A_SU_H_
+#define _PHYRX_HE_SIG_A_SU_H_
+
+#include "he_sig_a_su_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2
+
+struct phyrx_he_sig_a_su {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_a_su_info                                          phyrx_he_sig_a_su_info_details;
+#else
+             struct   he_sig_a_su_info                                          phyrx_he_sig_a_su_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET   0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB      0
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB      0
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK     0x00000001
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET         0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB            1
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB            1
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK           0x00000002
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET          0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB             2
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB             2
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK            0x00000004
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET        0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB           3
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB           6
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK          0x00000078
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET                 0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB                    7
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB                    7
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK                   0x00000080
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET        0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB           8
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB           13
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK          0x00003f00
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET         0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB            14
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB            14
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK           0x00004000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET       0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB          15
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB          18
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK         0x00078000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET         0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB            19
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB            20
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK           0x00180000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET         0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB            21
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB            22
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK           0x00600000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET                0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB                   23
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB                   25
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK                  0x03800000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET         0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB            26
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB            31
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK           0xfc000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET       0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB          0
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB          6
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK         0x0000007f
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET              0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB                 7
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB                 7
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK                0x00000080
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET   0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB      8
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB      8
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK     0x00000100
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET                0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB                   9
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB                   9
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK                  0x00000200
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET                0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB                   10
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB                   10
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK                  0x00000400
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 12
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET         0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB            14
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB            14
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK           0x00004000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET  0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB     15
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB     15
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK    0x00008000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET                 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB                    16
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB                    19
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK                   0x000f0000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET                0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB                   20
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB                   25
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK                  0x03f00000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB    26
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB    26
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK   0x04000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB    27
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB    29
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK   0x38000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET              0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB                 30
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB                 30
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK                0x40000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/hw/peach/v1/phyrx_he_sig_b1_mu.h b/hw/peach/v1/phyrx_he_sig_b1_mu.h
new file mode 100644
index 000000000000..cfe51c2026c0
--- /dev/null
+++ b/hw/peach/v1/phyrx_he_sig_b1_mu.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_HE_SIG_B1_MU_H_
+#define _PHYRX_HE_SIG_B1_MU_H_
+
+#include "he_sig_b1_mu_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 1
+
+struct phyrx_he_sig_b1_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b1_mu_info                                         phyrx_he_sig_b1_mu_info_details;
+#else
+             struct   he_sig_b1_mu_info                                         phyrx_he_sig_b1_mu_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET     0x00000000
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB        0
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB        7
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK       0x000000ff
+
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET        0x00000000
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB           8
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB           30
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK          0x7fffff00
+
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/hw/peach/v1/phyrx_he_sig_b2_mu.h b/hw/peach/v1/phyrx_he_sig_b2_mu.h
new file mode 100644
index 000000000000..1fc8f8b0da22
--- /dev/null
+++ b/hw/peach/v1/phyrx_he_sig_b2_mu.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_HE_SIG_B2_MU_H_
+#define _PHYRX_HE_SIG_B2_MU_H_
+
+#include "he_sig_b2_mu_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2
+
+struct phyrx_he_sig_b2_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_mu_info                                         phyrx_he_sig_b2_mu_info_details;
+#else
+             struct   he_sig_b2_mu_info                                         phyrx_he_sig_b2_mu_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET            0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB               0
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB               10
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK              0x000007ff
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB   11
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB   14
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK  0x00007800
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET           0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB              15
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB              18
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK             0x00078000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB    19
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB    19
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK   0x00080000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET        0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB           20
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB           20
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK          0x00100000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET       0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB          21
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB          27
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK         0x0fe00000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET              0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB                 28
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB                 30
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK                0x70000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET        0x00000004
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB           0
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB           7
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK          0x000000ff
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET           0x00000004
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB              8
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB              15
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK             0x0000ff00
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET       0x00000004
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB          16
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB          31
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK         0xffff0000
+
+#endif
diff --git a/hw/peach/v1/phyrx_he_sig_b2_ofdma.h b/hw/peach/v1/phyrx_he_sig_b2_ofdma.h
new file mode 100644
index 000000000000..60f343a1eb17
--- /dev/null
+++ b/hw/peach/v1/phyrx_he_sig_b2_ofdma.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_
+#define _PHYRX_HE_SIG_B2_OFDMA_H_
+
+#include "he_sig_b2_ofdma_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2
+
+struct phyrx_he_sig_b2_ofdma {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   he_sig_b2_ofdma_info                                      phyrx_he_sig_b2_ofdma_info_details;
+#else
+             struct   he_sig_b2_ofdma_info                                      phyrx_he_sig_b2_ofdma_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET      0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB         0
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB         10
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK        0x000007ff
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET        0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB           11
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB           13
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK          0x00003800
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET        0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB           14
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB           14
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK          0x00004000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET     0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB        15
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB        18
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK       0x00078000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET     0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB        19
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB        19
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK       0x00080000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET  0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB     20
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB     20
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK    0x00100000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET  0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB     21
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB     30
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK    0x7fe00000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET  0x00000004
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB     0
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB     7
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK    0x000000ff
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET     0x00000004
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB        8
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB        15
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK       0x0000ff00
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB    16
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB    31
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK   0xffff0000
+
+#endif
diff --git a/hw/peach/v1/phyrx_ht_sig.h b/hw/peach/v1/phyrx_ht_sig.h
new file mode 100644
index 000000000000..f9f1e04911a2
--- /dev/null
+++ b/hw/peach/v1/phyrx_ht_sig.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_HT_SIG_H_
+#define _PHYRX_HT_SIG_H_
+
+#include "ht_sig_info.h"
+#define NUM_OF_DWORDS_PHYRX_HT_SIG 2
+
+struct phyrx_ht_sig {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   ht_sig_info                                               phyrx_ht_sig_info_details;
+#else
+             struct   ht_sig_info                                               phyrx_ht_sig_info_details;
+#endif
+};
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET                           0x00000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB                              0
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB                              6
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK                             0x0000007f
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET                           0x00000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB                              7
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB                              7
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK                             0x00000080
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET                        0x00000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB                           8
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB                           23
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK                          0x00ffff00
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET                    0x00000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB                       24
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB                       31
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK                      0xff000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET                     0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB                        0
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB                        0
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK                       0x00000001
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET                  0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB                     1
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB                     1
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK                    0x00000002
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET                   0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB                      2
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB                      2
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK                     0x00000004
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET                   0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB                      3
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB                      3
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK                     0x00000008
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET                          0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB                             4
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB                             5
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK                            0x00000030
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET                    0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB                       6
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB                       6
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK                      0x00000040
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET                      0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB                         7
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB                         7
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK                        0x00000080
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET                0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB                   8
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB                   9
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK                  0x00000300
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET                           0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB                              10
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB                              17
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK                             0x0003fc00
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET                   0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB                      18
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB                      23
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK                     0x00fc0000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET                    0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB                       24
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB                       30
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK                      0x7f000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET     0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB        31
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB        31
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK       0x80000000
+
+#endif
diff --git a/hw/peach/v1/phyrx_l_sig_a.h b/hw/peach/v1/phyrx_l_sig_a.h
new file mode 100644
index 000000000000..568e3dfc27f1
--- /dev/null
+++ b/hw/peach/v1/phyrx_l_sig_a.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_L_SIG_A_H_
+#define _PHYRX_L_SIG_A_H_
+
+#include "l_sig_a_info.h"
+#define NUM_OF_DWORDS_PHYRX_L_SIG_A 1
+
+struct phyrx_l_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_a_info                                              phyrx_l_sig_a_info_details;
+#else
+             struct   l_sig_a_info                                              phyrx_l_sig_a_info_details;
+#endif
+};
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET                        0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB                           0
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB                           3
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK                          0x0000000f
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET               0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB                  4
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB                  4
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK                 0x00000010
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET                      0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB                         5
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB                         16
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK                        0x0001ffe0
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET                      0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB                         17
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB                         17
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK                        0x00020000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET                        0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB                           18
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB                           23
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK                          0x00fc0000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET                    0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB                       24
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB                       27
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK                      0x0f000000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET  0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB     28
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB     28
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK    0x10000000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET                    0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB                       29
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB                       30
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK                      0x60000000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x80000000
+
+#endif
diff --git a/hw/peach/v1/phyrx_l_sig_b.h b/hw/peach/v1/phyrx_l_sig_b.h
new file mode 100644
index 000000000000..6c472400e614
--- /dev/null
+++ b/hw/peach/v1/phyrx_l_sig_b.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_L_SIG_B_H_
+#define _PHYRX_L_SIG_B_H_
+
+#include "l_sig_b_info.h"
+#define NUM_OF_DWORDS_PHYRX_L_SIG_B 1
+
+struct phyrx_l_sig_b {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   l_sig_b_info                                              phyrx_l_sig_b_info_details;
+#else
+             struct   l_sig_b_info                                              phyrx_l_sig_b_info_details;
+#endif
+};
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET                        0x00000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB                           0
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB                           3
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK                          0x0000000f
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET                      0x00000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB                         4
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB                         15
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK                        0x0000fff0
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET                    0x00000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB                       16
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB                       30
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK                      0x7fff0000
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET   0x00000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB      31
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB      31
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK     0x80000000
+
+#endif
diff --git a/hw/peach/v1/phyrx_location.h b/hw/peach/v1/phyrx_location.h
new file mode 100644
index 000000000000..1c92be1c6d5f
--- /dev/null
+++ b/hw/peach/v1/phyrx_location.h
@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_LOCATION_H_
+#define _PHYRX_LOCATION_H_
+
+#include "rx_location_info.h"
+#define NUM_OF_DWORDS_PHYRX_LOCATION 28
+
+struct phyrx_location {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_location_info                                          rx_location_info_details;
+#else
+             struct   rx_location_info                                          rx_location_info_details;
+#endif
+};
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET       0x00000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB          0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB          0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK         0x00000001
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET             0x00000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB                1
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB                1
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK               0x00000002
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_OFFSET                0x00000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_LSB                   2
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MSB                   3
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MASK                  0x0000000c
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET                   0x00000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB                      4
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB                      7
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK                     0x000000f0
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET                  0x00000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB                     8
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB                     15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK                    0x0000ff00
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET            0x00000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB               16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB               23
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK              0x00ff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET              0x00000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB                 24
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB                 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK                0xff000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET     0x00000004
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB        0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB        7
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK       0x000000ff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET    0x00000004
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB       8
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB       15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK      0x0000ff00
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET               0x00000004
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB                  16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB                  23
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK                 0x00ff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET               0x00000004
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB                  24
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB                  31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK                 0xff000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB    0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB    31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK   0xffffffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB    0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB    7
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK   0x000000ff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET                   0x0000000c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB                      8
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK                     0x0000ff00
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET               0x0000000c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB                  16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB                  19
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK                 0x000f0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET               0x0000000c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB                  20
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB                  23
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK                 0x00f00000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET                 0x0000000c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB                    24
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB                    31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK                   0xff000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET          0x00000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB             0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB             15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK            0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET            0x00000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB               16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB               23
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK              0x00ff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET                  0x00000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB                     24
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB                     31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK                    0xff000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET                  0x00000014
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB                     0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB                     31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK                    0xffffffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET            0x00000018
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB               0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB               31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK              0xffffffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET                    0x0000001c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB                       0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB                       31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK                      0xffffffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET                  0x00000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB                     0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB                     15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK                    0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET                  0x00000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB                     16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB                     31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK                    0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET                  0x00000024
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB                     0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB                     15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK                    0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET                  0x00000024
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB                     16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB                     31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK                    0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET           0x00000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB              0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB              7
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK             0x000000ff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET       0x00000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB          8
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB          15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK         0x0000ff00
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET             0x00000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB                16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB                31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK               0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET                    0x0000002c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB                       0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB                       15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK                      0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET                    0x0000002c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB                       16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB                       31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK                      0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET                    0x00000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB                       0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB                       15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK                      0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET                    0x00000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB                       16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB                       31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK                      0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET                    0x00000034
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB                       0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB                       15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK                      0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET                    0x00000034
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB                       16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB                       31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK                      0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET                    0x00000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB                       0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB                       15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK                      0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET                    0x00000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB                       16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB                       31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK                      0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET                    0x0000003c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB                       0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB                       15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK                      0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET                    0x0000003c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB                       16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB                       31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK                      0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET                   0x00000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK                     0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET                   0x00000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK                     0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET                   0x00000044
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK                     0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET                   0x00000044
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK                     0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET                   0x00000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK                     0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET                   0x00000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK                     0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET                   0x0000004c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK                     0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET                   0x0000004c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK                     0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET                   0x00000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK                     0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET                   0x00000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK                     0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET                   0x00000054
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK                     0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET                   0x00000054
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK                     0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET                   0x00000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK                     0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET                   0x00000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK                     0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET                   0x0000005c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK                     0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET                   0x0000005c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK                     0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET                   0x00000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK                     0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET                   0x00000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK                     0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET                   0x00000064
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK                     0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET                   0x00000064
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK                     0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET                   0x00000068
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB                      0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB                      15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK                     0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET                   0x00000068
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB                      16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB                      31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK                     0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET                 0x0000006c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB                    0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB                    31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK                   0xffffffff
+
+#endif
diff --git a/hw/peach/v1/phyrx_other_receive_info_ru_details.h b/hw/peach/v1/phyrx_other_receive_info_ru_details.h
new file mode 100644
index 000000000000..03f379615ad0
--- /dev/null
+++ b/hw/peach/v1/phyrx_other_receive_info_ru_details.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
+#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
+
+#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 3
+
+struct phyrx_other_receive_info_ru_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ru_details_channel_0                                    : 32;
+             uint32_t ru_details_channel_1                                    : 32;
+             uint32_t spare                                                   : 32;
+#else
+             uint32_t ru_details_channel_0                                    : 32;
+             uint32_t ru_details_channel_1                                    : 32;
+             uint32_t spare                                                   : 32;
+#endif
+};
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET             0x00000000
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB                0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB                31
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK               0xffffffff
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET             0x00000004
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB                0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB                31
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK               0xffffffff
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET                            0x00000008
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB                               0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB                               31
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK                              0xffffffff
+
+#endif
diff --git a/hw/peach/v1/phyrx_pkt_end.h b/hw/peach/v1/phyrx_pkt_end.h
new file mode 100644
index 000000000000..ab6d45be6a99
--- /dev/null
+++ b/hw/peach/v1/phyrx_pkt_end.h
@@ -0,0 +1,432 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_PKT_END_H_
+#define _PHYRX_PKT_END_H_
+
+#include "phyrx_pkt_end_info.h"
+#define NUM_OF_DWORDS_PHYRX_PKT_END 24
+
+struct phyrx_pkt_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   phyrx_pkt_end_info                                        rx_pkt_end_details;
+#else
+             struct   phyrx_pkt_end_info                                        rx_pkt_end_details;
+#endif
+};
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET                 0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB                    1
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB                    1
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK                   0x00000002
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET                   0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB                      2
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB                      2
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK                     0x00000004
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET                     0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB                        3
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB                        3
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK                       0x00000008
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET                         0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB                            4
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB                            4
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK                           0x00000010
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET            0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB               5
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB               5
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK              0x00000020
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET                         0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB                            6
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB                            7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK                           0x000000c0
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET                           0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB                              8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB                              15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK                             0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET                         0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB                            16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB                            31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK                           0xffff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET     0x00000014
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB        12
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB        31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK       0xfffff000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET                  0x00000058
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB                     0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB                     31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK                    0xffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET                 0x0000005c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB                    0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB                    31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK                   0xffffffff
+
+#endif
diff --git a/hw/peach/v1/phyrx_pkt_end_info.h b/hw/peach/v1/phyrx_pkt_end_info.h
new file mode 100644
index 000000000000..31e6ca16566b
--- /dev/null
+++ b/hw/peach/v1/phyrx_pkt_end_info.h
@@ -0,0 +1,457 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_PKT_END_INFO_H_
+#define _PHYRX_PKT_END_INFO_H_
+
+#include "receive_rssi_info.h"
+#include "rx_timing_info.h"
+#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24
+
+struct phyrx_pkt_end_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t __reserved_g_0001                                        :  1,
+                      location_info_valid                                     :  1,
+                      timing_info_valid                                       :  1,
+                      rssi_info_valid                                         :  1,
+                      reserved_0a                                             :  1,
+                      frameless_frame_received                                :  1,
+                      reserved_0b                                             :  2,
+                      rssi_comb                                               :  8,
+                      reserved_0c                                             : 16;
+             struct   rx_timing_info                                            rx_timing_info_details;
+             struct   receive_rssi_info                                         post_rssi_info_details;
+             uint32_t phy_sw_status_31_0                                      : 32;
+             uint32_t phy_sw_status_63_32                                     : 32;
+#else
+             uint32_t reserved_0c                                             : 16,
+                      rssi_comb                                               :  8,
+                      reserved_0b                                             :  2,
+                      frameless_frame_received                                :  1,
+                      reserved_0a                                             :  1,
+                      rssi_info_valid                                         :  1,
+                      timing_info_valid                                       :  1,
+                      location_info_valid                                     :  1,
+                      __reserved_g_0001                                        :  1;
+             struct   rx_timing_info                                            rx_timing_info_details;
+             struct   receive_rssi_info                                         post_rssi_info_details;
+             uint32_t phy_sw_status_31_0                                      : 32;
+             uint32_t phy_sw_status_63_32                                     : 32;
+#endif
+};
+
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET                               0x00000000
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB                                  1
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB                                  1
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK                                 0x00000002
+
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET                                 0x00000000
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB                                    2
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB                                    2
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK                                   0x00000004
+
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET                                   0x00000000
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB                                      3
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB                                      3
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK                                     0x00000008
+
+#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET                                       0x00000000
+#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB                                          4
+#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB                                          4
+#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK                                         0x00000010
+
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET                          0x00000000
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB                             5
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB                             5
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK                            0x00000020
+
+#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET                                       0x00000000
+#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB                                          6
+#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB                                          7
+#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK                                         0x000000c0
+
+#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET                                         0x00000000
+#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB                                            8
+#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB                                            15
+#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK                                           0x0000ff00
+
+#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET                                       0x00000000
+#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB                                          16
+#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB                                          31
+#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK                                         0xffff0000
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET   0x00000004
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET   0x00000008
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET   0x0000000c
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET   0x00000010
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB      0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK     0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET      0x00000014
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB         0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB         11
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK        0x00000fff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET                   0x00000014
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB                      12
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB                      31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK                     0xfffff000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET          0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET          0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET    0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET   0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET    0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET   0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET       0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET       0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET          0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET          0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET    0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET   0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET    0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET   0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET       0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET       0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET          0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET          0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET    0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET   0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET    0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET   0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET       0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET       0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET          0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB             0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB             7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK            0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET          0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB             8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB             15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK            0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET    0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB       16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB       23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK      0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET   0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET    0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB       0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB       7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK      0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB  8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB  15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB  16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB  23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET   0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB      24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB      31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK     0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET       0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB          0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB          7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK         0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB          8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB          15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK         0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB          16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB          23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK         0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET       0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB          24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB          31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK         0xff000000
+
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET                                0x00000058
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB                                   0
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB                                   31
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK                                  0xffffffff
+
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET                               0x0000005c
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB                                  0
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB                                  31
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK                                 0xffffffff
+
+#endif
diff --git a/hw/peach/v1/phyrx_rssi_legacy.h b/hw/peach/v1/phyrx_rssi_legacy.h
new file mode 100644
index 000000000000..9b8faea41c83
--- /dev/null
+++ b/hw/peach/v1/phyrx_rssi_legacy.h
@@ -0,0 +1,811 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_RSSI_LEGACY_H_
+#define _PHYRX_RSSI_LEGACY_H_
+
+#include "receive_rssi_info.h"
+#include "receive_pkt_start_info.h"
+#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42
+
+struct phyrx_rssi_legacy {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   receive_pkt_start_info                                    rx_pkt_start_details;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             struct   receive_rssi_info                                         pre_rssi_info_details;
+             struct   receive_rssi_info                                         preamble_rssi_info_details;
+             uint32_t pre_rssi_comb                                           :  8,
+                      rssi_comb                                               :  8,
+                      normalized_pre_rssi_comb                                :  8,
+                      normalized_rssi_comb                                    :  8;
+             uint32_t rssi_comb_ppdu                                          :  8,
+                      rssi_db_to_dbm_offset                                   :  8,
+                      rssi_for_spatial_reuse                                  :  8,
+                      rssi_for_trigger_resp                                   :  8;
+#else
+             struct   receive_pkt_start_info                                    rx_pkt_start_details;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             struct   receive_rssi_info                                         pre_rssi_info_details;
+             struct   receive_rssi_info                                         preamble_rssi_info_details;
+             uint32_t normalized_rssi_comb                                    :  8,
+                      normalized_pre_rssi_comb                                :  8,
+                      rssi_comb                                               :  8,
+                      pre_rssi_comb                                           :  8;
+             uint32_t rssi_for_trigger_resp                                   :  8,
+                      rssi_for_spatial_reuse                                  :  8,
+                      rssi_db_to_dbm_offset                                   :  8,
+                      rssi_comb_ppdu                                          :  8;
+#endif
+};
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET                0x00000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB                   0
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB                   3
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK                  0x0000000f
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET            0x00000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB               4
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB               4
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK              0x00000010
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET             0x00000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB                5
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB                7
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK               0x000000e0
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET                 0x00000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB                    8
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB                    15
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK                   0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET                   0x00000000
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB                      16
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB                      31
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK                     0xffff0000
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET     0x00000004
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB        0
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB        31
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK       0xffffffff
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET    0x00000008
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB       0
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB       31
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK      0xffffffff
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET      0x0000000c
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB         0
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB         7
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK        0x000000ff
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET       0x0000000c
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB          8
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB          8
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK         0x00000100
+
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET                   0x0000000c
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB                      9
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB                      31
+#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK                     0xfffffe00
+
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET                                   0x00000010
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB                                      0
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB                                      31
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK                                     0xffffffff
+
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET                                        0x00000014
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB                                           0
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB                                           31
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK                                          0xffffffff
+
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET                                        0x00000018
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB                                           0
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB                                           31
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK                                          0xffffffff
+
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET                                        0x0000001c
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB                                           0
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB                                           31
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK                                          0xffffffff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET            0x00000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK              0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET            0x00000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK              0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET      0x00000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK        0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET     0x00000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK       0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET      0x00000024
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB         0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB         7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK        0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB    8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB    15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK   0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB    16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB    23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK   0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET     0x00000024
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK       0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET         0x00000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK           0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET         0x00000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK           0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET         0x00000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK           0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET         0x00000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK           0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET         0x0000002c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK           0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET         0x0000002c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK           0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET         0x0000002c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK           0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET         0x0000002c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK           0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET            0x00000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK              0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET            0x00000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK              0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET      0x00000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK        0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET     0x00000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK       0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET      0x00000034
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB         0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB         7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK        0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB    8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB    15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK   0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB    16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB    23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK   0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET     0x00000034
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK       0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET         0x00000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK           0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET         0x00000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK           0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET         0x00000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK           0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET         0x00000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK           0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET         0x0000003c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK           0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET         0x0000003c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK           0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET         0x0000003c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK           0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET         0x0000003c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK           0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET            0x00000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK              0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET            0x00000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK              0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET      0x00000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK        0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET     0x00000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK       0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET      0x00000044
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB         0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB         7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK        0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB    8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB    15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK   0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB    16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB    23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK   0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET     0x00000044
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK       0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET         0x00000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK           0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET         0x00000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK           0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET         0x00000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK           0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET         0x00000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK           0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET         0x0000004c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK           0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET         0x0000004c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK           0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET         0x0000004c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK           0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET         0x0000004c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK           0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET            0x00000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB               0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB               7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK              0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET            0x00000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB               8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB               15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK              0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET      0x00000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB         16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB         23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK        0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET     0x00000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK       0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET      0x00000054
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB         0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB         7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK        0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB    8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB    15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK   0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB    16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB    23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK   0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET     0x00000054
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB        24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB        31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK       0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET         0x00000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK           0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET         0x00000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK           0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET         0x00000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK           0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET         0x00000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK           0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET         0x0000005c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB            0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB            7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK           0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET         0x0000005c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB            8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB            15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK           0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET         0x0000005c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB            16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB            23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK           0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET         0x0000005c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB            24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB            31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK           0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET       0x00000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK         0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET       0x00000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK         0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK   0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK  0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB    0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB    7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK   0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK  0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET    0x00000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK      0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET    0x00000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK      0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET    0x00000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK      0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET    0x00000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK      0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET    0x0000006c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK      0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET    0x0000006c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK      0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET    0x0000006c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK      0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET    0x0000006c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK      0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET       0x00000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK         0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET       0x00000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK         0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK   0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK  0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB    0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB    7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK   0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK  0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET    0x00000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK      0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET    0x00000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK      0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET    0x00000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK      0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET    0x00000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK      0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET    0x0000007c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK      0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET    0x0000007c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK      0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET    0x0000007c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK      0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET    0x0000007c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK      0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET       0x00000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK         0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET       0x00000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK         0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK   0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK  0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB    0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB    7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK   0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK  0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET    0x00000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK      0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET    0x00000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK      0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET    0x00000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK      0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET    0x00000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK      0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET    0x0000008c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK      0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET    0x0000008c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK      0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET    0x0000008c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK      0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET    0x0000008c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK      0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET       0x00000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB          0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB          7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK         0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET       0x00000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB          8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB          15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK         0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB    16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB    23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK   0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK  0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000094
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB    0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB    7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK   0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000094
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000094
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000094
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB   24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB   31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK  0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET    0x00000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK      0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET    0x00000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK      0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET    0x00000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK      0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET    0x00000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK      0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET    0x0000009c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB       0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB       7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK      0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET    0x0000009c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB       8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB       15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK      0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET    0x0000009c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB       16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB       23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK      0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET    0x0000009c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB       24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB       31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK      0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET                                      0x000000a0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB                                         0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB                                         7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK                                        0x000000ff
+
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET                                          0x000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB                                             8
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB                                             15
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK                                            0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET                           0x000000a0
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB                              16
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB                              23
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK                             0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET                               0x000000a0
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB                                  24
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB                                  31
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK                                 0xff000000
+
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET                                     0x000000a4
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB                                        0
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB                                        7
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK                                       0x000000ff
+
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET                              0x000000a4
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB                                 8
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB                                 15
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK                                0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET                             0x000000a4
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB                                16
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB                                23
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK                               0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET                              0x000000a4
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB                                 24
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB                                 31
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK                                0xff000000
+
+#endif
diff --git a/hw/peach/v1/phyrx_user_info.h b/hw/peach/v1/phyrx_user_info.h
new file mode 100644
index 000000000000..b3b4cb6ced15
--- /dev/null
+++ b/hw/peach/v1/phyrx_user_info.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_USER_INFO_H_
+#define _PHYRX_USER_INFO_H_
+
+#include "receive_user_info.h"
+#define NUM_OF_DWORDS_PHYRX_USER_INFO 8
+
+struct phyrx_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   receive_user_info                                         receive_user_info_details;
+#else
+             struct   receive_user_info                                         receive_user_info_details;
+#endif
+};
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET                0x00000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB                   0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB                   15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK                  0x0000ffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET                  0x00000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB                     16
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB                     23
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK                    0x00ff0000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET                   0x00000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB                      24
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB                      27
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK                     0x0f000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET                       0x00000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB                          28
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB                          28
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK                         0x10000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET             0x00000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB                29
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB                31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK               0xe0000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET                   0x00000004
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB                      0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB                      3
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK                     0x0000000f
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET                        0x00000004
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB                           4
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB                           5
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK                          0x00000030
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET                0x00000004
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB                   7
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB                   7
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK                  0x00000080
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET             0x00000004
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB                8
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB                15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK               0x0000ff00
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET          0x00000004
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB             16
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB             18
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK            0x00070000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET                0x00000004
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB                   19
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB                   23
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK                  0x00f80000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET        0x00000004
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB           24
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB           31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK          0xff000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET   0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB      0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB      0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK     0x00000001
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET                0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB                   1
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB                   7
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK                  0x000000fe
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET                        0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB                           8
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB                           10
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK                          0x00000700
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET              0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB                 11
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB                 13
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK                0x00003800
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET                    0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB                       14
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB                       14
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK                      0x00004000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET                       0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB                          15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB                          15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK                         0x00008000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET               0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB                  16
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB                  19
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK                 0x000f0000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET               0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB                  20
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB                  23
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK                 0x00f00000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET               0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB                  24
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB                  27
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK                 0x0f000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET               0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB                  28
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB                  31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK                 0xf0000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET        0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB           0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB           5
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK          0x0000003f
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET                0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB                   6
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB                   7
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK                  0x000000c0
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET        0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB           8
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB           13
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK          0x00003f00
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET                0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB                   14
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB                   15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK                  0x0000c000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET        0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB           16
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB           21
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK          0x003f0000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET                0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB                   22
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB                   23
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK                  0x00c00000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET        0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB           24
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB           29
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK          0x3f000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET                0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB                   30
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB                   31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK                  0xc0000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET          0x00000010
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB             0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB             31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK            0xffffffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET          0x00000014
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB             0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB             31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK            0xffffffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET          0x00000018
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB             0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB             31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK            0xffffffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET          0x0000001c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB             0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB             31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK            0xffffffff
+
+#endif
diff --git a/hw/peach/v1/phyrx_vht_sig_a.h b/hw/peach/v1/phyrx_vht_sig_a.h
new file mode 100644
index 000000000000..dda1c96b070d
--- /dev/null
+++ b/hw/peach/v1/phyrx_vht_sig_a.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_VHT_SIG_A_H_
+#define _PHYRX_VHT_SIG_A_H_
+
+#include "vht_sig_a_info.h"
+#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2
+
+struct phyrx_vht_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   vht_sig_a_info                                            phyrx_vht_sig_a_info_details;
+#else
+             struct   vht_sig_a_info                                            phyrx_vht_sig_a_info_details;
+#endif
+};
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET               0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB                  0
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB                  1
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK                 0x00000003
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET         0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB            2
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB            2
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK           0x00000004
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET                    0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB                       3
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB                       3
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK                      0x00000008
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET                0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB                   4
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB                   9
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK                  0x000003f0
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET                   0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB                      10
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB                      21
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK                     0x003ffc00
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET     0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB        22
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB        22
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK       0x00400000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET        0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB           23
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB           23
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK          0x00800000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET              0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB                 24
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB                 31
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK                0xff000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET              0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB                 0
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB                 1
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK                0x00000003
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET            0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB               2
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB               2
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK              0x00000004
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET       0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB          3
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB          3
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK         0x00000008
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET                     0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB                        4
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB                        7
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK                       0x000000f0
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET              0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB                 8
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB                 8
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK                0x00000100
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET         0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB            9
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB            9
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK           0x00000200
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET                     0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB                        10
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB                        17
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK                       0x0003fc00
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET                    0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB                       18
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB                       23
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK                      0x00fc0000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET              0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB                 24
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB                 30
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK                0x7f000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB  31
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB  31
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/hw/peach/v1/phytx_abort_request_info.h b/hw/peach/v1/phytx_abort_request_info.h
new file mode 100644
index 000000000000..85b70949c579
--- /dev/null
+++ b/hw/peach/v1/phytx_abort_request_info.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYTX_ABORT_REQUEST_INFO_H_
+#define _PHYTX_ABORT_REQUEST_INFO_H_
+
+#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1
+
+struct phytx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t phytx_abort_reason                                      :  8,
+                      user_number                                             :  6,
+                      reserved                                                :  2;
+#else
+             uint16_t reserved                                                :  2,
+                      user_number                                             :  6,
+                      phytx_abort_reason                                      :  8;
+#endif
+};
+
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET                          0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB                             0
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB                             7
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK                            0x000000ff
+
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET                                 0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB                                    8
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB                                    13
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK                                   0x00003f00
+
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET                                    0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB                                       14
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB                                       15
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK                                      0x0000c000
+
+#endif
diff --git a/hw/peach/v1/phytx_pkt_end.h b/hw/peach/v1/phytx_pkt_end.h
new file mode 100644
index 000000000000..d055a48ac3d4
--- /dev/null
+++ b/hw/peach/v1/phytx_pkt_end.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYTX_PKT_END_H_
+#define _PHYTX_PKT_END_H_
+
+#define NUM_OF_WORDS_PHYTX_PKT_END 26
+
+#define NUM_OF_DWORDS_PHYTX_PKT_END 13
+
+struct phytx_pkt_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t start_of_frame_timestamp_15_0                           : 16;
+             uint16_t start_of_frame_timestamp_31_16                          : 16;
+             uint16_t end_of_frame_timestamp_15_0                             : 16;
+             uint16_t end_of_frame_timestamp_31_16                            : 16;
+             uint16_t tx_group_delay                                          : 12,
+                      timing_status                                           :  2,
+                      phyrx_entered_nap_state                                 :  1,
+                      dpdtrain_done                                           :  1;
+             uint16_t transmit_delay                                          : 16;
+             uint16_t tpc_dbg_info_cmn_15_0                                   : 16;
+             uint16_t tpc_dbg_info_cmn_31_16                                  : 16;
+             uint16_t tpc_dbg_info_cmn_47_32                                  : 16;
+             uint16_t tpc_dbg_info_chn1_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn1_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn1_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn1_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn1_79_64                                 : 16;
+             uint16_t tpc_dbg_info_chn2_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn2_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn2_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn2_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn2_79_64                                 : 16;
+             uint16_t phytx_tx_end_sw_info_15_0                               : 16;
+             uint16_t phytx_tx_end_sw_info_31_16                              : 16;
+             uint16_t phytx_tx_end_sw_info_47_32                              : 16;
+             uint16_t phytx_tx_end_sw_info_63_48                              : 16;
+             uint16_t beamform_masked_user_bitmap_15_0                        : 16;
+             uint16_t beamform_masked_user_bitmap_31_16                       : 16;
+             uint16_t beamform_masked_user_bitmap_36_32                       :  5,
+                      reserved_23                                             : 11;
+#else
+             uint16_t start_of_frame_timestamp_15_0                           : 16;
+             uint16_t start_of_frame_timestamp_31_16                          : 16;
+             uint16_t end_of_frame_timestamp_15_0                             : 16;
+             uint16_t end_of_frame_timestamp_31_16                            : 16;
+             uint16_t dpdtrain_done                                           :  1,
+                      phyrx_entered_nap_state                                 :  1,
+                      timing_status                                           :  2,
+                      tx_group_delay                                          : 12;
+             uint16_t transmit_delay                                          : 16;
+             uint16_t tpc_dbg_info_cmn_15_0                                   : 16;
+             uint16_t tpc_dbg_info_cmn_31_16                                  : 16;
+             uint16_t tpc_dbg_info_cmn_47_32                                  : 16;
+             uint16_t tpc_dbg_info_chn1_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn1_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn1_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn1_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn1_79_64                                 : 16;
+             uint16_t tpc_dbg_info_chn2_15_0                                  : 16;
+             uint16_t tpc_dbg_info_chn2_31_16                                 : 16;
+             uint16_t tpc_dbg_info_chn2_47_32                                 : 16;
+             uint16_t tpc_dbg_info_chn2_63_48                                 : 16;
+             uint16_t tpc_dbg_info_chn2_79_64                                 : 16;
+             uint16_t phytx_tx_end_sw_info_15_0                               : 16;
+             uint16_t phytx_tx_end_sw_info_31_16                              : 16;
+             uint16_t phytx_tx_end_sw_info_47_32                              : 16;
+             uint16_t phytx_tx_end_sw_info_63_48                              : 16;
+             uint16_t beamform_masked_user_bitmap_15_0                        : 16;
+             uint16_t beamform_masked_user_bitmap_31_16                       : 16;
+             uint16_t reserved_23                                             : 11,
+                      beamform_masked_user_bitmap_36_32                       :  5;
+#endif
+};
+
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET                          0x00000000
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB                             0
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB                             15
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK                            0x0000ffff
+
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET                         0x00000002
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB                            0
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB                            15
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK                           0x0000ffff
+
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET                            0x00000004
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB                               0
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB                               15
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK                              0x0000ffff
+
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET                           0x00000006
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB                              0
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB                              15
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK                             0x0000ffff
+
+#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET                                         0x00000008
+#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB                                            0
+#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB                                            11
+#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK                                           0x00000fff
+
+#define PHYTX_PKT_END_TIMING_STATUS_OFFSET                                          0x00000008
+#define PHYTX_PKT_END_TIMING_STATUS_LSB                                             12
+#define PHYTX_PKT_END_TIMING_STATUS_MSB                                             13
+#define PHYTX_PKT_END_TIMING_STATUS_MASK                                            0x00003000
+
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET                                0x00000008
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB                                   14
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB                                   14
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK                                  0x00004000
+
+#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET                                          0x00000008
+#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB                                             15
+#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB                                             15
+#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK                                            0x00008000
+
+#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET                                         0x0000000a
+#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB                                            0
+#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB                                            15
+#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK                                           0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET                                  0x0000000c
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB                                     0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB                                     15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK                                    0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET                                 0x0000000e
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET                                 0x00000010
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET                                 0x00000012
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET                                0x00000014
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET                                0x00000016
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET                                0x00000018
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET                                0x0000001a
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET                                 0x0000001c
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB                                    0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB                                    15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK                                   0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET                                0x0000001e
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET                                0x00000020
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET                                0x00000022
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET                                0x00000024
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB                                   0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB                                   15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK                                  0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET                              0x00000026
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB                                 0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB                                 15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK                                0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET                             0x00000028
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB                                0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB                                15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK                               0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET                             0x0000002a
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB                                0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB                                15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK                               0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET                             0x0000002c
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB                                0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB                                15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK                               0x0000ffff
+
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET                       0x0000002e
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB                          0
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB                          15
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK                         0x0000ffff
+
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET                      0x00000030
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB                         0
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB                         15
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK                        0x0000ffff
+
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET                      0x00000032
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB                         0
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB                         4
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK                        0x0000001f
+
+#define PHYTX_PKT_END_RESERVED_23_OFFSET                                            0x00000032
+#define PHYTX_PKT_END_RESERVED_23_LSB                                               5
+#define PHYTX_PKT_END_RESERVED_23_MSB                                               15
+#define PHYTX_PKT_END_RESERVED_23_MASK                                              0x0000ffe0
+
+#endif
diff --git a/hw/peach/v1/phytx_ppdu_header_info_request.h b/hw/peach/v1/phytx_ppdu_header_info_request.h
new file mode 100644
index 000000000000..c0d81901da84
--- /dev/null
+++ b/hw/peach/v1/phytx_ppdu_header_info_request.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
+#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
+
+#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2
+
+#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1
+
+struct phytx_ppdu_header_info_request {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint16_t request_type                                            :  5,
+                      reserved                                                : 11;
+             uint16_t tlv32_padding                                           : 16;
+#else
+             uint16_t reserved                                                : 11,
+                      request_type                                            :  5;
+             uint16_t tlv32_padding                                           : 16;
+#endif
+};
+
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET                          0x00000000
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB                             0
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB                             4
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK                            0x0000001f
+
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET                              0x00000000
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB                                 5
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB                                 15
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK                                0x0000ffe0
+
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET                         0x00000002
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB                            0
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB                            15
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK                           0x0000ffff
+
+#endif
diff --git a/hw/peach/v1/receive_pkt_start_info.h b/hw/peach/v1/receive_pkt_start_info.h
new file mode 100644
index 000000000000..d1c935cc6e72
--- /dev/null
+++ b/hw/peach/v1/receive_pkt_start_info.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVE_PKT_START_INFO_H_
+#define _RECEIVE_PKT_START_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4
+
+struct receive_pkt_start_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reception_type                                          :  4,
+                      rx_chain_mask_type                                      :  1,
+                      receive_bandwidth                                       :  3,
+                      rx_chain_mask                                           :  8,
+                      phy_ppdu_id                                             : 16;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t preamble_time_to_rxframe                                :  8,
+                      standalone_sniffer_mode                                 :  1,
+                      reserved_3a                                             : 23;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      rx_chain_mask                                           :  8,
+                      receive_bandwidth                                       :  3,
+                      rx_chain_mask_type                                      :  1,
+                      reception_type                                          :  4;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t reserved_3a                                             : 23,
+                      standalone_sniffer_mode                                 :  1,
+                      preamble_time_to_rxframe                                :  8;
+#endif
+};
+
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET                                0x00000000
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB                                   0
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB                                   3
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK                                  0x0000000f
+
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET                            0x00000000
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB                               4
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB                               4
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK                              0x00000010
+
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET                             0x00000000
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB                                5
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB                                7
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK                               0x000000e0
+
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET                                 0x00000000
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB                                    8
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB                                    15
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK                                   0x0000ff00
+
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET                                   0x00000000
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB                                      16
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB                                      31
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK                                     0xffff0000
+
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET                     0x00000004
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB                        0
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB                        31
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK                       0xffffffff
+
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET                    0x00000008
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB                       0
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB                       31
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK                      0xffffffff
+
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET                      0x0000000c
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB                         0
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB                         7
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK                        0x000000ff
+
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET                       0x0000000c
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB                          8
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB                          8
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK                         0x00000100
+
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET                                   0x0000000c
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB                                      9
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB                                      31
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK                                     0xfffffe00
+
+#endif
diff --git a/hw/peach/v1/receive_rssi_info.h b/hw/peach/v1/receive_rssi_info.h
new file mode 100644
index 000000000000..43fd1796f0eb
--- /dev/null
+++ b/hw/peach/v1/receive_rssi_info.h
@@ -0,0 +1,477 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVE_RSSI_INFO_H_
+#define _RECEIVE_RSSI_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16
+
+struct receive_rssi_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rssi_pri20_chain0                                       :  8,
+                      rssi_ext20_chain0                                       :  8,
+                      rssi_ext40_low20_chain0                                 :  8,
+                      rssi_ext40_high20_chain0                                :  8;
+             uint32_t rssi_ext80_low20_chain0                                 :  8,
+                      rssi_ext80_low_high20_chain0                            :  8,
+                      rssi_ext80_high_low20_chain0                            :  8,
+                      rssi_ext80_high20_chain0                                :  8;
+             uint32_t rssi_ext160_0_chain0                                    :  8,
+                      rssi_ext160_1_chain0                                    :  8,
+                      rssi_ext160_2_chain0                                    :  8,
+                      rssi_ext160_3_chain0                                    :  8;
+             uint32_t rssi_ext160_4_chain0                                    :  8,
+                      rssi_ext160_5_chain0                                    :  8,
+                      rssi_ext160_6_chain0                                    :  8,
+                      rssi_ext160_7_chain0                                    :  8;
+             uint32_t rssi_pri20_chain1                                       :  8,
+                      rssi_ext20_chain1                                       :  8,
+                      rssi_ext40_low20_chain1                                 :  8,
+                      rssi_ext40_high20_chain1                                :  8;
+             uint32_t rssi_ext80_low20_chain1                                 :  8,
+                      rssi_ext80_low_high20_chain1                            :  8,
+                      rssi_ext80_high_low20_chain1                            :  8,
+                      rssi_ext80_high20_chain1                                :  8;
+             uint32_t rssi_ext160_0_chain1                                    :  8,
+                      rssi_ext160_1_chain1                                    :  8,
+                      rssi_ext160_2_chain1                                    :  8,
+                      rssi_ext160_3_chain1                                    :  8;
+             uint32_t rssi_ext160_4_chain1                                    :  8,
+                      rssi_ext160_5_chain1                                    :  8,
+                      rssi_ext160_6_chain1                                    :  8,
+                      rssi_ext160_7_chain1                                    :  8;
+             uint32_t rssi_pri20_chain2                                       :  8,
+                      rssi_ext20_chain2                                       :  8,
+                      rssi_ext40_low20_chain2                                 :  8,
+                      rssi_ext40_high20_chain2                                :  8;
+             uint32_t rssi_ext80_low20_chain2                                 :  8,
+                      rssi_ext80_low_high20_chain2                            :  8,
+                      rssi_ext80_high_low20_chain2                            :  8,
+                      rssi_ext80_high20_chain2                                :  8;
+             uint32_t rssi_ext160_0_chain2                                    :  8,
+                      rssi_ext160_1_chain2                                    :  8,
+                      rssi_ext160_2_chain2                                    :  8,
+                      rssi_ext160_3_chain2                                    :  8;
+             uint32_t rssi_ext160_4_chain2                                    :  8,
+                      rssi_ext160_5_chain2                                    :  8,
+                      rssi_ext160_6_chain2                                    :  8,
+                      rssi_ext160_7_chain2                                    :  8;
+             uint32_t rssi_pri20_chain3                                       :  8,
+                      rssi_ext20_chain3                                       :  8,
+                      rssi_ext40_low20_chain3                                 :  8,
+                      rssi_ext40_high20_chain3                                :  8;
+             uint32_t rssi_ext80_low20_chain3                                 :  8,
+                      rssi_ext80_low_high20_chain3                            :  8,
+                      rssi_ext80_high_low20_chain3                            :  8,
+                      rssi_ext80_high20_chain3                                :  8;
+             uint32_t rssi_ext160_0_chain3                                    :  8,
+                      rssi_ext160_1_chain3                                    :  8,
+                      rssi_ext160_2_chain3                                    :  8,
+                      rssi_ext160_3_chain3                                    :  8;
+             uint32_t rssi_ext160_4_chain3                                    :  8,
+                      rssi_ext160_5_chain3                                    :  8,
+                      rssi_ext160_6_chain3                                    :  8,
+                      rssi_ext160_7_chain3                                    :  8;
+#else
+             uint32_t rssi_ext40_high20_chain0                                :  8,
+                      rssi_ext40_low20_chain0                                 :  8,
+                      rssi_ext20_chain0                                       :  8,
+                      rssi_pri20_chain0                                       :  8;
+             uint32_t rssi_ext80_high20_chain0                                :  8,
+                      rssi_ext80_high_low20_chain0                            :  8,
+                      rssi_ext80_low_high20_chain0                            :  8,
+                      rssi_ext80_low20_chain0                                 :  8;
+             uint32_t rssi_ext160_3_chain0                                    :  8,
+                      rssi_ext160_2_chain0                                    :  8,
+                      rssi_ext160_1_chain0                                    :  8,
+                      rssi_ext160_0_chain0                                    :  8;
+             uint32_t rssi_ext160_7_chain0                                    :  8,
+                      rssi_ext160_6_chain0                                    :  8,
+                      rssi_ext160_5_chain0                                    :  8,
+                      rssi_ext160_4_chain0                                    :  8;
+             uint32_t rssi_ext40_high20_chain1                                :  8,
+                      rssi_ext40_low20_chain1                                 :  8,
+                      rssi_ext20_chain1                                       :  8,
+                      rssi_pri20_chain1                                       :  8;
+             uint32_t rssi_ext80_high20_chain1                                :  8,
+                      rssi_ext80_high_low20_chain1                            :  8,
+                      rssi_ext80_low_high20_chain1                            :  8,
+                      rssi_ext80_low20_chain1                                 :  8;
+             uint32_t rssi_ext160_3_chain1                                    :  8,
+                      rssi_ext160_2_chain1                                    :  8,
+                      rssi_ext160_1_chain1                                    :  8,
+                      rssi_ext160_0_chain1                                    :  8;
+             uint32_t rssi_ext160_7_chain1                                    :  8,
+                      rssi_ext160_6_chain1                                    :  8,
+                      rssi_ext160_5_chain1                                    :  8,
+                      rssi_ext160_4_chain1                                    :  8;
+             uint32_t rssi_ext40_high20_chain2                                :  8,
+                      rssi_ext40_low20_chain2                                 :  8,
+                      rssi_ext20_chain2                                       :  8,
+                      rssi_pri20_chain2                                       :  8;
+             uint32_t rssi_ext80_high20_chain2                                :  8,
+                      rssi_ext80_high_low20_chain2                            :  8,
+                      rssi_ext80_low_high20_chain2                            :  8,
+                      rssi_ext80_low20_chain2                                 :  8;
+             uint32_t rssi_ext160_3_chain2                                    :  8,
+                      rssi_ext160_2_chain2                                    :  8,
+                      rssi_ext160_1_chain2                                    :  8,
+                      rssi_ext160_0_chain2                                    :  8;
+             uint32_t rssi_ext160_7_chain2                                    :  8,
+                      rssi_ext160_6_chain2                                    :  8,
+                      rssi_ext160_5_chain2                                    :  8,
+                      rssi_ext160_4_chain2                                    :  8;
+             uint32_t rssi_ext40_high20_chain3                                :  8,
+                      rssi_ext40_low20_chain3                                 :  8,
+                      rssi_ext20_chain3                                       :  8,
+                      rssi_pri20_chain3                                       :  8;
+             uint32_t rssi_ext80_high20_chain3                                :  8,
+                      rssi_ext80_high_low20_chain3                            :  8,
+                      rssi_ext80_low_high20_chain3                            :  8,
+                      rssi_ext80_low20_chain3                                 :  8;
+             uint32_t rssi_ext160_3_chain3                                    :  8,
+                      rssi_ext160_2_chain3                                    :  8,
+                      rssi_ext160_1_chain3                                    :  8,
+                      rssi_ext160_0_chain3                                    :  8;
+             uint32_t rssi_ext160_7_chain3                                    :  8,
+                      rssi_ext160_6_chain3                                    :  8,
+                      rssi_ext160_5_chain3                                    :  8,
+                      rssi_ext160_4_chain3                                    :  8;
+#endif
+};
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET                                  0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET                                  0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET                            0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET                           0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET                            0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET                       0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET                       0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET                           0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET                               0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET                               0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET                                  0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET                                  0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET                            0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET                           0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET                            0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET                       0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET                       0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET                           0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET                               0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET                               0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET                                  0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET                                  0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET                            0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET                           0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET                            0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET                       0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET                       0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET                           0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET                               0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET                               0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET                                  0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB                                     0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB                                     7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK                                    0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET                                  0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB                                     8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB                                     15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK                                    0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET                            0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB                               16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB                               23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK                              0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET                           0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET                            0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB                               0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB                               7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK                              0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET                       0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB                          8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB                          15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK                         0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET                       0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB                          16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB                          23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK                         0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET                           0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB                              24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB                              31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK                             0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET                               0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK                                 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB                                  0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB                                  7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK                                 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB                                  8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB                                  15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK                                 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB                                  16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB                                  23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK                                 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET                               0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB                                  24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB                                  31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK                                 0xff000000
+
+#endif
diff --git a/hw/peach/v1/receive_user_info.h b/hw/peach/v1/receive_user_info.h
new file mode 100644
index 000000000000..7ecc5e4232c4
--- /dev/null
+++ b/hw/peach/v1/receive_user_info.h
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVE_USER_INFO_H_
+#define _RECEIVE_USER_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8
+
+struct receive_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_ppdu_id                                             : 16,
+                      user_rssi                                               :  8,
+                      pkt_type                                                :  4,
+                      stbc                                                    :  1,
+                      reception_type                                          :  3;
+             uint32_t rate_mcs                                                :  4,
+                      sgi                                                     :  2,
+                      __reserved_g_0004                                          :  1,
+                      reserved_1a                                             :  1,
+                      mimo_ss_bitmap                                          :  8,
+                      receive_bandwidth                                       :  3,
+                      reserved_1b                                             :  5,
+                      dl_ofdma_user_index                                     :  8;
+             uint32_t dl_ofdma_content_channel                                :  1,
+                      reserved_2a                                             :  7,
+                      nss                                                     :  3,
+                      stream_offset                                           :  3,
+                      sta_dcm                                                 :  1,
+                      ldpc                                                    :  1,
+                      ru_type_80_0                                            :  4,
+                      ru_type_80_1                                            :  4,
+                      ru_type_80_2                                            :  4,
+                      ru_type_80_3                                            :  4;
+             uint32_t ru_start_index_80_0                                     :  6,
+                      reserved_3a                                             :  2,
+                      ru_start_index_80_1                                     :  6,
+                      reserved_3b                                             :  2,
+                      ru_start_index_80_2                                     :  6,
+                      reserved_3c                                             :  2,
+                      ru_start_index_80_3                                     :  6,
+                      reserved_3d                                             :  2;
+             uint32_t user_fd_rssi_seg0                                       : 32;
+             uint32_t user_fd_rssi_seg1                                       : 32;
+             uint32_t user_fd_rssi_seg2                                       : 32;
+             uint32_t user_fd_rssi_seg3                                       : 32;
+#else
+             uint32_t reception_type                                          :  3,
+                      stbc                                                    :  1,
+                      pkt_type                                                :  4,
+                      user_rssi                                               :  8,
+                      phy_ppdu_id                                             : 16;
+             uint32_t dl_ofdma_user_index                                     :  8,
+                      reserved_1b                                             :  5,
+                      receive_bandwidth                                       :  3,
+                      mimo_ss_bitmap                                          :  8,
+                      reserved_1a                                             :  1,
+                      __reserved_g_0004                                          :  1,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  4;
+             uint32_t ru_type_80_3                                            :  4,
+                      ru_type_80_2                                            :  4,
+                      ru_type_80_1                                            :  4,
+                      ru_type_80_0                                            :  4,
+                      ldpc                                                    :  1,
+                      sta_dcm                                                 :  1,
+                      stream_offset                                           :  3,
+                      nss                                                     :  3,
+                      reserved_2a                                             :  7,
+                      dl_ofdma_content_channel                                :  1;
+             uint32_t reserved_3d                                             :  2,
+                      ru_start_index_80_3                                     :  6,
+                      reserved_3c                                             :  2,
+                      ru_start_index_80_2                                     :  6,
+                      reserved_3b                                             :  2,
+                      ru_start_index_80_1                                     :  6,
+                      reserved_3a                                             :  2,
+                      ru_start_index_80_0                                     :  6;
+             uint32_t user_fd_rssi_seg0                                       : 32;
+             uint32_t user_fd_rssi_seg1                                       : 32;
+             uint32_t user_fd_rssi_seg2                                       : 32;
+             uint32_t user_fd_rssi_seg3                                       : 32;
+#endif
+};
+
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET                                        0x00000000
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB                                           0
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB                                           15
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK                                          0x0000ffff
+
+#define RECEIVE_USER_INFO_USER_RSSI_OFFSET                                          0x00000000
+#define RECEIVE_USER_INFO_USER_RSSI_LSB                                             16
+#define RECEIVE_USER_INFO_USER_RSSI_MSB                                             23
+#define RECEIVE_USER_INFO_USER_RSSI_MASK                                            0x00ff0000
+
+#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET                                           0x00000000
+#define RECEIVE_USER_INFO_PKT_TYPE_LSB                                              24
+#define RECEIVE_USER_INFO_PKT_TYPE_MSB                                              27
+#define RECEIVE_USER_INFO_PKT_TYPE_MASK                                             0x0f000000
+
+#define RECEIVE_USER_INFO_STBC_OFFSET                                               0x00000000
+#define RECEIVE_USER_INFO_STBC_LSB                                                  28
+#define RECEIVE_USER_INFO_STBC_MSB                                                  28
+#define RECEIVE_USER_INFO_STBC_MASK                                                 0x10000000
+
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET                                     0x00000000
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB                                        29
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB                                        31
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK                                       0xe0000000
+
+#define RECEIVE_USER_INFO_RATE_MCS_OFFSET                                           0x00000004
+#define RECEIVE_USER_INFO_RATE_MCS_LSB                                              0
+#define RECEIVE_USER_INFO_RATE_MCS_MSB                                              3
+#define RECEIVE_USER_INFO_RATE_MCS_MASK                                             0x0000000f
+
+#define RECEIVE_USER_INFO_SGI_OFFSET                                                0x00000004
+#define RECEIVE_USER_INFO_SGI_LSB                                                   4
+#define RECEIVE_USER_INFO_SGI_MSB                                                   5
+#define RECEIVE_USER_INFO_SGI_MASK                                                  0x00000030
+
+#define RECEIVE_USER_INFO_RESERVED_1A_OFFSET                                        0x00000004
+#define RECEIVE_USER_INFO_RESERVED_1A_LSB                                           7
+#define RECEIVE_USER_INFO_RESERVED_1A_MSB                                           7
+#define RECEIVE_USER_INFO_RESERVED_1A_MASK                                          0x00000080
+
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET                                     0x00000004
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB                                        8
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB                                        15
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK                                       0x0000ff00
+
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET                                  0x00000004
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB                                     16
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB                                     18
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK                                    0x00070000
+
+#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET                                        0x00000004
+#define RECEIVE_USER_INFO_RESERVED_1B_LSB                                           19
+#define RECEIVE_USER_INFO_RESERVED_1B_MSB                                           23
+#define RECEIVE_USER_INFO_RESERVED_1B_MASK                                          0x00f80000
+
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET                                0x00000004
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB                                   24
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB                                   31
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK                                  0xff000000
+
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET                           0x00000008
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB                              0
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB                              0
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK                             0x00000001
+
+#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET                                        0x00000008
+#define RECEIVE_USER_INFO_RESERVED_2A_LSB                                           1
+#define RECEIVE_USER_INFO_RESERVED_2A_MSB                                           7
+#define RECEIVE_USER_INFO_RESERVED_2A_MASK                                          0x000000fe
+
+#define RECEIVE_USER_INFO_NSS_OFFSET                                                0x00000008
+#define RECEIVE_USER_INFO_NSS_LSB                                                   8
+#define RECEIVE_USER_INFO_NSS_MSB                                                   10
+#define RECEIVE_USER_INFO_NSS_MASK                                                  0x00000700
+
+#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET                                      0x00000008
+#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB                                         11
+#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB                                         13
+#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK                                        0x00003800
+
+#define RECEIVE_USER_INFO_STA_DCM_OFFSET                                            0x00000008
+#define RECEIVE_USER_INFO_STA_DCM_LSB                                               14
+#define RECEIVE_USER_INFO_STA_DCM_MSB                                               14
+#define RECEIVE_USER_INFO_STA_DCM_MASK                                              0x00004000
+
+#define RECEIVE_USER_INFO_LDPC_OFFSET                                               0x00000008
+#define RECEIVE_USER_INFO_LDPC_LSB                                                  15
+#define RECEIVE_USER_INFO_LDPC_MSB                                                  15
+#define RECEIVE_USER_INFO_LDPC_MASK                                                 0x00008000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB                                          16
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB                                          19
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK                                         0x000f0000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB                                          20
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB                                          23
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK                                         0x00f00000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB                                          24
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB                                          27
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK                                         0x0f000000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET                                       0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB                                          28
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB                                          31
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK                                         0xf0000000
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB                                   0
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB                                   5
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK                                  0x0000003f
+
+#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3A_LSB                                           6
+#define RECEIVE_USER_INFO_RESERVED_3A_MSB                                           7
+#define RECEIVE_USER_INFO_RESERVED_3A_MASK                                          0x000000c0
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB                                   8
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB                                   13
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK                                  0x00003f00
+
+#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3B_LSB                                           14
+#define RECEIVE_USER_INFO_RESERVED_3B_MSB                                           15
+#define RECEIVE_USER_INFO_RESERVED_3B_MASK                                          0x0000c000
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB                                   16
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB                                   21
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK                                  0x003f0000
+
+#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3C_LSB                                           22
+#define RECEIVE_USER_INFO_RESERVED_3C_MSB                                           23
+#define RECEIVE_USER_INFO_RESERVED_3C_MASK                                          0x00c00000
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET                                0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB                                   24
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB                                   29
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK                                  0x3f000000
+
+#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET                                        0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3D_LSB                                           30
+#define RECEIVE_USER_INFO_RESERVED_3D_MSB                                           31
+#define RECEIVE_USER_INFO_RESERVED_3D_MASK                                          0xc0000000
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET                                  0x00000010
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK                                    0xffffffff
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET                                  0x00000014
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK                                    0xffffffff
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET                                  0x00000018
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK                                    0xffffffff
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET                                  0x0000001c
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB                                     0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB                                     31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK                                    0xffffffff
+
+#endif
diff --git a/hw/peach/v1/received_response_user_15_8.h b/hw/peach/v1/received_response_user_15_8.h
new file mode 100644
index 000000000000..bce76aff2a00
--- /dev/null
+++ b/hw/peach/v1/received_response_user_15_8.h
@@ -0,0 +1,1126 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_RESPONSE_USER_15_8_H_
+#define _RECEIVED_RESPONSE_USER_15_8_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64
+
+struct received_response_user_15_8 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user8;
+             struct   received_response_user_info                               received_response_details_user9;
+             struct   received_response_user_info                               received_response_details_user10;
+             struct   received_response_user_info                               received_response_details_user11;
+             struct   received_response_user_info                               received_response_details_user12;
+             struct   received_response_user_info                               received_response_details_user13;
+             struct   received_response_user_info                               received_response_details_user14;
+             struct   received_response_user_info                               received_response_details_user15;
+#else
+             struct   received_response_user_info                               received_response_details_user8;
+             struct   received_response_user_info                               received_response_details_user9;
+             struct   received_response_user_info                               received_response_details_user10;
+             struct   received_response_user_info                               received_response_details_user11;
+             struct   received_response_user_info                               received_response_details_user12;
+             struct   received_response_user_info                               received_response_details_user13;
+             struct   received_response_user_info                               received_response_details_user14;
+             struct   received_response_user_info                               received_response_details_user15;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x00000008
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB  0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB  31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET     0x0000000c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB        16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB        31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK       0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x00000028
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB  0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB  31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000002c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET     0x0000002c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB        16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB        31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK       0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x00000048
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000004c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET    0x0000004c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB       16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB       31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK      0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x00000068
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000006c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET    0x0000006c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB       16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB       31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK      0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x00000088
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000008c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET    0x0000008c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB       16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB       31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK      0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x000000a8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x000000ac
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET    0x000000ac
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB       16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB       31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK      0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x000000c8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x000000cc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET    0x000000cc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB       16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB       31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK      0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x000000e8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x000000ec
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET    0x000000ec
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB       16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB       31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK      0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#endif
diff --git a/hw/peach/v1/received_response_user_23_16.h b/hw/peach/v1/received_response_user_23_16.h
new file mode 100644
index 000000000000..ccd2d9191078
--- /dev/null
+++ b/hw/peach/v1/received_response_user_23_16.h
@@ -0,0 +1,1126 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_RESPONSE_USER_23_16_H_
+#define _RECEIVED_RESPONSE_USER_23_16_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64
+
+struct received_response_user_23_16 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user16;
+             struct   received_response_user_info                               received_response_details_user17;
+             struct   received_response_user_info                               received_response_details_user18;
+             struct   received_response_user_info                               received_response_details_user19;
+             struct   received_response_user_info                               received_response_details_user20;
+             struct   received_response_user_info                               received_response_details_user21;
+             struct   received_response_user_info                               received_response_details_user22;
+             struct   received_response_user_info                               received_response_details_user23;
+#else
+             struct   received_response_user_info                               received_response_details_user16;
+             struct   received_response_user_info                               received_response_details_user17;
+             struct   received_response_user_info                               received_response_details_user18;
+             struct   received_response_user_info                               received_response_details_user19;
+             struct   received_response_user_info                               received_response_details_user20;
+             struct   received_response_user_info                               received_response_details_user21;
+             struct   received_response_user_info                               received_response_details_user22;
+             struct   received_response_user_info                               received_response_details_user23;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x00000008
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET   0x0000000c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x00000028
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000002c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET   0x0000002c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x00000048
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000004c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET   0x0000004c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x00000068
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000006c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET   0x0000006c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x00000088
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000008c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET   0x0000008c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x000000a8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x000000ac
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET   0x000000ac
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x000000c8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x000000cc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET   0x000000cc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x000000e8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x000000ec
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET   0x000000ec
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#endif
diff --git a/hw/peach/v1/received_response_user_31_24.h b/hw/peach/v1/received_response_user_31_24.h
new file mode 100644
index 000000000000..81db62baa5da
--- /dev/null
+++ b/hw/peach/v1/received_response_user_31_24.h
@@ -0,0 +1,1126 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_RESPONSE_USER_31_24_H_
+#define _RECEIVED_RESPONSE_USER_31_24_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64
+
+struct received_response_user_31_24 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user24;
+             struct   received_response_user_info                               received_response_details_user25;
+             struct   received_response_user_info                               received_response_details_user26;
+             struct   received_response_user_info                               received_response_details_user27;
+             struct   received_response_user_info                               received_response_details_user28;
+             struct   received_response_user_info                               received_response_details_user29;
+             struct   received_response_user_info                               received_response_details_user30;
+             struct   received_response_user_info                               received_response_details_user31;
+#else
+             struct   received_response_user_info                               received_response_details_user24;
+             struct   received_response_user_info                               received_response_details_user25;
+             struct   received_response_user_info                               received_response_details_user26;
+             struct   received_response_user_info                               received_response_details_user27;
+             struct   received_response_user_info                               received_response_details_user28;
+             struct   received_response_user_info                               received_response_details_user29;
+             struct   received_response_user_info                               received_response_details_user30;
+             struct   received_response_user_info                               received_response_details_user31;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x00000008
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET   0x0000000c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x00000028
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000002c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET   0x0000002c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x00000048
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000004c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET   0x0000004c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x00000068
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000006c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET   0x0000006c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x00000088
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000008c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET   0x0000008c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x000000a8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x000000ac
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET   0x000000ac
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x000000c8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x000000cc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET   0x000000cc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x000000e8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x000000ec
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET   0x000000ec
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#endif
diff --git a/hw/peach/v1/received_response_user_36_32.h b/hw/peach/v1/received_response_user_36_32.h
new file mode 100644
index 000000000000..9ba8ee5d23e2
--- /dev/null
+++ b/hw/peach/v1/received_response_user_36_32.h
@@ -0,0 +1,715 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_RESPONSE_USER_36_32_H_
+#define _RECEIVED_RESPONSE_USER_36_32_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40
+
+struct received_response_user_36_32 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user32;
+             struct   received_response_user_info                               received_response_details_user33;
+             struct   received_response_user_info                               received_response_details_user34;
+             struct   received_response_user_info                               received_response_details_user35;
+             struct   received_response_user_info                               received_response_details_user36;
+#else
+             struct   received_response_user_info                               received_response_details_user32;
+             struct   received_response_user_info                               received_response_details_user33;
+             struct   received_response_user_info                               received_response_details_user34;
+             struct   received_response_user_info                               received_response_details_user35;
+             struct   received_response_user_info                               received_response_details_user36;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x00000008
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET   0x0000000c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x00000028
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000002c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET   0x0000002c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x00000048
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000004c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET   0x0000004c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x00000068
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000006c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET   0x0000006c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x00000088
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000008c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET   0x0000008c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB      16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB      31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK     0xffff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#endif
diff --git a/hw/peach/v1/received_response_user_7_0.h b/hw/peach/v1/received_response_user_7_0.h
new file mode 100644
index 000000000000..6b39f5cbea9d
--- /dev/null
+++ b/hw/peach/v1/received_response_user_7_0.h
@@ -0,0 +1,1126 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_RESPONSE_USER_7_0_H_
+#define _RECEIVED_RESPONSE_USER_7_0_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64
+
+struct received_response_user_7_0 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_response_user_info                               received_response_details_user0;
+             struct   received_response_user_info                               received_response_details_user1;
+             struct   received_response_user_info                               received_response_details_user2;
+             struct   received_response_user_info                               received_response_details_user3;
+             struct   received_response_user_info                               received_response_details_user4;
+             struct   received_response_user_info                               received_response_details_user5;
+             struct   received_response_user_info                               received_response_details_user6;
+             struct   received_response_user_info                               received_response_details_user7;
+#else
+             struct   received_response_user_info                               received_response_details_user0;
+             struct   received_response_user_info                               received_response_details_user1;
+             struct   received_response_user_info                               received_response_details_user2;
+             struct   received_response_user_info                               received_response_details_user3;
+             struct   received_response_user_info                               received_response_details_user4;
+             struct   received_response_user_info                               received_response_details_user5;
+             struct   received_response_user_info                               received_response_details_user6;
+             struct   received_response_user_info                               received_response_details_user7;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB  22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x00000008
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK  0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET      0x0000000c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB         16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB         31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK        0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB  22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x00000028
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK  0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000002c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET      0x0000002c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB         16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB         31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK        0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB  22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x00000048
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK  0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000004c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET      0x0000004c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB         16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB         31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK        0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB  22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x00000068
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK  0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000006c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET      0x0000006c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB         16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB         31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK        0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB  22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x00000088
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK  0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000008c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET      0x0000008c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB         16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB         31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK        0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB  22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x000000a8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK  0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x000000ac
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET      0x000000ac
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB         16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB         31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK        0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB  22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x000000c8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK  0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x000000cc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET      0x000000cc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB         16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB         31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK        0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB  28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB  22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB  30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x000000e8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB   0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB   31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK  0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x000000ec
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET      0x000000ec
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB         16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB         31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK        0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#endif
diff --git a/hw/peach/v1/received_response_user_info.h b/hw/peach/v1/received_response_user_info.h
new file mode 100644
index 000000000000..0f2676619a21
--- /dev/null
+++ b/hw/peach/v1/received_response_user_info.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_RESPONSE_USER_INFO_H_
+#define _RECEIVED_RESPONSE_USER_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8
+
+struct received_response_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mpdu_fcs_pass_count                                     : 12,
+                      mpdu_fcs_fail_count                                     : 12,
+                      qosnull_frame_count                                     :  4,
+                      reserved_0a                                             :  3,
+                      user_info_valid                                         :  1;
+             uint32_t null_delimiter_count                                    : 22,
+                      reserved_1a                                             :  9,
+                      ht_control_valid                                        :  1;
+             uint32_t ht_control                                              : 32;
+             uint32_t qos_control_valid                                       : 16,
+                      eosp                                                    : 16;
+             uint32_t qos_control_15_8_tid_0                                  :  8,
+                      qos_control_15_8_tid_1                                  :  8,
+                      qos_control_15_8_tid_2                                  :  8,
+                      qos_control_15_8_tid_3                                  :  8;
+             uint32_t qos_control_15_8_tid_4                                  :  8,
+                      qos_control_15_8_tid_5                                  :  8,
+                      qos_control_15_8_tid_6                                  :  8,
+                      qos_control_15_8_tid_7                                  :  8;
+             uint32_t qos_control_15_8_tid_8                                  :  8,
+                      qos_control_15_8_tid_9                                  :  8,
+                      qos_control_15_8_tid_10                                 :  8,
+                      qos_control_15_8_tid_11                                 :  8;
+             uint32_t qos_control_15_8_tid_12                                 :  8,
+                      qos_control_15_8_tid_13                                 :  8,
+                      qos_control_15_8_tid_14                                 :  8,
+                      qos_control_15_8_tid_15                                 :  8;
+#else
+             uint32_t user_info_valid                                         :  1,
+                      reserved_0a                                             :  3,
+                      qosnull_frame_count                                     :  4,
+                      mpdu_fcs_fail_count                                     : 12,
+                      mpdu_fcs_pass_count                                     : 12;
+             uint32_t ht_control_valid                                        :  1,
+                      reserved_1a                                             :  9,
+                      null_delimiter_count                                    : 22;
+             uint32_t ht_control                                              : 32;
+             uint32_t eosp                                                    : 16,
+                      qos_control_valid                                       : 16;
+             uint32_t qos_control_15_8_tid_3                                  :  8,
+                      qos_control_15_8_tid_2                                  :  8,
+                      qos_control_15_8_tid_1                                  :  8,
+                      qos_control_15_8_tid_0                                  :  8;
+             uint32_t qos_control_15_8_tid_7                                  :  8,
+                      qos_control_15_8_tid_6                                  :  8,
+                      qos_control_15_8_tid_5                                  :  8,
+                      qos_control_15_8_tid_4                                  :  8;
+             uint32_t qos_control_15_8_tid_11                                 :  8,
+                      qos_control_15_8_tid_10                                 :  8,
+                      qos_control_15_8_tid_9                                  :  8,
+                      qos_control_15_8_tid_8                                  :  8;
+             uint32_t qos_control_15_8_tid_15                                 :  8,
+                      qos_control_15_8_tid_14                                 :  8,
+                      qos_control_15_8_tid_13                                 :  8,
+                      qos_control_15_8_tid_12                                 :  8;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET                      0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB                         0
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB                         11
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK                        0x00000fff
+
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET                      0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB                         12
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB                         23
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK                        0x00fff000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET                      0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB                         24
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB                         27
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK                        0x0f000000
+
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET                              0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB                                 28
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB                                 30
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK                                0x70000000
+
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET                          0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB                             31
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB                             31
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK                            0x80000000
+
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET                     0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB                        0
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB                        21
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK                       0x003fffff
+
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET                              0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB                                 22
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB                                 30
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK                                0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET                         0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB                            31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB                            31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK                           0x80000000
+
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET                               0x00000008
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB                                  0
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB                                  31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK                                 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET                        0x0000000c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB                           0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB                           15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK                          0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET                                     0x0000000c
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB                                        16
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB                                        31
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK                                       0xffff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB                      0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB                      7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK                     0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB                      8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB                      15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK                     0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB                      16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB                      23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK                     0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET                   0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB                      24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB                      31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK                     0xff000000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB                      0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB                      7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK                     0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB                      8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB                      15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK                     0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB                      16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB                      23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK                     0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET                   0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB                      24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB                      31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK                     0xff000000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET                   0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB                      0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB                      7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK                     0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET                   0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB                      8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB                      15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK                     0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET                  0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB                     16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB                     23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK                    0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET                  0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB                     24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB                     31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK                    0xff000000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB                     0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB                     7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK                    0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB                     8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB                     15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK                    0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB                     16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB                     23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK                    0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET                  0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB                     24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB                     31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK                    0xff000000
+
+#endif
diff --git a/hw/peach/v1/received_trigger_info.h b/hw/peach/v1/received_trigger_info.h
new file mode 100644
index 000000000000..965dce76fbc4
--- /dev/null
+++ b/hw/peach/v1/received_trigger_info.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_TRIGGER_INFO_H_
+#define _RECEIVED_TRIGGER_INFO_H_
+
+#include "received_trigger_info_details.h"
+#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 5
+
+struct received_trigger_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   received_trigger_info_details                             received_trigger_details;
+#else
+             struct   received_trigger_info_details                             received_trigger_details;
+#endif
+};
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET          0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB             0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB             3
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK            0x0000000f
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET     0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB        4
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB        4
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK       0x00000010
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET       0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB          5
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB          8
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK         0x000001e0
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET   0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB      22
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB      22
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK     0x00400000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET     0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB        23
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB        23
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK       0x00800000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB    24
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB    24
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK   0x01000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB  25
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB  28
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_OFFSET     0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_LSB        29
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MSB        30
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MASK       0x60000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET           0x00000004
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB              0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB              15
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK             0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET  0x00000004
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB     16
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB     27
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK    0x0fff0000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET           0x00000004
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB              28
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB              31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK             0xf0000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET         0x00000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB            0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB            15
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK           0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET           0x00000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB              16
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB              31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK             0xffff0000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET            0x0000000c
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB               0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB               15
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK              0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET           0x0000000c
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB              25
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB              31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK             0xfe000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET            0x00000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB               0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB               31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK              0xffffffff
+
+#endif
diff --git a/hw/peach/v1/received_trigger_info_details.h b/hw/peach/v1/received_trigger_info_details.h
new file mode 100644
index 000000000000..b162adf0d8bc
--- /dev/null
+++ b/hw/peach/v1/received_trigger_info_details.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_
+#define _RECEIVED_TRIGGER_INFO_DETAILS_H_
+
+#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5
+
+struct received_trigger_info_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t trigger_type                                            :  4,
+                      ax_trigger_source                                       :  1,
+                      ax_trigger_type                                         :  4,
+                      trigger_source_sta_full_aid                             : 13,
+                      frame_control_valid                                     :  1,
+                      qos_control_valid                                       :  1,
+                      he_control_info_valid                                   :  1,
+                      __reserved_g_0005_trigger_subtype                                 :  4,
+                      txop_sharing_mode                                       :  2,
+                      tid_aggregation_limit_is_zero                           :  1;
+             uint32_t phy_ppdu_id                                             : 16,
+                      lsig_response_length                                    : 12,
+                      reserved_1a                                             :  4;
+             uint32_t frame_control                                           : 16,
+                      qos_control                                             : 16;
+             uint32_t sw_peer_id                                              : 16,
+                      txop_sharing_allocation_duration                        :  9,
+                      reserved_3a                                             :  7;
+             uint32_t he_control                                              : 32;
+#else
+             uint32_t tid_aggregation_limit_is_zero                           :  1,
+                      txop_sharing_mode                                       :  2,
+                      __reserved_g_0005_trigger_subtype                                 :  4,
+                      he_control_info_valid                                   :  1,
+                      qos_control_valid                                       :  1,
+                      frame_control_valid                                     :  1,
+                      trigger_source_sta_full_aid                             : 13,
+                      ax_trigger_type                                         :  4,
+                      ax_trigger_source                                       :  1,
+                      trigger_type                                            :  4;
+             uint32_t reserved_1a                                             :  4,
+                      lsig_response_length                                    : 12,
+                      phy_ppdu_id                                             : 16;
+             uint32_t qos_control                                             : 16,
+                      frame_control                                           : 16;
+             uint32_t reserved_3a                                             :  7,
+                      txop_sharing_allocation_duration                        :  9,
+                      sw_peer_id                                              : 16;
+             uint32_t he_control                                              : 32;
+#endif
+};
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET                           0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB                              0
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB                              3
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK                             0x0000000f
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET                      0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB                         4
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB                         4
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK                        0x00000010
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET                        0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB                           5
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB                           8
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK                          0x000001e0
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET            0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB               9
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB               21
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK              0x003ffe00
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET                    0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB                       22
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB                       22
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK                      0x00400000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET                      0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB                         23
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB                         23
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK                        0x00800000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET                  0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB                     24
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB                     24
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK                    0x01000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET                0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB                   25
+#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB                   28
+#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK                  0x1e000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET                      0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB                         29
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB                         30
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK                        0x60000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET          0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB             31
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB             31
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK            0x80000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET                            0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB                               0
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB                               15
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK                              0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET                   0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB                      16
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB                      27
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK                     0x0fff0000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET                            0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB                               28
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK                              0xf0000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET                          0x00000008
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB                             0
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB                             15
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK                            0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET                            0x00000008
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB                               16
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK                              0xffff0000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET                             0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB                                0
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB                                15
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK                               0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET       0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB          16
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB          24
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK         0x01ff0000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET                            0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB                               25
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB                               31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK                              0xfe000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET                             0x00000010
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB                                0
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB                                31
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK                               0xffffffff
+
+#endif
diff --git a/hw/peach/v1/reo_descriptor_threshold_reached_status.h b/hw/peach/v1/reo_descriptor_threshold_reached_status.h
new file mode 100644
index 000000000000..6c63c1dc0297
--- /dev/null
+++ b/hw/peach/v1/reo_descriptor_threshold_reached_status.h
@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 27
+
+struct reo_descriptor_threshold_reached_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tlv32_ring_padding                                      : 32;
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t threshold_index                                         :  2,
+                      reserved_2                                              : 30;
+             uint32_t link_descriptor_counter0                                : 24,
+                      reserved_3                                              :  8;
+             uint32_t link_descriptor_counter1                                : 24,
+                      reserved_4                                              :  8;
+             uint32_t link_descriptor_counter2                                : 24,
+                      reserved_5                                              :  8;
+             uint32_t link_descriptor_counter_sum                             : 26,
+                      reserved_6                                              :  6;
+             uint32_t reserved_7                                              : 32;
+             uint32_t reserved_8                                              : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t reserved_25a                                            : 28,
+                      looping_count                                           :  4;
+#else
+             uint32_t tlv32_ring_padding                                      : 32;
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2                                              : 30,
+                      threshold_index                                         :  2;
+             uint32_t reserved_3                                              :  8,
+                      link_descriptor_counter0                                : 24;
+             uint32_t reserved_4                                              :  8,
+                      link_descriptor_counter1                                : 24;
+             uint32_t reserved_5                                              :  8,
+                      link_descriptor_counter2                                : 24;
+             uint32_t reserved_6                                              :  6,
+                      link_descriptor_counter_sum                             : 26;
+             uint32_t reserved_7                                              : 32;
+             uint32_t reserved_8                                              : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_25a                                            : 28;
+#endif
+};
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_OFFSET           0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_LSB              0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_MSB              31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_MASK             0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET    0x00000004
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB       28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB       31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK      0xf0000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET      0x00000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB         0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB         31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK        0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET              0x0000000c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB                 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB                 1
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK                0x00000003
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET                   0x0000000c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB                      2
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB                      31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK                     0xfffffffc
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET     0x00000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB        0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB        23
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK       0x00ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET                   0x00000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB                      24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB                      31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK                     0xff000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET     0x00000014
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB        0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB        23
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK       0x00ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET                   0x00000014
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB                      24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB                      31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK                     0xff000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET     0x00000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB        0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB        23
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK       0x00ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET                   0x00000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB                      24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB                      31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK                     0xff000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET  0x0000001c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB     0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB     25
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK    0x03ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET                   0x0000001c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB                      26
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB                      31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK                     0xfc000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET                   0x00000020
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB                      0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB                      31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK                     0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET                   0x00000024
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB                      0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB                      31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK                     0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET                  0x00000028
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB                     0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB                     31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK                    0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET                 0x0000002c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK                   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET                 0x00000030
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK                   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET                 0x00000034
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK                   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET                 0x00000038
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK                   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET                 0x0000003c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK                   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET                 0x00000040
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK                   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET                 0x00000044
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK                   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET                 0x00000048
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK                   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET                 0x0000004c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK                   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET                 0x00000050
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK                   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET                 0x00000054
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK                   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET                 0x00000058
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK                   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET                 0x0000005c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK                   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET                 0x00000060
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK                   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET                 0x00000064
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB                    31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK                   0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET                 0x00000068
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB                    0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB                    27
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK                   0x0fffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET                0x00000068
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB                   28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB                   31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK                  0xf0000000
+
+#endif
diff --git a/hw/peach/v1/reo_destination_ring.h b/hw/peach/v1/reo_destination_ring.h
new file mode 100644
index 000000000000..fd54f690063d
--- /dev/null
+++ b/hw/peach/v1/reo_destination_ring.h
@@ -0,0 +1,275 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_DESTINATION_RING_H_
+#define _REO_DESTINATION_RING_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_REO_DESTINATION_RING 8
+
+struct reo_destination_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_or_link_desc_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t reo_dest_buffer_type                                    :  1,
+                      reo_push_reason                                         :  2,
+                      reo_error_code                                          :  5,
+                      captured_msdu_data_size                                 :  4,
+                      sw_exception                                            :  1,
+                      src_link_id                                             :  3,
+                      reo_destination_struct_signature                        :  4,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_or_link_desc_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reo_destination_struct_signature                        :  4,
+                      src_link_id                                             :  3,
+                      sw_exception                                            :  1,
+                      captured_msdu_data_size                                 :  4,
+                      reo_error_code                                          :  5,
+                      reo_push_reason                                         :  2,
+                      reo_dest_buffer_type                                    :  1;
+#endif
+};
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET     0x00000000
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB        0
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB        31
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK       0xffffffff
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET    0x00000004
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB       0
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB       7
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK      0x000000ff
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB   8
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB   11
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK  0x00000f00
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET     0x00000004
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB        12
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB        31
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK       0xfffff000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET            0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB               0
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB               7
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK              0x000000ff
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET         0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB            8
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB            8
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK           0x00000100
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET        0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB           9
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB           9
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK          0x00000200
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET            0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB               10
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB               10
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK              0x00000400
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET             0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB                11
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB                11
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK               0x00000800
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET              0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB                 13
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB                 13
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK                0x00002000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET    0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB       14
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB       14
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK      0x00004000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET              0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB                 15
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB                 26
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK                0x07ff8000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB   27
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB   27
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK  0x08000000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET                   0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB                      28
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB                      31
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK                     0xf0000000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET        0x0000000c
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB           0
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB           31
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK          0xffffffff
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB  0
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB  0
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB   1
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB   1
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK  0x00000002
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET     0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB        2
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB        2
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK       0x00000004
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET           0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB              3
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB              16
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK             0x0001fff8
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET             0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                17
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                17
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK               0x00020000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET           0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB              18
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB              18
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK             0x00040000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET           0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB              19
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB              19
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK             0x00080000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET            0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB               20
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB               20
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK              0x00100000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB    21
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB    21
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK   0x00200000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET   0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB      22
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB      22
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK     0x00400000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET        0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB           23
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB           23
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK          0x00800000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                    24
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                    24
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                   0x01000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                    25
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                    25
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                   0x02000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET             0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                26
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                26
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK               0x04000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET          0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB             27
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB             28
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK            0x18000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET          0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB             29
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB             30
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK            0x60000000
+
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_OFFSET                           0x00000014
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_LSB                              0
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MSB                              31
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MASK                             0xffffffff
+
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_OFFSET                          0x00000018
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_LSB                             0
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MSB                             31
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MASK                            0xffffffff
+
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET                            0x0000001c
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB                               0
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB                               0
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK                              0x00000001
+
+#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET                                 0x0000001c
+#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB                                    1
+#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB                                    2
+#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK                                   0x00000006
+
+#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET                                  0x0000001c
+#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB                                     3
+#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB                                     7
+#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK                                    0x000000f8
+
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET                         0x0000001c
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB                            8
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB                            11
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK                           0x00000f00
+
+#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET                                    0x0000001c
+#define REO_DESTINATION_RING_SW_EXCEPTION_LSB                                       12
+#define REO_DESTINATION_RING_SW_EXCEPTION_MSB                                       12
+#define REO_DESTINATION_RING_SW_EXCEPTION_MASK                                      0x00001000
+
+#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET                                     0x0000001c
+#define REO_DESTINATION_RING_SRC_LINK_ID_LSB                                        13
+#define REO_DESTINATION_RING_SRC_LINK_ID_MSB                                        15
+#define REO_DESTINATION_RING_SRC_LINK_ID_MASK                                       0x0000e000
+
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET                0x0000001c
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB                   16
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB                   19
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK                  0x000f0000
+
+#define REO_DESTINATION_RING_RING_ID_OFFSET                                         0x0000001c
+#define REO_DESTINATION_RING_RING_ID_LSB                                            20
+#define REO_DESTINATION_RING_RING_ID_MSB                                            27
+#define REO_DESTINATION_RING_RING_ID_MASK                                           0x0ff00000
+
+#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET                                   0x0000001c
+#define REO_DESTINATION_RING_LOOPING_COUNT_LSB                                      28
+#define REO_DESTINATION_RING_LOOPING_COUNT_MSB                                      31
+#define REO_DESTINATION_RING_LOOPING_COUNT_MASK                                     0xf0000000
+
+#endif
diff --git a/hw/peach/v1/reo_destination_ring_with_pn.h b/hw/peach/v1/reo_destination_ring_with_pn.h
new file mode 100644
index 000000000000..b8e162a8ab33
--- /dev/null
+++ b/hw/peach/v1/reo_destination_ring_with_pn.h
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_DESTINATION_RING_WITH_PN_H_
+#define _REO_DESTINATION_RING_WITH_PN_H_
+
+#include "rx_msdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8
+
+struct reo_destination_ring_with_pn {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_or_link_desc_addr_info;
+             uint32_t msdu_count                                              :  8,
+                      prev_pn_23_0                                            : 24;
+             uint32_t prev_pn_55_24                                           : 32;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t reo_dest_buffer_type                                    :  1,
+                      reo_push_reason                                         :  2,
+                      reo_error_code                                          :  5,
+                      captured_msdu_data_size                                 :  4,
+                      sw_exception                                            :  1,
+                      src_link_id                                             :  3,
+                      reo_destination_struct_signature                        :  4,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_or_link_desc_addr_info;
+             uint32_t prev_pn_23_0                                            : 24,
+                      msdu_count                                              :  8;
+             uint32_t prev_pn_55_24                                           : 32;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reo_destination_struct_signature                        :  4,
+                      src_link_id                                             :  3,
+                      sw_exception                                            :  1,
+                      captured_msdu_data_size                                 :  4,
+                      reo_error_code                                          :  5,
+                      reo_push_reason                                         :  2,
+                      reo_dest_buffer_type                                    :  1;
+#endif
+};
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET                              0x00000008
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB                                 0
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB                                 7
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK                                0x000000ff
+
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET                            0x00000008
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB                               8
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB                               31
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK                              0xffffff00
+
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_OFFSET                           0x0000000c
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_LSB                              0
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MSB                              31
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MASK                             0xffffffff
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET   0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB      3
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB      16
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK     0x0001fff8
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET     0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB        17
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB        17
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK       0x00020000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET   0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB      18
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB      18
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK     0x00040000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET   0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB      19
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB      19
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK     0x00080000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET    0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB       20
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB       20
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK      0x00100000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB   23
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB   23
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK  0x00800000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET         0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB            24
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB            24
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK           0x01000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET         0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB            25
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB            25
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK           0x02000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET     0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB        26
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB        26
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK       0x04000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET  0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB     27
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB     28
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK    0x18000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET  0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB     29
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB     30
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK    0x60000000
+
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_OFFSET                   0x00000014
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_LSB                      0
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MSB                      31
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MASK                     0xffffffff
+
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_OFFSET                  0x00000018
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_LSB                     0
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MSB                     31
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MASK                    0xffffffff
+
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET                    0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB                       0
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB                       0
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK                      0x00000001
+
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET                         0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB                            1
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB                            2
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK                           0x00000006
+
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET                          0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB                             3
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB                             7
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK                            0x000000f8
+
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET                 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB                    8
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB                    11
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK                   0x00000f00
+
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET                            0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB                               12
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB                               12
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK                              0x00001000
+
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET                             0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB                                13
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB                                15
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK                               0x0000e000
+
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET        0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB           16
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB           19
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK          0x000f0000
+
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET                                 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB                                    20
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB                                    27
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK                                   0x0ff00000
+
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET                           0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB                              28
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB                              31
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK                             0xf0000000
+
+#endif
diff --git a/hw/peach/v1/reo_entrance_ring.h b/hw/peach/v1/reo_entrance_ring.h
new file mode 100644
index 000000000000..c9c9df2bd53a
--- /dev/null
+++ b/hw/peach/v1/reo_entrance_ring.h
@@ -0,0 +1,252 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_ENTRANCE_RING_H_
+#define _REO_ENTRANCE_RING_H_
+
+#include "rx_mpdu_details.h"
+#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
+
+struct reo_entrance_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_mpdu_details                                           reo_level_mpdu_frame_info;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t rx_reo_queue_desc_addr_39_32                            :  8,
+                      rounded_mpdu_byte_count                                 : 14,
+                      reo_destination_indication                              :  5,
+                      frameless_bar                                           :  1,
+                      reserved_5a                                             :  4;
+             uint32_t rxdma_push_reason                                       :  2,
+                      rxdma_error_code                                        :  5,
+                      mpdu_fragment_number                                    :  4,
+                      sw_exception                                            :  1,
+                      sw_exception_mpdu_delink                                :  1,
+                      sw_exception_destination_ring_valid                     :  1,
+                      sw_exception_destination_ring                           :  5,
+                      mpdu_sequence_number                                    : 12,
+                      reserved_6a                                             :  1;
+             uint32_t phy_ppdu_id                                             : 16,
+                      src_link_id                                             :  3,
+                      reserved_7a                                             :  1,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   rx_mpdu_details                                           reo_level_mpdu_frame_info;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t reserved_5a                                             :  4,
+                      frameless_bar                                           :  1,
+                      reo_destination_indication                              :  5,
+                      rounded_mpdu_byte_count                                 : 14,
+                      rx_reo_queue_desc_addr_39_32                            :  8;
+             uint32_t reserved_6a                                             :  1,
+                      mpdu_sequence_number                                    : 12,
+                      sw_exception_destination_ring                           :  5,
+                      sw_exception_destination_ring_valid                     :  1,
+                      sw_exception_mpdu_delink                                :  1,
+                      sw_exception                                            :  1,
+                      mpdu_fragment_number                                    :  4,
+                      rxdma_error_code                                        :  5,
+                      rxdma_push_reason                                       :  2;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_7a                                             :  1,
+                      src_link_id                                             :  3,
+                      phy_ppdu_id                                             : 16;
+#endif
+};
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET                        0x00000010
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB                           0
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB                           31
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK                          0xffffffff
+
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET                       0x00000014
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB                          0
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB                          7
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK                         0x000000ff
+
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET                            0x00000014
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB                               8
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB                               21
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK                              0x003fff00
+
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET                         0x00000014
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB                            22
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB                            26
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK                           0x07c00000
+
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET                                      0x00000014
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB                                         27
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB                                         27
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK                                        0x08000000
+
+#define REO_ENTRANCE_RING_RESERVED_5A_OFFSET                                        0x00000014
+#define REO_ENTRANCE_RING_RESERVED_5A_LSB                                           28
+#define REO_ENTRANCE_RING_RESERVED_5A_MSB                                           31
+#define REO_ENTRANCE_RING_RESERVED_5A_MASK                                          0xf0000000
+
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET                                  0x00000018
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB                                     0
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB                                     1
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK                                    0x00000003
+
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET                                   0x00000018
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB                                      2
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB                                      6
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK                                     0x0000007c
+
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET                               0x00000018
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB                                  7
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB                                  10
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK                                 0x00000780
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET                                       0x00000018
+#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB                                          11
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB                                          11
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK                                         0x00000800
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET                           0x00000018
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB                              12
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB                              12
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK                             0x00001000
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET                0x00000018
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB                   13
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB                   13
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK                  0x00002000
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET                      0x00000018
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB                         14
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB                         18
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK                        0x0007c000
+
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET                               0x00000018
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB                                  19
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB                                  30
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK                                 0x7ff80000
+
+#define REO_ENTRANCE_RING_RESERVED_6A_OFFSET                                        0x00000018
+#define REO_ENTRANCE_RING_RESERVED_6A_LSB                                           31
+#define REO_ENTRANCE_RING_RESERVED_6A_MSB                                           31
+#define REO_ENTRANCE_RING_RESERVED_6A_MASK                                          0x80000000
+
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET                                        0x0000001c
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB                                           0
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB                                           15
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK                                          0x0000ffff
+
+#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET                                        0x0000001c
+#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB                                           16
+#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB                                           18
+#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK                                          0x00070000
+
+#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET                                        0x0000001c
+#define REO_ENTRANCE_RING_RESERVED_7A_LSB                                           19
+#define REO_ENTRANCE_RING_RESERVED_7A_MSB                                           19
+#define REO_ENTRANCE_RING_RESERVED_7A_MASK                                          0x00080000
+
+#define REO_ENTRANCE_RING_RING_ID_OFFSET                                            0x0000001c
+#define REO_ENTRANCE_RING_RING_ID_LSB                                               20
+#define REO_ENTRANCE_RING_RING_ID_MSB                                               27
+#define REO_ENTRANCE_RING_RING_ID_MASK                                              0x0ff00000
+
+#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET                                      0x0000001c
+#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB                                         28
+#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB                                         31
+#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK                                        0xf0000000
+
+#endif
diff --git a/hw/peach/v1/reo_flush_cache.h b/hw/peach/v1/reo_flush_cache.h
new file mode 100644
index 000000000000..1d6e09f51d6f
--- /dev/null
+++ b/hw/peach/v1/reo_flush_cache.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_FLUSH_CACHE_H_
+#define _REO_FLUSH_CACHE_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9
+
+struct reo_flush_cache {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t flush_addr_31_0                                         : 32;
+             uint32_t flush_addr_39_32                                        :  8,
+                      forward_all_mpdus_in_queue                              :  1,
+                      release_cache_block_index                               :  1,
+                      cache_block_resource_index                              :  2,
+                      flush_without_invalidate                                :  1,
+                      block_cache_usage_after_flush                           :  1,
+                      flush_entire_cache                                      :  1,
+                      flush_queue_1k_desc                                     :  1,
+                      reserved_2b                                             : 16;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+#else
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t flush_addr_31_0                                         : 32;
+             uint32_t reserved_2b                                             : 16,
+                      flush_queue_1k_desc                                     :  1,
+                      flush_entire_cache                                      :  1,
+                      block_cache_usage_after_flush                           :  1,
+                      flush_without_invalidate                                :  1,
+                      cache_block_resource_index                              :  2,
+                      release_cache_block_index                               :  1,
+                      forward_all_mpdus_in_queue                              :  1,
+                      flush_addr_39_32                                        :  8;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+#endif
+};
+
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                            0x00000000
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB                               0
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB                               15
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK                              0x0000ffff
+
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                       0x00000000
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                          16
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                          16
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                         0x00010000
+
+#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET                               0x00000000
+#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB                                  17
+#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB                                  31
+#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK                                 0xfffe0000
+
+#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET                                      0x00000004
+#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB                                         0
+#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB                                         31
+#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK                                        0xffffffff
+
+#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET                                     0x00000008
+#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB                                        0
+#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB                                        7
+#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK                                       0x000000ff
+
+#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET                           0x00000008
+#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB                              8
+#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB                              8
+#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK                             0x00000100
+
+#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET                            0x00000008
+#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB                               9
+#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB                               9
+#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK                              0x00000200
+
+#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET                           0x00000008
+#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB                              10
+#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB                              11
+#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK                             0x00000c00
+
+#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET                             0x00000008
+#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB                                12
+#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB                                12
+#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK                               0x00001000
+
+#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET                        0x00000008
+#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB                           13
+#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB                           13
+#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK                          0x00002000
+
+#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET                                   0x00000008
+#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB                                      14
+#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB                                      14
+#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK                                     0x00004000
+
+#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET                                  0x00000008
+#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB                                     15
+#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB                                     15
+#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK                                    0x00008000
+
+#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET                                          0x00000008
+#define REO_FLUSH_CACHE_RESERVED_2B_LSB                                             16
+#define REO_FLUSH_CACHE_RESERVED_2B_MSB                                             31
+#define REO_FLUSH_CACHE_RESERVED_2B_MASK                                            0xffff0000
+
+#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET                                          0x0000000c
+#define REO_FLUSH_CACHE_RESERVED_3A_LSB                                             0
+#define REO_FLUSH_CACHE_RESERVED_3A_MSB                                             31
+#define REO_FLUSH_CACHE_RESERVED_3A_MASK                                            0xffffffff
+
+#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET                                          0x00000010
+#define REO_FLUSH_CACHE_RESERVED_4A_LSB                                             0
+#define REO_FLUSH_CACHE_RESERVED_4A_MSB                                             31
+#define REO_FLUSH_CACHE_RESERVED_4A_MASK                                            0xffffffff
+
+#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET                                          0x00000014
+#define REO_FLUSH_CACHE_RESERVED_5A_LSB                                             0
+#define REO_FLUSH_CACHE_RESERVED_5A_MSB                                             31
+#define REO_FLUSH_CACHE_RESERVED_5A_MASK                                            0xffffffff
+
+#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET                                          0x00000018
+#define REO_FLUSH_CACHE_RESERVED_6A_LSB                                             0
+#define REO_FLUSH_CACHE_RESERVED_6A_MSB                                             31
+#define REO_FLUSH_CACHE_RESERVED_6A_MASK                                            0xffffffff
+
+#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET                                          0x0000001c
+#define REO_FLUSH_CACHE_RESERVED_7A_LSB                                             0
+#define REO_FLUSH_CACHE_RESERVED_7A_MSB                                             31
+#define REO_FLUSH_CACHE_RESERVED_7A_MASK                                            0xffffffff
+
+#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET                                          0x00000020
+#define REO_FLUSH_CACHE_RESERVED_8A_LSB                                             0
+#define REO_FLUSH_CACHE_RESERVED_8A_MSB                                             31
+#define REO_FLUSH_CACHE_RESERVED_8A_MASK                                            0xffffffff
+
+#endif
diff --git a/hw/peach/v1/reo_flush_cache_status.h b/hw/peach/v1/reo_flush_cache_status.h
new file mode 100644
index 000000000000..6f2716362cd4
--- /dev/null
+++ b/hw/peach/v1/reo_flush_cache_status.h
@@ -0,0 +1,302 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_FLUSH_CACHE_STATUS_H_
+#define _REO_FLUSH_CACHE_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 27
+
+struct reo_flush_cache_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tlv32_ring_padding                                      : 32;
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t error_detected                                          :  1,
+                      block_error_details                                     :  2,
+                      reserved_2a                                             :  5,
+                      cache_controller_flush_status_hit                       :  1,
+                      cache_controller_flush_status_desc_type                 :  3,
+                      cache_controller_flush_status_client_id                 :  4,
+                      cache_controller_flush_status_error                     :  2,
+                      cache_controller_flush_count                            :  8,
+                      flush_queue_1k_desc                                     :  1,
+                      reserved_2b                                             :  5;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t reserved_25a                                            : 28,
+                      looping_count                                           :  4;
+#else
+             uint32_t tlv32_ring_padding                                      : 32;
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2b                                             :  5,
+                      flush_queue_1k_desc                                     :  1,
+                      cache_controller_flush_count                            :  8,
+                      cache_controller_flush_status_error                     :  2,
+                      cache_controller_flush_status_client_id                 :  4,
+                      cache_controller_flush_status_desc_type                 :  3,
+                      cache_controller_flush_status_hit                       :  1,
+                      reserved_2a                                             :  5,
+                      block_error_details                                     :  2,
+                      error_detected                                          :  1;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_25a                                            : 28;
+#endif
+};
+
+#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_OFFSET                            0x00000000
+#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_LSB                               0
+#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_MSB                               31
+#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_MASK                              0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET               0x00000004
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB                  0
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB                  15
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK                 0x0000ffff
+
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET              0x00000004
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB                 16
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB                 25
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK                0x03ff0000
+
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET        0x00000004
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB           26
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB           27
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK          0x0c000000
+
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                     0x00000004
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                        28
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                        31
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK                       0xf0000000
+
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                       0x00000008
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                          0
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                          31
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                         0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET                                0x0000000c
+#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB                                   0
+#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB                                   0
+#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK                                  0x00000001
+
+#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET                           0x0000000c
+#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB                              1
+#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB                              2
+#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK                             0x00000006
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET                                   0x0000000c
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB                                      3
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB                                      7
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK                                     0x000000f8
+
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET             0x0000000c
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB                8
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB                8
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK               0x00000100
+
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET       0x0000000c
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB          9
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB          11
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK         0x00000e00
+
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET       0x0000000c
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB          12
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB          15
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK         0x0000f000
+
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET           0x0000000c
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB              16
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB              17
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK             0x00030000
+
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET                  0x0000000c
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB                     18
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB                     25
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK                    0x03fc0000
+
+#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET                           0x0000000c
+#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB                              26
+#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB                              26
+#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK                             0x04000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET                                   0x0000000c
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB                                      27
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB                                      31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK                                     0xf8000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET                                   0x00000010
+#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB                                      0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB                                      31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK                                     0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET                                   0x00000014
+#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB                                      0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB                                      31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK                                     0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET                                   0x00000018
+#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB                                      0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB                                      31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK                                     0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET                                   0x0000001c
+#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB                                      0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB                                      31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK                                     0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET                                   0x00000020
+#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB                                      0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB                                      31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK                                     0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET                                   0x00000024
+#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB                                      0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB                                      31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK                                     0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET                                   0x00000028
+#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB                                      0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB                                      31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK                                     0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET                                  0x0000002c
+#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK                                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET                                  0x00000030
+#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK                                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET                                  0x00000034
+#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK                                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET                                  0x00000038
+#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK                                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET                                  0x0000003c
+#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK                                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET                                  0x00000040
+#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK                                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET                                  0x00000044
+#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK                                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET                                  0x00000048
+#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK                                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET                                  0x0000004c
+#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK                                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET                                  0x00000050
+#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK                                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET                                  0x00000054
+#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK                                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET                                  0x00000058
+#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK                                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET                                  0x0000005c
+#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK                                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET                                  0x00000060
+#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK                                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET                                  0x00000064
+#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB                                     31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK                                    0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET                                  0x00000068
+#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB                                     0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB                                     27
+#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK                                    0x0fffffff
+
+#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET                                 0x00000068
+#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB                                    28
+#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB                                    31
+#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK                                   0xf0000000
+
+#endif
diff --git a/hw/peach/v1/reo_flush_queue.h b/hw/peach/v1/reo_flush_queue.h
new file mode 100644
index 000000000000..701a8546d33a
--- /dev/null
+++ b/hw/peach/v1/reo_flush_queue.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_FLUSH_QUEUE_H_
+#define _REO_FLUSH_QUEUE_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9
+
+struct reo_flush_queue {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t flush_desc_addr_31_0                                    : 32;
+             uint32_t flush_desc_addr_39_32                                   :  8,
+                      block_desc_addr_usage_after_flush                       :  1,
+                      block_resource_index                                    :  2,
+                      reserved_2a                                             : 21;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+#else
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t flush_desc_addr_31_0                                    : 32;
+             uint32_t reserved_2a                                             : 21,
+                      block_resource_index                                    :  2,
+                      block_desc_addr_usage_after_flush                       :  1,
+                      flush_desc_addr_39_32                                   :  8;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+#endif
+};
+
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                            0x00000000
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB                               0
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB                               15
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK                              0x0000ffff
+
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                       0x00000000
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                          16
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                          16
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                         0x00010000
+
+#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET                               0x00000000
+#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB                                  17
+#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB                                  31
+#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK                                 0xfffe0000
+
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET                                 0x00000004
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB                                    0
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB                                    31
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK                                   0xffffffff
+
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET                                0x00000008
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB                                   0
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB                                   7
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK                                  0x000000ff
+
+#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET                    0x00000008
+#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB                       8
+#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB                       8
+#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK                      0x00000100
+
+#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET                                 0x00000008
+#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB                                    9
+#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB                                    10
+#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK                                   0x00000600
+
+#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET                                          0x00000008
+#define REO_FLUSH_QUEUE_RESERVED_2A_LSB                                             11
+#define REO_FLUSH_QUEUE_RESERVED_2A_MSB                                             31
+#define REO_FLUSH_QUEUE_RESERVED_2A_MASK                                            0xfffff800
+
+#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET                                          0x0000000c
+#define REO_FLUSH_QUEUE_RESERVED_3A_LSB                                             0
+#define REO_FLUSH_QUEUE_RESERVED_3A_MSB                                             31
+#define REO_FLUSH_QUEUE_RESERVED_3A_MASK                                            0xffffffff
+
+#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET                                          0x00000010
+#define REO_FLUSH_QUEUE_RESERVED_4A_LSB                                             0
+#define REO_FLUSH_QUEUE_RESERVED_4A_MSB                                             31
+#define REO_FLUSH_QUEUE_RESERVED_4A_MASK                                            0xffffffff
+
+#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET                                          0x00000014
+#define REO_FLUSH_QUEUE_RESERVED_5A_LSB                                             0
+#define REO_FLUSH_QUEUE_RESERVED_5A_MSB                                             31
+#define REO_FLUSH_QUEUE_RESERVED_5A_MASK                                            0xffffffff
+
+#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET                                          0x00000018
+#define REO_FLUSH_QUEUE_RESERVED_6A_LSB                                             0
+#define REO_FLUSH_QUEUE_RESERVED_6A_MSB                                             31
+#define REO_FLUSH_QUEUE_RESERVED_6A_MASK                                            0xffffffff
+
+#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET                                          0x0000001c
+#define REO_FLUSH_QUEUE_RESERVED_7A_LSB                                             0
+#define REO_FLUSH_QUEUE_RESERVED_7A_MSB                                             31
+#define REO_FLUSH_QUEUE_RESERVED_7A_MASK                                            0xffffffff
+
+#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET                                          0x00000020
+#define REO_FLUSH_QUEUE_RESERVED_8A_LSB                                             0
+#define REO_FLUSH_QUEUE_RESERVED_8A_MSB                                             31
+#define REO_FLUSH_QUEUE_RESERVED_8A_MASK                                            0xffffffff
+
+#endif
diff --git a/hw/peach/v1/reo_flush_queue_status.h b/hw/peach/v1/reo_flush_queue_status.h
new file mode 100644
index 000000000000..51490730c058
--- /dev/null
+++ b/hw/peach/v1/reo_flush_queue_status.h
@@ -0,0 +1,246 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_FLUSH_QUEUE_STATUS_H_
+#define _REO_FLUSH_QUEUE_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 27
+
+struct reo_flush_queue_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tlv32_ring_padding                                      : 32;
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t error_detected                                          :  1,
+                      reserved_2a                                             : 31;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t reserved_25a                                            : 28,
+                      looping_count                                           :  4;
+#else
+             uint32_t tlv32_ring_padding                                      : 32;
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2a                                             : 31,
+                      error_detected                                          :  1;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_25a                                            : 28;
+#endif
+};
+
+#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_OFFSET                            0x00000000
+#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_LSB                               0
+#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_MSB                               31
+#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_MASK                              0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET               0x00000004
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB                  0
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB                  15
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK                 0x0000ffff
+
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET              0x00000004
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB                 16
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB                 25
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK                0x03ff0000
+
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET        0x00000004
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB           26
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB           27
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK          0x0c000000
+
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                     0x00000004
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                        28
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                        31
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK                       0xf0000000
+
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                       0x00000008
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                          0
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                          31
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                         0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET                                0x0000000c
+#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB                                   0
+#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB                                   0
+#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK                                  0x00000001
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET                                   0x0000000c
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB                                      1
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB                                      31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK                                     0xfffffffe
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET                                   0x00000010
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB                                      0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB                                      31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK                                     0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET                                   0x00000014
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB                                      0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB                                      31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK                                     0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET                                   0x00000018
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB                                      0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB                                      31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK                                     0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET                                   0x0000001c
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB                                      0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB                                      31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK                                     0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET                                   0x00000020
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB                                      0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB                                      31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK                                     0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET                                   0x00000024
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB                                      0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB                                      31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK                                     0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET                                   0x00000028
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB                                      0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB                                      31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK                                     0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET                                  0x0000002c
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK                                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET                                  0x00000030
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK                                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET                                  0x00000034
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK                                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET                                  0x00000038
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK                                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET                                  0x0000003c
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK                                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET                                  0x00000040
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK                                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET                                  0x00000044
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK                                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET                                  0x00000048
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK                                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET                                  0x0000004c
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK                                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET                                  0x00000050
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK                                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET                                  0x00000054
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK                                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET                                  0x00000058
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK                                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET                                  0x0000005c
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK                                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET                                  0x00000060
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK                                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET                                  0x00000064
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB                                     31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK                                    0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET                                  0x00000068
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB                                     0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB                                     27
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK                                    0x0fffffff
+
+#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET                                 0x00000068
+#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB                                    28
+#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB                                    31
+#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK                                   0xf0000000
+
+#endif
diff --git a/hw/peach/v1/reo_flush_timeout_list.h b/hw/peach/v1/reo_flush_timeout_list.h
new file mode 100644
index 000000000000..02a307a3c189
--- /dev/null
+++ b/hw/peach/v1/reo_flush_timeout_list.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
+#define _REO_FLUSH_TIMEOUT_LIST_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9
+
+struct reo_flush_timeout_list {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t ac_timout_list                                          :  2,
+                      reserved_1                                              : 30;
+             uint32_t minimum_release_desc_count                              : 16,
+                      minimum_forward_buf_count                               : 16;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+#else
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t reserved_1                                              : 30,
+                      ac_timout_list                                          :  2;
+             uint32_t minimum_forward_buf_count                               : 16,
+                      minimum_release_desc_count                              : 16;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+#endif
+};
+
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET                     0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB                        0
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB                        15
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK                       0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB                   16
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB                   16
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK                  0x00010000
+
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET                        0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB                           17
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB                           31
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK                          0xfffe0000
+
+#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET                                0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB                                   0
+#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB                                   1
+#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK                                  0x00000003
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET                                    0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB                                       2
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB                                       31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK                                      0xfffffffc
+
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET                    0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB                       0
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB                       15
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK                      0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET                     0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB                        16
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB                        31
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK                       0xffff0000
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET                                   0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB                                      0
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB                                      31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK                                     0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET                                   0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB                                      0
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB                                      31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK                                     0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET                                   0x00000014
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB                                      0
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB                                      31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK                                     0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET                                   0x00000018
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB                                      0
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB                                      31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK                                     0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET                                   0x0000001c
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB                                      0
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB                                      31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK                                     0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET                                   0x00000020
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB                                      0
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB                                      31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK                                     0xffffffff
+
+#endif
diff --git a/hw/peach/v1/reo_flush_timeout_list_status.h b/hw/peach/v1/reo_flush_timeout_list_status.h
new file mode 100644
index 000000000000..0bb7d402cd66
--- /dev/null
+++ b/hw/peach/v1/reo_flush_timeout_list_status.h
@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 27
+
+struct reo_flush_timeout_list_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tlv32_ring_padding                                      : 32;
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t error_detected                                          :  1,
+                      timout_list_empty                                       :  1,
+                      reserved_2a                                             : 30;
+             uint32_t release_desc_count                                      : 16,
+                      forward_buf_count                                       : 16;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t reserved_25a                                            : 28,
+                      looping_count                                           :  4;
+#else
+             uint32_t tlv32_ring_padding                                      : 32;
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2a                                             : 30,
+                      timout_list_empty                                       :  1,
+                      error_detected                                          :  1;
+             uint32_t forward_buf_count                                       : 16,
+                      release_desc_count                                      : 16;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_25a                                            : 28;
+#endif
+};
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_OFFSET                     0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_LSB                        0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_MSB                        31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_MASK                       0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET        0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB           0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB           15
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK          0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET       0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB          16
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB          25
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK         0x03ff0000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB    26
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB    27
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK   0x0c000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET              0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB                 28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB                 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK                0xf0000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB                   0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB                   31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK                  0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET                         0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB                            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB                            0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK                           0x00000001
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET                      0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB                         1
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB                         1
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK                        0x00000002
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET                            0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB                               2
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB                               31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK                              0xfffffffc
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET                     0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB                        0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB                        15
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK                       0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET                      0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB                         16
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB                         31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK                        0xffff0000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET                            0x00000014
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB                               0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB                               31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK                              0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET                            0x00000018
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB                               0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB                               31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK                              0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET                            0x0000001c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB                               0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB                               31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK                              0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET                            0x00000020
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB                               0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB                               31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK                              0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET                            0x00000024
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB                               0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB                               31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK                              0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET                            0x00000028
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB                               0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB                               31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK                              0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET                           0x0000002c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK                             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET                           0x00000030
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK                             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET                           0x00000034
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK                             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET                           0x00000038
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK                             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET                           0x0000003c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK                             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET                           0x00000040
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK                             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET                           0x00000044
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK                             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET                           0x00000048
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK                             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET                           0x0000004c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK                             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET                           0x00000050
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK                             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET                           0x00000054
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK                             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET                           0x00000058
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK                             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET                           0x0000005c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK                             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET                           0x00000060
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK                             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET                           0x00000064
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB                              31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK                             0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET                           0x00000068
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB                              0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB                              27
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK                             0x0fffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET                          0x00000068
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB                             28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB                             31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK                            0xf0000000
+
+#endif
diff --git a/hw/peach/v1/reo_get_queue_stats.h b/hw/peach/v1/reo_get_queue_stats.h
new file mode 100644
index 000000000000..6fff523c04a5
--- /dev/null
+++ b/hw/peach/v1/reo_get_queue_stats.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_GET_QUEUE_STATS_H_
+#define _REO_GET_QUEUE_STATS_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9
+
+struct reo_get_queue_stats {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t rx_reo_queue_desc_addr_39_32                            :  8,
+                      clear_stats                                             :  1,
+                      reserved_2a                                             : 23;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+#else
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t reserved_2a                                             : 23,
+                      clear_stats                                             :  1,
+                      rx_reo_queue_desc_addr_39_32                            :  8;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+#endif
+};
+
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET                        0x00000000
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB                           0
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB                           15
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK                          0x0000ffff
+
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                   0x00000000
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB                      16
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB                      16
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK                     0x00010000
+
+#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET                           0x00000000
+#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB                              17
+#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB                              31
+#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK                             0xfffe0000
+
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET                      0x00000004
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB                         0
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB                         31
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK                        0xffffffff
+
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET                     0x00000008
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB                        0
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB                        7
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK                       0x000000ff
+
+#define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET                                      0x00000008
+#define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB                                         8
+#define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB                                         8
+#define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK                                        0x00000100
+
+#define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET                                      0x00000008
+#define REO_GET_QUEUE_STATS_RESERVED_2A_LSB                                         9
+#define REO_GET_QUEUE_STATS_RESERVED_2A_MSB                                         31
+#define REO_GET_QUEUE_STATS_RESERVED_2A_MASK                                        0xfffffe00
+
+#define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET                                      0x0000000c
+#define REO_GET_QUEUE_STATS_RESERVED_3A_LSB                                         0
+#define REO_GET_QUEUE_STATS_RESERVED_3A_MSB                                         31
+#define REO_GET_QUEUE_STATS_RESERVED_3A_MASK                                        0xffffffff
+
+#define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET                                      0x00000010
+#define REO_GET_QUEUE_STATS_RESERVED_4A_LSB                                         0
+#define REO_GET_QUEUE_STATS_RESERVED_4A_MSB                                         31
+#define REO_GET_QUEUE_STATS_RESERVED_4A_MASK                                        0xffffffff
+
+#define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET                                      0x00000014
+#define REO_GET_QUEUE_STATS_RESERVED_5A_LSB                                         0
+#define REO_GET_QUEUE_STATS_RESERVED_5A_MSB                                         31
+#define REO_GET_QUEUE_STATS_RESERVED_5A_MASK                                        0xffffffff
+
+#define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET                                      0x00000018
+#define REO_GET_QUEUE_STATS_RESERVED_6A_LSB                                         0
+#define REO_GET_QUEUE_STATS_RESERVED_6A_MSB                                         31
+#define REO_GET_QUEUE_STATS_RESERVED_6A_MASK                                        0xffffffff
+
+#define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET                                      0x0000001c
+#define REO_GET_QUEUE_STATS_RESERVED_7A_LSB                                         0
+#define REO_GET_QUEUE_STATS_RESERVED_7A_MSB                                         31
+#define REO_GET_QUEUE_STATS_RESERVED_7A_MASK                                        0xffffffff
+
+#define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET                                      0x00000020
+#define REO_GET_QUEUE_STATS_RESERVED_8A_LSB                                         0
+#define REO_GET_QUEUE_STATS_RESERVED_8A_MSB                                         31
+#define REO_GET_QUEUE_STATS_RESERVED_8A_MASK                                        0xffffffff
+
+#endif
diff --git a/hw/peach/v1/reo_get_queue_stats_status.h b/hw/peach/v1/reo_get_queue_stats_status.h
new file mode 100644
index 000000000000..b80815d0d748
--- /dev/null
+++ b/hw/peach/v1/reo_get_queue_stats_status.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_GET_QUEUE_STATS_STATUS_H_
+#define _REO_GET_QUEUE_STATS_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 27
+
+struct reo_get_queue_stats_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tlv32_ring_padding                                      : 32;
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t ssn                                                     : 12,
+                      current_index                                           : 10,
+                      reserved_2                                              : 10;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t last_rx_enqueue_timestamp                               : 32;
+             uint32_t last_rx_dequeue_timestamp                               : 32;
+             uint32_t rx_bitmap_31_0                                          : 32;
+             uint32_t rx_bitmap_63_32                                         : 32;
+             uint32_t rx_bitmap_95_64                                         : 32;
+             uint32_t rx_bitmap_127_96                                        : 32;
+             uint32_t rx_bitmap_159_128                                       : 32;
+             uint32_t rx_bitmap_191_160                                       : 32;
+             uint32_t rx_bitmap_223_192                                       : 32;
+             uint32_t rx_bitmap_255_224                                       : 32;
+             uint32_t rx_bitmap_287_256                                       : 32;
+             uint32_t current_mpdu_count                                      :  7,
+                      current_msdu_count                                      : 25;
+             uint32_t window_jump_2k                                          :  4,
+                      timeout_count                                           :  6,
+                      forward_due_to_bar_count                                :  6,
+                      duplicate_count                                         : 16;
+             uint32_t frames_in_order_count                                   : 24,
+                      bar_received_count                                      :  8;
+             uint32_t mpdu_frames_processed_count                             : 32;
+             uint32_t msdu_frames_processed_count                             : 32;
+             uint32_t total_processed_byte_count                              : 32;
+             uint32_t late_receive_mpdu_count                                 : 12,
+                      hole_count                                              : 16,
+                      get_queue_1k_stats_status_to_follow                     :  1,
+                      reserved_24a                                            :  3;
+             uint32_t aging_drop_mpdu_count                                   : 16,
+                      aging_drop_interval                                     :  8,
+                      reserved_25a                                            :  4,
+                      looping_count                                           :  4;
+#else
+             uint32_t tlv32_ring_padding                                      : 32;
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2                                              : 10,
+                      current_index                                           : 10,
+                      ssn                                                     : 12;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t last_rx_enqueue_timestamp                               : 32;
+             uint32_t last_rx_dequeue_timestamp                               : 32;
+             uint32_t rx_bitmap_31_0                                          : 32;
+             uint32_t rx_bitmap_63_32                                         : 32;
+             uint32_t rx_bitmap_95_64                                         : 32;
+             uint32_t rx_bitmap_127_96                                        : 32;
+             uint32_t rx_bitmap_159_128                                       : 32;
+             uint32_t rx_bitmap_191_160                                       : 32;
+             uint32_t rx_bitmap_223_192                                       : 32;
+             uint32_t rx_bitmap_255_224                                       : 32;
+             uint32_t rx_bitmap_287_256                                       : 32;
+             uint32_t current_msdu_count                                      : 25,
+                      current_mpdu_count                                      :  7;
+             uint32_t duplicate_count                                         : 16,
+                      forward_due_to_bar_count                                :  6,
+                      timeout_count                                           :  6,
+                      window_jump_2k                                          :  4;
+             uint32_t bar_received_count                                      :  8,
+                      frames_in_order_count                                   : 24;
+             uint32_t mpdu_frames_processed_count                             : 32;
+             uint32_t msdu_frames_processed_count                             : 32;
+             uint32_t total_processed_byte_count                              : 32;
+             uint32_t reserved_24a                                            :  3,
+                      get_queue_1k_stats_status_to_follow                     :  1,
+                      hole_count                                              : 16,
+                      late_receive_mpdu_count                                 : 12;
+             uint32_t looping_count                                           :  4,
+                      reserved_25a                                            :  4,
+                      aging_drop_interval                                     :  8,
+                      aging_drop_mpdu_count                                   : 16;
+#endif
+};
+
+#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_OFFSET                        0x00000000
+#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_LSB                           0
+#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_MSB                           31
+#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_MASK                          0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET           0x00000004
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB              0
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB              15
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK             0x0000ffff
+
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET          0x00000004
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB             16
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB             25
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK            0x03ff0000
+
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET    0x00000004
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB       26
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB       27
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK      0x0c000000
+
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                 0x00000004
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_LSB                    28
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MSB                    31
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MASK                   0xf0000000
+
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                   0x00000008
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_LSB                      0
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MSB                      31
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MASK                     0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_SSN_OFFSET                                       0x0000000c
+#define REO_GET_QUEUE_STATS_STATUS_SSN_LSB                                          0
+#define REO_GET_QUEUE_STATS_STATUS_SSN_MSB                                          11
+#define REO_GET_QUEUE_STATS_STATUS_SSN_MASK                                         0x00000fff
+
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_OFFSET                             0x0000000c
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_LSB                                12
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MSB                                21
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MASK                               0x003ff000
+
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_OFFSET                                0x0000000c
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_LSB                                   22
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MSB                                   31
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MASK                                  0xffc00000
+
+#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_OFFSET                                   0x00000010
+#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_LSB                                      0
+#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MSB                                      31
+#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MASK                                     0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_OFFSET                                  0x00000014
+#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_LSB                                     0
+#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MSB                                     31
+#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MASK                                    0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_OFFSET                                  0x00000018
+#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_LSB                                     0
+#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MSB                                     31
+#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MASK                                    0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_OFFSET                                 0x0000001c
+#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_LSB                                    0
+#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MSB                                    31
+#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MASK                                   0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET                 0x00000020
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_LSB                    0
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MSB                    31
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MASK                   0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET                 0x00000024
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_LSB                    0
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MSB                    31
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MASK                   0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_OFFSET                            0x00000028
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_LSB                               0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MSB                               31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MASK                              0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_OFFSET                           0x0000002c
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_LSB                              0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MSB                              31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MASK                             0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_OFFSET                           0x00000030
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_LSB                              0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MSB                              31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MASK                             0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_OFFSET                          0x00000034
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_LSB                             0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MSB                             31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MASK                            0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_OFFSET                         0x00000038
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_LSB                            0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MSB                            31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MASK                           0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_OFFSET                         0x0000003c
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_LSB                            0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MSB                            31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MASK                           0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_OFFSET                         0x00000040
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_LSB                            0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MSB                            31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MASK                           0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_OFFSET                         0x00000044
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_LSB                            0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MSB                            31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MASK                           0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_OFFSET                         0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_LSB                            0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MSB                            31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MASK                           0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_OFFSET                        0x0000004c
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_LSB                           0
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MSB                           6
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MASK                          0x0000007f
+
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_OFFSET                        0x0000004c
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_LSB                           7
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MSB                           31
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MASK                          0xffffff80
+
+#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_OFFSET                            0x00000050
+#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_LSB                               0
+#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MSB                               3
+#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MASK                              0x0000000f
+
+#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_OFFSET                             0x00000050
+#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_LSB                                4
+#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MSB                                9
+#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MASK                               0x000003f0
+
+#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_OFFSET                  0x00000050
+#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_LSB                     10
+#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MSB                     15
+#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MASK                    0x0000fc00
+
+#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_OFFSET                           0x00000050
+#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_LSB                              16
+#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MSB                              31
+#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MASK                             0xffff0000
+
+#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_OFFSET                     0x00000054
+#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_LSB                        0
+#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MSB                        23
+#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MASK                       0x00ffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_OFFSET                        0x00000054
+#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_LSB                           24
+#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MSB                           31
+#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MASK                          0xff000000
+
+#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_OFFSET               0x00000058
+#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_LSB                  0
+#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MSB                  31
+#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MASK                 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_OFFSET               0x0000005c
+#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_LSB                  0
+#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MSB                  31
+#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MASK                 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_OFFSET                0x00000060
+#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_LSB                   0
+#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MSB                   31
+#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MASK                  0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_OFFSET                   0x00000064
+#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_LSB                      0
+#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MSB                      11
+#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MASK                     0x00000fff
+
+#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_OFFSET                                0x00000064
+#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_LSB                                   12
+#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MSB                                   27
+#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MASK                                  0x0ffff000
+
+#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_OFFSET       0x00000064
+#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_LSB          28
+#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MSB          28
+#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MASK         0x10000000
+
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_OFFSET                              0x00000064
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_LSB                                 29
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MSB                                 31
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MASK                                0xe0000000
+
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_OFFSET                     0x00000068
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_LSB                        0
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MSB                        15
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MASK                       0x0000ffff
+
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_OFFSET                       0x00000068
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_LSB                          16
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MSB                          23
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MASK                         0x00ff0000
+
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_OFFSET                              0x00000068
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_LSB                                 24
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MSB                                 27
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MASK                                0x0f000000
+
+#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_OFFSET                             0x00000068
+#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_LSB                                28
+#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MSB                                31
+#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MASK                               0xf0000000
+
+#endif
diff --git a/hw/peach/v1/reo_unblock_cache.h b/hw/peach/v1/reo_unblock_cache.h
new file mode 100644
index 000000000000..b3dd68876515
--- /dev/null
+++ b/hw/peach/v1/reo_unblock_cache.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_UNBLOCK_CACHE_H_
+#define _REO_UNBLOCK_CACHE_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9
+
+struct reo_unblock_cache {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t unblock_type                                            :  1,
+                      cache_block_resource_index                              :  2,
+                      reserved_1a                                             : 29;
+             uint32_t reserved_2a                                             : 32;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+#else
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t reserved_1a                                             : 29,
+                      cache_block_resource_index                              :  2,
+                      unblock_type                                            :  1;
+             uint32_t reserved_2a                                             : 32;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+#endif
+};
+
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                          0x00000000
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB                             0
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB                             15
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK                            0x0000ffff
+
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                     0x00000000
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                        16
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                        16
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                       0x00010000
+
+#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET                             0x00000000
+#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB                                17
+#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB                                31
+#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK                               0xfffe0000
+
+#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET                                       0x00000004
+#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB                                          0
+#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB                                          0
+#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK                                         0x00000001
+
+#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET                         0x00000004
+#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB                            1
+#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB                            2
+#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK                           0x00000006
+
+#define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET                                        0x00000004
+#define REO_UNBLOCK_CACHE_RESERVED_1A_LSB                                           3
+#define REO_UNBLOCK_CACHE_RESERVED_1A_MSB                                           31
+#define REO_UNBLOCK_CACHE_RESERVED_1A_MASK                                          0xfffffff8
+
+#define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET                                        0x00000008
+#define REO_UNBLOCK_CACHE_RESERVED_2A_LSB                                           0
+#define REO_UNBLOCK_CACHE_RESERVED_2A_MSB                                           31
+#define REO_UNBLOCK_CACHE_RESERVED_2A_MASK                                          0xffffffff
+
+#define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET                                        0x0000000c
+#define REO_UNBLOCK_CACHE_RESERVED_3A_LSB                                           0
+#define REO_UNBLOCK_CACHE_RESERVED_3A_MSB                                           31
+#define REO_UNBLOCK_CACHE_RESERVED_3A_MASK                                          0xffffffff
+
+#define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET                                        0x00000010
+#define REO_UNBLOCK_CACHE_RESERVED_4A_LSB                                           0
+#define REO_UNBLOCK_CACHE_RESERVED_4A_MSB                                           31
+#define REO_UNBLOCK_CACHE_RESERVED_4A_MASK                                          0xffffffff
+
+#define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET                                        0x00000014
+#define REO_UNBLOCK_CACHE_RESERVED_5A_LSB                                           0
+#define REO_UNBLOCK_CACHE_RESERVED_5A_MSB                                           31
+#define REO_UNBLOCK_CACHE_RESERVED_5A_MASK                                          0xffffffff
+
+#define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET                                        0x00000018
+#define REO_UNBLOCK_CACHE_RESERVED_6A_LSB                                           0
+#define REO_UNBLOCK_CACHE_RESERVED_6A_MSB                                           31
+#define REO_UNBLOCK_CACHE_RESERVED_6A_MASK                                          0xffffffff
+
+#define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET                                        0x0000001c
+#define REO_UNBLOCK_CACHE_RESERVED_7A_LSB                                           0
+#define REO_UNBLOCK_CACHE_RESERVED_7A_MSB                                           31
+#define REO_UNBLOCK_CACHE_RESERVED_7A_MASK                                          0xffffffff
+
+#define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET                                        0x00000020
+#define REO_UNBLOCK_CACHE_RESERVED_8A_LSB                                           0
+#define REO_UNBLOCK_CACHE_RESERVED_8A_MSB                                           31
+#define REO_UNBLOCK_CACHE_RESERVED_8A_MASK                                          0xffffffff
+
+#endif
diff --git a/hw/peach/v1/reo_unblock_cache_status.h b/hw/peach/v1/reo_unblock_cache_status.h
new file mode 100644
index 000000000000..fe0de6cbb282
--- /dev/null
+++ b/hw/peach/v1/reo_unblock_cache_status.h
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_UNBLOCK_CACHE_STATUS_H_
+#define _REO_UNBLOCK_CACHE_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 27
+
+struct reo_unblock_cache_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tlv32_ring_padding                                      : 32;
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t error_detected                                          :  1,
+                      unblock_type                                            :  1,
+                      reserved_2a                                             : 30;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t reserved_25a                                            : 28,
+                      looping_count                                           :  4;
+#else
+             uint32_t tlv32_ring_padding                                      : 32;
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2a                                             : 30,
+                      unblock_type                                            :  1,
+                      error_detected                                          :  1;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_25a                                            : 28;
+#endif
+};
+
+#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_OFFSET                          0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_LSB                             0
+#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_MSB                             31
+#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_MASK                            0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET             0x00000004
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB                0
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB                15
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK               0x0000ffff
+
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET            0x00000004
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB               16
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB               25
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK              0x03ff0000
+
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET      0x00000004
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB         26
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB         27
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK        0x0c000000
+
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET                   0x00000004
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                      28
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                      31
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK                     0xf0000000
+
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET                     0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                        0
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                        31
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                       0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET                              0x0000000c
+#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB                                 0
+#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB                                 0
+#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK                                0x00000001
+
+#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET                                0x0000000c
+#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB                                   1
+#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB                                   1
+#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK                                  0x00000002
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET                                 0x0000000c
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB                                    2
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB                                    31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK                                   0xfffffffc
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET                                 0x00000010
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB                                    0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB                                    31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK                                   0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET                                 0x00000014
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB                                    0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB                                    31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK                                   0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET                                 0x00000018
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB                                    0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB                                    31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK                                   0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET                                 0x0000001c
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB                                    0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB                                    31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK                                   0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET                                 0x00000020
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB                                    0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB                                    31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK                                   0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET                                 0x00000024
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB                                    0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB                                    31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK                                   0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET                                 0x00000028
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB                                    0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB                                    31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK                                   0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET                                0x0000002c
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK                                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET                                0x00000030
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK                                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET                                0x00000034
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK                                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET                                0x00000038
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK                                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET                                0x0000003c
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK                                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET                                0x00000040
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK                                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET                                0x00000044
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK                                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET                                0x00000048
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK                                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET                                0x0000004c
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK                                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET                                0x00000050
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK                                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET                                0x00000054
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK                                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET                                0x00000058
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK                                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET                                0x0000005c
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK                                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET                                0x00000060
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK                                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET                                0x00000064
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB                                   31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK                                  0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET                                0x00000068
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB                                   0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB                                   27
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK                                  0x0fffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET                               0x00000068
+#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB                                  28
+#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB                                  31
+#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK                                 0xf0000000
+
+#endif
diff --git a/hw/peach/v1/reo_update_rx_reo_queue.h b/hw/peach/v1/reo_update_rx_reo_queue.h
new file mode 100644
index 000000000000..3aefb3f39a92
--- /dev/null
+++ b/hw/peach/v1/reo_update_rx_reo_queue.h
@@ -0,0 +1,425 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_H_
+#define _REO_UPDATE_RX_REO_QUEUE_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9
+
+struct reo_update_rx_reo_queue {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t rx_reo_queue_desc_addr_39_32                            :  8,
+                      update_receive_queue_number                             :  1,
+                      update_vld                                              :  1,
+                      update_associated_link_descriptor_counter               :  1,
+                      update_disable_duplicate_detection                      :  1,
+                      update_soft_reorder_enable                              :  1,
+                      update_ac                                               :  1,
+                      update_bar                                              :  1,
+                      update_rty                                              :  1,
+                      update_chk_2k_mode                                      :  1,
+                      update_oor_mode                                         :  1,
+                      update_ba_window_size                                   :  1,
+                      update_pn_check_needed                                  :  1,
+                      update_pn_shall_be_even                                 :  1,
+                      update_pn_shall_be_uneven                               :  1,
+                      update_pn_handling_enable                               :  1,
+                      update_pn_size                                          :  1,
+                      update_ignore_ampdu_flag                                :  1,
+                      update_svld                                             :  1,
+                      update_ssn                                              :  1,
+                      update_seq_2k_error_detected_flag                       :  1,
+                      update_pn_error_detected_flag                           :  1,
+                      update_pn_valid                                         :  1,
+                      update_pn                                               :  1,
+                      clear_stat_counters                                     :  1;
+             uint32_t receive_queue_number                                    : 16,
+                      vld                                                     :  1,
+                      associated_link_descriptor_counter                      :  2,
+                      disable_duplicate_detection                             :  1,
+                      soft_reorder_enable                                     :  1,
+                      ac                                                      :  2,
+                      bar                                                     :  1,
+                      rty                                                     :  1,
+                      chk_2k_mode                                             :  1,
+                      oor_mode                                                :  1,
+                      pn_check_needed                                         :  1,
+                      pn_shall_be_even                                        :  1,
+                      pn_shall_be_uneven                                      :  1,
+                      pn_handling_enable                                      :  1,
+                      ignore_ampdu_flag                                       :  1;
+             uint32_t ba_window_size                                          : 10,
+                      pn_size                                                 :  2,
+                      svld                                                    :  1,
+                      ssn                                                     : 12,
+                      seq_2k_error_detected_flag                              :  1,
+                      pn_error_detected_flag                                  :  1,
+                      pn_valid                                                :  1,
+                      flush_from_cache                                        :  1,
+                      reserved_4a                                             :  3;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+#else
+             struct   uniform_reo_cmd_header                                    cmd_header;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t clear_stat_counters                                     :  1,
+                      update_pn                                               :  1,
+                      update_pn_valid                                         :  1,
+                      update_pn_error_detected_flag                           :  1,
+                      update_seq_2k_error_detected_flag                       :  1,
+                      update_ssn                                              :  1,
+                      update_svld                                             :  1,
+                      update_ignore_ampdu_flag                                :  1,
+                      update_pn_size                                          :  1,
+                      update_pn_handling_enable                               :  1,
+                      update_pn_shall_be_uneven                               :  1,
+                      update_pn_shall_be_even                                 :  1,
+                      update_pn_check_needed                                  :  1,
+                      update_ba_window_size                                   :  1,
+                      update_oor_mode                                         :  1,
+                      update_chk_2k_mode                                      :  1,
+                      update_rty                                              :  1,
+                      update_bar                                              :  1,
+                      update_ac                                               :  1,
+                      update_soft_reorder_enable                              :  1,
+                      update_disable_duplicate_detection                      :  1,
+                      update_associated_link_descriptor_counter               :  1,
+                      update_vld                                              :  1,
+                      update_receive_queue_number                             :  1,
+                      rx_reo_queue_desc_addr_39_32                            :  8;
+             uint32_t ignore_ampdu_flag                                       :  1,
+                      pn_handling_enable                                      :  1,
+                      pn_shall_be_uneven                                      :  1,
+                      pn_shall_be_even                                        :  1,
+                      pn_check_needed                                         :  1,
+                      oor_mode                                                :  1,
+                      chk_2k_mode                                             :  1,
+                      rty                                                     :  1,
+                      bar                                                     :  1,
+                      ac                                                      :  2,
+                      soft_reorder_enable                                     :  1,
+                      disable_duplicate_detection                             :  1,
+                      associated_link_descriptor_counter                      :  2,
+                      vld                                                     :  1,
+                      receive_queue_number                                    : 16;
+             uint32_t reserved_4a                                             :  3,
+                      flush_from_cache                                        :  1,
+                      pn_valid                                                :  1,
+                      pn_error_detected_flag                                  :  1,
+                      seq_2k_error_detected_flag                              :  1,
+                      ssn                                                     : 12,
+                      svld                                                    :  1,
+                      pn_size                                                 :  2,
+                      ba_window_size                                          : 10;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+#endif
+};
+
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET                    0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB                       0
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB                       15
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK                      0x0000ffff
+
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET               0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB                  16
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB                  16
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK                 0x00010000
+
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET                       0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB                          17
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB                          31
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK                         0xfffe0000
+
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET                  0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB                     0
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB                     31
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK                    0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET                 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB                    0
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB                    7
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK                   0x000000ff
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET                  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB                     8
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB                     8
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK                    0x00000100
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET                                   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB                                      9
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB                                      9
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK                                     0x00000200
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET    0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB       10
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB       10
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK      0x00000400
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET           0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB              11
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB              11
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK             0x00000800
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET                   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB                      12
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB                      12
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK                     0x00001000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET                                    0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB                                       13
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB                                       13
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK                                      0x00002000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET                                   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB                                      14
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB                                      14
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK                                     0x00004000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET                                   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB                                      15
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB                                      15
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK                                     0x00008000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET                           0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB                              16
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB                              16
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK                             0x00010000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET                              0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB                                 17
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB                                 17
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK                                0x00020000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET                        0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB                           18
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB                           18
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK                          0x00040000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET                       0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB                          19
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB                          19
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK                         0x00080000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET                      0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB                         20
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB                         20
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK                        0x00100000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET                    0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB                       21
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB                       21
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK                      0x00200000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET                    0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB                       22
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB                       22
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK                      0x00400000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET                               0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB                                  23
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB                                  23
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK                                 0x00800000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET                     0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB                        24
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB                        24
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK                       0x01000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET                                  0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB                                     25
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB                                     25
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK                                    0x02000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET                                   0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB                                      26
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB                                      26
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK                                     0x04000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET            0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB               27
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB               27
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK              0x08000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET                0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB                   28
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB                   28
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK                  0x10000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET                              0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB                                 29
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB                                 29
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK                                0x20000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET                                    0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB                                       30
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB                                       30
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK                                      0x40000000
+
+#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET                          0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK                            0x80000000
+
+#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET                         0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB                            0
+#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB                            15
+#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK                           0x0000ffff
+
+#define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET                                          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_VLD_LSB                                             16
+#define REO_UPDATE_RX_REO_QUEUE_VLD_MSB                                             16
+#define REO_UPDATE_RX_REO_QUEUE_VLD_MASK                                            0x00010000
+
+#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET           0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB              17
+#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB              18
+#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK             0x00060000
+
+#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET                  0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB                     19
+#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB                     19
+#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK                    0x00080000
+
+#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET                          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB                             20
+#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB                             20
+#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK                            0x00100000
+
+#define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET                                           0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_AC_LSB                                              21
+#define REO_UPDATE_RX_REO_QUEUE_AC_MSB                                              22
+#define REO_UPDATE_RX_REO_QUEUE_AC_MASK                                             0x00600000
+
+#define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET                                          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_BAR_LSB                                             23
+#define REO_UPDATE_RX_REO_QUEUE_BAR_MSB                                             23
+#define REO_UPDATE_RX_REO_QUEUE_BAR_MASK                                            0x00800000
+
+#define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET                                          0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_RTY_LSB                                             24
+#define REO_UPDATE_RX_REO_QUEUE_RTY_MSB                                             24
+#define REO_UPDATE_RX_REO_QUEUE_RTY_MASK                                            0x01000000
+
+#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET                                  0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB                                     25
+#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB                                     25
+#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK                                    0x02000000
+
+#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET                                     0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB                                        26
+#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB                                        26
+#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK                                       0x04000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET                              0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB                                 27
+#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB                                 27
+#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK                                0x08000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET                             0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB                                28
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB                                28
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK                               0x10000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET                           0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB                              29
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB                              29
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK                             0x20000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET                           0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB                              30
+#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB                              30
+#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK                             0x40000000
+
+#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET                            0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB                               31
+#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB                               31
+#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK                              0x80000000
+
+#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET                               0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB                                  0
+#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB                                  9
+#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK                                 0x000003ff
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET                                      0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB                                         10
+#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB                                         11
+#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK                                        0x00000c00
+
+#define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET                                         0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB                                            12
+#define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB                                            12
+#define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK                                           0x00001000
+
+#define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET                                          0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_SSN_LSB                                             13
+#define REO_UPDATE_RX_REO_QUEUE_SSN_MSB                                             24
+#define REO_UPDATE_RX_REO_QUEUE_SSN_MASK                                            0x01ffe000
+
+#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET                   0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB                      25
+#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB                      25
+#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK                     0x02000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET                       0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB                          26
+#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB                          26
+#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK                         0x04000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET                                     0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB                                        27
+#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB                                        27
+#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK                                       0x08000000
+
+#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET                             0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB                                28
+#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB                                28
+#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK                               0x10000000
+
+#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET                                  0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB                                     29
+#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB                                     31
+#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK                                    0xe0000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET                                      0x00000014
+#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB                                         0
+#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB                                         31
+#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK                                        0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET                                     0x00000018
+#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB                                        0
+#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB                                        31
+#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK                                       0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET                                     0x0000001c
+#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB                                        0
+#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB                                        31
+#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK                                       0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET                                    0x00000020
+#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB                                       0
+#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB                                       31
+#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK                                      0xffffffff
+
+#endif
diff --git a/hw/peach/v1/reo_update_rx_reo_queue_status.h b/hw/peach/v1/reo_update_rx_reo_queue_status.h
new file mode 100644
index 000000000000..9ec7efc6ad3a
--- /dev/null
+++ b/hw/peach/v1/reo_update_rx_reo_queue_status.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 27
+
+struct reo_update_rx_reo_queue_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tlv32_ring_padding                                      : 32;
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2a                                             : 32;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t reserved_25a                                            : 28,
+                      looping_count                                           :  4;
+#else
+             uint32_t tlv32_ring_padding                                      : 32;
+             struct   uniform_reo_status_header                                 status_header;
+             uint32_t reserved_2a                                             : 32;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 32;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+             uint32_t reserved_10a                                            : 32;
+             uint32_t reserved_11a                                            : 32;
+             uint32_t reserved_12a                                            : 32;
+             uint32_t reserved_13a                                            : 32;
+             uint32_t reserved_14a                                            : 32;
+             uint32_t reserved_15a                                            : 32;
+             uint32_t reserved_16a                                            : 32;
+             uint32_t reserved_17a                                            : 32;
+             uint32_t reserved_18a                                            : 32;
+             uint32_t reserved_19a                                            : 32;
+             uint32_t reserved_20a                                            : 32;
+             uint32_t reserved_21a                                            : 32;
+             uint32_t reserved_22a                                            : 32;
+             uint32_t reserved_23a                                            : 32;
+             uint32_t reserved_24a                                            : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_25a                                            : 28;
+#endif
+};
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_OFFSET                    0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_LSB                       0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_MSB                       31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_MASK                      0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET       0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB          0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB          15
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK         0x0000ffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET      0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB         16
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB         25
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK        0x03ff0000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB   26
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB   27
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK  0x0c000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET             0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB                28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB                31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK               0xf0000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET               0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB                  0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB                  31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK                 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET                           0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB                              0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB                              31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK                             0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET                           0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB                              0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB                              31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK                             0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET                           0x00000014
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB                              0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB                              31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK                             0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET                           0x00000018
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB                              0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB                              31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK                             0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET                           0x0000001c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB                              0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB                              31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK                             0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET                           0x00000020
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB                              0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB                              31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK                             0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET                           0x00000024
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB                              0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB                              31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK                             0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET                           0x00000028
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB                              0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB                              31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK                             0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET                          0x0000002c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK                            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET                          0x00000030
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK                            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET                          0x00000034
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK                            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET                          0x00000038
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK                            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET                          0x0000003c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK                            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET                          0x00000040
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK                            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET                          0x00000044
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK                            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET                          0x00000048
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK                            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET                          0x0000004c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK                            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET                          0x00000050
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK                            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET                          0x00000054
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK                            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET                          0x00000058
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK                            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET                          0x0000005c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK                            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET                          0x00000060
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK                            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET                          0x00000064
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB                             31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK                            0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET                          0x00000068
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB                             0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB                             27
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK                            0x0fffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET                         0x00000068
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB                            28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB                            31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK                           0xf0000000
+
+#endif
diff --git a/hw/peach/v1/response_end_status.h b/hw/peach/v1/response_end_status.h
new file mode 100644
index 000000000000..600d007ce572
--- /dev/null
+++ b/hw/peach/v1/response_end_status.h
@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RESPONSE_END_STATUS_H_
+#define _RESPONSE_END_STATUS_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_RESPONSE_END_STATUS 10
+
+struct response_end_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t coex_bt_tx_while_wlan_tx                                :  1,
+                      coex_wan_tx_while_wlan_tx                               :  1,
+                      coex_wlan_tx_while_wlan_tx                              :  1,
+                      global_data_underflow_warning                           :  1,
+                      response_transmit_status                                :  4,
+                      phytx_pkt_end_info_valid                                :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      generated_response                                      :  3,
+                      mba_user_count                                          :  7,
+                      mba_fake_bitmap_count                                   :  7,
+                      coex_based_tx_bw                                        :  3,
+                      trig_response_related                                   :  1,
+                      reserved_0a                                             :  1;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t cbf_segment_request_mask                                :  8,
+                      cbf_segment_sent_mask                                   :  8;
+             uint32_t underflow_mpdu_count                                    :  9,
+                      data_underflow_warning                                  :  2,
+                      reserved_2b                                             : 10,
+                      only_null_delim_sent                                    :  1,
+                      brp_info_valid                                          :  1,
+                      coex_uwb_tx_while_wlan_tx                               :  1,
+                      coex_lte_tx_while_wlan_tx                               :  1,
+                      reserved_2a                                             :  7;
+             uint32_t mu_response_bitmap_31_0                                 : 32;
+             uint32_t mu_response_bitmap_36_32                                :  5,
+                      reserved_4a                                             : 27;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t addr3_47_32                                             : 16,
+                      __reserved_g_0005                                                 :  1,
+                      secure                                                  :  1,
+                      __reserved_g_0005_ftm_frame_sent                                  :  1,
+                      reserved_20a                                            : 13;
+#else
+             uint32_t reserved_0a                                             :  1,
+                      trig_response_related                                   :  1,
+                      coex_based_tx_bw                                        :  3,
+                      mba_fake_bitmap_count                                   :  7,
+                      mba_user_count                                          :  7,
+                      generated_response                                      :  3,
+                      phytx_abort_request_info_valid                          :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      response_transmit_status                                :  4,
+                      global_data_underflow_warning                           :  1,
+                      coex_wlan_tx_while_wlan_tx                              :  1,
+                      coex_wan_tx_while_wlan_tx                               :  1,
+                      coex_bt_tx_while_wlan_tx                                :  1;
+             uint32_t cbf_segment_sent_mask                                   :  8,
+                      cbf_segment_request_mask                                :  8;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint32_t reserved_2a                                             :  7,
+                      coex_lte_tx_while_wlan_tx                               :  1,
+                      coex_uwb_tx_while_wlan_tx                               :  1,
+                      brp_info_valid                                          :  1,
+                      only_null_delim_sent                                    :  1,
+                      reserved_2b                                             : 10,
+                      data_underflow_warning                                  :  2,
+                      underflow_mpdu_count                                    :  9;
+             uint32_t mu_response_bitmap_31_0                                 : 32;
+             uint32_t reserved_4a                                             : 27,
+                      mu_response_bitmap_36_32                                :  5;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t reserved_20a                                            : 13,
+                      __reserved_g_0005_ftm_frame_sent                                  :  1,
+                      secure                                                  :  1,
+                      __reserved_g_0005                                                 :  1,
+                      addr3_47_32                                             : 16;
+#endif
+};
+
+#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET                         0x00000000
+#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB                            0
+#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB                            0
+#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK                           0x00000001
+
+#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET                        0x00000000
+#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB                           1
+#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB                           1
+#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK                          0x00000002
+
+#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET                       0x00000000
+#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB                          2
+#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB                          2
+#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK                         0x00000004
+
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET                    0x00000000
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB                       3
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB                       3
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK                      0x00000008
+
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET                         0x00000000
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB                            4
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB                            7
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK                           0x000000f0
+
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET                         0x00000000
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB                            8
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB                            8
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK                           0x00000100
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET                   0x00000000
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB                      9
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB                      9
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK                     0x00000200
+
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET                               0x00000000
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB                                  10
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB                                  12
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK                                 0x00001c00
+
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET                                   0x00000000
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB                                      13
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB                                      19
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK                                     0x000fe000
+
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET                            0x00000000
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB                               20
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB                               26
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK                              0x07f00000
+
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET                                 0x00000000
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB                                    27
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB                                    29
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK                                   0x38000000
+
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET                            0x00000000
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB                               30
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB                               30
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK                              0x40000000
+
+#define RESPONSE_END_STATUS_RESERVED_0A_OFFSET                                      0x00000000
+#define RESPONSE_END_STATUS_RESERVED_0A_LSB                                         31
+#define RESPONSE_END_STATUS_RESERVED_0A_MSB                                         31
+#define RESPONSE_END_STATUS_RESERVED_0A_MASK                                        0x80000000
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET     0x00000004
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB        8
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB        13
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK       0x00003f00
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET        0x00000004
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB           14
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB           15
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK          0x0000c000
+
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET                         0x00000004
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB                            16
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB                            23
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK                           0x00ff0000
+
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET                            0x00000004
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB                               24
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB                               31
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK                              0xff000000
+
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET                             0x00000008
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB                                0
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB                                8
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK                               0x000001ff
+
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET                           0x00000008
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB                              9
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB                              10
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK                             0x00000600
+
+#define RESPONSE_END_STATUS_RESERVED_2B_OFFSET                                      0x00000008
+#define RESPONSE_END_STATUS_RESERVED_2B_LSB                                         11
+#define RESPONSE_END_STATUS_RESERVED_2B_MSB                                         20
+#define RESPONSE_END_STATUS_RESERVED_2B_MASK                                        0x001ff800
+
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET                             0x00000008
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB                                21
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB                                21
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK                               0x00200000
+
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET                                   0x00000008
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB                                      22
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB                                      22
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK                                     0x00400000
+
+#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET                        0x00000008
+#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_LSB                           23
+#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_MSB                           23
+#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_MASK                          0x00800000
+
+#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET                        0x00000008
+#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_LSB                           24
+#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_MSB                           24
+#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_MASK                          0x01000000
+
+#define RESPONSE_END_STATUS_RESERVED_2A_OFFSET                                      0x00000008
+#define RESPONSE_END_STATUS_RESERVED_2A_LSB                                         25
+#define RESPONSE_END_STATUS_RESERVED_2A_MSB                                         31
+#define RESPONSE_END_STATUS_RESERVED_2A_MASK                                        0xfe000000
+
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET                          0x0000000c
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB                             0
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB                             31
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK                            0xffffffff
+
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET                         0x00000010
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB                            0
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB                            4
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK                           0x0000001f
+
+#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET                                      0x00000010
+#define RESPONSE_END_STATUS_RESERVED_4A_LSB                                         5
+#define RESPONSE_END_STATUS_RESERVED_4A_MSB                                         31
+#define RESPONSE_END_STATUS_RESERVED_4A_MASK                                        0xffffffe0
+
+#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET                                       0x00000014
+#define RESPONSE_END_STATUS_ADDR1_31_0_LSB                                          0
+#define RESPONSE_END_STATUS_ADDR1_31_0_MSB                                          31
+#define RESPONSE_END_STATUS_ADDR1_31_0_MASK                                         0xffffffff
+
+#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET                                      0x00000018
+#define RESPONSE_END_STATUS_ADDR1_47_32_LSB                                         0
+#define RESPONSE_END_STATUS_ADDR1_47_32_MSB                                         15
+#define RESPONSE_END_STATUS_ADDR1_47_32_MASK                                        0x0000ffff
+
+#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET                                       0x00000018
+#define RESPONSE_END_STATUS_ADDR2_15_0_LSB                                          16
+#define RESPONSE_END_STATUS_ADDR2_15_0_MSB                                          31
+#define RESPONSE_END_STATUS_ADDR2_15_0_MASK                                         0xffff0000
+
+#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET                                      0x0000001c
+#define RESPONSE_END_STATUS_ADDR2_47_16_LSB                                         0
+#define RESPONSE_END_STATUS_ADDR2_47_16_MSB                                         31
+#define RESPONSE_END_STATUS_ADDR2_47_16_MASK                                        0xffffffff
+
+#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET                                       0x00000020
+#define RESPONSE_END_STATUS_ADDR3_31_0_LSB                                          0
+#define RESPONSE_END_STATUS_ADDR3_31_0_MSB                                          31
+#define RESPONSE_END_STATUS_ADDR3_31_0_MASK                                         0xffffffff
+
+#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET                                      0x00000024
+#define RESPONSE_END_STATUS_ADDR3_47_32_LSB                                         0
+#define RESPONSE_END_STATUS_ADDR3_47_32_MSB                                         15
+#define RESPONSE_END_STATUS_ADDR3_47_32_MASK                                        0x0000ffff
+
+#define RESPONSE_END_STATUS_SECURE_OFFSET                                           0x00000024
+#define RESPONSE_END_STATUS_SECURE_LSB                                              17
+#define RESPONSE_END_STATUS_SECURE_MSB                                              17
+#define RESPONSE_END_STATUS_SECURE_MASK                                             0x00020000
+
+#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET                           0x00000024
+#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB                              18
+#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB                              18
+#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK                             0x00040000
+
+#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET                                     0x00000024
+#define RESPONSE_END_STATUS_RESERVED_20A_LSB                                        19
+#define RESPONSE_END_STATUS_RESERVED_20A_MSB                                        31
+#define RESPONSE_END_STATUS_RESERVED_20A_MASK                                       0xfff80000
+
+#endif
diff --git a/hw/peach/v1/response_start_status.h b/hw/peach/v1/response_start_status.h
new file mode 100644
index 000000000000..2b54ed1da7ab
--- /dev/null
+++ b/hw/peach/v1/response_start_status.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RESPONSE_START_STATUS_H_
+#define _RESPONSE_START_STATUS_H_
+
+#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2
+
+struct response_start_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t generated_response                                      :  3,
+                      __reserved_g_0012                                                  :  2,
+                      trig_response_related                                   :  1,
+                      response_sta_count                                      :  7,
+                      reserved                                                : 19;
+             uint32_t phy_ppdu_id                                             : 16,
+                      sw_peer_id                                              : 16;
+#else
+             uint32_t reserved                                                : 19,
+                      response_sta_count                                      :  7,
+                      trig_response_related                                   :  1,
+                      __reserved_g_0012                                                  :  2,
+                      generated_response                                      :  3;
+             uint32_t sw_peer_id                                              : 16,
+                      phy_ppdu_id                                             : 16;
+#endif
+};
+
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET                             0x00000000
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB                                0
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB                                2
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK                               0x00000007
+
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET                          0x00000000
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB                             5
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB                             5
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK                            0x00000020
+
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET                             0x00000000
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB                                6
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB                                12
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK                               0x00001fc0
+
+#define RESPONSE_START_STATUS_RESERVED_OFFSET                                       0x00000000
+#define RESPONSE_START_STATUS_RESERVED_LSB                                          13
+#define RESPONSE_START_STATUS_RESERVED_MSB                                          31
+#define RESPONSE_START_STATUS_RESERVED_MASK                                         0xffffe000
+
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET                                    0x00000004
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB                                       0
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB                                       15
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK                                      0x0000ffff
+
+#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET                                     0x00000004
+#define RESPONSE_START_STATUS_SW_PEER_ID_LSB                                        16
+#define RESPONSE_START_STATUS_SW_PEER_ID_MSB                                        31
+#define RESPONSE_START_STATUS_SW_PEER_ID_MASK                                       0xffff0000
+
+#endif
diff --git a/hw/peach/v1/ru_allocation_160_info.h b/hw/peach/v1/ru_allocation_160_info.h
new file mode 100644
index 000000000000..3693e4ba6442
--- /dev/null
+++ b/hw/peach/v1/ru_allocation_160_info.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RU_ALLOCATION_160_INFO_H_
+#define _RU_ALLOCATION_160_INFO_H_
+
+#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4
+
+struct ru_allocation_160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ru_allocation_band0_0                                   :  9,
+                      ru_allocation_band0_1                                   :  9,
+                      reserved_0a                                             :  6,
+                      ru_allocations_01_subband80_mask                        :  4,
+                      ru_allocations_23_subband80_mask                        :  4;
+             uint32_t ru_allocation_band0_2                                   :  9,
+                      ru_allocation_band0_3                                   :  9,
+                      reserved_1a                                             : 14;
+             uint32_t ru_allocation_band1_0                                   :  9,
+                      ru_allocation_band1_1                                   :  9,
+                      reserved_2a                                             : 14;
+             uint32_t ru_allocation_band1_2                                   :  9,
+                      ru_allocation_band1_3                                   :  9,
+                      reserved_3a                                             : 14;
+#else
+             uint32_t ru_allocations_23_subband80_mask                        :  4,
+                      ru_allocations_01_subband80_mask                        :  4,
+                      reserved_0a                                             :  6,
+                      ru_allocation_band0_1                                   :  9,
+                      ru_allocation_band0_0                                   :  9;
+             uint32_t reserved_1a                                             : 14,
+                      ru_allocation_band0_3                                   :  9,
+                      ru_allocation_band0_2                                   :  9;
+             uint32_t reserved_2a                                             : 14,
+                      ru_allocation_band1_1                                   :  9,
+                      ru_allocation_band1_0                                   :  9;
+             uint32_t reserved_3a                                             : 14,
+                      ru_allocation_band1_3                                   :  9,
+                      ru_allocation_band1_2                                   :  9;
+#endif
+};
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET                         0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET                         0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET                                   0x00000000
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB                                      23
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK                                     0x00fc0000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET              0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB                 24
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB                 27
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK                0x0f000000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET              0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB                 28
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB                 31
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK                0xf0000000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET                         0x00000004
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET                         0x00000004
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET                                   0x00000004
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB                                      31
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK                                     0xfffc0000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET                         0x00000008
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET                         0x00000008
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET                                   0x00000008
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB                                      31
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK                                     0xfffc0000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET                         0x0000000c
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB                            0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB                            8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK                           0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET                         0x0000000c
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB                            9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB                            17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK                           0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET                                   0x0000000c
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB                                      18
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB                                      31
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK                                     0xfffc0000
+
+#endif
diff --git a/hw/peach/v1/rx_attention.h b/hw/peach/v1/rx_attention.h
new file mode 100644
index 000000000000..cafa2abe8ea7
--- /dev/null
+++ b/hw/peach/v1/rx_attention.h
@@ -0,0 +1,379 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_ATTENTION_H_
+#define _RX_ATTENTION_H_
+
+#define NUM_OF_DWORDS_RX_ATTENTION 3
+
+struct rx_attention {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+             uint32_t first_mpdu                                              :  1,
+                      reserved_1a                                             :  1,
+                      mcast_bcast                                             :  1,
+                      ast_index_not_found                                     :  1,
+                      ast_index_timeout                                       :  1,
+                      power_mgmt                                              :  1,
+                      non_qos                                                 :  1,
+                      null_data                                               :  1,
+                      mgmt_type                                               :  1,
+                      ctrl_type                                               :  1,
+                      more_data                                               :  1,
+                      eosp                                                    :  1,
+                      a_msdu_error                                            :  1,
+                      fragment_flag                                           :  1,
+                      order                                                   :  1,
+                      cce_match                                               :  1,
+                      overflow_err                                            :  1,
+                      msdu_length_err                                         :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      ip_chksum_fail                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      da_idx_invalid                                          :  1,
+                      reserved_1b                                             :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      encrypt_required                                        :  1,
+                      directed                                                :  1,
+                      buffer_fragment                                         :  1,
+                      mpdu_length_err                                         :  1,
+                      tkip_mic_err                                            :  1,
+                      decrypt_err                                             :  1,
+                      unencrypted_frame_err                                   :  1,
+                      fcs_err                                                 :  1;
+             uint32_t flow_idx_timeout                                        :  1,
+                      flow_idx_invalid                                        :  1,
+                      wifi_parser_error                                       :  1,
+                      amsdu_parser_error                                      :  1,
+                      sa_idx_timeout                                          :  1,
+                      da_idx_timeout                                          :  1,
+                      msdu_limit_error                                        :  1,
+                      da_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      sa_is_valid                                             :  1,
+                      decrypt_status_code                                     :  3,
+                      rx_bitmap_not_updated                                   :  1,
+                      reserved_2                                              : 17,
+                      msdu_done                                               :  1;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t fcs_err                                                 :  1,
+                      unencrypted_frame_err                                   :  1,
+                      decrypt_err                                             :  1,
+                      tkip_mic_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      buffer_fragment                                         :  1,
+                      directed                                                :  1,
+                      encrypt_required                                        :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      reserved_1b                                             :  1,
+                      da_idx_invalid                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      ip_chksum_fail                                          :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      msdu_length_err                                         :  1,
+                      overflow_err                                            :  1,
+                      cce_match                                               :  1,
+                      order                                                   :  1,
+                      fragment_flag                                           :  1,
+                      a_msdu_error                                            :  1,
+                      eosp                                                    :  1,
+                      more_data                                               :  1,
+                      ctrl_type                                               :  1,
+                      mgmt_type                                               :  1,
+                      null_data                                               :  1,
+                      non_qos                                                 :  1,
+                      power_mgmt                                              :  1,
+                      ast_index_timeout                                       :  1,
+                      ast_index_not_found                                     :  1,
+                      mcast_bcast                                             :  1,
+                      reserved_1a                                             :  1,
+                      first_mpdu                                              :  1;
+             uint32_t msdu_done                                               :  1,
+                      reserved_2                                              : 17,
+                      rx_bitmap_not_updated                                   :  1,
+                      decrypt_status_code                                     :  3,
+                      sa_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      da_is_valid                                             :  1,
+                      msdu_limit_error                                        :  1,
+                      da_idx_timeout                                          :  1,
+                      sa_idx_timeout                                          :  1,
+                      amsdu_parser_error                                      :  1,
+                      wifi_parser_error                                       :  1,
+                      flow_idx_invalid                                        :  1,
+                      flow_idx_timeout                                        :  1;
+#endif
+};
+
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                           0x00000000
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                              0
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                              1
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                             0x00000003
+
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET                                       0x00000000
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB                                          2
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB                                          8
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK                                         0x000001fc
+
+#define RX_ATTENTION_RESERVED_0_OFFSET                                              0x00000000
+#define RX_ATTENTION_RESERVED_0_LSB                                                 9
+#define RX_ATTENTION_RESERVED_0_MSB                                                 15
+#define RX_ATTENTION_RESERVED_0_MASK                                                0x0000fe00
+
+#define RX_ATTENTION_PHY_PPDU_ID_OFFSET                                             0x00000000
+#define RX_ATTENTION_PHY_PPDU_ID_LSB                                                16
+#define RX_ATTENTION_PHY_PPDU_ID_MSB                                                31
+#define RX_ATTENTION_PHY_PPDU_ID_MASK                                               0xffff0000
+
+#define RX_ATTENTION_FIRST_MPDU_OFFSET                                              0x00000004
+#define RX_ATTENTION_FIRST_MPDU_LSB                                                 0
+#define RX_ATTENTION_FIRST_MPDU_MSB                                                 0
+#define RX_ATTENTION_FIRST_MPDU_MASK                                                0x00000001
+
+#define RX_ATTENTION_RESERVED_1A_OFFSET                                             0x00000004
+#define RX_ATTENTION_RESERVED_1A_LSB                                                1
+#define RX_ATTENTION_RESERVED_1A_MSB                                                1
+#define RX_ATTENTION_RESERVED_1A_MASK                                               0x00000002
+
+#define RX_ATTENTION_MCAST_BCAST_OFFSET                                             0x00000004
+#define RX_ATTENTION_MCAST_BCAST_LSB                                                2
+#define RX_ATTENTION_MCAST_BCAST_MSB                                                2
+#define RX_ATTENTION_MCAST_BCAST_MASK                                               0x00000004
+
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET                                     0x00000004
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB                                        3
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB                                        3
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK                                       0x00000008
+
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET                                       0x00000004
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB                                          4
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB                                          4
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK                                         0x00000010
+
+#define RX_ATTENTION_POWER_MGMT_OFFSET                                              0x00000004
+#define RX_ATTENTION_POWER_MGMT_LSB                                                 5
+#define RX_ATTENTION_POWER_MGMT_MSB                                                 5
+#define RX_ATTENTION_POWER_MGMT_MASK                                                0x00000020
+
+#define RX_ATTENTION_NON_QOS_OFFSET                                                 0x00000004
+#define RX_ATTENTION_NON_QOS_LSB                                                    6
+#define RX_ATTENTION_NON_QOS_MSB                                                    6
+#define RX_ATTENTION_NON_QOS_MASK                                                   0x00000040
+
+#define RX_ATTENTION_NULL_DATA_OFFSET                                               0x00000004
+#define RX_ATTENTION_NULL_DATA_LSB                                                  7
+#define RX_ATTENTION_NULL_DATA_MSB                                                  7
+#define RX_ATTENTION_NULL_DATA_MASK                                                 0x00000080
+
+#define RX_ATTENTION_MGMT_TYPE_OFFSET                                               0x00000004
+#define RX_ATTENTION_MGMT_TYPE_LSB                                                  8
+#define RX_ATTENTION_MGMT_TYPE_MSB                                                  8
+#define RX_ATTENTION_MGMT_TYPE_MASK                                                 0x00000100
+
+#define RX_ATTENTION_CTRL_TYPE_OFFSET                                               0x00000004
+#define RX_ATTENTION_CTRL_TYPE_LSB                                                  9
+#define RX_ATTENTION_CTRL_TYPE_MSB                                                  9
+#define RX_ATTENTION_CTRL_TYPE_MASK                                                 0x00000200
+
+#define RX_ATTENTION_MORE_DATA_OFFSET                                               0x00000004
+#define RX_ATTENTION_MORE_DATA_LSB                                                  10
+#define RX_ATTENTION_MORE_DATA_MSB                                                  10
+#define RX_ATTENTION_MORE_DATA_MASK                                                 0x00000400
+
+#define RX_ATTENTION_EOSP_OFFSET                                                    0x00000004
+#define RX_ATTENTION_EOSP_LSB                                                       11
+#define RX_ATTENTION_EOSP_MSB                                                       11
+#define RX_ATTENTION_EOSP_MASK                                                      0x00000800
+
+#define RX_ATTENTION_A_MSDU_ERROR_OFFSET                                            0x00000004
+#define RX_ATTENTION_A_MSDU_ERROR_LSB                                               12
+#define RX_ATTENTION_A_MSDU_ERROR_MSB                                               12
+#define RX_ATTENTION_A_MSDU_ERROR_MASK                                              0x00001000
+
+#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET                                           0x00000004
+#define RX_ATTENTION_FRAGMENT_FLAG_LSB                                              13
+#define RX_ATTENTION_FRAGMENT_FLAG_MSB                                              13
+#define RX_ATTENTION_FRAGMENT_FLAG_MASK                                             0x00002000
+
+#define RX_ATTENTION_ORDER_OFFSET                                                   0x00000004
+#define RX_ATTENTION_ORDER_LSB                                                      14
+#define RX_ATTENTION_ORDER_MSB                                                      14
+#define RX_ATTENTION_ORDER_MASK                                                     0x00004000
+
+#define RX_ATTENTION_CCE_MATCH_OFFSET                                               0x00000004
+#define RX_ATTENTION_CCE_MATCH_LSB                                                  15
+#define RX_ATTENTION_CCE_MATCH_MSB                                                  15
+#define RX_ATTENTION_CCE_MATCH_MASK                                                 0x00008000
+
+#define RX_ATTENTION_OVERFLOW_ERR_OFFSET                                            0x00000004
+#define RX_ATTENTION_OVERFLOW_ERR_LSB                                               16
+#define RX_ATTENTION_OVERFLOW_ERR_MSB                                               16
+#define RX_ATTENTION_OVERFLOW_ERR_MASK                                              0x00010000
+
+#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET                                         0x00000004
+#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB                                            17
+#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB                                            17
+#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK                                           0x00020000
+
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET                                     0x00000004
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB                                        18
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB                                        18
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK                                       0x00040000
+
+#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET                                          0x00000004
+#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB                                             19
+#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB                                             19
+#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK                                            0x00080000
+
+#define RX_ATTENTION_SA_IDX_INVALID_OFFSET                                          0x00000004
+#define RX_ATTENTION_SA_IDX_INVALID_LSB                                             20
+#define RX_ATTENTION_SA_IDX_INVALID_MSB                                             20
+#define RX_ATTENTION_SA_IDX_INVALID_MASK                                            0x00100000
+
+#define RX_ATTENTION_DA_IDX_INVALID_OFFSET                                          0x00000004
+#define RX_ATTENTION_DA_IDX_INVALID_LSB                                             21
+#define RX_ATTENTION_DA_IDX_INVALID_MSB                                             21
+#define RX_ATTENTION_DA_IDX_INVALID_MASK                                            0x00200000
+
+#define RX_ATTENTION_RESERVED_1B_OFFSET                                             0x00000004
+#define RX_ATTENTION_RESERVED_1B_LSB                                                22
+#define RX_ATTENTION_RESERVED_1B_MSB                                                22
+#define RX_ATTENTION_RESERVED_1B_MASK                                               0x00400000
+
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET                                    0x00000004
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB                                       23
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB                                       23
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK                                      0x00800000
+
+#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET                                        0x00000004
+#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB                                           24
+#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB                                           24
+#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK                                          0x01000000
+
+#define RX_ATTENTION_DIRECTED_OFFSET                                                0x00000004
+#define RX_ATTENTION_DIRECTED_LSB                                                   25
+#define RX_ATTENTION_DIRECTED_MSB                                                   25
+#define RX_ATTENTION_DIRECTED_MASK                                                  0x02000000
+
+#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET                                         0x00000004
+#define RX_ATTENTION_BUFFER_FRAGMENT_LSB                                            26
+#define RX_ATTENTION_BUFFER_FRAGMENT_MSB                                            26
+#define RX_ATTENTION_BUFFER_FRAGMENT_MASK                                           0x04000000
+
+#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET                                         0x00000004
+#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB                                            27
+#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB                                            27
+#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK                                           0x08000000
+
+#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET                                            0x00000004
+#define RX_ATTENTION_TKIP_MIC_ERR_LSB                                               28
+#define RX_ATTENTION_TKIP_MIC_ERR_MSB                                               28
+#define RX_ATTENTION_TKIP_MIC_ERR_MASK                                              0x10000000
+
+#define RX_ATTENTION_DECRYPT_ERR_OFFSET                                             0x00000004
+#define RX_ATTENTION_DECRYPT_ERR_LSB                                                29
+#define RX_ATTENTION_DECRYPT_ERR_MSB                                                29
+#define RX_ATTENTION_DECRYPT_ERR_MASK                                               0x20000000
+
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET                                   0x00000004
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB                                      30
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB                                      30
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK                                     0x40000000
+
+#define RX_ATTENTION_FCS_ERR_OFFSET                                                 0x00000004
+#define RX_ATTENTION_FCS_ERR_LSB                                                    31
+#define RX_ATTENTION_FCS_ERR_MSB                                                    31
+#define RX_ATTENTION_FCS_ERR_MASK                                                   0x80000000
+
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET                                        0x00000008
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB                                           0
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB                                           0
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK                                          0x00000001
+
+#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET                                        0x00000008
+#define RX_ATTENTION_FLOW_IDX_INVALID_LSB                                           1
+#define RX_ATTENTION_FLOW_IDX_INVALID_MSB                                           1
+#define RX_ATTENTION_FLOW_IDX_INVALID_MASK                                          0x00000002
+
+#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET                                       0x00000008
+#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB                                          2
+#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB                                          2
+#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK                                         0x00000004
+
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET                                      0x00000008
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB                                         3
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB                                         3
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK                                        0x00000008
+
+#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET                                          0x00000008
+#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB                                             4
+#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB                                             4
+#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK                                            0x00000010
+
+#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET                                          0x00000008
+#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB                                             5
+#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB                                             5
+#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK                                            0x00000020
+
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET                                        0x00000008
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB                                           6
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB                                           6
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK                                          0x00000040
+
+#define RX_ATTENTION_DA_IS_VALID_OFFSET                                             0x00000008
+#define RX_ATTENTION_DA_IS_VALID_LSB                                                7
+#define RX_ATTENTION_DA_IS_VALID_MSB                                                7
+#define RX_ATTENTION_DA_IS_VALID_MASK                                               0x00000080
+
+#define RX_ATTENTION_DA_IS_MCBC_OFFSET                                              0x00000008
+#define RX_ATTENTION_DA_IS_MCBC_LSB                                                 8
+#define RX_ATTENTION_DA_IS_MCBC_MSB                                                 8
+#define RX_ATTENTION_DA_IS_MCBC_MASK                                                0x00000100
+
+#define RX_ATTENTION_SA_IS_VALID_OFFSET                                             0x00000008
+#define RX_ATTENTION_SA_IS_VALID_LSB                                                9
+#define RX_ATTENTION_SA_IS_VALID_MSB                                                9
+#define RX_ATTENTION_SA_IS_VALID_MASK                                               0x00000200
+
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET                                     0x00000008
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB                                        10
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB                                        12
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK                                       0x00001c00
+
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET                                   0x00000008
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB                                      13
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB                                      13
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK                                     0x00002000
+
+#define RX_ATTENTION_RESERVED_2_OFFSET                                              0x00000008
+#define RX_ATTENTION_RESERVED_2_LSB                                                 14
+#define RX_ATTENTION_RESERVED_2_MSB                                                 30
+#define RX_ATTENTION_RESERVED_2_MASK                                                0x7fffc000
+
+#define RX_ATTENTION_MSDU_DONE_OFFSET                                               0x00000008
+#define RX_ATTENTION_MSDU_DONE_LSB                                                  31
+#define RX_ATTENTION_MSDU_DONE_MSB                                                  31
+#define RX_ATTENTION_MSDU_DONE_MASK                                                 0x80000000
+
+#endif
diff --git a/hw/peach/v1/rx_flow_search_entry.h b/hw/peach/v1/rx_flow_search_entry.h
new file mode 100644
index 000000000000..adcae02a8492
--- /dev/null
+++ b/hw/peach/v1/rx_flow_search_entry.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_FLOW_SEARCH_ENTRY_H_
+#define _RX_FLOW_SEARCH_ENTRY_H_
+
+#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16
+
+struct rx_flow_search_entry {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t src_ip_127_96                                           : 32;
+             uint32_t src_ip_95_64                                            : 32;
+             uint32_t src_ip_63_32                                            : 32;
+             uint32_t src_ip_31_0                                             : 32;
+             uint32_t dest_ip_127_96                                          : 32;
+             uint32_t dest_ip_95_64                                           : 32;
+             uint32_t dest_ip_63_32                                           : 32;
+             uint32_t dest_ip_31_0                                            : 32;
+             uint32_t src_port                                                : 16,
+                      dest_port                                               : 16;
+             uint32_t l4_protocol                                             :  8,
+                      valid                                                   :  1,
+                      reserved_9                                              :  4,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      use_ppe                                                 :  1,
+                      reo_destination_indication                              :  5,
+                      msdu_drop                                               :  1,
+                      reo_destination_handler                                 :  2;
+             uint32_t metadata                                                : 32;
+             uint32_t aggregation_count                                       :  7,
+                      lro_eligible                                            :  1,
+                      msdu_count                                              : 24;
+             uint32_t msdu_byte_count                                         : 32;
+             uint32_t timestamp                                               : 32;
+             uint32_t cumulative_ip_length_pmac1                              : 16,
+                      cumulative_ip_length                                    : 16;
+             uint32_t tcp_sequence_number                                     : 32;
+#else
+             uint32_t src_ip_127_96                                           : 32;
+             uint32_t src_ip_95_64                                            : 32;
+             uint32_t src_ip_63_32                                            : 32;
+             uint32_t src_ip_31_0                                             : 32;
+             uint32_t dest_ip_127_96                                          : 32;
+             uint32_t dest_ip_95_64                                           : 32;
+             uint32_t dest_ip_63_32                                           : 32;
+             uint32_t dest_ip_31_0                                            : 32;
+             uint32_t dest_port                                               : 16,
+                      src_port                                                : 16;
+             uint32_t reo_destination_handler                                 :  2,
+                      msdu_drop                                               :  1,
+                      reo_destination_indication                              :  5,
+                      use_ppe                                                 :  1,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      reserved_9                                              :  4,
+                      valid                                                   :  1,
+                      l4_protocol                                             :  8;
+             uint32_t metadata                                                : 32;
+             uint32_t msdu_count                                              : 24,
+                      lro_eligible                                            :  1,
+                      aggregation_count                                       :  7;
+             uint32_t msdu_byte_count                                         : 32;
+             uint32_t timestamp                                               : 32;
+             uint32_t cumulative_ip_length                                    : 16,
+                      cumulative_ip_length_pmac1                              : 16;
+             uint32_t tcp_sequence_number                                     : 32;
+#endif
+};
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET                                   0x00000000
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB                                      0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB                                      31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK                                     0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET                                    0x00000004
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB                                       0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB                                       31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK                                      0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET                                    0x00000008
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB                                       0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB                                       31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK                                      0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET                                     0x0000000c
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB                                        0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB                                        31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK                                       0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET                                  0x00000010
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB                                     0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB                                     31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK                                    0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET                                   0x00000014
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB                                      0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB                                      31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK                                     0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET                                   0x00000018
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB                                      0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB                                      31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK                                     0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET                                    0x0000001c
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB                                       0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB                                       31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK                                      0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET                                        0x00000020
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB                                           0
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB                                           15
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK                                          0x0000ffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET                                       0x00000020
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB                                          16
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB                                          31
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK                                         0xffff0000
+
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET                                     0x00000024
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB                                        0
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB                                        7
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK                                       0x000000ff
+
+#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET                                           0x00000024
+#define RX_FLOW_SEARCH_ENTRY_VALID_LSB                                              8
+#define RX_FLOW_SEARCH_ENTRY_VALID_MSB                                              8
+#define RX_FLOW_SEARCH_ENTRY_VALID_MASK                                             0x00000100
+
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET                                      0x00000024
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB                                         9
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB                                         12
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK                                        0x00001e00
+
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET                                    0x00000024
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB                                       13
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB                                       21
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK                                      0x003fe000
+
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET                                  0x00000024
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB                                     22
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB                                     22
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK                                    0x00400000
+
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET                                         0x00000024
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB                                            23
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB                                            23
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK                                           0x00800000
+
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET                      0x00000024
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB                         24
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB                         28
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK                        0x1f000000
+
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET                                       0x00000024
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB                                          29
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB                                          29
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK                                         0x20000000
+
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET                         0x00000024
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB                            30
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB                            31
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK                           0xc0000000
+
+#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET                                        0x00000028
+#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB                                           0
+#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB                                           31
+#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK                                          0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET                               0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB                                  0
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB                                  6
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK                                 0x0000007f
+
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET                                    0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB                                       7
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB                                       7
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK                                      0x00000080
+
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET                                      0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB                                         8
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB                                         31
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK                                        0xffffff00
+
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET                                 0x00000030
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB                                    0
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB                                    31
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK                                   0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET                                       0x00000034
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB                                          0
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB                                          31
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK                                         0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET                      0x00000038
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB                         0
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB                         15
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK                        0x0000ffff
+
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET                            0x00000038
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB                               16
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB                               31
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK                              0xffff0000
+
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET                             0x0000003c
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB                                0
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB                                31
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK                               0xffffffff
+
+#endif
diff --git a/hw/peach/v1/rx_frame_1k_bitmap_ack.h b/hw/peach/v1/rx_frame_1k_bitmap_ack.h
new file mode 100644
index 000000000000..2698e5b0a542
--- /dev/null
+++ b/hw/peach/v1/rx_frame_1k_bitmap_ack.h
@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_FRAME_1K_BITMAP_ACK_H_
+#define _RX_FRAME_1K_BITMAP_ACK_H_
+
+#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 37
+
+struct rx_frame_1k_bitmap_ack {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reserved_0a                                             :  5,
+                      ba_bitmap_size                                          :  2,
+                      reserved_0b                                             :  3,
+                      ba_tid                                                  :  4,
+                      sta_full_aid                                            : 13,
+                      reserved_0c                                             :  5;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_ctrl                                              : 16,
+                      ba_ts_seq                                               : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+             uint32_t ba_ts_bitmap_287_256                                    : 32;
+             uint32_t ba_ts_bitmap_319_288                                    : 32;
+             uint32_t ba_ts_bitmap_351_320                                    : 32;
+             uint32_t ba_ts_bitmap_383_352                                    : 32;
+             uint32_t ba_ts_bitmap_415_384                                    : 32;
+             uint32_t ba_ts_bitmap_447_416                                    : 32;
+             uint32_t ba_ts_bitmap_479_448                                    : 32;
+             uint32_t ba_ts_bitmap_511_480                                    : 32;
+             uint32_t ba_ts_bitmap_543_512                                    : 32;
+             uint32_t ba_ts_bitmap_575_544                                    : 32;
+             uint32_t ba_ts_bitmap_607_576                                    : 32;
+             uint32_t ba_ts_bitmap_639_608                                    : 32;
+             uint32_t ba_ts_bitmap_671_640                                    : 32;
+             uint32_t ba_ts_bitmap_703_672                                    : 32;
+             uint32_t ba_ts_bitmap_735_704                                    : 32;
+             uint32_t ba_ts_bitmap_767_736                                    : 32;
+             uint32_t ba_ts_bitmap_799_768                                    : 32;
+             uint32_t ba_ts_bitmap_831_800                                    : 32;
+             uint32_t ba_ts_bitmap_863_832                                    : 32;
+             uint32_t ba_ts_bitmap_895_864                                    : 32;
+             uint32_t ba_ts_bitmap_927_896                                    : 32;
+             uint32_t ba_ts_bitmap_959_928                                    : 32;
+             uint32_t ba_ts_bitmap_991_960                                    : 32;
+             uint32_t ba_ts_bitmap_1023_992                                   : 32;
+#else
+             uint32_t reserved_0c                                             :  5,
+                      sta_full_aid                                            : 13,
+                      ba_tid                                                  :  4,
+                      reserved_0b                                             :  3,
+                      ba_bitmap_size                                          :  2,
+                      reserved_0a                                             :  5;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_seq                                               : 16,
+                      ba_ts_ctrl                                              : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+             uint32_t ba_ts_bitmap_287_256                                    : 32;
+             uint32_t ba_ts_bitmap_319_288                                    : 32;
+             uint32_t ba_ts_bitmap_351_320                                    : 32;
+             uint32_t ba_ts_bitmap_383_352                                    : 32;
+             uint32_t ba_ts_bitmap_415_384                                    : 32;
+             uint32_t ba_ts_bitmap_447_416                                    : 32;
+             uint32_t ba_ts_bitmap_479_448                                    : 32;
+             uint32_t ba_ts_bitmap_511_480                                    : 32;
+             uint32_t ba_ts_bitmap_543_512                                    : 32;
+             uint32_t ba_ts_bitmap_575_544                                    : 32;
+             uint32_t ba_ts_bitmap_607_576                                    : 32;
+             uint32_t ba_ts_bitmap_639_608                                    : 32;
+             uint32_t ba_ts_bitmap_671_640                                    : 32;
+             uint32_t ba_ts_bitmap_703_672                                    : 32;
+             uint32_t ba_ts_bitmap_735_704                                    : 32;
+             uint32_t ba_ts_bitmap_767_736                                    : 32;
+             uint32_t ba_ts_bitmap_799_768                                    : 32;
+             uint32_t ba_ts_bitmap_831_800                                    : 32;
+             uint32_t ba_ts_bitmap_863_832                                    : 32;
+             uint32_t ba_ts_bitmap_895_864                                    : 32;
+             uint32_t ba_ts_bitmap_927_896                                    : 32;
+             uint32_t ba_ts_bitmap_959_928                                    : 32;
+             uint32_t ba_ts_bitmap_991_960                                    : 32;
+             uint32_t ba_ts_bitmap_1023_992                                   : 32;
+#endif
+};
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET                                   0x00000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB                                      0
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB                                      4
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK                                     0x0000001f
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET                                0x00000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB                                   5
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB                                   6
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK                                  0x00000060
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET                                   0x00000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB                                      7
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB                                      9
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK                                     0x00000380
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET                                        0x00000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB                                           10
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB                                           13
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK                                          0x00003c00
+
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET                                  0x00000000
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB                                     14
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB                                     26
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK                                    0x07ffc000
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET                                   0x00000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB                                      27
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB                                      31
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK                                     0xf8000000
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET                                    0x00000004
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB                                       0
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB                                       31
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK                                      0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET                                   0x00000008
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB                                      0
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB                                      15
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK                                     0x0000ffff
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET                                    0x00000008
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB                                       16
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB                                       31
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK                                      0xffff0000
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET                                   0x0000000c
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB                                      0
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB                                      31
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK                                     0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET                                    0x00000010
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB                                       0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB                                       15
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK                                      0x0000ffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET                                     0x00000010
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB                                        16
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB                                        31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK                                       0xffff0000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET                             0x00000014
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB                                0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB                                31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK                               0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET                            0x00000018
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB                               0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB                               31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK                              0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET                            0x0000001c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB                               0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB                               31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK                              0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET                           0x00000020
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB                              0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB                              31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK                             0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET                          0x00000024
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET                          0x00000028
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET                          0x0000002c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET                          0x00000030
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET                          0x00000034
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET                          0x00000038
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET                          0x0000003c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET                          0x00000040
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET                          0x00000044
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET                          0x00000048
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET                          0x0000004c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET                          0x00000050
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET                          0x00000054
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET                          0x00000058
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET                          0x0000005c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET                          0x00000060
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET                          0x00000064
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET                          0x00000068
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET                          0x0000006c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET                          0x00000070
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET                          0x00000074
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET                          0x00000078
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET                          0x0000007c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET                          0x00000080
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET                          0x00000084
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET                          0x00000088
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET                          0x0000008c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB                             0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB                             31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK                            0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET                         0x00000090
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB                            0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB                            31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK                           0xffffffff
+
+#endif
diff --git a/hw/peach/v1/rx_frame_bitmap_ack.h b/hw/peach/v1/rx_frame_bitmap_ack.h
new file mode 100644
index 000000000000..c9db51691c31
--- /dev/null
+++ b/hw/peach/v1/rx_frame_bitmap_ack.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_FRAME_BITMAP_ACK_H_
+#define _RX_FRAME_BITMAP_ACK_H_
+
+#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 13
+
+struct rx_frame_bitmap_ack {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t no_bitmap_available                                     :  1,
+                      explicit_ack                                            :  1,
+                      explict_ack_type                                        :  3,
+                      ba_bitmap_size                                          :  2,
+                      reserved_0a                                             :  3,
+                      ba_tid                                                  :  4,
+                      sta_full_aid                                            : 13,
+                      reserved_0b                                             :  5;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_ctrl                                              : 16,
+                      ba_ts_seq                                               : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+#else
+             uint32_t reserved_0b                                             :  5,
+                      sta_full_aid                                            : 13,
+                      ba_tid                                                  :  4,
+                      reserved_0a                                             :  3,
+                      ba_bitmap_size                                          :  2,
+                      explict_ack_type                                        :  3,
+                      explicit_ack                                            :  1,
+                      no_bitmap_available                                     :  1;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ba_ts_seq                                               : 16,
+                      ba_ts_ctrl                                              : 16;
+             uint32_t ba_ts_bitmap_31_0                                       : 32;
+             uint32_t ba_ts_bitmap_63_32                                      : 32;
+             uint32_t ba_ts_bitmap_95_64                                      : 32;
+             uint32_t ba_ts_bitmap_127_96                                     : 32;
+             uint32_t ba_ts_bitmap_159_128                                    : 32;
+             uint32_t ba_ts_bitmap_191_160                                    : 32;
+             uint32_t ba_ts_bitmap_223_192                                    : 32;
+             uint32_t ba_ts_bitmap_255_224                                    : 32;
+#endif
+};
+
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET                              0x00000000
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB                                 0
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB                                 0
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK                                0x00000001
+
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET                                     0x00000000
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB                                        1
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB                                        1
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK                                       0x00000002
+
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET                                 0x00000000
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB                                    2
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB                                    4
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK                                   0x0000001c
+
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET                                   0x00000000
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB                                      5
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB                                      6
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK                                     0x00000060
+
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET                                      0x00000000
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB                                         7
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB                                         9
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK                                        0x00000380
+
+#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET                                           0x00000000
+#define RX_FRAME_BITMAP_ACK_BA_TID_LSB                                              10
+#define RX_FRAME_BITMAP_ACK_BA_TID_MSB                                              13
+#define RX_FRAME_BITMAP_ACK_BA_TID_MASK                                             0x00003c00
+
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET                                     0x00000000
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB                                        14
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB                                        26
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK                                       0x07ffc000
+
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET                                      0x00000000
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB                                         27
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB                                         31
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK                                        0xf8000000
+
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET                                       0x00000004
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB                                          0
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB                                          31
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK                                         0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET                                      0x00000008
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB                                         0
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB                                         15
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK                                        0x0000ffff
+
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET                                       0x00000008
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB                                          16
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB                                          31
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK                                         0xffff0000
+
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET                                      0x0000000c
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB                                         0
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB                                         31
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK                                        0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET                                       0x00000010
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB                                          0
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB                                          15
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK                                         0x0000ffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET                                        0x00000010
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB                                           16
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB                                           31
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK                                          0xffff0000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET                                0x00000014
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB                                   0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB                                   31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK                                  0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET                               0x00000018
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB                                  0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB                                  31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK                                 0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET                               0x0000001c
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB                                  0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB                                  31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK                                 0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET                              0x00000020
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB                                 0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB                                 31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK                                0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET                             0x00000024
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB                                0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB                                31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK                               0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET                             0x00000028
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB                                0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB                                31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK                               0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET                             0x0000002c
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB                                0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB                                31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK                               0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET                             0x00000030
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB                                0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB                                31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK                               0xffffffff
+
+#endif
diff --git a/hw/peach/v1/rx_frame_bitmap_req.h b/hw/peach/v1/rx_frame_bitmap_req.h
new file mode 100644
index 000000000000..160de339bdf6
--- /dev/null
+++ b/hw/peach/v1/rx_frame_bitmap_req.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_FRAME_BITMAP_REQ_H_
+#define _RX_FRAME_BITMAP_REQ_H_
+
+#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 1
+
+struct rx_frame_bitmap_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t explicit_user_request                                   :  1,
+                      user_request_type                                       :  1,
+                      user_number                                             :  6,
+                      sw_peer_id                                              : 16,
+                      tid_specific_request                                    :  1,
+                      requested_tid                                           :  4,
+                      reserved_0                                              :  3;
+#else
+             uint32_t reserved_0                                              :  3,
+                      requested_tid                                           :  4,
+                      tid_specific_request                                    :  1,
+                      sw_peer_id                                              : 16,
+                      user_number                                             :  6,
+                      user_request_type                                       :  1,
+                      explicit_user_request                                   :  1;
+#endif
+};
+
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET                            0x00000000
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB                               0
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB                               0
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK                              0x00000001
+
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET                                0x00000000
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB                                   1
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB                                   1
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK                                  0x00000002
+
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET                                      0x00000000
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB                                         2
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB                                         7
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK                                        0x000000fc
+
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET                                       0x00000000
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB                                          8
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB                                          23
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK                                         0x00ffff00
+
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET                             0x00000000
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB                                24
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB                                24
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK                               0x01000000
+
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET                                    0x00000000
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB                                       25
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB                                       28
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK                                      0x1e000000
+
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET                                       0x00000000
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB                                          29
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB                                          31
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK                                         0xe0000000
+
+#endif
diff --git a/hw/peach/v1/rx_location_info.h b/hw/peach/v1/rx_location_info.h
new file mode 100644
index 000000000000..77089c7cf312
--- /dev/null
+++ b/hw/peach/v1/rx_location_info.h
@@ -0,0 +1,470 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_LOCATION_INFO_H_
+#define _RX_LOCATION_INFO_H_
+
+#define NUM_OF_DWORDS_RX_LOCATION_INFO 28
+
+struct rx_location_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rx_location_info_valid                                  :  1,
+                      rtt_hw_ifft_mode                                        :  1,
+                      rtt_11az_mode                                           :  2,
+                      reserved_0                                              :  4,
+                      rtt_num_fac                                             :  8,
+                      rtt_rx_chain_mask                                       :  8,
+                      rtt_num_streams                                         :  8;
+             uint32_t rtt_first_selected_chain                                :  8,
+                      rtt_second_selected_chain                               :  8,
+                      rtt_cfr_status                                          :  8,
+                      rtt_cir_status                                          :  8;
+             uint32_t rtt_che_buffer_pointer_low32                            : 32;
+             uint32_t rtt_che_buffer_pointer_high8                            :  8,
+                      reserved_3                                              :  8,
+                      rtt_pkt_bw_vht                                          :  4,
+                      rtt_pkt_bw_leg                                          :  4,
+                      rtt_mcs_rate                                            :  8;
+             uint32_t rtt_cfo_measurement                                     : 16,
+                      rtt_preamble_type                                       :  8,
+                      rtt_gi_type                                             :  8;
+             uint32_t rx_start_ts                                             : 32;
+             uint32_t rx_start_ts_upper                                       : 32;
+             uint32_t rx_end_ts                                               : 32;
+             uint32_t gain_chain0                                             : 16,
+                      gain_chain1                                             : 16;
+             uint32_t gain_chain2                                             : 16,
+                      gain_chain3                                             : 16;
+             uint32_t gain_report_status                                      :  8,
+                      rtt_timing_backoff_sel                                  :  8,
+                      rtt_fac_combined                                        : 16;
+             uint32_t rtt_fac_0                                               : 16,
+                      rtt_fac_1                                               : 16;
+             uint32_t rtt_fac_2                                               : 16,
+                      rtt_fac_3                                               : 16;
+             uint32_t rtt_fac_4                                               : 16,
+                      rtt_fac_5                                               : 16;
+             uint32_t rtt_fac_6                                               : 16,
+                      rtt_fac_7                                               : 16;
+             uint32_t rtt_fac_8                                               : 16,
+                      rtt_fac_9                                               : 16;
+             uint32_t rtt_fac_10                                              : 16,
+                      rtt_fac_11                                              : 16;
+             uint32_t rtt_fac_12                                              : 16,
+                      rtt_fac_13                                              : 16;
+             uint32_t rtt_fac_14                                              : 16,
+                      rtt_fac_15                                              : 16;
+             uint32_t rtt_fac_16                                              : 16,
+                      rtt_fac_17                                              : 16;
+             uint32_t rtt_fac_18                                              : 16,
+                      rtt_fac_19                                              : 16;
+             uint32_t rtt_fac_20                                              : 16,
+                      rtt_fac_21                                              : 16;
+             uint32_t rtt_fac_22                                              : 16,
+                      rtt_fac_23                                              : 16;
+             uint32_t rtt_fac_24                                              : 16,
+                      rtt_fac_25                                              : 16;
+             uint32_t rtt_fac_26                                              : 16,
+                      rtt_fac_27                                              : 16;
+             uint32_t rtt_fac_28                                              : 16,
+                      rtt_fac_29                                              : 16;
+             uint32_t rtt_fac_30                                              : 16,
+                      rtt_fac_31                                              : 16;
+             uint32_t reserved_27a                                            : 32;
+#else
+             uint32_t rtt_num_streams                                         :  8,
+                      rtt_rx_chain_mask                                       :  8,
+                      rtt_num_fac                                             :  8,
+                      reserved_0                                              :  4,
+                      rtt_11az_mode                                           :  2,
+                      rtt_hw_ifft_mode                                        :  1,
+                      rx_location_info_valid                                  :  1;
+             uint32_t rtt_cir_status                                          :  8,
+                      rtt_cfr_status                                          :  8,
+                      rtt_second_selected_chain                               :  8,
+                      rtt_first_selected_chain                                :  8;
+             uint32_t rtt_che_buffer_pointer_low32                            : 32;
+             uint32_t rtt_mcs_rate                                            :  8,
+                      rtt_pkt_bw_leg                                          :  4,
+                      rtt_pkt_bw_vht                                          :  4,
+                      reserved_3                                              :  8,
+                      rtt_che_buffer_pointer_high8                            :  8;
+             uint32_t rtt_gi_type                                             :  8,
+                      rtt_preamble_type                                       :  8,
+                      rtt_cfo_measurement                                     : 16;
+             uint32_t rx_start_ts                                             : 32;
+             uint32_t rx_start_ts_upper                                       : 32;
+             uint32_t rx_end_ts                                               : 32;
+             uint32_t gain_chain1                                             : 16,
+                      gain_chain0                                             : 16;
+             uint32_t gain_chain3                                             : 16,
+                      gain_chain2                                             : 16;
+             uint32_t rtt_fac_combined                                        : 16,
+                      rtt_timing_backoff_sel                                  :  8,
+                      gain_report_status                                      :  8;
+             uint32_t rtt_fac_1                                               : 16,
+                      rtt_fac_0                                               : 16;
+             uint32_t rtt_fac_3                                               : 16,
+                      rtt_fac_2                                               : 16;
+             uint32_t rtt_fac_5                                               : 16,
+                      rtt_fac_4                                               : 16;
+             uint32_t rtt_fac_7                                               : 16,
+                      rtt_fac_6                                               : 16;
+             uint32_t rtt_fac_9                                               : 16,
+                      rtt_fac_8                                               : 16;
+             uint32_t rtt_fac_11                                              : 16,
+                      rtt_fac_10                                              : 16;
+             uint32_t rtt_fac_13                                              : 16,
+                      rtt_fac_12                                              : 16;
+             uint32_t rtt_fac_15                                              : 16,
+                      rtt_fac_14                                              : 16;
+             uint32_t rtt_fac_17                                              : 16,
+                      rtt_fac_16                                              : 16;
+             uint32_t rtt_fac_19                                              : 16,
+                      rtt_fac_18                                              : 16;
+             uint32_t rtt_fac_21                                              : 16,
+                      rtt_fac_20                                              : 16;
+             uint32_t rtt_fac_23                                              : 16,
+                      rtt_fac_22                                              : 16;
+             uint32_t rtt_fac_25                                              : 16,
+                      rtt_fac_24                                              : 16;
+             uint32_t rtt_fac_27                                              : 16,
+                      rtt_fac_26                                              : 16;
+             uint32_t rtt_fac_29                                              : 16,
+                      rtt_fac_28                                              : 16;
+             uint32_t rtt_fac_31                                              : 16,
+                      rtt_fac_30                                              : 16;
+             uint32_t reserved_27a                                            : 32;
+#endif
+};
+
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET                              0x00000000
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB                                 0
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB                                 0
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK                                0x00000001
+
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET                                    0x00000000
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB                                       1
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB                                       1
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK                                      0x00000002
+
+#define RX_LOCATION_INFO_RTT_11AZ_MODE_OFFSET                                       0x00000000
+#define RX_LOCATION_INFO_RTT_11AZ_MODE_LSB                                          2
+#define RX_LOCATION_INFO_RTT_11AZ_MODE_MSB                                          3
+#define RX_LOCATION_INFO_RTT_11AZ_MODE_MASK                                         0x0000000c
+
+#define RX_LOCATION_INFO_RESERVED_0_OFFSET                                          0x00000000
+#define RX_LOCATION_INFO_RESERVED_0_LSB                                             4
+#define RX_LOCATION_INFO_RESERVED_0_MSB                                             7
+#define RX_LOCATION_INFO_RESERVED_0_MASK                                            0x000000f0
+
+#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET                                         0x00000000
+#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB                                            8
+#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB                                            15
+#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK                                           0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET                                   0x00000000
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB                                      16
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB                                      23
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK                                     0x00ff0000
+
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET                                     0x00000000
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB                                        24
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB                                        31
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK                                       0xff000000
+
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET                            0x00000004
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB                               0
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB                               7
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK                              0x000000ff
+
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET                           0x00000004
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB                              8
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB                              15
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK                             0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET                                      0x00000004
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB                                         16
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB                                         23
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK                                        0x00ff0000
+
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET                                      0x00000004
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB                                         24
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB                                         31
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK                                        0xff000000
+
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET                        0x00000008
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB                           0
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB                           31
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK                          0xffffffff
+
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET                        0x0000000c
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB                           0
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB                           7
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK                          0x000000ff
+
+#define RX_LOCATION_INFO_RESERVED_3_OFFSET                                          0x0000000c
+#define RX_LOCATION_INFO_RESERVED_3_LSB                                             8
+#define RX_LOCATION_INFO_RESERVED_3_MSB                                             15
+#define RX_LOCATION_INFO_RESERVED_3_MASK                                            0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET                                      0x0000000c
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB                                         16
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB                                         19
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK                                        0x000f0000
+
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET                                      0x0000000c
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB                                         20
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB                                         23
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK                                        0x00f00000
+
+#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET                                        0x0000000c
+#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB                                           24
+#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB                                           31
+#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK                                          0xff000000
+
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET                                 0x00000010
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB                                    0
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB                                    15
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK                                   0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET                                   0x00000010
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB                                      16
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB                                      23
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK                                     0x00ff0000
+
+#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET                                         0x00000010
+#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB                                            24
+#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB                                            31
+#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK                                           0xff000000
+
+#define RX_LOCATION_INFO_RX_START_TS_OFFSET                                         0x00000014
+#define RX_LOCATION_INFO_RX_START_TS_LSB                                            0
+#define RX_LOCATION_INFO_RX_START_TS_MSB                                            31
+#define RX_LOCATION_INFO_RX_START_TS_MASK                                           0xffffffff
+
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET                                   0x00000018
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB                                      0
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB                                      31
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK                                     0xffffffff
+
+#define RX_LOCATION_INFO_RX_END_TS_OFFSET                                           0x0000001c
+#define RX_LOCATION_INFO_RX_END_TS_LSB                                              0
+#define RX_LOCATION_INFO_RX_END_TS_MSB                                              31
+#define RX_LOCATION_INFO_RX_END_TS_MASK                                             0xffffffff
+
+#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET                                         0x00000020
+#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB                                            0
+#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB                                            15
+#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK                                           0x0000ffff
+
+#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET                                         0x00000020
+#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB                                            16
+#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB                                            31
+#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK                                           0xffff0000
+
+#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET                                         0x00000024
+#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB                                            0
+#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB                                            15
+#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK                                           0x0000ffff
+
+#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET                                         0x00000024
+#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB                                            16
+#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB                                            31
+#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK                                           0xffff0000
+
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET                                  0x00000028
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB                                     0
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB                                     7
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK                                    0x000000ff
+
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET                              0x00000028
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB                                 8
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB                                 15
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK                                0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET                                    0x00000028
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB                                       16
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB                                       31
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK                                      0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET                                           0x0000002c
+#define RX_LOCATION_INFO_RTT_FAC_0_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_0_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_0_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET                                           0x0000002c
+#define RX_LOCATION_INFO_RTT_FAC_1_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_1_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_1_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET                                           0x00000030
+#define RX_LOCATION_INFO_RTT_FAC_2_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_2_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_2_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET                                           0x00000030
+#define RX_LOCATION_INFO_RTT_FAC_3_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_3_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_3_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET                                           0x00000034
+#define RX_LOCATION_INFO_RTT_FAC_4_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_4_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_4_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET                                           0x00000034
+#define RX_LOCATION_INFO_RTT_FAC_5_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_5_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_5_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET                                           0x00000038
+#define RX_LOCATION_INFO_RTT_FAC_6_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_6_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_6_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET                                           0x00000038
+#define RX_LOCATION_INFO_RTT_FAC_7_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_7_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_7_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET                                           0x0000003c
+#define RX_LOCATION_INFO_RTT_FAC_8_LSB                                              0
+#define RX_LOCATION_INFO_RTT_FAC_8_MSB                                              15
+#define RX_LOCATION_INFO_RTT_FAC_8_MASK                                             0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET                                           0x0000003c
+#define RX_LOCATION_INFO_RTT_FAC_9_LSB                                              16
+#define RX_LOCATION_INFO_RTT_FAC_9_MSB                                              31
+#define RX_LOCATION_INFO_RTT_FAC_9_MASK                                             0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET                                          0x00000040
+#define RX_LOCATION_INFO_RTT_FAC_10_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_10_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_10_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET                                          0x00000040
+#define RX_LOCATION_INFO_RTT_FAC_11_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_11_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_11_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET                                          0x00000044
+#define RX_LOCATION_INFO_RTT_FAC_12_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_12_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_12_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET                                          0x00000044
+#define RX_LOCATION_INFO_RTT_FAC_13_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_13_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_13_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET                                          0x00000048
+#define RX_LOCATION_INFO_RTT_FAC_14_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_14_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_14_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET                                          0x00000048
+#define RX_LOCATION_INFO_RTT_FAC_15_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_15_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_15_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET                                          0x0000004c
+#define RX_LOCATION_INFO_RTT_FAC_16_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_16_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_16_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET                                          0x0000004c
+#define RX_LOCATION_INFO_RTT_FAC_17_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_17_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_17_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET                                          0x00000050
+#define RX_LOCATION_INFO_RTT_FAC_18_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_18_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_18_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET                                          0x00000050
+#define RX_LOCATION_INFO_RTT_FAC_19_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_19_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_19_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET                                          0x00000054
+#define RX_LOCATION_INFO_RTT_FAC_20_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_20_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_20_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET                                          0x00000054
+#define RX_LOCATION_INFO_RTT_FAC_21_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_21_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_21_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET                                          0x00000058
+#define RX_LOCATION_INFO_RTT_FAC_22_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_22_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_22_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET                                          0x00000058
+#define RX_LOCATION_INFO_RTT_FAC_23_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_23_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_23_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET                                          0x0000005c
+#define RX_LOCATION_INFO_RTT_FAC_24_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_24_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_24_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET                                          0x0000005c
+#define RX_LOCATION_INFO_RTT_FAC_25_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_25_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_25_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET                                          0x00000060
+#define RX_LOCATION_INFO_RTT_FAC_26_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_26_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_26_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET                                          0x00000060
+#define RX_LOCATION_INFO_RTT_FAC_27_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_27_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_27_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET                                          0x00000064
+#define RX_LOCATION_INFO_RTT_FAC_28_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_28_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_28_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET                                          0x00000064
+#define RX_LOCATION_INFO_RTT_FAC_29_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_29_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_29_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET                                          0x00000068
+#define RX_LOCATION_INFO_RTT_FAC_30_LSB                                             0
+#define RX_LOCATION_INFO_RTT_FAC_30_MSB                                             15
+#define RX_LOCATION_INFO_RTT_FAC_30_MASK                                            0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET                                          0x00000068
+#define RX_LOCATION_INFO_RTT_FAC_31_LSB                                             16
+#define RX_LOCATION_INFO_RTT_FAC_31_MSB                                             31
+#define RX_LOCATION_INFO_RTT_FAC_31_MASK                                            0xffff0000
+
+#define RX_LOCATION_INFO_RESERVED_27A_OFFSET                                        0x0000006c
+#define RX_LOCATION_INFO_RESERVED_27A_LSB                                           0
+#define RX_LOCATION_INFO_RESERVED_27A_MSB                                           31
+#define RX_LOCATION_INFO_RESERVED_27A_MASK                                          0xffffffff
+
+#endif
diff --git a/hw/peach/v1/rx_mpdu_desc_info.h b/hw/peach/v1/rx_mpdu_desc_info.h
new file mode 100644
index 000000000000..c88ba6a17199
--- /dev/null
+++ b/hw/peach/v1/rx_mpdu_desc_info.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MPDU_DESC_INFO_H_
+#define _RX_MPDU_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2
+
+struct rx_mpdu_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t msdu_count                                              :  8,
+                      fragment_flag                                           :  1,
+                      mpdu_retry_bit                                          :  1,
+                      ampdu_flag                                              :  1,
+                      bar_frame                                               :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      raw_mpdu                                                :  1,
+                      more_fragment_flag                                      :  1,
+                      src_info                                                : 12,
+                      mpdu_qos_control_valid                                  :  1,
+                      tid                                                     :  4;
+             uint32_t peer_meta_data                                          : 32;
+#else
+             uint32_t tid                                                     :  4,
+                      mpdu_qos_control_valid                                  :  1,
+                      src_info                                                : 12,
+                      more_fragment_flag                                      :  1,
+                      raw_mpdu                                                :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      bar_frame                                               :  1,
+                      ampdu_flag                                              :  1,
+                      mpdu_retry_bit                                          :  1,
+                      fragment_flag                                           :  1,
+                      msdu_count                                              :  8;
+             uint32_t peer_meta_data                                          : 32;
+#endif
+};
+
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET                                         0x00000000
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB                                            0
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB                                            7
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK                                           0x000000ff
+
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET                                      0x00000000
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB                                         8
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB                                         8
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK                                        0x00000100
+
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET                                     0x00000000
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB                                        9
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB                                        9
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK                                       0x00000200
+
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET                                         0x00000000
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB                                            10
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB                                            10
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK                                           0x00000400
+
+#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET                                          0x00000000
+#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB                                             11
+#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB                                             11
+#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK                                            0x00000800
+
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET                       0x00000000
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB                          12
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB                          12
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK                         0x00001000
+
+#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET                                           0x00000000
+#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB                                              13
+#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB                                              13
+#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK                                             0x00002000
+
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET                                 0x00000000
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB                                    14
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB                                    14
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK                                   0x00004000
+
+#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET                                           0x00000000
+#define RX_MPDU_DESC_INFO_SRC_INFO_LSB                                              15
+#define RX_MPDU_DESC_INFO_SRC_INFO_MSB                                              26
+#define RX_MPDU_DESC_INFO_SRC_INFO_MASK                                             0x07ff8000
+
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET                             0x00000000
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB                                27
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB                                27
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK                               0x08000000
+
+#define RX_MPDU_DESC_INFO_TID_OFFSET                                                0x00000000
+#define RX_MPDU_DESC_INFO_TID_LSB                                                   28
+#define RX_MPDU_DESC_INFO_TID_MSB                                                   31
+#define RX_MPDU_DESC_INFO_TID_MASK                                                  0xf0000000
+
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET                                     0x00000004
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB                                        0
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB                                        31
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK                                       0xffffffff
+
+#endif
diff --git a/hw/peach/v1/rx_mpdu_details.h b/hw/peach/v1/rx_mpdu_details.h
new file mode 100644
index 000000000000..9c909a87e2c1
--- /dev/null
+++ b/hw/peach/v1/rx_mpdu_details.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MPDU_DETAILS_H_
+#define _RX_MPDU_DETAILS_H_
+
+#include "rx_mpdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4
+
+struct rx_mpdu_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          msdu_link_desc_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+#else
+             struct   buffer_addr_info                                          msdu_link_desc_addr_info;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+#endif
+};
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET            0x00000000
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB               0
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB               31
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK              0xffffffff
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET           0x00000004
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB              0
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB              7
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK             0x000000ff
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET       0x00000004
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB          8
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB          11
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK         0x00000f00
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET            0x00000004
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB               12
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB               31
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK              0xfffff000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET                 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB                    0
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB                    7
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK                   0x000000ff
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET              0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB                 8
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB                 8
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK                0x00000100
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET             0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB                9
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB                9
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK               0x00000200
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET                 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB                    10
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB                    10
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK                   0x00000400
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET                  0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB                     11
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB                     11
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK                    0x00000800
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB  12
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB  12
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET                   0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB                      13
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB                      13
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK                     0x00002000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET         0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB            14
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB            14
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK           0x00004000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET                   0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB                      15
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB                      26
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK                     0x07ff8000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET     0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB        27
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB        27
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK       0x08000000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET                        0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB                           28
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB                           31
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK                          0xf0000000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET             0x0000000c
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB                0
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB                31
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK               0xffffffff
+
+#endif
diff --git a/hw/peach/v1/rx_mpdu_end.h b/hw/peach/v1/rx_mpdu_end.h
new file mode 100644
index 000000000000..26824a03ee3a
--- /dev/null
+++ b/hw/peach/v1/rx_mpdu_end.h
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MPDU_END_H_
+#define _RX_MPDU_END_H_
+
+#define NUM_OF_DWORDS_RX_MPDU_END 4
+
+struct rx_mpdu_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+             uint32_t reserved_1a                                             : 11,
+                      unsup_ktype_short_frame                                 :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      overflow_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      tkip_mic_err                                            :  1,
+                      decrypt_err                                             :  1,
+                      unencrypted_frame_err                                   :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      fcs_err                                                 :  1,
+                      msdu_length_err                                         :  1,
+                      rxdma0_destination_ring                                 :  3,
+                      rxdma1_destination_ring                                 :  3,
+                      decrypt_status_code                                     :  3,
+                      rx_bitmap_not_updated                                   :  1,
+                      reserved_1b                                             :  1;
+             uint32_t reserved_2a                                             : 15,
+                      rxpcu_mgmt_sequence_nr_valid                            :  1,
+                      rxpcu_mgmt_sequence_nr                                  : 16;
+             uint32_t __reserved_g_0002                                       : 32;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t reserved_1b                                             :  1,
+                      rx_bitmap_not_updated                                   :  1,
+                      decrypt_status_code                                     :  3,
+                      rxdma1_destination_ring                                 :  3,
+                      rxdma0_destination_ring                                 :  3,
+                      msdu_length_err                                         :  1,
+                      fcs_err                                                 :  1,
+                      pn_fields_contain_valid_info                            :  1,
+                      unencrypted_frame_err                                   :  1,
+                      decrypt_err                                             :  1,
+                      tkip_mic_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      overflow_err                                            :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      unsup_ktype_short_frame                                 :  1,
+                      reserved_1a                                             : 11;
+             uint32_t rxpcu_mgmt_sequence_nr                                  : 16,
+                      rxpcu_mgmt_sequence_nr_valid                            :  1,
+                      reserved_2a                                             : 15;
+             uint32_t __reserved_g_0002                                       : 32;
+#endif
+};
+
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                            0x00000000
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                               0
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                               1
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                              0x00000003
+
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET                                        0x00000000
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB                                           2
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB                                           8
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK                                          0x000001fc
+
+#define RX_MPDU_END_RESERVED_0_OFFSET                                               0x00000000
+#define RX_MPDU_END_RESERVED_0_LSB                                                  9
+#define RX_MPDU_END_RESERVED_0_MSB                                                  15
+#define RX_MPDU_END_RESERVED_0_MASK                                                 0x0000fe00
+
+#define RX_MPDU_END_PHY_PPDU_ID_OFFSET                                              0x00000000
+#define RX_MPDU_END_PHY_PPDU_ID_LSB                                                 16
+#define RX_MPDU_END_PHY_PPDU_ID_MSB                                                 31
+#define RX_MPDU_END_PHY_PPDU_ID_MASK                                                0xffff0000
+
+#define RX_MPDU_END_RESERVED_1A_OFFSET                                              0x00000004
+#define RX_MPDU_END_RESERVED_1A_LSB                                                 0
+#define RX_MPDU_END_RESERVED_1A_MSB                                                 10
+#define RX_MPDU_END_RESERVED_1A_MASK                                                0x000007ff
+
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET                                  0x00000004
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB                                     11
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB                                     11
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK                                    0x00000800
+
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET                                     0x00000004
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB                                        12
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB                                        12
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK                                       0x00001000
+
+#define RX_MPDU_END_OVERFLOW_ERR_OFFSET                                             0x00000004
+#define RX_MPDU_END_OVERFLOW_ERR_LSB                                                13
+#define RX_MPDU_END_OVERFLOW_ERR_MSB                                                13
+#define RX_MPDU_END_OVERFLOW_ERR_MASK                                               0x00002000
+
+#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET                                          0x00000004
+#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB                                             14
+#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB                                             14
+#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK                                            0x00004000
+
+#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET                                             0x00000004
+#define RX_MPDU_END_TKIP_MIC_ERR_LSB                                                15
+#define RX_MPDU_END_TKIP_MIC_ERR_MSB                                                15
+#define RX_MPDU_END_TKIP_MIC_ERR_MASK                                               0x00008000
+
+#define RX_MPDU_END_DECRYPT_ERR_OFFSET                                              0x00000004
+#define RX_MPDU_END_DECRYPT_ERR_LSB                                                 16
+#define RX_MPDU_END_DECRYPT_ERR_MSB                                                 16
+#define RX_MPDU_END_DECRYPT_ERR_MASK                                                0x00010000
+
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET                                    0x00000004
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB                                       17
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB                                       17
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK                                      0x00020000
+
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET                             0x00000004
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB                                18
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB                                18
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK                               0x00040000
+
+#define RX_MPDU_END_FCS_ERR_OFFSET                                                  0x00000004
+#define RX_MPDU_END_FCS_ERR_LSB                                                     19
+#define RX_MPDU_END_FCS_ERR_MSB                                                     19
+#define RX_MPDU_END_FCS_ERR_MASK                                                    0x00080000
+
+#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET                                          0x00000004
+#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB                                             20
+#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB                                             20
+#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK                                            0x00100000
+
+#define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET                                  0x00000004
+#define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB                                     21
+#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB                                     23
+#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK                                    0x00e00000
+
+#define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET                                  0x00000004
+#define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB                                     24
+#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB                                     26
+#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK                                    0x07000000
+
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET                                      0x00000004
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB                                         27
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB                                         29
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK                                        0x38000000
+
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET                                    0x00000004
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB                                       30
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB                                       30
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK                                      0x40000000
+
+#define RX_MPDU_END_RESERVED_1B_OFFSET                                              0x00000004
+#define RX_MPDU_END_RESERVED_1B_LSB                                                 31
+#define RX_MPDU_END_RESERVED_1B_MSB                                                 31
+#define RX_MPDU_END_RESERVED_1B_MASK                                                0x80000000
+
+#define RX_MPDU_END_RESERVED_2A_OFFSET                                              0x00000008
+#define RX_MPDU_END_RESERVED_2A_LSB                                                 0
+#define RX_MPDU_END_RESERVED_2A_MSB                                                 14
+#define RX_MPDU_END_RESERVED_2A_MASK                                                0x00007fff
+
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET                             0x00000008
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB                                15
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB                                15
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK                               0x00008000
+
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET                                   0x00000008
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB                                      16
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB                                      31
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK                                     0xffff0000
+
+#endif
diff --git a/hw/peach/v1/rx_mpdu_info.h b/hw/peach/v1/rx_mpdu_info.h
new file mode 100644
index 000000000000..2231090a035a
--- /dev/null
+++ b/hw/peach/v1/rx_mpdu_info.h
@@ -0,0 +1,835 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MPDU_INFO_H_
+#define _RX_MPDU_INFO_H_
+
+#include "rxpt_classify_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_INFO 30
+
+struct rx_mpdu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rxpt_classify_info                                        rxpt_classify_info_details;
+             uint32_t epd_en                                                  :  1,
+                      all_frames_shall_be_encrypted                           :  1,
+                      encrypt_type                                            :  4,
+                      wep_key_width_for_variable_key                          :  2,
+                      __reserved_g_0003                                                :  2,
+                      bssid_hit                                               :  1,
+                      bssid_number                                            :  4,
+                      tid                                                     :  4,
+                      reserved_7a                                             : 13;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t rx_reo_queue_desc_addr_39_32                            :  8,
+                      receive_queue_number                                    : 16,
+                      pre_delim_err_warning                                   :  1,
+                      first_delim_err                                         :  1,
+                      reserved_2a                                             :  6;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t mpdu_frame_control_valid                                :  1,
+                      mpdu_duration_valid                                     :  1,
+                      mac_addr_ad1_valid                                      :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      mac_addr_ad3_valid                                      :  1,
+                      mac_addr_ad4_valid                                      :  1,
+                      mpdu_sequence_control_valid                             :  1,
+                      mpdu_qos_control_valid                                  :  1,
+                      mpdu_ht_control_valid                                   :  1,
+                      frame_encryption_info_valid                             :  1,
+                      mpdu_fragment_number                                    :  4,
+                      more_fragment_flag                                      :  1,
+                      reserved_11a                                            :  1,
+                      fr_ds                                                   :  1,
+                      to_ds                                                   :  1,
+                      encrypted                                               :  1,
+                      mpdu_retry                                              :  1,
+                      mpdu_sequence_number                                    : 12;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t ast_index                                               : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      ndp_frame                                               :  1,
+                      phy_err                                                 :  1,
+                      phy_err_during_mpdu_header                              :  1,
+                      protocol_version_err                                    :  1,
+                      ast_based_lookup_valid                                  :  1,
+                      __reserved_g_0005                                                 :  1,
+                      reserved_9a                                             :  1,
+                      phy_ppdu_id                                             : 16;
+             uint32_t key_id_octet                                            :  8,
+                      new_peer_entry                                          :  1,
+                      decrypt_needed                                          :  1,
+                      decap_type                                              :  2,
+                      rx_insert_vlan_c_tag_padding                            :  1,
+                      rx_insert_vlan_s_tag_padding                            :  1,
+                      strip_vlan_c_tag_decap                                  :  1,
+                      strip_vlan_s_tag_decap                                  :  1,
+                      pre_delim_count                                         : 12,
+                      ampdu_flag                                              :  1,
+                      bar_frame                                               :  1,
+                      raw_mpdu                                                :  1,
+                      reserved_12                                             :  1;
+             uint32_t mpdu_length                                             : 14,
+                      first_mpdu                                              :  1,
+                      mcast_bcast                                             :  1,
+                      ast_index_not_found                                     :  1,
+                      ast_index_timeout                                       :  1,
+                      power_mgmt                                              :  1,
+                      non_qos                                                 :  1,
+                      null_data                                               :  1,
+                      mgmt_type                                               :  1,
+                      ctrl_type                                               :  1,
+                      more_data                                               :  1,
+                      eosp                                                    :  1,
+                      fragment_flag                                           :  1,
+                      order                                                   :  1,
+                      u_apsd_trigger                                          :  1,
+                      encrypt_required                                        :  1,
+                      directed                                                :  1,
+                      amsdu_present                                           :  1,
+                      reserved_13                                             :  1;
+             uint32_t mpdu_frame_control_field                                : 16,
+                      mpdu_duration_field                                     : 16;
+             uint32_t mac_addr_ad1_31_0                                       : 32;
+             uint32_t mac_addr_ad1_47_32                                      : 16,
+                      mac_addr_ad2_15_0                                       : 16;
+             uint32_t mac_addr_ad2_47_16                                      : 32;
+             uint32_t mac_addr_ad3_31_0                                       : 32;
+             uint32_t mac_addr_ad3_47_32                                      : 16,
+                      mpdu_sequence_control_field                             : 16;
+             uint32_t mac_addr_ad4_31_0                                       : 32;
+             uint32_t mac_addr_ad4_47_32                                      : 16,
+                      mpdu_qos_control_field                                  : 16;
+             uint32_t mpdu_ht_control_field                                   : 32;
+             uint32_t vdev_id                                                 :  8,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      src_info                                                : 12,
+                      reserved_23a                                            :  1,
+                      __reserved_g_0006                                       :  1;
+             uint32_t __reserved_g_0007                                       : 32;
+             uint32_t __reserved_g_0008                                       : 16,
+                      __reserved_g_0009                                       : 16;
+             uint32_t __reserved_g_0010                                       : 32;
+             uint32_t authorized_to_send_wds                                  :  1,
+                      reserved_27a                                            : 31;
+             uint32_t reserved_28a                                            : 32;
+             uint32_t reserved_29a                                            : 32;
+#else
+             struct   rxpt_classify_info                                        rxpt_classify_info_details;
+             uint32_t reserved_7a                                             : 13,
+                      tid                                                     :  4,
+                      bssid_number                                            :  4,
+                      bssid_hit                                               :  1,
+                      __reserved_g_0003                                                :  2,
+                      wep_key_width_for_variable_key                          :  2,
+                      encrypt_type                                            :  4,
+                      all_frames_shall_be_encrypted                           :  1,
+                      epd_en                                                  :  1;
+             uint32_t rx_reo_queue_desc_addr_31_0                             : 32;
+             uint32_t reserved_2a                                             :  6,
+                      first_delim_err                                         :  1,
+                      pre_delim_err_warning                                   :  1,
+                      receive_queue_number                                    : 16,
+                      rx_reo_queue_desc_addr_39_32                            :  8;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t mpdu_sequence_number                                    : 12,
+                      mpdu_retry                                              :  1,
+                      encrypted                                               :  1,
+                      to_ds                                                   :  1,
+                      fr_ds                                                   :  1,
+                      reserved_11a                                            :  1,
+                      more_fragment_flag                                      :  1,
+                      mpdu_fragment_number                                    :  4,
+                      frame_encryption_info_valid                             :  1,
+                      mpdu_ht_control_valid                                   :  1,
+                      mpdu_qos_control_valid                                  :  1,
+                      mpdu_sequence_control_valid                             :  1,
+                      mac_addr_ad4_valid                                      :  1,
+                      mac_addr_ad3_valid                                      :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      mac_addr_ad1_valid                                      :  1,
+                      mpdu_duration_valid                                     :  1,
+                      mpdu_frame_control_valid                                :  1;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t sw_peer_id                                              : 16,
+                      ast_index                                               : 16;
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_9a                                             :  1,
+                      __reserved_g_0005                                                 :  1,
+                      ast_based_lookup_valid                                  :  1,
+                      protocol_version_err                                    :  1,
+                      phy_err_during_mpdu_header                              :  1,
+                      phy_err                                                 :  1,
+                      ndp_frame                                               :  1,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t reserved_12                                             :  1,
+                      raw_mpdu                                                :  1,
+                      bar_frame                                               :  1,
+                      ampdu_flag                                              :  1,
+                      pre_delim_count                                         : 12,
+                      strip_vlan_s_tag_decap                                  :  1,
+                      strip_vlan_c_tag_decap                                  :  1,
+                      rx_insert_vlan_s_tag_padding                            :  1,
+                      rx_insert_vlan_c_tag_padding                            :  1,
+                      decap_type                                              :  2,
+                      decrypt_needed                                          :  1,
+                      new_peer_entry                                          :  1,
+                      key_id_octet                                            :  8;
+             uint32_t reserved_13                                             :  1,
+                      amsdu_present                                           :  1,
+                      directed                                                :  1,
+                      encrypt_required                                        :  1,
+                      u_apsd_trigger                                          :  1,
+                      order                                                   :  1,
+                      fragment_flag                                           :  1,
+                      eosp                                                    :  1,
+                      more_data                                               :  1,
+                      ctrl_type                                               :  1,
+                      mgmt_type                                               :  1,
+                      null_data                                               :  1,
+                      non_qos                                                 :  1,
+                      power_mgmt                                              :  1,
+                      ast_index_timeout                                       :  1,
+                      ast_index_not_found                                     :  1,
+                      mcast_bcast                                             :  1,
+                      first_mpdu                                              :  1,
+                      mpdu_length                                             : 14;
+             uint32_t mpdu_duration_field                                     : 16,
+                      mpdu_frame_control_field                                : 16;
+             uint32_t mac_addr_ad1_31_0                                       : 32;
+             uint32_t mac_addr_ad2_15_0                                       : 16,
+                      mac_addr_ad1_47_32                                      : 16;
+             uint32_t mac_addr_ad2_47_16                                      : 32;
+             uint32_t mac_addr_ad3_31_0                                       : 32;
+             uint32_t mpdu_sequence_control_field                             : 16,
+                      mac_addr_ad3_47_32                                      : 16;
+             uint32_t mac_addr_ad4_31_0                                       : 32;
+             uint32_t mpdu_qos_control_field                                  : 16,
+                      mac_addr_ad4_47_32                                      : 16;
+             uint32_t mpdu_ht_control_field                                   : 32;
+             uint32_t __reserved_g_0006                                       :  1,
+                      reserved_23a                                            :  1,
+                      src_info                                                : 12,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      vdev_id                                                 :  8;
+             uint32_t __reserved_g_0007                                       : 32;
+             uint32_t __reserved_g_0009                                       : 16,
+                      __reserved_g_0008                                       : 16;
+             uint32_t __reserved_g_0010                                       : 32;
+             uint32_t reserved_27a                                            : 31,
+                      authorized_to_send_wds                                  :  1;
+             uint32_t reserved_28a                                            : 32;
+             uint32_t reserved_29a                                            : 32;
+#endif
+};
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET   0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB      0
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB      4
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK     0x0000001f
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET             0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB                5
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB                6
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK               0x00000060
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET    0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB       7
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB       7
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK      0x00000080
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET  0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB     8
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB     8
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK    0x00000100
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET  0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB     9
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB     9
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK    0x00000200
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET        0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB           10
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB           10
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK          0x00000400
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB    11
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB    13
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK   0x00003800
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET       0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB          17
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB          17
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK         0x00020000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET       0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB          18
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB          18
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK         0x00040000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET            0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB               19
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB               19
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK              0x00080000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET                      0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB                         20
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB                         20
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK                        0x00100000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET           0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB              21
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB              21
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK             0x00200000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET            0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB               22
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB               22
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK              0x00400000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET                  0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB                     23
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB                     31
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK                    0xff800000
+
+#define RX_MPDU_INFO_EPD_EN_OFFSET                                                  0x00000004
+#define RX_MPDU_INFO_EPD_EN_LSB                                                     0
+#define RX_MPDU_INFO_EPD_EN_MSB                                                     0
+#define RX_MPDU_INFO_EPD_EN_MASK                                                    0x00000001
+
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET                           0x00000004
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB                              1
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB                              1
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK                             0x00000002
+
+#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET                                            0x00000004
+#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB                                               2
+#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB                                               5
+#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK                                              0x0000003c
+
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET                          0x00000004
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB                             6
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB                             7
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK                            0x000000c0
+
+#define RX_MPDU_INFO_BSSID_HIT_OFFSET                                               0x00000004
+#define RX_MPDU_INFO_BSSID_HIT_LSB                                                  10
+#define RX_MPDU_INFO_BSSID_HIT_MSB                                                  10
+#define RX_MPDU_INFO_BSSID_HIT_MASK                                                 0x00000400
+
+#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET                                            0x00000004
+#define RX_MPDU_INFO_BSSID_NUMBER_LSB                                               11
+#define RX_MPDU_INFO_BSSID_NUMBER_MSB                                               14
+#define RX_MPDU_INFO_BSSID_NUMBER_MASK                                              0x00007800
+
+#define RX_MPDU_INFO_TID_OFFSET                                                     0x00000004
+#define RX_MPDU_INFO_TID_LSB                                                        15
+#define RX_MPDU_INFO_TID_MSB                                                        18
+#define RX_MPDU_INFO_TID_MASK                                                       0x00078000
+
+#define RX_MPDU_INFO_RESERVED_7A_OFFSET                                             0x00000004
+#define RX_MPDU_INFO_RESERVED_7A_LSB                                                19
+#define RX_MPDU_INFO_RESERVED_7A_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_7A_MASK                                               0xfff80000
+
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET                             0x00000008
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB                                0
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB                                31
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK                               0xffffffff
+
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET                            0x0000000c
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB                               0
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB                               7
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK                              0x000000ff
+
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET                                    0x0000000c
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB                                       8
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB                                       23
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK                                      0x00ffff00
+
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET                                   0x0000000c
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB                                      24
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB                                      24
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK                                     0x01000000
+
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET                                         0x0000000c
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB                                            25
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB                                            25
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK                                           0x02000000
+
+#define RX_MPDU_INFO_RESERVED_2A_OFFSET                                             0x0000000c
+#define RX_MPDU_INFO_RESERVED_2A_LSB                                                26
+#define RX_MPDU_INFO_RESERVED_2A_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_2A_MASK                                               0xfc000000
+
+#define RX_MPDU_INFO_PN_31_0_OFFSET                                                 0x00000010
+#define RX_MPDU_INFO_PN_31_0_LSB                                                    0
+#define RX_MPDU_INFO_PN_31_0_MSB                                                    31
+#define RX_MPDU_INFO_PN_31_0_MASK                                                   0xffffffff
+
+#define RX_MPDU_INFO_PN_63_32_OFFSET                                                0x00000014
+#define RX_MPDU_INFO_PN_63_32_LSB                                                   0
+#define RX_MPDU_INFO_PN_63_32_MSB                                                   31
+#define RX_MPDU_INFO_PN_63_32_MASK                                                  0xffffffff
+
+#define RX_MPDU_INFO_PN_95_64_OFFSET                                                0x00000018
+#define RX_MPDU_INFO_PN_95_64_LSB                                                   0
+#define RX_MPDU_INFO_PN_95_64_MSB                                                   31
+#define RX_MPDU_INFO_PN_95_64_MASK                                                  0xffffffff
+
+#define RX_MPDU_INFO_PN_127_96_OFFSET                                               0x0000001c
+#define RX_MPDU_INFO_PN_127_96_LSB                                                  0
+#define RX_MPDU_INFO_PN_127_96_MSB                                                  31
+#define RX_MPDU_INFO_PN_127_96_MASK                                                 0xffffffff
+
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET                                0x00000020
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB                                   0
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB                                   0
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK                                  0x00000001
+
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET                                     0x00000020
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB                                        1
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB                                        1
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK                                       0x00000002
+
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB                                         2
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB                                         2
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK                                        0x00000004
+
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB                                         3
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB                                         3
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK                                        0x00000008
+
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB                                         4
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB                                         4
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK                                        0x00000010
+
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB                                         5
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB                                         5
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK                                        0x00000020
+
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET                             0x00000020
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB                                6
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB                                6
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK                               0x00000040
+
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET                                  0x00000020
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB                                     7
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB                                     7
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK                                    0x00000080
+
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET                                   0x00000020
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB                                      8
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB                                      8
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK                                     0x00000100
+
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET                             0x00000020
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB                                9
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB                                9
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK                               0x00000200
+
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET                                    0x00000020
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB                                       10
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB                                       13
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK                                      0x00003c00
+
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET                                      0x00000020
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB                                         14
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB                                         14
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK                                        0x00004000
+
+#define RX_MPDU_INFO_RESERVED_11A_OFFSET                                            0x00000020
+#define RX_MPDU_INFO_RESERVED_11A_LSB                                               15
+#define RX_MPDU_INFO_RESERVED_11A_MSB                                               15
+#define RX_MPDU_INFO_RESERVED_11A_MASK                                              0x00008000
+
+#define RX_MPDU_INFO_FR_DS_OFFSET                                                   0x00000020
+#define RX_MPDU_INFO_FR_DS_LSB                                                      16
+#define RX_MPDU_INFO_FR_DS_MSB                                                      16
+#define RX_MPDU_INFO_FR_DS_MASK                                                     0x00010000
+
+#define RX_MPDU_INFO_TO_DS_OFFSET                                                   0x00000020
+#define RX_MPDU_INFO_TO_DS_LSB                                                      17
+#define RX_MPDU_INFO_TO_DS_MSB                                                      17
+#define RX_MPDU_INFO_TO_DS_MASK                                                     0x00020000
+
+#define RX_MPDU_INFO_ENCRYPTED_OFFSET                                               0x00000020
+#define RX_MPDU_INFO_ENCRYPTED_LSB                                                  18
+#define RX_MPDU_INFO_ENCRYPTED_MSB                                                  18
+#define RX_MPDU_INFO_ENCRYPTED_MASK                                                 0x00040000
+
+#define RX_MPDU_INFO_MPDU_RETRY_OFFSET                                              0x00000020
+#define RX_MPDU_INFO_MPDU_RETRY_LSB                                                 19
+#define RX_MPDU_INFO_MPDU_RETRY_MSB                                                 19
+#define RX_MPDU_INFO_MPDU_RETRY_MASK                                                0x00080000
+
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET                                    0x00000020
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB                                       20
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB                                       31
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK                                      0xfff00000
+
+#define RX_MPDU_INFO_PEER_META_DATA_OFFSET                                          0x00000024
+#define RX_MPDU_INFO_PEER_META_DATA_LSB                                             0
+#define RX_MPDU_INFO_PEER_META_DATA_MSB                                             31
+#define RX_MPDU_INFO_PEER_META_DATA_MASK                                            0xffffffff
+
+#define RX_MPDU_INFO_AST_INDEX_OFFSET                                               0x00000028
+#define RX_MPDU_INFO_AST_INDEX_LSB                                                  0
+#define RX_MPDU_INFO_AST_INDEX_MSB                                                  15
+#define RX_MPDU_INFO_AST_INDEX_MASK                                                 0x0000ffff
+
+#define RX_MPDU_INFO_SW_PEER_ID_OFFSET                                              0x00000028
+#define RX_MPDU_INFO_SW_PEER_ID_LSB                                                 16
+#define RX_MPDU_INFO_SW_PEER_ID_MSB                                                 31
+#define RX_MPDU_INFO_SW_PEER_ID_MASK                                                0xffff0000
+
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                           0x0000002c
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                              0
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                              1
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                             0x00000003
+
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET                                       0x0000002c
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB                                          2
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB                                          8
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK                                         0x000001fc
+
+#define RX_MPDU_INFO_NDP_FRAME_OFFSET                                               0x0000002c
+#define RX_MPDU_INFO_NDP_FRAME_LSB                                                  9
+#define RX_MPDU_INFO_NDP_FRAME_MSB                                                  9
+#define RX_MPDU_INFO_NDP_FRAME_MASK                                                 0x00000200
+
+#define RX_MPDU_INFO_PHY_ERR_OFFSET                                                 0x0000002c
+#define RX_MPDU_INFO_PHY_ERR_LSB                                                    10
+#define RX_MPDU_INFO_PHY_ERR_MSB                                                    10
+#define RX_MPDU_INFO_PHY_ERR_MASK                                                   0x00000400
+
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET                              0x0000002c
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB                                 11
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB                                 11
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK                                0x00000800
+
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET                                    0x0000002c
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB                                       12
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB                                       12
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK                                      0x00001000
+
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET                                  0x0000002c
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB                                     13
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB                                     13
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK                                    0x00002000
+
+#define RX_MPDU_INFO_RESERVED_9A_OFFSET                                             0x0000002c
+#define RX_MPDU_INFO_RESERVED_9A_LSB                                                15
+#define RX_MPDU_INFO_RESERVED_9A_MSB                                                15
+#define RX_MPDU_INFO_RESERVED_9A_MASK                                               0x00008000
+
+#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET                                             0x0000002c
+#define RX_MPDU_INFO_PHY_PPDU_ID_LSB                                                16
+#define RX_MPDU_INFO_PHY_PPDU_ID_MSB                                                31
+#define RX_MPDU_INFO_PHY_PPDU_ID_MASK                                               0xffff0000
+
+#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET                                            0x00000030
+#define RX_MPDU_INFO_KEY_ID_OCTET_LSB                                               0
+#define RX_MPDU_INFO_KEY_ID_OCTET_MSB                                               7
+#define RX_MPDU_INFO_KEY_ID_OCTET_MASK                                              0x000000ff
+
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET                                          0x00000030
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB                                             8
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB                                             8
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK                                            0x00000100
+
+#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET                                          0x00000030
+#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB                                             9
+#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB                                             9
+#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK                                            0x00000200
+
+#define RX_MPDU_INFO_DECAP_TYPE_OFFSET                                              0x00000030
+#define RX_MPDU_INFO_DECAP_TYPE_LSB                                                 10
+#define RX_MPDU_INFO_DECAP_TYPE_MSB                                                 11
+#define RX_MPDU_INFO_DECAP_TYPE_MASK                                                0x00000c00
+
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET                            0x00000030
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB                               12
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB                               12
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK                              0x00001000
+
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET                            0x00000030
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB                               13
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB                               13
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK                              0x00002000
+
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET                                  0x00000030
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB                                     14
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB                                     14
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK                                    0x00004000
+
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET                                  0x00000030
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB                                     15
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB                                     15
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK                                    0x00008000
+
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET                                         0x00000030
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB                                            16
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB                                            27
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK                                           0x0fff0000
+
+#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET                                              0x00000030
+#define RX_MPDU_INFO_AMPDU_FLAG_LSB                                                 28
+#define RX_MPDU_INFO_AMPDU_FLAG_MSB                                                 28
+#define RX_MPDU_INFO_AMPDU_FLAG_MASK                                                0x10000000
+
+#define RX_MPDU_INFO_BAR_FRAME_OFFSET                                               0x00000030
+#define RX_MPDU_INFO_BAR_FRAME_LSB                                                  29
+#define RX_MPDU_INFO_BAR_FRAME_MSB                                                  29
+#define RX_MPDU_INFO_BAR_FRAME_MASK                                                 0x20000000
+
+#define RX_MPDU_INFO_RAW_MPDU_OFFSET                                                0x00000030
+#define RX_MPDU_INFO_RAW_MPDU_LSB                                                   30
+#define RX_MPDU_INFO_RAW_MPDU_MSB                                                   30
+#define RX_MPDU_INFO_RAW_MPDU_MASK                                                  0x40000000
+
+#define RX_MPDU_INFO_RESERVED_12_OFFSET                                             0x00000030
+#define RX_MPDU_INFO_RESERVED_12_LSB                                                31
+#define RX_MPDU_INFO_RESERVED_12_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_12_MASK                                               0x80000000
+
+#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET                                             0x00000034
+#define RX_MPDU_INFO_MPDU_LENGTH_LSB                                                0
+#define RX_MPDU_INFO_MPDU_LENGTH_MSB                                                13
+#define RX_MPDU_INFO_MPDU_LENGTH_MASK                                               0x00003fff
+
+#define RX_MPDU_INFO_FIRST_MPDU_OFFSET                                              0x00000034
+#define RX_MPDU_INFO_FIRST_MPDU_LSB                                                 14
+#define RX_MPDU_INFO_FIRST_MPDU_MSB                                                 14
+#define RX_MPDU_INFO_FIRST_MPDU_MASK                                                0x00004000
+
+#define RX_MPDU_INFO_MCAST_BCAST_OFFSET                                             0x00000034
+#define RX_MPDU_INFO_MCAST_BCAST_LSB                                                15
+#define RX_MPDU_INFO_MCAST_BCAST_MSB                                                15
+#define RX_MPDU_INFO_MCAST_BCAST_MASK                                               0x00008000
+
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET                                     0x00000034
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB                                        16
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB                                        16
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK                                       0x00010000
+
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET                                       0x00000034
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB                                          17
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB                                          17
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK                                         0x00020000
+
+#define RX_MPDU_INFO_POWER_MGMT_OFFSET                                              0x00000034
+#define RX_MPDU_INFO_POWER_MGMT_LSB                                                 18
+#define RX_MPDU_INFO_POWER_MGMT_MSB                                                 18
+#define RX_MPDU_INFO_POWER_MGMT_MASK                                                0x00040000
+
+#define RX_MPDU_INFO_NON_QOS_OFFSET                                                 0x00000034
+#define RX_MPDU_INFO_NON_QOS_LSB                                                    19
+#define RX_MPDU_INFO_NON_QOS_MSB                                                    19
+#define RX_MPDU_INFO_NON_QOS_MASK                                                   0x00080000
+
+#define RX_MPDU_INFO_NULL_DATA_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_NULL_DATA_LSB                                                  20
+#define RX_MPDU_INFO_NULL_DATA_MSB                                                  20
+#define RX_MPDU_INFO_NULL_DATA_MASK                                                 0x00100000
+
+#define RX_MPDU_INFO_MGMT_TYPE_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_MGMT_TYPE_LSB                                                  21
+#define RX_MPDU_INFO_MGMT_TYPE_MSB                                                  21
+#define RX_MPDU_INFO_MGMT_TYPE_MASK                                                 0x00200000
+
+#define RX_MPDU_INFO_CTRL_TYPE_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_CTRL_TYPE_LSB                                                  22
+#define RX_MPDU_INFO_CTRL_TYPE_MSB                                                  22
+#define RX_MPDU_INFO_CTRL_TYPE_MASK                                                 0x00400000
+
+#define RX_MPDU_INFO_MORE_DATA_OFFSET                                               0x00000034
+#define RX_MPDU_INFO_MORE_DATA_LSB                                                  23
+#define RX_MPDU_INFO_MORE_DATA_MSB                                                  23
+#define RX_MPDU_INFO_MORE_DATA_MASK                                                 0x00800000
+
+#define RX_MPDU_INFO_EOSP_OFFSET                                                    0x00000034
+#define RX_MPDU_INFO_EOSP_LSB                                                       24
+#define RX_MPDU_INFO_EOSP_MSB                                                       24
+#define RX_MPDU_INFO_EOSP_MASK                                                      0x01000000
+
+#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET                                           0x00000034
+#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB                                              25
+#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB                                              25
+#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK                                             0x02000000
+
+#define RX_MPDU_INFO_ORDER_OFFSET                                                   0x00000034
+#define RX_MPDU_INFO_ORDER_LSB                                                      26
+#define RX_MPDU_INFO_ORDER_MSB                                                      26
+#define RX_MPDU_INFO_ORDER_MASK                                                     0x04000000
+
+#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET                                          0x00000034
+#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB                                             27
+#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB                                             27
+#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK                                            0x08000000
+
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET                                        0x00000034
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB                                           28
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB                                           28
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK                                          0x10000000
+
+#define RX_MPDU_INFO_DIRECTED_OFFSET                                                0x00000034
+#define RX_MPDU_INFO_DIRECTED_LSB                                                   29
+#define RX_MPDU_INFO_DIRECTED_MSB                                                   29
+#define RX_MPDU_INFO_DIRECTED_MASK                                                  0x20000000
+
+#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET                                           0x00000034
+#define RX_MPDU_INFO_AMSDU_PRESENT_LSB                                              30
+#define RX_MPDU_INFO_AMSDU_PRESENT_MSB                                              30
+#define RX_MPDU_INFO_AMSDU_PRESENT_MASK                                             0x40000000
+
+#define RX_MPDU_INFO_RESERVED_13_OFFSET                                             0x00000034
+#define RX_MPDU_INFO_RESERVED_13_LSB                                                31
+#define RX_MPDU_INFO_RESERVED_13_MSB                                                31
+#define RX_MPDU_INFO_RESERVED_13_MASK                                               0x80000000
+
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET                                0x00000038
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB                                   0
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB                                   15
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK                                  0x0000ffff
+
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET                                     0x00000038
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB                                        16
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB                                        31
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK                                       0xffff0000
+
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET                                       0x0000003c
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB                                          0
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK                                         0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET                                      0x00000040
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB                                         15
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK                                        0x0000ffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET                                       0x00000040
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB                                          16
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK                                         0xffff0000
+
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET                                      0x00000044
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB                                         31
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK                                        0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET                                       0x00000048
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB                                          0
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK                                         0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET                                      0x0000004c
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB                                         15
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK                                        0x0000ffff
+
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET                             0x0000004c
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB                                16
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB                                31
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK                               0xffff0000
+
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET                                       0x00000050
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB                                          0
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB                                          31
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK                                         0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET                                      0x00000054
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB                                         0
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB                                         15
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK                                        0x0000ffff
+
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET                                  0x00000054
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB                                     16
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB                                     31
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK                                    0xffff0000
+
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET                                   0x00000058
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB                                      0
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB                                      31
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK                                     0xffffffff
+
+#define RX_MPDU_INFO_VDEV_ID_OFFSET                                                 0x0000005c
+#define RX_MPDU_INFO_VDEV_ID_LSB                                                    0
+#define RX_MPDU_INFO_VDEV_ID_MSB                                                    7
+#define RX_MPDU_INFO_VDEV_ID_MASK                                                   0x000000ff
+
+#define RX_MPDU_INFO_SERVICE_CODE_OFFSET                                            0x0000005c
+#define RX_MPDU_INFO_SERVICE_CODE_LSB                                               8
+#define RX_MPDU_INFO_SERVICE_CODE_MSB                                               16
+#define RX_MPDU_INFO_SERVICE_CODE_MASK                                              0x0001ff00
+
+#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET                                          0x0000005c
+#define RX_MPDU_INFO_PRIORITY_VALID_LSB                                             17
+#define RX_MPDU_INFO_PRIORITY_VALID_MSB                                             17
+#define RX_MPDU_INFO_PRIORITY_VALID_MASK                                            0x00020000
+
+#define RX_MPDU_INFO_SRC_INFO_OFFSET                                                0x0000005c
+#define RX_MPDU_INFO_SRC_INFO_LSB                                                   18
+#define RX_MPDU_INFO_SRC_INFO_MSB                                                   29
+#define RX_MPDU_INFO_SRC_INFO_MASK                                                  0x3ffc0000
+
+#define RX_MPDU_INFO_RESERVED_23A_OFFSET                                            0x0000005c
+#define RX_MPDU_INFO_RESERVED_23A_LSB                                               30
+#define RX_MPDU_INFO_RESERVED_23A_MSB                                               30
+#define RX_MPDU_INFO_RESERVED_23A_MASK                                              0x40000000
+
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET                                  0x0000006c
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB                                     0
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB                                     0
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK                                    0x00000001
+
+#define RX_MPDU_INFO_RESERVED_27A_OFFSET                                            0x0000006c
+#define RX_MPDU_INFO_RESERVED_27A_LSB                                               1
+#define RX_MPDU_INFO_RESERVED_27A_MSB                                               31
+#define RX_MPDU_INFO_RESERVED_27A_MASK                                              0xfffffffe
+
+#define RX_MPDU_INFO_RESERVED_28A_OFFSET                                            0x00000070
+#define RX_MPDU_INFO_RESERVED_28A_LSB                                               0
+#define RX_MPDU_INFO_RESERVED_28A_MSB                                               31
+#define RX_MPDU_INFO_RESERVED_28A_MASK                                              0xffffffff
+
+#define RX_MPDU_INFO_RESERVED_29A_OFFSET                                            0x00000074
+#define RX_MPDU_INFO_RESERVED_29A_LSB                                               0
+#define RX_MPDU_INFO_RESERVED_29A_MSB                                               31
+#define RX_MPDU_INFO_RESERVED_29A_MASK                                              0xffffffff
+
+#endif
diff --git a/hw/peach/v1/rx_mpdu_link_ptr.h b/hw/peach/v1/rx_mpdu_link_ptr.h
new file mode 100644
index 000000000000..d356550543f4
--- /dev/null
+++ b/hw/peach/v1/rx_mpdu_link_ptr.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MPDU_LINK_PTR_H_
+#define _RX_MPDU_LINK_PTR_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2
+
+struct rx_mpdu_link_ptr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          mpdu_link_desc_addr_info;
+#else
+             struct   buffer_addr_info                                          mpdu_link_desc_addr_info;
+#endif
+};
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET           0x00000000
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB              0
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB              31
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK             0xffffffff
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET          0x00000004
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB             0
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB             7
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK            0x000000ff
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET      0x00000004
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB         8
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB         11
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK        0x00000f00
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET           0x00000004
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB              12
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB              31
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK             0xfffff000
+
+#endif
diff --git a/hw/peach/v1/rx_mpdu_start.h b/hw/peach/v1/rx_mpdu_start.h
new file mode 100644
index 000000000000..18032824c2f0
--- /dev/null
+++ b/hw/peach/v1/rx_mpdu_start.h
@@ -0,0 +1,617 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MPDU_START_H_
+#define _RX_MPDU_START_H_
+
+#include "rx_mpdu_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_START 30
+
+struct rx_mpdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_mpdu_info                                              rx_mpdu_info_details;
+#else
+             struct   rx_mpdu_info                                              rx_mpdu_info_details;
+#endif
+};
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB   20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB   20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK  0x00100000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET                            0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB                               0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB                               0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK                              0x00000001
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET     0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB        1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB        1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK       0x00000002
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET                      0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB                         2
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB                         5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK                        0x0000003c
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET    0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB       6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB       7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK      0x000000c0
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET                         0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB                            10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB                            10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK                           0x00000400
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET                      0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB                         11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB                         14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK                        0x00007800
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET                               0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB                                  15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB                                  18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK                                 0x00078000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET                       0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB                          19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB                          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK                         0xfff80000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET       0x00000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB          0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK         0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET      0x0000000c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB         0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB         7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK        0x000000ff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET              0x0000000c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB                 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB                 23
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK                0x00ffff00
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET             0x0000000c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB                24
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB                24
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK               0x01000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET                   0x0000000c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB                      25
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB                      25
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK                     0x02000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET                       0x0000000c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB                          26
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB                          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK                         0xfc000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET                           0x00000010
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB                              0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB                              31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK                             0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET                          0x00000014
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB                             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB                             31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK                            0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET                          0x00000018
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB                             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB                             31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK                            0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET                         0x0000001c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB                            0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB                            31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK                           0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET          0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK            0x00000001
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET               0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB                  1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB                  1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK                 0x00000002
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET                0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB                   2
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB                   2
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK                  0x00000004
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET                0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB                   3
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB                   3
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK                  0x00000008
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET                0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB                   4
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB                   4
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK                  0x00000010
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET                0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB                   5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB                   5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK                  0x00000020
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET       0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB          6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB          6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK         0x00000040
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET            0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB               7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB               7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK              0x00000080
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET             0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB                8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB                8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK               0x00000100
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET       0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB          9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB          9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK         0x00000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET              0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB                 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB                 13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK                0x00003c00
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET                0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB                   14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB                   14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK                  0x00004000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET                      0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB                         15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MSB                         15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK                        0x00008000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET                             0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB                                16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB                                16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK                               0x00010000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET                             0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB                                17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB                                17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK                               0x00020000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET                         0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB                            18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB                            18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK                           0x00040000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET                        0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB                           19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB                           19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK                          0x00080000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET              0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB                 20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB                 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK                0xfff00000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET                    0x00000024
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB                       0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB                       31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK                      0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET                         0x00000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB                            0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB                            15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK                           0x0000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET                        0x00000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB                           16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB                           31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK                          0xffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET     0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB        0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB        1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK       0x00000003
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET                 0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB                    2
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB                    8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK                   0x000001fc
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET                         0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB                            9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB                            9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK                           0x00000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET                           0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB                              10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB                              10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK                             0x00000400
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET        0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB           11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB           11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK          0x00000800
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET              0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB                 12
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB                 12
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK                0x00001000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET            0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB               13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB               13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK              0x00002000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET                       0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB                          15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MSB                          15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK                         0x00008000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET                       0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB                          16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB                          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK                         0xffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET                      0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB                         0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB                         7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK                        0x000000ff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET                    0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB                       8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB                       8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK                      0x00000100
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET                    0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB                       9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB                       9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK                      0x00000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET                        0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB                           10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB                           11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK                          0x00000c00
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET      0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB         12
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB         12
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK        0x00001000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET      0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB         13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB         13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK        0x00002000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET            0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB               14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB               14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK              0x00004000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET            0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB               15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB               15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK              0x00008000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET                   0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB                      16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB                      27
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK                     0x0fff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET                        0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB                           28
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB                           28
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK                          0x10000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET                         0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB                            29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB                            29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK                           0x20000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET                          0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB                             30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB                             30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK                            0x40000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET                       0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB                          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB                          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK                         0x80000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET                       0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB                          0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB                          13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK                         0x00003fff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET                        0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB                           14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB                           14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK                          0x00004000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET                       0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB                          15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB                          15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK                         0x00008000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET               0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB                  16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB                  16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK                 0x00010000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET                 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB                    17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB                    17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK                   0x00020000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET                        0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB                           18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB                           18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK                          0x00040000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET                           0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB                              19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB                              19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK                             0x00080000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET                         0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB                            20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB                            20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK                           0x00100000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET                         0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB                            21
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB                            21
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK                           0x00200000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET                         0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB                            22
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB                            22
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK                           0x00400000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET                         0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB                            23
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB                            23
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK                           0x00800000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET                              0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB                                 24
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB                                 24
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK                                0x01000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET                     0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB                        25
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB                        25
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK                       0x02000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET                             0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB                                26
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB                                26
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK                               0x04000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET                    0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB                       27
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB                       27
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK                      0x08000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET                  0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB                     28
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB                     28
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK                    0x10000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET                          0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB                             29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB                             29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK                            0x20000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET                     0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB                        30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB                        30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK                       0x40000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET                       0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB                          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB                          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK                         0x80000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET          0x00000038
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB             0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB             15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK            0x0000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET               0x00000038
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB                  16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB                  31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK                 0xffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET                 0x0000003c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB                    0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB                    31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK                   0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET                0x00000040
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB                   0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB                   15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK                  0x0000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET                 0x00000040
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB                    16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB                    31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK                   0xffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET                0x00000044
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB                   0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB                   31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK                  0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET                 0x00000048
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB                    0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB                    31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK                   0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET                0x0000004c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB                   0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB                   15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK                  0x0000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET       0x0000004c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB          16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB          31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK         0xffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET                 0x00000050
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB                    0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB                    31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK                   0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET                0x00000054
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB                   0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB                   15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK                  0x0000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET            0x00000054
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB               16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB               31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK              0xffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET             0x00000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB                0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB                31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK               0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET                           0x0000005c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB                              0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB                              7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK                             0x000000ff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET                      0x0000005c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB                         8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB                         16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK                        0x0001ff00
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET                    0x0000005c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB                       17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB                       17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK                      0x00020000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET                          0x0000005c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB                             18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB                             29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK                            0x3ffc0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_OFFSET                      0x0000005c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_LSB                         30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MSB                         30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MASK                        0x40000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET            0x0000006c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB               0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB               0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK              0x00000001
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET                      0x0000006c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB                         1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB                         31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK                        0xfffffffe
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_OFFSET                      0x00000070
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_LSB                         0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MSB                         31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MASK                        0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET                      0x00000074
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB                         0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB                         31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK                        0xffffffff
+
+#endif
diff --git a/hw/peach/v1/rx_msdu_desc_info.h b/hw/peach/v1/rx_msdu_desc_info.h
new file mode 100644
index 000000000000..bca7ebfd9798
--- /dev/null
+++ b/hw/peach/v1/rx_msdu_desc_info.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MSDU_DESC_INFO_H_
+#define _RX_MSDU_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1
+
+struct rx_msdu_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t first_msdu_in_mpdu_flag                                 :  1,
+                      last_msdu_in_mpdu_flag                                  :  1,
+                      msdu_continuation                                       :  1,
+                      msdu_length                                             : 14,
+                      msdu_drop                                               :  1,
+                      sa_is_valid                                             :  1,
+                      da_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      l3_header_padding_msb                                   :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      ip_chksum_fail                                          :  1,
+                      fr_ds                                                   :  1,
+                      to_ds                                                   :  1,
+                      intra_bss                                               :  1,
+                      dest_chip_id                                            :  2,
+                      decap_format                                            :  2,
+                      __reserved_g_0015                                       :  1;
+#else
+             uint32_t __reserved_g_0015                                       :  1,
+                      decap_format                                            :  2,
+                      dest_chip_id                                            :  2,
+                      intra_bss                                               :  1,
+                      to_ds                                                   :  1,
+                      fr_ds                                                   :  1,
+                      ip_chksum_fail                                          :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      l3_header_padding_msb                                   :  1,
+                      da_is_mcbc                                              :  1,
+                      da_is_valid                                             :  1,
+                      sa_is_valid                                             :  1,
+                      msdu_drop                                               :  1,
+                      msdu_length                                             : 14,
+                      msdu_continuation                                       :  1,
+                      last_msdu_in_mpdu_flag                                  :  1,
+                      first_msdu_in_mpdu_flag                                 :  1;
+#endif
+};
+
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET                            0x00000000
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB                               0
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB                               0
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK                              0x00000001
+
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET                             0x00000000
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB                                1
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB                                1
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK                               0x00000002
+
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET                                  0x00000000
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB                                     2
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB                                     2
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK                                    0x00000004
+
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET                                        0x00000000
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB                                           3
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB                                           16
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK                                          0x0001fff8
+
+#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET                                          0x00000000
+#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB                                             17
+#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB                                             17
+#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK                                            0x00020000
+
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET                                        0x00000000
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB                                           18
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB                                           18
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK                                          0x00040000
+
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET                                        0x00000000
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB                                           19
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB                                           19
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK                                          0x00080000
+
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET                                         0x00000000
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB                                            20
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB                                            20
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK                                           0x00100000
+
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET                              0x00000000
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB                                 21
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB                                 21
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK                                0x00200000
+
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET                                0x00000000
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB                                   22
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB                                   22
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK                                  0x00400000
+
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET                                     0x00000000
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB                                        23
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB                                        23
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK                                       0x00800000
+
+#define RX_MSDU_DESC_INFO_FR_DS_OFFSET                                              0x00000000
+#define RX_MSDU_DESC_INFO_FR_DS_LSB                                                 24
+#define RX_MSDU_DESC_INFO_FR_DS_MSB                                                 24
+#define RX_MSDU_DESC_INFO_FR_DS_MASK                                                0x01000000
+
+#define RX_MSDU_DESC_INFO_TO_DS_OFFSET                                              0x00000000
+#define RX_MSDU_DESC_INFO_TO_DS_LSB                                                 25
+#define RX_MSDU_DESC_INFO_TO_DS_MSB                                                 25
+#define RX_MSDU_DESC_INFO_TO_DS_MASK                                                0x02000000
+
+#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET                                          0x00000000
+#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB                                             26
+#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB                                             26
+#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK                                            0x04000000
+
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET                                       0x00000000
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB                                          27
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB                                          28
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK                                         0x18000000
+
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET                                       0x00000000
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB                                          29
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB                                          30
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK                                         0x60000000
+
+#endif
diff --git a/hw/peach/v1/rx_msdu_details.h b/hw/peach/v1/rx_msdu_details.h
new file mode 100644
index 000000000000..4c284eb61837
--- /dev/null
+++ b/hw/peach/v1/rx_msdu_details.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MSDU_DETAILS_H_
+#define _RX_MSDU_DETAILS_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_msdu_ext_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4
+
+struct rx_msdu_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             struct   rx_msdu_ext_desc_info                                     rx_msdu_ext_desc_info_details;
+#else
+             struct   buffer_addr_info                                          buffer_addr_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             struct   rx_msdu_ext_desc_info                                     rx_msdu_ext_desc_info_details;
+#endif
+};
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET            0x00000000
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB               0
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB               31
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK              0xffffffff
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET           0x00000004
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB              0
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB              7
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK             0x000000ff
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET       0x00000004
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB          8
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB          11
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK         0x00000f00
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET            0x00000004
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB               12
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB               31
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK              0xfffff000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET    0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB       0
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB       0
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK      0x00000001
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET     0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB        1
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB        1
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK       0x00000002
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET          0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB             2
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB             2
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK            0x00000004
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET                0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB                   3
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB                   16
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK                  0x0001fff8
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET                  0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                     17
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                     17
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                    0x00020000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET                0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB                   18
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB                   18
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK                  0x00040000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET                0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB                   19
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB                   19
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK                  0x00080000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET                 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                    20
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                    20
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK                   0x00100000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET      0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB         21
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB         21
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK        0x00200000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET        0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB           22
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB           22
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK          0x00400000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET             0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB                23
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB                23
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK               0x00800000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                      0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                         24
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                         24
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                        0x01000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                      0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                         25
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                         25
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                        0x02000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET                  0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                     26
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                     26
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                    0x04000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET               0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB                  27
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB                  28
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK                 0x18000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET               0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB                  29
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB                  30
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK                 0x60000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET           0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB              5
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB              13
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK             0x00003fe0
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET         0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB            14
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB            14
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK           0x00004000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET            0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB               15
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB               26
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK              0x07ff8000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET            0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB               27
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB               29
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK              0x38000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET            0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB               30
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB               31
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK              0xc0000000
+
+#endif
diff --git a/hw/peach/v1/rx_msdu_end.h b/hw/peach/v1/rx_msdu_end.h
new file mode 100644
index 000000000000..15b0aa3f017b
--- /dev/null
+++ b/hw/peach/v1/rx_msdu_end.h
@@ -0,0 +1,1097 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MSDU_END_H_
+#define _RX_MSDU_END_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_END 32
+
+struct rx_msdu_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+             uint32_t ip_hdr_chksum                                           : 16,
+                      reported_mpdu_length                                    : 14,
+                      reserved_1a                                             :  2;
+             uint32_t reserved_2a                                             :  8,
+                      cce_super_rule                                          :  6,
+                      cce_classify_not_done_truncate                          :  1,
+                      cce_classify_not_done_cce_dis                           :  1,
+                      cumulative_l3_checksum                                  : 16;
+             uint32_t rule_indication_31_0                                    : 32;
+             uint32_t ipv6_options_crc                                        : 32;
+             uint32_t da_offset                                               :  6,
+                      sa_offset                                               :  6,
+                      da_offset_valid                                         :  1,
+                      sa_offset_valid                                         :  1,
+                      reserved_5a                                             :  2,
+                      l3_type                                                 : 16;
+             uint32_t rule_indication_63_32                                   : 32;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t tcp_ack_number                                          : 32;
+             uint32_t tcp_flag                                                :  9,
+                      lro_eligible                                            :  1,
+                      reserved_9a                                             :  6,
+                      window_size                                             : 16;
+             uint32_t sa_sw_peer_id                                           : 16,
+                      sa_idx_timeout                                          :  1,
+                      da_idx_timeout                                          :  1,
+                      to_ds                                                   :  1,
+                      tid                                                     :  4,
+                      sa_is_valid                                             :  1,
+                      da_is_valid                                             :  1,
+                      da_is_mcbc                                              :  1,
+                      l3_header_padding                                       :  2,
+                      first_msdu                                              :  1,
+                      last_msdu                                               :  1,
+                      fr_ds                                                   :  1,
+                      ip_chksum_fail_copy                                     :  1;
+             uint32_t sa_idx                                                  : 16,
+                      da_idx_or_sw_peer_id                                    : 16;
+             uint32_t msdu_drop                                               :  1,
+                      reo_destination_indication                              :  5,
+                      flow_idx                                                : 20,
+                      use_ppe                                                 :  1,
+                      __reserved_g_0003                                                :  2,
+                      vlan_ctag_stripped                                      :  1,
+                      vlan_stag_stripped                                      :  1,
+                      fragment_flag                                           :  1;
+             uint32_t fse_metadata                                            : 32;
+             uint32_t cce_metadata                                            : 16,
+                      tcp_udp_chksum                                          : 16;
+             uint32_t aggregation_count                                       :  8,
+                      flow_aggregation_continuation                           :  1,
+                      fisa_timeout                                            :  1,
+                      tcp_udp_chksum_fail_copy                                :  1,
+                      msdu_limit_error                                        :  1,
+                      flow_idx_timeout                                        :  1,
+                      flow_idx_invalid                                        :  1,
+                      cce_match                                               :  1,
+                      amsdu_parser_error                                      :  1,
+                      cumulative_ip_length                                    : 16;
+             uint32_t key_id_octet                                            :  8,
+                      reserved_16a                                            : 24;
+             uint32_t reserved_17a                                            :  6,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      intra_bss                                               :  1,
+                      dest_chip_id                                            :  2,
+                      multicast_echo                                          :  1,
+                      wds_learning_event                                      :  1,
+                      wds_roaming_event                                       :  1,
+                      wds_keep_alive_event                                    :  1,
+                      __reserved_g_0015                                       :  1,
+                      reserved_17b                                            :  8;
+             uint32_t msdu_length                                             : 14,
+                      stbc                                                    :  1,
+                      ipsec_esp                                               :  1,
+                      l3_offset                                               :  7,
+                      ipsec_ah                                                :  1,
+                      l4_offset                                               :  8;
+             uint32_t msdu_number                                             :  8,
+                      decap_format                                            :  2,
+                      ipv4_proto                                              :  1,
+                      ipv6_proto                                              :  1,
+                      tcp_proto                                               :  1,
+                      udp_proto                                               :  1,
+                      ip_frag                                                 :  1,
+                      tcp_only_ack                                            :  1,
+                      da_is_bcast_mcast                                       :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      ip_fixed_header_valid                                   :  1,
+                      ip_extn_header_valid                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      mesh_control_present                                    :  1,
+                      ldpc                                                    :  1,
+                      ip4_protocol_ip6_next_header                            :  8;
+             uint32_t vlan_ctag_ci                                            : 16,
+                      vlan_stag_ci                                            : 16;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t user_rssi                                               :  8,
+                      pkt_type                                                :  4,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  4,
+                      receive_bandwidth                                       :  3,
+                      reception_type                                          :  3,
+                      mimo_ss_bitmap                                          :  7,
+                      msdu_done_copy                                          :  1;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t reserved_28a                                            : 16,
+                      sa_15_0                                                 : 16;
+             uint32_t sa_47_16                                                : 32;
+             uint32_t first_mpdu                                              :  1,
+                      reserved_30a                                            :  1,
+                      mcast_bcast                                             :  1,
+                      ast_index_not_found                                     :  1,
+                      ast_index_timeout                                       :  1,
+                      power_mgmt                                              :  1,
+                      non_qos                                                 :  1,
+                      null_data                                               :  1,
+                      mgmt_type                                               :  1,
+                      ctrl_type                                               :  1,
+                      more_data                                               :  1,
+                      eosp                                                    :  1,
+                      a_msdu_error                                            :  1,
+                      reserved_30b                                            :  1,
+                      order                                                   :  1,
+                      wifi_parser_error                                       :  1,
+                      overflow_err                                            :  1,
+                      msdu_length_err                                         :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      ip_chksum_fail                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      da_idx_invalid                                          :  1,
+                      amsdu_addr_mismatch                                     :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      encrypt_required                                        :  1,
+                      directed                                                :  1,
+                      buffer_fragment                                         :  1,
+                      mpdu_length_err                                         :  1,
+                      tkip_mic_err                                            :  1,
+                      decrypt_err                                             :  1,
+                      unencrypted_frame_err                                   :  1,
+                      fcs_err                                                 :  1;
+             uint32_t reserved_31a                                            : 10,
+                      decrypt_status_code                                     :  3,
+                      rx_bitmap_not_updated                                   :  1,
+                      reserved_31b                                            : 17,
+                      msdu_done                                               :  1;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t reserved_1a                                             :  2,
+                      reported_mpdu_length                                    : 14,
+                      ip_hdr_chksum                                           : 16;
+             uint32_t cumulative_l3_checksum                                  : 16,
+                      cce_classify_not_done_cce_dis                           :  1,
+                      cce_classify_not_done_truncate                          :  1,
+                      cce_super_rule                                          :  6,
+                      reserved_2a                                             :  8;
+             uint32_t rule_indication_31_0                                    : 32;
+             uint32_t ipv6_options_crc                                        : 32;
+             uint32_t l3_type                                                 : 16,
+                      reserved_5a                                             :  2,
+                      sa_offset_valid                                         :  1,
+                      da_offset_valid                                         :  1,
+                      sa_offset                                               :  6,
+                      da_offset                                               :  6;
+             uint32_t rule_indication_63_32                                   : 32;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t tcp_ack_number                                          : 32;
+             uint32_t window_size                                             : 16,
+                      reserved_9a                                             :  6,
+                      lro_eligible                                            :  1,
+                      tcp_flag                                                :  9;
+             uint32_t ip_chksum_fail_copy                                     :  1,
+                      fr_ds                                                   :  1,
+                      last_msdu                                               :  1,
+                      first_msdu                                              :  1,
+                      l3_header_padding                                       :  2,
+                      da_is_mcbc                                              :  1,
+                      da_is_valid                                             :  1,
+                      sa_is_valid                                             :  1,
+                      tid                                                     :  4,
+                      to_ds                                                   :  1,
+                      da_idx_timeout                                          :  1,
+                      sa_idx_timeout                                          :  1,
+                      sa_sw_peer_id                                           : 16;
+             uint32_t da_idx_or_sw_peer_id                                    : 16,
+                      sa_idx                                                  : 16;
+             uint32_t fragment_flag                                           :  1,
+                      vlan_stag_stripped                                      :  1,
+                      vlan_ctag_stripped                                      :  1,
+                      __reserved_g_0003                                                :  2,
+                      use_ppe                                                 :  1,
+                      flow_idx                                                : 20,
+                      reo_destination_indication                              :  5,
+                      msdu_drop                                               :  1;
+             uint32_t fse_metadata                                            : 32;
+             uint32_t tcp_udp_chksum                                          : 16,
+                      cce_metadata                                            : 16;
+             uint32_t cumulative_ip_length                                    : 16,
+                      amsdu_parser_error                                      :  1,
+                      cce_match                                               :  1,
+                      flow_idx_invalid                                        :  1,
+                      flow_idx_timeout                                        :  1,
+                      msdu_limit_error                                        :  1,
+                      tcp_udp_chksum_fail_copy                                :  1,
+                      fisa_timeout                                            :  1,
+                      flow_aggregation_continuation                           :  1,
+                      aggregation_count                                       :  8;
+             uint32_t reserved_16a                                            : 24,
+                      key_id_octet                                            :  8;
+             uint32_t reserved_17b                                            :  8,
+                      __reserved_g_0015                                       :  1,
+                      wds_keep_alive_event                                    :  1,
+                      wds_roaming_event                                       :  1,
+                      wds_learning_event                                      :  1,
+                      multicast_echo                                          :  1,
+                      dest_chip_id                                            :  2,
+                      intra_bss                                               :  1,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      reserved_17a                                            :  6;
+             uint32_t l4_offset                                               :  8,
+                      ipsec_ah                                                :  1,
+                      l3_offset                                               :  7,
+                      ipsec_esp                                               :  1,
+                      stbc                                                    :  1,
+                      msdu_length                                             : 14;
+             uint32_t ip4_protocol_ip6_next_header                            :  8,
+                      ldpc                                                    :  1,
+                      mesh_control_present                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      ip_extn_header_valid                                    :  1,
+                      ip_fixed_header_valid                                   :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      da_is_bcast_mcast                                       :  1,
+                      tcp_only_ack                                            :  1,
+                      ip_frag                                                 :  1,
+                      udp_proto                                               :  1,
+                      tcp_proto                                               :  1,
+                      ipv6_proto                                              :  1,
+                      ipv4_proto                                              :  1,
+                      decap_format                                            :  2,
+                      msdu_number                                             :  8;
+             uint32_t vlan_stag_ci                                            : 16,
+                      vlan_ctag_ci                                            : 16;
+             uint32_t peer_meta_data                                          : 32;
+             uint32_t msdu_done_copy                                          :  1,
+                      mimo_ss_bitmap                                          :  7,
+                      reception_type                                          :  3,
+                      receive_bandwidth                                       :  3,
+                      rate_mcs                                                :  4,
+                      sgi                                                     :  2,
+                      pkt_type                                                :  4,
+                      user_rssi                                               :  8;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t sa_15_0                                                 : 16,
+                      reserved_28a                                            : 16;
+             uint32_t sa_47_16                                                : 32;
+             uint32_t fcs_err                                                 :  1,
+                      unencrypted_frame_err                                   :  1,
+                      decrypt_err                                             :  1,
+                      tkip_mic_err                                            :  1,
+                      mpdu_length_err                                         :  1,
+                      buffer_fragment                                         :  1,
+                      directed                                                :  1,
+                      encrypt_required                                        :  1,
+                      rx_in_tx_decrypt_byp                                    :  1,
+                      amsdu_addr_mismatch                                     :  1,
+                      da_idx_invalid                                          :  1,
+                      sa_idx_invalid                                          :  1,
+                      ip_chksum_fail                                          :  1,
+                      tcp_udp_chksum_fail                                     :  1,
+                      msdu_length_err                                         :  1,
+                      overflow_err                                            :  1,
+                      wifi_parser_error                                       :  1,
+                      order                                                   :  1,
+                      reserved_30b                                            :  1,
+                      a_msdu_error                                            :  1,
+                      eosp                                                    :  1,
+                      more_data                                               :  1,
+                      ctrl_type                                               :  1,
+                      mgmt_type                                               :  1,
+                      null_data                                               :  1,
+                      non_qos                                                 :  1,
+                      power_mgmt                                              :  1,
+                      ast_index_timeout                                       :  1,
+                      ast_index_not_found                                     :  1,
+                      mcast_bcast                                             :  1,
+                      reserved_30a                                            :  1,
+                      first_mpdu                                              :  1;
+             uint32_t msdu_done                                               :  1,
+                      reserved_31b                                            : 17,
+                      rx_bitmap_not_updated                                   :  1,
+                      decrypt_status_code                                     :  3,
+                      reserved_31a                                            : 10;
+#endif
+};
+
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                            0x00000000
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                               0
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                               1
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                              0x00000003
+
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET                                        0x00000000
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB                                           2
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB                                           8
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK                                          0x000001fc
+
+#define RX_MSDU_END_RESERVED_0_OFFSET                                               0x00000000
+#define RX_MSDU_END_RESERVED_0_LSB                                                  9
+#define RX_MSDU_END_RESERVED_0_MSB                                                  15
+#define RX_MSDU_END_RESERVED_0_MASK                                                 0x0000fe00
+
+#define RX_MSDU_END_PHY_PPDU_ID_OFFSET                                              0x00000000
+#define RX_MSDU_END_PHY_PPDU_ID_LSB                                                 16
+#define RX_MSDU_END_PHY_PPDU_ID_MSB                                                 31
+#define RX_MSDU_END_PHY_PPDU_ID_MASK                                                0xffff0000
+
+#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET                                            0x00000004
+#define RX_MSDU_END_IP_HDR_CHKSUM_LSB                                               0
+#define RX_MSDU_END_IP_HDR_CHKSUM_MSB                                               15
+#define RX_MSDU_END_IP_HDR_CHKSUM_MASK                                              0x0000ffff
+
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET                                     0x00000004
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB                                        16
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB                                        29
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK                                       0x3fff0000
+
+#define RX_MSDU_END_RESERVED_1A_OFFSET                                              0x00000004
+#define RX_MSDU_END_RESERVED_1A_LSB                                                 30
+#define RX_MSDU_END_RESERVED_1A_MSB                                                 31
+#define RX_MSDU_END_RESERVED_1A_MASK                                                0xc0000000
+
+#define RX_MSDU_END_RESERVED_2A_OFFSET                                              0x00000008
+#define RX_MSDU_END_RESERVED_2A_LSB                                                 0
+#define RX_MSDU_END_RESERVED_2A_MSB                                                 7
+#define RX_MSDU_END_RESERVED_2A_MASK                                                0x000000ff
+
+#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET                                           0x00000008
+#define RX_MSDU_END_CCE_SUPER_RULE_LSB                                              8
+#define RX_MSDU_END_CCE_SUPER_RULE_MSB                                              13
+#define RX_MSDU_END_CCE_SUPER_RULE_MASK                                             0x00003f00
+
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET                           0x00000008
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB                              14
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB                              14
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK                             0x00004000
+
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET                            0x00000008
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB                               15
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB                               15
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK                              0x00008000
+
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET                                   0x00000008
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB                                      16
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB                                      31
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK                                     0xffff0000
+
+#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET                                     0x0000000c
+#define RX_MSDU_END_RULE_INDICATION_31_0_LSB                                        0
+#define RX_MSDU_END_RULE_INDICATION_31_0_MSB                                        31
+#define RX_MSDU_END_RULE_INDICATION_31_0_MASK                                       0xffffffff
+
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET                                         0x00000010
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB                                            0
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB                                            31
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK                                           0xffffffff
+
+#define RX_MSDU_END_DA_OFFSET_OFFSET                                                0x00000014
+#define RX_MSDU_END_DA_OFFSET_LSB                                                   0
+#define RX_MSDU_END_DA_OFFSET_MSB                                                   5
+#define RX_MSDU_END_DA_OFFSET_MASK                                                  0x0000003f
+
+#define RX_MSDU_END_SA_OFFSET_OFFSET                                                0x00000014
+#define RX_MSDU_END_SA_OFFSET_LSB                                                   6
+#define RX_MSDU_END_SA_OFFSET_MSB                                                   11
+#define RX_MSDU_END_SA_OFFSET_MASK                                                  0x00000fc0
+
+#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET                                          0x00000014
+#define RX_MSDU_END_DA_OFFSET_VALID_LSB                                             12
+#define RX_MSDU_END_DA_OFFSET_VALID_MSB                                             12
+#define RX_MSDU_END_DA_OFFSET_VALID_MASK                                            0x00001000
+
+#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET                                          0x00000014
+#define RX_MSDU_END_SA_OFFSET_VALID_LSB                                             13
+#define RX_MSDU_END_SA_OFFSET_VALID_MSB                                             13
+#define RX_MSDU_END_SA_OFFSET_VALID_MASK                                            0x00002000
+
+#define RX_MSDU_END_RESERVED_5A_OFFSET                                              0x00000014
+#define RX_MSDU_END_RESERVED_5A_LSB                                                 14
+#define RX_MSDU_END_RESERVED_5A_MSB                                                 15
+#define RX_MSDU_END_RESERVED_5A_MASK                                                0x0000c000
+
+#define RX_MSDU_END_L3_TYPE_OFFSET                                                  0x00000014
+#define RX_MSDU_END_L3_TYPE_LSB                                                     16
+#define RX_MSDU_END_L3_TYPE_MSB                                                     31
+#define RX_MSDU_END_L3_TYPE_MASK                                                    0xffff0000
+
+#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET                                    0x00000018
+#define RX_MSDU_END_RULE_INDICATION_63_32_LSB                                       0
+#define RX_MSDU_END_RULE_INDICATION_63_32_MSB                                       31
+#define RX_MSDU_END_RULE_INDICATION_63_32_MASK                                      0xffffffff
+
+#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET                                           0x0000001c
+#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB                                              0
+#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB                                              31
+#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK                                             0xffffffff
+
+#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET                                           0x00000020
+#define RX_MSDU_END_TCP_ACK_NUMBER_LSB                                              0
+#define RX_MSDU_END_TCP_ACK_NUMBER_MSB                                              31
+#define RX_MSDU_END_TCP_ACK_NUMBER_MASK                                             0xffffffff
+
+#define RX_MSDU_END_TCP_FLAG_OFFSET                                                 0x00000024
+#define RX_MSDU_END_TCP_FLAG_LSB                                                    0
+#define RX_MSDU_END_TCP_FLAG_MSB                                                    8
+#define RX_MSDU_END_TCP_FLAG_MASK                                                   0x000001ff
+
+#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET                                             0x00000024
+#define RX_MSDU_END_LRO_ELIGIBLE_LSB                                                9
+#define RX_MSDU_END_LRO_ELIGIBLE_MSB                                                9
+#define RX_MSDU_END_LRO_ELIGIBLE_MASK                                               0x00000200
+
+#define RX_MSDU_END_RESERVED_9A_OFFSET                                              0x00000024
+#define RX_MSDU_END_RESERVED_9A_LSB                                                 10
+#define RX_MSDU_END_RESERVED_9A_MSB                                                 15
+#define RX_MSDU_END_RESERVED_9A_MASK                                                0x0000fc00
+
+#define RX_MSDU_END_WINDOW_SIZE_OFFSET                                              0x00000024
+#define RX_MSDU_END_WINDOW_SIZE_LSB                                                 16
+#define RX_MSDU_END_WINDOW_SIZE_MSB                                                 31
+#define RX_MSDU_END_WINDOW_SIZE_MASK                                                0xffff0000
+
+#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET                                            0x00000028
+#define RX_MSDU_END_SA_SW_PEER_ID_LSB                                               0
+#define RX_MSDU_END_SA_SW_PEER_ID_MSB                                               15
+#define RX_MSDU_END_SA_SW_PEER_ID_MASK                                              0x0000ffff
+
+#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET                                           0x00000028
+#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB                                              16
+#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB                                              16
+#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK                                             0x00010000
+
+#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET                                           0x00000028
+#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB                                              17
+#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB                                              17
+#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK                                             0x00020000
+
+#define RX_MSDU_END_TO_DS_OFFSET                                                    0x00000028
+#define RX_MSDU_END_TO_DS_LSB                                                       18
+#define RX_MSDU_END_TO_DS_MSB                                                       18
+#define RX_MSDU_END_TO_DS_MASK                                                      0x00040000
+
+#define RX_MSDU_END_TID_OFFSET                                                      0x00000028
+#define RX_MSDU_END_TID_LSB                                                         19
+#define RX_MSDU_END_TID_MSB                                                         22
+#define RX_MSDU_END_TID_MASK                                                        0x00780000
+
+#define RX_MSDU_END_SA_IS_VALID_OFFSET                                              0x00000028
+#define RX_MSDU_END_SA_IS_VALID_LSB                                                 23
+#define RX_MSDU_END_SA_IS_VALID_MSB                                                 23
+#define RX_MSDU_END_SA_IS_VALID_MASK                                                0x00800000
+
+#define RX_MSDU_END_DA_IS_VALID_OFFSET                                              0x00000028
+#define RX_MSDU_END_DA_IS_VALID_LSB                                                 24
+#define RX_MSDU_END_DA_IS_VALID_MSB                                                 24
+#define RX_MSDU_END_DA_IS_VALID_MASK                                                0x01000000
+
+#define RX_MSDU_END_DA_IS_MCBC_OFFSET                                               0x00000028
+#define RX_MSDU_END_DA_IS_MCBC_LSB                                                  25
+#define RX_MSDU_END_DA_IS_MCBC_MSB                                                  25
+#define RX_MSDU_END_DA_IS_MCBC_MASK                                                 0x02000000
+
+#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET                                        0x00000028
+#define RX_MSDU_END_L3_HEADER_PADDING_LSB                                           26
+#define RX_MSDU_END_L3_HEADER_PADDING_MSB                                           27
+#define RX_MSDU_END_L3_HEADER_PADDING_MASK                                          0x0c000000
+
+#define RX_MSDU_END_FIRST_MSDU_OFFSET                                               0x00000028
+#define RX_MSDU_END_FIRST_MSDU_LSB                                                  28
+#define RX_MSDU_END_FIRST_MSDU_MSB                                                  28
+#define RX_MSDU_END_FIRST_MSDU_MASK                                                 0x10000000
+
+#define RX_MSDU_END_LAST_MSDU_OFFSET                                                0x00000028
+#define RX_MSDU_END_LAST_MSDU_LSB                                                   29
+#define RX_MSDU_END_LAST_MSDU_MSB                                                   29
+#define RX_MSDU_END_LAST_MSDU_MASK                                                  0x20000000
+
+#define RX_MSDU_END_FR_DS_OFFSET                                                    0x00000028
+#define RX_MSDU_END_FR_DS_LSB                                                       30
+#define RX_MSDU_END_FR_DS_MSB                                                       30
+#define RX_MSDU_END_FR_DS_MASK                                                      0x40000000
+
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET                                      0x00000028
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB                                         31
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB                                         31
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK                                        0x80000000
+
+#define RX_MSDU_END_SA_IDX_OFFSET                                                   0x0000002c
+#define RX_MSDU_END_SA_IDX_LSB                                                      0
+#define RX_MSDU_END_SA_IDX_MSB                                                      15
+#define RX_MSDU_END_SA_IDX_MASK                                                     0x0000ffff
+
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET                                     0x0000002c
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB                                        16
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB                                        31
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK                                       0xffff0000
+
+#define RX_MSDU_END_MSDU_DROP_OFFSET                                                0x00000030
+#define RX_MSDU_END_MSDU_DROP_LSB                                                   0
+#define RX_MSDU_END_MSDU_DROP_MSB                                                   0
+#define RX_MSDU_END_MSDU_DROP_MASK                                                  0x00000001
+
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET                               0x00000030
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB                                  1
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB                                  5
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK                                 0x0000003e
+
+#define RX_MSDU_END_FLOW_IDX_OFFSET                                                 0x00000030
+#define RX_MSDU_END_FLOW_IDX_LSB                                                    6
+#define RX_MSDU_END_FLOW_IDX_MSB                                                    25
+#define RX_MSDU_END_FLOW_IDX_MASK                                                   0x03ffffc0
+
+#define RX_MSDU_END_USE_PPE_OFFSET                                                  0x00000030
+#define RX_MSDU_END_USE_PPE_LSB                                                     26
+#define RX_MSDU_END_USE_PPE_MSB                                                     26
+#define RX_MSDU_END_USE_PPE_MASK                                                    0x04000000
+
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET                                       0x00000030
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB                                          29
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB                                          29
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK                                         0x20000000
+
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET                                       0x00000030
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB                                          30
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB                                          30
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK                                         0x40000000
+
+#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET                                            0x00000030
+#define RX_MSDU_END_FRAGMENT_FLAG_LSB                                               31
+#define RX_MSDU_END_FRAGMENT_FLAG_MSB                                               31
+#define RX_MSDU_END_FRAGMENT_FLAG_MASK                                              0x80000000
+
+#define RX_MSDU_END_FSE_METADATA_OFFSET                                             0x00000034
+#define RX_MSDU_END_FSE_METADATA_LSB                                                0
+#define RX_MSDU_END_FSE_METADATA_MSB                                                31
+#define RX_MSDU_END_FSE_METADATA_MASK                                               0xffffffff
+
+#define RX_MSDU_END_CCE_METADATA_OFFSET                                             0x00000038
+#define RX_MSDU_END_CCE_METADATA_LSB                                                0
+#define RX_MSDU_END_CCE_METADATA_MSB                                                15
+#define RX_MSDU_END_CCE_METADATA_MASK                                               0x0000ffff
+
+#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET                                           0x00000038
+#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB                                              16
+#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB                                              31
+#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK                                             0xffff0000
+
+#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET                                        0x0000003c
+#define RX_MSDU_END_AGGREGATION_COUNT_LSB                                           0
+#define RX_MSDU_END_AGGREGATION_COUNT_MSB                                           7
+#define RX_MSDU_END_AGGREGATION_COUNT_MASK                                          0x000000ff
+
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET                            0x0000003c
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB                               8
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB                               8
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK                              0x00000100
+
+#define RX_MSDU_END_FISA_TIMEOUT_OFFSET                                             0x0000003c
+#define RX_MSDU_END_FISA_TIMEOUT_LSB                                                9
+#define RX_MSDU_END_FISA_TIMEOUT_MSB                                                9
+#define RX_MSDU_END_FISA_TIMEOUT_MASK                                               0x00000200
+
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET                                 0x0000003c
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB                                    10
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB                                    10
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK                                   0x00000400
+
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET                                         0x0000003c
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB                                            11
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB                                            11
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK                                           0x00000800
+
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET                                         0x0000003c
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB                                            12
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB                                            12
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK                                           0x00001000
+
+#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET                                         0x0000003c
+#define RX_MSDU_END_FLOW_IDX_INVALID_LSB                                            13
+#define RX_MSDU_END_FLOW_IDX_INVALID_MSB                                            13
+#define RX_MSDU_END_FLOW_IDX_INVALID_MASK                                           0x00002000
+
+#define RX_MSDU_END_CCE_MATCH_OFFSET                                                0x0000003c
+#define RX_MSDU_END_CCE_MATCH_LSB                                                   14
+#define RX_MSDU_END_CCE_MATCH_MSB                                                   14
+#define RX_MSDU_END_CCE_MATCH_MASK                                                  0x00004000
+
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET                                       0x0000003c
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB                                          15
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB                                          15
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK                                         0x00008000
+
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET                                     0x0000003c
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB                                        16
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB                                        31
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK                                       0xffff0000
+
+#define RX_MSDU_END_KEY_ID_OCTET_OFFSET                                             0x00000040
+#define RX_MSDU_END_KEY_ID_OCTET_LSB                                                0
+#define RX_MSDU_END_KEY_ID_OCTET_MSB                                                7
+#define RX_MSDU_END_KEY_ID_OCTET_MASK                                               0x000000ff
+
+#define RX_MSDU_END_RESERVED_16A_OFFSET                                             0x00000040
+#define RX_MSDU_END_RESERVED_16A_LSB                                                8
+#define RX_MSDU_END_RESERVED_16A_MSB                                                31
+#define RX_MSDU_END_RESERVED_16A_MASK                                               0xffffff00
+
+#define RX_MSDU_END_RESERVED_17A_OFFSET                                             0x00000044
+#define RX_MSDU_END_RESERVED_17A_LSB                                                0
+#define RX_MSDU_END_RESERVED_17A_MSB                                                5
+#define RX_MSDU_END_RESERVED_17A_MASK                                               0x0000003f
+
+#define RX_MSDU_END_SERVICE_CODE_OFFSET                                             0x00000044
+#define RX_MSDU_END_SERVICE_CODE_LSB                                                6
+#define RX_MSDU_END_SERVICE_CODE_MSB                                                14
+#define RX_MSDU_END_SERVICE_CODE_MASK                                               0x00007fc0
+
+#define RX_MSDU_END_PRIORITY_VALID_OFFSET                                           0x00000044
+#define RX_MSDU_END_PRIORITY_VALID_LSB                                              15
+#define RX_MSDU_END_PRIORITY_VALID_MSB                                              15
+#define RX_MSDU_END_PRIORITY_VALID_MASK                                             0x00008000
+
+#define RX_MSDU_END_INTRA_BSS_OFFSET                                                0x00000044
+#define RX_MSDU_END_INTRA_BSS_LSB                                                   16
+#define RX_MSDU_END_INTRA_BSS_MSB                                                   16
+#define RX_MSDU_END_INTRA_BSS_MASK                                                  0x00010000
+
+#define RX_MSDU_END_DEST_CHIP_ID_OFFSET                                             0x00000044
+#define RX_MSDU_END_DEST_CHIP_ID_LSB                                                17
+#define RX_MSDU_END_DEST_CHIP_ID_MSB                                                18
+#define RX_MSDU_END_DEST_CHIP_ID_MASK                                               0x00060000
+
+#define RX_MSDU_END_MULTICAST_ECHO_OFFSET                                           0x00000044
+#define RX_MSDU_END_MULTICAST_ECHO_LSB                                              19
+#define RX_MSDU_END_MULTICAST_ECHO_MSB                                              19
+#define RX_MSDU_END_MULTICAST_ECHO_MASK                                             0x00080000
+
+#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET                                       0x00000044
+#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB                                          20
+#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB                                          20
+#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK                                         0x00100000
+
+#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET                                        0x00000044
+#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB                                           21
+#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB                                           21
+#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK                                          0x00200000
+
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET                                     0x00000044
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB                                        22
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB                                        22
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK                                       0x00400000
+
+#define RX_MSDU_END_RESERVED_17B_OFFSET                                             0x00000044
+#define RX_MSDU_END_RESERVED_17B_LSB                                                24
+#define RX_MSDU_END_RESERVED_17B_MSB                                                31
+#define RX_MSDU_END_RESERVED_17B_MASK                                               0xff000000
+
+#define RX_MSDU_END_MSDU_LENGTH_OFFSET                                              0x00000048
+#define RX_MSDU_END_MSDU_LENGTH_LSB                                                 0
+#define RX_MSDU_END_MSDU_LENGTH_MSB                                                 13
+#define RX_MSDU_END_MSDU_LENGTH_MASK                                                0x00003fff
+
+#define RX_MSDU_END_STBC_OFFSET                                                     0x00000048
+#define RX_MSDU_END_STBC_LSB                                                        14
+#define RX_MSDU_END_STBC_MSB                                                        14
+#define RX_MSDU_END_STBC_MASK                                                       0x00004000
+
+#define RX_MSDU_END_IPSEC_ESP_OFFSET                                                0x00000048
+#define RX_MSDU_END_IPSEC_ESP_LSB                                                   15
+#define RX_MSDU_END_IPSEC_ESP_MSB                                                   15
+#define RX_MSDU_END_IPSEC_ESP_MASK                                                  0x00008000
+
+#define RX_MSDU_END_L3_OFFSET_OFFSET                                                0x00000048
+#define RX_MSDU_END_L3_OFFSET_LSB                                                   16
+#define RX_MSDU_END_L3_OFFSET_MSB                                                   22
+#define RX_MSDU_END_L3_OFFSET_MASK                                                  0x007f0000
+
+#define RX_MSDU_END_IPSEC_AH_OFFSET                                                 0x00000048
+#define RX_MSDU_END_IPSEC_AH_LSB                                                    23
+#define RX_MSDU_END_IPSEC_AH_MSB                                                    23
+#define RX_MSDU_END_IPSEC_AH_MASK                                                   0x00800000
+
+#define RX_MSDU_END_L4_OFFSET_OFFSET                                                0x00000048
+#define RX_MSDU_END_L4_OFFSET_LSB                                                   24
+#define RX_MSDU_END_L4_OFFSET_MSB                                                   31
+#define RX_MSDU_END_L4_OFFSET_MASK                                                  0xff000000
+
+#define RX_MSDU_END_MSDU_NUMBER_OFFSET                                              0x0000004c
+#define RX_MSDU_END_MSDU_NUMBER_LSB                                                 0
+#define RX_MSDU_END_MSDU_NUMBER_MSB                                                 7
+#define RX_MSDU_END_MSDU_NUMBER_MASK                                                0x000000ff
+
+#define RX_MSDU_END_DECAP_FORMAT_OFFSET                                             0x0000004c
+#define RX_MSDU_END_DECAP_FORMAT_LSB                                                8
+#define RX_MSDU_END_DECAP_FORMAT_MSB                                                9
+#define RX_MSDU_END_DECAP_FORMAT_MASK                                               0x00000300
+
+#define RX_MSDU_END_IPV4_PROTO_OFFSET                                               0x0000004c
+#define RX_MSDU_END_IPV4_PROTO_LSB                                                  10
+#define RX_MSDU_END_IPV4_PROTO_MSB                                                  10
+#define RX_MSDU_END_IPV4_PROTO_MASK                                                 0x00000400
+
+#define RX_MSDU_END_IPV6_PROTO_OFFSET                                               0x0000004c
+#define RX_MSDU_END_IPV6_PROTO_LSB                                                  11
+#define RX_MSDU_END_IPV6_PROTO_MSB                                                  11
+#define RX_MSDU_END_IPV6_PROTO_MASK                                                 0x00000800
+
+#define RX_MSDU_END_TCP_PROTO_OFFSET                                                0x0000004c
+#define RX_MSDU_END_TCP_PROTO_LSB                                                   12
+#define RX_MSDU_END_TCP_PROTO_MSB                                                   12
+#define RX_MSDU_END_TCP_PROTO_MASK                                                  0x00001000
+
+#define RX_MSDU_END_UDP_PROTO_OFFSET                                                0x0000004c
+#define RX_MSDU_END_UDP_PROTO_LSB                                                   13
+#define RX_MSDU_END_UDP_PROTO_MSB                                                   13
+#define RX_MSDU_END_UDP_PROTO_MASK                                                  0x00002000
+
+#define RX_MSDU_END_IP_FRAG_OFFSET                                                  0x0000004c
+#define RX_MSDU_END_IP_FRAG_LSB                                                     14
+#define RX_MSDU_END_IP_FRAG_MSB                                                     14
+#define RX_MSDU_END_IP_FRAG_MASK                                                    0x00004000
+
+#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET                                             0x0000004c
+#define RX_MSDU_END_TCP_ONLY_ACK_LSB                                                15
+#define RX_MSDU_END_TCP_ONLY_ACK_MSB                                                15
+#define RX_MSDU_END_TCP_ONLY_ACK_MASK                                               0x00008000
+
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET                                        0x0000004c
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB                                           16
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB                                           16
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK                                          0x00010000
+
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET                                        0x0000004c
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB                                           17
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB                                           18
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK                                          0x00060000
+
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET                                    0x0000004c
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB                                       19
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB                                       19
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK                                      0x00080000
+
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET                                     0x0000004c
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB                                        20
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB                                        20
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK                                       0x00100000
+
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET                                     0x0000004c
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB                                        21
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB                                        21
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK                                       0x00200000
+
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET                                     0x0000004c
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB                                        22
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB                                        22
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK                                       0x00400000
+
+#define RX_MSDU_END_LDPC_OFFSET                                                     0x0000004c
+#define RX_MSDU_END_LDPC_LSB                                                        23
+#define RX_MSDU_END_LDPC_MSB                                                        23
+#define RX_MSDU_END_LDPC_MASK                                                       0x00800000
+
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET                             0x0000004c
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB                                24
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB                                31
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK                               0xff000000
+
+#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET                                             0x00000050
+#define RX_MSDU_END_VLAN_CTAG_CI_LSB                                                0
+#define RX_MSDU_END_VLAN_CTAG_CI_MSB                                                15
+#define RX_MSDU_END_VLAN_CTAG_CI_MASK                                               0x0000ffff
+
+#define RX_MSDU_END_VLAN_STAG_CI_OFFSET                                             0x00000050
+#define RX_MSDU_END_VLAN_STAG_CI_LSB                                                16
+#define RX_MSDU_END_VLAN_STAG_CI_MSB                                                31
+#define RX_MSDU_END_VLAN_STAG_CI_MASK                                               0xffff0000
+
+#define RX_MSDU_END_PEER_META_DATA_OFFSET                                           0x00000054
+#define RX_MSDU_END_PEER_META_DATA_LSB                                              0
+#define RX_MSDU_END_PEER_META_DATA_MSB                                              31
+#define RX_MSDU_END_PEER_META_DATA_MASK                                             0xffffffff
+
+#define RX_MSDU_END_USER_RSSI_OFFSET                                                0x00000058
+#define RX_MSDU_END_USER_RSSI_LSB                                                   0
+#define RX_MSDU_END_USER_RSSI_MSB                                                   7
+#define RX_MSDU_END_USER_RSSI_MASK                                                  0x000000ff
+
+#define RX_MSDU_END_PKT_TYPE_OFFSET                                                 0x00000058
+#define RX_MSDU_END_PKT_TYPE_LSB                                                    8
+#define RX_MSDU_END_PKT_TYPE_MSB                                                    11
+#define RX_MSDU_END_PKT_TYPE_MASK                                                   0x00000f00
+
+#define RX_MSDU_END_SGI_OFFSET                                                      0x00000058
+#define RX_MSDU_END_SGI_LSB                                                         12
+#define RX_MSDU_END_SGI_MSB                                                         13
+#define RX_MSDU_END_SGI_MASK                                                        0x00003000
+
+#define RX_MSDU_END_RATE_MCS_OFFSET                                                 0x00000058
+#define RX_MSDU_END_RATE_MCS_LSB                                                    14
+#define RX_MSDU_END_RATE_MCS_MSB                                                    17
+#define RX_MSDU_END_RATE_MCS_MASK                                                   0x0003c000
+
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET                                        0x00000058
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB                                           18
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB                                           20
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK                                          0x001c0000
+
+#define RX_MSDU_END_RECEPTION_TYPE_OFFSET                                           0x00000058
+#define RX_MSDU_END_RECEPTION_TYPE_LSB                                              21
+#define RX_MSDU_END_RECEPTION_TYPE_MSB                                              23
+#define RX_MSDU_END_RECEPTION_TYPE_MASK                                             0x00e00000
+
+#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET                                           0x00000058
+#define RX_MSDU_END_MIMO_SS_BITMAP_LSB                                              24
+#define RX_MSDU_END_MIMO_SS_BITMAP_MSB                                              30
+#define RX_MSDU_END_MIMO_SS_BITMAP_MASK                                             0x7f000000
+
+#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET                                           0x00000058
+#define RX_MSDU_END_MSDU_DONE_COPY_LSB                                              31
+#define RX_MSDU_END_MSDU_DONE_COPY_MSB                                              31
+#define RX_MSDU_END_MSDU_DONE_COPY_MASK                                             0x80000000
+
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET                                         0x0000005c
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB                                            0
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB                                            31
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK                                           0xffffffff
+
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET                               0x00000060
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB                                  0
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB                                  31
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK                                 0xffffffff
+
+#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET                                         0x00000064
+#define RX_MSDU_END_SW_PHY_META_DATA_LSB                                            0
+#define RX_MSDU_END_SW_PHY_META_DATA_MSB                                            31
+#define RX_MSDU_END_SW_PHY_META_DATA_MASK                                           0xffffffff
+
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET                                0x00000068
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB                                   0
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB                                   31
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK                                  0xffffffff
+
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET                                     0x0000006c
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB                                        0
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB                                        31
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK                                       0xffffffff
+
+#define RX_MSDU_END_RESERVED_28A_OFFSET                                             0x00000070
+#define RX_MSDU_END_RESERVED_28A_LSB                                                0
+#define RX_MSDU_END_RESERVED_28A_MSB                                                15
+#define RX_MSDU_END_RESERVED_28A_MASK                                               0x0000ffff
+
+#define RX_MSDU_END_SA_15_0_OFFSET                                                  0x00000070
+#define RX_MSDU_END_SA_15_0_LSB                                                     16
+#define RX_MSDU_END_SA_15_0_MSB                                                     31
+#define RX_MSDU_END_SA_15_0_MASK                                                    0xffff0000
+
+#define RX_MSDU_END_SA_47_16_OFFSET                                                 0x00000074
+#define RX_MSDU_END_SA_47_16_LSB                                                    0
+#define RX_MSDU_END_SA_47_16_MSB                                                    31
+#define RX_MSDU_END_SA_47_16_MASK                                                   0xffffffff
+
+#define RX_MSDU_END_FIRST_MPDU_OFFSET                                               0x00000078
+#define RX_MSDU_END_FIRST_MPDU_LSB                                                  0
+#define RX_MSDU_END_FIRST_MPDU_MSB                                                  0
+#define RX_MSDU_END_FIRST_MPDU_MASK                                                 0x00000001
+
+#define RX_MSDU_END_RESERVED_30A_OFFSET                                             0x00000078
+#define RX_MSDU_END_RESERVED_30A_LSB                                                1
+#define RX_MSDU_END_RESERVED_30A_MSB                                                1
+#define RX_MSDU_END_RESERVED_30A_MASK                                               0x00000002
+
+#define RX_MSDU_END_MCAST_BCAST_OFFSET                                              0x00000078
+#define RX_MSDU_END_MCAST_BCAST_LSB                                                 2
+#define RX_MSDU_END_MCAST_BCAST_MSB                                                 2
+#define RX_MSDU_END_MCAST_BCAST_MASK                                                0x00000004
+
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET                                      0x00000078
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB                                         3
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB                                         3
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK                                        0x00000008
+
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET                                        0x00000078
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB                                           4
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB                                           4
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK                                          0x00000010
+
+#define RX_MSDU_END_POWER_MGMT_OFFSET                                               0x00000078
+#define RX_MSDU_END_POWER_MGMT_LSB                                                  5
+#define RX_MSDU_END_POWER_MGMT_MSB                                                  5
+#define RX_MSDU_END_POWER_MGMT_MASK                                                 0x00000020
+
+#define RX_MSDU_END_NON_QOS_OFFSET                                                  0x00000078
+#define RX_MSDU_END_NON_QOS_LSB                                                     6
+#define RX_MSDU_END_NON_QOS_MSB                                                     6
+#define RX_MSDU_END_NON_QOS_MASK                                                    0x00000040
+
+#define RX_MSDU_END_NULL_DATA_OFFSET                                                0x00000078
+#define RX_MSDU_END_NULL_DATA_LSB                                                   7
+#define RX_MSDU_END_NULL_DATA_MSB                                                   7
+#define RX_MSDU_END_NULL_DATA_MASK                                                  0x00000080
+
+#define RX_MSDU_END_MGMT_TYPE_OFFSET                                                0x00000078
+#define RX_MSDU_END_MGMT_TYPE_LSB                                                   8
+#define RX_MSDU_END_MGMT_TYPE_MSB                                                   8
+#define RX_MSDU_END_MGMT_TYPE_MASK                                                  0x00000100
+
+#define RX_MSDU_END_CTRL_TYPE_OFFSET                                                0x00000078
+#define RX_MSDU_END_CTRL_TYPE_LSB                                                   9
+#define RX_MSDU_END_CTRL_TYPE_MSB                                                   9
+#define RX_MSDU_END_CTRL_TYPE_MASK                                                  0x00000200
+
+#define RX_MSDU_END_MORE_DATA_OFFSET                                                0x00000078
+#define RX_MSDU_END_MORE_DATA_LSB                                                   10
+#define RX_MSDU_END_MORE_DATA_MSB                                                   10
+#define RX_MSDU_END_MORE_DATA_MASK                                                  0x00000400
+
+#define RX_MSDU_END_EOSP_OFFSET                                                     0x00000078
+#define RX_MSDU_END_EOSP_LSB                                                        11
+#define RX_MSDU_END_EOSP_MSB                                                        11
+#define RX_MSDU_END_EOSP_MASK                                                       0x00000800
+
+#define RX_MSDU_END_A_MSDU_ERROR_OFFSET                                             0x00000078
+#define RX_MSDU_END_A_MSDU_ERROR_LSB                                                12
+#define RX_MSDU_END_A_MSDU_ERROR_MSB                                                12
+#define RX_MSDU_END_A_MSDU_ERROR_MASK                                               0x00001000
+
+#define RX_MSDU_END_RESERVED_30B_OFFSET                                             0x00000078
+#define RX_MSDU_END_RESERVED_30B_LSB                                                13
+#define RX_MSDU_END_RESERVED_30B_MSB                                                13
+#define RX_MSDU_END_RESERVED_30B_MASK                                               0x00002000
+
+#define RX_MSDU_END_ORDER_OFFSET                                                    0x00000078
+#define RX_MSDU_END_ORDER_LSB                                                       14
+#define RX_MSDU_END_ORDER_MSB                                                       14
+#define RX_MSDU_END_ORDER_MASK                                                      0x00004000
+
+#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET                                        0x00000078
+#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB                                           15
+#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB                                           15
+#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK                                          0x00008000
+
+#define RX_MSDU_END_OVERFLOW_ERR_OFFSET                                             0x00000078
+#define RX_MSDU_END_OVERFLOW_ERR_LSB                                                16
+#define RX_MSDU_END_OVERFLOW_ERR_MSB                                                16
+#define RX_MSDU_END_OVERFLOW_ERR_MASK                                               0x00010000
+
+#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET                                          0x00000078
+#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB                                             17
+#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB                                             17
+#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK                                            0x00020000
+
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET                                      0x00000078
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB                                         18
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB                                         18
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK                                        0x00040000
+
+#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET                                           0x00000078
+#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB                                              19
+#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB                                              19
+#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK                                             0x00080000
+
+#define RX_MSDU_END_SA_IDX_INVALID_OFFSET                                           0x00000078
+#define RX_MSDU_END_SA_IDX_INVALID_LSB                                              20
+#define RX_MSDU_END_SA_IDX_INVALID_MSB                                              20
+#define RX_MSDU_END_SA_IDX_INVALID_MASK                                             0x00100000
+
+#define RX_MSDU_END_DA_IDX_INVALID_OFFSET                                           0x00000078
+#define RX_MSDU_END_DA_IDX_INVALID_LSB                                              21
+#define RX_MSDU_END_DA_IDX_INVALID_MSB                                              21
+#define RX_MSDU_END_DA_IDX_INVALID_MASK                                             0x00200000
+
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET                                      0x00000078
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB                                         22
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB                                         22
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK                                        0x00400000
+
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET                                     0x00000078
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB                                        23
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB                                        23
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK                                       0x00800000
+
+#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET                                         0x00000078
+#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB                                            24
+#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB                                            24
+#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK                                           0x01000000
+
+#define RX_MSDU_END_DIRECTED_OFFSET                                                 0x00000078
+#define RX_MSDU_END_DIRECTED_LSB                                                    25
+#define RX_MSDU_END_DIRECTED_MSB                                                    25
+#define RX_MSDU_END_DIRECTED_MASK                                                   0x02000000
+
+#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET                                          0x00000078
+#define RX_MSDU_END_BUFFER_FRAGMENT_LSB                                             26
+#define RX_MSDU_END_BUFFER_FRAGMENT_MSB                                             26
+#define RX_MSDU_END_BUFFER_FRAGMENT_MASK                                            0x04000000
+
+#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET                                          0x00000078
+#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB                                             27
+#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB                                             27
+#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK                                            0x08000000
+
+#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET                                             0x00000078
+#define RX_MSDU_END_TKIP_MIC_ERR_LSB                                                28
+#define RX_MSDU_END_TKIP_MIC_ERR_MSB                                                28
+#define RX_MSDU_END_TKIP_MIC_ERR_MASK                                               0x10000000
+
+#define RX_MSDU_END_DECRYPT_ERR_OFFSET                                              0x00000078
+#define RX_MSDU_END_DECRYPT_ERR_LSB                                                 29
+#define RX_MSDU_END_DECRYPT_ERR_MSB                                                 29
+#define RX_MSDU_END_DECRYPT_ERR_MASK                                                0x20000000
+
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET                                    0x00000078
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB                                       30
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB                                       30
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK                                      0x40000000
+
+#define RX_MSDU_END_FCS_ERR_OFFSET                                                  0x00000078
+#define RX_MSDU_END_FCS_ERR_LSB                                                     31
+#define RX_MSDU_END_FCS_ERR_MSB                                                     31
+#define RX_MSDU_END_FCS_ERR_MASK                                                    0x80000000
+
+#define RX_MSDU_END_RESERVED_31A_OFFSET                                             0x0000007c
+#define RX_MSDU_END_RESERVED_31A_LSB                                                0
+#define RX_MSDU_END_RESERVED_31A_MSB                                                9
+#define RX_MSDU_END_RESERVED_31A_MASK                                               0x000003ff
+
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET                                      0x0000007c
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB                                         10
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB                                         12
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK                                        0x00001c00
+
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET                                    0x0000007c
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB                                       13
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB                                       13
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK                                      0x00002000
+
+#define RX_MSDU_END_RESERVED_31B_OFFSET                                             0x0000007c
+#define RX_MSDU_END_RESERVED_31B_LSB                                                14
+#define RX_MSDU_END_RESERVED_31B_MSB                                                30
+#define RX_MSDU_END_RESERVED_31B_MASK                                               0x7fffc000
+
+#define RX_MSDU_END_MSDU_DONE_OFFSET                                                0x0000007c
+#define RX_MSDU_END_MSDU_DONE_LSB                                                   31
+#define RX_MSDU_END_MSDU_DONE_MSB                                                   31
+#define RX_MSDU_END_MSDU_DONE_MASK                                                  0x80000000
+
+#endif
diff --git a/hw/peach/v1/rx_msdu_ext_desc_info.h b/hw/peach/v1/rx_msdu_ext_desc_info.h
new file mode 100644
index 000000000000..3fc24d531259
--- /dev/null
+++ b/hw/peach/v1/rx_msdu_ext_desc_info.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MSDU_EXT_DESC_INFO_H_
+#define _RX_MSDU_EXT_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1
+
+struct rx_msdu_ext_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reo_destination_indication                              :  5,
+                      service_code                                            :  9,
+                      priority_valid                                          :  1,
+                      data_offset                                             : 12,
+                      src_link_id                                             :  3,
+                      reserved_0a                                             :  2;
+#else
+             uint32_t reserved_0a                                             :  2,
+                      src_link_id                                             :  3,
+                      data_offset                                             : 12,
+                      priority_valid                                          :  1,
+                      service_code                                            :  9,
+                      reo_destination_indication                              :  5;
+#endif
+};
+
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET                     0x00000000
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB                        0
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB                        4
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK                       0x0000001f
+
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET                                   0x00000000
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB                                      5
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB                                      13
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK                                     0x00003fe0
+
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET                                 0x00000000
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB                                    14
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB                                    14
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK                                   0x00004000
+
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET                                    0x00000000
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB                                       15
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB                                       26
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK                                      0x07ff8000
+
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET                                    0x00000000
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB                                       27
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB                                       29
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK                                      0x38000000
+
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET                                    0x00000000
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB                                       30
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB                                       31
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK                                      0xc0000000
+
+#endif
diff --git a/hw/peach/v1/rx_msdu_link.h b/hw/peach/v1/rx_msdu_link.h
new file mode 100644
index 000000000000..7506bfd60465
--- /dev/null
+++ b/hw/peach/v1/rx_msdu_link.h
@@ -0,0 +1,917 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MSDU_LINK_H_
+#define _RX_MSDU_LINK_H_
+
+#include "uniform_descriptor_header.h"
+#include "buffer_addr_info.h"
+#include "rx_msdu_details.h"
+#define NUM_OF_DWORDS_RX_MSDU_LINK 32
+
+struct rx_msdu_link {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_descriptor_header                                 descriptor_header;
+             struct   buffer_addr_info                                          next_msdu_link_desc_addr_info;
+             uint32_t receive_queue_number                                    : 16,
+                      first_rx_msdu_link_struct                               :  1,
+                      reserved_3a                                             : 15;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             struct   rx_msdu_details                                           msdu_0;
+             struct   rx_msdu_details                                           msdu_1;
+             struct   rx_msdu_details                                           msdu_2;
+             struct   rx_msdu_details                                           msdu_3;
+             struct   rx_msdu_details                                           msdu_4;
+             struct   rx_msdu_details                                           msdu_5;
+#else
+             struct   uniform_descriptor_header                                 descriptor_header;
+             struct   buffer_addr_info                                          next_msdu_link_desc_addr_info;
+             uint32_t reserved_3a                                             : 15,
+                      first_rx_msdu_link_struct                               :  1,
+                      receive_queue_number                                    : 16;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             struct   rx_msdu_details                                           msdu_0;
+             struct   rx_msdu_details                                           msdu_1;
+             struct   rx_msdu_details                                           msdu_2;
+             struct   rx_msdu_details                                           msdu_3;
+             struct   rx_msdu_details                                           msdu_4;
+             struct   rx_msdu_details                                           msdu_5;
+#endif
+};
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET                                 0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB                                    0
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB                                    3
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK                                   0x0000000f
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                           0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                              4
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                              7
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                             0x000000f0
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET                  0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                     8
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                     27
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                    0x0fffff00
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                           0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB                              28
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB                              31
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK                             0xf0000000
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET          0x00000004
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB             0
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB             31
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK            0xffffffff
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET         0x00000008
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB            0
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB            7
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK           0x000000ff
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET     0x00000008
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB        8
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB        11
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK       0x00000f00
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET          0x00000008
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB             12
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB             31
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK            0xfffff000
+
+#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_OFFSET                                    0x0000000c
+#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_LSB                                       0
+#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MSB                                       15
+#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MASK                                      0x0000ffff
+
+#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_OFFSET                               0x0000000c
+#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_LSB                                  16
+#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MSB                                  16
+#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MASK                                 0x00010000
+
+#define RX_MSDU_LINK_RESERVED_3A_OFFSET                                             0x0000000c
+#define RX_MSDU_LINK_RESERVED_3A_LSB                                                17
+#define RX_MSDU_LINK_RESERVED_3A_MSB                                                31
+#define RX_MSDU_LINK_RESERVED_3A_MASK                                               0xfffe0000
+
+#define RX_MSDU_LINK_PN_31_0_OFFSET                                                 0x00000010
+#define RX_MSDU_LINK_PN_31_0_LSB                                                    0
+#define RX_MSDU_LINK_PN_31_0_MSB                                                    31
+#define RX_MSDU_LINK_PN_31_0_MASK                                                   0xffffffff
+
+#define RX_MSDU_LINK_PN_63_32_OFFSET                                                0x00000014
+#define RX_MSDU_LINK_PN_63_32_LSB                                                   0
+#define RX_MSDU_LINK_PN_63_32_MSB                                                   31
+#define RX_MSDU_LINK_PN_63_32_MASK                                                  0xffffffff
+
+#define RX_MSDU_LINK_PN_95_64_OFFSET                                                0x00000018
+#define RX_MSDU_LINK_PN_95_64_LSB                                                   0
+#define RX_MSDU_LINK_PN_95_64_MSB                                                   31
+#define RX_MSDU_LINK_PN_95_64_MASK                                                  0xffffffff
+
+#define RX_MSDU_LINK_PN_127_96_OFFSET                                               0x0000001c
+#define RX_MSDU_LINK_PN_127_96_LSB                                                  0
+#define RX_MSDU_LINK_PN_127_96_MSB                                                  31
+#define RX_MSDU_LINK_PN_127_96_MASK                                                 0xffffffff
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000020
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000024
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000024
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000024
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000002c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000002c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000002c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000002c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000002c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000030
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000034
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000034
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000034
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000003c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000003c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000003c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000003c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000003c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000040
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000044
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000044
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000044
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000004c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000004c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000004c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000004c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000004c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000050
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000054
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000054
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000054
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000005c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000005c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000005c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000005c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000005c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000060
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000064
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000064
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000064
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000006c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000006c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000006c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000006c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000006c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET        0x00000070
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB           0
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB           31
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK          0xffffffff
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET       0x00000074
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB          0
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB          7
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK         0x000000ff
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET   0x00000074
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB      8
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB      11
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK     0x00000f00
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET        0x00000074
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB           12
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB           31
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK          0xfffff000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET       0x0000007c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB          5
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB          13
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK         0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET     0x0000007c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB        14
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB        14
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK       0x00004000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET        0x0000007c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB           15
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB           26
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK          0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET        0x0000007c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB           27
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB           29
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK          0x38000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET        0x0000007c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB           30
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB           31
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK          0xc0000000
+
+#endif
diff --git a/hw/peach/v1/rx_msdu_start.h b/hw/peach/v1/rx_msdu_start.h
new file mode 100644
index 000000000000..6dbba7795115
--- /dev/null
+++ b/hw/peach/v1/rx_msdu_start.h
@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MSDU_START_H_
+#define _RX_MSDU_START_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_START 10
+
+struct rx_msdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+             uint32_t msdu_length                                             : 14,
+                      stbc                                                    :  1,
+                      ipsec_esp                                               :  1,
+                      l3_offset                                               :  7,
+                      ipsec_ah                                                :  1,
+                      l4_offset                                               :  8;
+             uint32_t msdu_number                                             :  8,
+                      decap_format                                            :  2,
+                      ipv4_proto                                              :  1,
+                      ipv6_proto                                              :  1,
+                      tcp_proto                                               :  1,
+                      udp_proto                                               :  1,
+                      ip_frag                                                 :  1,
+                      tcp_only_ack                                            :  1,
+                      da_is_bcast_mcast                                       :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      ip_fixed_header_valid                                   :  1,
+                      ip_extn_header_valid                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      mesh_control_present                                    :  1,
+                      ldpc                                                    :  1,
+                      ip4_protocol_ip6_next_header                            :  8;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t user_rssi                                               :  8,
+                      pkt_type                                                :  4,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  4,
+                      receive_bandwidth                                       :  3,
+                      reception_type                                          :  3,
+                      mimo_ss_bitmap                                          :  8;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t vlan_ctag_ci                                            : 16,
+                      vlan_stag_ci                                            : 16;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t l4_offset                                               :  8,
+                      ipsec_ah                                                :  1,
+                      l3_offset                                               :  7,
+                      ipsec_esp                                               :  1,
+                      stbc                                                    :  1,
+                      msdu_length                                             : 14;
+             uint32_t ip4_protocol_ip6_next_header                            :  8,
+                      ldpc                                                    :  1,
+                      mesh_control_present                                    :  1,
+                      tcp_udp_header_valid                                    :  1,
+                      ip_extn_header_valid                                    :  1,
+                      ip_fixed_header_valid                                   :  1,
+                      toeplitz_hash_sel                                       :  2,
+                      da_is_bcast_mcast                                       :  1,
+                      tcp_only_ack                                            :  1,
+                      ip_frag                                                 :  1,
+                      udp_proto                                               :  1,
+                      tcp_proto                                               :  1,
+                      ipv6_proto                                              :  1,
+                      ipv4_proto                                              :  1,
+                      decap_format                                            :  2,
+                      msdu_number                                             :  8;
+             uint32_t toeplitz_hash_2_or_4                                    : 32;
+             uint32_t flow_id_toeplitz                                        : 32;
+             uint32_t mimo_ss_bitmap                                          :  8,
+                      reception_type                                          :  3,
+                      receive_bandwidth                                       :  3,
+                      rate_mcs                                                :  4,
+                      sgi                                                     :  2,
+                      pkt_type                                                :  4,
+                      user_rssi                                               :  8;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t vlan_stag_ci                                            : 16,
+                      vlan_ctag_ci                                            : 16;
+#endif
+};
+
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                          0x00000000
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                             0
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                             1
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                            0x00000003
+
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET                                      0x00000000
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB                                         2
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB                                         8
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK                                        0x000001fc
+
+#define RX_MSDU_START_RESERVED_0_OFFSET                                             0x00000000
+#define RX_MSDU_START_RESERVED_0_LSB                                                9
+#define RX_MSDU_START_RESERVED_0_MSB                                                15
+#define RX_MSDU_START_RESERVED_0_MASK                                               0x0000fe00
+
+#define RX_MSDU_START_PHY_PPDU_ID_OFFSET                                            0x00000000
+#define RX_MSDU_START_PHY_PPDU_ID_LSB                                               16
+#define RX_MSDU_START_PHY_PPDU_ID_MSB                                               31
+#define RX_MSDU_START_PHY_PPDU_ID_MASK                                              0xffff0000
+
+#define RX_MSDU_START_MSDU_LENGTH_OFFSET                                            0x00000004
+#define RX_MSDU_START_MSDU_LENGTH_LSB                                               0
+#define RX_MSDU_START_MSDU_LENGTH_MSB                                               13
+#define RX_MSDU_START_MSDU_LENGTH_MASK                                              0x00003fff
+
+#define RX_MSDU_START_STBC_OFFSET                                                   0x00000004
+#define RX_MSDU_START_STBC_LSB                                                      14
+#define RX_MSDU_START_STBC_MSB                                                      14
+#define RX_MSDU_START_STBC_MASK                                                     0x00004000
+
+#define RX_MSDU_START_IPSEC_ESP_OFFSET                                              0x00000004
+#define RX_MSDU_START_IPSEC_ESP_LSB                                                 15
+#define RX_MSDU_START_IPSEC_ESP_MSB                                                 15
+#define RX_MSDU_START_IPSEC_ESP_MASK                                                0x00008000
+
+#define RX_MSDU_START_L3_OFFSET_OFFSET                                              0x00000004
+#define RX_MSDU_START_L3_OFFSET_LSB                                                 16
+#define RX_MSDU_START_L3_OFFSET_MSB                                                 22
+#define RX_MSDU_START_L3_OFFSET_MASK                                                0x007f0000
+
+#define RX_MSDU_START_IPSEC_AH_OFFSET                                               0x00000004
+#define RX_MSDU_START_IPSEC_AH_LSB                                                  23
+#define RX_MSDU_START_IPSEC_AH_MSB                                                  23
+#define RX_MSDU_START_IPSEC_AH_MASK                                                 0x00800000
+
+#define RX_MSDU_START_L4_OFFSET_OFFSET                                              0x00000004
+#define RX_MSDU_START_L4_OFFSET_LSB                                                 24
+#define RX_MSDU_START_L4_OFFSET_MSB                                                 31
+#define RX_MSDU_START_L4_OFFSET_MASK                                                0xff000000
+
+#define RX_MSDU_START_MSDU_NUMBER_OFFSET                                            0x00000008
+#define RX_MSDU_START_MSDU_NUMBER_LSB                                               0
+#define RX_MSDU_START_MSDU_NUMBER_MSB                                               7
+#define RX_MSDU_START_MSDU_NUMBER_MASK                                              0x000000ff
+
+#define RX_MSDU_START_DECAP_FORMAT_OFFSET                                           0x00000008
+#define RX_MSDU_START_DECAP_FORMAT_LSB                                              8
+#define RX_MSDU_START_DECAP_FORMAT_MSB                                              9
+#define RX_MSDU_START_DECAP_FORMAT_MASK                                             0x00000300
+
+#define RX_MSDU_START_IPV4_PROTO_OFFSET                                             0x00000008
+#define RX_MSDU_START_IPV4_PROTO_LSB                                                10
+#define RX_MSDU_START_IPV4_PROTO_MSB                                                10
+#define RX_MSDU_START_IPV4_PROTO_MASK                                               0x00000400
+
+#define RX_MSDU_START_IPV6_PROTO_OFFSET                                             0x00000008
+#define RX_MSDU_START_IPV6_PROTO_LSB                                                11
+#define RX_MSDU_START_IPV6_PROTO_MSB                                                11
+#define RX_MSDU_START_IPV6_PROTO_MASK                                               0x00000800
+
+#define RX_MSDU_START_TCP_PROTO_OFFSET                                              0x00000008
+#define RX_MSDU_START_TCP_PROTO_LSB                                                 12
+#define RX_MSDU_START_TCP_PROTO_MSB                                                 12
+#define RX_MSDU_START_TCP_PROTO_MASK                                                0x00001000
+
+#define RX_MSDU_START_UDP_PROTO_OFFSET                                              0x00000008
+#define RX_MSDU_START_UDP_PROTO_LSB                                                 13
+#define RX_MSDU_START_UDP_PROTO_MSB                                                 13
+#define RX_MSDU_START_UDP_PROTO_MASK                                                0x00002000
+
+#define RX_MSDU_START_IP_FRAG_OFFSET                                                0x00000008
+#define RX_MSDU_START_IP_FRAG_LSB                                                   14
+#define RX_MSDU_START_IP_FRAG_MSB                                                   14
+#define RX_MSDU_START_IP_FRAG_MASK                                                  0x00004000
+
+#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET                                           0x00000008
+#define RX_MSDU_START_TCP_ONLY_ACK_LSB                                              15
+#define RX_MSDU_START_TCP_ONLY_ACK_MSB                                              15
+#define RX_MSDU_START_TCP_ONLY_ACK_MASK                                             0x00008000
+
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET                                      0x00000008
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB                                         16
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB                                         16
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK                                        0x00010000
+
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET                                      0x00000008
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB                                         17
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB                                         18
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK                                        0x00060000
+
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET                                  0x00000008
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB                                     19
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB                                     19
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK                                    0x00080000
+
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET                                   0x00000008
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB                                      20
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB                                      20
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK                                     0x00100000
+
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET                                   0x00000008
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB                                      21
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB                                      21
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK                                     0x00200000
+
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET                                   0x00000008
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB                                      22
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB                                      22
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK                                     0x00400000
+
+#define RX_MSDU_START_LDPC_OFFSET                                                   0x00000008
+#define RX_MSDU_START_LDPC_LSB                                                      23
+#define RX_MSDU_START_LDPC_MSB                                                      23
+#define RX_MSDU_START_LDPC_MASK                                                     0x00800000
+
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET                           0x00000008
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB                              24
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB                              31
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK                             0xff000000
+
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET                                   0x0000000c
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB                                      0
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB                                      31
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK                                     0xffffffff
+
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET                                       0x00000010
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB                                          0
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB                                          31
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK                                         0xffffffff
+
+#define RX_MSDU_START_USER_RSSI_OFFSET                                              0x00000014
+#define RX_MSDU_START_USER_RSSI_LSB                                                 0
+#define RX_MSDU_START_USER_RSSI_MSB                                                 7
+#define RX_MSDU_START_USER_RSSI_MASK                                                0x000000ff
+
+#define RX_MSDU_START_PKT_TYPE_OFFSET                                               0x00000014
+#define RX_MSDU_START_PKT_TYPE_LSB                                                  8
+#define RX_MSDU_START_PKT_TYPE_MSB                                                  11
+#define RX_MSDU_START_PKT_TYPE_MASK                                                 0x00000f00
+
+#define RX_MSDU_START_SGI_OFFSET                                                    0x00000014
+#define RX_MSDU_START_SGI_LSB                                                       12
+#define RX_MSDU_START_SGI_MSB                                                       13
+#define RX_MSDU_START_SGI_MASK                                                      0x00003000
+
+#define RX_MSDU_START_RATE_MCS_OFFSET                                               0x00000014
+#define RX_MSDU_START_RATE_MCS_LSB                                                  14
+#define RX_MSDU_START_RATE_MCS_MSB                                                  17
+#define RX_MSDU_START_RATE_MCS_MASK                                                 0x0003c000
+
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET                                      0x00000014
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB                                         18
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB                                         20
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK                                        0x001c0000
+
+#define RX_MSDU_START_RECEPTION_TYPE_OFFSET                                         0x00000014
+#define RX_MSDU_START_RECEPTION_TYPE_LSB                                            21
+#define RX_MSDU_START_RECEPTION_TYPE_MSB                                            23
+#define RX_MSDU_START_RECEPTION_TYPE_MASK                                           0x00e00000
+
+#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET                                         0x00000014
+#define RX_MSDU_START_MIMO_SS_BITMAP_LSB                                            24
+#define RX_MSDU_START_MIMO_SS_BITMAP_MSB                                            31
+#define RX_MSDU_START_MIMO_SS_BITMAP_MASK                                           0xff000000
+
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET                              0x00000018
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB                                 0
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB                                 31
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK                                0xffffffff
+
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET                             0x0000001c
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB                                0
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB                                31
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK                               0xffffffff
+
+#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET                                       0x00000020
+#define RX_MSDU_START_SW_PHY_META_DATA_LSB                                          0
+#define RX_MSDU_START_SW_PHY_META_DATA_MSB                                          31
+#define RX_MSDU_START_SW_PHY_META_DATA_MASK                                         0xffffffff
+
+#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET                                           0x00000024
+#define RX_MSDU_START_VLAN_CTAG_CI_LSB                                              0
+#define RX_MSDU_START_VLAN_CTAG_CI_MSB                                              15
+#define RX_MSDU_START_VLAN_CTAG_CI_MASK                                             0x0000ffff
+
+#define RX_MSDU_START_VLAN_STAG_CI_OFFSET                                           0x00000024
+#define RX_MSDU_START_VLAN_STAG_CI_LSB                                              16
+#define RX_MSDU_START_VLAN_STAG_CI_MSB                                              31
+#define RX_MSDU_START_VLAN_STAG_CI_MASK                                             0xffff0000
+
+#endif
diff --git a/hw/peach/v1/rx_ppdu_ack_report.h b/hw/peach/v1/rx_ppdu_ack_report.h
new file mode 100644
index 000000000000..91bf12463386
--- /dev/null
+++ b/hw/peach/v1/rx_ppdu_ack_report.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_PPDU_ACK_REPORT_H_
+#define _RX_PPDU_ACK_REPORT_H_
+
+#include "ack_report.h"
+#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 1
+
+struct rx_ppdu_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   ack_report                                                ack_report_details;
+#else
+             struct   ack_report                                                ack_report_details;
+#endif
+};
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET        0x00000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB           0
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB           3
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK          0x0000000f
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET                0x00000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB                   4
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB                   7
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK                  0x000000f0
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET                        0x00000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB                           8
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB                           8
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK                          0x00000100
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET                       0x00000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB                          9
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB                          15
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK                         0x0000fe00
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET                  0x00000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB                     16
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB                     31
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK                    0xffff0000
+
+#endif
diff --git a/hw/peach/v1/rx_ppdu_end_user_stats.h b/hw/peach/v1/rx_ppdu_end_user_stats.h
new file mode 100644
index 000000000000..e08c0dbe0e0f
--- /dev/null
+++ b/hw/peach/v1/rx_ppdu_end_user_stats.h
@@ -0,0 +1,703 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_PPDU_END_USER_STATS_H_
+#define _RX_PPDU_END_USER_STATS_H_
+
+#include "rx_rxpcu_classification_overview.h"
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30
+
+struct rx_ppdu_end_user_stats {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t sta_full_aid                                            : 13,
+                      mcs                                                     :  4,
+                      nss                                                     :  3,
+                      expected_response_ack_or_ba                             :  1,
+                      reserved_1a                                             : 11;
+             uint32_t sw_peer_id                                              : 16,
+                      mpdu_cnt_fcs_err                                        : 11,
+                      sw2rxdma0_buf_source_used                               :  1,
+                      fw2rxdma_pmac0_buf_source_used                          :  1,
+                      sw2rxdma1_buf_source_used                               :  1,
+                      sw2rxdma_exception_buf_source_used                      :  1,
+                      fw2rxdma_pmac1_buf_source_used                          :  1;
+             uint32_t mpdu_cnt_fcs_ok                                         : 11,
+                      frame_control_info_valid                                :  1,
+                      qos_control_info_valid                                  :  1,
+                      ht_control_info_valid                                   :  1,
+                      data_sequence_control_info_valid                        :  1,
+                      ht_control_info_null_valid                              :  1,
+                      rxdma2fw_pmac1_ring_used                                :  1,
+                      rxdma2reo_ring_used                                     :  1,
+                      rxdma2fw_pmac0_ring_used                                :  1,
+                      rxdma2sw_ring_used                                      :  1,
+                      rxdma_release_ring_used                                 :  1,
+                      ht_control_field_pkt_type                               :  4,
+                      rxdma2reo_remote0_ring_used                             :  1,
+                      rxdma2reo_remote1_ring_used                             :  1,
+                      reserved_3b                                             :  5;
+             uint32_t ast_index                                               : 16,
+                      frame_control_field                                     : 16;
+             uint32_t first_data_seq_ctrl                                     : 16,
+                      qos_control_field                                       : 16;
+             uint32_t ht_control_field                                        : 32;
+             uint32_t fcs_ok_bitmap_31_0                                      : 32;
+             uint32_t fcs_ok_bitmap_63_32                                     : 32;
+             uint32_t udp_msdu_count                                          : 16,
+                      tcp_msdu_count                                          : 16;
+             uint32_t other_msdu_count                                        : 16,
+                      tcp_ack_msdu_count                                      : 16;
+             uint32_t sw_response_reference_ptr                               : 32;
+             uint32_t received_qos_data_tid_bitmap                            : 16,
+                      received_qos_data_tid_eosp_bitmap                       : 16;
+             uint32_t qosctrl_15_8_tid0                                       :  8,
+                      qosctrl_15_8_tid1                                       :  8,
+                      qosctrl_15_8_tid2                                       :  8,
+                      qosctrl_15_8_tid3                                       :  8;
+             uint32_t qosctrl_15_8_tid4                                       :  8,
+                      qosctrl_15_8_tid5                                       :  8,
+                      qosctrl_15_8_tid6                                       :  8,
+                      qosctrl_15_8_tid7                                       :  8;
+             uint32_t qosctrl_15_8_tid8                                       :  8,
+                      qosctrl_15_8_tid9                                       :  8,
+                      qosctrl_15_8_tid10                                      :  8,
+                      qosctrl_15_8_tid11                                      :  8;
+             uint32_t qosctrl_15_8_tid12                                      :  8,
+                      qosctrl_15_8_tid13                                      :  8,
+                      qosctrl_15_8_tid14                                      :  8,
+                      qosctrl_15_8_tid15                                      :  8;
+             uint32_t mpdu_ok_byte_count                                      : 25,
+                      ampdu_delim_ok_count_6_0                                :  7;
+             uint32_t ampdu_delim_err_count                                   : 25,
+                      ampdu_delim_ok_count_13_7                               :  7;
+             uint32_t mpdu_err_byte_count                                     : 25,
+                      ampdu_delim_ok_count_20_14                              :  7;
+             uint32_t non_consecutive_delimiter_err                           : 16,
+                      retried_msdu_count                                      : 16;
+             uint32_t ht_control_null_field                                   : 32;
+             uint32_t sw_response_reference_ptr_ext                           : 32;
+             uint32_t corrupted_due_to_fifo_delay                             :  1,
+                      frame_control_info_null_valid                           :  1,
+                      frame_control_field_null                                : 16,
+                      retried_mpdu_count                                      : 11,
+                      reserved_23a                                            :  3;
+             uint32_t rxpcu_mpdu_filter_in_category                           :  2,
+                      sw_frame_group_id                                       :  7,
+                      reserved_24a                                            :  4,
+                      frame_control_info_mgmt_ctrl_valid                      :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      mcast_bcast                                             :  1,
+                      frame_control_field_mgmt_ctrl                           : 16;
+             uint32_t user_ppdu_len                                           : 24,
+                      reserved_25a                                            :  8;
+             uint32_t mac_addr_ad2_31_0                                       : 32;
+             uint32_t mac_addr_ad2_47_32                                      : 16,
+                      amsdu_msdu_count                                        : 16;
+             uint32_t non_amsdu_msdu_count                                    : 16,
+                      ucast_msdu_count                                        : 16;
+             uint32_t bcast_msdu_count                                        : 16,
+                      mcast_bcast_msdu_count                                  : 16;
+#else
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t reserved_1a                                             : 11,
+                      expected_response_ack_or_ba                             :  1,
+                      nss                                                     :  3,
+                      mcs                                                     :  4,
+                      sta_full_aid                                            : 13;
+             uint32_t fw2rxdma_pmac1_buf_source_used                          :  1,
+                      sw2rxdma_exception_buf_source_used                      :  1,
+                      sw2rxdma1_buf_source_used                               :  1,
+                      fw2rxdma_pmac0_buf_source_used                          :  1,
+                      sw2rxdma0_buf_source_used                               :  1,
+                      mpdu_cnt_fcs_err                                        : 11,
+                      sw_peer_id                                              : 16;
+             uint32_t reserved_3b                                             :  5,
+                      rxdma2reo_remote1_ring_used                             :  1,
+                      rxdma2reo_remote0_ring_used                             :  1,
+                      ht_control_field_pkt_type                               :  4,
+                      rxdma_release_ring_used                                 :  1,
+                      rxdma2sw_ring_used                                      :  1,
+                      rxdma2fw_pmac0_ring_used                                :  1,
+                      rxdma2reo_ring_used                                     :  1,
+                      rxdma2fw_pmac1_ring_used                                :  1,
+                      ht_control_info_null_valid                              :  1,
+                      data_sequence_control_info_valid                        :  1,
+                      ht_control_info_valid                                   :  1,
+                      qos_control_info_valid                                  :  1,
+                      frame_control_info_valid                                :  1,
+                      mpdu_cnt_fcs_ok                                         : 11;
+             uint32_t frame_control_field                                     : 16,
+                      ast_index                                               : 16;
+             uint32_t qos_control_field                                       : 16,
+                      first_data_seq_ctrl                                     : 16;
+             uint32_t ht_control_field                                        : 32;
+             uint32_t fcs_ok_bitmap_31_0                                      : 32;
+             uint32_t fcs_ok_bitmap_63_32                                     : 32;
+             uint32_t tcp_msdu_count                                          : 16,
+                      udp_msdu_count                                          : 16;
+             uint32_t tcp_ack_msdu_count                                      : 16,
+                      other_msdu_count                                        : 16;
+             uint32_t sw_response_reference_ptr                               : 32;
+             uint32_t received_qos_data_tid_eosp_bitmap                       : 16,
+                      received_qos_data_tid_bitmap                            : 16;
+             uint32_t qosctrl_15_8_tid3                                       :  8,
+                      qosctrl_15_8_tid2                                       :  8,
+                      qosctrl_15_8_tid1                                       :  8,
+                      qosctrl_15_8_tid0                                       :  8;
+             uint32_t qosctrl_15_8_tid7                                       :  8,
+                      qosctrl_15_8_tid6                                       :  8,
+                      qosctrl_15_8_tid5                                       :  8,
+                      qosctrl_15_8_tid4                                       :  8;
+             uint32_t qosctrl_15_8_tid11                                      :  8,
+                      qosctrl_15_8_tid10                                      :  8,
+                      qosctrl_15_8_tid9                                       :  8,
+                      qosctrl_15_8_tid8                                       :  8;
+             uint32_t qosctrl_15_8_tid15                                      :  8,
+                      qosctrl_15_8_tid14                                      :  8,
+                      qosctrl_15_8_tid13                                      :  8,
+                      qosctrl_15_8_tid12                                      :  8;
+             uint32_t ampdu_delim_ok_count_6_0                                :  7,
+                      mpdu_ok_byte_count                                      : 25;
+             uint32_t ampdu_delim_ok_count_13_7                               :  7,
+                      ampdu_delim_err_count                                   : 25;
+             uint32_t ampdu_delim_ok_count_20_14                              :  7,
+                      mpdu_err_byte_count                                     : 25;
+             uint32_t retried_msdu_count                                      : 16,
+                      non_consecutive_delimiter_err                           : 16;
+             uint32_t ht_control_null_field                                   : 32;
+             uint32_t sw_response_reference_ptr_ext                           : 32;
+             uint32_t reserved_23a                                            :  3,
+                      retried_mpdu_count                                      : 11,
+                      frame_control_field_null                                : 16,
+                      frame_control_info_null_valid                           :  1,
+                      corrupted_due_to_fifo_delay                             :  1;
+             uint32_t frame_control_field_mgmt_ctrl                           : 16,
+                      mcast_bcast                                             :  1,
+                      mac_addr_ad2_valid                                      :  1,
+                      frame_control_info_mgmt_ctrl_valid                      :  1,
+                      reserved_24a                                            :  4,
+                      sw_frame_group_id                                       :  7,
+                      rxpcu_mpdu_filter_in_category                           :  2;
+             uint32_t reserved_25a                                            :  8,
+                      user_ppdu_len                                           : 24;
+             uint32_t mac_addr_ad2_31_0                                       : 32;
+             uint32_t amsdu_msdu_count                                        : 16,
+                      mac_addr_ad2_47_32                                      : 16;
+             uint32_t ucast_msdu_count                                        : 16,
+                      non_amsdu_msdu_count                                    : 16;
+             uint32_t mcast_bcast_msdu_count                                  : 16,
+                      bcast_msdu_count                                        : 16;
+#endif
+};
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB   0
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB   0
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK  0x00000001
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET       0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB          9
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB          15
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK         0x0000fe00
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET      0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB         16
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB         31
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK        0xffff0000
+
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET                                  0x00000004
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB                                     0
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB                                     12
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK                                    0x00001fff
+
+#define RX_PPDU_END_USER_STATS_MCS_OFFSET                                           0x00000004
+#define RX_PPDU_END_USER_STATS_MCS_LSB                                              13
+#define RX_PPDU_END_USER_STATS_MCS_MSB                                              16
+#define RX_PPDU_END_USER_STATS_MCS_MASK                                             0x0001e000
+
+#define RX_PPDU_END_USER_STATS_NSS_OFFSET                                           0x00000004
+#define RX_PPDU_END_USER_STATS_NSS_LSB                                              17
+#define RX_PPDU_END_USER_STATS_NSS_MSB                                              19
+#define RX_PPDU_END_USER_STATS_NSS_MASK                                             0x000e0000
+
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET                   0x00000004
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB                      20
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB                      20
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK                     0x00100000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET                                   0x00000004
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB                                      21
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB                                      31
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK                                     0xffe00000
+
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET                                    0x00000008
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB                                       0
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB                                       15
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK                                      0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET                              0x00000008
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB                                 16
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB                                 26
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK                                0x07ff0000
+
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET                     0x00000008
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB                        27
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB                        27
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK                       0x08000000
+
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET                0x00000008
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB                   28
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB                   28
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK                  0x10000000
+
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET                     0x00000008
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB                        29
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB                        29
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK                       0x20000000
+
+#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET            0x00000008
+#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB               30
+#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB               30
+#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK              0x40000000
+
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET                0x00000008
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB                   31
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB                   31
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK                  0x80000000
+
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET                               0x0000000c
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB                                  0
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB                                  10
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK                                 0x000007ff
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET                      0x0000000c
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB                         11
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB                         11
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK                        0x00000800
+
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET                        0x0000000c
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB                           12
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB                           12
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK                          0x00001000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET                         0x0000000c
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB                            13
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB                            13
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK                           0x00002000
+
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET              0x0000000c
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB                 14
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB                 14
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK                0x00004000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET                    0x0000000c
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB                       15
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB                       15
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK                      0x00008000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET                      0x0000000c
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB                         16
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB                         16
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK                        0x00010000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET                           0x0000000c
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB                              17
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB                              17
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK                             0x00020000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET                      0x0000000c
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB                         18
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB                         18
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK                        0x00040000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET                            0x0000000c
+#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB                               19
+#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB                               19
+#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK                              0x00080000
+
+#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET                       0x0000000c
+#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB                          20
+#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB                          20
+#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK                         0x00100000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET                     0x0000000c
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB                        21
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB                        24
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK                       0x01e00000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_OFFSET                   0x0000000c
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_LSB                      25
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MSB                      25
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MASK                     0x02000000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_OFFSET                   0x0000000c
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_LSB                      26
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MSB                      26
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MASK                     0x04000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET                                   0x0000000c
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB                                      27
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB                                      31
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK                                     0xf8000000
+
+#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET                                     0x00000010
+#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB                                        0
+#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB                                        15
+#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK                                       0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET                           0x00000010
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB                              16
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB                              31
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK                             0xffff0000
+
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET                           0x00000014
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB                              0
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB                              15
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK                             0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET                             0x00000014
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB                                16
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB                                31
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK                               0xffff0000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET                              0x00000018
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB                                 0
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB                                 31
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK                                0xffffffff
+
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET                            0x0000001c
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB                               0
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB                               31
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK                              0xffffffff
+
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET                           0x00000020
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB                              0
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB                              31
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK                             0xffffffff
+
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET                                0x00000024
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB                                   0
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB                                   15
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK                                  0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET                                0x00000024
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB                                   16
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB                                   31
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK                                  0xffff0000
+
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET                              0x00000028
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB                                 0
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB                                 15
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK                                0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET                            0x00000028
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB                               16
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB                               31
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK                              0xffff0000
+
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET                     0x0000002c
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB                        0
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB                        31
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK                       0xffffffff
+
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET                  0x00000030
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB                     0
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB                     15
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK                    0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET             0x00000030
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB                16
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB                31
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK               0xffff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET                             0x00000034
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB                                0
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB                                7
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK                               0x000000ff
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET                             0x00000034
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB                                8
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB                                15
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK                               0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET                             0x00000034
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB                                16
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB                                23
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK                               0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET                             0x00000034
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB                                24
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB                                31
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK                               0xff000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET                             0x00000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB                                0
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB                                7
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK                               0x000000ff
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET                             0x00000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB                                8
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB                                15
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK                               0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET                             0x00000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB                                16
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB                                23
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK                               0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET                             0x00000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB                                24
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB                                31
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK                               0xff000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET                             0x0000003c
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB                                0
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB                                7
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK                               0x000000ff
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET                             0x0000003c
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB                                8
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB                                15
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK                               0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET                            0x0000003c
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB                               16
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB                               23
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK                              0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET                            0x0000003c
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB                               24
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB                               31
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK                              0xff000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET                            0x00000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB                               0
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB                               7
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK                              0x000000ff
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET                            0x00000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB                               8
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB                               15
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK                              0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET                            0x00000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB                               16
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB                               23
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK                              0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET                            0x00000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB                               24
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB                               31
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK                              0xff000000
+
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET                            0x00000044
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB                               0
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB                               24
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK                              0x01ffffff
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET                      0x00000044
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB                         25
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB                         31
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK                        0xfe000000
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET                         0x00000048
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB                            0
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB                            24
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK                           0x01ffffff
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET                     0x00000048
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB                        25
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB                        31
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK                       0xfe000000
+
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET                           0x0000004c
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB                              0
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB                              24
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK                             0x01ffffff
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET                    0x0000004c
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB                       25
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB                       31
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK                      0xfe000000
+
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET                 0x00000050
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB                    0
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB                    15
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK                   0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET                            0x00000050
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB                               16
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB                               31
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK                              0xffff0000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET                         0x00000054
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB                            0
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB                            31
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK                           0xffffffff
+
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET                 0x00000058
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB                    0
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB                    31
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK                   0xffffffff
+
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET                   0x0000005c
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB                      0
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB                      0
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK                     0x00000001
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET                 0x0000005c
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB                    1
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB                    1
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK                   0x00000002
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET                      0x0000005c
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB                         2
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB                         17
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK                        0x0003fffc
+
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET                            0x0000005c
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB                               18
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB                               28
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK                              0x1ffc0000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET                                  0x0000005c
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB                                     29
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB                                     31
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK                                    0xe0000000
+
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET                 0x00000060
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB                    0
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB                    1
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK                   0x00000003
+
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET                             0x00000060
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB                                2
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB                                8
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK                               0x000001fc
+
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET                                  0x00000060
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB                                     9
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB                                     12
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK                                    0x00001e00
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET            0x00000060
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB               13
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB               13
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK              0x00002000
+
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET                            0x00000060
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB                               14
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB                               14
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK                              0x00004000
+
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET                                   0x00000060
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB                                      15
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB                                      15
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK                                     0x00008000
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET                 0x00000060
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB                    16
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB                    31
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK                   0xffff0000
+
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET                                 0x00000064
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB                                    0
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB                                    23
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK                                   0x00ffffff
+
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET                                  0x00000064
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB                                     24
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB                                     31
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK                                    0xff000000
+
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET                             0x00000068
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB                                0
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB                                31
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK                               0xffffffff
+
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET                            0x0000006c
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB                               0
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB                               15
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK                              0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET                              0x0000006c
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB                                 16
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB                                 31
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK                                0xffff0000
+
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET                          0x00000070
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB                             0
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB                             15
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK                            0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET                              0x00000070
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB                                 16
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB                                 31
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK                                0xffff0000
+
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET                              0x00000074
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB                                 0
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB                                 15
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK                                0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET                        0x00000074
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB                           16
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB                           31
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK                          0xffff0000
+
+#endif
diff --git a/hw/peach/v1/rx_ppdu_end_user_stats_ext.h b/hw/peach/v1/rx_ppdu_end_user_stats_ext.h
new file mode 100644
index 000000000000..8c41ae305749
--- /dev/null
+++ b/hw/peach/v1/rx_ppdu_end_user_stats_ext.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_PPDU_END_USER_STATS_EXT_H_
+#define _RX_PPDU_END_USER_STATS_EXT_H_
+
+#include "rx_rxpcu_classification_overview.h"
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8
+
+struct rx_ppdu_end_user_stats_ext {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t fcs_ok_bitmap_95_64                                     : 32;
+             uint32_t fcs_ok_bitmap_127_96                                    : 32;
+             uint32_t fcs_ok_bitmap_159_128                                   : 32;
+             uint32_t fcs_ok_bitmap_191_160                                   : 32;
+             uint32_t fcs_ok_bitmap_223_192                                   : 32;
+             uint32_t fcs_ok_bitmap_255_224                                   : 32;
+             uint32_t corrupted_due_to_fifo_delay                             :  1,
+                      reserved_7a                                             : 31;
+#else
+             struct   rx_rxpcu_classification_overview                          rxpcu_classification_details;
+             uint32_t fcs_ok_bitmap_95_64                                     : 32;
+             uint32_t fcs_ok_bitmap_127_96                                    : 32;
+             uint32_t fcs_ok_bitmap_159_128                                   : 32;
+             uint32_t fcs_ok_bitmap_191_160                                   : 32;
+             uint32_t fcs_ok_bitmap_223_192                                   : 32;
+             uint32_t fcs_ok_bitmap_255_224                                   : 32;
+             uint32_t reserved_7a                                             : 31,
+                      corrupted_due_to_fifo_delay                             :  1;
+#endif
+};
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET   0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB      9
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB      15
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK     0x0000fe00
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET  0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB     16
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB     31
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK    0xffff0000
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET                       0x00000004
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB                          0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB                          31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK                         0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET                      0x00000008
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB                         0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB                         31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK                        0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET                     0x0000000c
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB                        0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB                        31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK                       0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET                     0x00000010
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB                        0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB                        31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK                       0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET                     0x00000014
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB                        0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB                        31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK                       0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET                     0x00000018
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB                        0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB                        31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK                       0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET               0x0000001c
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB                  0
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB                  0
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK                 0x00000001
+
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET                               0x0000001c
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB                                  1
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB                                  31
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK                                 0xfffffffe
+
+#endif
diff --git a/hw/peach/v1/rx_ppdu_no_ack_report.h b/hw/peach/v1/rx_ppdu_no_ack_report.h
new file mode 100644
index 000000000000..c98fd8f9ac8c
--- /dev/null
+++ b/hw/peach/v1/rx_ppdu_no_ack_report.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_PPDU_NO_ACK_REPORT_H_
+#define _RX_PPDU_NO_ACK_REPORT_H_
+
+#include "no_ack_report.h"
+#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4
+
+struct rx_ppdu_no_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   no_ack_report                                             no_ack_report_details;
+#else
+             struct   no_ack_report                                             no_ack_report_details;
+#endif
+};
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET   0x00000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB      0
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB      3
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK     0x0000000f
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET       0x00000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB          4
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB          7
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK         0x000000f0
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET       0x00000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB          8
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB          15
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK         0x0000ff00
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET            0x00000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB               16
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB               31
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK              0xffff0000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET         0x00000004
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB            0
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB            23
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK           0x00ffffff
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET      0x00000004
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB         24
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB         24
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK        0x01000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET               0x00000004
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB                  29
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB                  31
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK                 0xe0000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET               0x00000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB                  24
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB                  31
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK                 0xff000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET               0x0000000c
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB                  12
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB                  31
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK                 0xfffff000
+
+#endif
diff --git a/hw/peach/v1/rx_ppdu_start.h b/hw/peach/v1/rx_ppdu_start.h
new file mode 100644
index 000000000000..174b88cda1fa
--- /dev/null
+++ b/hw/peach/v1/rx_ppdu_start.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_PPDU_START_H_
+#define _RX_PPDU_START_H_
+
+#define NUM_OF_DWORDS_RX_PPDU_START 5
+
+struct rx_ppdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_ppdu_id                                             : 16,
+                      preamble_time_to_rxframe                                :  8,
+                      reserved_0a                                             :  8;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t rxframe_assert_timestamp                                : 32;
+#else
+             uint32_t reserved_0a                                             :  8,
+                      preamble_time_to_rxframe                                :  8,
+                      phy_ppdu_id                                             : 16;
+             uint32_t sw_phy_meta_data                                        : 32;
+             uint32_t ppdu_start_timestamp_31_0                               : 32;
+             uint32_t ppdu_start_timestamp_63_32                              : 32;
+             uint32_t rxframe_assert_timestamp                                : 32;
+#endif
+};
+
+#define RX_PPDU_START_PHY_PPDU_ID_OFFSET                                            0x00000000
+#define RX_PPDU_START_PHY_PPDU_ID_LSB                                               0
+#define RX_PPDU_START_PHY_PPDU_ID_MSB                                               15
+#define RX_PPDU_START_PHY_PPDU_ID_MASK                                              0x0000ffff
+
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET                               0x00000000
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB                                  16
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB                                  23
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK                                 0x00ff0000
+
+#define RX_PPDU_START_RESERVED_0A_OFFSET                                            0x00000000
+#define RX_PPDU_START_RESERVED_0A_LSB                                               24
+#define RX_PPDU_START_RESERVED_0A_MSB                                               31
+#define RX_PPDU_START_RESERVED_0A_MASK                                              0xff000000
+
+#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET                                       0x00000004
+#define RX_PPDU_START_SW_PHY_META_DATA_LSB                                          0
+#define RX_PPDU_START_SW_PHY_META_DATA_MSB                                          31
+#define RX_PPDU_START_SW_PHY_META_DATA_MASK                                         0xffffffff
+
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET                              0x00000008
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB                                 0
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB                                 31
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK                                0xffffffff
+
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET                             0x0000000c
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB                                0
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB                                31
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK                               0xffffffff
+
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET                               0x00000010
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB                                  0
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB                                  31
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK                                 0xffffffff
+
+#endif
diff --git a/hw/peach/v1/rx_ppdu_start_user_info.h b/hw/peach/v1/rx_ppdu_start_user_info.h
new file mode 100644
index 000000000000..544532ca7734
--- /dev/null
+++ b/hw/peach/v1/rx_ppdu_start_user_info.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_PPDU_START_USER_INFO_H_
+#define _RX_PPDU_START_USER_INFO_H_
+
+#include "receive_user_info.h"
+#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8
+
+struct rx_ppdu_start_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   receive_user_info                                         receive_user_info_details;
+#else
+             struct   receive_user_info                                         receive_user_info_details;
+#endif
+};
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET        0x00000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB           0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB           15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK          0x0000ffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET          0x00000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB             16
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB             23
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK            0x00ff0000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET           0x00000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB              24
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB              27
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK             0x0f000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET               0x00000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB                  28
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB                  28
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK                 0x10000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET     0x00000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB        29
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB        31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK       0xe0000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET           0x00000004
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB              0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB              3
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK             0x0000000f
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET                0x00000004
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB                   4
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB                   5
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK                  0x00000030
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET        0x00000004
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB           7
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB           7
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK          0x00000080
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET     0x00000004
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB        8
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB        15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK       0x0000ff00
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET  0x00000004
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB     16
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB     18
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK    0x00070000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET        0x00000004
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB           19
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB           23
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK          0x00f80000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB   24
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB   31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK  0xff000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET        0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB           1
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB           7
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK          0x000000fe
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET                0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB                   8
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB                   10
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK                  0x00000700
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET      0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB         11
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB         13
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK        0x00003800
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET            0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB               14
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB               14
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK              0x00004000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET               0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB                  15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB                  15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK                 0x00008000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET       0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB          16
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB          19
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK         0x000f0000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET       0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB          20
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB          23
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK         0x00f00000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET       0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB          24
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB          27
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK         0x0f000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET       0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB          28
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB          31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK         0xf0000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB   0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB   5
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK  0x0000003f
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET        0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB           6
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB           7
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK          0x000000c0
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB   8
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB   13
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK  0x00003f00
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET        0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB           14
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB           15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK          0x0000c000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB   16
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB   21
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK  0x003f0000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET        0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB           22
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB           23
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK          0x00c00000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB   24
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB   29
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK  0x3f000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET        0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB           30
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB           31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK          0xc0000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET  0x00000010
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB     0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB     31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK    0xffffffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET  0x00000014
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB     0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB     31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK    0xffffffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET  0x00000018
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB     0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB     31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK    0xffffffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET  0x0000001c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB     0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB     31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK    0xffffffff
+
+#endif
diff --git a/hw/peach/v1/rx_preamble.h b/hw/peach/v1/rx_preamble.h
new file mode 100644
index 000000000000..75862b6e9a8c
--- /dev/null
+++ b/hw/peach/v1/rx_preamble.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_PREAMBLE_H_
+#define _RX_PREAMBLE_H_
+
+#define NUM_OF_DWORDS_RX_PREAMBLE 1
+
+struct rx_preamble {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t num_users                                               :  6,
+                      pkt_type                                                :  4,
+                      direction                                               :  1,
+                      reserved_0a                                             : 21;
+#else
+             uint32_t reserved_0a                                             : 21,
+                      direction                                               :  1,
+                      pkt_type                                                :  4,
+                      num_users                                               :  6;
+#endif
+};
+
+#define RX_PREAMBLE_NUM_USERS_OFFSET                                                0x00000000
+#define RX_PREAMBLE_NUM_USERS_LSB                                                   0
+#define RX_PREAMBLE_NUM_USERS_MSB                                                   5
+#define RX_PREAMBLE_NUM_USERS_MASK                                                  0x0000003f
+
+#define RX_PREAMBLE_PKT_TYPE_OFFSET                                                 0x00000000
+#define RX_PREAMBLE_PKT_TYPE_LSB                                                    6
+#define RX_PREAMBLE_PKT_TYPE_MSB                                                    9
+#define RX_PREAMBLE_PKT_TYPE_MASK                                                   0x000003c0
+
+#define RX_PREAMBLE_DIRECTION_OFFSET                                                0x00000000
+#define RX_PREAMBLE_DIRECTION_LSB                                                   10
+#define RX_PREAMBLE_DIRECTION_MSB                                                   10
+#define RX_PREAMBLE_DIRECTION_MASK                                                  0x00000400
+
+#define RX_PREAMBLE_RESERVED_0A_OFFSET                                              0x00000000
+#define RX_PREAMBLE_RESERVED_0A_LSB                                                 11
+#define RX_PREAMBLE_RESERVED_0A_MSB                                                 31
+#define RX_PREAMBLE_RESERVED_0A_MASK                                                0xfffff800
+
+#endif
diff --git a/hw/peach/v1/rx_reo_queue.h b/hw/peach/v1/rx_reo_queue.h
new file mode 100644
index 000000000000..be630859dfd4
--- /dev/null
+++ b/hw/peach/v1/rx_reo_queue.h
@@ -0,0 +1,514 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_REO_QUEUE_H_
+#define _RX_REO_QUEUE_H_
+
+#include "uniform_descriptor_header.h"
+#define NUM_OF_DWORDS_RX_REO_QUEUE 32
+
+struct rx_reo_queue {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_descriptor_header                                 descriptor_header;
+             uint32_t receive_queue_number                                    : 16,
+                      reserved_1b                                             : 16;
+             uint32_t vld                                                     :  1,
+                      associated_link_descriptor_counter                      :  2,
+                      disable_duplicate_detection                             :  1,
+                      soft_reorder_enable                                     :  1,
+                      ac                                                      :  2,
+                      bar                                                     :  1,
+                      rty                                                     :  1,
+                      chk_2k_mode                                             :  1,
+                      oor_mode                                                :  1,
+                      ba_window_size                                          : 10,
+                      pn_check_needed                                         :  1,
+                      pn_shall_be_even                                        :  1,
+                      pn_shall_be_uneven                                      :  1,
+                      pn_handling_enable                                      :  1,
+                      pn_size                                                 :  2,
+                      ignore_ampdu_flag                                       :  1,
+                      reserved_2b                                             :  4;
+             uint32_t svld                                                    :  1,
+                      ssn                                                     : 12,
+                      current_index                                           : 10,
+                      seq_2k_error_detected_flag                              :  1,
+                      pn_error_detected_flag                                  :  1,
+                      reserved_3a                                             :  6,
+                      pn_valid                                                :  1;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t last_rx_enqueue_timestamp                               : 32;
+             uint32_t last_rx_dequeue_timestamp                               : 32;
+             uint32_t ptr_to_next_aging_queue_31_0                            : 32;
+             uint32_t ptr_to_next_aging_queue_39_32                           :  8,
+                      reserved_11a                                            : 24;
+             uint32_t ptr_to_previous_aging_queue_31_0                        : 32;
+             uint32_t ptr_to_previous_aging_queue_39_32                       :  8,
+                      statistics_counter_index                                :  6,
+                      reserved_13a                                            : 18;
+             uint32_t rx_bitmap_31_0                                          : 32;
+             uint32_t rx_bitmap_63_32                                         : 32;
+             uint32_t rx_bitmap_95_64                                         : 32;
+             uint32_t rx_bitmap_127_96                                        : 32;
+             uint32_t rx_bitmap_159_128                                       : 32;
+             uint32_t rx_bitmap_191_160                                       : 32;
+             uint32_t rx_bitmap_223_192                                       : 32;
+             uint32_t rx_bitmap_255_224                                       : 32;
+             uint32_t rx_bitmap_287_256                                       : 32;
+             uint32_t current_mpdu_count                                      :  7,
+                      current_msdu_count                                      : 25;
+             uint32_t last_sn_reg_index                                       :  4,
+                      timeout_count                                           :  6,
+                      forward_due_to_bar_count                                :  6,
+                      duplicate_count                                         : 16;
+             uint32_t frames_in_order_count                                   : 24,
+                      bar_received_count                                      :  8;
+             uint32_t mpdu_frames_processed_count                             : 32;
+             uint32_t msdu_frames_processed_count                             : 32;
+             uint32_t total_processed_byte_count                              : 32;
+             uint32_t late_receive_mpdu_count                                 : 12,
+                      window_jump_2k                                          :  4,
+                      hole_count                                              : 16;
+             uint32_t aging_drop_mpdu_count                                   : 16,
+                      aging_drop_interval                                     :  8,
+                      reserved_30                                             :  8;
+             uint32_t reserved_31                                             : 32;
+#else
+             struct   uniform_descriptor_header                                 descriptor_header;
+             uint32_t reserved_1b                                             : 16,
+                      receive_queue_number                                    : 16;
+             uint32_t reserved_2b                                             :  4,
+                      ignore_ampdu_flag                                       :  1,
+                      pn_size                                                 :  2,
+                      pn_handling_enable                                      :  1,
+                      pn_shall_be_uneven                                      :  1,
+                      pn_shall_be_even                                        :  1,
+                      pn_check_needed                                         :  1,
+                      ba_window_size                                          : 10,
+                      oor_mode                                                :  1,
+                      chk_2k_mode                                             :  1,
+                      rty                                                     :  1,
+                      bar                                                     :  1,
+                      ac                                                      :  2,
+                      soft_reorder_enable                                     :  1,
+                      disable_duplicate_detection                             :  1,
+                      associated_link_descriptor_counter                      :  2,
+                      vld                                                     :  1;
+             uint32_t pn_valid                                                :  1,
+                      reserved_3a                                             :  6,
+                      pn_error_detected_flag                                  :  1,
+                      seq_2k_error_detected_flag                              :  1,
+                      current_index                                           : 10,
+                      ssn                                                     : 12,
+                      svld                                                    :  1;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_63_32                                                : 32;
+             uint32_t pn_95_64                                                : 32;
+             uint32_t pn_127_96                                               : 32;
+             uint32_t last_rx_enqueue_timestamp                               : 32;
+             uint32_t last_rx_dequeue_timestamp                               : 32;
+             uint32_t ptr_to_next_aging_queue_31_0                            : 32;
+             uint32_t reserved_11a                                            : 24,
+                      ptr_to_next_aging_queue_39_32                           :  8;
+             uint32_t ptr_to_previous_aging_queue_31_0                        : 32;
+             uint32_t reserved_13a                                            : 18,
+                      statistics_counter_index                                :  6,
+                      ptr_to_previous_aging_queue_39_32                       :  8;
+             uint32_t rx_bitmap_31_0                                          : 32;
+             uint32_t rx_bitmap_63_32                                         : 32;
+             uint32_t rx_bitmap_95_64                                         : 32;
+             uint32_t rx_bitmap_127_96                                        : 32;
+             uint32_t rx_bitmap_159_128                                       : 32;
+             uint32_t rx_bitmap_191_160                                       : 32;
+             uint32_t rx_bitmap_223_192                                       : 32;
+             uint32_t rx_bitmap_255_224                                       : 32;
+             uint32_t rx_bitmap_287_256                                       : 32;
+             uint32_t current_msdu_count                                      : 25,
+                      current_mpdu_count                                      :  7;
+             uint32_t duplicate_count                                         : 16,
+                      forward_due_to_bar_count                                :  6,
+                      timeout_count                                           :  6,
+                      last_sn_reg_index                                       :  4;
+             uint32_t bar_received_count                                      :  8,
+                      frames_in_order_count                                   : 24;
+             uint32_t mpdu_frames_processed_count                             : 32;
+             uint32_t msdu_frames_processed_count                             : 32;
+             uint32_t total_processed_byte_count                              : 32;
+             uint32_t hole_count                                              : 16,
+                      window_jump_2k                                          :  4,
+                      late_receive_mpdu_count                                 : 12;
+             uint32_t reserved_30                                             :  8,
+                      aging_drop_interval                                     :  8,
+                      aging_drop_mpdu_count                                   : 16;
+             uint32_t reserved_31                                             : 32;
+#endif
+};
+
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET                                 0x00000000
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB                                    0
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB                                    3
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK                                   0x0000000f
+
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                           0x00000000
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                              4
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                              7
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                             0x000000f0
+
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET                  0x00000000
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                     8
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                     27
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                    0x0fffff00
+
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                           0x00000000
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB                              28
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB                              31
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK                             0xf0000000
+
+#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET                                    0x00000004
+#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB                                       0
+#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB                                       15
+#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK                                      0x0000ffff
+
+#define RX_REO_QUEUE_RESERVED_1B_OFFSET                                             0x00000004
+#define RX_REO_QUEUE_RESERVED_1B_LSB                                                16
+#define RX_REO_QUEUE_RESERVED_1B_MSB                                                31
+#define RX_REO_QUEUE_RESERVED_1B_MASK                                               0xffff0000
+
+#define RX_REO_QUEUE_VLD_OFFSET                                                     0x00000008
+#define RX_REO_QUEUE_VLD_LSB                                                        0
+#define RX_REO_QUEUE_VLD_MSB                                                        0
+#define RX_REO_QUEUE_VLD_MASK                                                       0x00000001
+
+#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET                      0x00000008
+#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB                         1
+#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB                         2
+#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK                        0x00000006
+
+#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET                             0x00000008
+#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB                                3
+#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB                                3
+#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK                               0x00000008
+
+#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET                                     0x00000008
+#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB                                        4
+#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB                                        4
+#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK                                       0x00000010
+
+#define RX_REO_QUEUE_AC_OFFSET                                                      0x00000008
+#define RX_REO_QUEUE_AC_LSB                                                         5
+#define RX_REO_QUEUE_AC_MSB                                                         6
+#define RX_REO_QUEUE_AC_MASK                                                        0x00000060
+
+#define RX_REO_QUEUE_BAR_OFFSET                                                     0x00000008
+#define RX_REO_QUEUE_BAR_LSB                                                        7
+#define RX_REO_QUEUE_BAR_MSB                                                        7
+#define RX_REO_QUEUE_BAR_MASK                                                       0x00000080
+
+#define RX_REO_QUEUE_RTY_OFFSET                                                     0x00000008
+#define RX_REO_QUEUE_RTY_LSB                                                        8
+#define RX_REO_QUEUE_RTY_MSB                                                        8
+#define RX_REO_QUEUE_RTY_MASK                                                       0x00000100
+
+#define RX_REO_QUEUE_CHK_2K_MODE_OFFSET                                             0x00000008
+#define RX_REO_QUEUE_CHK_2K_MODE_LSB                                                9
+#define RX_REO_QUEUE_CHK_2K_MODE_MSB                                                9
+#define RX_REO_QUEUE_CHK_2K_MODE_MASK                                               0x00000200
+
+#define RX_REO_QUEUE_OOR_MODE_OFFSET                                                0x00000008
+#define RX_REO_QUEUE_OOR_MODE_LSB                                                   10
+#define RX_REO_QUEUE_OOR_MODE_MSB                                                   10
+#define RX_REO_QUEUE_OOR_MODE_MASK                                                  0x00000400
+
+#define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET                                          0x00000008
+#define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB                                             11
+#define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB                                             20
+#define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK                                            0x001ff800
+
+#define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET                                         0x00000008
+#define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB                                            21
+#define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB                                            21
+#define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK                                           0x00200000
+
+#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET                                        0x00000008
+#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB                                           22
+#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB                                           22
+#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK                                          0x00400000
+
+#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET                                      0x00000008
+#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB                                         23
+#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB                                         23
+#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK                                        0x00800000
+
+#define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET                                      0x00000008
+#define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB                                         24
+#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB                                         24
+#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK                                        0x01000000
+
+#define RX_REO_QUEUE_PN_SIZE_OFFSET                                                 0x00000008
+#define RX_REO_QUEUE_PN_SIZE_LSB                                                    25
+#define RX_REO_QUEUE_PN_SIZE_MSB                                                    26
+#define RX_REO_QUEUE_PN_SIZE_MASK                                                   0x06000000
+
+#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET                                       0x00000008
+#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB                                          27
+#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB                                          27
+#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK                                         0x08000000
+
+#define RX_REO_QUEUE_RESERVED_2B_OFFSET                                             0x00000008
+#define RX_REO_QUEUE_RESERVED_2B_LSB                                                28
+#define RX_REO_QUEUE_RESERVED_2B_MSB                                                31
+#define RX_REO_QUEUE_RESERVED_2B_MASK                                               0xf0000000
+
+#define RX_REO_QUEUE_SVLD_OFFSET                                                    0x0000000c
+#define RX_REO_QUEUE_SVLD_LSB                                                       0
+#define RX_REO_QUEUE_SVLD_MSB                                                       0
+#define RX_REO_QUEUE_SVLD_MASK                                                      0x00000001
+
+#define RX_REO_QUEUE_SSN_OFFSET                                                     0x0000000c
+#define RX_REO_QUEUE_SSN_LSB                                                        1
+#define RX_REO_QUEUE_SSN_MSB                                                        12
+#define RX_REO_QUEUE_SSN_MASK                                                       0x00001ffe
+
+#define RX_REO_QUEUE_CURRENT_INDEX_OFFSET                                           0x0000000c
+#define RX_REO_QUEUE_CURRENT_INDEX_LSB                                              13
+#define RX_REO_QUEUE_CURRENT_INDEX_MSB                                              22
+#define RX_REO_QUEUE_CURRENT_INDEX_MASK                                             0x007fe000
+
+#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET                              0x0000000c
+#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB                                 23
+#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB                                 23
+#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK                                0x00800000
+
+#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET                                  0x0000000c
+#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB                                     24
+#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB                                     24
+#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK                                    0x01000000
+
+#define RX_REO_QUEUE_RESERVED_3A_OFFSET                                             0x0000000c
+#define RX_REO_QUEUE_RESERVED_3A_LSB                                                25
+#define RX_REO_QUEUE_RESERVED_3A_MSB                                                30
+#define RX_REO_QUEUE_RESERVED_3A_MASK                                               0x7e000000
+
+#define RX_REO_QUEUE_PN_VALID_OFFSET                                                0x0000000c
+#define RX_REO_QUEUE_PN_VALID_LSB                                                   31
+#define RX_REO_QUEUE_PN_VALID_MSB                                                   31
+#define RX_REO_QUEUE_PN_VALID_MASK                                                  0x80000000
+
+#define RX_REO_QUEUE_PN_31_0_OFFSET                                                 0x00000010
+#define RX_REO_QUEUE_PN_31_0_LSB                                                    0
+#define RX_REO_QUEUE_PN_31_0_MSB                                                    31
+#define RX_REO_QUEUE_PN_31_0_MASK                                                   0xffffffff
+
+#define RX_REO_QUEUE_PN_63_32_OFFSET                                                0x00000014
+#define RX_REO_QUEUE_PN_63_32_LSB                                                   0
+#define RX_REO_QUEUE_PN_63_32_MSB                                                   31
+#define RX_REO_QUEUE_PN_63_32_MASK                                                  0xffffffff
+
+#define RX_REO_QUEUE_PN_95_64_OFFSET                                                0x00000018
+#define RX_REO_QUEUE_PN_95_64_LSB                                                   0
+#define RX_REO_QUEUE_PN_95_64_MSB                                                   31
+#define RX_REO_QUEUE_PN_95_64_MASK                                                  0xffffffff
+
+#define RX_REO_QUEUE_PN_127_96_OFFSET                                               0x0000001c
+#define RX_REO_QUEUE_PN_127_96_LSB                                                  0
+#define RX_REO_QUEUE_PN_127_96_MSB                                                  31
+#define RX_REO_QUEUE_PN_127_96_MASK                                                 0xffffffff
+
+#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET                               0x00000020
+#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB                                  0
+#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB                                  31
+#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK                                 0xffffffff
+
+#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET                               0x00000024
+#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB                                  0
+#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB                                  31
+#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK                                 0xffffffff
+
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET                            0x00000028
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB                               0
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB                               31
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK                              0xffffffff
+
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET                           0x0000002c
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB                              0
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB                              7
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK                             0x000000ff
+
+#define RX_REO_QUEUE_RESERVED_11A_OFFSET                                            0x0000002c
+#define RX_REO_QUEUE_RESERVED_11A_LSB                                               8
+#define RX_REO_QUEUE_RESERVED_11A_MSB                                               31
+#define RX_REO_QUEUE_RESERVED_11A_MASK                                              0xffffff00
+
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET                        0x00000030
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB                           0
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB                           31
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK                          0xffffffff
+
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET                       0x00000034
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB                          0
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB                          7
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK                         0x000000ff
+
+#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET                                0x00000034
+#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB                                   8
+#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB                                   13
+#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK                                  0x00003f00
+
+#define RX_REO_QUEUE_RESERVED_13A_OFFSET                                            0x00000034
+#define RX_REO_QUEUE_RESERVED_13A_LSB                                               14
+#define RX_REO_QUEUE_RESERVED_13A_MSB                                               31
+#define RX_REO_QUEUE_RESERVED_13A_MASK                                              0xffffc000
+
+#define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET                                          0x00000038
+#define RX_REO_QUEUE_RX_BITMAP_31_0_LSB                                             0
+#define RX_REO_QUEUE_RX_BITMAP_31_0_MSB                                             31
+#define RX_REO_QUEUE_RX_BITMAP_31_0_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET                                         0x0000003c
+#define RX_REO_QUEUE_RX_BITMAP_63_32_LSB                                            0
+#define RX_REO_QUEUE_RX_BITMAP_63_32_MSB                                            31
+#define RX_REO_QUEUE_RX_BITMAP_63_32_MASK                                           0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET                                         0x00000040
+#define RX_REO_QUEUE_RX_BITMAP_95_64_LSB                                            0
+#define RX_REO_QUEUE_RX_BITMAP_95_64_MSB                                            31
+#define RX_REO_QUEUE_RX_BITMAP_95_64_MASK                                           0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET                                        0x00000044
+#define RX_REO_QUEUE_RX_BITMAP_127_96_LSB                                           0
+#define RX_REO_QUEUE_RX_BITMAP_127_96_MSB                                           31
+#define RX_REO_QUEUE_RX_BITMAP_127_96_MASK                                          0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET                                       0x00000048
+#define RX_REO_QUEUE_RX_BITMAP_159_128_LSB                                          0
+#define RX_REO_QUEUE_RX_BITMAP_159_128_MSB                                          31
+#define RX_REO_QUEUE_RX_BITMAP_159_128_MASK                                         0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET                                       0x0000004c
+#define RX_REO_QUEUE_RX_BITMAP_191_160_LSB                                          0
+#define RX_REO_QUEUE_RX_BITMAP_191_160_MSB                                          31
+#define RX_REO_QUEUE_RX_BITMAP_191_160_MASK                                         0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET                                       0x00000050
+#define RX_REO_QUEUE_RX_BITMAP_223_192_LSB                                          0
+#define RX_REO_QUEUE_RX_BITMAP_223_192_MSB                                          31
+#define RX_REO_QUEUE_RX_BITMAP_223_192_MASK                                         0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET                                       0x00000054
+#define RX_REO_QUEUE_RX_BITMAP_255_224_LSB                                          0
+#define RX_REO_QUEUE_RX_BITMAP_255_224_MSB                                          31
+#define RX_REO_QUEUE_RX_BITMAP_255_224_MASK                                         0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET                                       0x00000058
+#define RX_REO_QUEUE_RX_BITMAP_287_256_LSB                                          0
+#define RX_REO_QUEUE_RX_BITMAP_287_256_MSB                                          31
+#define RX_REO_QUEUE_RX_BITMAP_287_256_MASK                                         0xffffffff
+
+#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET                                      0x0000005c
+#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB                                         0
+#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB                                         6
+#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK                                        0x0000007f
+
+#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET                                      0x0000005c
+#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB                                         7
+#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB                                         31
+#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK                                        0xffffff80
+
+#define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET                                       0x00000060
+#define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB                                          0
+#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB                                          3
+#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK                                         0x0000000f
+
+#define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET                                           0x00000060
+#define RX_REO_QUEUE_TIMEOUT_COUNT_LSB                                              4
+#define RX_REO_QUEUE_TIMEOUT_COUNT_MSB                                              9
+#define RX_REO_QUEUE_TIMEOUT_COUNT_MASK                                             0x000003f0
+
+#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET                                0x00000060
+#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB                                   10
+#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB                                   15
+#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK                                  0x0000fc00
+
+#define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET                                         0x00000060
+#define RX_REO_QUEUE_DUPLICATE_COUNT_LSB                                            16
+#define RX_REO_QUEUE_DUPLICATE_COUNT_MSB                                            31
+#define RX_REO_QUEUE_DUPLICATE_COUNT_MASK                                           0xffff0000
+
+#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET                                   0x00000064
+#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB                                      0
+#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB                                      23
+#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK                                     0x00ffffff
+
+#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET                                      0x00000064
+#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB                                         24
+#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB                                         31
+#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK                                        0xff000000
+
+#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET                             0x00000068
+#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB                                0
+#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB                                31
+#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK                               0xffffffff
+
+#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET                             0x0000006c
+#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB                                0
+#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB                                31
+#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK                               0xffffffff
+
+#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET                              0x00000070
+#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB                                 0
+#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB                                 31
+#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK                                0xffffffff
+
+#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET                                 0x00000074
+#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB                                    0
+#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB                                    11
+#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK                                   0x00000fff
+
+#define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET                                          0x00000074
+#define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB                                             12
+#define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB                                             15
+#define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK                                            0x0000f000
+
+#define RX_REO_QUEUE_HOLE_COUNT_OFFSET                                              0x00000074
+#define RX_REO_QUEUE_HOLE_COUNT_LSB                                                 16
+#define RX_REO_QUEUE_HOLE_COUNT_MSB                                                 31
+#define RX_REO_QUEUE_HOLE_COUNT_MASK                                                0xffff0000
+
+#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET                                   0x00000078
+#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB                                      0
+#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB                                      15
+#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK                                     0x0000ffff
+
+#define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET                                     0x00000078
+#define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB                                        16
+#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB                                        23
+#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK                                       0x00ff0000
+
+#define RX_REO_QUEUE_RESERVED_30_OFFSET                                             0x00000078
+#define RX_REO_QUEUE_RESERVED_30_LSB                                                24
+#define RX_REO_QUEUE_RESERVED_30_MSB                                                31
+#define RX_REO_QUEUE_RESERVED_30_MASK                                               0xff000000
+
+#define RX_REO_QUEUE_RESERVED_31_OFFSET                                             0x0000007c
+#define RX_REO_QUEUE_RESERVED_31_LSB                                                0
+#define RX_REO_QUEUE_RESERVED_31_MSB                                                31
+#define RX_REO_QUEUE_RESERVED_31_MASK                                               0xffffffff
+
+#endif
diff --git a/hw/peach/v1/rx_reo_queue_1k.h b/hw/peach/v1/rx_reo_queue_1k.h
new file mode 100644
index 000000000000..410c1d499c51
--- /dev/null
+++ b/hw/peach/v1/rx_reo_queue_1k.h
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_REO_QUEUE_1K_H_
+#define _RX_REO_QUEUE_1K_H_
+
+#include "uniform_descriptor_header.h"
+#define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32
+
+struct rx_reo_queue_1k {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_descriptor_header                                 descriptor_header;
+             uint32_t rx_bitmap_319_288                                       : 32;
+             uint32_t rx_bitmap_351_320                                       : 32;
+             uint32_t rx_bitmap_383_352                                       : 32;
+             uint32_t rx_bitmap_415_384                                       : 32;
+             uint32_t rx_bitmap_447_416                                       : 32;
+             uint32_t rx_bitmap_479_448                                       : 32;
+             uint32_t rx_bitmap_511_480                                       : 32;
+             uint32_t rx_bitmap_543_512                                       : 32;
+             uint32_t rx_bitmap_575_544                                       : 32;
+             uint32_t rx_bitmap_607_576                                       : 32;
+             uint32_t rx_bitmap_639_608                                       : 32;
+             uint32_t rx_bitmap_671_640                                       : 32;
+             uint32_t rx_bitmap_703_672                                       : 32;
+             uint32_t rx_bitmap_735_704                                       : 32;
+             uint32_t rx_bitmap_767_736                                       : 32;
+             uint32_t rx_bitmap_799_768                                       : 32;
+             uint32_t rx_bitmap_831_800                                       : 32;
+             uint32_t rx_bitmap_863_832                                       : 32;
+             uint32_t rx_bitmap_895_864                                       : 32;
+             uint32_t rx_bitmap_927_896                                       : 32;
+             uint32_t rx_bitmap_959_928                                       : 32;
+             uint32_t rx_bitmap_991_960                                       : 32;
+             uint32_t rx_bitmap_1023_992                                      : 32;
+             uint32_t reserved_24                                             : 32;
+             uint32_t reserved_25                                             : 32;
+             uint32_t reserved_26                                             : 32;
+             uint32_t reserved_27                                             : 32;
+             uint32_t reserved_28                                             : 32;
+             uint32_t reserved_29                                             : 32;
+             uint32_t reserved_30                                             : 32;
+             uint32_t reserved_31                                             : 32;
+#else
+             struct   uniform_descriptor_header                                 descriptor_header;
+             uint32_t rx_bitmap_319_288                                       : 32;
+             uint32_t rx_bitmap_351_320                                       : 32;
+             uint32_t rx_bitmap_383_352                                       : 32;
+             uint32_t rx_bitmap_415_384                                       : 32;
+             uint32_t rx_bitmap_447_416                                       : 32;
+             uint32_t rx_bitmap_479_448                                       : 32;
+             uint32_t rx_bitmap_511_480                                       : 32;
+             uint32_t rx_bitmap_543_512                                       : 32;
+             uint32_t rx_bitmap_575_544                                       : 32;
+             uint32_t rx_bitmap_607_576                                       : 32;
+             uint32_t rx_bitmap_639_608                                       : 32;
+             uint32_t rx_bitmap_671_640                                       : 32;
+             uint32_t rx_bitmap_703_672                                       : 32;
+             uint32_t rx_bitmap_735_704                                       : 32;
+             uint32_t rx_bitmap_767_736                                       : 32;
+             uint32_t rx_bitmap_799_768                                       : 32;
+             uint32_t rx_bitmap_831_800                                       : 32;
+             uint32_t rx_bitmap_863_832                                       : 32;
+             uint32_t rx_bitmap_895_864                                       : 32;
+             uint32_t rx_bitmap_927_896                                       : 32;
+             uint32_t rx_bitmap_959_928                                       : 32;
+             uint32_t rx_bitmap_991_960                                       : 32;
+             uint32_t rx_bitmap_1023_992                                      : 32;
+             uint32_t reserved_24                                             : 32;
+             uint32_t reserved_25                                             : 32;
+             uint32_t reserved_26                                             : 32;
+             uint32_t reserved_27                                             : 32;
+             uint32_t reserved_28                                             : 32;
+             uint32_t reserved_29                                             : 32;
+             uint32_t reserved_30                                             : 32;
+             uint32_t reserved_31                                             : 32;
+#endif
+};
+
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET                              0x00000000
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB                                 0
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB                                 3
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK                                0x0000000f
+
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                        0x00000000
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                           4
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                           7
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                          0x000000f0
+
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET               0x00000000
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                  8
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                  27
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                 0x0fffff00
+
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                        0x00000000
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB                           28
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB                           31
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK                          0xf0000000
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET                                    0x00000004
+#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET                                    0x00000008
+#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET                                    0x0000000c
+#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET                                    0x00000010
+#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET                                    0x00000014
+#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET                                    0x00000018
+#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET                                    0x0000001c
+#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET                                    0x00000020
+#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET                                    0x00000024
+#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET                                    0x00000028
+#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET                                    0x0000002c
+#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET                                    0x00000030
+#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET                                    0x00000034
+#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET                                    0x00000038
+#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET                                    0x0000003c
+#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET                                    0x00000040
+#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET                                    0x00000044
+#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET                                    0x00000048
+#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET                                    0x0000004c
+#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET                                    0x00000050
+#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET                                    0x00000054
+#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET                                    0x00000058
+#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB                                       0
+#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB                                       31
+#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK                                      0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET                                   0x0000005c
+#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB                                      0
+#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB                                      31
+#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK                                     0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_24_OFFSET                                          0x00000060
+#define RX_REO_QUEUE_1K_RESERVED_24_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_24_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_24_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_25_OFFSET                                          0x00000064
+#define RX_REO_QUEUE_1K_RESERVED_25_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_25_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_25_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_26_OFFSET                                          0x00000068
+#define RX_REO_QUEUE_1K_RESERVED_26_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_26_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_26_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_27_OFFSET                                          0x0000006c
+#define RX_REO_QUEUE_1K_RESERVED_27_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_27_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_27_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_28_OFFSET                                          0x00000070
+#define RX_REO_QUEUE_1K_RESERVED_28_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_28_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_28_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_29_OFFSET                                          0x00000074
+#define RX_REO_QUEUE_1K_RESERVED_29_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_29_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_29_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_30_OFFSET                                          0x00000078
+#define RX_REO_QUEUE_1K_RESERVED_30_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_30_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_30_MASK                                            0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_31_OFFSET                                          0x0000007c
+#define RX_REO_QUEUE_1K_RESERVED_31_LSB                                             0
+#define RX_REO_QUEUE_1K_RESERVED_31_MSB                                             31
+#define RX_REO_QUEUE_1K_RESERVED_31_MASK                                            0xffffffff
+
+#endif
diff --git a/hw/peach/v1/rx_reo_queue_ext.h b/hw/peach/v1/rx_reo_queue_ext.h
new file mode 100644
index 000000000000..32c25df690d3
--- /dev/null
+++ b/hw/peach/v1/rx_reo_queue_ext.h
@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_REO_QUEUE_EXT_H_
+#define _RX_REO_QUEUE_EXT_H_
+
+#include "rx_mpdu_link_ptr.h"
+#include "uniform_descriptor_header.h"
+#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32
+
+struct rx_reo_queue_ext {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   uniform_descriptor_header                                 descriptor_header;
+             uint32_t reserved_1a                                             : 32;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_0;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_1;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_2;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_3;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_4;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_5;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_6;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_7;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_8;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_9;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_10;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_11;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_12;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_13;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_14;
+#else
+             struct   uniform_descriptor_header                                 descriptor_header;
+             uint32_t reserved_1a                                             : 32;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_0;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_1;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_2;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_3;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_4;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_5;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_6;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_7;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_8;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_9;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_10;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_11;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_12;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_13;
+             struct   rx_mpdu_link_ptr                                          mpdu_link_pointer_14;
+#endif
+};
+
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET                             0x00000000
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB                                0
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB                                3
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK                               0x0000000f
+
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                       0x00000000
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                          4
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                          7
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                         0x000000f0
+
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET              0x00000000
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                 8
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                 27
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                0x0fffff00
+
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                       0x00000000
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB                          28
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB                          31
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK                         0xf0000000
+
+#define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET                                         0x00000004
+#define RX_REO_QUEUE_EXT_RESERVED_1A_LSB                                            0
+#define RX_REO_QUEUE_EXT_RESERVED_1A_MSB                                            31
+#define RX_REO_QUEUE_EXT_RESERVED_1A_MASK                                           0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#endif
diff --git a/hw/peach/v1/rx_response_required_info.h b/hw/peach/v1/rx_response_required_info.h
new file mode 100644
index 000000000000..516ea5180df1
--- /dev/null
+++ b/hw/peach/v1/rx_response_required_info.h
@@ -0,0 +1,700 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_RESPONSE_REQUIRED_INFO_H_
+#define _RX_RESPONSE_REQUIRED_INFO_H_
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 15
+
+struct rx_response_required_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_ppdu_id                                             : 16,
+                      su_or_uplink_mu_reception                               :  1,
+                      trigger_frame_received                                  :  1,
+                      __reserved_g_0012                                                  :  2,
+                      tb___reserved_g_0005_response_required                            :  2,
+                      mac_security                                            :  1,
+                      filter_pass_monitor_ovrd                                :  1,
+                      ast_search_incomplete                                   :  1,
+                      r2r_end_status_to_follow                                :  1,
+                      __reserved_g_0016_listen_cca_check_at_phy_desc                        :  1,
+                      __reserved_g_0016_listen_indication                                   :  1,
+                      three_or_more_type_subtypes                             :  1,
+                      wait_sifs_config_valid                                  :  1,
+                      wait_sifs                                               :  2;
+             uint32_t general_frame_control                                   : 16,
+                      second_frame_control                                    : 16;
+             uint32_t duration                                                : 16,
+                      pkt_type                                                :  4,
+                      dot11ax_su_extended                                     :  1,
+                      rate_mcs                                                :  4,
+                      sgi                                                     :  2,
+                      stbc                                                    :  1,
+                      ldpc                                                    :  1,
+                      ampdu                                                   :  1,
+                      vht_ack                                                 :  1,
+                      rts_ta_grp_bit                                          :  1;
+             uint32_t ctrl_frame_soliciting_resp                              :  1,
+                      ast_fail_for_dot11ax_su_ext                             :  1,
+                      service_dynamic                                         :  1,
+                      m_pkt                                                   :  1,
+                      sta_partial_aid                                         : 12,
+                      group_id                                                :  6,
+                      ctrl_resp_pwr_mgmt                                      :  1,
+                      response_indication                                     :  2,
+                      ndp_indication                                          :  1,
+                      ndp_frame_type                                          :  3,
+                      second_frame_control_valid                              :  1,
+                      ack_ba_resp_more_data                                   :  1,
+                      reserved_3a                                             :  1;
+             uint32_t ack_id                                                  : 16,
+                      ack_id_ext                                              : 10,
+                      agc_cbw                                                 :  3,
+                      service_cbw                                             :  3;
+             uint32_t response_sta_count                                      :  7,
+                      reserved                                                :  4,
+                      ht_vht_sig_cbw                                          :  3,
+                      cts_cbw                                                 :  3,
+                      response_ack_count                                      :  7,
+                      response_assoc_ack_count                                :  7,
+                      txop_duration_all_ones                                  :  1;
+             uint32_t response_ba32_count                                     :  7,
+                      response_ba64_count                                     :  7,
+                      response_ba128_count                                    :  7,
+                      response_ba256_count                                    :  7,
+                      multi_tid                                               :  1,
+                      sw_response_tlv_from_crypto                             :  1,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      emlsr_main_tlv_if                                       :  1;
+             uint32_t sw_response_frame_length                                : 16,
+                      response_ba512_count                                    :  7,
+                      response_ba1024_count                                   :  7,
+                      reserved_7a                                             :  2;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t dot11ax_received_format_indication                      :  1,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      ftm_fields_valid                                        :  1,
+                      ftm_pe_nss                                              :  3,
+                      ftm_pe_ltf_size                                         :  2,
+                      ftm_pe_content                                          :  1,
+                      ftm_chain_csd_en                                        :  1,
+                      ftm_pe_chain_csd_en                                     :  1;
+             uint32_t dot11ax_response_rate_source                            :  8,
+                      dot11ax_ext_response_rate_source                        :  8,
+                      sw_peer_id                                              : 16;
+             uint32_t dot11be_puncture_bitmap                                 : 16,
+                      dot11be_response                                        :  1,
+                      punctured_response                                      :  1,
+                      eht_duplicate_mode                                      :  2,
+                      force_extra_symbol                                      :  1,
+                      reserved_13a                                            :  5,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+             uint16_t he_a_control_response_time                              : 12,
+                      reserved_after_struct16                                 :  4;
+#else
+             uint32_t wait_sifs                                               :  2,
+                      wait_sifs_config_valid                                  :  1,
+                      three_or_more_type_subtypes                             :  1,
+                      __reserved_g_0016_listen_indication                                   :  1,
+                      __reserved_g_0016_listen_cca_check_at_phy_desc                        :  1,
+                      r2r_end_status_to_follow                                :  1,
+                      ast_search_incomplete                                   :  1,
+                      filter_pass_monitor_ovrd                                :  1,
+                      mac_security                                            :  1,
+                      tb___reserved_g_0005_response_required                            :  2,
+                      __reserved_g_0012                                                  :  2,
+                      trigger_frame_received                                  :  1,
+                      su_or_uplink_mu_reception                               :  1,
+                      phy_ppdu_id                                             : 16;
+             uint32_t second_frame_control                                    : 16,
+                      general_frame_control                                   : 16;
+             uint32_t rts_ta_grp_bit                                          :  1,
+                      vht_ack                                                 :  1,
+                      ampdu                                                   :  1,
+                      ldpc                                                    :  1,
+                      stbc                                                    :  1,
+                      sgi                                                     :  2,
+                      rate_mcs                                                :  4,
+                      dot11ax_su_extended                                     :  1,
+                      pkt_type                                                :  4,
+                      duration                                                : 16;
+             uint32_t reserved_3a                                             :  1,
+                      ack_ba_resp_more_data                                   :  1,
+                      second_frame_control_valid                              :  1,
+                      ndp_frame_type                                          :  3,
+                      ndp_indication                                          :  1,
+                      response_indication                                     :  2,
+                      ctrl_resp_pwr_mgmt                                      :  1,
+                      group_id                                                :  6,
+                      sta_partial_aid                                         : 12,
+                      m_pkt                                                   :  1,
+                      service_dynamic                                         :  1,
+                      ast_fail_for_dot11ax_su_ext                             :  1,
+                      ctrl_frame_soliciting_resp                              :  1;
+             uint32_t service_cbw                                             :  3,
+                      agc_cbw                                                 :  3,
+                      ack_id_ext                                              : 10,
+                      ack_id                                                  : 16;
+             uint32_t txop_duration_all_ones                                  :  1,
+                      response_assoc_ack_count                                :  7,
+                      response_ack_count                                      :  7,
+                      cts_cbw                                                 :  3,
+                      ht_vht_sig_cbw                                          :  3,
+                      reserved                                                :  4,
+                      response_sta_count                                      :  7;
+             uint32_t emlsr_main_tlv_if                                       :  1,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      sw_response_tlv_from_crypto                             :  1,
+                      multi_tid                                               :  1,
+                      response_ba256_count                                    :  7,
+                      response_ba128_count                                    :  7,
+                      response_ba64_count                                     :  7,
+                      response_ba32_count                                     :  7;
+             uint32_t reserved_7a                                             :  2,
+                      response_ba1024_count                                   :  7,
+                      response_ba512_count                                    :  7,
+                      sw_response_frame_length                                : 16;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t ftm_pe_chain_csd_en                                     :  1,
+                      ftm_chain_csd_en                                        :  1,
+                      ftm_pe_content                                          :  1,
+                      ftm_pe_ltf_size                                         :  2,
+                      ftm_pe_nss                                              :  3,
+                      ftm_fields_valid                                        :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_format_indication                      :  1;
+             uint32_t sw_peer_id                                              : 16,
+                      dot11ax_ext_response_rate_source                        :  8,
+                      dot11ax_response_rate_source                            :  8;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_13a                                            :  5,
+                      force_extra_symbol                                      :  1,
+                      eht_duplicate_mode                                      :  2,
+                      punctured_response                                      :  1,
+                      dot11be_response                                        :  1,
+                      dot11be_puncture_bitmap                                 : 16;
+             uint32_t reserved_after_struct16                                 :  4,
+                      he_a_control_response_time                              : 12;
+             struct   mlo_sta_id_details                                        mlo_sta_id_details_rx;
+#endif
+};
+
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET                                0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB                                   0
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB                                   15
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK                                  0x0000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET                  0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB                     16
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB                     16
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK                    0x00010000
+
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET                     0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB                        17
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB                        17
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK                       0x00020000
+
+#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET               0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB                  20
+#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB                  21
+#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK                 0x00300000
+
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET                               0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB                                  22
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB                                  22
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK                                 0x00400000
+
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET                   0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB                      23
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB                      23
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK                     0x00800000
+
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET                      0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB                         24
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB                         24
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK                        0x01000000
+
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET                   0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB                      25
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB                      25
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK                     0x02000000
+
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET                0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB                   28
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB                   28
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK                  0x10000000
+
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET                     0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB                        29
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB                        29
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK                       0x20000000
+
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET                                  0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB                                     30
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB                                     31
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK                                    0xc0000000
+
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET                      0x00000004
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB                         0
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB                         15
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK                        0x0000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET                       0x00000004
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB                          16
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB                          31
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK                         0xffff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET                                   0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB                                      0
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB                                      15
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK                                     0x0000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET                                   0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB                                      16
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB                                      19
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK                                     0x000f0000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET                        0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB                           20
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB                           20
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK                          0x00100000
+
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET                                   0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB                                      21
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB                                      24
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK                                     0x01e00000
+
+#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET                                        0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB                                           25
+#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB                                           26
+#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK                                          0x06000000
+
+#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET                                       0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB                                          27
+#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB                                          27
+#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK                                         0x08000000
+
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET                                       0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB                                          28
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB                                          28
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK                                         0x10000000
+
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET                                      0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB                                         29
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB                                         29
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK                                        0x20000000
+
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET                                    0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB                                       30
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB                                       30
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK                                      0x40000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET                             0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB                                31
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB                                31
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK                               0x80000000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET                 0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB                    0
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB                    0
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK                   0x00000001
+
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET                0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB                   1
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB                   1
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK                  0x00000002
+
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET                            0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB                               2
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB                               2
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK                              0x00000004
+
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET                                      0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB                                         3
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB                                         3
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK                                        0x00000008
+
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET                            0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB                               4
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB                               15
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK                              0x0000fff0
+
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET                                   0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB                                      16
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB                                      21
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK                                     0x003f0000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET                         0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB                            22
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB                            22
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK                           0x00400000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET                        0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB                           23
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB                           24
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK                          0x01800000
+
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET                             0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB                                25
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB                                25
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK                               0x02000000
+
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET                             0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB                                26
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB                                28
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK                               0x1c000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET                 0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB                    29
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB                    29
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK                   0x20000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_OFFSET                      0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_LSB                         30
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MSB                         30
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MASK                        0x40000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_OFFSET                                0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_LSB                                   31
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MSB                                   31
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MASK                                  0x80000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_OFFSET                                     0x00000010
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_LSB                                        0
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MSB                                        15
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MASK                                       0x0000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET                                 0x00000010
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB                                    16
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB                                    25
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK                                   0x03ff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET                                    0x00000010
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB                                       26
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB                                       28
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK                                      0x1c000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET                                0x00000010
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB                                   29
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB                                   31
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK                                  0xe0000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET                         0x00000014
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB                            0
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB                            6
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK                           0x0000007f
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET                                   0x00000014
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB                                      7
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB                                      10
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK                                     0x00000780
+
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET                             0x00000014
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB                                11
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB                                13
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK                               0x00003800
+
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET                                    0x00000014
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB                                       14
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB                                       16
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK                                      0x0001c000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET                         0x00000014
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB                            17
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB                            23
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK                           0x00fe0000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET                   0x00000014
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB                      24
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB                      30
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK                     0x7f000000
+
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET                     0x00000014
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB                        31
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB                        31
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK                       0x80000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET                        0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB                           0
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB                           6
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK                          0x0000007f
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET                        0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB                           7
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB                           13
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK                          0x00003f80
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET                       0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB                          14
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB                          20
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK                         0x001fc000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET                       0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB                          21
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB                          27
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK                         0x0fe00000
+
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET                                  0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB                                     28
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB                                     28
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK                                    0x10000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET                0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB                   29
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB                   29
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK                  0x20000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET                         0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB                            30
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB                            30
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK                           0x40000000
+
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_OFFSET                          0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_LSB                             31
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MSB                             31
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MASK                            0x80000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET                   0x0000001c
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB                      0
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB                      15
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK                     0x0000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET                       0x0000001c
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB                          16
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB                          22
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK                         0x007f0000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET                      0x0000001c
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB                         23
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB                         29
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK                        0x3f800000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET                                0x0000001c
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB                                   30
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB                                   31
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK                                  0xc0000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET                                 0x00000020
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB                                    0
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB                                    31
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK                                   0xffffffff
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET                                0x00000024
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB                                   0
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB                                   15
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK                                  0x0000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET                                 0x00000024
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB                                    16
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB                                    31
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK                                   0xffff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET                                0x00000028
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB                                   0
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB                                   31
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK                                  0xffffffff
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET         0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB            0
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB            0
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK           0x00000001
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET                0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB                   1
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB                   1
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK                  0x00000002
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET              0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB                 2
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB                 7
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK                0x000000fc
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET             0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB                8
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB                11
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK               0x00000f00
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET                   0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB                      12
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB                      13
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK                     0x00003000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET                  0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB                     14
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB                     15
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK                    0x0000c000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET                    0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB                       16
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB                       16
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK                      0x00010000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET                       0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB                          17
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB                          17
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK                         0x00020000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET        0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB           18
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB           18
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK          0x00040000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET               0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB                  19
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB                  22
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK                 0x00780000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET                           0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB                              23
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB                              23
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK                             0x00800000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET                                 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB                                    24
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB                                    26
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK                                   0x07000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET                            0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB                               27
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB                               28
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK                              0x18000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET                             0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB                                29
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB                                29
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK                               0x20000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET                           0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB                              30
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB                              30
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK                             0x40000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET                        0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB                           31
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB                           31
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK                          0x80000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET               0x00000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB                  0
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB                  7
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK                 0x000000ff
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET           0x00000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB              8
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB              15
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK             0x0000ff00
+
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET                                 0x00000030
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB                                    16
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB                                    31
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK                                   0xffff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET                    0x00000034
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB                       0
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB                       15
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK                      0x0000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET                           0x00000034
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB                              16
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB                              16
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK                             0x00010000
+
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET                         0x00000034
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB                            17
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB                            17
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK                           0x00020000
+
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET                         0x00000034
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB                            18
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB                            19
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK                           0x000c0000
+
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET                         0x00000034
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB                            20
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB                            20
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK                           0x00100000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET                               0x00000034
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB                                  21
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB                                  25
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK                                 0x03e00000
+
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET            0x00000034
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB               26
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB               31
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK              0xfc000000
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET      0x00000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB         0
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB         9
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK        0x000003ff
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET   0x00000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB      10
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB      10
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK     0x00000400
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB   11
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB   11
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK  0x00000800
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB   12
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB   12
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK  0x00001000
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET          0x00000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB             13
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB             15
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK            0x0000e000
+
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET                 0x00000038
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB                    16
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB                    27
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK                   0x0fff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET                    0x00000038
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB                       28
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB                       31
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK                      0xf0000000
+
+#endif
diff --git a/hw/peach/v1/rx_rxpcu_classification_overview.h b/hw/peach/v1/rx_rxpcu_classification_overview.h
new file mode 100644
index 000000000000..36bc52b5415c
--- /dev/null
+++ b/hw/peach/v1/rx_rxpcu_classification_overview.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+
+#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1
+
+struct rx_rxpcu_classification_overview {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t filter_pass_mpdus                                       :  1,
+                      filter_pass_mpdus_fcs_ok                                :  1,
+                      monitor_direct_mpdus                                    :  1,
+                      monitor_direct_mpdus_fcs_ok                             :  1,
+                      monitor_other_mpdus                                     :  1,
+                      monitor_other_mpdus_fcs_ok                              :  1,
+                      phyrx_abort_received                                    :  1,
+                      filter_pass_monitor_ovrd_mpdus                          :  1,
+                      filter_pass_monitor_ovrd_mpdus_fcs_ok                   :  1,
+                      reserved_0                                              :  7,
+                      phy_ppdu_id                                             : 16;
+#else
+             uint32_t phy_ppdu_id                                             : 16,
+                      reserved_0                                              :  7,
+                      filter_pass_monitor_ovrd_mpdus_fcs_ok                   :  1,
+                      filter_pass_monitor_ovrd_mpdus                          :  1,
+                      phyrx_abort_received                                    :  1,
+                      monitor_other_mpdus_fcs_ok                              :  1,
+                      monitor_other_mpdus                                     :  1,
+                      monitor_direct_mpdus_fcs_ok                             :  1,
+                      monitor_direct_mpdus                                    :  1,
+                      filter_pass_mpdus_fcs_ok                                :  1,
+                      filter_pass_mpdus                                       :  1;
+#endif
+};
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET                   0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB                      0
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB                      0
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK                     0x00000001
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET            0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB               1
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB               1
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK              0x00000002
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET                0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB                   2
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB                   2
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK                  0x00000004
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET         0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB            3
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB            3
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK           0x00000008
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET                 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB                    4
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB                    4
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK                   0x00000010
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET          0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB             5
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB             5
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK            0x00000020
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET                0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB                   6
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB                   6
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK                  0x00000040
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET      0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB         7
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB         7
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK        0x00000080
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB  8
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB  8
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET                          0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB                             9
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB                             15
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK                            0x0000fe00
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET                         0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB                            16
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB                            31
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK                           0xffff0000
+
+#endif
diff --git a/hw/peach/v1/rx_start_param.h b/hw/peach/v1/rx_start_param.h
new file mode 100644
index 000000000000..b10ffb979b3a
--- /dev/null
+++ b/hw/peach/v1/rx_start_param.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_START_PARAM_H_
+#define _RX_START_PARAM_H_
+
+#define NUM_OF_DWORDS_RX_START_PARAM 1
+
+struct rx_start_param {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t pkt_type                                                :  4,
+                      reserved_0a                                             : 12,
+                      remaining_rx_time                                       : 16;
+#else
+             uint32_t remaining_rx_time                                       : 16,
+                      reserved_0a                                             : 12,
+                      pkt_type                                                :  4;
+#endif
+};
+
+#define RX_START_PARAM_PKT_TYPE_OFFSET                                              0x00000000
+#define RX_START_PARAM_PKT_TYPE_LSB                                                 0
+#define RX_START_PARAM_PKT_TYPE_MSB                                                 3
+#define RX_START_PARAM_PKT_TYPE_MASK                                                0x0000000f
+
+#define RX_START_PARAM_RESERVED_0A_OFFSET                                           0x00000000
+#define RX_START_PARAM_RESERVED_0A_LSB                                              4
+#define RX_START_PARAM_RESERVED_0A_MSB                                              15
+#define RX_START_PARAM_RESERVED_0A_MASK                                             0x0000fff0
+
+#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET                                     0x00000000
+#define RX_START_PARAM_REMAINING_RX_TIME_LSB                                        16
+#define RX_START_PARAM_REMAINING_RX_TIME_MSB                                        31
+#define RX_START_PARAM_REMAINING_RX_TIME_MASK                                       0xffff0000
+
+#endif
diff --git a/hw/peach/v1/rx_timing_info.h b/hw/peach/v1/rx_timing_info.h
new file mode 100644
index 000000000000..50c0a41e408c
--- /dev/null
+++ b/hw/peach/v1/rx_timing_info.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_TIMING_INFO_H_
+#define _RX_TIMING_INFO_H_
+
+#define NUM_OF_DWORDS_RX_TIMING_INFO 5
+
+struct rx_timing_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_timestamp_1_lower_32                                : 32;
+             uint32_t phy_timestamp_1_upper_32                                : 32;
+             uint32_t phy_timestamp_2_lower_32                                : 32;
+             uint32_t phy_timestamp_2_upper_32                                : 32;
+             uint32_t residual_phase_offset                                   : 12,
+                      reserved                                                : 20;
+#else
+             uint32_t phy_timestamp_1_lower_32                                : 32;
+             uint32_t phy_timestamp_1_upper_32                                : 32;
+             uint32_t phy_timestamp_2_lower_32                                : 32;
+             uint32_t phy_timestamp_2_upper_32                                : 32;
+             uint32_t reserved                                                : 20,
+                      residual_phase_offset                                   : 12;
+#endif
+};
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET                              0x00000000
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET                              0x00000004
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET                              0x00000008
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET                              0x0000000c
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB                                 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB                                 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK                                0xffffffff
+
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_OFFSET                                 0x00000010
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_LSB                                    0
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MSB                                    11
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MASK                                   0x00000fff
+
+#define RX_TIMING_INFO_RESERVED_OFFSET                                              0x00000010
+#define RX_TIMING_INFO_RESERVED_LSB                                                 12
+#define RX_TIMING_INFO_RESERVED_MSB                                                 31
+#define RX_TIMING_INFO_RESERVED_MASK                                                0xfffff000
+
+#endif
diff --git a/hw/peach/v1/rx_trig_info.h b/hw/peach/v1/rx_trig_info.h
new file mode 100644
index 000000000000..d13b2bed819b
--- /dev/null
+++ b/hw/peach/v1/rx_trig_info.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_TRIG_INFO_H_
+#define _RX_TRIG_INFO_H_
+
+#define NUM_OF_DWORDS_RX_TRIG_INFO 2
+
+struct rx_trig_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rx_trigger_frame_type                                   :  2,
+                      trigger_resp_type                                       :  3,
+                      reserved_0                                              : 27;
+             uint32_t ppdu_duration                                           : 16,
+                      unique_destination_id                                   : 16;
+#else
+             uint32_t reserved_0                                              : 27,
+                      trigger_resp_type                                       :  3,
+                      rx_trigger_frame_type                                   :  2;
+             uint32_t unique_destination_id                                   : 16,
+                      ppdu_duration                                           : 16;
+#endif
+};
+
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET                                   0x00000000
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB                                      0
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB                                      1
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK                                     0x00000003
+
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET                                       0x00000000
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB                                          2
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB                                          4
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK                                         0x0000001c
+
+#define RX_TRIG_INFO_RESERVED_0_OFFSET                                              0x00000000
+#define RX_TRIG_INFO_RESERVED_0_LSB                                                 5
+#define RX_TRIG_INFO_RESERVED_0_MSB                                                 31
+#define RX_TRIG_INFO_RESERVED_0_MASK                                                0xffffffe0
+
+#define RX_TRIG_INFO_PPDU_DURATION_OFFSET                                           0x00000004
+#define RX_TRIG_INFO_PPDU_DURATION_LSB                                              0
+#define RX_TRIG_INFO_PPDU_DURATION_MSB                                              15
+#define RX_TRIG_INFO_PPDU_DURATION_MASK                                             0x0000ffff
+
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET                                   0x00000004
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB                                      16
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB                                      31
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK                                     0xffff0000
+
+#endif
diff --git a/hw/peach/v1/rxpcu_early_rx_indication.h b/hw/peach/v1/rxpcu_early_rx_indication.h
new file mode 100644
index 000000000000..92fcdb29560f
--- /dev/null
+++ b/hw/peach/v1/rxpcu_early_rx_indication.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RXPCU_EARLY_RX_INDICATION_H_
+#define _RXPCU_EARLY_RX_INDICATION_H_
+
+#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 1
+
+struct rxpcu_early_rx_indication {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t pkt_type                                                :  4,
+                      dot11ax_su_extended                                     :  1,
+                      rate_mcs                                                :  4,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      reserved_0a                                             : 19;
+#else
+             uint32_t reserved_0a                                             : 19,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      rate_mcs                                                :  4,
+                      dot11ax_su_extended                                     :  1,
+                      pkt_type                                                :  4;
+#endif
+};
+
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET                                   0x00000000
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB                                      0
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB                                      3
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK                                     0x0000000f
+
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET                        0x00000000
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB                           4
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB                           4
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK                          0x00000010
+
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET                                   0x00000000
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB                                      5
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB                                      8
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK                                     0x000001e0
+
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET               0x00000000
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB                  9
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB                  12
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK                 0x00001e00
+
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET                                0x00000000
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB                                   13
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB                                   31
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK                                  0xffffe000
+
+#endif
diff --git a/hw/peach/v1/rxpcu_ppdu_end_info.h b/hw/peach/v1/rxpcu_ppdu_end_info.h
new file mode 100644
index 000000000000..3248374744f9
--- /dev/null
+++ b/hw/peach/v1/rxpcu_ppdu_end_info.h
@@ -0,0 +1,861 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RXPCU_PPDU_END_INFO_H_
+#define _RXPCU_PPDU_END_INFO_H_
+
+#include "phyrx_abort_request_info.h"
+#include "macrx_abort_request_info.h"
+#include "rxpcu_ppdu_end_layout_info.h"
+#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 31
+
+struct rxpcu_ppdu_end_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t wb_timestamp_lower_32                                   : 32;
+             uint32_t wb_timestamp_upper_32                                   : 32;
+             uint32_t rx_antenna                                              : 24,
+                      tx_ht_vht_ack                                           :  1,
+                      unsupported_mu_nc                                       :  1,
+                      otp_txbf_disable                                        :  1,
+                      previous_tlv_corrupted                                  :  1,
+                      phyrx_abort_request_info_valid                          :  1,
+                      macrx_abort_request_info_valid                          :  1,
+                      reserved                                                :  2;
+             uint32_t coex_bt_tx_from_start_of_rx                             :  1,
+                      coex_bt_tx_after_start_of_rx                            :  1,
+                      coex_wan_tx_from_start_of_rx                            :  1,
+                      coex_wan_tx_after_start_of_rx                           :  1,
+                      coex_wlan_tx_from_start_of_rx                           :  1,
+                      coex_wlan_tx_after_start_of_rx                          :  1,
+                      mpdu_delimiter_errors_seen                              :  1,
+                      __reserved_g_0012                                                  :  2,
+                      dialog_token                                            :  8,
+                      follow_up_dialog_token                                  :  8,
+                      bb_captured_channel                                     :  1,
+                      bb_captured_reason                                      :  3,
+                      bb_captured_timeout                                     :  1,
+                      coex_uwb_tx_after_start_of_rx                           :  1,
+                      coex_uwb_tx_from_start_of_rx                            :  1;
+             uint32_t before_mpdu_count_passing_fcs                           : 10,
+                      before_mpdu_count_failing_fcs                           : 10,
+                      after_mpdu_count_passing_fcs                            : 10,
+                      reserved_4                                              :  2;
+             uint32_t after_mpdu_count_failing_fcs                            : 10,
+                      reserved_5                                              : 22;
+             uint32_t phy_timestamp_tx_lower_32                               : 32;
+             uint32_t phy_timestamp_tx_upper_32                               : 32;
+             uint32_t bb_length                                               : 16,
+                      bb_data                                                 :  1,
+                      reserved_8                                              :  3,
+                      first_bt_broadcast_status_details                       : 12;
+             uint32_t rx_ppdu_duration                                        : 24,
+                      reserved_9                                              :  8;
+             uint32_t ast_index                                               : 16,
+                      ast_index_valid                                         :  1,
+                      reserved_10                                             :  3,
+                      second_bt_broadcast_status_details                      : 12;
+             struct   phyrx_abort_request_info                                  phyrx_abort_request_info_details;
+             struct   macrx_abort_request_info                                  macrx_abort_request_info_details;
+             uint16_t pre_bt_broadcast_status_details                         : 12,
+                      reserved_12a                                            :  4;
+             uint32_t non_qos_sn_info_valid                                   :  1,
+                      rts_or_trig_protected_ppdu                              :  1,
+                      rts_or_trig_prot_type                                   :  2,
+                      reserved_13a                                            :  2,
+                      non_qos_sn_highest                                      : 12,
+                      non_qos_sn_highest_retry_setting                        :  1,
+                      non_qos_sn_lowest                                       : 12,
+                      non_qos_sn_lowest_retry_setting                         :  1;
+             uint32_t qos_sn_1_info_valid                                     :  1,
+                      reserved_14a                                            :  1,
+                      qos_sn_1_tid                                            :  4,
+                      qos_sn_1_highest                                        : 12,
+                      qos_sn_1_highest_retry_setting                          :  1,
+                      qos_sn_1_lowest                                         : 12,
+                      qos_sn_1_lowest_retry_setting                           :  1;
+             uint32_t qos_sn_2_info_valid                                     :  1,
+                      reserved_15a                                            :  1,
+                      qos_sn_2_tid                                            :  4,
+                      qos_sn_2_highest                                        : 12,
+                      qos_sn_2_highest_retry_setting                          :  1,
+                      qos_sn_2_lowest                                         : 12,
+                      qos_sn_2_lowest_retry_setting                           :  1;
+             struct   rxpcu_ppdu_end_layout_info                                rxpcu_ppdu_end_layout_details;
+             uint32_t corrupted_due_to_fifo_delay                             :  1,
+                      qos_sn_1_more_frag_state                                :  1,
+                      qos_sn_1_frag_num_state                                 :  4,
+                      qos_sn_2_more_frag_state                                :  1,
+                      qos_sn_2_frag_num_state                                 :  4,
+                      rts_or_trig_prot_non_11a                                :  1,
+                      rts_or_trig_prot_rate_mcs                               :  4,
+                      rts_or_trig_prot_peer_addr_15_0                         : 16;
+             uint32_t rts_or_trig_prot_peer_addr_47_16                        : 32;
+             uint32_t rts_or_trig_rx_count                                    : 32;
+             uint32_t cts_or_null_tx_count                                    : 32;
+             uint32_t rx_ppdu_end_marker                                      : 32;
+#else
+             uint32_t wb_timestamp_lower_32                                   : 32;
+             uint32_t wb_timestamp_upper_32                                   : 32;
+             uint32_t reserved                                                :  2,
+                      macrx_abort_request_info_valid                          :  1,
+                      phyrx_abort_request_info_valid                          :  1,
+                      previous_tlv_corrupted                                  :  1,
+                      otp_txbf_disable                                        :  1,
+                      unsupported_mu_nc                                       :  1,
+                      tx_ht_vht_ack                                           :  1,
+                      rx_antenna                                              : 24;
+             uint32_t coex_uwb_tx_from_start_of_rx                            :  1,
+                      coex_uwb_tx_after_start_of_rx                           :  1,
+                      bb_captured_timeout                                     :  1,
+                      bb_captured_reason                                      :  3,
+                      bb_captured_channel                                     :  1,
+                      follow_up_dialog_token                                  :  8,
+                      dialog_token                                            :  8,
+                      __reserved_g_0012                                                  :  2,
+                      mpdu_delimiter_errors_seen                              :  1,
+                      coex_wlan_tx_after_start_of_rx                          :  1,
+                      coex_wlan_tx_from_start_of_rx                           :  1,
+                      coex_wan_tx_after_start_of_rx                           :  1,
+                      coex_wan_tx_from_start_of_rx                            :  1,
+                      coex_bt_tx_after_start_of_rx                            :  1,
+                      coex_bt_tx_from_start_of_rx                             :  1;
+             uint32_t reserved_4                                              :  2,
+                      after_mpdu_count_passing_fcs                            : 10,
+                      before_mpdu_count_failing_fcs                           : 10,
+                      before_mpdu_count_passing_fcs                           : 10;
+             uint32_t reserved_5                                              : 22,
+                      after_mpdu_count_failing_fcs                            : 10;
+             uint32_t phy_timestamp_tx_lower_32                               : 32;
+             uint32_t phy_timestamp_tx_upper_32                               : 32;
+             uint32_t first_bt_broadcast_status_details                       : 12,
+                      reserved_8                                              :  3,
+                      bb_data                                                 :  1,
+                      bb_length                                               : 16;
+             uint32_t reserved_9                                              :  8,
+                      rx_ppdu_duration                                        : 24;
+             uint32_t second_bt_broadcast_status_details                      : 12,
+                      reserved_10                                             :  3,
+                      ast_index_valid                                         :  1,
+                      ast_index                                               : 16;
+             struct   phyrx_abort_request_info                                  phyrx_abort_request_info_details;
+             uint32_t reserved_12a                                            :  4,
+                      pre_bt_broadcast_status_details                         : 12;
+             struct   macrx_abort_request_info                                  macrx_abort_request_info_details;
+             uint32_t non_qos_sn_lowest_retry_setting                         :  1,
+                      non_qos_sn_lowest                                       : 12,
+                      non_qos_sn_highest_retry_setting                        :  1,
+                      non_qos_sn_highest                                      : 12,
+                      reserved_13a                                            :  2,
+                      rts_or_trig_prot_type                                   :  2,
+                      rts_or_trig_protected_ppdu                              :  1,
+                      non_qos_sn_info_valid                                   :  1;
+             uint32_t qos_sn_1_lowest_retry_setting                           :  1,
+                      qos_sn_1_lowest                                         : 12,
+                      qos_sn_1_highest_retry_setting                          :  1,
+                      qos_sn_1_highest                                        : 12,
+                      qos_sn_1_tid                                            :  4,
+                      reserved_14a                                            :  1,
+                      qos_sn_1_info_valid                                     :  1;
+             uint32_t qos_sn_2_lowest_retry_setting                           :  1,
+                      qos_sn_2_lowest                                         : 12,
+                      qos_sn_2_highest_retry_setting                          :  1,
+                      qos_sn_2_highest                                        : 12,
+                      qos_sn_2_tid                                            :  4,
+                      reserved_15a                                            :  1,
+                      qos_sn_2_info_valid                                     :  1;
+             struct   rxpcu_ppdu_end_layout_info                                rxpcu_ppdu_end_layout_details;
+             uint32_t rts_or_trig_prot_peer_addr_15_0                         : 16,
+                      rts_or_trig_prot_rate_mcs                               :  4,
+                      rts_or_trig_prot_non_11a                                :  1,
+                      qos_sn_2_frag_num_state                                 :  4,
+                      qos_sn_2_more_frag_state                                :  1,
+                      qos_sn_1_frag_num_state                                 :  4,
+                      qos_sn_1_more_frag_state                                :  1,
+                      corrupted_due_to_fifo_delay                             :  1;
+             uint32_t rts_or_trig_prot_peer_addr_47_16                        : 32;
+             uint32_t rts_or_trig_rx_count                                    : 32;
+             uint32_t cts_or_null_tx_count                                    : 32;
+             uint32_t rx_ppdu_end_marker                                      : 32;
+#endif
+};
+
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET                            0x00000000
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB                               0
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB                               31
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK                              0xffffffff
+
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET                            0x00000004
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB                               0
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB                               31
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK                              0xffffffff
+
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET                                       0x00000008
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB                                          0
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB                                          23
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK                                         0x00ffffff
+
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET                                    0x00000008
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB                                       24
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB                                       24
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK                                      0x01000000
+
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET                                0x00000008
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB                                   25
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB                                   25
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK                                  0x02000000
+
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET                                 0x00000008
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB                                    26
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB                                    26
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK                                   0x04000000
+
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET                           0x00000008
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB                              27
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB                              27
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK                             0x08000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET                   0x00000008
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB                      28
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB                      28
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK                     0x10000000
+
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET                   0x00000008
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB                      29
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB                      29
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK                     0x20000000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_OFFSET                                         0x00000008
+#define RXPCU_PPDU_END_INFO_RESERVED_LSB                                            30
+#define RXPCU_PPDU_END_INFO_RESERVED_MSB                                            31
+#define RXPCU_PPDU_END_INFO_RESERVED_MASK                                           0xc0000000
+
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET                      0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB                         0
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB                         0
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK                        0x00000001
+
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET                     0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB                        1
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB                        1
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK                       0x00000002
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET                     0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB                        2
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB                        2
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK                       0x00000004
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET                    0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB                       3
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB                       3
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK                      0x00000008
+
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET                    0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB                       4
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB                       4
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK                      0x00000010
+
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET                   0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB                      5
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB                      5
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK                     0x00000020
+
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET                       0x0000000c
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB                          6
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB                          6
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK                         0x00000040
+
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET                                     0x0000000c
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB                                        9
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB                                        16
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK                                       0x0001fe00
+
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET                           0x0000000c
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB                              17
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB                              24
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK                             0x01fe0000
+
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET                              0x0000000c
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB                                 25
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB                                 25
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK                                0x02000000
+
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET                               0x0000000c
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB                                  26
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB                                  28
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK                                 0x1c000000
+
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET                              0x0000000c
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB                                 29
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB                                 29
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK                                0x20000000
+
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_OFFSET                    0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_LSB                       30
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_MSB                       30
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_MASK                      0x40000000
+
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_OFFSET                     0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_LSB                        31
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_MSB                        31
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_MASK                       0x80000000
+
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET                    0x00000010
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB                       0
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB                       9
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK                      0x000003ff
+
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET                    0x00000010
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB                       10
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB                       19
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK                      0x000ffc00
+
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET                     0x00000010
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB                        20
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB                        29
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK                       0x3ff00000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET                                       0x00000010
+#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB                                          30
+#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB                                          31
+#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK                                         0xc0000000
+
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET                     0x00000014
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB                        0
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB                        9
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK                       0x000003ff
+
+#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET                                       0x00000014
+#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB                                          10
+#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB                                          31
+#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK                                         0xfffffc00
+
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET                        0x00000018
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB                           0
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB                           31
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK                          0xffffffff
+
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET                        0x0000001c
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB                           0
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB                           31
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK                          0xffffffff
+
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET                                        0x00000020
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB                                           0
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB                                           15
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK                                          0x0000ffff
+
+#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET                                          0x00000020
+#define RXPCU_PPDU_END_INFO_BB_DATA_LSB                                             16
+#define RXPCU_PPDU_END_INFO_BB_DATA_MSB                                             16
+#define RXPCU_PPDU_END_INFO_BB_DATA_MASK                                            0x00010000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET                                       0x00000020
+#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB                                          17
+#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB                                          19
+#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK                                         0x000e0000
+
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET                0x00000020
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB                   20
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB                   31
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK                  0xfff00000
+
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET                                 0x00000024
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB                                    0
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB                                    23
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK                                   0x00ffffff
+
+#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET                                       0x00000024
+#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB                                          24
+#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB                                          31
+#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK                                         0xff000000
+
+#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET                                        0x00000028
+#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB                                           0
+#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB                                           15
+#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK                                          0x0000ffff
+
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET                                  0x00000028
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB                                     16
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB                                     16
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK                                    0x00010000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET                                      0x00000028
+#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB                                         17
+#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB                                         19
+#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK                                        0x000e0000
+
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET               0x00000028
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB                  20
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB                  31
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK                 0xfff00000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 7
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 8
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 9
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_LSB 10
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MSB 10
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MASK 0x00000400
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_LSB  11
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MSB  11
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MASK 0x00000800
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_LSB 12
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MSB 12
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MASK 0x00001000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_LSB   13
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MSB   13
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MASK  0x00002000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_LSB    14
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MSB    14
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MASK   0x00004000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET      0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB         15
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB         15
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK        0x00008000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB   16
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB   31
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK  0xffff0000
+
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff
+
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET      0x00000030
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB         8
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB         15
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK        0x0000ff00
+
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET                  0x00000030
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB                     16
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB                     27
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK                    0x0fff0000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET                                     0x00000030
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB                                        28
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB                                        31
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK                                       0xf0000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET                            0x00000034
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB                               0
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB                               0
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK                              0x00000001
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_OFFSET                       0x00000034
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_LSB                          1
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MSB                          1
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MASK                         0x00000002
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_OFFSET                            0x00000034
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_LSB                               2
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MSB                               3
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MASK                              0x0000000c
+
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET                                     0x00000034
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB                                        4
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB                                        5
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK                                       0x00000030
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET                               0x00000034
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB                                  6
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB                                  17
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK                                 0x0003ffc0
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET                 0x00000034
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB                    18
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB                    18
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK                   0x00040000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET                                0x00000034
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB                                   19
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB                                   30
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK                                  0x7ff80000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET                  0x00000034
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB                     31
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB                     31
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK                    0x80000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET                              0x00000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB                                 0
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB                                 0
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK                                0x00000001
+
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET                                     0x00000038
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB                                        1
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB                                        1
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK                                       0x00000002
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET                                     0x00000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB                                        2
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB                                        5
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK                                       0x0000003c
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET                                 0x00000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB                                    6
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB                                    17
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK                                   0x0003ffc0
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET                   0x00000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB                      18
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB                      18
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK                     0x00040000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET                                  0x00000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB                                     19
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB                                     30
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK                                    0x7ff80000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET                    0x00000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB                       31
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB                       31
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK                      0x80000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET                              0x0000003c
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB                                 0
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB                                 0
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK                                0x00000001
+
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET                                     0x0000003c
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB                                        1
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB                                        1
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK                                       0x00000002
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET                                     0x0000003c
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB                                        2
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB                                        5
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK                                       0x0000003c
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET                                 0x0000003c
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB                                    6
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB                                    17
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK                                   0x0003ffc0
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET                   0x0000003c
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB                      18
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB                      18
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK                     0x00040000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET                                  0x0000003c
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB                                     19
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB                                     30
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK                                    0x7ff80000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET                    0x0000003c
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB                       31
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB                       31
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK                      0x80000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x00000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB    0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB    1
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK   0x00000003
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET     0x00000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB        2
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB        7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK       0x000000fc
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET     0x00000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB        8
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB        13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK       0x00003f00
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET      0x00000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB         14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB         19
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK        0x000fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET   0x00000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB      20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB      25
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK     0x03f00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x00000044
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB    0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB    5
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK   0x0000003f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000044
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 11
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000044
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 12
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 17
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x00000044
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB  18
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB  23
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET     0x00000044
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB        24
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB        30
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK       0x7f000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET        0x00000044
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK          0x80000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET        0x00000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB           28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK          0xf0000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000004c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000004c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000004c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000004c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 21
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 27
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET        0x0000004c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB           28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK          0xf0000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB   0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB   6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK  0x0000007f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB   7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB   13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK  0x00003f80
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET        0x00000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB           29
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK          0xe0000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x00000054
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000054
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000054
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000054
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000054
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET        0x00000054
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB           25
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK          0xfe000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET   0x00000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB      0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB      7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK     0x000000ff
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x00000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB  16
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB  23
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x00ff0000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET    0x00000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB       24
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB       31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK      0xff000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET     0x0000005c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB        8
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB        15
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK       0x0000ff00
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000005c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 16
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 23
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET        0x0000005c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB           24
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK          0xff000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET        0x00000060
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB           0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK          0xffffffff
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET        0x00000064
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB           0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB           31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK          0xffffffff
+
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET                      0x00000068
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB                         0
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB                         0
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK                        0x00000001
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET                         0x00000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB                            1
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB                            1
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK                           0x00000002
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET                          0x00000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB                             2
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB                             5
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK                            0x0000003c
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET                         0x00000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB                            6
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB                            6
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK                           0x00000040
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET                          0x00000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB                             7
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB                             10
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK                            0x00000780
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_OFFSET                         0x00000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_LSB                            11
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MSB                            11
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MASK                           0x00000800
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_OFFSET                        0x00000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_LSB                           12
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MSB                           15
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MASK                          0x0000f000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_OFFSET                  0x00000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_LSB                     16
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MSB                     31
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MASK                    0xffff0000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_OFFSET                 0x0000006c
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_LSB                    0
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MSB                    31
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MASK                   0xffffffff
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_OFFSET                             0x00000070
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_LSB                                0
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MSB                                31
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MASK                               0xffffffff
+
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_OFFSET                             0x00000074
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_LSB                                0
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MSB                                31
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MASK                               0xffffffff
+
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET                               0x00000078
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB                                  0
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB                                  31
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK                                 0xffffffff
+
+#endif
diff --git a/hw/peach/v1/rxpcu_ppdu_end_layout_info.h b/hw/peach/v1/rxpcu_ppdu_end_layout_info.h
new file mode 100644
index 000000000000..9f8f00dd9d5b
--- /dev/null
+++ b/hw/peach/v1/rxpcu_ppdu_end_layout_info.h
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_
+#define _RXPCU_PPDU_END_LAYOUT_INFO_H_
+
+#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10
+
+struct rxpcu_ppdu_end_layout_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t rssi_legacy_offset                                      :  2,
+                      l_sig_a_offset                                          :  6,
+                      l_sig_b_offset                                          :  6,
+                      ht_sig_offset                                           :  6,
+                      vht_sig_a_offset                                        :  6,
+                      repeat_l_sig_a_offset                                   :  6;
+             uint32_t he_sig_a_su_offset                                      :  6,
+                      he_sig_a_mu_dl_offset                                   :  6,
+                      he_sig_a_mu_ul_offset                                   :  6,
+                      generic_u_sig_offset                                    :  6,
+                      rssi_ht_offset                                          :  7,
+                      reserved_1a                                             :  1;
+             uint32_t vht_sig_b_su20_offset                                   :  7,
+                      vht_sig_b_su40_offset                                   :  7,
+                      vht_sig_b_su80_offset                                   :  7,
+                      vht_sig_b_su160_offset                                  :  7,
+                      reserved_2a                                             :  4;
+             uint32_t vht_sig_b_mu20_offset                                   :  7,
+                      vht_sig_b_mu40_offset                                   :  7,
+                      vht_sig_b_mu80_offset                                   :  7,
+                      vht_sig_b_mu160_offset                                  :  7,
+                      reserved_3a                                             :  4;
+             uint32_t he_sig_b1_mu_offset                                     :  7,
+                      he_sig_b2_mu_offset                                     :  7,
+                      he_sig_b2_ofdma_offset                                  :  7,
+                      first_generic_eht_sig_offset                            :  7,
+                      multiple_generic_eht_sig_included                       :  1,
+                      reserved_4a                                             :  3;
+             uint32_t common_user_info_offset                                 :  7,
+                      first_debug_info_offset                                 :  8,
+                      multiple_debug_info_included                            :  1,
+                      first_other_receive_info_offset                         :  8,
+                      multiple_other_receive_info_included                    :  1,
+                      reserved_5a                                             :  7;
+             uint32_t data_done_offset                                        :  8,
+                      generated_cbf_details_offset                            :  8,
+                      pkt_end_part1_offset                                    :  8,
+                      location_offset                                         :  8;
+             uint32_t __reserved_g_0011                                       :  8,
+                      pkt_end_offset                                          :  8,
+                      abort_request_ack_offset                                :  8,
+                      reserved_7a                                             :  8;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+#else
+             uint32_t repeat_l_sig_a_offset                                   :  6,
+                      vht_sig_a_offset                                        :  6,
+                      ht_sig_offset                                           :  6,
+                      l_sig_b_offset                                          :  6,
+                      l_sig_a_offset                                          :  6,
+                      rssi_legacy_offset                                      :  2;
+             uint32_t reserved_1a                                             :  1,
+                      rssi_ht_offset                                          :  7,
+                      generic_u_sig_offset                                    :  6,
+                      he_sig_a_mu_ul_offset                                   :  6,
+                      he_sig_a_mu_dl_offset                                   :  6,
+                      he_sig_a_su_offset                                      :  6;
+             uint32_t reserved_2a                                             :  4,
+                      vht_sig_b_su160_offset                                  :  7,
+                      vht_sig_b_su80_offset                                   :  7,
+                      vht_sig_b_su40_offset                                   :  7,
+                      vht_sig_b_su20_offset                                   :  7;
+             uint32_t reserved_3a                                             :  4,
+                      vht_sig_b_mu160_offset                                  :  7,
+                      vht_sig_b_mu80_offset                                   :  7,
+                      vht_sig_b_mu40_offset                                   :  7,
+                      vht_sig_b_mu20_offset                                   :  7;
+             uint32_t reserved_4a                                             :  3,
+                      multiple_generic_eht_sig_included                       :  1,
+                      first_generic_eht_sig_offset                            :  7,
+                      he_sig_b2_ofdma_offset                                  :  7,
+                      he_sig_b2_mu_offset                                     :  7,
+                      he_sig_b1_mu_offset                                     :  7;
+             uint32_t reserved_5a                                             :  7,
+                      multiple_other_receive_info_included                    :  1,
+                      first_other_receive_info_offset                         :  8,
+                      multiple_debug_info_included                            :  1,
+                      first_debug_info_offset                                 :  8,
+                      common_user_info_offset                                 :  7;
+             uint32_t location_offset                                         :  8,
+                      pkt_end_part1_offset                                    :  8,
+                      generated_cbf_details_offset                            :  8,
+                      data_done_offset                                        :  8;
+             uint32_t reserved_7a                                             :  8,
+                      abort_request_ack_offset                                :  8,
+                      pkt_end_offset                                          :  8,
+                      __reserved_g_0011                                       :  8;
+             uint32_t reserved_8a                                             : 32;
+             uint32_t reserved_9a                                             : 32;
+#endif
+};
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET                        0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB                           0
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB                           1
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK                          0x00000003
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET                            0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB                               2
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB                               7
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK                              0x000000fc
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET                            0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB                               8
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB                               13
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK                              0x00003f00
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET                             0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB                                14
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB                                19
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK                               0x000fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET                          0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB                             20
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB                             25
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK                            0x03f00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET                     0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB                        26
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB                        31
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK                       0xfc000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET                        0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB                           0
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB                           5
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK                          0x0000003f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET                     0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB                        6
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB                        11
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK                       0x00000fc0
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET                     0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB                        12
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB                        17
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK                       0x0003f000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET                      0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB                         18
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB                         23
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK                        0x00fc0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET                            0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB                               24
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB                               30
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK                              0x7f000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET                               0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK                                 0x80000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET                     0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB                        0
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB                        6
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK                       0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET                     0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB                        7
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB                        13
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK                       0x00003f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET                     0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB                        14
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB                        20
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK                       0x001fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET                    0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB                       21
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB                       27
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK                      0x0fe00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET                               0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB                                  28
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK                                 0xf0000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET                     0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB                        0
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB                        6
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK                       0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET                     0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB                        7
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB                        13
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK                       0x00003f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET                     0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB                        14
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB                        20
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK                       0x001fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET                    0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB                       21
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB                       27
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK                      0x0fe00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET                               0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB                                  28
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK                                 0xf0000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET                       0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB                          0
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB                          6
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK                         0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET                       0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB                          7
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB                          13
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK                         0x00003f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET                    0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB                       14
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB                       20
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK                      0x001fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET              0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB                 21
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB                 27
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK                0x0fe00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET         0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB            28
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB            28
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK           0x10000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET                               0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB                                  29
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK                                 0xe0000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET                   0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB                      0
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB                      6
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK                     0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET                   0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB                      7
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB                      14
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK                     0x00007f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET              0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB                 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB                 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK                0x00008000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET           0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB              16
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB              23
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK             0x00ff0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET      0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB         24
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB         24
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK        0x01000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET                               0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB                                  25
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK                                 0xfe000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET                          0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB                             0
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB                             7
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK                            0x000000ff
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET              0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB                 8
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB                 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK                0x0000ff00
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET                      0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB                         16
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB                         23
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK                        0x00ff0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET                           0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB                              24
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB                              31
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK                             0xff000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET                            0x0000001c
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB                               8
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB                               15
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK                              0x0000ff00
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET                  0x0000001c
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB                     16
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB                     23
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK                    0x00ff0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET                               0x0000001c
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB                                  24
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK                                 0xff000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET                               0x00000020
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB                                  0
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK                                 0xffffffff
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET                               0x00000024
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB                                  0
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB                                  31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK                                 0xffffffff
+
+#endif
diff --git a/hw/peach/v1/rxpt_classify_info.h b/hw/peach/v1/rxpt_classify_info.h
new file mode 100644
index 000000000000..e87054cf2dfb
--- /dev/null
+++ b/hw/peach/v1/rxpt_classify_info.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RXPT_CLASSIFY_INFO_H_
+#define _RXPT_CLASSIFY_INFO_H_
+
+#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1
+
+struct rxpt_classify_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reo_destination_indication                              :  5,
+                      lmac_peer_id_msb                                        :  2,
+                      use_flow_id_toeplitz_clfy                               :  1,
+                      pkt_selection_fp_ucast_data                             :  1,
+                      pkt_selection_fp_mcast_data                             :  1,
+                      pkt_selection_fp_1000                                   :  1,
+                      rxdma0_source_ring_selection                            :  3,
+                      rxdma0_destination_ring_selection                       :  3,
+                      mcast_echo_drop_enable                                  :  1,
+                      wds_learning_detect_en                                  :  1,
+                      intrabss_check_en                                       :  1,
+                      use_ppe                                                 :  1,
+                      ppe_routing_enable                                      :  1,
+                      cce_source_sel_en                                       :  1,
+                      reserved_0b                                             :  9;
+#else
+             uint32_t reserved_0b                                             :  9,
+                      cce_source_sel_en                                       :  1,
+                      ppe_routing_enable                                      :  1,
+                      use_ppe                                                 :  1,
+                      intrabss_check_en                                       :  1,
+                      wds_learning_detect_en                                  :  1,
+                      mcast_echo_drop_enable                                  :  1,
+                      rxdma0_destination_ring_selection                       :  3,
+                      rxdma0_source_ring_selection                            :  3,
+                      pkt_selection_fp_1000                                   :  1,
+                      pkt_selection_fp_mcast_data                             :  1,
+                      pkt_selection_fp_ucast_data                             :  1,
+                      use_flow_id_toeplitz_clfy                               :  1,
+                      lmac_peer_id_msb                                        :  2,
+                      reo_destination_indication                              :  5;
+#endif
+};
+
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET                        0x00000000
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB                           0
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB                           4
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK                          0x0000001f
+
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET                                  0x00000000
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB                                     5
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB                                     6
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK                                    0x00000060
+
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET                         0x00000000
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB                            7
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB                            7
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK                           0x00000080
+
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET                       0x00000000
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB                          8
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB                          8
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK                         0x00000100
+
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET                       0x00000000
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB                          9
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB                          9
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK                         0x00000200
+
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET                             0x00000000
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB                                10
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB                                10
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK                               0x00000400
+
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET                      0x00000000
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB                         11
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB                         13
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK                        0x00003800
+
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET                 0x00000000
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB                    14
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB                    16
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK                   0x0001c000
+
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET                            0x00000000
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB                               17
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB                               17
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK                              0x00020000
+
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET                            0x00000000
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB                               18
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB                               18
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK                              0x00040000
+
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET                                 0x00000000
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB                                    19
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB                                    19
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK                                   0x00080000
+
+#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET                                           0x00000000
+#define RXPT_CLASSIFY_INFO_USE_PPE_LSB                                              20
+#define RXPT_CLASSIFY_INFO_USE_PPE_MSB                                              20
+#define RXPT_CLASSIFY_INFO_USE_PPE_MASK                                             0x00100000
+
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET                                0x00000000
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB                                   21
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB                                   21
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK                                  0x00200000
+
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_OFFSET                                 0x00000000
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_LSB                                    22
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MSB                                    22
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MASK                                   0x00400000
+
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET                                       0x00000000
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB                                          23
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB                                          31
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK                                         0xff800000
+
+#endif
diff --git a/hw/peach/v1/seq_hwio.h b/hw/peach/v1/seq_hwio.h
new file mode 100644
index 000000000000..576abae9ee69
--- /dev/null
+++ b/hw/peach/v1/seq_hwio.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef __SEQ_H__
+#define __SEQ_H__
+
+#include "HALhwio.h"
+
+#define SEQ_INH(base, regtype, reg) \
+        SEQ_##regtype##_INH(base, reg)
+
+#define SEQ_INMH(base, regtype, reg, mask) \
+        SEQ_##regtype##_INMH(base, reg, mask)
+
+#define SEQ_INFH(base, regtype, reg, fld) \
+        (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld))
+
+#define SEQ_OUTH(base, regtype, reg, val) \
+        SEQ_##regtype##_OUTH(base, reg, val)
+
+#define SEQ_OUTMH(base, regtype, reg, mask, val) \
+        SEQ_##regtype##_OUTMH(base, reg, mask, val)
+
+#define SEQ_OUTFH(base, regtype, reg, fld, val) \
+        SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld))
+
+typedef enum {
+    SEC,
+    MS,
+    US,
+    NS
+} SEQ_TimeUnit;
+
+extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit);
+
+extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt);
+
+#endif
+
diff --git a/hw/peach/v1/tcl_data_cmd.h b/hw/peach/v1/tcl_data_cmd.h
new file mode 100644
index 000000000000..388b6dd7a301
--- /dev/null
+++ b/hw/peach/v1/tcl_data_cmd.h
@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TCL_DATA_CMD_H_
+#define _TCL_DATA_CMD_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_TCL_DATA_CMD 8
+
+struct tcl_data_cmd {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_addr_info;
+             uint32_t tcl_cmd_type                                            :  1,
+                      buf_or_ext_desc_type                                    :  1,
+                      bank_id                                                 :  6,
+                      tx_notify_frame                                         :  3,
+                      header_length_read_sel                                  :  1,
+                      buffer_timestamp                                        : 19,
+                      buffer_timestamp_valid                                  :  1;
+             uint32_t reserved_3a                                             : 16,
+                      tcl_cmd_number                                          : 16;
+             uint32_t data_length                                             : 16,
+                      ipv4_checksum_en                                        :  1,
+                      udp_over_ipv4_checksum_en                               :  1,
+                      udp_over_ipv6_checksum_en                               :  1,
+                      tcp_over_ipv4_checksum_en                               :  1,
+                      tcp_over_ipv6_checksum_en                               :  1,
+                      to_fw                                                   :  1,
+                      reserved_4a                                             :  1,
+                      packet_offset                                           :  9;
+             uint32_t hlos_tid_overwrite                                      :  1,
+                      flow_override_enable                                    :  1,
+                      who_classify_info_sel                                   :  2,
+                      hlos_tid                                                :  4,
+                      flow_override                                           :  1,
+                      pmac_id                                                 :  2,
+                      msdu_color                                              :  2,
+                      reserved_5a                                             : 11,
+                      vdev_id                                                 :  8;
+             uint32_t search_index                                            : 20,
+                      cache_set_num                                           :  4,
+                      index_lookup_override                                   :  1,
+                      reserved_6a                                             :  7;
+             uint32_t reserved_7a                                             : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          buf_addr_info;
+             uint32_t buffer_timestamp_valid                                  :  1,
+                      buffer_timestamp                                        : 19,
+                      header_length_read_sel                                  :  1,
+                      tx_notify_frame                                         :  3,
+                      bank_id                                                 :  6,
+                      buf_or_ext_desc_type                                    :  1,
+                      tcl_cmd_type                                            :  1;
+             uint32_t tcl_cmd_number                                          : 16,
+                      reserved_3a                                             : 16;
+             uint32_t packet_offset                                           :  9,
+                      reserved_4a                                             :  1,
+                      to_fw                                                   :  1,
+                      tcp_over_ipv6_checksum_en                               :  1,
+                      tcp_over_ipv4_checksum_en                               :  1,
+                      udp_over_ipv6_checksum_en                               :  1,
+                      udp_over_ipv4_checksum_en                               :  1,
+                      ipv4_checksum_en                                        :  1,
+                      data_length                                             : 16;
+             uint32_t vdev_id                                                 :  8,
+                      reserved_5a                                             : 11,
+                      msdu_color                                              :  2,
+                      pmac_id                                                 :  2,
+                      flow_override                                           :  1,
+                      hlos_tid                                                :  4,
+                      who_classify_info_sel                                   :  2,
+                      flow_override_enable                                    :  1,
+                      hlos_tid_overwrite                                      :  1;
+             uint32_t reserved_6a                                             :  7,
+                      index_lookup_override                                   :  1,
+                      cache_set_num                                           :  4,
+                      search_index                                            : 20;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_7a                                             : 20;
+#endif
+};
+
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET                          0x00000000
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB                             0
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB                             31
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK                            0xffffffff
+
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET                         0x00000004
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB                            0
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB                            7
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK                           0x000000ff
+
+#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET                     0x00000004
+#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB                        8
+#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB                        11
+#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK                       0x00000f00
+
+#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET                          0x00000004
+#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB                             12
+#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB                             31
+#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK                            0xfffff000
+
+#define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET                                            0x00000008
+#define TCL_DATA_CMD_TCL_CMD_TYPE_LSB                                               0
+#define TCL_DATA_CMD_TCL_CMD_TYPE_MSB                                               0
+#define TCL_DATA_CMD_TCL_CMD_TYPE_MASK                                              0x00000001
+
+#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET                                    0x00000008
+#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB                                       1
+#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB                                       1
+#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK                                      0x00000002
+
+#define TCL_DATA_CMD_BANK_ID_OFFSET                                                 0x00000008
+#define TCL_DATA_CMD_BANK_ID_LSB                                                    2
+#define TCL_DATA_CMD_BANK_ID_MSB                                                    7
+#define TCL_DATA_CMD_BANK_ID_MASK                                                   0x000000fc
+
+#define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET                                         0x00000008
+#define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB                                            8
+#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB                                            10
+#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK                                           0x00000700
+
+#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET                                  0x00000008
+#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB                                     11
+#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB                                     11
+#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK                                    0x00000800
+
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET                                        0x00000008
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB                                           12
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB                                           30
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK                                          0x7ffff000
+
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET                                  0x00000008
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB                                     31
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB                                     31
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK                                    0x80000000
+
+#define TCL_DATA_CMD_RESERVED_3A_OFFSET                                             0x0000000c
+#define TCL_DATA_CMD_RESERVED_3A_LSB                                                0
+#define TCL_DATA_CMD_RESERVED_3A_MSB                                                15
+#define TCL_DATA_CMD_RESERVED_3A_MASK                                               0x0000ffff
+
+#define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET                                          0x0000000c
+#define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB                                             16
+#define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB                                             31
+#define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK                                            0xffff0000
+
+#define TCL_DATA_CMD_DATA_LENGTH_OFFSET                                             0x00000010
+#define TCL_DATA_CMD_DATA_LENGTH_LSB                                                0
+#define TCL_DATA_CMD_DATA_LENGTH_MSB                                                15
+#define TCL_DATA_CMD_DATA_LENGTH_MASK                                               0x0000ffff
+
+#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET                                        0x00000010
+#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB                                           16
+#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB                                           16
+#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK                                          0x00010000
+
+#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET                               0x00000010
+#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB                                  17
+#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB                                  17
+#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK                                 0x00020000
+
+#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET                               0x00000010
+#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB                                  18
+#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB                                  18
+#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK                                 0x00040000
+
+#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET                               0x00000010
+#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB                                  19
+#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB                                  19
+#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK                                 0x00080000
+
+#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET                               0x00000010
+#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB                                  20
+#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB                                  20
+#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK                                 0x00100000
+
+#define TCL_DATA_CMD_TO_FW_OFFSET                                                   0x00000010
+#define TCL_DATA_CMD_TO_FW_LSB                                                      21
+#define TCL_DATA_CMD_TO_FW_MSB                                                      21
+#define TCL_DATA_CMD_TO_FW_MASK                                                     0x00200000
+
+#define TCL_DATA_CMD_RESERVED_4A_OFFSET                                             0x00000010
+#define TCL_DATA_CMD_RESERVED_4A_LSB                                                22
+#define TCL_DATA_CMD_RESERVED_4A_MSB                                                22
+#define TCL_DATA_CMD_RESERVED_4A_MASK                                               0x00400000
+
+#define TCL_DATA_CMD_PACKET_OFFSET_OFFSET                                           0x00000010
+#define TCL_DATA_CMD_PACKET_OFFSET_LSB                                              23
+#define TCL_DATA_CMD_PACKET_OFFSET_MSB                                              31
+#define TCL_DATA_CMD_PACKET_OFFSET_MASK                                             0xff800000
+
+#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET                                      0x00000014
+#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB                                         0
+#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB                                         0
+#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK                                        0x00000001
+
+#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET                                    0x00000014
+#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB                                       1
+#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB                                       1
+#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK                                      0x00000002
+
+#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET                                   0x00000014
+#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB                                      2
+#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB                                      3
+#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK                                     0x0000000c
+
+#define TCL_DATA_CMD_HLOS_TID_OFFSET                                                0x00000014
+#define TCL_DATA_CMD_HLOS_TID_LSB                                                   4
+#define TCL_DATA_CMD_HLOS_TID_MSB                                                   7
+#define TCL_DATA_CMD_HLOS_TID_MASK                                                  0x000000f0
+
+#define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET                                           0x00000014
+#define TCL_DATA_CMD_FLOW_OVERRIDE_LSB                                              8
+#define TCL_DATA_CMD_FLOW_OVERRIDE_MSB                                              8
+#define TCL_DATA_CMD_FLOW_OVERRIDE_MASK                                             0x00000100
+
+#define TCL_DATA_CMD_PMAC_ID_OFFSET                                                 0x00000014
+#define TCL_DATA_CMD_PMAC_ID_LSB                                                    9
+#define TCL_DATA_CMD_PMAC_ID_MSB                                                    10
+#define TCL_DATA_CMD_PMAC_ID_MASK                                                   0x00000600
+
+#define TCL_DATA_CMD_MSDU_COLOR_OFFSET                                              0x00000014
+#define TCL_DATA_CMD_MSDU_COLOR_LSB                                                 11
+#define TCL_DATA_CMD_MSDU_COLOR_MSB                                                 12
+#define TCL_DATA_CMD_MSDU_COLOR_MASK                                                0x00001800
+
+#define TCL_DATA_CMD_RESERVED_5A_OFFSET                                             0x00000014
+#define TCL_DATA_CMD_RESERVED_5A_LSB                                                13
+#define TCL_DATA_CMD_RESERVED_5A_MSB                                                23
+#define TCL_DATA_CMD_RESERVED_5A_MASK                                               0x00ffe000
+
+#define TCL_DATA_CMD_VDEV_ID_OFFSET                                                 0x00000014
+#define TCL_DATA_CMD_VDEV_ID_LSB                                                    24
+#define TCL_DATA_CMD_VDEV_ID_MSB                                                    31
+#define TCL_DATA_CMD_VDEV_ID_MASK                                                   0xff000000
+
+#define TCL_DATA_CMD_SEARCH_INDEX_OFFSET                                            0x00000018
+#define TCL_DATA_CMD_SEARCH_INDEX_LSB                                               0
+#define TCL_DATA_CMD_SEARCH_INDEX_MSB                                               19
+#define TCL_DATA_CMD_SEARCH_INDEX_MASK                                              0x000fffff
+
+#define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET                                           0x00000018
+#define TCL_DATA_CMD_CACHE_SET_NUM_LSB                                              20
+#define TCL_DATA_CMD_CACHE_SET_NUM_MSB                                              23
+#define TCL_DATA_CMD_CACHE_SET_NUM_MASK                                             0x00f00000
+
+#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET                                   0x00000018
+#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB                                      24
+#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB                                      24
+#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK                                     0x01000000
+
+#define TCL_DATA_CMD_RESERVED_6A_OFFSET                                             0x00000018
+#define TCL_DATA_CMD_RESERVED_6A_LSB                                                25
+#define TCL_DATA_CMD_RESERVED_6A_MSB                                                31
+#define TCL_DATA_CMD_RESERVED_6A_MASK                                               0xfe000000
+
+#define TCL_DATA_CMD_RESERVED_7A_OFFSET                                             0x0000001c
+#define TCL_DATA_CMD_RESERVED_7A_LSB                                                0
+#define TCL_DATA_CMD_RESERVED_7A_MSB                                                19
+#define TCL_DATA_CMD_RESERVED_7A_MASK                                               0x000fffff
+
+#define TCL_DATA_CMD_RING_ID_OFFSET                                                 0x0000001c
+#define TCL_DATA_CMD_RING_ID_LSB                                                    20
+#define TCL_DATA_CMD_RING_ID_MSB                                                    27
+#define TCL_DATA_CMD_RING_ID_MASK                                                   0x0ff00000
+
+#define TCL_DATA_CMD_LOOPING_COUNT_OFFSET                                           0x0000001c
+#define TCL_DATA_CMD_LOOPING_COUNT_LSB                                              28
+#define TCL_DATA_CMD_LOOPING_COUNT_MSB                                              31
+#define TCL_DATA_CMD_LOOPING_COUNT_MASK                                             0xf0000000
+
+#endif
diff --git a/hw/peach/v1/tcl_gse_cmd.h b/hw/peach/v1/tcl_gse_cmd.h
new file mode 100644
index 000000000000..9ab07f469049
--- /dev/null
+++ b/hw/peach/v1/tcl_gse_cmd.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TCL_GSE_CMD_H_
+#define _TCL_GSE_CMD_H_
+
+#define NUM_OF_DWORDS_TCL_GSE_CMD 8
+
+struct tcl_gse_cmd {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t control_buffer_addr_31_0                                : 32;
+             uint32_t control_buffer_addr_39_32                               :  8,
+                      gse_ctrl                                                :  4,
+                      gse_sel                                                 :  1,
+                      status_destination_ring_id                              :  1,
+                      swap                                                    :  1,
+                      index_search_en                                         :  1,
+                      cache_set_num                                           :  4,
+                      reserved_1a                                             : 12;
+             uint32_t tcl_cmd_type                                            :  1,
+                      reserved_2a                                             : 31;
+             uint32_t cmd_meta_data_31_0                                      : 32;
+             uint32_t cmd_meta_data_63_32                                     : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t control_buffer_addr_31_0                                : 32;
+             uint32_t reserved_1a                                             : 12,
+                      cache_set_num                                           :  4,
+                      index_search_en                                         :  1,
+                      swap                                                    :  1,
+                      status_destination_ring_id                              :  1,
+                      gse_sel                                                 :  1,
+                      gse_ctrl                                                :  4,
+                      control_buffer_addr_39_32                               :  8;
+             uint32_t reserved_2a                                             : 31,
+                      tcl_cmd_type                                            :  1;
+             uint32_t cmd_meta_data_31_0                                      : 32;
+             uint32_t cmd_meta_data_63_32                                     : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_7a                                             : 20;
+#endif
+};
+
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET                                 0x00000000
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB                                    0
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB                                    31
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK                                   0xffffffff
+
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET                                0x00000004
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB                                   0
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB                                   7
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK                                  0x000000ff
+
+#define TCL_GSE_CMD_GSE_CTRL_OFFSET                                                 0x00000004
+#define TCL_GSE_CMD_GSE_CTRL_LSB                                                    8
+#define TCL_GSE_CMD_GSE_CTRL_MSB                                                    11
+#define TCL_GSE_CMD_GSE_CTRL_MASK                                                   0x00000f00
+
+#define TCL_GSE_CMD_GSE_SEL_OFFSET                                                  0x00000004
+#define TCL_GSE_CMD_GSE_SEL_LSB                                                     12
+#define TCL_GSE_CMD_GSE_SEL_MSB                                                     12
+#define TCL_GSE_CMD_GSE_SEL_MASK                                                    0x00001000
+
+#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET                               0x00000004
+#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB                                  13
+#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB                                  13
+#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK                                 0x00002000
+
+#define TCL_GSE_CMD_SWAP_OFFSET                                                     0x00000004
+#define TCL_GSE_CMD_SWAP_LSB                                                        14
+#define TCL_GSE_CMD_SWAP_MSB                                                        14
+#define TCL_GSE_CMD_SWAP_MASK                                                       0x00004000
+
+#define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET                                          0x00000004
+#define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB                                             15
+#define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB                                             15
+#define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK                                            0x00008000
+
+#define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET                                            0x00000004
+#define TCL_GSE_CMD_CACHE_SET_NUM_LSB                                               16
+#define TCL_GSE_CMD_CACHE_SET_NUM_MSB                                               19
+#define TCL_GSE_CMD_CACHE_SET_NUM_MASK                                              0x000f0000
+
+#define TCL_GSE_CMD_RESERVED_1A_OFFSET                                              0x00000004
+#define TCL_GSE_CMD_RESERVED_1A_LSB                                                 20
+#define TCL_GSE_CMD_RESERVED_1A_MSB                                                 31
+#define TCL_GSE_CMD_RESERVED_1A_MASK                                                0xfff00000
+
+#define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET                                             0x00000008
+#define TCL_GSE_CMD_TCL_CMD_TYPE_LSB                                                0
+#define TCL_GSE_CMD_TCL_CMD_TYPE_MSB                                                0
+#define TCL_GSE_CMD_TCL_CMD_TYPE_MASK                                               0x00000001
+
+#define TCL_GSE_CMD_RESERVED_2A_OFFSET                                              0x00000008
+#define TCL_GSE_CMD_RESERVED_2A_LSB                                                 1
+#define TCL_GSE_CMD_RESERVED_2A_MSB                                                 31
+#define TCL_GSE_CMD_RESERVED_2A_MASK                                                0xfffffffe
+
+#define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET                                       0x0000000c
+#define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB                                          0
+#define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB                                          31
+#define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK                                         0xffffffff
+
+#define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET                                      0x00000010
+#define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB                                         0
+#define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB                                         31
+#define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK                                        0xffffffff
+
+#define TCL_GSE_CMD_RESERVED_5A_OFFSET                                              0x00000014
+#define TCL_GSE_CMD_RESERVED_5A_LSB                                                 0
+#define TCL_GSE_CMD_RESERVED_5A_MSB                                                 31
+#define TCL_GSE_CMD_RESERVED_5A_MASK                                                0xffffffff
+
+#define TCL_GSE_CMD_RESERVED_6A_OFFSET                                              0x00000018
+#define TCL_GSE_CMD_RESERVED_6A_LSB                                                 0
+#define TCL_GSE_CMD_RESERVED_6A_MSB                                                 31
+#define TCL_GSE_CMD_RESERVED_6A_MASK                                                0xffffffff
+
+#define TCL_GSE_CMD_RESERVED_7A_OFFSET                                              0x0000001c
+#define TCL_GSE_CMD_RESERVED_7A_LSB                                                 0
+#define TCL_GSE_CMD_RESERVED_7A_MSB                                                 19
+#define TCL_GSE_CMD_RESERVED_7A_MASK                                                0x000fffff
+
+#define TCL_GSE_CMD_RING_ID_OFFSET                                                  0x0000001c
+#define TCL_GSE_CMD_RING_ID_LSB                                                     20
+#define TCL_GSE_CMD_RING_ID_MSB                                                     27
+#define TCL_GSE_CMD_RING_ID_MASK                                                    0x0ff00000
+
+#define TCL_GSE_CMD_LOOPING_COUNT_OFFSET                                            0x0000001c
+#define TCL_GSE_CMD_LOOPING_COUNT_LSB                                               28
+#define TCL_GSE_CMD_LOOPING_COUNT_MSB                                               31
+#define TCL_GSE_CMD_LOOPING_COUNT_MASK                                              0xf0000000
+
+#endif
diff --git a/hw/peach/v1/tcl_status_ring.h b/hw/peach/v1/tcl_status_ring.h
new file mode 100644
index 000000000000..8930533a442e
--- /dev/null
+++ b/hw/peach/v1/tcl_status_ring.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TCL_STATUS_RING_H_
+#define _TCL_STATUS_RING_H_
+
+#define NUM_OF_DWORDS_TCL_STATUS_RING 8
+
+struct tcl_status_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t gse_ctrl                                                :  4,
+                      ase_fse_sel                                             :  1,
+                      cache_op_res                                            :  2,
+                      index_search_en                                         :  1,
+                      msdu_cnt_n                                              : 24;
+             uint32_t msdu_byte_cnt_n                                         : 32;
+             uint32_t msdu_timestmp_n                                         : 32;
+             uint32_t cmd_meta_data_31_0                                      : 32;
+             uint32_t cmd_meta_data_63_32                                     : 32;
+             uint32_t hash_indx_val                                           : 20,
+                      cache_set_num                                           :  4,
+                      reserved_5a                                             :  8;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t msdu_cnt_n                                              : 24,
+                      index_search_en                                         :  1,
+                      cache_op_res                                            :  2,
+                      ase_fse_sel                                             :  1,
+                      gse_ctrl                                                :  4;
+             uint32_t msdu_byte_cnt_n                                         : 32;
+             uint32_t msdu_timestmp_n                                         : 32;
+             uint32_t cmd_meta_data_31_0                                      : 32;
+             uint32_t cmd_meta_data_63_32                                     : 32;
+             uint32_t reserved_5a                                             :  8,
+                      cache_set_num                                           :  4,
+                      hash_indx_val                                           : 20;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_7a                                             : 20;
+#endif
+};
+
+#define TCL_STATUS_RING_GSE_CTRL_OFFSET                                             0x00000000
+#define TCL_STATUS_RING_GSE_CTRL_LSB                                                0
+#define TCL_STATUS_RING_GSE_CTRL_MSB                                                3
+#define TCL_STATUS_RING_GSE_CTRL_MASK                                               0x0000000f
+
+#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET                                          0x00000000
+#define TCL_STATUS_RING_ASE_FSE_SEL_LSB                                             4
+#define TCL_STATUS_RING_ASE_FSE_SEL_MSB                                             4
+#define TCL_STATUS_RING_ASE_FSE_SEL_MASK                                            0x00000010
+
+#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET                                         0x00000000
+#define TCL_STATUS_RING_CACHE_OP_RES_LSB                                            5
+#define TCL_STATUS_RING_CACHE_OP_RES_MSB                                            6
+#define TCL_STATUS_RING_CACHE_OP_RES_MASK                                           0x00000060
+
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET                                      0x00000000
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB                                         7
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB                                         7
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK                                        0x00000080
+
+#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET                                           0x00000000
+#define TCL_STATUS_RING_MSDU_CNT_N_LSB                                              8
+#define TCL_STATUS_RING_MSDU_CNT_N_MSB                                              31
+#define TCL_STATUS_RING_MSDU_CNT_N_MASK                                             0xffffff00
+
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET                                      0x00000004
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB                                         0
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB                                         31
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK                                        0xffffffff
+
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET                                      0x00000008
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB                                         0
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB                                         31
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK                                        0xffffffff
+
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET                                   0x0000000c
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB                                      0
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB                                      31
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK                                     0xffffffff
+
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET                                  0x00000010
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB                                     0
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB                                     31
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK                                    0xffffffff
+
+#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET                                        0x00000014
+#define TCL_STATUS_RING_HASH_INDX_VAL_LSB                                           0
+#define TCL_STATUS_RING_HASH_INDX_VAL_MSB                                           19
+#define TCL_STATUS_RING_HASH_INDX_VAL_MASK                                          0x000fffff
+
+#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET                                        0x00000014
+#define TCL_STATUS_RING_CACHE_SET_NUM_LSB                                           20
+#define TCL_STATUS_RING_CACHE_SET_NUM_MSB                                           23
+#define TCL_STATUS_RING_CACHE_SET_NUM_MASK                                          0x00f00000
+
+#define TCL_STATUS_RING_RESERVED_5A_OFFSET                                          0x00000014
+#define TCL_STATUS_RING_RESERVED_5A_LSB                                             24
+#define TCL_STATUS_RING_RESERVED_5A_MSB                                             31
+#define TCL_STATUS_RING_RESERVED_5A_MASK                                            0xff000000
+
+#define TCL_STATUS_RING_RESERVED_6A_OFFSET                                          0x00000018
+#define TCL_STATUS_RING_RESERVED_6A_LSB                                             0
+#define TCL_STATUS_RING_RESERVED_6A_MSB                                             31
+#define TCL_STATUS_RING_RESERVED_6A_MASK                                            0xffffffff
+
+#define TCL_STATUS_RING_RESERVED_7A_OFFSET                                          0x0000001c
+#define TCL_STATUS_RING_RESERVED_7A_LSB                                             0
+#define TCL_STATUS_RING_RESERVED_7A_MSB                                             19
+#define TCL_STATUS_RING_RESERVED_7A_MASK                                            0x000fffff
+
+#define TCL_STATUS_RING_RING_ID_OFFSET                                              0x0000001c
+#define TCL_STATUS_RING_RING_ID_LSB                                                 20
+#define TCL_STATUS_RING_RING_ID_MSB                                                 27
+#define TCL_STATUS_RING_RING_ID_MASK                                                0x0ff00000
+
+#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET                                        0x0000001c
+#define TCL_STATUS_RING_LOOPING_COUNT_LSB                                           28
+#define TCL_STATUS_RING_LOOPING_COUNT_MSB                                           31
+#define TCL_STATUS_RING_LOOPING_COUNT_MASK                                          0xf0000000
+
+#endif
diff --git a/hw/peach/v1/tlv_hdr.h b/hw/peach/v1/tlv_hdr.h
new file mode 100644
index 000000000000..6d25ff3047dc
--- /dev/null
+++ b/hw/peach/v1/tlv_hdr.h
@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TLV_HDR_H_
+#define _TLV_HDR_H_
+
+#define _TLV_USERID_WIDTH_      6
+#define _TLV_DATA_WIDTH_        32
+#define _TLV_TAG_WIDTH_         9
+
+#define _TLV_MRV_EN_LEN_WIDTH_  9
+#define _TLV_MRV_DIS_LEN_WIDTH_ 12
+
+#define _TLV_16_DATA_WIDTH_     16
+#define _TLV_16_TAG_WIDTH_      5
+#define _TLV_16_LEN_WIDTH_      4
+#define _TLV_CTAG_WIDTH_        5
+#define _TLV_44_DATA_WIDTH_     44
+#define _TLV_64_DATA_WIDTH_     64
+#define _TLV_76_DATA_WIDTH_     64
+#define _TLV_CDATA_WIDTH_       32
+#define _TLV_CDATA_76_WIDTH_    64
+
+struct tlv_usr_16_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint16_t             tlv_cflg_reserved   :   1,
+                                tlv_tag             :   _TLV_16_TAG_WIDTH_,
+                                tlv_len             :   _TLV_16_LEN_WIDTH_,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+#else
+           uint16_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_len             :   _TLV_16_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_16_TAG_WIDTH_,
+                                tlv_cflg_reserved   :   1;
+#endif
+};
+
+struct tlv_16_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint16_t             tlv_cflg_reserved   :   1,
+                                tlv_len             :   _TLV_16_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_16_TAG_WIDTH_,
+                                tlv_reserved        :   6;
+#else
+           uint16_t             tlv_reserved        :   6,
+                                tlv_tag             :   _TLV_16_TAG_WIDTH_,
+                                tlv_len             :   _TLV_16_LEN_WIDTH_,
+                                tlv_cflg_reserved   :   1;
+#endif
+};
+
+struct tlv_mac_usr_32_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_cflg_reserved   :   1,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_cflg_reserved   :   1;
+#endif
+};
+
+struct tlv_mac_32_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_cflg_reserved   :   1,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   6;
+#else
+           uint32_t             tlv_reserved        :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_cflg_reserved   :   1;
+#endif
+};
+
+struct tlv_mac_usr_64_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_cflg_reserved   :   1,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+#else
+           uint64_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_cflg_reserved   :   1,
+#endif
+                                tlv_reserved        :   32;
+};
+
+struct tlv_mac_64_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_cflg_reserved   :   1,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   38;
+#else
+           uint64_t             tlv_usrid_reserved  :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_cflg_reserved   :   1,
+                                tlv_reserved        :   32;
+#endif
+};
+
+struct tlv_mac_usr_44_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_compression     :   1,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_reserved        :   10,
+                                pad_44to64_bit      :   22;
+#else
+           uint64_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_compression     :   1,
+                                pad_44to64_bit      :   22,
+                                tlv_reserved        :   10;
+#endif
+};
+
+struct tlv_mac_44_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_compression     :   1,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   16,
+                                pad_44to64_bit      :   22;
+#else
+           uint64_t             tlv_usrid_reserved  :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_compression     :   1,
+                                pad_44to64_bit      :   22,
+                                tlv_reserved        :   10;
+#endif
+};
+
+struct tlv_mac_usr_76_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_compression     :   1,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+#else
+           uint64_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_compression     :   1,
+#endif
+                                tlv_reserved        :   32;
+           uint64_t             pad_64to128_bit     :   64;
+};
+
+struct tlv_mac_76_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_compression     :   1,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   38;
+#else
+           uint64_t             tlv_usrid_reserved  :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_compression     :   1,
+                                tlv_reserved        :   32;
+#endif
+           uint64_t             pad_64to128_bit     :   64;
+};
+
+struct tlv_usr_c_44_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_compression     :   1,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_cdata           :   _TLV_CDATA_WIDTH_,
+                                pad_44to64_bit      :   20;
+#else
+           uint64_t             tlv_cdata_lower_20  :   20,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_compression     :   1,
+                                pad_44to64_bit      :   20,
+                                tlv_cdata_upper_12  :   12;
+#endif
+};
+
+struct tlv_usr_c_76_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint64_t             tlv_compression     :   1,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_cdata_lower_52  :   52;
+           uint64_t             tlv_cdata_upper_12  :   12,
+                                pad_76to128_bit     :   52;
+#else
+           uint64_t             tlv_cdata_lower_20  :   20,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_compression     :   1,
+                                tlv_cdata_middle_32 :   32;
+           uint64_t             pad_76to96_bit      :   20,
+                                tlv_cdata_upper_12  :   12,
+                                pad_96to128_bit     :   32;
+#endif
+};
+
+struct tlv_usr_32_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_cflg_reserved   :   1,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_cflg_reserved   :   1;
+#endif
+};
+
+struct tlv_32_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_cflg_reserved   :   1,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   6;
+#else
+           uint32_t             tlv_reserved        :   6,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_cflg_reserved   :   1;
+#endif
+};
+
+struct tlv_mlo_usr_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_cflg_reserved   :   1,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_dst_linkid      :   3,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_dst_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_cflg_reserved   :   1;
+#endif
+           uint32_t             pad_32to64_bit      :   32;
+};
+
+struct tlv_mlo_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_cflg_reserved   :   1,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_dst_linkid      :   3,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_reserved        :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_dst_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_EN_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_cflg_reserved   :   1;
+#endif
+           uint32_t             pad_32to64_bit      :   32;
+};
+
+struct tlv_mac_usr_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_cflg_reserved   :   1,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_cflg_reserved   :   1;
+#endif
+           uint32_t             pad_32to64_bit      :   32;
+};
+
+struct tlv_mac_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_cflg_reserved   :   1,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_src_linkid      :   3,
+                                tlv_mrv             :   1,
+                                tlv_reserved        :   _TLV_USERID_WIDTH_;
+#else
+           uint32_t             tlv_reserved        :   _TLV_USERID_WIDTH_,
+                                tlv_mrv             :   1,
+                                tlv_src_linkid      :   3,
+                                tlv_len             :   _TLV_MRV_DIS_LEN_WIDTH_,
+                                tlv_tag             :   _TLV_TAG_WIDTH_,
+                                tlv_cflg_reserved   :   1;
+#endif
+           uint32_t             pad_32to64_bit      :   32;
+};
+
+struct tlv_usr_c_44_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_compression     :   1,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_cdata_lower_20  :   20;
+           uint32_t             tlv_cdata_upper_12  :   12,
+                                pad_44to64_bit      :   20;
+#else
+           uint32_t             tlv_cdata_lower_20  :   20,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_compression     :   1;
+           uint32_t             pad_44to64_bit      :   20,
+                                tlv_cdata_upper_12  :   12;
+#endif
+};
+
+struct tlv_usr_c_76_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+           uint32_t             tlv_compression     :   1,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_cdata_lower_20  :   20;
+           uint32_t             tlv_cdata_middle_32 :   32;
+           uint32_t             tlv_cdata_upper_12  :   12,
+                                pad_76to96_bit      :   20;
+           uint32_t             pad_96to128_bit     :   32;
+#else
+           uint32_t             tlv_cdata_lower_20  :   20,
+                                tlv_usrid           :   _TLV_USERID_WIDTH_,
+                                tlv_ctag            :   _TLV_CTAG_WIDTH_,
+                                tlv_compression     :   1;
+           uint32_t             tlv_cdata_middle_32 :   32;
+           uint32_t             pad_76to96_bit      :   20,
+                                tlv_cdata_upper_12  :   12;
+           uint32_t             pad_96to128_bit     :   32;
+#endif
+};
+
+#endif
diff --git a/hw/peach/v1/tlv_tag_def.h b/hw/peach/v1/tlv_tag_def.h
new file mode 100644
index 000000000000..bbbd5f376f44
--- /dev/null
+++ b/hw/peach/v1/tlv_tag_def.h
@@ -0,0 +1,510 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TLV_TAG_DEF_
+#define _TLV_TAG_DEF_
+
+typedef enum tlv_tag_def {
+  WIFIMACTX_CBF_START_E                                    = 0  ,
+  WIFIPHYRX_DATA_E                                         = 1  ,
+  WIFIPHYRX_CBF_DATA_RESP_E                                = 2  ,
+  WIFIPHYRX_ABORT_REQUEST_E                                = 3  ,
+  WIFIPHYRX_USER_ABORT_NOTIFICATION_E                      = 4  ,
+  WIFIMACTX_DATA_RESP_E                                    = 5  ,
+  WIFIMACTX_CBF_DATA_E                                     = 6  ,
+  WIFIMACTX_CBF_DONE_E                                     = 7  ,
+  WIFIPHYRX_LMR_DATA_RESP_E                                = 8  ,
+  WIFIRXPCU_TO_UCODE_START_E                               = 9  ,
+  WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E             = 10  ,
+  WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E                      = 11  ,
+  WIFIRXPCU_TO_UCODE_FCS_STATUS_E                          = 12  ,
+  WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E                      = 13  ,
+  WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E           = 14  ,
+  WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E                    = 15  ,
+  WIFIRXPCU_TO_UCODE_END_E                                 = 16  ,
+  WIFIPHYRX_RSSI_LEGACY_20MHZ_E                            = 28  ,
+  WIFIPHYRX_NC_ABORT_REQUEST_E                             = 29  ,
+  WIFIPHYRX_PKT_END_20MHZ_E                                = 30  ,
+  WIFIPHYRX_NC_DATA_E                                      = 31  ,
+  WIFIMACRX_CBF_READ_REQUEST_E                             = 32  ,
+  WIFIMACRX_CBF_DATA_REQUEST_E                             = 33  ,
+  WIFIMACRX_EXPECT_NDP_RECEPTION_E                         = 34  ,
+  WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E                       = 35  ,
+  WIFIMACRX_NDP_TIMEOUT_E                                  = 36  ,
+  WIFIMACRX_ABORT_ACK_E                                    = 37  ,
+  WIFIMACRX_REQ_IMPLICIT_FB_E                              = 38  ,
+  WIFIMACRX_CHAIN_MASK_E                                   = 39  ,
+  WIFIMACRX_NAP_USER_E                                     = 40  ,
+  WIFIMACRX_ABORT_REQUEST_E                                = 41  ,
+  WIFIPHYTX_OTHER_TRANSMIT_INFO16_E                        = 42  ,
+  WIFIPHYTX_ABORT_ACK_E                                    = 43  ,
+  WIFIPHYTX_ABORT_REQUEST_E                                = 44  ,
+  WIFIPHYTX_PKT_END_E                                      = 45  ,
+  WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E                     = 46  ,
+  WIFIPHYTX_REQUEST_CTRL_INFO_E                            = 47  ,
+  WIFIPHYTX_DATA_REQUEST_E                                 = 48  ,
+  WIFIPHYTX_BF_CV_LOADING_DONE_E                           = 49  ,
+  WIFIPHYTX_NAP_ACK_E                                      = 50  ,
+  WIFIPHYTX_NAP_DONE_E                                     = 51  ,
+  WIFIPHYTX_OFF_ACK_E                                      = 52  ,
+  WIFIPHYTX_ON_ACK_E                                       = 53  ,
+  WIFIPHYTX_SYNTH_OFF_ACK_E                                = 54  ,
+  WIFIPHYTX_DEBUG16_E                                      = 55  ,
+  WIFIMACTX_ABORT_REQUEST_E                                = 56  ,
+  WIFIMACTX_ABORT_ACK_E                                    = 57  ,
+  WIFIMACTX_PKT_END_E                                      = 58  ,
+  WIFIMACTX_PRE_PHY_DESC_E                                 = 59  ,
+  WIFIMACTX_BF_PARAMS_COMMON_E                             = 60  ,
+  WIFIMACTX_BF_PARAMS_PER_USER_E                           = 61  ,
+  WIFIMACTX_PREFETCH_CV_E                                  = 62  ,
+  WIFIMACTX_USER_DESC_COMMON_E                             = 63  ,
+  WIFIMACTX_USER_DESC_PER_USER_E                           = 64  ,
+  WIFIEXAMPLE_USER_TLV_16_E                                = 65  ,
+  WIFIEXAMPLE_TLV_16_E                                     = 66  ,
+  WIFIMACTX_PHY_OFF_E                                      = 67  ,
+  WIFIMACTX_PHY_ON_E                                       = 68  ,
+  WIFIMACTX_SYNTH_OFF_E                                    = 69  ,
+  WIFIMACTX_EXPECT_CBF_COMMON_E                            = 70  ,
+  WIFIMACTX_EXPECT_CBF_PER_USER_E                          = 71  ,
+  WIFIMACTX_PHY_DESC_E                                     = 72  ,
+  WIFIMACTX_L_SIG_A_E                                      = 73  ,
+  WIFIMACTX_L_SIG_B_E                                      = 74  ,
+  WIFIMACTX_HT_SIG_E                                       = 75  ,
+  WIFIMACTX_VHT_SIG_A_E                                    = 76  ,
+  WIFIMACTX_VHT_SIG_B_SU20_E                               = 77  ,
+  WIFIMACTX_VHT_SIG_B_SU40_E                               = 78  ,
+  WIFIMACTX_VHT_SIG_B_SU80_E                               = 79  ,
+  WIFIMACTX_VHT_SIG_B_SU160_E                              = 80  ,
+  WIFIMACTX_VHT_SIG_B_MU20_E                               = 81  ,
+  WIFIMACTX_VHT_SIG_B_MU40_E                               = 82  ,
+  WIFIMACTX_VHT_SIG_B_MU80_E                               = 83  ,
+  WIFIMACTX_VHT_SIG_B_MU160_E                              = 84  ,
+  WIFIMACTX_SERVICE_E                                      = 85  ,
+  WIFIMACTX_HE_SIG_A_SU_E                                  = 86  ,
+  WIFIMACTX_HE_SIG_A_MU_DL_E                               = 87  ,
+  WIFIMACTX_HE_SIG_A_MU_UL_E                               = 88  ,
+  WIFIMACTX_HE_SIG_B1_MU_E                                 = 89  ,
+  WIFIMACTX_HE_SIG_B2_MU_E                                 = 90  ,
+  WIFIMACTX_HE_SIG_B2_OFDMA_E                              = 91  ,
+  WIFIMACTX_DELETE_CV_E                                    = 92  ,
+  WIFIMACTX_MU_UPLINK_COMMON_E                             = 93  ,
+  WIFIMACTX_MU_UPLINK_USER_SETUP_E                         = 94  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_E                          = 95  ,
+  WIFIMACTX_PHY_NAP_E                                      = 96  ,
+  WIFIMACTX_DEBUG_E                                        = 97  ,
+  WIFIPHYRX_ABORT_ACK_E                                    = 98  ,
+  WIFIPHYRX_GENERATED_CBF_DETAILS_E                        = 99  ,
+  WIFIPHYRX_RSSI_LEGACY_E                                  = 100  ,
+  WIFIPHYRX_RSSI_HT_E                                      = 101  ,
+  WIFIPHYRX_USER_INFO_E                                    = 102  ,
+  WIFIPHYRX_PKT_END_E                                      = 103  ,
+  WIFIPHYRX_DEBUG_E                                        = 104  ,
+  WIFIPHYRX_CBF_TRANSFER_DONE_E                            = 105  ,
+  WIFIPHYRX_CBF_TRANSFER_ABORT_E                           = 106  ,
+  WIFIPHYRX_L_SIG_A_E                                      = 107  ,
+  WIFIPHYRX_L_SIG_B_E                                      = 108  ,
+  WIFIPHYRX_HT_SIG_E                                       = 109  ,
+  WIFIPHYRX_VHT_SIG_A_E                                    = 110  ,
+  WIFIPHYRX_VHT_SIG_B_SU20_E                               = 111  ,
+  WIFIPHYRX_VHT_SIG_B_SU40_E                               = 112  ,
+  WIFIPHYRX_VHT_SIG_B_SU80_E                               = 113  ,
+  WIFIPHYRX_VHT_SIG_B_SU160_E                              = 114  ,
+  WIFIPHYRX_VHT_SIG_B_MU20_E                               = 115  ,
+  WIFIPHYRX_VHT_SIG_B_MU40_E                               = 116  ,
+  WIFIPHYRX_VHT_SIG_B_MU80_E                               = 117  ,
+  WIFIPHYRX_VHT_SIG_B_MU160_E                              = 118  ,
+  WIFIPHYRX_HE_SIG_A_SU_E                                  = 119  ,
+  WIFIPHYRX_HE_SIG_A_MU_DL_E                               = 120  ,
+  WIFIPHYRX_HE_SIG_A_MU_UL_E                               = 121  ,
+  WIFIPHYRX_HE_SIG_B1_MU_E                                 = 122  ,
+  WIFIPHYRX_HE_SIG_B2_MU_E                                 = 123  ,
+  WIFIPHYRX_HE_SIG_B2_OFDMA_E                              = 124  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_E                           = 125  ,
+  WIFIPHYRX_COMMON_USER_INFO_E                             = 126  ,
+  WIFIPHYRX_DATA_DONE_E                                    = 127  ,
+  WIFICOEX_TX_REQ_E                                        = 128  ,
+  WIFIDUMMY_E                                              = 129  ,
+  WIFIEXAMPLE_TLV_32_NAME_E                                = 130  ,
+  WIFIMPDU_LIMIT_E                                         = 131  ,
+  WIFINA_LENGTH_END_E                                      = 132  ,
+  WIFIOLE_BUF_STATUS_E                                     = 133  ,
+  WIFIPCU_PPDU_SETUP_DONE_E                                = 134  ,
+  WIFIPCU_PPDU_SETUP_END_E                                 = 135  ,
+  WIFIPCU_PPDU_SETUP_INIT_E                                = 136  ,
+  WIFIPCU_PPDU_SETUP_START_E                               = 137  ,
+  WIFIPDG_FES_SETUP_E                                      = 138  ,
+  WIFIPDG_RESPONSE_E                                       = 139  ,
+  WIFIPDG_TX_REQ_E                                         = 140  ,
+  WIFISCH_WAIT_INSTR_E                                     = 141  ,
+  WIFIMACTX_SWITCH_TO_MAIN_E                               = 142  ,
+  WIFIPHYTX_LINK_STATE_E                                   = 143  ,
+  WIFIAUX_PPDU_END_E                                       = 144  ,
+  WIFITQM_GEN_MPDU_LENGTH_LIST_E                           = 145  ,
+  WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E                    = 146  ,
+  WIFITQM_GEN_MPDUS_E                                      = 147  ,
+  WIFITQM_GEN_MPDUS_STATUS_E                               = 148  ,
+  WIFITQM_REMOVE_MPDU_E                                    = 149  ,
+  WIFITQM_REMOVE_MPDU_STATUS_E                             = 150  ,
+  WIFITQM_REMOVE_MSDU_E                                    = 151  ,
+  WIFITQM_REMOVE_MSDU_STATUS_E                             = 152  ,
+  WIFITQM_UPDATE_TX_MPDU_COUNT_E                           = 153  ,
+  WIFITQM_WRITE_CMD_E                                      = 154  ,
+  WIFIOFDMA_TRIGGER_DETAILS_E                              = 155  ,
+  WIFITX_DATA_E                                            = 156  ,
+  WIFITX_FES_SETUP_E                                       = 157  ,
+  WIFIRX_PACKET_E                                          = 158  ,
+  WIFIEXPECTED_RESPONSE_E                                  = 159  ,
+  WIFITX_MPDU_END_E                                        = 160  ,
+  WIFITX_MPDU_START_E                                      = 161  ,
+  WIFITX_MSDU_END_E                                        = 162  ,
+  WIFITX_MSDU_START_E                                      = 163  ,
+  WIFITX_SW_MODE_SETUP_E                                   = 164  ,
+  WIFITXPCU_BUFFER_STATUS_E                                = 165  ,
+  WIFITXPCU_USER_BUFFER_STATUS_E                           = 166  ,
+  WIFIDATA_TO_TIME_CONFIG_E                                = 167  ,
+  WIFIEXAMPLE_USER_TLV_32_E                                = 168  ,
+  WIFIMPDU_INFO_E                                          = 169  ,
+  WIFIPDG_USER_SETUP_E                                     = 170  ,
+  WIFITX_11AH_SETUP_E                                      = 171  ,
+  WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E                     = 172  ,
+  WIFITX_PEER_ENTRY_E                                      = 173  ,
+  WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E                       = 174  ,
+  WIFIEXAMPLE_USER_TLV_44_E                                = 175  ,
+  WIFITX_FLUSH_E                                           = 176  ,
+  WIFITX_FLUSH_REQ_E                                       = 177  ,
+  WIFITQM_WRITE_CMD_STATUS_E                               = 178  ,
+  WIFITQM_GET_MPDU_QUEUE_STATS_E                           = 179  ,
+  WIFITQM_GET_MSDU_FLOW_STATS_E                            = 180  ,
+  WIFIEXAMPLE_USER_CTLV_44_E                               = 181  ,
+  WIFITX_FES_STATUS_START_E                                = 182  ,
+  WIFITX_FES_STATUS_USER_PPDU_E                            = 183  ,
+  WIFITX_FES_STATUS_USER_RESPONSE_E                        = 184  ,
+  WIFITX_FES_STATUS_END_E                                  = 185  ,
+  WIFIRX_TRIG_INFO_E                                       = 186  ,
+  WIFIRXPCU_TX_SETUP_CLEAR_E                               = 187  ,
+  WIFIRX_FRAME_BITMAP_REQ_E                                = 188  ,
+  WIFIRX_FRAME_BITMAP_ACK_E                                = 189  ,
+  WIFICOEX_RX_STATUS_E                                     = 190  ,
+  WIFIRX_START_PARAM_E                                     = 191  ,
+  WIFIRX_PPDU_START_E                                      = 192  ,
+  WIFIRX_PPDU_END_E                                        = 193  ,
+  WIFIRX_MPDU_START_E                                      = 194  ,
+  WIFIRX_MPDU_END_E                                        = 195  ,
+  WIFIRX_MSDU_START_E                                      = 196  ,
+  WIFIRX_MSDU_END_E                                        = 197  ,
+  WIFIRX_ATTENTION_E                                       = 198  ,
+  WIFIRECEIVED_RESPONSE_INFO_E                             = 199  ,
+  WIFIRX_PHY_SLEEP_E                                       = 200  ,
+  WIFIRX_HEADER_E                                          = 201  ,
+  WIFIRX_PEER_ENTRY_E                                      = 202  ,
+  WIFIRX_FLUSH_E                                           = 203  ,
+  WIFIRX_RESPONSE_REQUIRED_INFO_E                          = 204  ,
+  WIFIRX_FRAMELESS_BAR_DETAILS_E                           = 205  ,
+  WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E                    = 206  ,
+  WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E                     = 207  ,
+  WIFITX_CBF_INFO_E                                        = 208  ,
+  WIFIPCU_PPDU_SETUP_USER_E                                = 209  ,
+  WIFIRX_MPDU_PCU_START_E                                  = 210  ,
+  WIFIRX_PM_INFO_E                                         = 211  ,
+  WIFIRX_USER_PPDU_END_E                                   = 212  ,
+  WIFIRX_PRE_PPDU_START_E                                  = 213  ,
+  WIFIRX_PREAMBLE_E                                        = 214  ,
+  WIFITX_FES_SETUP_COMPLETE_E                              = 215  ,
+  WIFITX_LAST_MPDU_FETCHED_E                               = 216  ,
+  WIFITXDMA_STOP_REQUEST_E                                 = 217  ,
+  WIFIRXPCU_SETUP_E                                        = 218  ,
+  WIFIRXPCU_USER_SETUP_E                                   = 219  ,
+  WIFITX_FES_STATUS_ACK_OR_BA_E                            = 220  ,
+  WIFITQM_ACKED_MPDU_E                                     = 221  ,
+  WIFICOEX_TX_RESP_E                                       = 222  ,
+  WIFICOEX_TX_STATUS_E                                     = 223  ,
+  WIFIMACTX_COEX_PHY_CTRL_E                                = 224  ,
+  WIFICOEX_STATUS_BROADCAST_E                              = 225  ,
+  WIFIRESPONSE_START_STATUS_E                              = 226  ,
+  WIFIRESPONSE_END_STATUS_E                                = 227  ,
+  WIFICRYPTO_STATUS_E                                      = 228  ,
+  WIFIRECEIVED_TRIGGER_INFO_E                              = 229  ,
+  WIFICOEX_TX_STOP_CTRL_E                                  = 230  ,
+  WIFIRX_PPDU_ACK_REPORT_E                                 = 231  ,
+  WIFIRX_PPDU_NO_ACK_REPORT_E                              = 232  ,
+  WIFISCH_COEX_STATUS_E                                    = 233  ,
+  WIFISCHEDULER_COMMAND_STATUS_E                           = 234  ,
+  WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E               = 235  ,
+  WIFITX_FES_STATUS_PROT_E                                 = 236  ,
+  WIFITX_FES_STATUS_START_PPDU_E                           = 237  ,
+  WIFITX_FES_STATUS_START_PROT_E                           = 238  ,
+  WIFITXPCU_PHYTX_DEBUG32_E                                = 239  ,
+  WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E                  = 240  ,
+  WIFITX_MPDU_COUNT_TRANSFER_END_E                         = 241  ,
+  WIFIWHO_ANCHOR_OFFSET_E                                  = 242  ,
+  WIFIWHO_ANCHOR_VALUE_E                                   = 243  ,
+  WIFIWHO_CCE_INFO_E                                       = 244  ,
+  WIFIWHO_COMMIT_E                                         = 245  ,
+  WIFIWHO_COMMIT_DONE_E                                    = 246  ,
+  WIFIWHO_FLUSH_E                                          = 247  ,
+  WIFIWHO_L2_LLC_E                                         = 248  ,
+  WIFIWHO_L2_PAYLOAD_E                                     = 249  ,
+  WIFIWHO_L3_CHECKSUM_E                                    = 250  ,
+  WIFIWHO_L3_INFO_E                                        = 251  ,
+  WIFIWHO_L4_CHECKSUM_E                                    = 252  ,
+  WIFIWHO_L4_INFO_E                                        = 253  ,
+  WIFIWHO_MSDU_E                                           = 254  ,
+  WIFIWHO_MSDU_MISC_E                                      = 255  ,
+  WIFIWHO_PACKET_DATA_E                                    = 256  ,
+  WIFIWHO_PACKET_HDR_E                                     = 257  ,
+  WIFIWHO_PPDU_END_E                                       = 258  ,
+  WIFIWHO_PPDU_START_E                                     = 259  ,
+  WIFIWHO_TSO_E                                            = 260  ,
+  WIFIWHO_WMAC_HEADER_PV0_E                                = 261  ,
+  WIFIWHO_WMAC_HEADER_PV1_E                                = 262  ,
+  WIFIWHO_WMAC_IV_E                                        = 263  ,
+  WIFIMPDU_INFO_END_E                                      = 264  ,
+  WIFIMPDU_INFO_BITMAP_E                                   = 265  ,
+  WIFITX_QUEUE_EXTENSION_E                                 = 266  ,
+  WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E                  = 267  ,
+  WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E                    = 268  ,
+  WIFITQM_ACKED_MPDU_STATUS_E                              = 269  ,
+  WIFITQM_ADD_MSDU_STATUS_E                                = 270  ,
+  WIFITQM_LIST_GEN_DONE_E                                  = 271  ,
+  WIFIWHO_TERMINATE_E                                      = 272  ,
+  WIFITX_LAST_MPDU_END_E                                   = 273  ,
+  WIFITX_CV_DATA_E                                         = 274  ,
+  WIFIPPDU_TX_END_E                                        = 275  ,
+  WIFIPROT_TX_END_E                                        = 276  ,
+  WIFIMPDU_INFO_GLOBAL_END_E                               = 277  ,
+  WIFITQM_SCH_INSTR_GLOBAL_END_E                           = 278  ,
+  WIFIRX_PPDU_END_USER_STATS_E                             = 279  ,
+  WIFIRX_PPDU_END_USER_STATS_EXT_E                         = 280  ,
+  WIFIREO_GET_QUEUE_STATS_E                                = 281  ,
+  WIFIREO_FLUSH_QUEUE_E                                    = 282  ,
+  WIFIREO_FLUSH_CACHE_E                                    = 283  ,
+  WIFIREO_UNBLOCK_CACHE_E                                  = 284  ,
+  WIFIREO_GET_QUEUE_STATS_STATUS_E                         = 285  ,
+  WIFIREO_FLUSH_QUEUE_STATUS_E                             = 286  ,
+  WIFIREO_FLUSH_CACHE_STATUS_E                             = 287  ,
+  WIFIREO_UNBLOCK_CACHE_STATUS_E                           = 288  ,
+  WIFITQM_FLUSH_CACHE_E                                    = 289  ,
+  WIFITQM_UNBLOCK_CACHE_E                                  = 290  ,
+  WIFITQM_FLUSH_CACHE_STATUS_E                             = 291  ,
+  WIFITQM_UNBLOCK_CACHE_STATUS_E                           = 292  ,
+  WIFIRX_PPDU_END_STATUS_DONE_E                            = 293  ,
+  WIFIRX_STATUS_BUFFER_DONE_E                              = 294  ,
+  WIFISCHEDULER_MLO_SW_MSG_STATUS_E                        = 295  ,
+  WIFISCHEDULER_TXOP_DURATION_TRIGGER_E                    = 296  ,
+  WIFITX_DATA_SYNC_E                                       = 297  ,
+  WIFIPHYRX_CBF_READ_REQUEST_ACK_E                         = 298  ,
+  WIFITQM_GET_MPDU_HEAD_INFO_E                             = 299  ,
+  WIFITQM_SYNC_CMD_E                                       = 300  ,
+  WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E                      = 301  ,
+  WIFITQM_SYNC_CMD_STATUS_E                                = 302  ,
+  WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E             = 303  ,
+  WIFIREO_FLUSH_TIMEOUT_LIST_E                             = 305  ,
+  WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E                      = 306  ,
+  WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E            = 307  ,
+  WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E          = 308  ,
+  WIFIEXAMPLE_USER_TLV_32_NAME_E                           = 309  ,
+  WIFIRX_PPDU_START_USER_INFO_E                            = 310  ,
+  WIFIRX_RING_MASK_E                                       = 311  ,
+  WIFICOEX_MAC_NAP_E                                       = 312  ,
+  WIFIRXPCU_PPDU_END_INFO_E                                = 313  ,
+  WIFIWHO_MESH_CONTROL_E                                   = 314  ,
+  WIFIPDG_SW_MODE_BW_START_E                               = 315  ,
+  WIFIPDG_SW_MODE_BW_END_E                                 = 316  ,
+  WIFIPDG_WAIT_FOR_MAC_REQUEST_E                           = 317  ,
+  WIFIPDG_WAIT_FOR_PHY_REQUEST_E                           = 318  ,
+  WIFISCHEDULER_END_E                                      = 319  ,
+  WIFIRX_PPDU_START_DROPPED_E                              = 320  ,
+  WIFIRX_PPDU_END_DROPPED_E                                = 321  ,
+  WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E                    = 322  ,
+  WIFIRX_MPDU_START_DROPPED_E                              = 323  ,
+  WIFIRX_MSDU_START_DROPPED_E                              = 324  ,
+  WIFIRX_MSDU_END_DROPPED_E                                = 325  ,
+  WIFIRX_MPDU_END_DROPPED_E                                = 326  ,
+  WIFIRX_ATTENTION_DROPPED_E                               = 327  ,
+  WIFITXPCU_USER_SETUP_E                                   = 328  ,
+  WIFIRXPCU_USER_SETUP_EXT_E                               = 329  ,
+  WIFICMD_PART_0_END_E                                     = 330  ,
+  WIFIMACTX_SYNTH_ON_E                                     = 331  ,
+  WIFISCH_CRITICAL_TLV_REFERENCE_E                         = 332  ,
+  WIFITQM_MPDU_GLOBAL_START_E                              = 333  ,
+  WIFIEXAMPLE_TLV_32_E                                     = 334  ,
+  WIFITQM_UPDATE_TX_MSDU_FLOW_E                            = 335  ,
+  WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E                      = 336  ,
+  WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E                     = 337  ,
+  WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E               = 338  ,
+  WIFIREO_UPDATE_RX_REO_QUEUE_E                            = 339  ,
+  WIFITQM_2_SCH_MPDU_AVAILABLE_E                           = 341  ,
+  WIFIPDG_TRIG_RESPONSE_E                                  = 342  ,
+  WIFITRIGGER_RESPONSE_TX_DONE_E                           = 343  ,
+  WIFIABORT_FROM_PHYRX_DETAILS_E                           = 344  ,
+  WIFISCH_TQM_CMD_WRAPPER_E                                = 345  ,
+  WIFIMPDUS_AVAILABLE_E                                    = 346  ,
+  WIFIRECEIVED_RESPONSE_INFO_PART2_E                       = 347  ,
+  WIFIPHYRX_TX_START_TIMING_E                              = 348  ,
+  WIFITXPCU_PREAMBLE_DONE_E                                = 349  ,
+  WIFINDP_PREAMBLE_DONE_E                                  = 350  ,
+  WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E                       = 351  ,
+  WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E                      = 352  ,
+  WIFIMACTX_CLEAR_PREV_TX_INFO_E                           = 353  ,
+  WIFITX_PUNCTURE_SETUP_E                                  = 354  ,
+  WIFIR2R_STATUS_END_E                                     = 355  ,
+  WIFIMACTX_PREFETCH_CV_COMMON_E                           = 356  ,
+  WIFIEND_OF_FLUSH_MARKER_E                                = 357  ,
+  WIFIMACTX_MU_UPLINK_COMMON_PUNC_E                        = 358  ,
+  WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E                    = 359  ,
+  WIFIRECEIVED_RESPONSE_USER_7_0_E                         = 360  ,
+  WIFIRECEIVED_RESPONSE_USER_15_8_E                        = 361  ,
+  WIFIRECEIVED_RESPONSE_USER_23_16_E                       = 362  ,
+  WIFIRECEIVED_RESPONSE_USER_31_24_E                       = 363  ,
+  WIFIRECEIVED_RESPONSE_USER_36_32_E                       = 364  ,
+  WIFITX_LOOPBACK_SETUP_E                                  = 365  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E                = 366  ,
+  WIFISCH_WAIT_INSTR_TX_PATH_E                             = 367  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E                    = 368  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E             = 369  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E               = 370  ,
+  WIFITX_WUR_DATA_E                                        = 371  ,
+  WIFIRX_PPDU_END_START_E                                  = 372  ,
+  WIFIRX_PPDU_END_MIDDLE_E                                 = 373  ,
+  WIFIRX_PPDU_END_LAST_E                                   = 374  ,
+  WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E                   = 375  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E              = 376  ,
+  WIFISRP_INFO_E                                           = 377  ,
+  WIFIOBSS_SR_INFO_E                                       = 378  ,
+  WIFISCHEDULER_SW_MSG_STATUS_E                            = 379  ,
+  WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E                  = 380  ,
+  WIFIRXPCU_SETUP_COMPLETE_E                               = 381  ,
+  WIFIMACTX_MCC_SWITCH_E                                   = 382  ,
+  WIFIMACTX_MCC_SWITCH_BACK_E                              = 383  ,
+  WIFIPHYTX_MCC_SWITCH_ACK_E                               = 384  ,
+  WIFIPHYTX_MCC_SWITCH_BACK_ACK_E                          = 385  ,
+  WIFIPHYTX_EMLSR_PRE_SWITCH_ACK_E                         = 386  ,
+  WIFILMR_TX_END_E                                         = 389  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E            = 390  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E              = 391  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E              = 392  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E          = 393  ,
+  WIFISCH_TLV_WRAPPER_E                                    = 394  ,
+  WIFISCHEDULER_STATUS_WRAPPER_E                           = 395  ,
+  WIFIMPDU_INFO_6X_E                                       = 396  ,
+  WIFIMACTX___RESERVED_G_0013                              = 397  ,
+  WIFIMACTX_U_SIG_EHT_SU_MU_E                              = 398  ,
+  WIFIMACTX_U_SIG_EHT_TB_E                                 = 399  ,
+  WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E                          = 400  ,
+  WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E                          = 401  ,
+  WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E                          = 402  ,
+  WIFIPHYRX_U_SIG_EHT_SU_MU_E                              = 403  ,
+  WIFIPHYRX_U_SIG_EHT_TB_E                                 = 404  ,
+  WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E                          = 405  ,
+  WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E                      = 406  ,
+  WIFITX_PUNCTURE_6PATTERNS_SETUP_E                        = 407  ,
+  WIFIMACRX_LMR_READ_REQUEST_E                             = 408  ,
+  WIFIMACRX_LMR_DATA_REQUEST_E                             = 409  ,
+  WIFIPHYRX_LMR_TRANSFER_DONE_E                            = 410  ,
+  WIFIPHYRX_LMR_TRANSFER_ABORT_E                           = 411  ,
+  WIFIPHYRX_LMR_READ_REQUEST_ACK_E                         = 412  ,
+  WIFIMACRX_SECURE_LTF_SEQ_PTR_E                           = 413  ,
+  WIFIPHYRX_USER_INFO_MU_UL_E                              = 414  ,
+  WIFIMPDU_QUEUE_OVERVIEW_E                                = 415  ,
+  WIFISCHEDULER_NAV_INFO_E                                 = 416  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E                = 417  ,
+  WIFILMR_PEER_ENTRY_E                                     = 418  ,
+  WIFILMR_MPDU_START_E                                     = 419  ,
+  WIFILMR_DATA_E                                           = 420  ,
+  WIFILMR_MPDU_END_E                                       = 421  ,
+  WIFIREO_GET_QUEUE_1K_STATS_STATUS_E                      = 422  ,
+  WIFIRX_FRAME_1K_BITMAP_ACK_E                             = 423  ,
+  WIFITX_FES_STATUS_1K_BA_E                                = 424  ,
+  WIFITQM_ACKED_1K_MPDU_E                                  = 425  ,
+  WIFIMACRX_INBSS_OBSS_IND_E                               = 426  ,
+  WIFIPHYRX_LOCATION_E                                     = 427  ,
+  WIFIMLO_TX_NOTIFICATION_SU_E                             = 428  ,
+  WIFIMLO_TX_NOTIFICATION_MU_E                             = 429  ,
+  WIFIMLO_TX_REQ_SU_E                                      = 430  ,
+  WIFIMLO_TX_REQ_MU_E                                      = 431  ,
+  WIFIMLO_TX_RESP_E                                        = 432  ,
+  WIFIMLO_RX_NOTIFICATION_E                                = 433  ,
+  WIFIMLO_BKOFF_TRUNC_REQ_E                                = 434  ,
+  WIFIMLO_TBTT_NOTIFICATION_E                              = 435  ,
+  WIFIMLO_MESSAGE_E                                        = 436  ,
+  WIFIMLO_TS_SYNC_MSG_E                                    = 437  ,
+  WIFIMLO_FES_SETUP_E                                      = 438  ,
+  WIFIMLO_PDG_FES_SETUP_SU_E                               = 439  ,
+  WIFIMLO_PDG_FES_SETUP_MU_E                               = 440  ,
+  WIFIMPDU_INFO_1K_BITMAP_E                                = 441  ,
+  WIFIMON_BUFFER_ADDR_E                                    = 442  ,
+  WIFITX_FRAG_STATE_E                                      = 443  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E             = 444  ,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E              = 445  ,
+  WIFIMACTX_EHT_SIG_USR_OFDMA_E                            = 446  ,
+  WIFIPHYRX_EHT_SIG_CMN_PUNC_E                             = 448  ,
+  WIFIPHYRX_EHT_SIG_CMN_OFDMA_E                            = 450  ,
+  WIFIPHYRX_EHT_SIG_USR_OFDMA_E                            = 454  ,
+  WIFIPHYRX_PKT_END_PART1_E                                = 456  ,
+  WIFIMACTX_EXPECT_NDP_RECEPTION_E                         = 457  ,
+  WIFIMACTX_SECURE_LTF_SEQ_PTR_E                           = 458  ,
+  WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E                         = 460  ,
+  WIFIPHYRX___RESERVED_G_0014                              = 461  ,
+  WIFIPHYTX_LOCATION_E                                     = 462  ,
+  WIFIPHYTX___RESERVED_G_0014                              = 463  ,
+  WIFIMACTX_EHT_SIG_USR_SU_E                               = 466  ,
+  WIFIMACTX_EHT_SIG_USR_MU_MIMO_E                          = 467  ,
+  WIFIPHYRX_EHT_SIG_USR_SU_E                               = 468  ,
+  WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E                          = 469  ,
+  WIFIPHYRX_GENERIC_U_SIG_E                                = 470  ,
+  WIFIPHYRX_GENERIC_EHT_SIG_E                              = 471  ,
+  WIFIOVERWRITE_RESP_START_E                               = 472  ,
+  WIFIOVERWRITE_RESP_PREAMBLE_INFO_E                       = 473  ,
+  WIFIOVERWRITE_RESP_FRAME_INFO_E                          = 474  ,
+  WIFIOVERWRITE_RESP_END_E                                 = 475  ,
+  WIFIRXPCU_EARLY_RX_INDICATION_E                          = 476  ,
+  WIFIMON_DROP_E                                           = 477  ,
+  WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E                       = 478  ,
+  WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E                   = 479  ,
+  WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E                     = 480  ,
+  WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E                   = 481  ,
+  WIFIMACTX_PREFETCH_CV_DMA_E                              = 482  ,
+  WIFIMACTX_PREFETCH_CV_PER_USER_E                         = 483  ,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E          = 484  ,
+  WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E                      = 485  ,
+  WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E                    = 486  ,
+  WIFIRANGING_USER_DETAILS_E                               = 487  ,
+  WIFIPHYTX_CV_CORR_STATUS_E                               = 488  ,
+  WIFIPHYTX_CV_CORR_COMMON_E                               = 489  ,
+  WIFIPHYTX_CV_CORR_USER_E                                 = 490  ,
+  WIFIMACTX_CV_CORR_COMMON_E                               = 491  ,
+  WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E                       = 492  ,
+  WIFIBW_PUNCTURE_EVAL_WRAPPER_E                           = 493  ,
+  WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E                      = 494  ,
+  WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E                      = 495  ,
+  WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E                      = 496  ,
+  WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E                  = 497  ,
+  WIFIRX_PPDU_END_USER_STATS_EXT2_E                        = 498  ,
+  WIFIFW2SW_MON_E                                          = 499  ,
+  WIFIWSI_DIRECT_MESSAGE_E                                 = 500  ,
+  WIFIMACTX_EMLSR_PRE_SWITCH_E                             = 501  ,
+  WIFIMACTX_EMLSR_SWITCH_E                                 = 502  ,
+  WIFIMACTX_EMLSR_SWITCH_BACK_E                            = 503  ,
+  WIFIPHYTX_EMLSR_SWITCH_ACK_E                             = 504  ,
+  WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E                        = 505  ,
+  WIFISPARE_REUSE_TAG_0_E                                  = 506  ,
+  WIFISPARE_REUSE_TAG_1_E                                  = 507  ,
+  WIFISPARE_REUSE_TAG_2_E                                  = 508  ,
+  WIFISPARE_REUSE_TAG_3_E                                  = 509
+} tlv_tag_def__e;
+
+#endif
diff --git a/hw/peach/v1/tx_cbf_info.h b/hw/peach/v1/tx_cbf_info.h
new file mode 100644
index 000000000000..704e096b629c
--- /dev/null
+++ b/hw/peach/v1/tx_cbf_info.h
@@ -0,0 +1,458 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_CBF_INFO_H_
+#define _TX_CBF_INFO_H_
+
+#define NUM_OF_DWORDS_TX_CBF_INFO 15
+
+struct tx_cbf_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t sw_peer_id                                              : 16,
+                      pre_cbf_duration                                        : 16;
+             uint32_t brpoll_info_valid                                       :  1,
+                      trigger_brpoll_info_valid                               :  1,
+                      npda_info_11ac_valid                                    :  1,
+                      npda_info_11ax_valid                                    :  1,
+                      dot11ax_su_extended                                     :  1,
+                      bandwidth                                               :  3,
+                      brpoll_info                                             :  8,
+                      cbf_response_table_base_index                           :  8,
+                      peer_index                                              :  3,
+                      pkt_type                                                :  4,
+                      txop_duration_all_ones                                  :  1;
+             uint32_t trigger_brpoll_common_info_15_0                         : 16,
+                      trigger_brpoll_common_info_31_16                        : 16;
+             uint32_t trigger_brpoll_user_info_15_0                           : 16,
+                      trigger_brpoll_user_info_31_16                          : 16;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr1_47_32                                             : 16,
+                      addr2_15_0                                              : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t addr3_47_32                                             : 16,
+                      sta_partial_aid                                         : 11,
+                      reserved_8a                                             :  4,
+                      cbf_resp_pwr_mgmt                                       :  1;
+             uint32_t group_id                                                :  6,
+                      rssi_comb                                               :  8,
+                      reserved_9a                                             :  2,
+                      vht_ndpa_sta_info                                       : 16;
+             uint32_t he_eht_sta_info_15_0                                    : 16,
+                      he_eht_sta_info_31_16                                   : 16;
+             uint32_t dot11ax_received_format_indication                      :  1,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      reserved_11a                                            :  8;
+             uint32_t sw_response_frame_length                                : 16,
+                      sw_response_tlv_from_crypto                             :  1,
+                      wait_sifs_config_valid                                  :  1,
+                      wait_sifs                                               :  2,
+                      __reserved_g_0005                                                 :  1,
+                      secure                                                  :  1,
+                      tb___reserved_g_0005_response_required                            :  2,
+                      emlsr_main_tlv_if                                       :  1,
+                      reserved_12a                                            :  1,
+                      u_sig_puncture_pattern_encoding                         :  6;
+             uint32_t dot11be_puncture_bitmap                                 : 16,
+                      dot11be_response                                        :  1,
+                      punctured_response                                      :  1,
+                      npda_info_11be_valid                                    :  1,
+                      eht_duplicate_mode                                      :  2,
+                      reserved_13a                                            : 11;
+             uint32_t eht_sta_info_39_32                                      :  8,
+                      reserved_14a                                            : 24;
+#else
+             uint32_t pre_cbf_duration                                        : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t txop_duration_all_ones                                  :  1,
+                      pkt_type                                                :  4,
+                      peer_index                                              :  3,
+                      cbf_response_table_base_index                           :  8,
+                      brpoll_info                                             :  8,
+                      bandwidth                                               :  3,
+                      dot11ax_su_extended                                     :  1,
+                      npda_info_11ax_valid                                    :  1,
+                      npda_info_11ac_valid                                    :  1,
+                      trigger_brpoll_info_valid                               :  1,
+                      brpoll_info_valid                                       :  1;
+             uint32_t trigger_brpoll_common_info_31_16                        : 16,
+                      trigger_brpoll_common_info_15_0                         : 16;
+             uint32_t trigger_brpoll_user_info_31_16                          : 16,
+                      trigger_brpoll_user_info_15_0                           : 16;
+             uint32_t addr1_31_0                                              : 32;
+             uint32_t addr2_15_0                                              : 16,
+                      addr1_47_32                                             : 16;
+             uint32_t addr2_47_16                                             : 32;
+             uint32_t addr3_31_0                                              : 32;
+             uint32_t cbf_resp_pwr_mgmt                                       :  1,
+                      reserved_8a                                             :  4,
+                      sta_partial_aid                                         : 11,
+                      addr3_47_32                                             : 16;
+             uint32_t vht_ndpa_sta_info                                       : 16,
+                      reserved_9a                                             :  2,
+                      rssi_comb                                               :  8,
+                      group_id                                                :  6;
+             uint32_t he_eht_sta_info_31_16                                   : 16,
+                      he_eht_sta_info_15_0                                    : 16;
+             uint32_t reserved_11a                                            :  8,
+                      dot11ax_dl_ul_flag                                      :  1,
+                      dot11ax_received_ext_ru_size                            :  4,
+                      dot11ax_received_doppler_indication                     :  1,
+                      dot11ax_received_dcm                                    :  1,
+                      dot11ax_received_coding                                 :  1,
+                      dot11ax_received_ltf_size                               :  2,
+                      dot11ax_received_cp_size                                :  2,
+                      dot11ax_received_spatial_reuse                          :  4,
+                      dot11ax_received_bss_color_id                           :  6,
+                      dot11ax_received_dl_ul_flag                             :  1,
+                      dot11ax_received_format_indication                      :  1;
+             uint32_t u_sig_puncture_pattern_encoding                         :  6,
+                      reserved_12a                                            :  1,
+                      emlsr_main_tlv_if                                       :  1,
+                      tb___reserved_g_0005_response_required                            :  2,
+                      secure                                                  :  1,
+                      __reserved_g_0005                                                 :  1,
+                      wait_sifs                                               :  2,
+                      wait_sifs_config_valid                                  :  1,
+                      sw_response_tlv_from_crypto                             :  1,
+                      sw_response_frame_length                                : 16;
+             uint32_t reserved_13a                                            : 11,
+                      eht_duplicate_mode                                      :  2,
+                      npda_info_11be_valid                                    :  1,
+                      punctured_response                                      :  1,
+                      dot11be_response                                        :  1,
+                      dot11be_puncture_bitmap                                 : 16;
+             uint32_t reserved_14a                                            : 24,
+                      eht_sta_info_39_32                                      :  8;
+#endif
+};
+
+#define TX_CBF_INFO_SW_PEER_ID_OFFSET                                               0x00000000
+#define TX_CBF_INFO_SW_PEER_ID_LSB                                                  0
+#define TX_CBF_INFO_SW_PEER_ID_MSB                                                  15
+#define TX_CBF_INFO_SW_PEER_ID_MASK                                                 0x0000ffff
+
+#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET                                         0x00000000
+#define TX_CBF_INFO_PRE_CBF_DURATION_LSB                                            16
+#define TX_CBF_INFO_PRE_CBF_DURATION_MSB                                            31
+#define TX_CBF_INFO_PRE_CBF_DURATION_MASK                                           0xffff0000
+
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET                                        0x00000004
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB                                           0
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB                                           0
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK                                          0x00000001
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET                                0x00000004
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB                                   1
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB                                   1
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK                                  0x00000002
+
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET                                     0x00000004
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB                                        2
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB                                        2
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK                                       0x00000004
+
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET                                     0x00000004
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB                                        3
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB                                        3
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK                                       0x00000008
+
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET                                      0x00000004
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB                                         4
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB                                         4
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK                                        0x00000010
+
+#define TX_CBF_INFO_BANDWIDTH_OFFSET                                                0x00000004
+#define TX_CBF_INFO_BANDWIDTH_LSB                                                   5
+#define TX_CBF_INFO_BANDWIDTH_MSB                                                   7
+#define TX_CBF_INFO_BANDWIDTH_MASK                                                  0x000000e0
+
+#define TX_CBF_INFO_BRPOLL_INFO_OFFSET                                              0x00000004
+#define TX_CBF_INFO_BRPOLL_INFO_LSB                                                 8
+#define TX_CBF_INFO_BRPOLL_INFO_MSB                                                 15
+#define TX_CBF_INFO_BRPOLL_INFO_MASK                                                0x0000ff00
+
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET                            0x00000004
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB                               16
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB                               23
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK                              0x00ff0000
+
+#define TX_CBF_INFO_PEER_INDEX_OFFSET                                               0x00000004
+#define TX_CBF_INFO_PEER_INDEX_LSB                                                  24
+#define TX_CBF_INFO_PEER_INDEX_MSB                                                  26
+#define TX_CBF_INFO_PEER_INDEX_MASK                                                 0x07000000
+
+#define TX_CBF_INFO_PKT_TYPE_OFFSET                                                 0x00000004
+#define TX_CBF_INFO_PKT_TYPE_LSB                                                    27
+#define TX_CBF_INFO_PKT_TYPE_MSB                                                    30
+#define TX_CBF_INFO_PKT_TYPE_MASK                                                   0x78000000
+
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET                                   0x00000004
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB                                      31
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB                                      31
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK                                     0x80000000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET                          0x00000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB                             0
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB                             15
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK                            0x0000ffff
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET                         0x00000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB                            16
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB                            31
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK                           0xffff0000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET                            0x0000000c
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB                               0
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB                               15
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK                              0x0000ffff
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET                           0x0000000c
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB                              16
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB                              31
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK                             0xffff0000
+
+#define TX_CBF_INFO_ADDR1_31_0_OFFSET                                               0x00000010
+#define TX_CBF_INFO_ADDR1_31_0_LSB                                                  0
+#define TX_CBF_INFO_ADDR1_31_0_MSB                                                  31
+#define TX_CBF_INFO_ADDR1_31_0_MASK                                                 0xffffffff
+
+#define TX_CBF_INFO_ADDR1_47_32_OFFSET                                              0x00000014
+#define TX_CBF_INFO_ADDR1_47_32_LSB                                                 0
+#define TX_CBF_INFO_ADDR1_47_32_MSB                                                 15
+#define TX_CBF_INFO_ADDR1_47_32_MASK                                                0x0000ffff
+
+#define TX_CBF_INFO_ADDR2_15_0_OFFSET                                               0x00000014
+#define TX_CBF_INFO_ADDR2_15_0_LSB                                                  16
+#define TX_CBF_INFO_ADDR2_15_0_MSB                                                  31
+#define TX_CBF_INFO_ADDR2_15_0_MASK                                                 0xffff0000
+
+#define TX_CBF_INFO_ADDR2_47_16_OFFSET                                              0x00000018
+#define TX_CBF_INFO_ADDR2_47_16_LSB                                                 0
+#define TX_CBF_INFO_ADDR2_47_16_MSB                                                 31
+#define TX_CBF_INFO_ADDR2_47_16_MASK                                                0xffffffff
+
+#define TX_CBF_INFO_ADDR3_31_0_OFFSET                                               0x0000001c
+#define TX_CBF_INFO_ADDR3_31_0_LSB                                                  0
+#define TX_CBF_INFO_ADDR3_31_0_MSB                                                  31
+#define TX_CBF_INFO_ADDR3_31_0_MASK                                                 0xffffffff
+
+#define TX_CBF_INFO_ADDR3_47_32_OFFSET                                              0x00000020
+#define TX_CBF_INFO_ADDR3_47_32_LSB                                                 0
+#define TX_CBF_INFO_ADDR3_47_32_MSB                                                 15
+#define TX_CBF_INFO_ADDR3_47_32_MASK                                                0x0000ffff
+
+#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET                                          0x00000020
+#define TX_CBF_INFO_STA_PARTIAL_AID_LSB                                             16
+#define TX_CBF_INFO_STA_PARTIAL_AID_MSB                                             26
+#define TX_CBF_INFO_STA_PARTIAL_AID_MASK                                            0x07ff0000
+
+#define TX_CBF_INFO_RESERVED_8A_OFFSET                                              0x00000020
+#define TX_CBF_INFO_RESERVED_8A_LSB                                                 27
+#define TX_CBF_INFO_RESERVED_8A_MSB                                                 30
+#define TX_CBF_INFO_RESERVED_8A_MASK                                                0x78000000
+
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET                                        0x00000020
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB                                           31
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB                                           31
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK                                          0x80000000
+
+#define TX_CBF_INFO_GROUP_ID_OFFSET                                                 0x00000024
+#define TX_CBF_INFO_GROUP_ID_LSB                                                    0
+#define TX_CBF_INFO_GROUP_ID_MSB                                                    5
+#define TX_CBF_INFO_GROUP_ID_MASK                                                   0x0000003f
+
+#define TX_CBF_INFO_RSSI_COMB_OFFSET                                                0x00000024
+#define TX_CBF_INFO_RSSI_COMB_LSB                                                   6
+#define TX_CBF_INFO_RSSI_COMB_MSB                                                   13
+#define TX_CBF_INFO_RSSI_COMB_MASK                                                  0x00003fc0
+
+#define TX_CBF_INFO_RESERVED_9A_OFFSET                                              0x00000024
+#define TX_CBF_INFO_RESERVED_9A_LSB                                                 14
+#define TX_CBF_INFO_RESERVED_9A_MSB                                                 15
+#define TX_CBF_INFO_RESERVED_9A_MASK                                                0x0000c000
+
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET                                        0x00000024
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB                                           16
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB                                           31
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK                                          0xffff0000
+
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET                                     0x00000028
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB                                        0
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB                                        15
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK                                       0x0000ffff
+
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET                                    0x00000028
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB                                       16
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB                                       31
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK                                      0xffff0000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET                       0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB                          0
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB                          0
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK                         0x00000001
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET                              0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB                                 1
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB                                 1
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK                                0x00000002
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET                            0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB                               2
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB                               7
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK                              0x000000fc
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET                           0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB                              8
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB                              11
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK                             0x00000f00
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET                                 0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB                                    12
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB                                    13
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK                                   0x00003000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET                                0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB                                   14
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB                                   15
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK                                  0x0000c000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET                                  0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB                                     16
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB                                     16
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK                                    0x00010000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET                                     0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB                                        17
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB                                        17
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK                                       0x00020000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET                      0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB                         18
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB                         18
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK                        0x00040000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET                             0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB                                19
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB                                22
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK                               0x00780000
+
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET                                       0x0000002c
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB                                          23
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB                                          23
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK                                         0x00800000
+
+#define TX_CBF_INFO_RESERVED_11A_OFFSET                                             0x0000002c
+#define TX_CBF_INFO_RESERVED_11A_LSB                                                24
+#define TX_CBF_INFO_RESERVED_11A_MSB                                                31
+#define TX_CBF_INFO_RESERVED_11A_MASK                                               0xff000000
+
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET                                 0x00000030
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB                                    0
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB                                    15
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK                                   0x0000ffff
+
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET                              0x00000030
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB                                 16
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB                                 16
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK                                0x00010000
+
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET                                   0x00000030
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB                                      17
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB                                      17
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK                                     0x00020000
+
+#define TX_CBF_INFO_WAIT_SIFS_OFFSET                                                0x00000030
+#define TX_CBF_INFO_WAIT_SIFS_LSB                                                   18
+#define TX_CBF_INFO_WAIT_SIFS_MSB                                                   19
+#define TX_CBF_INFO_WAIT_SIFS_MASK                                                  0x000c0000
+
+#define TX_CBF_INFO_SECURE_OFFSET                                                   0x00000030
+#define TX_CBF_INFO_SECURE_LSB                                                      21
+#define TX_CBF_INFO_SECURE_MSB                                                      21
+#define TX_CBF_INFO_SECURE_MASK                                                     0x00200000
+
+#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET                             0x00000030
+#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB                                22
+#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB                                23
+#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK                               0x00c00000
+
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_OFFSET                                        0x00000030
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_LSB                                           24
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MSB                                           24
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MASK                                          0x01000000
+
+#define TX_CBF_INFO_RESERVED_12A_OFFSET                                             0x00000030
+#define TX_CBF_INFO_RESERVED_12A_LSB                                                25
+#define TX_CBF_INFO_RESERVED_12A_MSB                                                25
+#define TX_CBF_INFO_RESERVED_12A_MASK                                               0x02000000
+
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET                          0x00000030
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB                             26
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB                             31
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK                            0xfc000000
+
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET                                  0x00000034
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB                                     0
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB                                     15
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK                                    0x0000ffff
+
+#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET                                         0x00000034
+#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB                                            16
+#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB                                            16
+#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK                                           0x00010000
+
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET                                       0x00000034
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB                                          17
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB                                          17
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK                                         0x00020000
+
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET                                     0x00000034
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB                                        18
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB                                        18
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK                                       0x00040000
+
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET                                       0x00000034
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB                                          19
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB                                          20
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK                                         0x00180000
+
+#define TX_CBF_INFO_RESERVED_13A_OFFSET                                             0x00000034
+#define TX_CBF_INFO_RESERVED_13A_LSB                                                21
+#define TX_CBF_INFO_RESERVED_13A_MSB                                                31
+#define TX_CBF_INFO_RESERVED_13A_MASK                                               0xffe00000
+
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET                                       0x00000038
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB                                          0
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB                                          7
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK                                         0x000000ff
+
+#define TX_CBF_INFO_RESERVED_14A_OFFSET                                             0x00000038
+#define TX_CBF_INFO_RESERVED_14A_LSB                                                8
+#define TX_CBF_INFO_RESERVED_14A_MSB                                                31
+#define TX_CBF_INFO_RESERVED_14A_MASK                                               0xffffff00
+
+#endif
diff --git a/hw/peach/v1/tx_fes_setup.h b/hw/peach/v1/tx_fes_setup.h
new file mode 100644
index 000000000000..c141ea42f748
--- /dev/null
+++ b/hw/peach/v1/tx_fes_setup.h
@@ -0,0 +1,511 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_SETUP_H_
+#define _TX_FES_SETUP_H_
+
+#define NUM_OF_DWORDS_TX_FES_SETUP 10
+
+struct tx_fes_setup {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t schedule_id                                             : 32;
+             uint32_t fes_in_11ax_trigger_response_config                     :  1,
+                      bo_based_tid_aggregation_limit                          :  4,
+                      __reserved_g_0005                                                 :  1,
+                      expect_i2r_lmr                                          :  1,
+                      transmit_start_reason                                   :  3,
+                      use_alt_power_sr                                        :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_pd_based_transmit_status                           :  1,
+                      puncture_from_all_allowed_modes                         :  1,
+                      schedule_cmd_ring_id                                    :  5,
+                      fes_control_mode                                        :  2,
+                      number_of_users                                         :  6,
+                      mu_type                                                 :  1,
+                      ofdma_triggered_response                                :  1,
+                      response_to_response_cmd                                :  1;
+             uint32_t schedule_try                                            :  4,
+                      ndp_frame                                               :  2,
+                      txbf                                                    :  1,
+                      allow_txop_exceed_in_1st_pkt                            :  1,
+                      ignore_bw_available                                     :  1,
+                      ignore_tbtt                                             :  1,
+                      static_bandwidth                                        :  3,
+                      set_txop_duration_all_ones                              :  1,
+                      transmission_contains_mu_rts                            :  1,
+                      bw_restricted_frames_embedded                           :  1,
+                      ast_index                                               : 16;
+             uint32_t cv_id                                                   :  8,
+                      trigger_resp_txpdu_ppdu_boundary                        :  2,
+                      rxpcu_setup_complete_present                            :  1,
+                      rbo_must_have_data_user_limit                           :  4,
+                      mu_ndp                                                  :  1,
+                      bf_type                                                 :  2,
+                      cbf_nc_index_mask                                       :  1,
+                      cbf_nc_index                                            :  3,
+                      cbf_nr_index_mask                                       :  1,
+                      cbf_nr_index                                            :  3,
+                      secure___reserved_g_0005_ista                                     :  1,
+                      ndpa                                                    :  1,
+                      wait_sifs                                               :  2,
+                      cbf_feedback_type_mask                                  :  1,
+                      cbf_feedback_type                                       :  1;
+             uint32_t cbf_sounding_token                                      :  6,
+                      cbf_sounding_token_mask                                 :  1,
+                      cbf_bw_mask                                             :  1,
+                      cbf_bw                                                  :  3,
+                      use_static_bw                                           :  1,
+                      coex_nack_count                                         :  5,
+                      sch_tx_burst_ongoing                                    :  1,
+                      gen_tqm_update_mpdu_count_tlv                           :  1,
+                      rts_tx_over___reserved_g_0016                                         :  1,
+                      reserved_4a                                             :  3,
+                      optimal_bw_retry_count                                  :  4,
+                      fes_continuation_ratio_threshold                        :  5;
+             uint32_t transmit_cca_bitmap                                     : 32;
+             uint32_t tb___reserved_g_0005                                              :  1,
+                      __reserved_g_0005_trigger_subtype                                 :  4,
+                      min_cts2self_count                                      :  4,
+                      max_cts2self_count                                      :  4,
+                      wifi_radar_enable                                       :  1,
+                      reserved_6a                                             :  1,
+                      wait_for_chksum_done                                    :  1,
+                      reserved_6b                                             : 15,
+                      enable_hw_qos_null                                      :  1;
+             uint32_t monitor_override_sta_31_0                               : 32;
+             uint32_t monitor_override_sta_36_32                              :  5,
+                      enable_qos_null_switch_for_eosp                         :  1,
+                      reserved_8a                                             : 26;
+             uint32_t fw2sw_info                                              : 32;
+#else
+             uint32_t schedule_id                                             : 32;
+             uint32_t response_to_response_cmd                                :  1,
+                      ofdma_triggered_response                                :  1,
+                      mu_type                                                 :  1,
+                      number_of_users                                         :  6,
+                      fes_control_mode                                        :  2,
+                      schedule_cmd_ring_id                                    :  5,
+                      puncture_from_all_allowed_modes                         :  1,
+                      obss_pd_based_transmit_status                           :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      use_alt_power_sr                                        :  1,
+                      transmit_start_reason                                   :  3,
+                      expect_i2r_lmr                                          :  1,
+                      __reserved_g_0005                                                 :  1,
+                      bo_based_tid_aggregation_limit                          :  4,
+                      fes_in_11ax_trigger_response_config                     :  1;
+             uint32_t ast_index                                               : 16,
+                      bw_restricted_frames_embedded                           :  1,
+                      transmission_contains_mu_rts                            :  1,
+                      set_txop_duration_all_ones                              :  1,
+                      static_bandwidth                                        :  3,
+                      ignore_tbtt                                             :  1,
+                      ignore_bw_available                                     :  1,
+                      allow_txop_exceed_in_1st_pkt                            :  1,
+                      txbf                                                    :  1,
+                      ndp_frame                                               :  2,
+                      schedule_try                                            :  4;
+             uint32_t cbf_feedback_type                                       :  1,
+                      cbf_feedback_type_mask                                  :  1,
+                      wait_sifs                                               :  2,
+                      ndpa                                                    :  1,
+                      secure___reserved_g_0005_ista                                     :  1,
+                      cbf_nr_index                                            :  3,
+                      cbf_nr_index_mask                                       :  1,
+                      cbf_nc_index                                            :  3,
+                      cbf_nc_index_mask                                       :  1,
+                      bf_type                                                 :  2,
+                      mu_ndp                                                  :  1,
+                      rbo_must_have_data_user_limit                           :  4,
+                      rxpcu_setup_complete_present                            :  1,
+                      trigger_resp_txpdu_ppdu_boundary                        :  2,
+                      cv_id                                                   :  8;
+             uint32_t fes_continuation_ratio_threshold                        :  5,
+                      optimal_bw_retry_count                                  :  4,
+                      reserved_4a                                             :  3,
+                      rts_tx_over___reserved_g_0016                                         :  1,
+                      gen_tqm_update_mpdu_count_tlv                           :  1,
+                      sch_tx_burst_ongoing                                    :  1,
+                      coex_nack_count                                         :  5,
+                      use_static_bw                                           :  1,
+                      cbf_bw                                                  :  3,
+                      cbf_bw_mask                                             :  1,
+                      cbf_sounding_token_mask                                 :  1,
+                      cbf_sounding_token                                      :  6;
+             uint32_t transmit_cca_bitmap                                     : 32;
+             uint32_t enable_hw_qos_null                                      :  1,
+                      reserved_6b                                             : 15,
+                      wait_for_chksum_done                                    :  1,
+                      reserved_6a                                             :  1,
+                      wifi_radar_enable                                       :  1,
+                      max_cts2self_count                                      :  4,
+                      min_cts2self_count                                      :  4,
+                      __reserved_g_0005_trigger_subtype                                 :  4,
+                      tb___reserved_g_0005                                              :  1;
+             uint32_t monitor_override_sta_31_0                               : 32;
+             uint32_t reserved_8a                                             : 26,
+                      enable_qos_null_switch_for_eosp                         :  1,
+                      monitor_override_sta_36_32                              :  5;
+             uint32_t fw2sw_info                                              : 32;
+#endif
+};
+
+#define TX_FES_SETUP_SCHEDULE_ID_OFFSET                                             0x00000000
+#define TX_FES_SETUP_SCHEDULE_ID_LSB                                                0
+#define TX_FES_SETUP_SCHEDULE_ID_MSB                                                31
+#define TX_FES_SETUP_SCHEDULE_ID_MASK                                               0xffffffff
+
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET                     0x00000004
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB                        0
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB                        0
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK                       0x00000001
+
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET                          0x00000004
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB                             1
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB                             4
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK                            0x0000001e
+
+#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET                                          0x00000004
+#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB                                             6
+#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB                                             6
+#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK                                            0x00000040
+
+#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET                                   0x00000004
+#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB                                      7
+#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB                                      9
+#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK                                     0x00000380
+
+#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET                                        0x00000004
+#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB                                           10
+#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB                                           10
+#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK                                          0x00000400
+
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET                                0x00000004
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB                                   11
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB                                   11
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK                                  0x00000800
+
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET                         0x00000004
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB                            12
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB                            12
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK                           0x00001000
+
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET                               0x00000004
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB                                  13
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB                                  13
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK                                 0x00002000
+
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET                           0x00000004
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB                              14
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB                              14
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK                             0x00004000
+
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET                         0x00000004
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB                            15
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB                            15
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK                           0x00008000
+
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET                                    0x00000004
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB                                       16
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB                                       20
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK                                      0x001f0000
+
+#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET                                        0x00000004
+#define TX_FES_SETUP_FES_CONTROL_MODE_LSB                                           21
+#define TX_FES_SETUP_FES_CONTROL_MODE_MSB                                           22
+#define TX_FES_SETUP_FES_CONTROL_MODE_MASK                                          0x00600000
+
+#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET                                         0x00000004
+#define TX_FES_SETUP_NUMBER_OF_USERS_LSB                                            23
+#define TX_FES_SETUP_NUMBER_OF_USERS_MSB                                            28
+#define TX_FES_SETUP_NUMBER_OF_USERS_MASK                                           0x1f800000
+
+#define TX_FES_SETUP_MU_TYPE_OFFSET                                                 0x00000004
+#define TX_FES_SETUP_MU_TYPE_LSB                                                    29
+#define TX_FES_SETUP_MU_TYPE_MSB                                                    29
+#define TX_FES_SETUP_MU_TYPE_MASK                                                   0x20000000
+
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET                                0x00000004
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB                                   30
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB                                   30
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK                                  0x40000000
+
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET                                0x00000004
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB                                   31
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB                                   31
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK                                  0x80000000
+
+#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET                                            0x00000008
+#define TX_FES_SETUP_SCHEDULE_TRY_LSB                                               0
+#define TX_FES_SETUP_SCHEDULE_TRY_MSB                                               3
+#define TX_FES_SETUP_SCHEDULE_TRY_MASK                                              0x0000000f
+
+#define TX_FES_SETUP_NDP_FRAME_OFFSET                                               0x00000008
+#define TX_FES_SETUP_NDP_FRAME_LSB                                                  4
+#define TX_FES_SETUP_NDP_FRAME_MSB                                                  5
+#define TX_FES_SETUP_NDP_FRAME_MASK                                                 0x00000030
+
+#define TX_FES_SETUP_TXBF_OFFSET                                                    0x00000008
+#define TX_FES_SETUP_TXBF_LSB                                                       6
+#define TX_FES_SETUP_TXBF_MSB                                                       6
+#define TX_FES_SETUP_TXBF_MASK                                                      0x00000040
+
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET                            0x00000008
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB                               7
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB                               7
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK                              0x00000080
+
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET                                     0x00000008
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB                                        8
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB                                        8
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK                                       0x00000100
+
+#define TX_FES_SETUP_IGNORE_TBTT_OFFSET                                             0x00000008
+#define TX_FES_SETUP_IGNORE_TBTT_LSB                                                9
+#define TX_FES_SETUP_IGNORE_TBTT_MSB                                                9
+#define TX_FES_SETUP_IGNORE_TBTT_MASK                                               0x00000200
+
+#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET                                        0x00000008
+#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB                                           10
+#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB                                           12
+#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK                                          0x00001c00
+
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET                              0x00000008
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB                                 13
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB                                 13
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK                                0x00002000
+
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET                            0x00000008
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB                               14
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB                               14
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK                              0x00004000
+
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET                           0x00000008
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB                              15
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB                              15
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK                             0x00008000
+
+#define TX_FES_SETUP_AST_INDEX_OFFSET                                               0x00000008
+#define TX_FES_SETUP_AST_INDEX_LSB                                                  16
+#define TX_FES_SETUP_AST_INDEX_MSB                                                  31
+#define TX_FES_SETUP_AST_INDEX_MASK                                                 0xffff0000
+
+#define TX_FES_SETUP_CV_ID_OFFSET                                                   0x0000000c
+#define TX_FES_SETUP_CV_ID_LSB                                                      0
+#define TX_FES_SETUP_CV_ID_MSB                                                      7
+#define TX_FES_SETUP_CV_ID_MASK                                                     0x000000ff
+
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET                        0x0000000c
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB                           8
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB                           9
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK                          0x00000300
+
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET                            0x0000000c
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB                               10
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB                               10
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK                              0x00000400
+
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET                           0x0000000c
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB                              11
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB                              14
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK                             0x00007800
+
+#define TX_FES_SETUP_MU_NDP_OFFSET                                                  0x0000000c
+#define TX_FES_SETUP_MU_NDP_LSB                                                     15
+#define TX_FES_SETUP_MU_NDP_MSB                                                     15
+#define TX_FES_SETUP_MU_NDP_MASK                                                    0x00008000
+
+#define TX_FES_SETUP_BF_TYPE_OFFSET                                                 0x0000000c
+#define TX_FES_SETUP_BF_TYPE_LSB                                                    16
+#define TX_FES_SETUP_BF_TYPE_MSB                                                    17
+#define TX_FES_SETUP_BF_TYPE_MASK                                                   0x00030000
+
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET                                       0x0000000c
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB                                          18
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB                                          18
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK                                         0x00040000
+
+#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET                                            0x0000000c
+#define TX_FES_SETUP_CBF_NC_INDEX_LSB                                               19
+#define TX_FES_SETUP_CBF_NC_INDEX_MSB                                               21
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK                                              0x00380000
+
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET                                       0x0000000c
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB                                          22
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB                                          22
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK                                         0x00400000
+
+#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET                                            0x0000000c
+#define TX_FES_SETUP_CBF_NR_INDEX_LSB                                               23
+#define TX_FES_SETUP_CBF_NR_INDEX_MSB                                               25
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK                                              0x03800000
+
+#define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET                                     0x0000000c
+#define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB                                        26
+#define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB                                        26
+#define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK                                       0x04000000
+
+#define TX_FES_SETUP_NDPA_OFFSET                                                    0x0000000c
+#define TX_FES_SETUP_NDPA_LSB                                                       27
+#define TX_FES_SETUP_NDPA_MSB                                                       27
+#define TX_FES_SETUP_NDPA_MASK                                                      0x08000000
+
+#define TX_FES_SETUP_WAIT_SIFS_OFFSET                                               0x0000000c
+#define TX_FES_SETUP_WAIT_SIFS_LSB                                                  28
+#define TX_FES_SETUP_WAIT_SIFS_MSB                                                  29
+#define TX_FES_SETUP_WAIT_SIFS_MASK                                                 0x30000000
+
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET                                  0x0000000c
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB                                     30
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB                                     30
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK                                    0x40000000
+
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET                                       0x0000000c
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB                                          31
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB                                          31
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK                                         0x80000000
+
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET                                      0x00000010
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB                                         0
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB                                         5
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK                                        0x0000003f
+
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET                                 0x00000010
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB                                    6
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB                                    6
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK                                   0x00000040
+
+#define TX_FES_SETUP_CBF_BW_MASK_OFFSET                                             0x00000010
+#define TX_FES_SETUP_CBF_BW_MASK_LSB                                                7
+#define TX_FES_SETUP_CBF_BW_MASK_MSB                                                7
+#define TX_FES_SETUP_CBF_BW_MASK_MASK                                               0x00000080
+
+#define TX_FES_SETUP_CBF_BW_OFFSET                                                  0x00000010
+#define TX_FES_SETUP_CBF_BW_LSB                                                     8
+#define TX_FES_SETUP_CBF_BW_MSB                                                     10
+#define TX_FES_SETUP_CBF_BW_MASK                                                    0x00000700
+
+#define TX_FES_SETUP_USE_STATIC_BW_OFFSET                                           0x00000010
+#define TX_FES_SETUP_USE_STATIC_BW_LSB                                              11
+#define TX_FES_SETUP_USE_STATIC_BW_MSB                                              11
+#define TX_FES_SETUP_USE_STATIC_BW_MASK                                             0x00000800
+
+#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET                                         0x00000010
+#define TX_FES_SETUP_COEX_NACK_COUNT_LSB                                            12
+#define TX_FES_SETUP_COEX_NACK_COUNT_MSB                                            16
+#define TX_FES_SETUP_COEX_NACK_COUNT_MASK                                           0x0001f000
+
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET                                    0x00000010
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB                                       17
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB                                       17
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK                                      0x00020000
+
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET                           0x00000010
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB                              18
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB                              18
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK                             0x00040000
+
+#define TX_FES_SETUP_RESERVED_4A_OFFSET                                             0x00000010
+#define TX_FES_SETUP_RESERVED_4A_LSB                                                20
+#define TX_FES_SETUP_RESERVED_4A_MSB                                                22
+#define TX_FES_SETUP_RESERVED_4A_MASK                                               0x00700000
+
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET                                  0x00000010
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB                                     23
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB                                     26
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK                                    0x07800000
+
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET                        0x00000010
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB                           27
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB                           31
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK                          0xf8000000
+
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET                                     0x00000014
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB                                        0
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB                                        31
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK                                       0xffffffff
+
+#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET                                 0x00000018
+#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB                                    1
+#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB                                    4
+#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK                                   0x0000001e
+
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET                                      0x00000018
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB                                         5
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB                                         8
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK                                        0x000001e0
+
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET                                      0x00000018
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB                                         9
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB                                         12
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK                                        0x00001e00
+
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET                                       0x00000018
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB                                          13
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB                                          13
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK                                         0x00002000
+
+#define TX_FES_SETUP_RESERVED_6A_OFFSET                                             0x00000018
+#define TX_FES_SETUP_RESERVED_6A_LSB                                                14
+#define TX_FES_SETUP_RESERVED_6A_MSB                                                14
+#define TX_FES_SETUP_RESERVED_6A_MASK                                               0x00004000
+
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET                                    0x00000018
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB                                       15
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB                                       15
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK                                      0x00008000
+
+#define TX_FES_SETUP_RESERVED_6B_OFFSET                                             0x00000018
+#define TX_FES_SETUP_RESERVED_6B_LSB                                                16
+#define TX_FES_SETUP_RESERVED_6B_MSB                                                30
+#define TX_FES_SETUP_RESERVED_6B_MASK                                               0x7fff0000
+
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET                                      0x00000018
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB                                         31
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB                                         31
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK                                        0x80000000
+
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET                               0x0000001c
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB                                  0
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB                                  31
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK                                 0xffffffff
+
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET                              0x00000020
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB                                 0
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB                                 4
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK                                0x0000001f
+
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET                         0x00000020
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB                            5
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB                            5
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK                           0x00000020
+
+#define TX_FES_SETUP_RESERVED_8A_OFFSET                                             0x00000020
+#define TX_FES_SETUP_RESERVED_8A_LSB                                                6
+#define TX_FES_SETUP_RESERVED_8A_MSB                                                31
+#define TX_FES_SETUP_RESERVED_8A_MASK                                               0xffffffc0
+
+#define TX_FES_SETUP_FW2SW_INFO_OFFSET                                              0x00000024
+#define TX_FES_SETUP_FW2SW_INFO_LSB                                                 0
+#define TX_FES_SETUP_FW2SW_INFO_MSB                                                 31
+#define TX_FES_SETUP_FW2SW_INFO_MASK                                                0xffffffff
+
+#endif
diff --git a/hw/peach/v1/tx_fes_status_1k_ba.h b/hw/peach/v1/tx_fes_status_1k_ba.h
new file mode 100644
index 000000000000..7b391758e361
--- /dev/null
+++ b/hw/peach/v1/tx_fes_status_1k_ba.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_1K_BA_H_
+#define _TX_FES_STATUS_1K_BA_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34
+
+struct tx_fes_status_1k_ba {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ack_ba_status_type                                      :  1,
+                      ba_type                                                 :  1,
+                      ba_tid                                                  :  4,
+                      unexpected_ack_or_ba                                    :  1,
+                      response_timeout                                        :  1,
+                      ack_frame_rssi                                          :  8,
+                      ssn                                                     : 12,
+                      reserved_0b                                             :  4;
+             uint32_t sw_peer_id                                              : 16,
+                      reserved_1a                                             : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+             uint32_t ba_bitmap_287_256                                       : 32;
+             uint32_t ba_bitmap_319_288                                       : 32;
+             uint32_t ba_bitmap_351_320                                       : 32;
+             uint32_t ba_bitmap_383_352                                       : 32;
+             uint32_t ba_bitmap_415_384                                       : 32;
+             uint32_t ba_bitmap_447_416                                       : 32;
+             uint32_t ba_bitmap_479_448                                       : 32;
+             uint32_t ba_bitmap_511_480                                       : 32;
+             uint32_t ba_bitmap_543_512                                       : 32;
+             uint32_t ba_bitmap_575_544                                       : 32;
+             uint32_t ba_bitmap_607_576                                       : 32;
+             uint32_t ba_bitmap_639_608                                       : 32;
+             uint32_t ba_bitmap_671_640                                       : 32;
+             uint32_t ba_bitmap_703_672                                       : 32;
+             uint32_t ba_bitmap_735_704                                       : 32;
+             uint32_t ba_bitmap_767_736                                       : 32;
+             uint32_t ba_bitmap_799_768                                       : 32;
+             uint32_t ba_bitmap_831_800                                       : 32;
+             uint32_t ba_bitmap_863_832                                       : 32;
+             uint32_t ba_bitmap_895_864                                       : 32;
+             uint32_t ba_bitmap_927_896                                       : 32;
+             uint32_t ba_bitmap_959_928                                       : 32;
+             uint32_t ba_bitmap_991_960                                       : 32;
+             uint32_t ba_bitmap_1023_992                                      : 32;
+#else
+             uint32_t reserved_0b                                             :  4,
+                      ssn                                                     : 12,
+                      ack_frame_rssi                                          :  8,
+                      response_timeout                                        :  1,
+                      unexpected_ack_or_ba                                    :  1,
+                      ba_tid                                                  :  4,
+                      ba_type                                                 :  1,
+                      ack_ba_status_type                                      :  1;
+             uint32_t reserved_1a                                             : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+             uint32_t ba_bitmap_287_256                                       : 32;
+             uint32_t ba_bitmap_319_288                                       : 32;
+             uint32_t ba_bitmap_351_320                                       : 32;
+             uint32_t ba_bitmap_383_352                                       : 32;
+             uint32_t ba_bitmap_415_384                                       : 32;
+             uint32_t ba_bitmap_447_416                                       : 32;
+             uint32_t ba_bitmap_479_448                                       : 32;
+             uint32_t ba_bitmap_511_480                                       : 32;
+             uint32_t ba_bitmap_543_512                                       : 32;
+             uint32_t ba_bitmap_575_544                                       : 32;
+             uint32_t ba_bitmap_607_576                                       : 32;
+             uint32_t ba_bitmap_639_608                                       : 32;
+             uint32_t ba_bitmap_671_640                                       : 32;
+             uint32_t ba_bitmap_703_672                                       : 32;
+             uint32_t ba_bitmap_735_704                                       : 32;
+             uint32_t ba_bitmap_767_736                                       : 32;
+             uint32_t ba_bitmap_799_768                                       : 32;
+             uint32_t ba_bitmap_831_800                                       : 32;
+             uint32_t ba_bitmap_863_832                                       : 32;
+             uint32_t ba_bitmap_895_864                                       : 32;
+             uint32_t ba_bitmap_927_896                                       : 32;
+             uint32_t ba_bitmap_959_928                                       : 32;
+             uint32_t ba_bitmap_991_960                                       : 32;
+             uint32_t ba_bitmap_1023_992                                      : 32;
+#endif
+};
+
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET                               0x00000000
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB                                  0
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB                                  0
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK                                 0x00000001
+
+#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET                                          0x00000000
+#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB                                             1
+#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB                                             1
+#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK                                            0x00000002
+
+#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET                                           0x00000000
+#define TX_FES_STATUS_1K_BA_BA_TID_LSB                                              2
+#define TX_FES_STATUS_1K_BA_BA_TID_MSB                                              5
+#define TX_FES_STATUS_1K_BA_BA_TID_MASK                                             0x0000003c
+
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET                             0x00000000
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB                                6
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB                                6
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK                               0x00000040
+
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET                                 0x00000000
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB                                    7
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB                                    7
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK                                   0x00000080
+
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET                                   0x00000000
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB                                      8
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB                                      15
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK                                     0x0000ff00
+
+#define TX_FES_STATUS_1K_BA_SSN_OFFSET                                              0x00000000
+#define TX_FES_STATUS_1K_BA_SSN_LSB                                                 16
+#define TX_FES_STATUS_1K_BA_SSN_MSB                                                 27
+#define TX_FES_STATUS_1K_BA_SSN_MASK                                                0x0fff0000
+
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET                                      0x00000000
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB                                         28
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB                                         31
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK                                        0xf0000000
+
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET                                       0x00000004
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB                                          0
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB                                          15
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK                                         0x0000ffff
+
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET                                      0x00000004
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB                                         16
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB                                         31
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK                                        0xffff0000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET                                   0x00000008
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB                                      0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB                                      31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK                                     0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET                                  0x0000000c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB                                     0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB                                     31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK                                    0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET                                  0x00000010
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB                                     0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB                                     31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK                                    0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET                                 0x00000014
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB                                    0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB                                    31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK                                   0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET                                0x00000018
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET                                0x0000001c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET                                0x00000020
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET                                0x00000024
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET                                0x00000028
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET                                0x0000002c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET                                0x00000030
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET                                0x00000034
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET                                0x00000038
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET                                0x0000003c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET                                0x00000040
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET                                0x00000044
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET                                0x00000048
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET                                0x0000004c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET                                0x00000050
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET                                0x00000054
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET                                0x00000058
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET                                0x0000005c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET                                0x00000060
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET                                0x00000064
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET                                0x00000068
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET                                0x0000006c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET                                0x00000070
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET                                0x00000074
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET                                0x00000078
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET                                0x0000007c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET                                0x00000080
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB                                   0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB                                   31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK                                  0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET                               0x00000084
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB                                  0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB                                  31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK                                 0xffffffff
+
+#endif
diff --git a/hw/peach/v1/tx_fes_status_ack_or_ba.h b/hw/peach/v1/tx_fes_status_ack_or_ba.h
new file mode 100644
index 000000000000..582cc09ba72a
--- /dev/null
+++ b/hw/peach/v1/tx_fes_status_ack_or_ba.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_ACK_OR_BA_H_
+#define _TX_FES_STATUS_ACK_OR_BA_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10
+
+struct tx_fes_status_ack_or_ba {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ack_ba_status_type                                      :  1,
+                      ba_type                                                 :  1,
+                      ba_tid                                                  :  4,
+                      unexpected_ack_or_ba                                    :  1,
+                      response_timeout                                        :  1,
+                      ack_frame_rssi                                          :  8,
+                      ssn                                                     : 12,
+                      reserved_0b                                             :  4;
+             uint32_t sw_peer_id                                              : 16,
+                      reserved_1a                                             : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+#else
+             uint32_t reserved_0b                                             :  4,
+                      ssn                                                     : 12,
+                      ack_frame_rssi                                          :  8,
+                      response_timeout                                        :  1,
+                      unexpected_ack_or_ba                                    :  1,
+                      ba_tid                                                  :  4,
+                      ba_type                                                 :  1,
+                      ack_ba_status_type                                      :  1;
+             uint32_t reserved_1a                                             : 16,
+                      sw_peer_id                                              : 16;
+             uint32_t ba_bitmap_31_0                                          : 32;
+             uint32_t ba_bitmap_63_32                                         : 32;
+             uint32_t ba_bitmap_95_64                                         : 32;
+             uint32_t ba_bitmap_127_96                                        : 32;
+             uint32_t ba_bitmap_159_128                                       : 32;
+             uint32_t ba_bitmap_191_160                                       : 32;
+             uint32_t ba_bitmap_223_192                                       : 32;
+             uint32_t ba_bitmap_255_224                                       : 32;
+#endif
+};
+
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET                           0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB                              0
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB                              0
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK                             0x00000001
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET                                      0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB                                         1
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB                                         1
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK                                        0x00000002
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET                                       0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB                                          2
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB                                          5
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK                                         0x0000003c
+
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET                         0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB                            6
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB                            6
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK                           0x00000040
+
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET                             0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB                                7
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB                                7
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK                               0x00000080
+
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET                               0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB                                  8
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB                                  15
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK                                 0x0000ff00
+
+#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET                                          0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB                                             16
+#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB                                             27
+#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK                                            0x0fff0000
+
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET                                  0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB                                     28
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB                                     31
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK                                    0xf0000000
+
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET                                   0x00000004
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB                                      0
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB                                      15
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK                                     0x0000ffff
+
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET                                  0x00000004
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB                                     16
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB                                     31
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK                                    0xffff0000
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET                               0x00000008
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB                                  0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB                                  31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK                                 0xffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET                              0x0000000c
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB                                 0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB                                 31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK                                0xffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET                              0x00000010
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB                                 0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB                                 31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK                                0xffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET                             0x00000014
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB                                0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB                                31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK                               0xffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET                            0x00000018
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB                               0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB                               31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK                              0xffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET                            0x0000001c
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB                               0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB                               31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK                              0xffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET                            0x00000020
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB                               0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB                               31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK                              0xffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET                            0x00000024
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB                               0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB                               31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK                              0xffffffff
+
+#endif
diff --git a/hw/peach/v1/tx_fes_status_end.h b/hw/peach/v1/tx_fes_status_end.h
new file mode 100644
index 000000000000..eea99f35e333
--- /dev/null
+++ b/hw/peach/v1/tx_fes_status_end.h
@@ -0,0 +1,649 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_END_H_
+#define _TX_FES_STATUS_END_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_TX_FES_STATUS_END 11
+
+struct tx_fes_status_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t prot_coex_bt_tx_while_wlan_tx                           :  1,
+                      prot_coex_bt_tx_while_wlan_rx                           :  1,
+                      prot_coex_wan_tx_while_wlan_tx                          :  1,
+                      prot_coex_wan_tx_while_wlan_rx                          :  1,
+                      prot_coex_wlan_tx_while_wlan_tx                         :  1,
+                      prot_coex_wlan_tx_while_wlan_rx                         :  1,
+                      coex_bt_tx_while_wlan_tx                                :  1,
+                      coex_bt_tx_while_wlan_rx                                :  1,
+                      coex_wan_tx_while_wlan_tx                               :  1,
+                      coex_wan_tx_while_wlan_rx                               :  1,
+                      coex_wlan_tx_while_wlan_tx                              :  1,
+                      coex_wlan_tx_while_wlan_rx                              :  1,
+                      global_data_underflow_warning                           :  1,
+                      global_fes_transmit_result                              :  4,
+                      cbf_bw_received_valid                                   :  1,
+                      cbf_bw_received                                         :  3,
+                      actual_received_ack_type                                :  4,
+                      sta_response_count                                      :  6,
+                      more_data_received                                      :  1;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t reserved_after_struct16                                 :  4,
+                      brp_info_valid                                          :  1,
+                      qos_null_switch_done_for_eosp                           :  1,
+                      reserved_1a                                             :  5,
+                      phytx_pkt_end_info_valid                                :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      fes_in_11ax_trigger_response_config                     :  1,
+                      null_delim_inserted_before_mpdus                        :  1,
+                      only_null_delim_sent                                    :  1;
+             uint32_t terminate___reserved_g_0005_sequence                              :  1,
+                      reserved_2b                                             :  5,
+                      response_type                                           :  5,
+                      r2r_end_status_to_follow                                :  1,
+                      reserved_5a                                             :  3,
+                      prot_coex_lte_tx_while_wlan_tx                          :  1,
+                      prot_coex_lte_tx_while_wlan_rx                          :  1,
+                      reserved_2c                                             : 15;
+             uint32_t beamform_masked_user_bitmap_15_0                        : 16,
+                      beamform_masked_user_bitmap_31_16                       : 16;
+             uint32_t cbf_segment_request_mask                                :  8,
+                      cbf_segment_sent_mask                                   :  8,
+                      highest_achieved_data_null_ratio                        :  5,
+                      use_alt_power_sr                                        :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_pd_based_transmit_status                           :  1,
+                      beamform_masked_user_bitmap_36_32                       :  5,
+                      pdg_mpdu_ready                                          :  1;
+             uint32_t pdg_mpdu_count                                          : 16,
+                      pdg_est_mpdu_tx_count                                   : 16;
+             uint32_t pdg_overview_length                                     : 24,
+                      txop_duration                                           :  7,
+                      pdg_dropped_mpdu_warning                                :  1;
+             uint32_t packet_extension_a_factor                               :  2,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension                                        :  3,
+                      fec_type                                                :  1,
+                      stbc                                                    :  1,
+                      num_data_symbols                                        : 16,
+                      ru_size                                                 :  4,
+                      reserved_17a                                            :  4;
+             uint32_t num_ltf_symbols                                         :  3,
+                      ltf_size                                                :  2,
+                      cp_setting                                              :  2,
+                      reserved_18a                                            :  5,
+                      dcm                                                     :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      force_extra_symbol                                      :  1,
+                      reserved_18b                                            :  1,
+                      tx_pwr_shared                                           :  8,
+                      tx_pwr_unshared                                         :  8;
+             uint32_t __reserved_g_0005_active_user_map                                 : 16,
+                      __reserved_g_0005_sent_dummy_tx                                   :  1,
+                      __reserved_g_0005_ftm_frame_sent                                  :  1,
+                      coex_uwb_tx_while_wlan_tx                               :  1,
+                      coex_uwb_tx_while_wlan_rx                               :  1,
+                      prot_coex_uwb_tx_while_wlan_tx                          :  1,
+                      prot_coex_uwb_tx_while_wlan_rx                          :  1,
+                      coex_lte_tx_while_wlan_tx                               :  1,
+                      coex_lte_tx_while_wlan_rx                               :  1,
+                      cv_corr_status                                          :  8;
+             uint32_t current_tx_duration                                     : 16,
+                      reserved_21a                                            :  4,
+                      hw_qos_null_bitmap                                      :  8,
+                      hw_qos_null_setup_missing                               :  1,
+                      reserved_21b                                            :  3;
+#else
+             uint32_t more_data_received                                      :  1,
+                      sta_response_count                                      :  6,
+                      actual_received_ack_type                                :  4,
+                      cbf_bw_received                                         :  3,
+                      cbf_bw_received_valid                                   :  1,
+                      global_fes_transmit_result                              :  4,
+                      global_data_underflow_warning                           :  1,
+                      coex_wlan_tx_while_wlan_rx                              :  1,
+                      coex_wlan_tx_while_wlan_tx                              :  1,
+                      coex_wan_tx_while_wlan_rx                               :  1,
+                      coex_wan_tx_while_wlan_tx                               :  1,
+                      coex_bt_tx_while_wlan_rx                                :  1,
+                      coex_bt_tx_while_wlan_tx                                :  1,
+                      prot_coex_wlan_tx_while_wlan_rx                         :  1,
+                      prot_coex_wlan_tx_while_wlan_tx                         :  1,
+                      prot_coex_wan_tx_while_wlan_rx                          :  1,
+                      prot_coex_wan_tx_while_wlan_tx                          :  1,
+                      prot_coex_bt_tx_while_wlan_rx                           :  1,
+                      prot_coex_bt_tx_while_wlan_tx                           :  1;
+             uint32_t only_null_delim_sent                                    :  1,
+                      null_delim_inserted_before_mpdus                        :  1,
+                      fes_in_11ax_trigger_response_config                     :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      reserved_1a                                             :  5,
+                      qos_null_switch_done_for_eosp                           :  1,
+                      brp_info_valid                                          :  1,
+                      reserved_after_struct16                                 :  4;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint32_t reserved_2c                                             : 15,
+                      prot_coex_lte_tx_while_wlan_rx                          :  1,
+                      prot_coex_lte_tx_while_wlan_tx                          :  1,
+                      reserved_5a                                             :  3,
+                      r2r_end_status_to_follow                                :  1,
+                      response_type                                           :  5,
+                      reserved_2b                                             :  5,
+                      terminate___reserved_g_0005_sequence                              :  1;
+             uint32_t beamform_masked_user_bitmap_31_16                       : 16,
+                      beamform_masked_user_bitmap_15_0                        : 16;
+             uint32_t pdg_mpdu_ready                                          :  1,
+                      beamform_masked_user_bitmap_36_32                       :  5,
+                      obss_pd_based_transmit_status                           :  1,
+                      srp_based_transmit_status                               :  1,
+                      obss_srg_opport_transmit_status                         :  1,
+                      static_2_pwr_mode_status                                :  1,
+                      use_alt_power_sr                                        :  1,
+                      highest_achieved_data_null_ratio                        :  5,
+                      cbf_segment_sent_mask                                   :  8,
+                      cbf_segment_request_mask                                :  8;
+             uint32_t pdg_est_mpdu_tx_count                                   : 16,
+                      pdg_mpdu_count                                          : 16;
+             uint32_t pdg_dropped_mpdu_warning                                :  1,
+                      txop_duration                                           :  7,
+                      pdg_overview_length                                     : 24;
+             uint32_t reserved_17a                                            :  4,
+                      ru_size                                                 :  4,
+                      num_data_symbols                                        : 16,
+                      stbc                                                    :  1,
+                      fec_type                                                :  1,
+                      packet_extension                                        :  3,
+                      packet_extension_pe_disambiguity                        :  1,
+                      packet_extension_a_factor                               :  2;
+             uint32_t tx_pwr_unshared                                         :  8,
+                      tx_pwr_shared                                           :  8,
+                      reserved_18b                                            :  1,
+                      force_extra_symbol                                      :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      dcm                                                     :  1,
+                      reserved_18a                                            :  5,
+                      cp_setting                                              :  2,
+                      ltf_size                                                :  2,
+                      num_ltf_symbols                                         :  3;
+             uint32_t cv_corr_status                                          :  8,
+                      coex_lte_tx_while_wlan_rx                               :  1,
+                      coex_lte_tx_while_wlan_tx                               :  1,
+                      prot_coex_uwb_tx_while_wlan_rx                          :  1,
+                      prot_coex_uwb_tx_while_wlan_tx                          :  1,
+                      coex_uwb_tx_while_wlan_rx                               :  1,
+                      coex_uwb_tx_while_wlan_tx                               :  1,
+                      __reserved_g_0005_ftm_frame_sent                                  :  1,
+                      __reserved_g_0005_sent_dummy_tx                                   :  1,
+                      __reserved_g_0005_active_user_map                                 : 16;
+             uint32_t reserved_21b                                            :  3,
+                      hw_qos_null_setup_missing                               :  1,
+                      hw_qos_null_bitmap                                      :  8,
+                      reserved_21a                                            :  4,
+                      current_tx_duration                                     : 16;
+#endif
+};
+
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET                      0x00000000
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB                         0
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB                         0
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK                        0x00000001
+
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET                      0x00000000
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB                         1
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB                         1
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK                        0x00000002
+
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET                     0x00000000
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB                        2
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB                        2
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK                       0x00000004
+
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET                     0x00000000
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB                        3
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB                        3
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK                       0x00000008
+
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET                    0x00000000
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB                       4
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB                       4
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK                      0x00000010
+
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET                    0x00000000
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB                       5
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB                       5
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK                      0x00000020
+
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET                           0x00000000
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB                              6
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB                              6
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK                             0x00000040
+
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET                           0x00000000
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB                              7
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB                              7
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK                             0x00000080
+
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET                          0x00000000
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB                             8
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB                             8
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK                            0x00000100
+
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET                          0x00000000
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB                             9
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB                             9
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK                            0x00000200
+
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET                         0x00000000
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB                            10
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB                            10
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK                           0x00000400
+
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET                         0x00000000
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB                            11
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB                            11
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK                           0x00000800
+
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET                      0x00000000
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB                         12
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB                         12
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK                        0x00001000
+
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET                         0x00000000
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB                            13
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB                            16
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK                           0x0001e000
+
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET                              0x00000000
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB                                 17
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB                                 17
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK                                0x00020000
+
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET                                    0x00000000
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB                                       18
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB                                       20
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK                                      0x001c0000
+
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET                           0x00000000
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB                              21
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB                              24
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK                             0x01e00000
+
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET                                 0x00000000
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB                                    25
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB                                    30
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK                                   0x7e000000
+
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_OFFSET                                 0x00000000
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_LSB                                    31
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MSB                                    31
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MASK                                   0x80000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB   0
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB   7
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK  0x000000ff
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET       0x00000004
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB          8
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB          13
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK         0x00003f00
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET          0x00000004
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB             14
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB             15
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK            0x0000c000
+
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET                            0x00000004
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB                               16
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB                               19
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK                              0x000f0000
+
+#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET                                     0x00000004
+#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB                                        20
+#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB                                        20
+#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK                                       0x00100000
+
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_OFFSET                      0x00000004
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_LSB                         21
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MSB                         21
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MASK                        0x00200000
+
+#define TX_FES_STATUS_END_RESERVED_1A_OFFSET                                        0x00000004
+#define TX_FES_STATUS_END_RESERVED_1A_LSB                                           22
+#define TX_FES_STATUS_END_RESERVED_1A_MSB                                           26
+#define TX_FES_STATUS_END_RESERVED_1A_MASK                                          0x07c00000
+
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET                           0x00000004
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB                              27
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB                              27
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK                             0x08000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET                     0x00000004
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB                        28
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB                        28
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK                       0x10000000
+
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET                0x00000004
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB                   29
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB                   29
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK                  0x20000000
+
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET                   0x00000004
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB                      30
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB                      30
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK                     0x40000000
+
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET                               0x00000004
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB                                  31
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB                                  31
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK                                 0x80000000
+
+#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET                         0x00000008
+#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB                            0
+#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB                            0
+#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK                           0x00000001
+
+#define TX_FES_STATUS_END_RESERVED_2B_OFFSET                                        0x00000008
+#define TX_FES_STATUS_END_RESERVED_2B_LSB                                           1
+#define TX_FES_STATUS_END_RESERVED_2B_MSB                                           5
+#define TX_FES_STATUS_END_RESERVED_2B_MASK                                          0x0000003e
+
+#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET                                      0x00000008
+#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB                                         6
+#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB                                         10
+#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK                                        0x000007c0
+
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET                           0x00000008
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB                              11
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB                              11
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK                             0x00000800
+
+#define TX_FES_STATUS_END_RESERVED_5A_OFFSET                                        0x00000008
+#define TX_FES_STATUS_END_RESERVED_5A_LSB                                           12
+#define TX_FES_STATUS_END_RESERVED_5A_MSB                                           14
+#define TX_FES_STATUS_END_RESERVED_5A_MASK                                          0x00007000
+
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET                     0x00000008
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_LSB                        15
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_MSB                        15
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_MASK                       0x00008000
+
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_OFFSET                     0x00000008
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_LSB                        16
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_MSB                        16
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_MASK                       0x00010000
+
+#define TX_FES_STATUS_END_RESERVED_2C_OFFSET                                        0x00000008
+#define TX_FES_STATUS_END_RESERVED_2C_LSB                                           17
+#define TX_FES_STATUS_END_RESERVED_2C_MSB                                           31
+#define TX_FES_STATUS_END_RESERVED_2C_MASK                                          0xfffe0000
+
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET                   0x0000000c
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB                      0
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB                      15
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK                     0x0000ffff
+
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET                  0x0000000c
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB                     16
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB                     31
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK                    0xffff0000
+
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET                           0x00000010
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB                              0
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB                              7
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK                             0x000000ff
+
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET                              0x00000010
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB                                 8
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB                                 15
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK                                0x0000ff00
+
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET                   0x00000010
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB                      16
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB                      20
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK                     0x001f0000
+
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET                                   0x00000010
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB                                      21
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB                                      21
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK                                     0x00200000
+
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET                           0x00000010
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB                              22
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB                              22
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK                             0x00400000
+
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET                    0x00000010
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB                       23
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB                       23
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK                      0x00800000
+
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET                          0x00000010
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB                             24
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB                             24
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK                            0x01000000
+
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET                      0x00000010
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB                         25
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB                         25
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK                        0x02000000
+
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET                  0x00000010
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB                     26
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB                     30
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK                    0x7c000000
+
+#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET                                     0x00000010
+#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB                                        31
+#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB                                        31
+#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK                                       0x80000000
+
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET                                     0x00000014
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB                                        0
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB                                        15
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK                                       0x0000ffff
+
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET                              0x00000014
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB                                 16
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB                                 31
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK                                0xffff0000
+
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET                                0x00000018
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB                                   0
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB                                   23
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK                                  0x00ffffff
+
+#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET                                      0x00000018
+#define TX_FES_STATUS_END_TXOP_DURATION_LSB                                         24
+#define TX_FES_STATUS_END_TXOP_DURATION_MSB                                         30
+#define TX_FES_STATUS_END_TXOP_DURATION_MASK                                        0x7f000000
+
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET                           0x00000018
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB                              31
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB                              31
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK                             0x80000000
+
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET                          0x0000001c
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB                             0
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB                             1
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK                            0x00000003
+
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET                   0x0000001c
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB                      2
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB                      2
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK                     0x00000004
+
+#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET                                   0x0000001c
+#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB                                      3
+#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB                                      5
+#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK                                     0x00000038
+
+#define TX_FES_STATUS_END_FEC_TYPE_OFFSET                                           0x0000001c
+#define TX_FES_STATUS_END_FEC_TYPE_LSB                                              6
+#define TX_FES_STATUS_END_FEC_TYPE_MSB                                              6
+#define TX_FES_STATUS_END_FEC_TYPE_MASK                                             0x00000040
+
+#define TX_FES_STATUS_END_STBC_OFFSET                                               0x0000001c
+#define TX_FES_STATUS_END_STBC_LSB                                                  7
+#define TX_FES_STATUS_END_STBC_MSB                                                  7
+#define TX_FES_STATUS_END_STBC_MASK                                                 0x00000080
+
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET                                   0x0000001c
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB                                      8
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB                                      23
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK                                     0x00ffff00
+
+#define TX_FES_STATUS_END_RU_SIZE_OFFSET                                            0x0000001c
+#define TX_FES_STATUS_END_RU_SIZE_LSB                                               24
+#define TX_FES_STATUS_END_RU_SIZE_MSB                                               27
+#define TX_FES_STATUS_END_RU_SIZE_MASK                                              0x0f000000
+
+#define TX_FES_STATUS_END_RESERVED_17A_OFFSET                                       0x0000001c
+#define TX_FES_STATUS_END_RESERVED_17A_LSB                                          28
+#define TX_FES_STATUS_END_RESERVED_17A_MSB                                          31
+#define TX_FES_STATUS_END_RESERVED_17A_MASK                                         0xf0000000
+
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET                                    0x00000020
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB                                       0
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB                                       2
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK                                      0x00000007
+
+#define TX_FES_STATUS_END_LTF_SIZE_OFFSET                                           0x00000020
+#define TX_FES_STATUS_END_LTF_SIZE_LSB                                              3
+#define TX_FES_STATUS_END_LTF_SIZE_MSB                                              4
+#define TX_FES_STATUS_END_LTF_SIZE_MASK                                             0x00000018
+
+#define TX_FES_STATUS_END_CP_SETTING_OFFSET                                         0x00000020
+#define TX_FES_STATUS_END_CP_SETTING_LSB                                            5
+#define TX_FES_STATUS_END_CP_SETTING_MSB                                            6
+#define TX_FES_STATUS_END_CP_SETTING_MASK                                           0x00000060
+
+#define TX_FES_STATUS_END_RESERVED_18A_OFFSET                                       0x00000020
+#define TX_FES_STATUS_END_RESERVED_18A_LSB                                          7
+#define TX_FES_STATUS_END_RESERVED_18A_MSB                                          11
+#define TX_FES_STATUS_END_RESERVED_18A_MASK                                         0x00000f80
+
+#define TX_FES_STATUS_END_DCM_OFFSET                                                0x00000020
+#define TX_FES_STATUS_END_DCM_LSB                                                   12
+#define TX_FES_STATUS_END_DCM_MSB                                                   12
+#define TX_FES_STATUS_END_DCM_MASK                                                  0x00001000
+
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET                                  0x00000020
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB                                     13
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB                                     13
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK                                    0x00002000
+
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET                                 0x00000020
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB                                    14
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB                                    14
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK                                   0x00004000
+
+#define TX_FES_STATUS_END_RESERVED_18B_OFFSET                                       0x00000020
+#define TX_FES_STATUS_END_RESERVED_18B_LSB                                          15
+#define TX_FES_STATUS_END_RESERVED_18B_MSB                                          15
+#define TX_FES_STATUS_END_RESERVED_18B_MASK                                         0x00008000
+
+#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET                                      0x00000020
+#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB                                         16
+#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB                                         23
+#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK                                        0x00ff0000
+
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET                                    0x00000020
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB                                       24
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB                                       31
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK                                      0xff000000
+
+#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET                            0x00000024
+#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB                               0
+#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB                               15
+#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK                              0x0000ffff
+
+#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET                              0x00000024
+#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB                                 16
+#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB                                 16
+#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK                                0x00010000
+
+#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET                             0x00000024
+#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB                                17
+#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB                                17
+#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK                               0x00020000
+
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET                          0x00000024
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_LSB                             18
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_MSB                             18
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_MASK                            0x00040000
+
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_OFFSET                          0x00000024
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_LSB                             19
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_MSB                             19
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_MASK                            0x00080000
+
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET                     0x00000024
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_LSB                        20
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_MSB                        20
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_MASK                       0x00100000
+
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_OFFSET                     0x00000024
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_LSB                        21
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_MSB                        21
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_MASK                       0x00200000
+
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET                          0x00000024
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_LSB                             22
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_MSB                             22
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_MASK                            0x00400000
+
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_OFFSET                          0x00000024
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_LSB                             23
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_MSB                             23
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_MASK                            0x00800000
+
+#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET                                     0x00000024
+#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB                                        24
+#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB                                        31
+#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK                                       0xff000000
+
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET                                0x00000028
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB                                   0
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB                                   15
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK                                  0x0000ffff
+
+#define TX_FES_STATUS_END_RESERVED_21A_OFFSET                                       0x00000028
+#define TX_FES_STATUS_END_RESERVED_21A_LSB                                          16
+#define TX_FES_STATUS_END_RESERVED_21A_MSB                                          19
+#define TX_FES_STATUS_END_RESERVED_21A_MASK                                         0x000f0000
+
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_OFFSET                                 0x00000028
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_LSB                                    20
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MSB                                    27
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MASK                                   0x0ff00000
+
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_OFFSET                          0x00000028
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_LSB                             28
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MSB                             28
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MASK                            0x10000000
+
+#define TX_FES_STATUS_END_RESERVED_21B_OFFSET                                       0x00000028
+#define TX_FES_STATUS_END_RESERVED_21B_LSB                                          29
+#define TX_FES_STATUS_END_RESERVED_21B_MSB                                          31
+#define TX_FES_STATUS_END_RESERVED_21B_MASK                                         0xe0000000
+
+#endif
diff --git a/hw/peach/v1/tx_fes_status_prot.h b/hw/peach/v1/tx_fes_status_prot.h
new file mode 100644
index 000000000000..b595140a53bf
--- /dev/null
+++ b/hw/peach/v1/tx_fes_status_prot.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_PROT_H_
+#define _TX_FES_STATUS_PROT_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 3
+
+struct tx_fes_status_prot {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t success                                                 :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      phytx_abort_request_info_valid                          :  1,
+                      reserved_0                                              : 20,
+                      pkt_type                                                :  4,
+                      dot11ax_su_extended                                     :  1,
+                      rate_mcs                                                :  4;
+             uint32_t frame_type                                              :  2,
+                      frame_subtype                                           :  4,
+                      rx_pwr_mgmt                                             :  1,
+                      status                                                  :  1,
+                      duration_field                                          : 16,
+                      reserved_1a                                             :  2,
+                      agc_cbw                                                 :  3,
+                      service_cbw                                             :  3;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t reserved_2a                                             : 16;
+#else
+             uint32_t rate_mcs                                                :  4,
+                      dot11ax_su_extended                                     :  1,
+                      pkt_type                                                :  4,
+                      reserved_0                                              : 20,
+                      phytx_abort_request_info_valid                          :  1,
+                      phytx_pkt_end_info_valid                                :  1,
+                      success                                                 :  1;
+             uint32_t service_cbw                                             :  3,
+                      agc_cbw                                                 :  3,
+                      reserved_1a                                             :  2,
+                      duration_field                                          : 16,
+                      status                                                  :  1,
+                      rx_pwr_mgmt                                             :  1,
+                      frame_subtype                                           :  4,
+                      frame_type                                              :  2;
+             uint32_t reserved_2a                                             : 16;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+#endif
+};
+
+#define TX_FES_STATUS_PROT_SUCCESS_OFFSET                                           0x00000000
+#define TX_FES_STATUS_PROT_SUCCESS_LSB                                              0
+#define TX_FES_STATUS_PROT_SUCCESS_MSB                                              0
+#define TX_FES_STATUS_PROT_SUCCESS_MASK                                             0x00000001
+
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET                          0x00000000
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB                             1
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB                             1
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK                            0x00000002
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET                    0x00000000
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB                       2
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB                       2
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK                      0x00000004
+
+#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET                                        0x00000000
+#define TX_FES_STATUS_PROT_RESERVED_0_LSB                                           3
+#define TX_FES_STATUS_PROT_RESERVED_0_MSB                                           22
+#define TX_FES_STATUS_PROT_RESERVED_0_MASK                                          0x007ffff8
+
+#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET                                          0x00000000
+#define TX_FES_STATUS_PROT_PKT_TYPE_LSB                                             23
+#define TX_FES_STATUS_PROT_PKT_TYPE_MSB                                             26
+#define TX_FES_STATUS_PROT_PKT_TYPE_MASK                                            0x07800000
+
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET                               0x00000000
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB                                  27
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB                                  27
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK                                 0x08000000
+
+#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET                                          0x00000000
+#define TX_FES_STATUS_PROT_RATE_MCS_LSB                                             28
+#define TX_FES_STATUS_PROT_RATE_MCS_MSB                                             31
+#define TX_FES_STATUS_PROT_RATE_MCS_MASK                                            0xf0000000
+
+#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET                                        0x00000004
+#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB                                           0
+#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB                                           1
+#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK                                          0x00000003
+
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET                                     0x00000004
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB                                        2
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB                                        5
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK                                       0x0000003c
+
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET                                       0x00000004
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB                                          6
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB                                          6
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK                                         0x00000040
+
+#define TX_FES_STATUS_PROT_STATUS_OFFSET                                            0x00000004
+#define TX_FES_STATUS_PROT_STATUS_LSB                                               7
+#define TX_FES_STATUS_PROT_STATUS_MSB                                               7
+#define TX_FES_STATUS_PROT_STATUS_MASK                                              0x00000080
+
+#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET                                    0x00000004
+#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB                                       8
+#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB                                       23
+#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK                                      0x00ffff00
+
+#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET                                       0x00000004
+#define TX_FES_STATUS_PROT_RESERVED_1A_LSB                                          24
+#define TX_FES_STATUS_PROT_RESERVED_1A_MSB                                          25
+#define TX_FES_STATUS_PROT_RESERVED_1A_MASK                                         0x03000000
+
+#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET                                           0x00000004
+#define TX_FES_STATUS_PROT_AGC_CBW_LSB                                              26
+#define TX_FES_STATUS_PROT_AGC_CBW_MSB                                              28
+#define TX_FES_STATUS_PROT_AGC_CBW_MASK                                             0x1c000000
+
+#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET                                       0x00000004
+#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB                                          29
+#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB                                          31
+#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK                                         0xe0000000
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000008
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB  0
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB  7
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET      0x00000008
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB         8
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB         13
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK        0x00003f00
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET         0x00000008
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB            14
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB            15
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK           0x0000c000
+
+#define TX_FES_STATUS_PROT_RESERVED_2A_OFFSET                                       0x00000008
+#define TX_FES_STATUS_PROT_RESERVED_2A_LSB                                          16
+#define TX_FES_STATUS_PROT_RESERVED_2A_MSB                                          31
+#define TX_FES_STATUS_PROT_RESERVED_2A_MASK                                         0xffff0000
+
+#endif
diff --git a/hw/peach/v1/tx_fes_status_start.h b/hw/peach/v1/tx_fes_status_start.h
new file mode 100644
index 000000000000..b8704980b178
--- /dev/null
+++ b/hw/peach/v1/tx_fes_status_start.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_START_H_
+#define _TX_FES_STATUS_START_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_START 4
+
+struct tx_fes_status_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t schedule_id                                             : 32;
+             uint32_t reserved_1a                                             :  8,
+                      transmit_start_reason                                   :  3,
+                      disabled_user_bitmap_36_32                              :  5,
+                      schedule_cmd_ring_id                                    :  5,
+                      fes_control_mode                                        :  2,
+                      schedule_try                                            :  4,
+                      medium_prot_type                                        :  3,
+                      reserved_1b                                             :  2;
+             uint32_t optimal_bw_try_count                                    :  4,
+                      number_of_users                                         :  7,
+                      coex_nack_count                                         :  5,
+                      cca_ed0                                                 : 16;
+             uint32_t disabled_user_bitmap_31_0                               : 32;
+#else
+             uint32_t schedule_id                                             : 32;
+             uint32_t reserved_1b                                             :  2,
+                      medium_prot_type                                        :  3,
+                      schedule_try                                            :  4,
+                      fes_control_mode                                        :  2,
+                      schedule_cmd_ring_id                                    :  5,
+                      disabled_user_bitmap_36_32                              :  5,
+                      transmit_start_reason                                   :  3,
+                      reserved_1a                                             :  8;
+             uint32_t cca_ed0                                                 : 16,
+                      coex_nack_count                                         :  5,
+                      number_of_users                                         :  7,
+                      optimal_bw_try_count                                    :  4;
+             uint32_t disabled_user_bitmap_31_0                               : 32;
+#endif
+};
+
+#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET                                      0x00000000
+#define TX_FES_STATUS_START_SCHEDULE_ID_LSB                                         0
+#define TX_FES_STATUS_START_SCHEDULE_ID_MSB                                         31
+#define TX_FES_STATUS_START_SCHEDULE_ID_MASK                                        0xffffffff
+
+#define TX_FES_STATUS_START_RESERVED_1A_OFFSET                                      0x00000004
+#define TX_FES_STATUS_START_RESERVED_1A_LSB                                         0
+#define TX_FES_STATUS_START_RESERVED_1A_MSB                                         7
+#define TX_FES_STATUS_START_RESERVED_1A_MASK                                        0x000000ff
+
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET                            0x00000004
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB                               8
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB                               10
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK                              0x00000700
+
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET                       0x00000004
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB                          11
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB                          15
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK                         0x0000f800
+
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET                             0x00000004
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB                                16
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB                                20
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK                               0x001f0000
+
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET                                 0x00000004
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB                                    21
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB                                    22
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK                                   0x00600000
+
+#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET                                     0x00000004
+#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB                                        23
+#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB                                        26
+#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK                                       0x07800000
+
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET                                 0x00000004
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB                                    27
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB                                    29
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK                                   0x38000000
+
+#define TX_FES_STATUS_START_RESERVED_1B_OFFSET                                      0x00000004
+#define TX_FES_STATUS_START_RESERVED_1B_LSB                                         30
+#define TX_FES_STATUS_START_RESERVED_1B_MSB                                         31
+#define TX_FES_STATUS_START_RESERVED_1B_MASK                                        0xc0000000
+
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET                             0x00000008
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB                                0
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB                                3
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK                               0x0000000f
+
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET                                  0x00000008
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB                                     4
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB                                     10
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK                                    0x000007f0
+
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET                                  0x00000008
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB                                     11
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB                                     15
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK                                    0x0000f800
+
+#define TX_FES_STATUS_START_CCA_ED0_OFFSET                                          0x00000008
+#define TX_FES_STATUS_START_CCA_ED0_LSB                                             16
+#define TX_FES_STATUS_START_CCA_ED0_MSB                                             31
+#define TX_FES_STATUS_START_CCA_ED0_MASK                                            0xffff0000
+
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET                        0x0000000c
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB                           0
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB                           31
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK                          0xffffffff
+
+#endif
diff --git a/hw/peach/v1/tx_fes_status_start_ppdu.h b/hw/peach/v1/tx_fes_status_start_ppdu.h
new file mode 100644
index 000000000000..21fbf64bae9c
--- /dev/null
+++ b/hw/peach/v1/tx_fes_status_start_ppdu.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_START_PPDU_H_
+#define _TX_FES_STATUS_START_PPDU_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 4
+
+struct tx_fes_status_start_ppdu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t ppdu_timestamp_lower_32                                 : 32;
+             uint32_t ppdu_timestamp_upper_32                                 : 32;
+             uint32_t subband_mask                                            : 16,
+                      ndp_frame                                               :  2,
+                      reserved_2b                                             :  2,
+                      coex_based_tx_bw                                        :  3,
+                      coex_based_ant_mask                                     :  8,
+                      reserved_2c                                             :  1;
+             uint32_t coex_based_tx_pwr_shared_ant                            :  8,
+                      coex_based_tx_pwr_ant                                   :  8,
+                      concurrent_bt_tx                                        :  1,
+                      concurrent_wlan_tx                                      :  1,
+                      concurrent_wan_tx                                       :  1,
+                      concurrent_wan_rx                                       :  1,
+                      coex_pwr_reduction_bt                                   :  1,
+                      coex_pwr_reduction_wlan                                 :  1,
+                      coex_pwr_reduction_wan                                  :  1,
+                      coex_result_alt_based                                   :  1,
+                      request_packet_bw                                       :  3,
+                      response_type                                           :  5;
+#else
+             uint32_t ppdu_timestamp_lower_32                                 : 32;
+             uint32_t ppdu_timestamp_upper_32                                 : 32;
+             uint32_t reserved_2c                                             :  1,
+                      coex_based_ant_mask                                     :  8,
+                      coex_based_tx_bw                                        :  3,
+                      reserved_2b                                             :  2,
+                      ndp_frame                                               :  2,
+                      subband_mask                                            : 16;
+             uint32_t response_type                                           :  5,
+                      request_packet_bw                                       :  3,
+                      coex_result_alt_based                                   :  1,
+                      coex_pwr_reduction_wan                                  :  1,
+                      coex_pwr_reduction_wlan                                 :  1,
+                      coex_pwr_reduction_bt                                   :  1,
+                      concurrent_wan_rx                                       :  1,
+                      concurrent_wan_tx                                       :  1,
+                      concurrent_wlan_tx                                      :  1,
+                      concurrent_bt_tx                                        :  1,
+                      coex_based_tx_pwr_ant                                   :  8,
+                      coex_based_tx_pwr_shared_ant                            :  8;
+#endif
+};
+
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET                     0x00000000
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB                        0
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB                        31
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK                       0xffffffff
+
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET                     0x00000004
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB                        0
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB                        31
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK                       0xffffffff
+
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET                                0x00000008
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB                                   0
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB                                   15
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK                                  0x0000ffff
+
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET                                   0x00000008
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB                                      16
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB                                      17
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK                                     0x00030000
+
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET                                 0x00000008
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB                                    18
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB                                    19
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK                                   0x000c0000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET                            0x00000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB                               20
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB                               22
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK                              0x00700000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET                         0x00000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB                            23
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB                            30
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK                           0x7f800000
+
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET                                 0x00000008
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB                                    31
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB                                    31
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK                                   0x80000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET                0x0000000c
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB                   0
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB                   7
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK                  0x000000ff
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET                       0x0000000c
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB                          8
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB                          15
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK                         0x0000ff00
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET                            0x0000000c
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB                               16
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB                               16
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK                              0x00010000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET                          0x0000000c
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB                             17
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB                             17
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK                            0x00020000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET                           0x0000000c
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB                              18
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB                              18
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK                             0x00040000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET                           0x0000000c
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB                              19
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB                              19
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK                             0x00080000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET                       0x0000000c
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB                          20
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB                          20
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK                         0x00100000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET                     0x0000000c
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB                        21
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB                        21
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK                       0x00200000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET                      0x0000000c
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB                         22
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB                         22
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK                        0x00400000
+
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET                       0x0000000c
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB                          23
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB                          23
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK                         0x00800000
+
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET                           0x0000000c
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB                              24
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB                              26
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK                             0x07000000
+
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET                               0x0000000c
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB                                  27
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB                                  31
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK                                 0xf8000000
+
+#endif
diff --git a/hw/peach/v1/tx_fes_status_start_prot.h b/hw/peach/v1/tx_fes_status_start_prot.h
new file mode 100644
index 000000000000..4e3bbe0004a5
--- /dev/null
+++ b/hw/peach/v1/tx_fes_status_start_prot.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_START_PROT_H_
+#define _TX_FES_STATUS_START_PROT_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 4
+
+struct tx_fes_status_start_prot {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t prot_timestamp_lower_32                                 : 32;
+             uint32_t prot_timestamp_upper_32                                 : 32;
+             uint32_t subband_mask                                            : 16,
+                      reserved_2b                                             :  4,
+                      prot_coex_based_tx_bw                                   :  3,
+                      prot_coex_based_ant_mask                                :  8,
+                      prot_coex_result_alt_based                              :  1;
+             uint32_t prot_coex_tx_pwr_shared_ant                             :  8,
+                      prot_coex_tx_pwr_ant                                    :  8,
+                      prot_concurrent_bt_tx                                   :  1,
+                      prot_concurrent_wlan_tx                                 :  1,
+                      prot_concurrent_wan_tx                                  :  1,
+                      prot_concurrent_wan_rx                                  :  1,
+                      prot_coex_pwr_reduction_bt                              :  1,
+                      prot_coex_pwr_reduction_wlan                            :  1,
+                      prot_coex_pwr_reduction_wan                             :  1,
+                      prot_request_packet_bw                                  :  3,
+                      response_type                                           :  5,
+                      reserved_3a                                             :  1;
+#else
+             uint32_t prot_timestamp_lower_32                                 : 32;
+             uint32_t prot_timestamp_upper_32                                 : 32;
+             uint32_t prot_coex_result_alt_based                              :  1,
+                      prot_coex_based_ant_mask                                :  8,
+                      prot_coex_based_tx_bw                                   :  3,
+                      reserved_2b                                             :  4,
+                      subband_mask                                            : 16;
+             uint32_t reserved_3a                                             :  1,
+                      response_type                                           :  5,
+                      prot_request_packet_bw                                  :  3,
+                      prot_coex_pwr_reduction_wan                             :  1,
+                      prot_coex_pwr_reduction_wlan                            :  1,
+                      prot_coex_pwr_reduction_bt                              :  1,
+                      prot_concurrent_wan_rx                                  :  1,
+                      prot_concurrent_wan_tx                                  :  1,
+                      prot_concurrent_wlan_tx                                 :  1,
+                      prot_concurrent_bt_tx                                   :  1,
+                      prot_coex_tx_pwr_ant                                    :  8,
+                      prot_coex_tx_pwr_shared_ant                             :  8;
+#endif
+};
+
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET                     0x00000000
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB                        0
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB                        31
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK                       0xffffffff
+
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET                     0x00000004
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB                        0
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB                        31
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK                       0xffffffff
+
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET                                0x00000008
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB                                   0
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB                                   15
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK                                  0x0000ffff
+
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET                                 0x00000008
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB                                    16
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB                                    19
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK                                   0x000f0000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET                       0x00000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB                          20
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB                          22
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK                         0x00700000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET                    0x00000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB                       23
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB                       30
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK                      0x7f800000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET                  0x00000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB                     31
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB                     31
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK                    0x80000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET                 0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB                    0
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB                    7
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK                   0x000000ff
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET                        0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB                           8
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB                           15
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK                          0x0000ff00
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET                       0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB                          16
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB                          16
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK                         0x00010000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET                     0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB                        17
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB                        17
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK                       0x00020000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET                      0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB                         18
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB                         18
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK                        0x00040000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET                      0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB                         19
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB                         19
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK                        0x00080000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET                  0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB                     20
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB                     20
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK                    0x00100000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET                0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB                   21
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB                   21
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK                  0x00200000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET                 0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB                    22
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB                    22
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK                   0x00400000
+
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET                      0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB                         23
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB                         25
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK                        0x03800000
+
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET                               0x0000000c
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB                                  26
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB                                  30
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK                                 0x7c000000
+
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET                                 0x0000000c
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB                                    31
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB                                    31
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK                                   0x80000000
+
+#endif
diff --git a/hw/peach/v1/tx_fes_status_user_ppdu.h b/hw/peach/v1/tx_fes_status_user_ppdu.h
new file mode 100644
index 000000000000..a18815551738
--- /dev/null
+++ b/hw/peach/v1/tx_fes_status_user_ppdu.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_USER_PPDU_H_
+#define _TX_FES_STATUS_USER_PPDU_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6
+
+struct tx_fes_status_user_ppdu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t underflow_mpdu_count                                    :  9,
+                      data_underflow_warning                                  :  2,
+                      bw_drop_underflow_warning                               :  1,
+                      qc_eosp_setting                                         :  1,
+                      fc_more_data_setting                                    :  1,
+                      fc_pwr_mgt_setting                                      :  1,
+                      mpdu_tx_count                                           :  9,
+                      user_blocked                                            :  1,
+                      pre_trig_response_delim_count                           :  7;
+             uint32_t underflow_byte_count                                    : 16,
+                      coex_abort_mpdu_count_valid                             :  1,
+                      coex_abort_mpdu_count                                   :  9,
+                      transmitted_tid                                         :  4,
+                      txdma_dropped_mpdu_warning                              :  1,
+                      reserved_1                                              :  1;
+             uint32_t duration                                                : 16,
+                      num_eof_delim_added                                     : 16;
+             uint32_t psdu_octet                                              : 24,
+                      qos_buf_state                                           :  8;
+             uint32_t num_null_delim_added                                    : 22,
+                      reserved_4a                                             :  2,
+                      cv_corr_user_valid_in_phy                               :  1,
+                      nss                                                     :  3,
+                      mcs                                                     :  4;
+             uint32_t ht_control                                              : 32;
+#else
+             uint32_t pre_trig_response_delim_count                           :  7,
+                      user_blocked                                            :  1,
+                      mpdu_tx_count                                           :  9,
+                      fc_pwr_mgt_setting                                      :  1,
+                      fc_more_data_setting                                    :  1,
+                      qc_eosp_setting                                         :  1,
+                      bw_drop_underflow_warning                               :  1,
+                      data_underflow_warning                                  :  2,
+                      underflow_mpdu_count                                    :  9;
+             uint32_t reserved_1                                              :  1,
+                      txdma_dropped_mpdu_warning                              :  1,
+                      transmitted_tid                                         :  4,
+                      coex_abort_mpdu_count                                   :  9,
+                      coex_abort_mpdu_count_valid                             :  1,
+                      underflow_byte_count                                    : 16;
+             uint32_t num_eof_delim_added                                     : 16,
+                      duration                                                : 16;
+             uint32_t qos_buf_state                                           :  8,
+                      psdu_octet                                              : 24;
+             uint32_t mcs                                                     :  4,
+                      nss                                                     :  3,
+                      cv_corr_user_valid_in_phy                               :  1,
+                      reserved_4a                                             :  2,
+                      num_null_delim_added                                    : 22;
+             uint32_t ht_control                                              : 32;
+#endif
+};
+
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET                         0x00000000
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB                            0
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB                            8
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK                           0x000001ff
+
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET                       0x00000000
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB                          9
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB                          10
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK                         0x00000600
+
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET                    0x00000000
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB                       11
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB                       11
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK                      0x00000800
+
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET                              0x00000000
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB                                 12
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB                                 12
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK                                0x00001000
+
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET                         0x00000000
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB                            13
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB                            13
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK                           0x00002000
+
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET                           0x00000000
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB                              14
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB                              14
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK                             0x00004000
+
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET                                0x00000000
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB                                   15
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB                                   23
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK                                  0x00ff8000
+
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET                                 0x00000000
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB                                    24
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB                                    24
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK                                   0x01000000
+
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET                0x00000000
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB                   25
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB                   31
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK                  0xfe000000
+
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET                         0x00000004
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB                            0
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB                            15
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK                           0x0000ffff
+
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET                  0x00000004
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB                     16
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB                     16
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK                    0x00010000
+
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET                        0x00000004
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB                           17
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB                           25
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK                          0x03fe0000
+
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET                              0x00000004
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB                                 26
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB                                 29
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK                                0x3c000000
+
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET                   0x00000004
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB                      30
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB                      30
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK                     0x40000000
+
+#define TX_FES_STATUS_USER_PPDU_RESERVED_1_OFFSET                                   0x00000004
+#define TX_FES_STATUS_USER_PPDU_RESERVED_1_LSB                                      31
+#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MSB                                      31
+#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MASK                                     0x80000000
+
+#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET                                     0x00000008
+#define TX_FES_STATUS_USER_PPDU_DURATION_LSB                                        0
+#define TX_FES_STATUS_USER_PPDU_DURATION_MSB                                        15
+#define TX_FES_STATUS_USER_PPDU_DURATION_MASK                                       0x0000ffff
+
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET                          0x00000008
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB                             16
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB                             31
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK                            0xffff0000
+
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET                                   0x0000000c
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB                                      0
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB                                      23
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK                                     0x00ffffff
+
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET                                0x0000000c
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB                                   24
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB                                   31
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK                                  0xff000000
+
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET                         0x00000010
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB                            0
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB                            21
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK                           0x003fffff
+
+#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_OFFSET                                  0x00000010
+#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_LSB                                     22
+#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MSB                                     23
+#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MASK                                    0x00c00000
+
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET                    0x00000010
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB                       24
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB                       24
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK                      0x01000000
+
+#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET                                          0x00000010
+#define TX_FES_STATUS_USER_PPDU_NSS_LSB                                             25
+#define TX_FES_STATUS_USER_PPDU_NSS_MSB                                             27
+#define TX_FES_STATUS_USER_PPDU_NSS_MASK                                            0x0e000000
+
+#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET                                          0x00000010
+#define TX_FES_STATUS_USER_PPDU_MCS_LSB                                             28
+#define TX_FES_STATUS_USER_PPDU_MCS_MSB                                             31
+#define TX_FES_STATUS_USER_PPDU_MCS_MASK                                            0xf0000000
+
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET                                   0x00000014
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB                                      0
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB                                      31
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK                                     0xffffffff
+
+#endif
diff --git a/hw/peach/v1/tx_fes_status_user_response.h b/hw/peach/v1/tx_fes_status_user_response.h
new file mode 100644
index 000000000000..f1255bdb12b3
--- /dev/null
+++ b/hw/peach/v1/tx_fes_status_user_response.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_USER_RESPONSE_H_
+#define _TX_FES_STATUS_USER_RESPONSE_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2
+
+struct tx_fes_status_user_response {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t fes_transmit_result                                     :  4,
+                      reserved_0                                              : 28;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+             uint16_t reserved_after_struct16                                 : 16;
+#else
+             uint32_t reserved_0                                              : 28,
+                      fes_transmit_result                                     :  4;
+             uint32_t reserved_after_struct16                                 : 16;
+             struct   phytx_abort_request_info                                  phytx_abort_request_info_details;
+#endif
+};
+
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET                      0x00000000
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB                         0
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB                         3
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK                        0x0000000f
+
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET                               0x00000000
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB                                  4
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB                                  31
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK                                 0xfffffff0
+
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff
+
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000004
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00
+
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000004
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB   14
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB   15
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK  0x0000c000
+
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET                  0x00000004
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB                     16
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB                     31
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK                    0xffff0000
+
+#endif
diff --git a/hw/peach/v1/tx_flush_req.h b/hw/peach/v1/tx_flush_req.h
new file mode 100644
index 000000000000..1ee52b57ad22
--- /dev/null
+++ b/hw/peach/v1/tx_flush_req.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FLUSH_REQ_H_
+#define _TX_FLUSH_REQ_H_
+
+#define NUM_OF_DWORDS_TX_FLUSH_REQ 1
+
+struct tx_flush_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t flush_req_reason                                        :  8,
+                      phytx_abort_reason                                      :  8,
+                      flush_req_user_number_or_link_id                        :  6,
+                      mlo_abort_reason                                        :  5,
+                      reserved_0a                                             :  5;
+#else
+             uint32_t reserved_0a                                             :  5,
+                      mlo_abort_reason                                        :  5,
+                      flush_req_user_number_or_link_id                        :  6,
+                      phytx_abort_reason                                      :  8,
+                      flush_req_reason                                        :  8;
+#endif
+};
+
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET                                        0x00000000
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB                                           0
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB                                           7
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK                                          0x000000ff
+
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET                                      0x00000000
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB                                         8
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB                                         15
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK                                        0x0000ff00
+
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET                        0x00000000
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB                           16
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB                           21
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK                          0x003f0000
+
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET                                        0x00000000
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB                                           22
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB                                           26
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK                                          0x07c00000
+
+#define TX_FLUSH_REQ_RESERVED_0A_OFFSET                                             0x00000000
+#define TX_FLUSH_REQ_RESERVED_0A_LSB                                                27
+#define TX_FLUSH_REQ_RESERVED_0A_MSB                                                31
+#define TX_FLUSH_REQ_RESERVED_0A_MASK                                               0xf8000000
+
+#endif
diff --git a/hw/peach/v1/tx_mpdu_start.h b/hw/peach/v1/tx_mpdu_start.h
new file mode 100644
index 000000000000..aa7bebca07ad
--- /dev/null
+++ b/hw/peach/v1/tx_mpdu_start.h
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_MPDU_START_H_
+#define _TX_MPDU_START_H_
+
+#define NUM_OF_DWORDS_TX_MPDU_START 9
+
+struct tx_mpdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mpdu_length                                             : 14,
+                      frame_not_from_tqm                                      :  1,
+                      vht_control_present                                     :  1,
+                      mpdu_header_length                                      :  8,
+                      retry_count                                             :  7,
+                      wds                                                     :  1;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t pn_47_32                                                : 16,
+                      mpdu_sequence_number                                    : 12,
+                      raw_already_encrypted                                   :  1,
+                      frame_type                                              :  2,
+                      txdma_dropped_mpdu_warning                              :  1;
+             uint32_t iv_byte_0                                               :  8,
+                      iv_byte_1                                               :  8,
+                      iv_byte_2                                               :  8,
+                      iv_byte_3                                               :  8;
+             uint32_t iv_byte_4                                               :  8,
+                      iv_byte_5                                               :  8,
+                      iv_byte_6                                               :  8,
+                      iv_byte_7                                               :  8;
+             uint32_t iv_byte_8                                               :  8,
+                      iv_byte_9                                               :  8,
+                      iv_byte_10                                              :  8,
+                      iv_byte_11                                              :  8;
+             uint32_t iv_byte_12                                              :  8,
+                      iv_byte_13                                              :  8,
+                      iv_byte_14                                              :  8,
+                      iv_byte_15                                              :  8;
+             uint32_t iv_byte_16                                              :  8,
+                      iv_byte_17                                              :  8,
+                      iv_len                                                  :  5,
+                      icv_len                                                 :  5,
+                      vht_control_offset                                      :  6;
+             uint32_t mpdu_type                                               :  1,
+                      transmit_bw_restriction                                 :  1,
+                      allowed_transmit_bw                                     :  4,
+                      tx_notify_frame                                         :  3,
+                      reserved_8a                                             : 23;
+#else
+             uint32_t wds                                                     :  1,
+                      retry_count                                             :  7,
+                      mpdu_header_length                                      :  8,
+                      vht_control_present                                     :  1,
+                      frame_not_from_tqm                                      :  1,
+                      mpdu_length                                             : 14;
+             uint32_t pn_31_0                                                 : 32;
+             uint32_t txdma_dropped_mpdu_warning                              :  1,
+                      frame_type                                              :  2,
+                      raw_already_encrypted                                   :  1,
+                      mpdu_sequence_number                                    : 12,
+                      pn_47_32                                                : 16;
+             uint32_t iv_byte_3                                               :  8,
+                      iv_byte_2                                               :  8,
+                      iv_byte_1                                               :  8,
+                      iv_byte_0                                               :  8;
+             uint32_t iv_byte_7                                               :  8,
+                      iv_byte_6                                               :  8,
+                      iv_byte_5                                               :  8,
+                      iv_byte_4                                               :  8;
+             uint32_t iv_byte_11                                              :  8,
+                      iv_byte_10                                              :  8,
+                      iv_byte_9                                               :  8,
+                      iv_byte_8                                               :  8;
+             uint32_t iv_byte_15                                              :  8,
+                      iv_byte_14                                              :  8,
+                      iv_byte_13                                              :  8,
+                      iv_byte_12                                              :  8;
+             uint32_t vht_control_offset                                      :  6,
+                      icv_len                                                 :  5,
+                      iv_len                                                  :  5,
+                      iv_byte_17                                              :  8,
+                      iv_byte_16                                              :  8;
+             uint32_t reserved_8a                                             : 23,
+                      tx_notify_frame                                         :  3,
+                      allowed_transmit_bw                                     :  4,
+                      transmit_bw_restriction                                 :  1,
+                      mpdu_type                                               :  1;
+#endif
+};
+
+#define TX_MPDU_START_MPDU_LENGTH_OFFSET                                            0x00000000
+#define TX_MPDU_START_MPDU_LENGTH_LSB                                               0
+#define TX_MPDU_START_MPDU_LENGTH_MSB                                               13
+#define TX_MPDU_START_MPDU_LENGTH_MASK                                              0x00003fff
+
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET                                     0x00000000
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB                                        14
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB                                        14
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK                                       0x00004000
+
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET                                    0x00000000
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB                                       15
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB                                       15
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK                                      0x00008000
+
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET                                     0x00000000
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB                                        16
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB                                        23
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK                                       0x00ff0000
+
+#define TX_MPDU_START_RETRY_COUNT_OFFSET                                            0x00000000
+#define TX_MPDU_START_RETRY_COUNT_LSB                                               24
+#define TX_MPDU_START_RETRY_COUNT_MSB                                               30
+#define TX_MPDU_START_RETRY_COUNT_MASK                                              0x7f000000
+
+#define TX_MPDU_START_WDS_OFFSET                                                    0x00000000
+#define TX_MPDU_START_WDS_LSB                                                       31
+#define TX_MPDU_START_WDS_MSB                                                       31
+#define TX_MPDU_START_WDS_MASK                                                      0x80000000
+
+#define TX_MPDU_START_PN_31_0_OFFSET                                                0x00000004
+#define TX_MPDU_START_PN_31_0_LSB                                                   0
+#define TX_MPDU_START_PN_31_0_MSB                                                   31
+#define TX_MPDU_START_PN_31_0_MASK                                                  0xffffffff
+
+#define TX_MPDU_START_PN_47_32_OFFSET                                               0x00000008
+#define TX_MPDU_START_PN_47_32_LSB                                                  0
+#define TX_MPDU_START_PN_47_32_MSB                                                  15
+#define TX_MPDU_START_PN_47_32_MASK                                                 0x0000ffff
+
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET                                   0x00000008
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB                                      16
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB                                      27
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK                                     0x0fff0000
+
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET                                  0x00000008
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB                                     28
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB                                     28
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK                                    0x10000000
+
+#define TX_MPDU_START_FRAME_TYPE_OFFSET                                             0x00000008
+#define TX_MPDU_START_FRAME_TYPE_LSB                                                29
+#define TX_MPDU_START_FRAME_TYPE_MSB                                                30
+#define TX_MPDU_START_FRAME_TYPE_MASK                                               0x60000000
+
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET                             0x00000008
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB                                31
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB                                31
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK                               0x80000000
+
+#define TX_MPDU_START_IV_BYTE_0_OFFSET                                              0x0000000c
+#define TX_MPDU_START_IV_BYTE_0_LSB                                                 0
+#define TX_MPDU_START_IV_BYTE_0_MSB                                                 7
+#define TX_MPDU_START_IV_BYTE_0_MASK                                                0x000000ff
+
+#define TX_MPDU_START_IV_BYTE_1_OFFSET                                              0x0000000c
+#define TX_MPDU_START_IV_BYTE_1_LSB                                                 8
+#define TX_MPDU_START_IV_BYTE_1_MSB                                                 15
+#define TX_MPDU_START_IV_BYTE_1_MASK                                                0x0000ff00
+
+#define TX_MPDU_START_IV_BYTE_2_OFFSET                                              0x0000000c
+#define TX_MPDU_START_IV_BYTE_2_LSB                                                 16
+#define TX_MPDU_START_IV_BYTE_2_MSB                                                 23
+#define TX_MPDU_START_IV_BYTE_2_MASK                                                0x00ff0000
+
+#define TX_MPDU_START_IV_BYTE_3_OFFSET                                              0x0000000c
+#define TX_MPDU_START_IV_BYTE_3_LSB                                                 24
+#define TX_MPDU_START_IV_BYTE_3_MSB                                                 31
+#define TX_MPDU_START_IV_BYTE_3_MASK                                                0xff000000
+
+#define TX_MPDU_START_IV_BYTE_4_OFFSET                                              0x00000010
+#define TX_MPDU_START_IV_BYTE_4_LSB                                                 0
+#define TX_MPDU_START_IV_BYTE_4_MSB                                                 7
+#define TX_MPDU_START_IV_BYTE_4_MASK                                                0x000000ff
+
+#define TX_MPDU_START_IV_BYTE_5_OFFSET                                              0x00000010
+#define TX_MPDU_START_IV_BYTE_5_LSB                                                 8
+#define TX_MPDU_START_IV_BYTE_5_MSB                                                 15
+#define TX_MPDU_START_IV_BYTE_5_MASK                                                0x0000ff00
+
+#define TX_MPDU_START_IV_BYTE_6_OFFSET                                              0x00000010
+#define TX_MPDU_START_IV_BYTE_6_LSB                                                 16
+#define TX_MPDU_START_IV_BYTE_6_MSB                                                 23
+#define TX_MPDU_START_IV_BYTE_6_MASK                                                0x00ff0000
+
+#define TX_MPDU_START_IV_BYTE_7_OFFSET                                              0x00000010
+#define TX_MPDU_START_IV_BYTE_7_LSB                                                 24
+#define TX_MPDU_START_IV_BYTE_7_MSB                                                 31
+#define TX_MPDU_START_IV_BYTE_7_MASK                                                0xff000000
+
+#define TX_MPDU_START_IV_BYTE_8_OFFSET                                              0x00000014
+#define TX_MPDU_START_IV_BYTE_8_LSB                                                 0
+#define TX_MPDU_START_IV_BYTE_8_MSB                                                 7
+#define TX_MPDU_START_IV_BYTE_8_MASK                                                0x000000ff
+
+#define TX_MPDU_START_IV_BYTE_9_OFFSET                                              0x00000014
+#define TX_MPDU_START_IV_BYTE_9_LSB                                                 8
+#define TX_MPDU_START_IV_BYTE_9_MSB                                                 15
+#define TX_MPDU_START_IV_BYTE_9_MASK                                                0x0000ff00
+
+#define TX_MPDU_START_IV_BYTE_10_OFFSET                                             0x00000014
+#define TX_MPDU_START_IV_BYTE_10_LSB                                                16
+#define TX_MPDU_START_IV_BYTE_10_MSB                                                23
+#define TX_MPDU_START_IV_BYTE_10_MASK                                               0x00ff0000
+
+#define TX_MPDU_START_IV_BYTE_11_OFFSET                                             0x00000014
+#define TX_MPDU_START_IV_BYTE_11_LSB                                                24
+#define TX_MPDU_START_IV_BYTE_11_MSB                                                31
+#define TX_MPDU_START_IV_BYTE_11_MASK                                               0xff000000
+
+#define TX_MPDU_START_IV_BYTE_12_OFFSET                                             0x00000018
+#define TX_MPDU_START_IV_BYTE_12_LSB                                                0
+#define TX_MPDU_START_IV_BYTE_12_MSB                                                7
+#define TX_MPDU_START_IV_BYTE_12_MASK                                               0x000000ff
+
+#define TX_MPDU_START_IV_BYTE_13_OFFSET                                             0x00000018
+#define TX_MPDU_START_IV_BYTE_13_LSB                                                8
+#define TX_MPDU_START_IV_BYTE_13_MSB                                                15
+#define TX_MPDU_START_IV_BYTE_13_MASK                                               0x0000ff00
+
+#define TX_MPDU_START_IV_BYTE_14_OFFSET                                             0x00000018
+#define TX_MPDU_START_IV_BYTE_14_LSB                                                16
+#define TX_MPDU_START_IV_BYTE_14_MSB                                                23
+#define TX_MPDU_START_IV_BYTE_14_MASK                                               0x00ff0000
+
+#define TX_MPDU_START_IV_BYTE_15_OFFSET                                             0x00000018
+#define TX_MPDU_START_IV_BYTE_15_LSB                                                24
+#define TX_MPDU_START_IV_BYTE_15_MSB                                                31
+#define TX_MPDU_START_IV_BYTE_15_MASK                                               0xff000000
+
+#define TX_MPDU_START_IV_BYTE_16_OFFSET                                             0x0000001c
+#define TX_MPDU_START_IV_BYTE_16_LSB                                                0
+#define TX_MPDU_START_IV_BYTE_16_MSB                                                7
+#define TX_MPDU_START_IV_BYTE_16_MASK                                               0x000000ff
+
+#define TX_MPDU_START_IV_BYTE_17_OFFSET                                             0x0000001c
+#define TX_MPDU_START_IV_BYTE_17_LSB                                                8
+#define TX_MPDU_START_IV_BYTE_17_MSB                                                15
+#define TX_MPDU_START_IV_BYTE_17_MASK                                               0x0000ff00
+
+#define TX_MPDU_START_IV_LEN_OFFSET                                                 0x0000001c
+#define TX_MPDU_START_IV_LEN_LSB                                                    16
+#define TX_MPDU_START_IV_LEN_MSB                                                    20
+#define TX_MPDU_START_IV_LEN_MASK                                                   0x001f0000
+
+#define TX_MPDU_START_ICV_LEN_OFFSET                                                0x0000001c
+#define TX_MPDU_START_ICV_LEN_LSB                                                   21
+#define TX_MPDU_START_ICV_LEN_MSB                                                   25
+#define TX_MPDU_START_ICV_LEN_MASK                                                  0x03e00000
+
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET                                     0x0000001c
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB                                        26
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB                                        31
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK                                       0xfc000000
+
+#define TX_MPDU_START_MPDU_TYPE_OFFSET                                              0x00000020
+#define TX_MPDU_START_MPDU_TYPE_LSB                                                 0
+#define TX_MPDU_START_MPDU_TYPE_MSB                                                 0
+#define TX_MPDU_START_MPDU_TYPE_MASK                                                0x00000001
+
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET                                0x00000020
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB                                   1
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB                                   1
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK                                  0x00000002
+
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET                                    0x00000020
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB                                       2
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB                                       5
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK                                      0x0000003c
+
+#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET                                        0x00000020
+#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB                                           6
+#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB                                           8
+#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK                                          0x000001c0
+
+#define TX_MPDU_START_RESERVED_8A_OFFSET                                            0x00000020
+#define TX_MPDU_START_RESERVED_8A_LSB                                               9
+#define TX_MPDU_START_RESERVED_8A_MSB                                               31
+#define TX_MPDU_START_RESERVED_8A_MASK                                              0xfffffe00
+
+#endif
diff --git a/hw/peach/v1/tx_msdu_extension.h b/hw/peach/v1/tx_msdu_extension.h
new file mode 100644
index 000000000000..6bceb28ed838
--- /dev/null
+++ b/hw/peach/v1/tx_msdu_extension.h
@@ -0,0 +1,372 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_MSDU_EXTENSION_H_
+#define _TX_MSDU_EXTENSION_H_
+
+#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
+
+struct tx_msdu_extension {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tso_enable                                              :  1,
+                      reserved_0a                                             :  6,
+                      tcp_flag                                                :  9,
+                      tcp_flag_mask                                           :  9,
+                      reserved_0b                                             :  7;
+             uint32_t l2_length                                               : 16,
+                      ip_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t ip_identification                                       : 16,
+                      udp_length                                              : 16;
+             uint32_t checksum_offset                                         : 14,
+                      partial_checksum_en                                     :  1,
+                      reserved_4a                                             :  1,
+                      payload_start_offset                                    : 14,
+                      reserved_4b                                             :  2;
+             uint32_t payload_end_offset                                      : 14,
+                      reserved_5a                                             :  2,
+                      wds                                                     :  1,
+                      reserved_5b                                             : 15;
+             uint32_t buf0_ptr_31_0                                           : 32;
+             uint32_t buf0_ptr_39_32                                          :  8,
+                      extn_override                                           :  1,
+                      encap_type                                              :  2,
+                      encrypt_type                                            :  4,
+                      tqm_no_drop                                             :  1,
+                      buf0_len                                                : 16;
+             uint32_t buf1_ptr_31_0                                           : 32;
+             uint32_t buf1_ptr_39_32                                          :  8,
+                      epd                                                     :  1,
+                      mesh_enable                                             :  2,
+                      reserved_9a                                             :  5,
+                      buf1_len                                                : 16;
+             uint32_t buf2_ptr_31_0                                           : 32;
+             uint32_t buf2_ptr_39_32                                          :  8,
+                      dscp_tid_table_num                                      :  6,
+                      reserved_11a                                            :  2,
+                      buf2_len                                                : 16;
+             uint32_t buf3_ptr_31_0                                           : 32;
+             uint32_t buf3_ptr_39_32                                          :  8,
+                      reserved_13a                                            :  8,
+                      buf3_len                                                : 16;
+             uint32_t buf4_ptr_31_0                                           : 32;
+             uint32_t buf4_ptr_39_32                                          :  8,
+                      reserved_15a                                            :  8,
+                      buf4_len                                                : 16;
+             uint32_t buf5_ptr_31_0                                           : 32;
+             uint32_t buf5_ptr_39_32                                          :  8,
+                      reserved_17a                                            :  8,
+                      buf5_len                                                : 16;
+#else
+             uint32_t reserved_0b                                             :  7,
+                      tcp_flag_mask                                           :  9,
+                      tcp_flag                                                :  9,
+                      reserved_0a                                             :  6,
+                      tso_enable                                              :  1;
+             uint32_t ip_length                                               : 16,
+                      l2_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t udp_length                                              : 16,
+                      ip_identification                                       : 16;
+             uint32_t reserved_4b                                             :  2,
+                      payload_start_offset                                    : 14,
+                      reserved_4a                                             :  1,
+                      partial_checksum_en                                     :  1,
+                      checksum_offset                                         : 14;
+             uint32_t reserved_5b                                             : 15,
+                      wds                                                     :  1,
+                      reserved_5a                                             :  2,
+                      payload_end_offset                                      : 14;
+             uint32_t buf0_ptr_31_0                                           : 32;
+             uint32_t buf0_len                                                : 16,
+                      tqm_no_drop                                             :  1,
+                      encrypt_type                                            :  4,
+                      encap_type                                              :  2,
+                      extn_override                                           :  1,
+                      buf0_ptr_39_32                                          :  8;
+             uint32_t buf1_ptr_31_0                                           : 32;
+             uint32_t buf1_len                                                : 16,
+                      reserved_9a                                             :  5,
+                      mesh_enable                                             :  2,
+                      epd                                                     :  1,
+                      buf1_ptr_39_32                                          :  8;
+             uint32_t buf2_ptr_31_0                                           : 32;
+             uint32_t buf2_len                                                : 16,
+                      reserved_11a                                            :  2,
+                      dscp_tid_table_num                                      :  6,
+                      buf2_ptr_39_32                                          :  8;
+             uint32_t buf3_ptr_31_0                                           : 32;
+             uint32_t buf3_len                                                : 16,
+                      reserved_13a                                            :  8,
+                      buf3_ptr_39_32                                          :  8;
+             uint32_t buf4_ptr_31_0                                           : 32;
+             uint32_t buf4_len                                                : 16,
+                      reserved_15a                                            :  8,
+                      buf4_ptr_39_32                                          :  8;
+             uint32_t buf5_ptr_31_0                                           : 32;
+             uint32_t buf5_len                                                : 16,
+                      reserved_17a                                            :  8,
+                      buf5_ptr_39_32                                          :  8;
+#endif
+};
+
+#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET                                         0x00000000
+#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB                                            0
+#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB                                            0
+#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK                                           0x00000001
+
+#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET                                        0x00000000
+#define TX_MSDU_EXTENSION_RESERVED_0A_LSB                                           1
+#define TX_MSDU_EXTENSION_RESERVED_0A_MSB                                           6
+#define TX_MSDU_EXTENSION_RESERVED_0A_MASK                                          0x0000007e
+
+#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET                                           0x00000000
+#define TX_MSDU_EXTENSION_TCP_FLAG_LSB                                              7
+#define TX_MSDU_EXTENSION_TCP_FLAG_MSB                                              15
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK                                             0x0000ff80
+
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET                                      0x00000000
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB                                         16
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB                                         24
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK                                        0x01ff0000
+
+#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET                                        0x00000000
+#define TX_MSDU_EXTENSION_RESERVED_0B_LSB                                           25
+#define TX_MSDU_EXTENSION_RESERVED_0B_MSB                                           31
+#define TX_MSDU_EXTENSION_RESERVED_0B_MASK                                          0xfe000000
+
+#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET                                          0x00000004
+#define TX_MSDU_EXTENSION_L2_LENGTH_LSB                                             0
+#define TX_MSDU_EXTENSION_L2_LENGTH_MSB                                             15
+#define TX_MSDU_EXTENSION_L2_LENGTH_MASK                                            0x0000ffff
+
+#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET                                          0x00000004
+#define TX_MSDU_EXTENSION_IP_LENGTH_LSB                                             16
+#define TX_MSDU_EXTENSION_IP_LENGTH_MSB                                             31
+#define TX_MSDU_EXTENSION_IP_LENGTH_MASK                                            0xffff0000
+
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET                                     0x00000008
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB                                        0
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB                                        31
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK                                       0xffffffff
+
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET                                  0x0000000c
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB                                     0
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB                                     15
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK                                    0x0000ffff
+
+#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET                                         0x0000000c
+#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB                                            16
+#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB                                            31
+#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK                                           0xffff0000
+
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET                                    0x00000010
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB                                       0
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB                                       13
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK                                      0x00003fff
+
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET                                0x00000010
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB                                   14
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB                                   14
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK                                  0x00004000
+
+#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET                                        0x00000010
+#define TX_MSDU_EXTENSION_RESERVED_4A_LSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_4A_MSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_4A_MASK                                          0x00008000
+
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET                               0x00000010
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB                                  16
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB                                  29
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK                                 0x3fff0000
+
+#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET                                        0x00000010
+#define TX_MSDU_EXTENSION_RESERVED_4B_LSB                                           30
+#define TX_MSDU_EXTENSION_RESERVED_4B_MSB                                           31
+#define TX_MSDU_EXTENSION_RESERVED_4B_MASK                                          0xc0000000
+
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET                                 0x00000014
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB                                    0
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB                                    13
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK                                   0x00003fff
+
+#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET                                        0x00000014
+#define TX_MSDU_EXTENSION_RESERVED_5A_LSB                                           14
+#define TX_MSDU_EXTENSION_RESERVED_5A_MSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_5A_MASK                                          0x0000c000
+
+#define TX_MSDU_EXTENSION_WDS_OFFSET                                                0x00000014
+#define TX_MSDU_EXTENSION_WDS_LSB                                                   16
+#define TX_MSDU_EXTENSION_WDS_MSB                                                   16
+#define TX_MSDU_EXTENSION_WDS_MASK                                                  0x00010000
+
+#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET                                        0x00000014
+#define TX_MSDU_EXTENSION_RESERVED_5B_LSB                                           17
+#define TX_MSDU_EXTENSION_RESERVED_5B_MSB                                           31
+#define TX_MSDU_EXTENSION_RESERVED_5B_MASK                                          0xfffe0000
+
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET                                      0x00000018
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET                                     0x0000001c
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_OFFSET                                      0x0000001c
+#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_LSB                                         8
+#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MSB                                         8
+#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MASK                                        0x00000100
+
+#define TX_MSDU_EXTENSION_ENCAP_TYPE_OFFSET                                         0x0000001c
+#define TX_MSDU_EXTENSION_ENCAP_TYPE_LSB                                            9
+#define TX_MSDU_EXTENSION_ENCAP_TYPE_MSB                                            10
+#define TX_MSDU_EXTENSION_ENCAP_TYPE_MASK                                           0x00000600
+
+#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_OFFSET                                       0x0000001c
+#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_LSB                                          11
+#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MSB                                          14
+#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MASK                                         0x00007800
+
+#define TX_MSDU_EXTENSION_TQM_NO_DROP_OFFSET                                        0x0000001c
+#define TX_MSDU_EXTENSION_TQM_NO_DROP_LSB                                           15
+#define TX_MSDU_EXTENSION_TQM_NO_DROP_MSB                                           15
+#define TX_MSDU_EXTENSION_TQM_NO_DROP_MASK                                          0x00008000
+
+#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET                                           0x0000001c
+#define TX_MSDU_EXTENSION_BUF0_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF0_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF0_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET                                      0x00000020
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET                                     0x00000024
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_EPD_OFFSET                                                0x00000024
+#define TX_MSDU_EXTENSION_EPD_LSB                                                   8
+#define TX_MSDU_EXTENSION_EPD_MSB                                                   8
+#define TX_MSDU_EXTENSION_EPD_MASK                                                  0x00000100
+
+#define TX_MSDU_EXTENSION_MESH_ENABLE_OFFSET                                        0x00000024
+#define TX_MSDU_EXTENSION_MESH_ENABLE_LSB                                           9
+#define TX_MSDU_EXTENSION_MESH_ENABLE_MSB                                           10
+#define TX_MSDU_EXTENSION_MESH_ENABLE_MASK                                          0x00000600
+
+#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET                                        0x00000024
+#define TX_MSDU_EXTENSION_RESERVED_9A_LSB                                           11
+#define TX_MSDU_EXTENSION_RESERVED_9A_MSB                                           15
+#define TX_MSDU_EXTENSION_RESERVED_9A_MASK                                          0x0000f800
+
+#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET                                           0x00000024
+#define TX_MSDU_EXTENSION_BUF1_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF1_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF1_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET                                      0x00000028
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET                                     0x0000002c
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_OFFSET                                 0x0000002c
+#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_LSB                                    8
+#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MSB                                    13
+#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MASK                                   0x00003f00
+
+#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET                                       0x0000002c
+#define TX_MSDU_EXTENSION_RESERVED_11A_LSB                                          14
+#define TX_MSDU_EXTENSION_RESERVED_11A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_11A_MASK                                         0x0000c000
+
+#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET                                           0x0000002c
+#define TX_MSDU_EXTENSION_BUF2_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF2_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF2_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET                                      0x00000030
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET                                     0x00000034
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET                                       0x00000034
+#define TX_MSDU_EXTENSION_RESERVED_13A_LSB                                          8
+#define TX_MSDU_EXTENSION_RESERVED_13A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_13A_MASK                                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET                                           0x00000034
+#define TX_MSDU_EXTENSION_BUF3_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF3_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF3_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET                                      0x00000038
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET                                     0x0000003c
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET                                       0x0000003c
+#define TX_MSDU_EXTENSION_RESERVED_15A_LSB                                          8
+#define TX_MSDU_EXTENSION_RESERVED_15A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_15A_MASK                                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET                                           0x0000003c
+#define TX_MSDU_EXTENSION_BUF4_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF4_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF4_LEN_MASK                                             0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET                                      0x00000040
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB                                         0
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB                                         31
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK                                        0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET                                     0x00000044
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB                                        0
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB                                        7
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK                                       0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET                                       0x00000044
+#define TX_MSDU_EXTENSION_RESERVED_17A_LSB                                          8
+#define TX_MSDU_EXTENSION_RESERVED_17A_MSB                                          15
+#define TX_MSDU_EXTENSION_RESERVED_17A_MASK                                         0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET                                           0x00000044
+#define TX_MSDU_EXTENSION_BUF5_LEN_LSB                                              16
+#define TX_MSDU_EXTENSION_BUF5_LEN_MSB                                              31
+#define TX_MSDU_EXTENSION_BUF5_LEN_MASK                                             0xffff0000
+
+#endif
diff --git a/hw/peach/v1/tx_msdu_start.h b/hw/peach/v1/tx_msdu_start.h
new file mode 100644
index 000000000000..3b9e5b1c2c2f
--- /dev/null
+++ b/hw/peach/v1/tx_msdu_start.h
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_MSDU_START_H_
+#define _TX_MSDU_START_H_
+
+#define NUM_OF_DWORDS_TX_MSDU_START 7
+
+struct tx_msdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t msdu_len                                                : 14,
+                      first_msdu                                              :  1,
+                      last_msdu                                               :  1,
+                      encap_type                                              :  2,
+                      epd_en                                                  :  1,
+                      da_sa_present                                           :  2,
+                      ipv4_checksum_en                                        :  1,
+                      udp_over_ipv4_checksum_en                               :  1,
+                      udp_over_ipv6_checksum_en                               :  1,
+                      tcp_over_ipv4_checksum_en                               :  1,
+                      tcp_over_ipv6_checksum_en                               :  1,
+                      dummy_msdu_delimitation                                 :  1,
+                      reserved_0a                                             :  5;
+             uint32_t tso_enable                                              :  1,
+                      reserved_1a                                             :  6,
+                      tcp_flag                                                :  9,
+                      tcp_flag_mask                                           :  9,
+                      mesh_enable                                             :  1,
+                      reserved_1b                                             :  6;
+             uint32_t l2_length                                               : 16,
+                      ip_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t ip_identification                                       : 16,
+                      checksum_offset                                         : 13,
+                      partial_checksum_en                                     :  1,
+                      reserved_4                                              :  2;
+             uint32_t payload_start_offset                                    : 14,
+                      reserved_5a                                             :  2,
+                      payload_end_offset                                      : 14,
+                      reserved_5b                                             :  2;
+             uint32_t udp_length                                              : 16,
+                      reserved_6                                              : 16;
+#else
+             uint32_t reserved_0a                                             :  5,
+                      dummy_msdu_delimitation                                 :  1,
+                      tcp_over_ipv6_checksum_en                               :  1,
+                      tcp_over_ipv4_checksum_en                               :  1,
+                      udp_over_ipv6_checksum_en                               :  1,
+                      udp_over_ipv4_checksum_en                               :  1,
+                      ipv4_checksum_en                                        :  1,
+                      da_sa_present                                           :  2,
+                      epd_en                                                  :  1,
+                      encap_type                                              :  2,
+                      last_msdu                                               :  1,
+                      first_msdu                                              :  1,
+                      msdu_len                                                : 14;
+             uint32_t reserved_1b                                             :  6,
+                      mesh_enable                                             :  1,
+                      tcp_flag_mask                                           :  9,
+                      tcp_flag                                                :  9,
+                      reserved_1a                                             :  6,
+                      tso_enable                                              :  1;
+             uint32_t ip_length                                               : 16,
+                      l2_length                                               : 16;
+             uint32_t tcp_seq_number                                          : 32;
+             uint32_t reserved_4                                              :  2,
+                      partial_checksum_en                                     :  1,
+                      checksum_offset                                         : 13,
+                      ip_identification                                       : 16;
+             uint32_t reserved_5b                                             :  2,
+                      payload_end_offset                                      : 14,
+                      reserved_5a                                             :  2,
+                      payload_start_offset                                    : 14;
+             uint32_t reserved_6                                              : 16,
+                      udp_length                                              : 16;
+#endif
+};
+
+#define TX_MSDU_START_MSDU_LEN_OFFSET                                               0x00000000
+#define TX_MSDU_START_MSDU_LEN_LSB                                                  0
+#define TX_MSDU_START_MSDU_LEN_MSB                                                  13
+#define TX_MSDU_START_MSDU_LEN_MASK                                                 0x00003fff
+
+#define TX_MSDU_START_FIRST_MSDU_OFFSET                                             0x00000000
+#define TX_MSDU_START_FIRST_MSDU_LSB                                                14
+#define TX_MSDU_START_FIRST_MSDU_MSB                                                14
+#define TX_MSDU_START_FIRST_MSDU_MASK                                               0x00004000
+
+#define TX_MSDU_START_LAST_MSDU_OFFSET                                              0x00000000
+#define TX_MSDU_START_LAST_MSDU_LSB                                                 15
+#define TX_MSDU_START_LAST_MSDU_MSB                                                 15
+#define TX_MSDU_START_LAST_MSDU_MASK                                                0x00008000
+
+#define TX_MSDU_START_ENCAP_TYPE_OFFSET                                             0x00000000
+#define TX_MSDU_START_ENCAP_TYPE_LSB                                                16
+#define TX_MSDU_START_ENCAP_TYPE_MSB                                                17
+#define TX_MSDU_START_ENCAP_TYPE_MASK                                               0x00030000
+
+#define TX_MSDU_START_EPD_EN_OFFSET                                                 0x00000000
+#define TX_MSDU_START_EPD_EN_LSB                                                    18
+#define TX_MSDU_START_EPD_EN_MSB                                                    18
+#define TX_MSDU_START_EPD_EN_MASK                                                   0x00040000
+
+#define TX_MSDU_START_DA_SA_PRESENT_OFFSET                                          0x00000000
+#define TX_MSDU_START_DA_SA_PRESENT_LSB                                             19
+#define TX_MSDU_START_DA_SA_PRESENT_MSB                                             20
+#define TX_MSDU_START_DA_SA_PRESENT_MASK                                            0x00180000
+
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET                                       0x00000000
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB                                          21
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB                                          21
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK                                         0x00200000
+
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET                              0x00000000
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB                                 22
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB                                 22
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK                                0x00400000
+
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET                              0x00000000
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB                                 23
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB                                 23
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK                                0x00800000
+
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET                              0x00000000
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB                                 24
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB                                 24
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK                                0x01000000
+
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET                              0x00000000
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB                                 25
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB                                 25
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK                                0x02000000
+
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET                                0x00000000
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB                                   26
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB                                   26
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK                                  0x04000000
+
+#define TX_MSDU_START_RESERVED_0A_OFFSET                                            0x00000000
+#define TX_MSDU_START_RESERVED_0A_LSB                                               27
+#define TX_MSDU_START_RESERVED_0A_MSB                                               31
+#define TX_MSDU_START_RESERVED_0A_MASK                                              0xf8000000
+
+#define TX_MSDU_START_TSO_ENABLE_OFFSET                                             0x00000004
+#define TX_MSDU_START_TSO_ENABLE_LSB                                                0
+#define TX_MSDU_START_TSO_ENABLE_MSB                                                0
+#define TX_MSDU_START_TSO_ENABLE_MASK                                               0x00000001
+
+#define TX_MSDU_START_RESERVED_1A_OFFSET                                            0x00000004
+#define TX_MSDU_START_RESERVED_1A_LSB                                               1
+#define TX_MSDU_START_RESERVED_1A_MSB                                               6
+#define TX_MSDU_START_RESERVED_1A_MASK                                              0x0000007e
+
+#define TX_MSDU_START_TCP_FLAG_OFFSET                                               0x00000004
+#define TX_MSDU_START_TCP_FLAG_LSB                                                  7
+#define TX_MSDU_START_TCP_FLAG_MSB                                                  15
+#define TX_MSDU_START_TCP_FLAG_MASK                                                 0x0000ff80
+
+#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET                                          0x00000004
+#define TX_MSDU_START_TCP_FLAG_MASK_LSB                                             16
+#define TX_MSDU_START_TCP_FLAG_MASK_MSB                                             24
+#define TX_MSDU_START_TCP_FLAG_MASK_MASK                                            0x01ff0000
+
+#define TX_MSDU_START_MESH_ENABLE_OFFSET                                            0x00000004
+#define TX_MSDU_START_MESH_ENABLE_LSB                                               25
+#define TX_MSDU_START_MESH_ENABLE_MSB                                               25
+#define TX_MSDU_START_MESH_ENABLE_MASK                                              0x02000000
+
+#define TX_MSDU_START_RESERVED_1B_OFFSET                                            0x00000004
+#define TX_MSDU_START_RESERVED_1B_LSB                                               26
+#define TX_MSDU_START_RESERVED_1B_MSB                                               31
+#define TX_MSDU_START_RESERVED_1B_MASK                                              0xfc000000
+
+#define TX_MSDU_START_L2_LENGTH_OFFSET                                              0x00000008
+#define TX_MSDU_START_L2_LENGTH_LSB                                                 0
+#define TX_MSDU_START_L2_LENGTH_MSB                                                 15
+#define TX_MSDU_START_L2_LENGTH_MASK                                                0x0000ffff
+
+#define TX_MSDU_START_IP_LENGTH_OFFSET                                              0x00000008
+#define TX_MSDU_START_IP_LENGTH_LSB                                                 16
+#define TX_MSDU_START_IP_LENGTH_MSB                                                 31
+#define TX_MSDU_START_IP_LENGTH_MASK                                                0xffff0000
+
+#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET                                         0x0000000c
+#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB                                            0
+#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB                                            31
+#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK                                           0xffffffff
+
+#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET                                      0x00000010
+#define TX_MSDU_START_IP_IDENTIFICATION_LSB                                         0
+#define TX_MSDU_START_IP_IDENTIFICATION_MSB                                         15
+#define TX_MSDU_START_IP_IDENTIFICATION_MASK                                        0x0000ffff
+
+#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET                                        0x00000010
+#define TX_MSDU_START_CHECKSUM_OFFSET_LSB                                           16
+#define TX_MSDU_START_CHECKSUM_OFFSET_MSB                                           28
+#define TX_MSDU_START_CHECKSUM_OFFSET_MASK                                          0x1fff0000
+
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET                                    0x00000010
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB                                       29
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB                                       29
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK                                      0x20000000
+
+#define TX_MSDU_START_RESERVED_4_OFFSET                                             0x00000010
+#define TX_MSDU_START_RESERVED_4_LSB                                                30
+#define TX_MSDU_START_RESERVED_4_MSB                                                31
+#define TX_MSDU_START_RESERVED_4_MASK                                               0xc0000000
+
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET                                   0x00000014
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB                                      0
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB                                      13
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK                                     0x00003fff
+
+#define TX_MSDU_START_RESERVED_5A_OFFSET                                            0x00000014
+#define TX_MSDU_START_RESERVED_5A_LSB                                               14
+#define TX_MSDU_START_RESERVED_5A_MSB                                               15
+#define TX_MSDU_START_RESERVED_5A_MASK                                              0x0000c000
+
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET                                     0x00000014
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB                                        16
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB                                        29
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK                                       0x3fff0000
+
+#define TX_MSDU_START_RESERVED_5B_OFFSET                                            0x00000014
+#define TX_MSDU_START_RESERVED_5B_LSB                                               30
+#define TX_MSDU_START_RESERVED_5B_MSB                                               31
+#define TX_MSDU_START_RESERVED_5B_MASK                                              0xc0000000
+
+#define TX_MSDU_START_UDP_LENGTH_OFFSET                                             0x00000018
+#define TX_MSDU_START_UDP_LENGTH_LSB                                                0
+#define TX_MSDU_START_UDP_LENGTH_MSB                                                15
+#define TX_MSDU_START_UDP_LENGTH_MASK                                               0x0000ffff
+
+#define TX_MSDU_START_RESERVED_6_OFFSET                                             0x00000018
+#define TX_MSDU_START_RESERVED_6_LSB                                                16
+#define TX_MSDU_START_RESERVED_6_MSB                                                31
+#define TX_MSDU_START_RESERVED_6_MASK                                               0xffff0000
+
+#endif
diff --git a/hw/peach/v1/tx_peer_entry.h b/hw/peach/v1/tx_peer_entry.h
new file mode 100644
index 000000000000..4011563b7f7b
--- /dev/null
+++ b/hw/peach/v1/tx_peer_entry.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_PEER_ENTRY_H_
+#define _TX_PEER_ENTRY_H_
+
+#define NUM_OF_DWORDS_TX_PEER_ENTRY 18
+
+struct tx_peer_entry {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t mac_addr_a_31_0                                         : 32;
+             uint32_t mac_addr_a_47_32                                        : 16,
+                      mac_addr_b_15_0                                         : 16;
+             uint32_t mac_addr_b_47_16                                        : 32;
+             uint32_t use_ad_b                                                :  1,
+                      strip_insert_vlan_inner                                 :  1,
+                      strip_insert_vlan_outer                                 :  1,
+                      vlan_llc_mode                                           :  1,
+                      key_type                                                :  4,
+                      a_msdu_wds_ad3_ad4                                      :  3,
+                      ignore_hard_filters                                     :  1,
+                      ignore_soft_filters                                     :  1,
+                      epd_output                                              :  1,
+                      wds                                                     :  1,
+                      insert_or_strip                                         :  1,
+                      sw_filter_id                                            : 16;
+             uint32_t temporal_key_31_0                                       : 32;
+             uint32_t temporal_key_63_32                                      : 32;
+             uint32_t temporal_key_95_64                                      : 32;
+             uint32_t temporal_key_127_96                                     : 32;
+             uint32_t temporal_key_159_128                                    : 32;
+             uint32_t temporal_key_191_160                                    : 32;
+             uint32_t temporal_key_223_192                                    : 32;
+             uint32_t temporal_key_255_224                                    : 32;
+             uint32_t sta_partial_aid                                         : 11,
+                      transmit_vif                                            :  4,
+                      block_this_user                                         :  1,
+                      mesh_amsdu_mode                                         :  2,
+                      use_qos_alt_mute_mask                                   :  1,
+                      dl_ul_direction                                         :  1,
+                      reserved_12                                             : 12;
+             uint32_t insert_vlan_outer_tci                                   : 16,
+                      insert_vlan_inner_tci                                   : 16;
+             uint32_t __reserved_g_0007                                       : 32;
+             uint32_t __reserved_g_0008                                       : 16,
+                      __reserved_g_0009                                       : 16;
+             uint32_t __reserved_g_0010                                       : 32;
+             uint32_t multi_link_addr_crypto_enable                           :  1,
+                      reserved_17a                                            : 15,
+                      sw_peer_id                                              : 16;
+#else
+             uint32_t mac_addr_a_31_0                                         : 32;
+             uint32_t mac_addr_b_15_0                                         : 16,
+                      mac_addr_a_47_32                                        : 16;
+             uint32_t mac_addr_b_47_16                                        : 32;
+             uint32_t sw_filter_id                                            : 16,
+                      insert_or_strip                                         :  1,
+                      wds                                                     :  1,
+                      epd_output                                              :  1,
+                      ignore_soft_filters                                     :  1,
+                      ignore_hard_filters                                     :  1,
+                      a_msdu_wds_ad3_ad4                                      :  3,
+                      key_type                                                :  4,
+                      vlan_llc_mode                                           :  1,
+                      strip_insert_vlan_outer                                 :  1,
+                      strip_insert_vlan_inner                                 :  1,
+                      use_ad_b                                                :  1;
+             uint32_t temporal_key_31_0                                       : 32;
+             uint32_t temporal_key_63_32                                      : 32;
+             uint32_t temporal_key_95_64                                      : 32;
+             uint32_t temporal_key_127_96                                     : 32;
+             uint32_t temporal_key_159_128                                    : 32;
+             uint32_t temporal_key_191_160                                    : 32;
+             uint32_t temporal_key_223_192                                    : 32;
+             uint32_t temporal_key_255_224                                    : 32;
+             uint32_t reserved_12                                             : 12,
+                      dl_ul_direction                                         :  1,
+                      use_qos_alt_mute_mask                                   :  1,
+                      mesh_amsdu_mode                                         :  2,
+                      block_this_user                                         :  1,
+                      transmit_vif                                            :  4,
+                      sta_partial_aid                                         : 11;
+             uint32_t insert_vlan_inner_tci                                   : 16,
+                      insert_vlan_outer_tci                                   : 16;
+             uint32_t __reserved_g_0007                                       : 32;
+             uint32_t __reserved_g_0009                                       : 16,
+                      __reserved_g_0008                                       : 16;
+             uint32_t __reserved_g_0010                                       : 32;
+             uint32_t sw_peer_id                                              : 16,
+                      reserved_17a                                            : 15,
+                      multi_link_addr_crypto_enable                           :  1;
+#endif
+};
+
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET                                        0x00000000
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB                                           0
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB                                           31
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK                                          0xffffffff
+
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET                                       0x00000004
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB                                          0
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB                                          15
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK                                         0x0000ffff
+
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET                                        0x00000004
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB                                           16
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB                                           31
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK                                          0xffff0000
+
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET                                       0x00000008
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB                                          0
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB                                          31
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK                                         0xffffffff
+
+#define TX_PEER_ENTRY_USE_AD_B_OFFSET                                               0x0000000c
+#define TX_PEER_ENTRY_USE_AD_B_LSB                                                  0
+#define TX_PEER_ENTRY_USE_AD_B_MSB                                                  0
+#define TX_PEER_ENTRY_USE_AD_B_MASK                                                 0x00000001
+
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET                                0x0000000c
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB                                   1
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB                                   1
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK                                  0x00000002
+
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET                                0x0000000c
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB                                   2
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB                                   2
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK                                  0x00000004
+
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET                                          0x0000000c
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB                                             3
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB                                             3
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK                                            0x00000008
+
+#define TX_PEER_ENTRY_KEY_TYPE_OFFSET                                               0x0000000c
+#define TX_PEER_ENTRY_KEY_TYPE_LSB                                                  4
+#define TX_PEER_ENTRY_KEY_TYPE_MSB                                                  7
+#define TX_PEER_ENTRY_KEY_TYPE_MASK                                                 0x000000f0
+
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET                                     0x0000000c
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB                                        8
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB                                        10
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK                                       0x00000700
+
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET                                    0x0000000c
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB                                       11
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB                                       11
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK                                      0x00000800
+
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET                                    0x0000000c
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB                                       12
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB                                       12
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK                                      0x00001000
+
+#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET                                             0x0000000c
+#define TX_PEER_ENTRY_EPD_OUTPUT_LSB                                                13
+#define TX_PEER_ENTRY_EPD_OUTPUT_MSB                                                13
+#define TX_PEER_ENTRY_EPD_OUTPUT_MASK                                               0x00002000
+
+#define TX_PEER_ENTRY_WDS_OFFSET                                                    0x0000000c
+#define TX_PEER_ENTRY_WDS_LSB                                                       14
+#define TX_PEER_ENTRY_WDS_MSB                                                       14
+#define TX_PEER_ENTRY_WDS_MASK                                                      0x00004000
+
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET                                        0x0000000c
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB                                           15
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB                                           15
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK                                          0x00008000
+
+#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET                                           0x0000000c
+#define TX_PEER_ENTRY_SW_FILTER_ID_LSB                                              16
+#define TX_PEER_ENTRY_SW_FILTER_ID_MSB                                              31
+#define TX_PEER_ENTRY_SW_FILTER_ID_MASK                                             0xffff0000
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET                                      0x00000010
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB                                         0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB                                         31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK                                        0xffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET                                     0x00000014
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB                                        0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB                                        31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK                                       0xffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET                                     0x00000018
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB                                        0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB                                        31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK                                       0xffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET                                    0x0000001c
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB                                       0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB                                       31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK                                      0xffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET                                   0x00000020
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB                                      0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB                                      31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK                                     0xffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET                                   0x00000024
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB                                      0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB                                      31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK                                     0xffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET                                   0x00000028
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB                                      0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB                                      31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK                                     0xffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET                                   0x0000002c
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB                                      0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB                                      31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK                                     0xffffffff
+
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET                                        0x00000030
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB                                           0
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB                                           10
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK                                          0x000007ff
+
+#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET                                           0x00000030
+#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB                                              11
+#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB                                              14
+#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK                                             0x00007800
+
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET                                        0x00000030
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB                                           15
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB                                           15
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK                                          0x00008000
+
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET                                        0x00000030
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB                                           16
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB                                           17
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK                                          0x00030000
+
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET                                  0x00000030
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB                                     18
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB                                     18
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK                                    0x00040000
+
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET                                        0x00000030
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB                                           19
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB                                           19
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK                                          0x00080000
+
+#define TX_PEER_ENTRY_RESERVED_12_OFFSET                                            0x00000030
+#define TX_PEER_ENTRY_RESERVED_12_LSB                                               20
+#define TX_PEER_ENTRY_RESERVED_12_MSB                                               31
+#define TX_PEER_ENTRY_RESERVED_12_MASK                                              0xfff00000
+
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET                                  0x00000034
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB                                     0
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB                                     15
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK                                    0x0000ffff
+
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET                                  0x00000034
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB                                     16
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB                                     31
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK                                    0xffff0000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET                          0x00000044
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB                             0
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB                             0
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK                            0x00000001
+
+#define TX_PEER_ENTRY_RESERVED_17A_OFFSET                                           0x00000044
+#define TX_PEER_ENTRY_RESERVED_17A_LSB                                              1
+#define TX_PEER_ENTRY_RESERVED_17A_MSB                                              15
+#define TX_PEER_ENTRY_RESERVED_17A_MASK                                             0x0000fffe
+
+#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET                                             0x00000044
+#define TX_PEER_ENTRY_SW_PEER_ID_LSB                                                16
+#define TX_PEER_ENTRY_SW_PEER_ID_MSB                                                31
+#define TX_PEER_ENTRY_SW_PEER_ID_MASK                                               0xffff0000
+
+#endif
diff --git a/hw/peach/v1/tx_queue_extension.h b/hw/peach/v1/tx_queue_extension.h
new file mode 100644
index 000000000000..7b0d123d544b
--- /dev/null
+++ b/hw/peach/v1/tx_queue_extension.h
@@ -0,0 +1,316 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_QUEUE_EXTENSION_H_
+#define _TX_QUEUE_EXTENSION_H_
+
+#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14
+
+struct tx_queue_extension {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t frame_ctl                                               : 16,
+                      qos_ctl                                                 : 16;
+             uint32_t ampdu_flag                                              :  1,
+                      tx_notify_no_htc_override                               :  1,
+                      reserved_1a                                             :  7,
+                      checksum_tso_disable_for_frag                           :  1,
+                      key_id                                                  :  8,
+                      qos_buf_state_overwrite                                 :  1,
+                      buf_state_sta_id                                        :  1,
+                      buf_state_source                                        :  1,
+                      ht_control_overwrite_enable                             :  1,
+                      ht_control_overwrite_source                             :  4,
+                      reserved_1b                                             :  6;
+             uint32_t ul_headroom_insertion_enable                            :  1,
+                      ul_headroom_offset                                      :  5,
+                      bqrp_insertion_enable                                   :  1,
+                      bqrp_offset                                             :  5,
+                      ul_headroom_rsvd_7_6                                    :  2,
+                      bqr_rsvd_9_8                                            :  2,
+                      base_pn_63_48                                           : 16;
+             uint32_t base_pn_95_64                                           : 32;
+             uint32_t base_pn_127_96                                          : 32;
+             uint32_t ht_control_field_bw20                                   : 32;
+             uint32_t ht_control_field_bw40                                   : 32;
+             uint32_t ht_control_field_bw80                                   : 32;
+             uint32_t ht_control_field_bw160                                  : 32;
+             uint32_t ht_control_overwrite_mask                               : 32;
+             uint32_t cas_control_info                                        :  8,
+                      cas_offset                                              :  5,
+                      cas_insertion_enable                                    :  1,
+                      reserved_10a                                            :  2,
+                      ht_control_overwrite_source_for_srp                     :  4,
+                      ht_control_overwrite_source_for_bsrp                    :  4,
+                      reserved_10b                                            :  6,
+                      mpdu_hdr_len_override_en                                :  1,
+                      bar_ssn_overwrite_enable                                :  1;
+             uint32_t bar_ssn_offset                                          : 12,
+                      mpdu_hdr_len_override_val                               :  9,
+                      reserved_11a                                            : 11;
+             uint32_t ht_control_field_bw320                                  : 32;
+             uint32_t fw2sw_info                                              : 32;
+#else
+             uint32_t qos_ctl                                                 : 16,
+                      frame_ctl                                               : 16;
+             uint32_t reserved_1b                                             :  6,
+                      ht_control_overwrite_source                             :  4,
+                      ht_control_overwrite_enable                             :  1,
+                      buf_state_source                                        :  1,
+                      buf_state_sta_id                                        :  1,
+                      qos_buf_state_overwrite                                 :  1,
+                      key_id                                                  :  8,
+                      checksum_tso_disable_for_frag                           :  1,
+                      reserved_1a                                             :  7,
+                      tx_notify_no_htc_override                               :  1,
+                      ampdu_flag                                              :  1;
+             uint32_t base_pn_63_48                                           : 16,
+                      bqr_rsvd_9_8                                            :  2,
+                      ul_headroom_rsvd_7_6                                    :  2,
+                      bqrp_offset                                             :  5,
+                      bqrp_insertion_enable                                   :  1,
+                      ul_headroom_offset                                      :  5,
+                      ul_headroom_insertion_enable                            :  1;
+             uint32_t base_pn_95_64                                           : 32;
+             uint32_t base_pn_127_96                                          : 32;
+             uint32_t ht_control_field_bw20                                   : 32;
+             uint32_t ht_control_field_bw40                                   : 32;
+             uint32_t ht_control_field_bw80                                   : 32;
+             uint32_t ht_control_field_bw160                                  : 32;
+             uint32_t ht_control_overwrite_mask                               : 32;
+             uint32_t bar_ssn_overwrite_enable                                :  1,
+                      mpdu_hdr_len_override_en                                :  1,
+                      reserved_10b                                            :  6,
+                      ht_control_overwrite_source_for_bsrp                    :  4,
+                      ht_control_overwrite_source_for_srp                     :  4,
+                      reserved_10a                                            :  2,
+                      cas_insertion_enable                                    :  1,
+                      cas_offset                                              :  5,
+                      cas_control_info                                        :  8;
+             uint32_t reserved_11a                                            : 11,
+                      mpdu_hdr_len_override_val                               :  9,
+                      bar_ssn_offset                                          : 12;
+             uint32_t ht_control_field_bw320                                  : 32;
+             uint32_t fw2sw_info                                              : 32;
+#endif
+};
+
+#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET                                         0x00000000
+#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB                                            0
+#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB                                            15
+#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK                                           0x0000ffff
+
+#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET                                           0x00000000
+#define TX_QUEUE_EXTENSION_QOS_CTL_LSB                                              16
+#define TX_QUEUE_EXTENSION_QOS_CTL_MSB                                              31
+#define TX_QUEUE_EXTENSION_QOS_CTL_MASK                                             0xffff0000
+
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET                                        0x00000004
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB                                           0
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB                                           0
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK                                          0x00000001
+
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET                         0x00000004
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB                            1
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB                            1
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK                           0x00000002
+
+#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET                                       0x00000004
+#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB                                          2
+#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB                                          8
+#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK                                         0x000001fc
+
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET                     0x00000004
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB                        9
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB                        9
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK                       0x00000200
+
+#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET                                            0x00000004
+#define TX_QUEUE_EXTENSION_KEY_ID_LSB                                               10
+#define TX_QUEUE_EXTENSION_KEY_ID_MSB                                               17
+#define TX_QUEUE_EXTENSION_KEY_ID_MASK                                              0x0003fc00
+
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET                           0x00000004
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB                              18
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB                              18
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK                             0x00040000
+
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET                                  0x00000004
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB                                     19
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB                                     19
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK                                    0x00080000
+
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET                                  0x00000004
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB                                     20
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB                                     20
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK                                    0x00100000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET                       0x00000004
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB                          21
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB                          21
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK                         0x00200000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET                       0x00000004
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB                          22
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB                          25
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK                         0x03c00000
+
+#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET                                       0x00000004
+#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB                                          26
+#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB                                          31
+#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK                                         0xfc000000
+
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET                      0x00000008
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB                         0
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB                         0
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK                        0x00000001
+
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET                                0x00000008
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB                                   1
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB                                   5
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK                                  0x0000003e
+
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET                             0x00000008
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB                                6
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB                                6
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK                               0x00000040
+
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET                                       0x00000008
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB                                          7
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB                                          11
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK                                         0x00000f80
+
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET                              0x00000008
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB                                 12
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB                                 13
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK                                0x00003000
+
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET                                      0x00000008
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB                                         14
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB                                         15
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK                                        0x0000c000
+
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET                                     0x00000008
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB                                        16
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB                                        31
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK                                       0xffff0000
+
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET                                     0x0000000c
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB                                        0
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB                                        31
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK                                       0xffffffff
+
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET                                    0x00000010
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB                                       0
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB                                       31
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK                                      0xffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET                             0x00000014
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB                                0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB                                31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK                               0xffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET                             0x00000018
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB                                0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB                                31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK                               0xffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET                             0x0000001c
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB                                0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB                                31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK                               0xffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET                            0x00000020
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB                               0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB                               31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK                              0xffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET                         0x00000024
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB                            0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB                            31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK                           0xffffffff
+
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET                                  0x00000028
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB                                     0
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB                                     7
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK                                    0x000000ff
+
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET                                        0x00000028
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB                                           8
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB                                           12
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK                                          0x00001f00
+
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET                              0x00000028
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB                                 13
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB                                 13
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK                                0x00002000
+
+#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET                                      0x00000028
+#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB                                         14
+#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB                                         15
+#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK                                        0x0000c000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET               0x00000028
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB                  16
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB                  19
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK                 0x000f0000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET              0x00000028
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB                 20
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB                 23
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK                0x00f00000
+
+#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET                                      0x00000028
+#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB                                         24
+#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB                                         29
+#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK                                        0x3f000000
+
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET                          0x00000028
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB                             30
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB                             30
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK                            0x40000000
+
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET                          0x00000028
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB                             31
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB                             31
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK                            0x80000000
+
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET                                    0x0000002c
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB                                       0
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB                                       11
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK                                      0x00000fff
+
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET                         0x0000002c
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB                            12
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB                            20
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK                           0x001ff000
+
+#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET                                      0x0000002c
+#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB                                         21
+#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB                                         31
+#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK                                        0xffe00000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET                            0x00000030
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB                               0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB                               31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK                              0xffffffff
+
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET                                        0x00000034
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB                                           0
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB                                           31
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK                                          0xffffffff
+
+#endif
diff --git a/hw/peach/v1/tx_rate_stats_info.h b/hw/peach/v1/tx_rate_stats_info.h
new file mode 100644
index 000000000000..4f311a2d6ea9
--- /dev/null
+++ b/hw/peach/v1/tx_rate_stats_info.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_RATE_STATS_INFO_H_
+#define _TX_RATE_STATS_INFO_H_
+
+#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2
+
+struct tx_rate_stats_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t tx_rate_stats_info_valid                                :  1,
+                      transmit_bw                                             :  3,
+                      transmit_pkt_type                                       :  4,
+                      transmit_stbc                                           :  1,
+                      transmit_ldpc                                           :  1,
+                      transmit_sgi                                            :  2,
+                      transmit_mcs                                            :  4,
+                      ofdma_transmission                                      :  1,
+                      tones_in_ru                                             : 12,
+                      transmit_nss                                            :  3;
+             uint32_t ppdu_transmission_tsf                                   : 32;
+#else
+             uint32_t transmit_nss                                            :  3,
+                      tones_in_ru                                             : 12,
+                      ofdma_transmission                                      :  1,
+                      transmit_mcs                                            :  4,
+                      transmit_sgi                                            :  2,
+                      transmit_ldpc                                           :  1,
+                      transmit_stbc                                           :  1,
+                      transmit_pkt_type                                       :  4,
+                      transmit_bw                                             :  3,
+                      tx_rate_stats_info_valid                                :  1;
+             uint32_t ppdu_transmission_tsf                                   : 32;
+#endif
+};
+
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET                          0x00000000
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB                             0
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB                             0
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK                            0x00000001
+
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET                                       0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB                                          1
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB                                          3
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK                                         0x0000000e
+
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET                                 0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB                                    4
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB                                    7
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK                                   0x000000f0
+
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET                                     0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB                                        8
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB                                        8
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK                                       0x00000100
+
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET                                     0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB                                        9
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB                                        9
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK                                       0x00000200
+
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET                                      0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB                                         10
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB                                         11
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK                                        0x00000c00
+
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET                                      0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB                                         12
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB                                         15
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK                                        0x0000f000
+
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET                                0x00000000
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB                                   16
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB                                   16
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK                                  0x00010000
+
+#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET                                       0x00000000
+#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB                                          17
+#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB                                          28
+#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK                                         0x1ffe0000
+
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET                                      0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB                                         29
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB                                         31
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK                                        0xe0000000
+
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET                             0x00000004
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB                                0
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB                                31
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK                               0xffffffff
+
+#endif
diff --git a/hw/peach/v1/tx_raw_or_native_frame_setup.h b/hw/peach/v1/tx_raw_or_native_frame_setup.h
new file mode 100644
index 000000000000..468ff4919f5a
--- /dev/null
+++ b/hw/peach/v1/tx_raw_or_native_frame_setup.h
@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_
+#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_
+
+#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2
+
+struct tx_raw_or_native_frame_setup {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t fc_to_ds_mask                                           :  1,
+                      fc_from_ds_mask                                         :  1,
+                      fc_more_frag_mask                                       :  1,
+                      fc_retry_mask                                           :  1,
+                      fc_pwr_mgt_mask                                         :  1,
+                      fc_more_data_mask                                       :  1,
+                      fc_prot_frame_mask                                      :  1,
+                      fc_order_mask                                           :  1,
+                      duration_field_mask                                     :  1,
+                      sequence_control_mask                                   :  1,
+                      qc_tid_mask                                             :  1,
+                      qc_eosp_mask                                            :  1,
+                      qc_ack_policy_mask                                      :  1,
+                      qc_amsdu_mask                                           :  1,
+                      reserved_0a                                             :  1,
+                      qc_15to8_mask                                           :  1,
+                      iv_mask                                                 :  1,
+                      fc_to_ds_setting                                        :  1,
+                      fc_from_ds_setting                                      :  1,
+                      fc_more_frag_setting                                    :  1,
+                      fc_retry_setting                                        :  2,
+                      fc_pwr_mgt_setting                                      :  1,
+                      fc_more_data_setting                                    :  2,
+                      fc_prot_frame_setting                                   :  2,
+                      fc_order_setting                                        :  1,
+                      qc_tid_setting                                          :  4;
+             uint32_t qc_eosp_setting                                         :  2,
+                      qc_ack_policy_setting                                   :  2,
+                      qc_amsdu_setting                                        :  1,
+                      qc_15to8_setting                                        :  8,
+                      mlo_addr_override                                       :  1,
+                      mlo_ignore_addr3_override                               :  1,
+                      sequence_control_source                                 :  1,
+                      fragment_number                                         :  4,
+                      sequence_number                                         : 12;
+#else
+             uint32_t qc_tid_setting                                          :  4,
+                      fc_order_setting                                        :  1,
+                      fc_prot_frame_setting                                   :  2,
+                      fc_more_data_setting                                    :  2,
+                      fc_pwr_mgt_setting                                      :  1,
+                      fc_retry_setting                                        :  2,
+                      fc_more_frag_setting                                    :  1,
+                      fc_from_ds_setting                                      :  1,
+                      fc_to_ds_setting                                        :  1,
+                      iv_mask                                                 :  1,
+                      qc_15to8_mask                                           :  1,
+                      reserved_0a                                             :  1,
+                      qc_amsdu_mask                                           :  1,
+                      qc_ack_policy_mask                                      :  1,
+                      qc_eosp_mask                                            :  1,
+                      qc_tid_mask                                             :  1,
+                      sequence_control_mask                                   :  1,
+                      duration_field_mask                                     :  1,
+                      fc_order_mask                                           :  1,
+                      fc_prot_frame_mask                                      :  1,
+                      fc_more_data_mask                                       :  1,
+                      fc_pwr_mgt_mask                                         :  1,
+                      fc_retry_mask                                           :  1,
+                      fc_more_frag_mask                                       :  1,
+                      fc_from_ds_mask                                         :  1,
+                      fc_to_ds_mask                                           :  1;
+             uint32_t sequence_number                                         : 12,
+                      fragment_number                                         :  4,
+                      sequence_control_source                                 :  1,
+                      mlo_ignore_addr3_override                               :  1,
+                      mlo_addr_override                                       :  1,
+                      qc_15to8_setting                                        :  8,
+                      qc_amsdu_setting                                        :  1,
+                      qc_ack_policy_setting                                   :  2,
+                      qc_eosp_setting                                         :  2;
+#endif
+};
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET                           0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB                              0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB                              0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK                             0x00000001
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET                         0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB                            1
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB                            1
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK                           0x00000002
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET                       0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB                          2
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB                          2
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK                         0x00000004
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET                           0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB                              3
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB                              3
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK                             0x00000008
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET                         0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB                            4
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB                            4
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK                           0x00000010
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET                       0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB                          5
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB                          5
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK                         0x00000020
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET                      0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB                         6
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB                         6
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK                        0x00000040
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET                           0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB                              7
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB                              7
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK                             0x00000080
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET                     0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB                        8
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB                        8
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK                       0x00000100
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET                   0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB                      9
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB                      9
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK                     0x00000200
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET                             0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB                                10
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB                                10
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK                               0x00000400
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET                            0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB                               11
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB                               11
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK                              0x00000800
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET                      0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB                         12
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB                         12
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK                        0x00001000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET                           0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB                              13
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB                              13
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK                             0x00002000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET                             0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB                                14
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB                                14
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK                               0x00004000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET                           0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB                              15
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB                              15
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK                             0x00008000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET                                 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB                                    16
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB                                    16
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK                                   0x00010000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET                        0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB                           17
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB                           17
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK                          0x00020000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET                      0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB                         18
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB                         18
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK                        0x00040000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET                    0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB                       19
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB                       19
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK                      0x00080000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET                        0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB                           20
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB                           21
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK                          0x00300000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET                      0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB                         22
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB                         22
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK                        0x00400000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET                    0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB                       23
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB                       24
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK                      0x01800000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET                   0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB                      25
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB                      26
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK                     0x06000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET                        0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB                           27
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB                           27
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK                          0x08000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET                          0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB                             28
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB                             31
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK                            0xf0000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET                         0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB                            0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB                            1
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK                           0x00000003
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET                   0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB                      2
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB                      3
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK                     0x0000000c
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET                        0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB                           4
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB                           4
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK                          0x00000010
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET                        0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB                           5
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB                           12
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK                          0x00001fe0
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET                       0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB                          13
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB                          13
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK                         0x00002000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET               0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB                  14
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB                  14
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK                 0x00004000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET                 0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB                    15
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB                    15
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK                   0x00008000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET                         0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB                            16
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB                            19
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK                           0x000f0000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET                         0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB                            20
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB                            31
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK                           0xfff00000
+
+#endif
diff --git a/hw/peach/v1/txpcu_buffer_basics.h b/hw/peach/v1/txpcu_buffer_basics.h
new file mode 100644
index 000000000000..236c1b83af92
--- /dev/null
+++ b/hw/peach/v1/txpcu_buffer_basics.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TXPCU_BUFFER_BASICS_H_
+#define _TXPCU_BUFFER_BASICS_H_
+
+#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1
+
+struct txpcu_buffer_basics {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t available_memory                                        :  8,
+                      partial_tx_data_tlv_count                               :  8,
+                      tx_data_tlv_count                                       : 16;
+#else
+             uint32_t tx_data_tlv_count                                       : 16,
+                      partial_tx_data_tlv_count                               :  8,
+                      available_memory                                        :  8;
+#endif
+};
+
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET                                 0x00000000
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB                                    0
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB                                    7
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK                                   0x000000ff
+
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET                        0x00000000
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB                           8
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB                           15
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK                          0x0000ff00
+
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET                                0x00000000
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB                                   16
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB                                   31
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK                                  0xffff0000
+
+#endif
diff --git a/hw/peach/v1/txpcu_buffer_status.h b/hw/peach/v1/txpcu_buffer_status.h
new file mode 100644
index 000000000000..f9d49adf23a2
--- /dev/null
+++ b/hw/peach/v1/txpcu_buffer_status.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TXPCU_BUFFER_STATUS_H_
+#define _TXPCU_BUFFER_STATUS_H_
+
+#include "txpcu_buffer_basics.h"
+#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2
+
+struct txpcu_buffer_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   txpcu_buffer_basics                                       txpcu_basix_buffer_info;
+             uint32_t reserved                                                : 15,
+                      msdu_end                                                :  1,
+                      tx_data_sync_value                                      : 16;
+#else
+             struct   txpcu_buffer_basics                                       txpcu_basix_buffer_info;
+             uint32_t tx_data_sync_value                                      : 16,
+                      msdu_end                                                :  1,
+                      reserved                                                : 15;
+#endif
+};
+
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET         0x00000000
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB            0
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB            7
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK           0x000000ff
+
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB   8
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB   15
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK  0x0000ff00
+
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET        0x00000000
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB           16
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB           31
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK          0xffff0000
+
+#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET                                         0x00000004
+#define TXPCU_BUFFER_STATUS_RESERVED_LSB                                            0
+#define TXPCU_BUFFER_STATUS_RESERVED_MSB                                            14
+#define TXPCU_BUFFER_STATUS_RESERVED_MASK                                           0x00007fff
+
+#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET                                         0x00000004
+#define TXPCU_BUFFER_STATUS_MSDU_END_LSB                                            15
+#define TXPCU_BUFFER_STATUS_MSDU_END_MSB                                            15
+#define TXPCU_BUFFER_STATUS_MSDU_END_MASK                                           0x00008000
+
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET                               0x00000004
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB                                  16
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB                                  31
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK                                 0xffff0000
+
+#endif
diff --git a/hw/peach/v1/txpcu_user_buffer_status.h b/hw/peach/v1/txpcu_user_buffer_status.h
new file mode 100644
index 000000000000..f6d6f049fcc5
--- /dev/null
+++ b/hw/peach/v1/txpcu_user_buffer_status.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TXPCU_USER_BUFFER_STATUS_H_
+#define _TXPCU_USER_BUFFER_STATUS_H_
+
+#include "txpcu_buffer_basics.h"
+#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2
+
+struct txpcu_user_buffer_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   txpcu_buffer_basics                                       txpcu_basic_buffer_info;
+             uint32_t stored_word_count_user                                  : 14,
+                      reserved_1a                                             :  1,
+                      msdu_end                                                :  1,
+                      tx_data_sync_value                                      : 16;
+#else
+             struct   txpcu_buffer_basics                                       txpcu_basic_buffer_info;
+             uint32_t tx_data_sync_value                                      : 16,
+                      msdu_end                                                :  1,
+                      reserved_1a                                             :  1,
+                      stored_word_count_user                                  : 14;
+#endif
+};
+
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET    0x00000000
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB       0
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB       7
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK      0x000000ff
+
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00
+
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET   0x00000000
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB      16
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB      31
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK     0xffff0000
+
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET                      0x00000004
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB                         0
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB                         13
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK                        0x00003fff
+
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET                                 0x00000004
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB                                    14
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB                                    14
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK                                   0x00004000
+
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET                                    0x00000004
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB                                       15
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB                                       15
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK                                      0x00008000
+
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET                          0x00000004
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB                             16
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB                             31
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK                            0xffff0000
+
+#endif
diff --git a/hw/peach/v1/u_sig_eht_su_mu_info.h b/hw/peach/v1/u_sig_eht_su_mu_info.h
new file mode 100644
index 000000000000..9e2f1616e31f
--- /dev/null
+++ b/hw/peach/v1/u_sig_eht_su_mu_info.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _U_SIG_EHT_SU_MU_INFO_H_
+#define _U_SIG_EHT_SU_MU_INFO_H_
+
+#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2
+
+struct u_sig_eht_su_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_version                                             :  3,
+                      transmit_bw                                             :  3,
+                      dl_ul_flag                                              :  1,
+                      bss_color_id                                            :  6,
+                      txop_duration                                           :  7,
+                      disregard_0a                                            :  5,
+                      validate_0b                                             :  1,
+                      reserved_0c                                             :  6;
+             uint32_t eht_ppdu_sig_cmn_type                                   :  2,
+                      validate_1a                                             :  1,
+                      punctured_channel_information                           :  5,
+                      validate_1b                                             :  1,
+                      mcs_of_eht_sig                                          :  2,
+                      num_eht_sig_symbols                                     :  5,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      dot11ax_su_extended                                     :  1,
+                      reserved_1d                                             :  3,
+                      rx_ndp                                                  :  1,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0c                                             :  6,
+                      validate_0b                                             :  1,
+                      disregard_0a                                            :  5,
+                      txop_duration                                           :  7,
+                      bss_color_id                                            :  6,
+                      dl_ul_flag                                              :  1,
+                      transmit_bw                                             :  3,
+                      phy_version                                             :  3;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      rx_ndp                                                  :  1,
+                      reserved_1d                                             :  3,
+                      dot11ax_su_extended                                     :  1,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      num_eht_sig_symbols                                     :  5,
+                      mcs_of_eht_sig                                          :  2,
+                      validate_1b                                             :  1,
+                      punctured_channel_information                           :  5,
+                      validate_1a                                             :  1,
+                      eht_ppdu_sig_cmn_type                                   :  2;
+#endif
+};
+
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB                                        0
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB                                        2
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK                                       0x00000007
+
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB                                        3
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB                                        5
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK                                       0x00000038
+
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET                                      0x00000000
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB                                         6
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB                                         6
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK                                        0x00000040
+
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET                                    0x00000000
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB                                       7
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB                                       12
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK                                      0x00001f80
+
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET                                   0x00000000
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB                                      13
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB                                      19
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK                                     0x000fe000
+
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET                                    0x00000000
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB                                       20
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB                                       24
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK                                      0x01f00000
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB                                        25
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB                                        25
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK                                       0x02000000
+
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET                                     0x00000000
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB                                        26
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB                                        31
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK                                       0xfc000000
+
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET                           0x00000004
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB                              0
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB                              1
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK                             0x00000003
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET                                     0x00000004
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB                                        2
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB                                        2
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK                                       0x00000004
+
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET                   0x00000004
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB                      3
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB                      7
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK                     0x000000f8
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET                                     0x00000004
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB                                        8
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB                                        8
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK                                       0x00000100
+
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET                                  0x00000004
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB                                     9
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB                                     10
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK                                    0x00000600
+
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET                             0x00000004
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB                                11
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB                                15
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK                               0x0000f800
+
+#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET                                             0x00000004
+#define U_SIG_EHT_SU_MU_INFO_CRC_LSB                                                16
+#define U_SIG_EHT_SU_MU_INFO_CRC_MSB                                                19
+#define U_SIG_EHT_SU_MU_INFO_CRC_MASK                                               0x000f0000
+
+#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET                                            0x00000004
+#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB                                               20
+#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB                                               25
+#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK                                              0x03f00000
+
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET                             0x00000004
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB                                26
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB                                26
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK                               0x04000000
+
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET                                     0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB                                        27
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB                                        29
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK                                       0x38000000
+
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET                                          0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB                                             30
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB                                             30
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK                                            0x40000000
+
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                       0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                          31
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                          31
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                         0x80000000
+
+#endif
diff --git a/hw/peach/v1/u_sig_eht_tb_info.h b/hw/peach/v1/u_sig_eht_tb_info.h
new file mode 100644
index 000000000000..1240c159f708
--- /dev/null
+++ b/hw/peach/v1/u_sig_eht_tb_info.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _U_SIG_EHT_TB_INFO_H_
+#define _U_SIG_EHT_TB_INFO_H_
+
+#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2
+
+struct u_sig_eht_tb_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t phy_version                                             :  3,
+                      transmit_bw                                             :  3,
+                      dl_ul_flag                                              :  1,
+                      bss_color_id                                            :  6,
+                      txop_duration                                           :  7,
+                      disregard_0a                                            :  6,
+                      reserved_0c                                             :  6;
+             uint32_t eht_ppdu_sig_cmn_type                                   :  2,
+                      validate_1a                                             :  1,
+                      spatial_reuse                                           :  8,
+                      disregard_1b                                            :  5,
+                      crc                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_1c                                             :  5,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0c                                             :  6,
+                      disregard_0a                                            :  6,
+                      txop_duration                                           :  7,
+                      bss_color_id                                            :  6,
+                      dl_ul_flag                                              :  1,
+                      transmit_bw                                             :  3,
+                      phy_version                                             :  3;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1c                                             :  5,
+                      tail                                                    :  6,
+                      crc                                                     :  4,
+                      disregard_1b                                            :  5,
+                      spatial_reuse                                           :  8,
+                      validate_1a                                             :  1,
+                      eht_ppdu_sig_cmn_type                                   :  2;
+#endif
+};
+
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET                                        0x00000000
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB                                           0
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB                                           2
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK                                          0x00000007
+
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET                                        0x00000000
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB                                           3
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB                                           5
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK                                          0x00000038
+
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET                                         0x00000000
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB                                            6
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB                                            6
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK                                           0x00000040
+
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET                                       0x00000000
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB                                          7
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB                                          12
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK                                         0x00001f80
+
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET                                      0x00000000
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB                                         13
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB                                         19
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK                                        0x000fe000
+
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET                                       0x00000000
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB                                          20
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB                                          25
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK                                         0x03f00000
+
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET                                        0x00000000
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB                                           26
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB                                           31
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK                                          0xfc000000
+
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET                              0x00000004
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB                                 0
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB                                 1
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK                                0x00000003
+
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET                                        0x00000004
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB                                           2
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB                                           2
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK                                          0x00000004
+
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET                                      0x00000004
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB                                         3
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB                                         10
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK                                        0x000007f8
+
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET                                       0x00000004
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB                                          11
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB                                          15
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK                                         0x0000f800
+
+#define U_SIG_EHT_TB_INFO_CRC_OFFSET                                                0x00000004
+#define U_SIG_EHT_TB_INFO_CRC_LSB                                                   16
+#define U_SIG_EHT_TB_INFO_CRC_MSB                                                   19
+#define U_SIG_EHT_TB_INFO_CRC_MASK                                                  0x000f0000
+
+#define U_SIG_EHT_TB_INFO_TAIL_OFFSET                                               0x00000004
+#define U_SIG_EHT_TB_INFO_TAIL_LSB                                                  20
+#define U_SIG_EHT_TB_INFO_TAIL_MSB                                                  25
+#define U_SIG_EHT_TB_INFO_TAIL_MASK                                                 0x03f00000
+
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET                                        0x00000004
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB                                           26
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB                                           30
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK                                          0x7c000000
+
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                          0x00000004
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                             31
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                             31
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                            0x80000000
+
+#endif
diff --git a/hw/peach/v1/unallocated_ru_160_info.h b/hw/peach/v1/unallocated_ru_160_info.h
new file mode 100644
index 000000000000..da3c52bfc217
--- /dev/null
+++ b/hw/peach/v1/unallocated_ru_160_info.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _UNALLOCATED_RU_160_INFO_H_
+#define _UNALLOCATED_RU_160_INFO_H_
+
+#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1
+
+struct unallocated_ru_160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t subband80_0_cc0                                         :  8,
+                      subband80_0_cc1                                         :  8,
+                      subband80_1_cc0                                         :  8,
+                      subband80_1_cc1                                         :  8;
+#else
+             uint32_t subband80_1_cc1                                         :  8,
+                      subband80_1_cc0                                         :  8,
+                      subband80_0_cc1                                         :  8,
+                      subband80_0_cc0                                         :  8;
+#endif
+};
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB                                 0
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB                                 7
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK                                0x000000ff
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB                                 8
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB                                 15
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK                                0x0000ff00
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB                                 16
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB                                 23
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK                                0x00ff0000
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET                              0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB                                 24
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB                                 31
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK                                0xff000000
+
+#endif
diff --git a/hw/peach/v1/uniform_descriptor_header.h b/hw/peach/v1/uniform_descriptor_header.h
new file mode 100644
index 000000000000..a00f6b9cd099
--- /dev/null
+++ b/hw/peach/v1/uniform_descriptor_header.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
+#define _UNIFORM_DESCRIPTOR_HEADER_H_
+
+#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1
+
+struct uniform_descriptor_header {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t owner                                                   :  4,
+                      buffer_type                                             :  4,
+                      tx_mpdu_queue_number                                    : 20,
+                      reserved_0a                                             :  4;
+#else
+             uint32_t reserved_0a                                             :  4,
+                      tx_mpdu_queue_number                                    : 20,
+                      buffer_type                                             :  4,
+                      owner                                                   :  4;
+#endif
+};
+
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET                                      0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB                                         0
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB                                         3
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK                                        0x0000000f
+
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET                                0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB                                   4
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB                                   7
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK                                  0x000000f0
+
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET                       0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB                          8
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                          27
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                         0x0fffff00
+
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                                0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB                                   28
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB                                   31
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK                                  0xf0000000
+
+#endif
diff --git a/hw/peach/v1/uniform_reo_cmd_header.h b/hw/peach/v1/uniform_reo_cmd_header.h
new file mode 100644
index 000000000000..e9139b54e9b2
--- /dev/null
+++ b/hw/peach/v1/uniform_reo_cmd_header.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _UNIFORM_REO_CMD_HEADER_H_
+#define _UNIFORM_REO_CMD_HEADER_H_
+
+#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1
+
+struct uniform_reo_cmd_header {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reo_cmd_number                                          : 16,
+                      reo_status_required                                     :  1,
+                      reserved_0a                                             : 15;
+#else
+             uint32_t reserved_0a                                             : 15,
+                      reo_status_required                                     :  1,
+                      reo_cmd_number                                          : 16;
+#endif
+};
+
+#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_OFFSET                                0x00000000
+#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_LSB                                   0
+#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MSB                                   15
+#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MASK                                  0x0000ffff
+
+#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET                           0x00000000
+#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_LSB                              16
+#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MSB                              16
+#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MASK                             0x00010000
+
+#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_OFFSET                                   0x00000000
+#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_LSB                                      17
+#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MSB                                      31
+#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MASK                                     0xfffe0000
+
+#endif
diff --git a/hw/peach/v1/uniform_reo_status_header.h b/hw/peach/v1/uniform_reo_status_header.h
new file mode 100644
index 000000000000..988ba6e05ec0
--- /dev/null
+++ b/hw/peach/v1/uniform_reo_status_header.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _UNIFORM_REO_STATUS_HEADER_H_
+#define _UNIFORM_REO_STATUS_HEADER_H_
+
+#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2
+
+struct uniform_reo_status_header {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t reo_status_number                                       : 16,
+                      cmd_execution_time                                      : 10,
+                      reo_cmd_execution_status                                :  2,
+                      reserved_0a                                             :  4;
+             uint32_t timestamp                                               : 32;
+#else
+             uint32_t reserved_0a                                             :  4,
+                      reo_cmd_execution_status                                :  2,
+                      cmd_execution_time                                      : 10,
+                      reo_status_number                                       : 16;
+             uint32_t timestamp                                               : 32;
+#endif
+};
+
+#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET                          0x00000000
+#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_LSB                             0
+#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MSB                             15
+#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MASK                            0x0000ffff
+
+#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET                         0x00000000
+#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_LSB                            16
+#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MSB                            25
+#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MASK                           0x03ff0000
+
+#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET                   0x00000000
+#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB                      26
+#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB                      27
+#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK                     0x0c000000
+
+#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_OFFSET                                0x00000000
+#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_LSB                                   28
+#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MSB                                   31
+#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MASK                                  0xf0000000
+
+#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_OFFSET                                  0x00000004
+#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_LSB                                     0
+#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MSB                                     31
+#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MASK                                    0xffffffff
+
+#endif
diff --git a/hw/peach/v1/vht_sig_a_info.h b/hw/peach/v1/vht_sig_a_info.h
new file mode 100644
index 000000000000..6b20f8f904f8
--- /dev/null
+++ b/hw/peach/v1/vht_sig_a_info.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_A_INFO_H_
+#define _VHT_SIG_A_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2
+
+struct vht_sig_a_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t bandwidth                                               :  2,
+                      vhta_reserved_0                                         :  1,
+                      stbc                                                    :  1,
+                      group_id                                                :  6,
+                      n_sts                                                   : 12,
+                      txop_ps_not_allowed                                     :  1,
+                      vhta_reserved_0b                                        :  1,
+                      reserved_0                                              :  8;
+             uint32_t gi_setting                                              :  2,
+                      su_mu_coding                                            :  1,
+                      ldpc_extra_symbol                                       :  1,
+                      mcs                                                     :  4,
+                      beamformed                                              :  1,
+                      vhta_reserved_1                                         :  1,
+                      crc                                                     :  8,
+                      tail                                                    :  6,
+                      reserved_1                                              :  7,
+                      rx_integrity_check_passed                               :  1;
+#else
+             uint32_t reserved_0                                              :  8,
+                      vhta_reserved_0b                                        :  1,
+                      txop_ps_not_allowed                                     :  1,
+                      n_sts                                                   : 12,
+                      group_id                                                :  6,
+                      stbc                                                    :  1,
+                      vhta_reserved_0                                         :  1,
+                      bandwidth                                               :  2;
+             uint32_t rx_integrity_check_passed                               :  1,
+                      reserved_1                                              :  7,
+                      tail                                                    :  6,
+                      crc                                                     :  8,
+                      vhta_reserved_1                                         :  1,
+                      beamformed                                              :  1,
+                      mcs                                                     :  4,
+                      ldpc_extra_symbol                                       :  1,
+                      su_mu_coding                                            :  1,
+                      gi_setting                                              :  2;
+#endif
+};
+
+#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET                                             0x00000000
+#define VHT_SIG_A_INFO_BANDWIDTH_LSB                                                0
+#define VHT_SIG_A_INFO_BANDWIDTH_MSB                                                1
+#define VHT_SIG_A_INFO_BANDWIDTH_MASK                                               0x00000003
+
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB                                          2
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB                                          2
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK                                         0x00000004
+
+#define VHT_SIG_A_INFO_STBC_OFFSET                                                  0x00000000
+#define VHT_SIG_A_INFO_STBC_LSB                                                     3
+#define VHT_SIG_A_INFO_STBC_MSB                                                     3
+#define VHT_SIG_A_INFO_STBC_MASK                                                    0x00000008
+
+#define VHT_SIG_A_INFO_GROUP_ID_OFFSET                                              0x00000000
+#define VHT_SIG_A_INFO_GROUP_ID_LSB                                                 4
+#define VHT_SIG_A_INFO_GROUP_ID_MSB                                                 9
+#define VHT_SIG_A_INFO_GROUP_ID_MASK                                                0x000003f0
+
+#define VHT_SIG_A_INFO_N_STS_OFFSET                                                 0x00000000
+#define VHT_SIG_A_INFO_N_STS_LSB                                                    10
+#define VHT_SIG_A_INFO_N_STS_MSB                                                    21
+#define VHT_SIG_A_INFO_N_STS_MASK                                                   0x003ffc00
+
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET                                   0x00000000
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB                                      22
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB                                      22
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK                                     0x00400000
+
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET                                      0x00000000
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB                                         23
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB                                         23
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK                                        0x00800000
+
+#define VHT_SIG_A_INFO_RESERVED_0_OFFSET                                            0x00000000
+#define VHT_SIG_A_INFO_RESERVED_0_LSB                                               24
+#define VHT_SIG_A_INFO_RESERVED_0_MSB                                               31
+#define VHT_SIG_A_INFO_RESERVED_0_MASK                                              0xff000000
+
+#define VHT_SIG_A_INFO_GI_SETTING_OFFSET                                            0x00000004
+#define VHT_SIG_A_INFO_GI_SETTING_LSB                                               0
+#define VHT_SIG_A_INFO_GI_SETTING_MSB                                               1
+#define VHT_SIG_A_INFO_GI_SETTING_MASK                                              0x00000003
+
+#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET                                          0x00000004
+#define VHT_SIG_A_INFO_SU_MU_CODING_LSB                                             2
+#define VHT_SIG_A_INFO_SU_MU_CODING_MSB                                             2
+#define VHT_SIG_A_INFO_SU_MU_CODING_MASK                                            0x00000004
+
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET                                     0x00000004
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB                                        3
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB                                        3
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK                                       0x00000008
+
+#define VHT_SIG_A_INFO_MCS_OFFSET                                                   0x00000004
+#define VHT_SIG_A_INFO_MCS_LSB                                                      4
+#define VHT_SIG_A_INFO_MCS_MSB                                                      7
+#define VHT_SIG_A_INFO_MCS_MASK                                                     0x000000f0
+
+#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET                                            0x00000004
+#define VHT_SIG_A_INFO_BEAMFORMED_LSB                                               8
+#define VHT_SIG_A_INFO_BEAMFORMED_MSB                                               8
+#define VHT_SIG_A_INFO_BEAMFORMED_MASK                                              0x00000100
+
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB                                          9
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB                                          9
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK                                         0x00000200
+
+#define VHT_SIG_A_INFO_CRC_OFFSET                                                   0x00000004
+#define VHT_SIG_A_INFO_CRC_LSB                                                      10
+#define VHT_SIG_A_INFO_CRC_MSB                                                      17
+#define VHT_SIG_A_INFO_CRC_MASK                                                     0x0003fc00
+
+#define VHT_SIG_A_INFO_TAIL_OFFSET                                                  0x00000004
+#define VHT_SIG_A_INFO_TAIL_LSB                                                     18
+#define VHT_SIG_A_INFO_TAIL_MSB                                                     23
+#define VHT_SIG_A_INFO_TAIL_MASK                                                    0x00fc0000
+
+#define VHT_SIG_A_INFO_RESERVED_1_OFFSET                                            0x00000004
+#define VHT_SIG_A_INFO_RESERVED_1_LSB                                               24
+#define VHT_SIG_A_INFO_RESERVED_1_MSB                                               30
+#define VHT_SIG_A_INFO_RESERVED_1_MASK                                              0x7f000000
+
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET                             0x00000004
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB                                31
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB                                31
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK                               0x80000000
+
+#endif
diff --git a/hw/peach/v1/vht_sig_b_mu160_info.h b/hw/peach/v1/vht_sig_b_mu160_info.h
new file mode 100644
index 000000000000..6709a5e3c87d
--- /dev/null
+++ b/hw/peach/v1/vht_sig_b_mu160_info.h
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_MU160_INFO_H_
+#define _VHT_SIG_B_MU160_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8
+
+struct vht_sig_b_mu160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 19,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_0                                              :  3;
+             uint32_t length_copy_a                                           : 19,
+                      mcs_copy_a                                              :  4,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  3;
+             uint32_t length_copy_b                                           : 19,
+                      mcs_copy_b                                              :  4,
+                      tail_copy_b                                             :  6,
+                      reserved_2                                              :  3;
+             uint32_t length_copy_c                                           : 19,
+                      mcs_copy_c                                              :  4,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  3;
+             uint32_t length_copy_d                                           : 19,
+                      mcs_copy_d                                              :  4,
+                      tail_copy_d                                             :  6,
+                      reserved_4                                              :  3;
+             uint32_t length_copy_e                                           : 19,
+                      mcs_copy_e                                              :  4,
+                      tail_copy_e                                             :  6,
+                      reserved_5                                              :  3;
+             uint32_t length_copy_f                                           : 19,
+                      mcs_copy_f                                              :  4,
+                      tail_copy_f                                             :  6,
+                      mu_user_number                                          :  3;
+             uint32_t length_copy_g                                           : 19,
+                      mcs_copy_g                                              :  4,
+                      tail_copy_g                                             :  6,
+                      reserved_7                                              :  3;
+#else
+             uint32_t reserved_0                                              :  3,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 19;
+             uint32_t reserved_1                                              :  3,
+                      tail_copy_a                                             :  6,
+                      mcs_copy_a                                              :  4,
+                      length_copy_a                                           : 19;
+             uint32_t reserved_2                                              :  3,
+                      tail_copy_b                                             :  6,
+                      mcs_copy_b                                              :  4,
+                      length_copy_b                                           : 19;
+             uint32_t reserved_3                                              :  3,
+                      tail_copy_c                                             :  6,
+                      mcs_copy_c                                              :  4,
+                      length_copy_c                                           : 19;
+             uint32_t reserved_4                                              :  3,
+                      tail_copy_d                                             :  6,
+                      mcs_copy_d                                              :  4,
+                      length_copy_d                                           : 19;
+             uint32_t reserved_5                                              :  3,
+                      tail_copy_e                                             :  6,
+                      mcs_copy_e                                              :  4,
+                      length_copy_e                                           : 19;
+             uint32_t mu_user_number                                          :  3,
+                      tail_copy_f                                             :  6,
+                      mcs_copy_f                                              :  4,
+                      length_copy_f                                           : 19;
+             uint32_t reserved_7                                              :  3,
+                      tail_copy_g                                             :  6,
+                      mcs_copy_g                                              :  4,
+                      length_copy_g                                           : 19;
+#endif
+};
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET                                          0x00000000
+#define VHT_SIG_B_MU160_INFO_LENGTH_LSB                                             0
+#define VHT_SIG_B_MU160_INFO_LENGTH_MSB                                             18
+#define VHT_SIG_B_MU160_INFO_LENGTH_MASK                                            0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU160_INFO_MCS_LSB                                                19
+#define VHT_SIG_B_MU160_INFO_MCS_MSB                                                22
+#define VHT_SIG_B_MU160_INFO_MCS_MASK                                               0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET                                            0x00000000
+#define VHT_SIG_B_MU160_INFO_TAIL_LSB                                               23
+#define VHT_SIG_B_MU160_INFO_TAIL_MSB                                               28
+#define VHT_SIG_B_MU160_INFO_TAIL_MASK                                              0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET                                      0x00000000
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET                                   0x00000004
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET                                     0x00000004
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET                                   0x00000008
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET                                      0x00000008
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET                                     0x00000008
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET                                      0x00000008
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET                                   0x0000000c
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET                                      0x0000000c
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET                                     0x0000000c
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET                                      0x0000000c
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET                                   0x00000010
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET                                      0x00000010
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET                                     0x00000010
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET                                      0x00000010
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET                                   0x00000014
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET                                      0x00000014
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET                                     0x00000014
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET                                      0x00000014
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK                                        0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET                                   0x00000018
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET                                      0x00000018
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET                                     0x00000018
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET                                  0x00000018
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB                                     29
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB                                     31
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK                                    0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET                                   0x0000001c
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB                                      0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB                                      18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK                                     0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET                                      0x0000001c
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB                                         19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB                                         22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK                                        0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET                                     0x0000001c
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB                                        23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB                                        28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK                                       0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET                                      0x0000001c
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB                                         29
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB                                         31
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK                                        0xe0000000
+
+#endif
diff --git a/hw/peach/v1/vht_sig_b_mu20_info.h b/hw/peach/v1/vht_sig_b_mu20_info.h
new file mode 100644
index 000000000000..3af2601c4424
--- /dev/null
+++ b/hw/peach/v1/vht_sig_b_mu20_info.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_MU20_INFO_H_
+#define _VHT_SIG_B_MU20_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1
+
+struct vht_sig_b_mu20_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 16,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      mu_user_number                                          :  3,
+                      reserved_0                                              :  3;
+#else
+             uint32_t reserved_0                                              :  3,
+                      mu_user_number                                          :  3,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 16;
+#endif
+};
+
+#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_MU20_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_MU20_INFO_LENGTH_MSB                                              15
+#define VHT_SIG_B_MU20_INFO_LENGTH_MASK                                             0x0000ffff
+
+#define VHT_SIG_B_MU20_INFO_MCS_OFFSET                                              0x00000000
+#define VHT_SIG_B_MU20_INFO_MCS_LSB                                                 16
+#define VHT_SIG_B_MU20_INFO_MCS_MSB                                                 19
+#define VHT_SIG_B_MU20_INFO_MCS_MASK                                                0x000f0000
+
+#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU20_INFO_TAIL_LSB                                                20
+#define VHT_SIG_B_MU20_INFO_TAIL_MSB                                                25
+#define VHT_SIG_B_MU20_INFO_TAIL_MASK                                               0x03f00000
+
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET                                   0x00000000
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB                                      26
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB                                      28
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK                                     0x1c000000
+
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB                                          29
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB                                          31
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK                                         0xe0000000
+
+#endif
diff --git a/hw/peach/v1/vht_sig_b_mu40_info.h b/hw/peach/v1/vht_sig_b_mu40_info.h
new file mode 100644
index 000000000000..565c9bd78fe0
--- /dev/null
+++ b/hw/peach/v1/vht_sig_b_mu40_info.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_MU40_INFO_H_
+#define _VHT_SIG_B_MU40_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2
+
+struct vht_sig_b_mu40_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 17,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_0                                              :  2,
+                      mu_user_number                                          :  3;
+             uint32_t length_copy                                             : 17,
+                      mcs_copy                                                :  4,
+                      tail_copy                                               :  6,
+                      reserved_1                                              :  5;
+#else
+             uint32_t mu_user_number                                          :  3,
+                      reserved_0                                              :  2,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 17;
+             uint32_t reserved_1                                              :  5,
+                      tail_copy                                               :  6,
+                      mcs_copy                                                :  4,
+                      length_copy                                             : 17;
+#endif
+};
+
+#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_MU40_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_MU40_INFO_LENGTH_MSB                                              16
+#define VHT_SIG_B_MU40_INFO_LENGTH_MASK                                             0x0001ffff
+
+#define VHT_SIG_B_MU40_INFO_MCS_OFFSET                                              0x00000000
+#define VHT_SIG_B_MU40_INFO_MCS_LSB                                                 17
+#define VHT_SIG_B_MU40_INFO_MCS_MSB                                                 20
+#define VHT_SIG_B_MU40_INFO_MCS_MASK                                                0x001e0000
+
+#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU40_INFO_TAIL_LSB                                                21
+#define VHT_SIG_B_MU40_INFO_TAIL_MSB                                                26
+#define VHT_SIG_B_MU40_INFO_TAIL_MASK                                               0x07e00000
+
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB                                          27
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB                                          28
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK                                         0x18000000
+
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET                                   0x00000000
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB                                      29
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB                                      31
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK                                     0xe0000000
+
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB                                         0
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB                                         16
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK                                        0x0001ffff
+
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET                                         0x00000004
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB                                            17
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB                                            20
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK                                           0x001e0000
+
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET                                        0x00000004
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB                                           21
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB                                           26
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK                                          0x07e00000
+
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB                                          27
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB                                          31
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK                                         0xf8000000
+
+#endif
diff --git a/hw/peach/v1/vht_sig_b_mu80_info.h b/hw/peach/v1/vht_sig_b_mu80_info.h
new file mode 100644
index 000000000000..5ede34ec87a4
--- /dev/null
+++ b/hw/peach/v1/vht_sig_b_mu80_info.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_MU80_INFO_H_
+#define _VHT_SIG_B_MU80_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4
+
+struct vht_sig_b_mu80_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 19,
+                      mcs                                                     :  4,
+                      tail                                                    :  6,
+                      reserved_0                                              :  3;
+             uint32_t length_copy_a                                           : 19,
+                      mcs_copy_a                                              :  4,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  3;
+             uint32_t length_copy_b                                           : 19,
+                      mcs_copy_b                                              :  4,
+                      tail_copy_b                                             :  6,
+                      mu_user_number                                          :  3;
+             uint32_t length_copy_c                                           : 19,
+                      mcs_copy_c                                              :  4,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  3;
+#else
+             uint32_t reserved_0                                              :  3,
+                      tail                                                    :  6,
+                      mcs                                                     :  4,
+                      length                                                  : 19;
+             uint32_t reserved_1                                              :  3,
+                      tail_copy_a                                             :  6,
+                      mcs_copy_a                                              :  4,
+                      length_copy_a                                           : 19;
+             uint32_t mu_user_number                                          :  3,
+                      tail_copy_b                                             :  6,
+                      mcs_copy_b                                              :  4,
+                      length_copy_b                                           : 19;
+             uint32_t reserved_3                                              :  3,
+                      tail_copy_c                                             :  6,
+                      mcs_copy_c                                              :  4,
+                      length_copy_c                                           : 19;
+#endif
+};
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_MU80_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_MU80_INFO_LENGTH_MSB                                              18
+#define VHT_SIG_B_MU80_INFO_LENGTH_MASK                                             0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_OFFSET                                              0x00000000
+#define VHT_SIG_B_MU80_INFO_MCS_LSB                                                 19
+#define VHT_SIG_B_MU80_INFO_MCS_MSB                                                 22
+#define VHT_SIG_B_MU80_INFO_MCS_MASK                                                0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_MU80_INFO_TAIL_LSB                                                23
+#define VHT_SIG_B_MU80_INFO_TAIL_MSB                                                28
+#define VHT_SIG_B_MU80_INFO_TAIL_MASK                                               0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB                                          29
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB                                          31
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK                                         0xe0000000
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET                                    0x00000004
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB                                       0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB                                       18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK                                      0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET                                       0x00000004
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB                                          19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB                                          22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK                                         0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET                                      0x00000004
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB                                         23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB                                         28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK                                        0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB                                          29
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB                                          31
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK                                         0xe0000000
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET                                    0x00000008
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB                                       0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB                                       18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK                                      0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET                                       0x00000008
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB                                          19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB                                          22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK                                         0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET                                      0x00000008
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB                                         23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB                                         28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK                                        0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET                                   0x00000008
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB                                      29
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB                                      31
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK                                     0xe0000000
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET                                    0x0000000c
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB                                       0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB                                       18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK                                      0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET                                       0x0000000c
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB                                          19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB                                          22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK                                         0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET                                      0x0000000c
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB                                         23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB                                         28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK                                        0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET                                       0x0000000c
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB                                          29
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB                                          31
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK                                         0xe0000000
+
+#endif
diff --git a/hw/peach/v1/vht_sig_b_su160_info.h b/hw/peach/v1/vht_sig_b_su160_info.h
new file mode 100644
index 000000000000..53e8156dc937
--- /dev/null
+++ b/hw/peach/v1/vht_sig_b_su160_info.h
@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_SU160_INFO_H_
+#define _VHT_SIG_B_SU160_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8
+
+struct vht_sig_b_su160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 21,
+                      vhtb_reserved                                           :  2,
+                      tail                                                    :  6,
+                      reserved_0                                              :  2,
+                      rx_ndp                                                  :  1;
+             uint32_t length_copy_a                                           : 21,
+                      vhtb_reserved_copy_a                                    :  2,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  2,
+                      rx_ndp_copy_a                                           :  1;
+             uint32_t length_copy_b                                           : 21,
+                      vhtb_reserved_copy_b                                    :  2,
+                      tail_copy_b                                             :  6,
+                      reserved_2                                              :  2,
+                      rx_ndp_copy_b                                           :  1;
+             uint32_t length_copy_c                                           : 21,
+                      vhtb_reserved_copy_c                                    :  2,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  2,
+                      rx_ndp_copy_c                                           :  1;
+             uint32_t length_copy_d                                           : 21,
+                      vhtb_reserved_copy_d                                    :  2,
+                      tail_copy_d                                             :  6,
+                      reserved_4                                              :  2,
+                      rx_ndp_copy_d                                           :  1;
+             uint32_t length_copy_e                                           : 21,
+                      vhtb_reserved_copy_e                                    :  2,
+                      tail_copy_e                                             :  6,
+                      reserved_5                                              :  2,
+                      rx_ndp_copy_e                                           :  1;
+             uint32_t length_copy_f                                           : 21,
+                      vhtb_reserved_copy_f                                    :  2,
+                      tail_copy_f                                             :  6,
+                      reserved_6                                              :  2,
+                      rx_ndp_copy_f                                           :  1;
+             uint32_t length_copy_g                                           : 21,
+                      vhtb_reserved_copy_g                                    :  2,
+                      tail_copy_g                                             :  6,
+                      reserved_7                                              :  2,
+                      rx_ndp_copy_g                                           :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved_0                                              :  2,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  2,
+                      length                                                  : 21;
+             uint32_t rx_ndp_copy_a                                           :  1,
+                      reserved_1                                              :  2,
+                      tail_copy_a                                             :  6,
+                      vhtb_reserved_copy_a                                    :  2,
+                      length_copy_a                                           : 21;
+             uint32_t rx_ndp_copy_b                                           :  1,
+                      reserved_2                                              :  2,
+                      tail_copy_b                                             :  6,
+                      vhtb_reserved_copy_b                                    :  2,
+                      length_copy_b                                           : 21;
+             uint32_t rx_ndp_copy_c                                           :  1,
+                      reserved_3                                              :  2,
+                      tail_copy_c                                             :  6,
+                      vhtb_reserved_copy_c                                    :  2,
+                      length_copy_c                                           : 21;
+             uint32_t rx_ndp_copy_d                                           :  1,
+                      reserved_4                                              :  2,
+                      tail_copy_d                                             :  6,
+                      vhtb_reserved_copy_d                                    :  2,
+                      length_copy_d                                           : 21;
+             uint32_t rx_ndp_copy_e                                           :  1,
+                      reserved_5                                              :  2,
+                      tail_copy_e                                             :  6,
+                      vhtb_reserved_copy_e                                    :  2,
+                      length_copy_e                                           : 21;
+             uint32_t rx_ndp_copy_f                                           :  1,
+                      reserved_6                                              :  2,
+                      tail_copy_f                                             :  6,
+                      vhtb_reserved_copy_f                                    :  2,
+                      length_copy_f                                           : 21;
+             uint32_t rx_ndp_copy_g                                           :  1,
+                      reserved_7                                              :  2,
+                      tail_copy_g                                             :  6,
+                      vhtb_reserved_copy_g                                    :  2,
+                      length_copy_g                                           : 21;
+#endif
+};
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET                                          0x00000000
+#define VHT_SIG_B_SU160_INFO_LENGTH_LSB                                             0
+#define VHT_SIG_B_SU160_INFO_LENGTH_MSB                                             20
+#define VHT_SIG_B_SU160_INFO_LENGTH_MASK                                            0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET                                   0x00000000
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB                                      21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB                                      22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK                                     0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET                                            0x00000000
+#define VHT_SIG_B_SU160_INFO_TAIL_LSB                                               23
+#define VHT_SIG_B_SU160_INFO_TAIL_MSB                                               28
+#define VHT_SIG_B_SU160_INFO_TAIL_MASK                                              0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET                                      0x00000000
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET                                          0x00000000
+#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB                                             31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB                                             31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK                                            0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET                                   0x00000004
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET                            0x00000004
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET                                     0x00000004
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET                                   0x00000004
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET                                   0x00000008
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET                            0x00000008
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET                                     0x00000008
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET                                      0x00000008
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET                                   0x00000008
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET                                   0x0000000c
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET                            0x0000000c
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET                                     0x0000000c
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET                                      0x0000000c
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET                                   0x0000000c
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET                                   0x00000010
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET                            0x00000010
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET                                     0x00000010
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET                                      0x00000010
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET                                   0x00000010
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET                                   0x00000014
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET                            0x00000014
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET                                     0x00000014
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET                                      0x00000014
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET                                   0x00000014
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET                                   0x00000018
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET                            0x00000018
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET                                     0x00000018
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET                                      0x00000018
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET                                   0x00000018
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK                                     0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET                                   0x0000001c
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB                                      0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB                                      20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK                                     0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET                            0x0000001c
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB                               21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB                               22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK                              0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET                                     0x0000001c
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB                                        23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB                                        28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK                                       0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET                                      0x0000001c
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB                                         29
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB                                         30
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK                                        0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET                                   0x0000001c
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB                                      31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK                                     0x80000000
+
+#endif
diff --git a/hw/peach/v1/vht_sig_b_su20_info.h b/hw/peach/v1/vht_sig_b_su20_info.h
new file mode 100644
index 000000000000..1343f424b763
--- /dev/null
+++ b/hw/peach/v1/vht_sig_b_su20_info.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_SU20_INFO_H_
+#define _VHT_SIG_B_SU20_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1
+
+struct vht_sig_b_su20_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 17,
+                      vhtb_reserved                                           :  3,
+                      tail                                                    :  6,
+                      reserved                                                :  5,
+                      rx_ndp                                                  :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved                                                :  5,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  3,
+                      length                                                  : 17;
+#endif
+};
+
+#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU20_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_SU20_INFO_LENGTH_MSB                                              16
+#define VHT_SIG_B_SU20_INFO_LENGTH_MASK                                             0x0001ffff
+
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB                                       17
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB                                       19
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK                                      0x000e0000
+
+#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_SU20_INFO_TAIL_LSB                                                20
+#define VHT_SIG_B_SU20_INFO_TAIL_MSB                                                25
+#define VHT_SIG_B_SU20_INFO_TAIL_MASK                                               0x03f00000
+
+#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET                                         0x00000000
+#define VHT_SIG_B_SU20_INFO_RESERVED_LSB                                            26
+#define VHT_SIG_B_SU20_INFO_RESERVED_MSB                                            30
+#define VHT_SIG_B_SU20_INFO_RESERVED_MASK                                           0x7c000000
+
+#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB                                              31
+#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB                                              31
+#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK                                             0x80000000
+
+#endif
diff --git a/hw/peach/v1/vht_sig_b_su40_info.h b/hw/peach/v1/vht_sig_b_su40_info.h
new file mode 100644
index 000000000000..1f0049317179
--- /dev/null
+++ b/hw/peach/v1/vht_sig_b_su40_info.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_SU40_INFO_H_
+#define _VHT_SIG_B_SU40_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2
+
+struct vht_sig_b_su40_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 19,
+                      vhtb_reserved                                           :  2,
+                      tail                                                    :  6,
+                      reserved                                                :  4,
+                      rx_ndp                                                  :  1;
+             uint32_t length_copy                                             : 19,
+                      vhtb_reserved_copy                                      :  2,
+                      tail_copy                                               :  6,
+                      reserved_copy                                           :  4,
+                      rx_ndp_copy                                             :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved                                                :  4,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  2,
+                      length                                                  : 19;
+             uint32_t rx_ndp_copy                                             :  1,
+                      reserved_copy                                           :  4,
+                      tail_copy                                               :  6,
+                      vhtb_reserved_copy                                      :  2,
+                      length_copy                                             : 19;
+#endif
+};
+
+#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU40_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_SU40_INFO_LENGTH_MSB                                              18
+#define VHT_SIG_B_SU40_INFO_LENGTH_MASK                                             0x0007ffff
+
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB                                       19
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB                                       20
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK                                      0x00180000
+
+#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_SU40_INFO_TAIL_LSB                                                21
+#define VHT_SIG_B_SU40_INFO_TAIL_MSB                                                26
+#define VHT_SIG_B_SU40_INFO_TAIL_MASK                                               0x07e00000
+
+#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET                                         0x00000000
+#define VHT_SIG_B_SU40_INFO_RESERVED_LSB                                            27
+#define VHT_SIG_B_SU40_INFO_RESERVED_MSB                                            30
+#define VHT_SIG_B_SU40_INFO_RESERVED_MASK                                           0x78000000
+
+#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB                                              31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB                                              31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK                                             0x80000000
+
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB                                         0
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB                                         18
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK                                        0x0007ffff
+
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET                               0x00000004
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB                                  19
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB                                  20
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK                                 0x00180000
+
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET                                        0x00000004
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB                                           21
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB                                           26
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK                                          0x07e00000
+
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET                                    0x00000004
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB                                       27
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB                                       30
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK                                      0x78000000
+
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB                                         31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB                                         31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK                                        0x80000000
+
+#endif
diff --git a/hw/peach/v1/vht_sig_b_su80_info.h b/hw/peach/v1/vht_sig_b_su80_info.h
new file mode 100644
index 000000000000..ac47150f8088
--- /dev/null
+++ b/hw/peach/v1/vht_sig_b_su80_info.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_SU80_INFO_H_
+#define _VHT_SIG_B_SU80_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4
+
+struct vht_sig_b_su80_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t length                                                  : 21,
+                      vhtb_reserved                                           :  2,
+                      tail                                                    :  6,
+                      reserved_0                                              :  2,
+                      rx_ndp                                                  :  1;
+             uint32_t length_copy_a                                           : 21,
+                      vhtb_reserved_copy_a                                    :  2,
+                      tail_copy_a                                             :  6,
+                      reserved_1                                              :  2,
+                      rx_ndp_copy_a                                           :  1;
+             uint32_t length_copy_b                                           : 21,
+                      vhtb_reserved_copy_b                                    :  2,
+                      tail_copy_b                                             :  6,
+                      reserved_2                                              :  2,
+                      rx_ndp_copy_b                                           :  1;
+             uint32_t length_copy_c                                           : 21,
+                      vhtb_reserved_copy_c                                    :  2,
+                      tail_copy_c                                             :  6,
+                      reserved_3                                              :  2,
+                      rx_ndp_copy_c                                           :  1;
+#else
+             uint32_t rx_ndp                                                  :  1,
+                      reserved_0                                              :  2,
+                      tail                                                    :  6,
+                      vhtb_reserved                                           :  2,
+                      length                                                  : 21;
+             uint32_t rx_ndp_copy_a                                           :  1,
+                      reserved_1                                              :  2,
+                      tail_copy_a                                             :  6,
+                      vhtb_reserved_copy_a                                    :  2,
+                      length_copy_a                                           : 21;
+             uint32_t rx_ndp_copy_b                                           :  1,
+                      reserved_2                                              :  2,
+                      tail_copy_b                                             :  6,
+                      vhtb_reserved_copy_b                                    :  2,
+                      length_copy_b                                           : 21;
+             uint32_t rx_ndp_copy_c                                           :  1,
+                      reserved_3                                              :  2,
+                      tail_copy_c                                             :  6,
+                      vhtb_reserved_copy_c                                    :  2,
+                      length_copy_c                                           : 21;
+#endif
+};
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU80_INFO_LENGTH_LSB                                              0
+#define VHT_SIG_B_SU80_INFO_LENGTH_MSB                                              20
+#define VHT_SIG_B_SU80_INFO_LENGTH_MASK                                             0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET                                    0x00000000
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB                                       21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB                                       22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK                                      0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET                                             0x00000000
+#define VHT_SIG_B_SU80_INFO_TAIL_LSB                                                23
+#define VHT_SIG_B_SU80_INFO_TAIL_MSB                                                28
+#define VHT_SIG_B_SU80_INFO_TAIL_MASK                                               0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET                                       0x00000000
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET                                           0x00000000
+#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB                                              31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB                                              31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK                                             0x80000000
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET                                    0x00000004
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB                                       0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB                                       20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK                                      0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET                             0x00000004
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB                                21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB                                22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK                               0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET                                      0x00000004
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB                                         23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB                                         28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK                                        0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET                                       0x00000004
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET                                    0x00000004
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK                                      0x80000000
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET                                    0x00000008
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB                                       0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB                                       20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK                                      0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET                             0x00000008
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB                                21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB                                22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK                               0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET                                      0x00000008
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB                                         23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB                                         28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK                                        0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET                                       0x00000008
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET                                    0x00000008
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK                                      0x80000000
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET                                    0x0000000c
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB                                       0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB                                       20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK                                      0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET                             0x0000000c
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB                                21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB                                22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK                               0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET                                      0x0000000c
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB                                         23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB                                         28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK                                        0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET                                       0x0000000c
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB                                          29
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB                                          30
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK                                         0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET                                    0x0000000c
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB                                       31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK                                      0x80000000
+
+#endif
diff --git a/hw/peach/v1/wbm2sw_completion_ring_rx.h b/hw/peach/v1/wbm2sw_completion_ring_rx.h
new file mode 100644
index 000000000000..f88a753bfbd2
--- /dev/null
+++ b/hw/peach/v1/wbm2sw_completion_ring_rx.h
@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _WBM2SW_COMPLETION_RING_RX_H_
+#define _WBM2SW_COMPLETION_RING_RX_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_mpdu_desc_info.h"
+#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8
+
+struct wbm2sw_completion_ring_rx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t release_source_module                                   :  3,
+                      bm_action                                               :  3,
+                      buffer_or_desc_type                                     :  3,
+                      return_buffer_manager                                   :  4,
+                      reserved_2a                                             :  2,
+                      cache_id                                                :  1,
+                      cookie_conversion_status                                :  1,
+                      rxdma_push_reason                                       :  2,
+                      rxdma_error_code                                        :  5,
+                      reo_push_reason                                         :  2,
+                      reo_error_code                                          :  5,
+                      wbm_internal_error                                      :  1;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t buffer_phys_addr_31_0                                   : 32;
+             uint32_t buffer_phys_addr_39_32                                  :  8,
+                      sw_buffer_cookie                                        : 20,
+                      looping_count                                           :  4;
+#else
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t wbm_internal_error                                      :  1,
+                      reo_error_code                                          :  5,
+                      reo_push_reason                                         :  2,
+                      rxdma_error_code                                        :  5,
+                      rxdma_push_reason                                       :  2,
+                      cookie_conversion_status                                :  1,
+                      cache_id                                                :  1,
+                      reserved_2a                                             :  2,
+                      return_buffer_manager                                   :  4,
+                      buffer_or_desc_type                                     :  3,
+                      bm_action                                               :  3,
+                      release_source_module                                   :  3;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t buffer_phys_addr_31_0                                   : 32;
+             uint32_t looping_count                                           :  4,
+                      sw_buffer_cookie                                        : 20,
+                      buffer_phys_addr_39_32                                  :  8;
+#endif
+};
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET                      0x00000000
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB                         0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB                         31
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK                        0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET                     0x00000004
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB                        0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB                        31
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK                       0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET                      0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB                         0
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB                         2
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK                        0x00000007
+
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET                                  0x00000008
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB                                     3
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB                                     5
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK                                    0x00000038
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET                        0x00000008
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB                           6
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB                           8
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK                          0x000001c0
+
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET                      0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB                         9
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB                         12
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK                        0x00001e00
+
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET                                0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB                                   13
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB                                   14
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK                                  0x00006000
+
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET                                   0x00000008
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB                                      15
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB                                      15
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK                                     0x00008000
+
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET                   0x00000008
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB                      16
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB                      16
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK                     0x00010000
+
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET                          0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB                             17
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB                             18
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK                            0x00060000
+
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET                           0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB                              19
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB                              23
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK                             0x00f80000
+
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET                            0x00000008
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB                               24
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB                               25
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK                              0x03000000
+
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET                             0x00000008
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB                                26
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB                                30
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK                               0x7c000000
+
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET                         0x00000008
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB                            31
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB                            31
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK                           0x80000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET       0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB          0
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB          7
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK         0x000000ff
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET    0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB       8
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB       8
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK      0x00000100
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET   0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB      9
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB      9
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK     0x00000200
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET       0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB          10
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB          10
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK         0x00000400
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET        0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB           11
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB           11
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK          0x00000800
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET         0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB            13
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB            13
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK           0x00002000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB  14
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB  14
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET         0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB            15
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB            26
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK           0x07ff8000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET              0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB                 28
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB                 31
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK                0xf0000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET   0x00000010
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB      0
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB      31
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK     0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB   2
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB   2
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK  0x00000004
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET      0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB         3
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB         16
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK        0x0001fff8
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET        0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB           17
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB           17
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK          0x00020000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET      0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB         18
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB         18
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK        0x00040000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET      0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB         19
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB         19
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK        0x00080000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET       0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB          20
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB          20
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK         0x00100000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET   0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB      23
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB      23
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK     0x00800000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET            0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB               24
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB               24
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK              0x01000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET            0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB               25
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB               25
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK              0x02000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET        0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB           26
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB           26
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK          0x04000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET     0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB        27
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB        28
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK       0x18000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET     0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB        29
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB        30
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK       0x60000000
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET                      0x00000018
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB                         0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB                         31
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK                        0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET                     0x0000001c
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB                        0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB                        7
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK                       0x000000ff
+
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET                           0x0000001c
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB                              8
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB                              27
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK                             0x0fffff00
+
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET                              0x0000001c
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB                                 28
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB                                 31
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK                                0xf0000000
+
+#endif
diff --git a/hw/peach/v1/wbm2sw_completion_ring_tx.h b/hw/peach/v1/wbm2sw_completion_ring_tx.h
new file mode 100644
index 000000000000..713cd8f04669
--- /dev/null
+++ b/hw/peach/v1/wbm2sw_completion_ring_tx.h
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _WBM2SW_COMPLETION_RING_TX_H_
+#define _WBM2SW_COMPLETION_RING_TX_H_
+
+#include "tx_rate_stats_info.h"
+#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8
+
+struct wbm2sw_completion_ring_tx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t release_source_module                                   :  3,
+                      cache_id                                                :  1,
+                      reserved_2a                                             :  2,
+                      buffer_or_desc_type                                     :  3,
+                      return_buffer_manager                                   :  4,
+                      tqm_release_reason                                      :  4,
+                      rbm_override_valid                                      :  1,
+                      sw_buffer_cookie_11_0                                   : 12,
+                      cookie_conversion_status                                :  1,
+                      wbm_internal_error                                      :  1;
+             uint32_t tqm_status_number                                       : 24,
+                      transmit_count                                          :  7,
+                      sw_release_details_valid                                :  1;
+             uint32_t ack_frame_rssi                                          :  8,
+                      first_msdu                                              :  1,
+                      last_msdu                                               :  1,
+                      fw_tx_notify_frame                                      :  3,
+                      buffer_timestamp                                        : 19;
+             struct   tx_rate_stats_info                                        tx_rate_stats;
+             uint32_t sw_peer_id                                              : 16,
+                      tid                                                     :  4,
+                      sw_buffer_cookie_19_12                                  :  8,
+                      looping_count                                           :  4;
+#else
+             uint32_t buffer_virt_addr_31_0                                   : 32;
+             uint32_t buffer_virt_addr_63_32                                  : 32;
+             uint32_t wbm_internal_error                                      :  1,
+                      cookie_conversion_status                                :  1,
+                      sw_buffer_cookie_11_0                                   : 12,
+                      rbm_override_valid                                      :  1,
+                      tqm_release_reason                                      :  4,
+                      return_buffer_manager                                   :  4,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2a                                             :  2,
+                      cache_id                                                :  1,
+                      release_source_module                                   :  3;
+             uint32_t sw_release_details_valid                                :  1,
+                      transmit_count                                          :  7,
+                      tqm_status_number                                       : 24;
+             uint32_t buffer_timestamp                                        : 19,
+                      fw_tx_notify_frame                                      :  3,
+                      last_msdu                                               :  1,
+                      first_msdu                                              :  1,
+                      ack_frame_rssi                                          :  8;
+             struct   tx_rate_stats_info                                        tx_rate_stats;
+             uint32_t looping_count                                           :  4,
+                      sw_buffer_cookie_19_12                                  :  8,
+                      tid                                                     :  4,
+                      sw_peer_id                                              : 16;
+#endif
+};
+
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET                      0x00000000
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB                         0
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB                         31
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK                        0xffffffff
+
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET                     0x00000004
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB                        0
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB                        31
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK                       0xffffffff
+
+#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET                      0x00000008
+#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB                         0
+#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB                         2
+#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK                        0x00000007
+
+#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET                                   0x00000008
+#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB                                      3
+#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB                                      3
+#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK                                     0x00000008
+
+#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET                                0x00000008
+#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB                                   4
+#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB                                   5
+#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK                                  0x00000030
+
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET                        0x00000008
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB                           6
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB                           8
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK                          0x000001c0
+
+#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET                      0x00000008
+#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB                         9
+#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB                         12
+#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK                        0x00001e00
+
+#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET                         0x00000008
+#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB                            13
+#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB                            16
+#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK                           0x0001e000
+
+#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET                         0x00000008
+#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB                            17
+#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB                            17
+#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK                           0x00020000
+
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET                      0x00000008
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB                         18
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB                         29
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK                        0x3ffc0000
+
+#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET                   0x00000008
+#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB                      30
+#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB                      30
+#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK                     0x40000000
+
+#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET                         0x00000008
+#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB                            31
+#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB                            31
+#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK                           0x80000000
+
+#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET                          0x0000000c
+#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB                             0
+#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB                             23
+#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK                            0x00ffffff
+
+#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET                             0x0000000c
+#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB                                24
+#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB                                30
+#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK                               0x7f000000
+
+#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET                   0x0000000c
+#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB                      31
+#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB                      31
+#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK                     0x80000000
+
+#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET                             0x00000010
+#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB                                0
+#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB                                7
+#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK                               0x000000ff
+
+#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET                                 0x00000010
+#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB                                    8
+#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB                                    8
+#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK                                   0x00000100
+
+#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET                                  0x00000010
+#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB                                     9
+#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB                                     9
+#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK                                    0x00000200
+
+#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET                         0x00000010
+#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB                            10
+#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB                            12
+#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK                           0x00001c00
+
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET                           0x00000010
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB                              13
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB                              31
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK                             0xffffe000
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET     0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB        0
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB        0
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK       0x00000001
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET                  0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB                     1
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB                     3
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK                    0x0000000e
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET            0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB               4
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB               7
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK              0x000000f0
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET                0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB                   8
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB                   8
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK                  0x00000100
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET                0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB                   9
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB                   9
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK                  0x00000200
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET                 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB                    10
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB                    11
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK                   0x00000c00
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET                 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB                    12
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB                    15
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK                   0x0000f000
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET           0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB              16
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB              16
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK             0x00010000
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET                  0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB                     17
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB                     28
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK                    0x1ffe0000
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET                 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB                    29
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB                    31
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK                   0xe0000000
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET        0x00000018
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB           0
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB           31
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK          0xffffffff
+
+#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET                                 0x0000001c
+#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB                                    0
+#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB                                    15
+#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK                                   0x0000ffff
+
+#define WBM2SW_COMPLETION_RING_TX_TID_OFFSET                                        0x0000001c
+#define WBM2SW_COMPLETION_RING_TX_TID_LSB                                           16
+#define WBM2SW_COMPLETION_RING_TX_TID_MSB                                           19
+#define WBM2SW_COMPLETION_RING_TX_TID_MASK                                          0x000f0000
+
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET                     0x0000001c
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB                        20
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB                        27
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK                       0x0ff00000
+
+#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET                              0x0000001c
+#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB                                 28
+#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB                                 31
+#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK                                0xf0000000
+
+#endif
diff --git a/hw/peach/v1/wbm_buffer_ring.h b/hw/peach/v1/wbm_buffer_ring.h
new file mode 100644
index 000000000000..eb472a7841e2
--- /dev/null
+++ b/hw/peach/v1/wbm_buffer_ring.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _WBM_BUFFER_RING_H_
+#define _WBM_BUFFER_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_BUFFER_RING 2
+
+struct wbm_buffer_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          buf_addr_info;
+#else
+             struct   buffer_addr_info                                          buf_addr_info;
+#endif
+};
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET                       0x00000000
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB                          0
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB                          31
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK                         0xffffffff
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET                      0x00000004
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB                         0
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB                         7
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK                        0x000000ff
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET                  0x00000004
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB                     8
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB                     11
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK                    0x00000f00
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET                       0x00000004
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB                          12
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB                          31
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK                         0xfffff000
+
+#endif
diff --git a/hw/peach/v1/wbm_link_descriptor_ring.h b/hw/peach/v1/wbm_link_descriptor_ring.h
new file mode 100644
index 000000000000..96e225e81c7f
--- /dev/null
+++ b/hw/peach/v1/wbm_link_descriptor_ring.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _WBM_LINK_DESCRIPTOR_RING_H_
+#define _WBM_LINK_DESCRIPTOR_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2
+
+struct wbm_link_descriptor_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          desc_addr_info;
+#else
+             struct   buffer_addr_info                                          desc_addr_info;
+#endif
+};
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET             0x00000000
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB                0
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB                31
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK               0xffffffff
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET            0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB               0
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB               7
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK              0x000000ff
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET        0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB           8
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB           11
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK          0x00000f00
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET             0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB                12
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB                31
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK               0xfffff000
+
+#endif
diff --git a/hw/peach/v1/wbm_release_ring.h b/hw/peach/v1/wbm_release_ring.h
new file mode 100644
index 000000000000..06978a0b66d8
--- /dev/null
+++ b/hw/peach/v1/wbm_release_ring.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _WBM_RELEASE_RING_H_
+#define _WBM_RELEASE_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_RELEASE_RING 8
+
+struct wbm_release_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t release_source_module                                   :  3,
+                      reserved_2a                                             :  3,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2b                                             : 22,
+                      wbm_internal_error                                      :  1;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 28,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t wbm_internal_error                                      :  1,
+                      reserved_2b                                             : 22,
+                      buffer_or_desc_type                                     :  3,
+                      reserved_2a                                             :  3,
+                      release_source_module                                   :  3;
+             uint32_t reserved_3a                                             : 32;
+             uint32_t reserved_4a                                             : 32;
+             uint32_t reserved_5a                                             : 32;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t looping_count                                           :  4,
+                      reserved_7a                                             : 28;
+#endif
+};
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET    0x00000000
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB       0
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB       31
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK      0xffffffff
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET   0x00000004
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB      0
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB      7
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK     0x000000ff
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB  8
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB  11
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET    0x00000004
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB       12
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB       31
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK      0xfffff000
+
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET                               0x00000008
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB                                  0
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB                                  2
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK                                 0x00000007
+
+#define WBM_RELEASE_RING_RESERVED_2A_OFFSET                                         0x00000008
+#define WBM_RELEASE_RING_RESERVED_2A_LSB                                            3
+#define WBM_RELEASE_RING_RESERVED_2A_MSB                                            5
+#define WBM_RELEASE_RING_RESERVED_2A_MASK                                           0x00000038
+
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET                                 0x00000008
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB                                    6
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB                                    8
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK                                   0x000001c0
+
+#define WBM_RELEASE_RING_RESERVED_2B_OFFSET                                         0x00000008
+#define WBM_RELEASE_RING_RESERVED_2B_LSB                                            9
+#define WBM_RELEASE_RING_RESERVED_2B_MSB                                            30
+#define WBM_RELEASE_RING_RESERVED_2B_MASK                                           0x7ffffe00
+
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET                                  0x00000008
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB                                     31
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB                                     31
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK                                    0x80000000
+
+#define WBM_RELEASE_RING_RESERVED_3A_OFFSET                                         0x0000000c
+#define WBM_RELEASE_RING_RESERVED_3A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_3A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_3A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_4A_OFFSET                                         0x00000010
+#define WBM_RELEASE_RING_RESERVED_4A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_4A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_4A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_5A_OFFSET                                         0x00000014
+#define WBM_RELEASE_RING_RESERVED_5A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_5A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_5A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_6A_OFFSET                                         0x00000018
+#define WBM_RELEASE_RING_RESERVED_6A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_6A_MSB                                            31
+#define WBM_RELEASE_RING_RESERVED_6A_MASK                                           0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_7A_OFFSET                                         0x0000001c
+#define WBM_RELEASE_RING_RESERVED_7A_LSB                                            0
+#define WBM_RELEASE_RING_RESERVED_7A_MSB                                            27
+#define WBM_RELEASE_RING_RESERVED_7A_MASK                                           0x0fffffff
+
+#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET                                       0x0000001c
+#define WBM_RELEASE_RING_LOOPING_COUNT_LSB                                          28
+#define WBM_RELEASE_RING_LOOPING_COUNT_MSB                                          31
+#define WBM_RELEASE_RING_LOOPING_COUNT_MASK                                         0xf0000000
+
+#endif
diff --git a/hw/peach/v1/wbm_release_ring_rx.h b/hw/peach/v1/wbm_release_ring_rx.h
new file mode 100644
index 000000000000..dd3c0d39f317
--- /dev/null
+++ b/hw/peach/v1/wbm_release_ring_rx.h
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _WBM_RELEASE_RING_RX_H_
+#define _WBM_RELEASE_RING_RX_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 8
+
+struct wbm_release_ring_rx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t release_source_module                                   :  3,
+                      bm_action                                               :  3,
+                      buffer_or_desc_type                                     :  3,
+                      first_msdu_index                                        :  4,
+                      reserved_2a                                             :  2,
+                      cache_id                                                :  1,
+                      cookie_conversion_status                                :  1,
+                      rxdma_push_reason                                       :  2,
+                      rxdma_error_code                                        :  5,
+                      reo_push_reason                                         :  2,
+                      reo_error_code                                          :  5,
+                      wbm_internal_error                                      :  1;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t reserved_7a                                             : 20,
+                      ring_id                                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t wbm_internal_error                                      :  1,
+                      reo_error_code                                          :  5,
+                      reo_push_reason                                         :  2,
+                      rxdma_error_code                                        :  5,
+                      rxdma_push_reason                                       :  2,
+                      cookie_conversion_status                                :  1,
+                      cache_id                                                :  1,
+                      reserved_2a                                             :  2,
+                      first_msdu_index                                        :  4,
+                      buffer_or_desc_type                                     :  3,
+                      bm_action                                               :  3,
+                      release_source_module                                   :  3;
+             struct   rx_mpdu_desc_info                                         rx_mpdu_desc_info_details;
+             struct   rx_msdu_desc_info                                         rx_msdu_desc_info_details;
+             uint32_t reserved_6a                                             : 32;
+             uint32_t looping_count                                           :  4,
+                      ring_id                                                 :  8,
+                      reserved_7a                                             : 20;
+#endif
+};
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB    0
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB    31
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK   0xffffffff
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB   0
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB   7
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK  0x000000ff
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB    12
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB    31
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK   0xfffff000
+
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET                            0x00000008
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB                               0
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB                               2
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK                              0x00000007
+
+#define WBM_RELEASE_RING_RX_BM_ACTION_OFFSET                                        0x00000008
+#define WBM_RELEASE_RING_RX_BM_ACTION_LSB                                           3
+#define WBM_RELEASE_RING_RX_BM_ACTION_MSB                                           5
+#define WBM_RELEASE_RING_RX_BM_ACTION_MASK                                          0x00000038
+
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET                              0x00000008
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB                                 6
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB                                 8
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK                                0x000001c0
+
+#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_OFFSET                                 0x00000008
+#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_LSB                                    9
+#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MSB                                    12
+#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MASK                                   0x00001e00
+
+#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET                                      0x00000008
+#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB                                         13
+#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB                                         14
+#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK                                        0x00006000
+
+#define WBM_RELEASE_RING_RX_CACHE_ID_OFFSET                                         0x00000008
+#define WBM_RELEASE_RING_RX_CACHE_ID_LSB                                            15
+#define WBM_RELEASE_RING_RX_CACHE_ID_MSB                                            15
+#define WBM_RELEASE_RING_RX_CACHE_ID_MASK                                           0x00008000
+
+#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET                         0x00000008
+#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_LSB                            16
+#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MSB                            16
+#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MASK                           0x00010000
+
+#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_OFFSET                                0x00000008
+#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_LSB                                   17
+#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MSB                                   18
+#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MASK                                  0x00060000
+
+#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_OFFSET                                 0x00000008
+#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_LSB                                    19
+#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MSB                                    23
+#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MASK                                   0x00f80000
+
+#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_OFFSET                                  0x00000008
+#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_LSB                                     24
+#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MSB                                     25
+#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MASK                                    0x03000000
+
+#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_OFFSET                                   0x00000008
+#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_LSB                                      26
+#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MSB                                      30
+#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MASK                                     0x7c000000
+
+#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_OFFSET                               0x00000008
+#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_LSB                                  31
+#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MSB                                  31
+#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MASK                                 0x80000000
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET             0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB                0
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB                7
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK               0x000000ff
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET          0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB             8
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB             8
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK            0x00000100
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET         0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB            9
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB            9
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK           0x00000200
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET             0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB                10
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB                10
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK               0x00000400
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET              0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB                 11
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB                 11
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK                0x00000800
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET               0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB                  13
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB                  13
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK                 0x00002000
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET     0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB        14
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB        14
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK       0x00004000
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET               0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB                  15
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB                  26
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK                 0x07ff8000
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB    27
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB    27
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK   0x08000000
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET                    0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB                       28
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB                       31
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK                      0xf0000000
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET         0x00000010
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB            0
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB            31
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK           0xffffffff
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB   0
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB   0
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK  0x00000001
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB    1
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB    1
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK   0x00000002
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET      0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB         2
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB         2
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK        0x00000004
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET            0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB               3
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB               16
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK              0x0001fff8
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET              0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB                 17
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB                 17
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK                0x00020000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET            0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB               18
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB               18
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK              0x00040000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET            0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB               19
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB               19
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK              0x00080000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET             0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB                20
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB                20
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK               0x00100000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET  0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB     21
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB     21
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK    0x00200000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET    0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB       22
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB       22
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK      0x00400000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET         0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB            23
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB            23
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK           0x00800000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET                  0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB                     24
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB                     24
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK                    0x01000000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET                  0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB                     25
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB                     25
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK                    0x02000000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET              0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB                 26
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB                 26
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK                0x04000000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET           0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB              27
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB              28
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK             0x18000000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET           0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB              29
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB              30
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK             0x60000000
+
+#define WBM_RELEASE_RING_RX_RESERVED_6A_OFFSET                                      0x00000018
+#define WBM_RELEASE_RING_RX_RESERVED_6A_LSB                                         0
+#define WBM_RELEASE_RING_RX_RESERVED_6A_MSB                                         31
+#define WBM_RELEASE_RING_RX_RESERVED_6A_MASK                                        0xffffffff
+
+#define WBM_RELEASE_RING_RX_RESERVED_7A_OFFSET                                      0x0000001c
+#define WBM_RELEASE_RING_RX_RESERVED_7A_LSB                                         0
+#define WBM_RELEASE_RING_RX_RESERVED_7A_MSB                                         19
+#define WBM_RELEASE_RING_RX_RESERVED_7A_MASK                                        0x000fffff
+
+#define WBM_RELEASE_RING_RX_RING_ID_OFFSET                                          0x0000001c
+#define WBM_RELEASE_RING_RX_RING_ID_LSB                                             20
+#define WBM_RELEASE_RING_RX_RING_ID_MSB                                             27
+#define WBM_RELEASE_RING_RX_RING_ID_MASK                                            0x0ff00000
+
+#define WBM_RELEASE_RING_RX_LOOPING_COUNT_OFFSET                                    0x0000001c
+#define WBM_RELEASE_RING_RX_LOOPING_COUNT_LSB                                       28
+#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MSB                                       31
+#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MASK                                      0xf0000000
+
+#endif
diff --git a/hw/peach/v1/wbm_release_ring_tx.h b/hw/peach/v1/wbm_release_ring_tx.h
new file mode 100644
index 000000000000..283568ff81a8
--- /dev/null
+++ b/hw/peach/v1/wbm_release_ring_tx.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _WBM_RELEASE_RING_TX_H_
+#define _WBM_RELEASE_RING_TX_H_
+
+#include "tx_rate_stats_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 8
+
+struct wbm_release_ring_tx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t release_source_module                                   :  3,
+                      bm_action                                               :  3,
+                      buffer_or_desc_type                                     :  3,
+                      first_msdu_index                                        :  4,
+                      tqm_release_reason                                      :  4,
+                      rbm_override_valid                                      :  1,
+                      rbm_override                                            :  4,
+                      reserved_2a                                             :  7,
+                      cache_id                                                :  1,
+                      cookie_conversion_status                                :  1,
+                      wbm_internal_error                                      :  1;
+             uint32_t tqm_status_number                                       : 24,
+                      transmit_count                                          :  7,
+                      sw_release_details_valid                                :  1;
+             uint32_t ack_frame_rssi                                          :  8,
+                      first_msdu                                              :  1,
+                      last_msdu                                               :  1,
+                      fw_tx_notify_frame                                      :  3,
+                      buffer_timestamp                                        : 19;
+             struct   tx_rate_stats_info                                        tx_rate_stats;
+             uint32_t sw_peer_id                                              : 16,
+                      tid                                                     :  4,
+                      tqm_status_number_31_24                                 :  8,
+                      looping_count                                           :  4;
+#else
+             struct   buffer_addr_info                                          released_buff_or_desc_addr_info;
+             uint32_t wbm_internal_error                                      :  1,
+                      cookie_conversion_status                                :  1,
+                      cache_id                                                :  1,
+                      reserved_2a                                             :  7,
+                      rbm_override                                            :  4,
+                      rbm_override_valid                                      :  1,
+                      tqm_release_reason                                      :  4,
+                      first_msdu_index                                        :  4,
+                      buffer_or_desc_type                                     :  3,
+                      bm_action                                               :  3,
+                      release_source_module                                   :  3;
+             uint32_t sw_release_details_valid                                :  1,
+                      transmit_count                                          :  7,
+                      tqm_status_number                                       : 24;
+             uint32_t buffer_timestamp                                        : 19,
+                      fw_tx_notify_frame                                      :  3,
+                      last_msdu                                               :  1,
+                      first_msdu                                              :  1,
+                      ack_frame_rssi                                          :  8;
+             struct   tx_rate_stats_info                                        tx_rate_stats;
+             uint32_t looping_count                                           :  4,
+                      tqm_status_number_31_24                                 :  8,
+                      tid                                                     :  4,
+                      sw_peer_id                                              : 16;
+#endif
+};
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB    0
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB    31
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK   0xffffffff
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB   0
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB   7
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK  0x000000ff
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB    12
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB    31
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK   0xfffff000
+
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET                            0x00000008
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB                               0
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB                               2
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK                              0x00000007
+
+#define WBM_RELEASE_RING_TX_BM_ACTION_OFFSET                                        0x00000008
+#define WBM_RELEASE_RING_TX_BM_ACTION_LSB                                           3
+#define WBM_RELEASE_RING_TX_BM_ACTION_MSB                                           5
+#define WBM_RELEASE_RING_TX_BM_ACTION_MASK                                          0x00000038
+
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET                              0x00000008
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB                                 6
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB                                 8
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK                                0x000001c0
+
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_OFFSET                                 0x00000008
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_LSB                                    9
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MSB                                    12
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MASK                                   0x00001e00
+
+#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_OFFSET                               0x00000008
+#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_LSB                                  13
+#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MSB                                  16
+#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MASK                                 0x0001e000
+
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_OFFSET                               0x00000008
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_LSB                                  17
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MSB                                  17
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MASK                                 0x00020000
+
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_OFFSET                                     0x00000008
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_LSB                                        18
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MSB                                        21
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MASK                                       0x003c0000
+
+#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET                                      0x00000008
+#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB                                         22
+#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB                                         28
+#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK                                        0x1fc00000
+
+#define WBM_RELEASE_RING_TX_CACHE_ID_OFFSET                                         0x00000008
+#define WBM_RELEASE_RING_TX_CACHE_ID_LSB                                            29
+#define WBM_RELEASE_RING_TX_CACHE_ID_MSB                                            29
+#define WBM_RELEASE_RING_TX_CACHE_ID_MASK                                           0x20000000
+
+#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET                         0x00000008
+#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_LSB                            30
+#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MSB                            30
+#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MASK                           0x40000000
+
+#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_OFFSET                               0x00000008
+#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_LSB                                  31
+#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MSB                                  31
+#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MASK                                 0x80000000
+
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET                                0x0000000c
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB                                   0
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB                                   23
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK                                  0x00ffffff
+
+#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_OFFSET                                   0x0000000c
+#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_LSB                                      24
+#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MSB                                      30
+#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MASK                                     0x7f000000
+
+#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET                         0x0000000c
+#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_LSB                            31
+#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MSB                            31
+#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MASK                           0x80000000
+
+#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_OFFSET                                   0x00000010
+#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_LSB                                      0
+#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MSB                                      7
+#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MASK                                     0x000000ff
+
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_OFFSET                                       0x00000010
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_LSB                                          8
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_MSB                                          8
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_MASK                                         0x00000100
+
+#define WBM_RELEASE_RING_TX_LAST_MSDU_OFFSET                                        0x00000010
+#define WBM_RELEASE_RING_TX_LAST_MSDU_LSB                                           9
+#define WBM_RELEASE_RING_TX_LAST_MSDU_MSB                                           9
+#define WBM_RELEASE_RING_TX_LAST_MSDU_MASK                                          0x00000200
+
+#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET                               0x00000010
+#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_LSB                                  10
+#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MSB                                  12
+#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MASK                                 0x00001c00
+
+#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_OFFSET                                 0x00000010
+#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_LSB                                    13
+#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MSB                                    31
+#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MASK                                   0xffffe000
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET           0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB              0
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB              0
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK             0x00000001
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET                        0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB                           1
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB                           3
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK                          0x0000000e
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET                  0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB                     4
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB                     7
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK                    0x000000f0
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET                      0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB                         8
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB                         8
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK                        0x00000100
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET                      0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB                         9
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB                         9
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK                        0x00000200
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET                       0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB                          10
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB                          11
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK                         0x00000c00
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET                       0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB                          12
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB                          15
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK                         0x0000f000
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET                 0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB                    16
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB                    16
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK                   0x00010000
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET                        0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB                           17
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB                           28
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK                          0x1ffe0000
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET                       0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB                          29
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB                          31
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK                         0xe0000000
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET              0x00000018
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB                 0
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB                 31
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK                0xffffffff
+
+#define WBM_RELEASE_RING_TX_SW_PEER_ID_OFFSET                                       0x0000001c
+#define WBM_RELEASE_RING_TX_SW_PEER_ID_LSB                                          0
+#define WBM_RELEASE_RING_TX_SW_PEER_ID_MSB                                          15
+#define WBM_RELEASE_RING_TX_SW_PEER_ID_MASK                                         0x0000ffff
+
+#define WBM_RELEASE_RING_TX_TID_OFFSET                                              0x0000001c
+#define WBM_RELEASE_RING_TX_TID_LSB                                                 16
+#define WBM_RELEASE_RING_TX_TID_MSB                                                 19
+#define WBM_RELEASE_RING_TX_TID_MASK                                                0x000f0000
+
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_OFFSET                          0x0000001c
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_LSB                             20
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MSB                             27
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MASK                            0x0ff00000
+
+#define WBM_RELEASE_RING_TX_LOOPING_COUNT_OFFSET                                    0x0000001c
+#define WBM_RELEASE_RING_TX_LOOPING_COUNT_LSB                                       28
+#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MSB                                       31
+#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MASK                                      0xf0000000
+
+#endif
diff --git a/hw/peach/v1/wcss_seq_hwiobase.h b/hw/peach/v1/wcss_seq_hwiobase.h
new file mode 100644
index 000000000000..12ae56650128
--- /dev/null
+++ b/hw/peach/v1/wcss_seq_hwiobase.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef __WCSS_SEQ_HWIOBASE_H__
+#define __WCSS_SEQ_HWIOBASE_H__
+
+#define WCSS_CFGBUS_BASE                                            0x00008000
+#define WCSS_CFGBUS_BASE_SIZE                                       0x00008000
+#define WCSS_CFGBUS_BASE_PHYS                                       0x00008000
+
+#define UMAC_NOC_BASE                                               0x00140000
+#define UMAC_NOC_BASE_SIZE                                          0x00004400
+#define UMAC_NOC_BASE_PHYS                                          0x00140000
+
+#define PHYA0_BASE                                                  0x00300000
+#define PHYA0_BASE_SIZE                                             0x00300000
+#define PHYA0_BASE_PHYS                                             0x00300000
+
+#define PHYA1_BASE                                                  0x00600000
+#define PHYA1_BASE_SIZE                                             0x00300000
+#define PHYA1_BASE_PHYS                                             0x00600000
+
+#define DMAC_BASE                                                   0x00900000
+#define DMAC_BASE_SIZE                                              0x00080000
+#define DMAC_BASE_PHYS                                              0x00900000
+
+#define UMAC_BASE                                                   0x00a00000
+#define UMAC_BASE_SIZE                                              0x0004d000
+#define UMAC_BASE_PHYS                                              0x00a00000
+
+#define PMAC0_BASE                                                  0x00a80000
+#define PMAC0_BASE_SIZE                                             0x00040000
+#define PMAC0_BASE_PHYS                                             0x00a80000
+
+#define PMAC1_BASE                                                  0x00ac0000
+#define PMAC1_BASE_SIZE                                             0x00040000
+#define PMAC1_BASE_PHYS                                             0x00ac0000
+
+#define WFSS_AMCSS_BASE                                             0x00b00000
+#define WFSS_AMCSS_BASE_SIZE                                        0x00040000
+#define WFSS_AMCSS_BASE_PHYS                                        0x00b00000
+
+#define CXC_BASE                                                    0x00b40000
+#define CXC_BASE_SIZE                                               0x00010000
+#define CXC_BASE_PHYS                                               0x00b40000
+
+#define WFSS_PMM_BASE                                               0x00b50000
+#define WFSS_PMM_BASE_SIZE                                          0x00002401
+#define WFSS_PMM_BASE_PHYS                                          0x00b50000
+
+#define WFSS_CC_BASE                                                0x00b60000
+#define WFSS_CC_BASE_SIZE                                           0x00008000
+#define WFSS_CC_BASE_PHYS                                           0x00b60000
+
+#define WCMN_CORE_BASE                                              0x00b68000
+#define WCMN_CORE_BASE_SIZE                                         0x000008a9
+#define WCMN_CORE_BASE_PHYS                                         0x00b68000
+
+#define WIFI_CFGBUS_APB_TSLV_BASE                                   0x00b6b000
+#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE                              0x00001000
+#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS                              0x00b6b000
+
+#define WFSS_CFGBUS_BASE                                            0x00b6c000
+#define WFSS_CFGBUS_BASE_SIZE                                       0x000000a0
+#define WFSS_CFGBUS_BASE_PHYS                                       0x00b6c000
+
+#define WIFI_CFGBUS_AHB_TSLV_BASE                                   0x00b6d000
+#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE                              0x00001000
+#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS                              0x00b6d000
+
+#define UMAC_ACMT_BASE                                              0x00b6e000
+#define UMAC_ACMT_BASE_SIZE                                         0x00001000
+#define UMAC_ACMT_BASE_PHYS                                         0x00b6e000
+
+#define WCSS_CC_BASE                                                0x00b80000
+#define WCSS_CC_BASE_SIZE                                           0x00010000
+#define WCSS_CC_BASE_PHYS                                           0x00b80000
+
+#define PMM_TOP_BASE                                                0x00b90000
+#define PMM_TOP_BASE_SIZE                                           0x00010000
+#define PMM_TOP_BASE_PHYS                                           0x00b90000
+
+#define WCSS_TOP_CMN_BASE                                           0x00ba0000
+#define WCSS_TOP_CMN_BASE_SIZE                                      0x00004000
+#define WCSS_TOP_CMN_BASE_PHYS                                      0x00ba0000
+
+#define MSIP_BASE                                                   0x00bb0000
+#define MSIP_BASE_SIZE                                              0x00010000
+#define MSIP_BASE_PHYS                                              0x00bb0000
+
+#define DBG_BASE                                                    0x01000000
+#define DBG_BASE_SIZE                                               0x00100000
+#define DBG_BASE_PHYS                                               0x01000000
+
+#define Q6SS_WLAN_BASE                                              0x01100000
+#define Q6SS_WLAN_BASE_SIZE                                         0x00100000
+#define Q6SS_WLAN_BASE_PHYS                                         0x01100000
+
+#endif
diff --git a/hw/peach/v1/wcss_seq_hwioreg_umac.h b/hw/peach/v1/wcss_seq_hwioreg_umac.h
new file mode 100644
index 000000000000..422bba82cf92
--- /dev/null
+++ b/hw/peach/v1/wcss_seq_hwioreg_umac.h
@@ -0,0 +1,2264 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef __WCSS_SEQ_HWIOREG_UMAC_H__
+#define __WCSS_SEQ_HWIOREG_UMAC_H__
+
+#include "seq_hwio.h"
+#include "wcss_seq_hwiobase.h"
+#ifdef SCALE_INCLUDES
+#include "HALhwio.h"
+#else
+#include "msmhwio.h"
+#endif
+
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)                                                     ((x) + 0xa0)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x)                                                     ((x) + 0xa0)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS                                                        (0xa0)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK                                                               0x7
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR                                                         0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR                                                                     0x3
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x))
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK                                            0x7
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT                                              0
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)                                        ((x) + 0xa4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x)                                        ((x) + 0xa4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS                                           (0xa4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK                                            0x1ffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR                                            0x00001ffe
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK                                       0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR                                                        0x3
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK                    0x1ffe000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT                           13
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK                       0x1ffe
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT                            1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK                            0x1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT                              0
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK                                    0x1000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT                                        12
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK                                     0x800
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT                                        11
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK                                     0x400
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT                                        10
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK                                     0x200
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT                                         9
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)                                                ((x) + 0xd8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x)                                                ((x) + 0xd8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS                                                   (0xd8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK                                                   0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR                                                    0x00000000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK                                               0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR                                                                0x1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK                                 0xff000000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT                                         24
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK                                   0xff0000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT                                         16
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK                                     0xff00
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT                                          8
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK                                       0xff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT                                          0
+
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n)                                       ((base) + 0X1A4 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n)                                       ((base) + 0X1A4 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n)                                            (0X1A4 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK                                                    0xfff
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn                                                        3
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR                                                0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK                                           0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR                                                            0x1
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n)                \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK)
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK                                   0xfff
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT                                       0
+
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x)                                                    ((x) + 0x1c4)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_PHYS(x)                                                    ((x) + 0x1c4)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OFFS                                                       (0x1c4)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_RMSK                                                              0x3
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR                                                        0x00000000
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR_RMSK                                                   0xffffffff
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ATTR                                                                    0x3
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x)            \
+                in_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x))
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_INM(x, m)            \
+                in_dword_masked(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUT(x, v)            \
+                out_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x))
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_BMSK                                                 0x2
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_SHFT                                                   1
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_BMSK                                                  0x1
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_SHFT                                                    0
+
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n)                                                 ((base) + 0X508 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n)                                                 ((base) + 0X508 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n)                                                      (0X508 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK                                                         0xffffffff
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn                                                                 63
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR                                                          0x00000000
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK                                                     0xffffffff
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR                                                                      0x1
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK)
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK                                                    0xffffffff
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT                                                             0
+
+#define WBM_REG_REG_BASE                                                                                        (UMAC_BASE      + 0x00034000)
+#define HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x)                                                                      ((x) + 0x40)
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x)                                                                      ((x) + 0x44)
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK                                                             0x40000
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT                                                                  18
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK                                                          0x3e000
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT                                                               13
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK                                                             0x1f00
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT                                                                  8
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK                                                      0xff
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT                                                         0
+
+#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x)                                                                        ((x) + 0x7c)
+#define HWIO_WBM_R0_WBM_CFG_2_ADDR(x)                                                                           ((x) + 0x90)
+#define HWIO_WBM_R0_WBM_CFG_2_PHYS(x)                                                                           ((x) + 0x90)
+#define HWIO_WBM_R0_WBM_CFG_2_OFFS                                                                              (0x90)
+#define HWIO_WBM_R0_WBM_CFG_2_RMSK                                                                                    0x4b
+#define HWIO_WBM_R0_WBM_CFG_2_POR                                                                               0x00000040
+#define HWIO_WBM_R0_WBM_CFG_2_POR_RMSK                                                                          0xffffffff
+#define HWIO_WBM_R0_WBM_CFG_2_ATTR                                                                                           0x3
+#define HWIO_WBM_R0_WBM_CFG_2_IN(x)            \
+                in_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x))
+#define HWIO_WBM_R0_WBM_CFG_2_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_WBM_CFG_2_ADDR(x), m)
+#define HWIO_WBM_R0_WBM_CFG_2_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),v)
+#define HWIO_WBM_R0_WBM_CFG_2_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),m,v,HWIO_WBM_R0_WBM_CFG_2_IN(x))
+#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK                                                                   0x40
+#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_SHFT                                                                      6
+#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_BMSK                                                           0x8
+#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_SHFT                                                             3
+#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_BMSK                                                           0x2
+#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_SHFT                                                             1
+#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_BMSK                                                         0x1
+#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_SHFT                                                           0
+
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x)                                                               ((x) + 0x94)
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_BMSK                                         0x100
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_SHFT                                             8
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_BMSK                                           0x80
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_SHFT                                              7
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_BMSK                                           0x40
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_SHFT                                              6
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_BMSK                                           0x20
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_SHFT                                              5
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_BMSK                                           0x10
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_SHFT                                              4
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_BMSK                                            0x8
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_SHFT                                              3
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_BMSK                                            0x4
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_SHFT                                              2
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_BMSK                                            0x2
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_SHFT                                              1
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_BMSK                                             0x1
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_SHFT                                               0
+
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x)                                                                   ((x) + 0x240)
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK                                                       0x7fc
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT                                                           2
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK                                                    0x2
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT                                                      1
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x)                                                                      ((x) + 0x244)
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK                                0xffff0000
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT                                        16
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK                                          0xffff
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT                                               0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x)                                                   ((x) + 0x250)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x)                                                   ((x) + 0x254)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK                                    0xffffff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT                                             8
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK                                         0xff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT                                            0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x)                                               ((x) + 0x260)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x)                                               ((x) + 0x264)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK                                0x1fff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT                                       8
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK                                   0xff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT                                      0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x)                                               ((x) + 0x270)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x)                                               ((x) + 0x274)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK                                0x1fff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT                                       8
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK                                   0xff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT                                      0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x)                                                          ((x) + 0x27c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x)                                                            ((x) + 0x37c)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                       0xffff00
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                              8
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                    0x400000
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                          22
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                    0x400000
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                          22
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                0x400000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                      22
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                 0x8000000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                        27
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                 0x8000000
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                        27
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                  0x8000000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                         27
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                  0x8000000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                         27
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x8000000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                     27
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x)                                                         ((x) + 0xd3c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK                                                   0xfffff00
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT                                                           8
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x)                                                             ((x) + 0xd4c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK                                                       0x1
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT                                                         0
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                               0x8000000
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                      27
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x)                                                       ((x) + 0xe08)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK                                                 0xfffff00
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                                                         8
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x8000000
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                     27
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x)                                                       ((x) + 0xe80)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x8000000
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                     27
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x8000000
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                     27
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x8000000
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                     27
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x8000000
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                     27
+#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x8000000
+#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                     27
+#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x8000000
+#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                     27
+#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                            0x8000000
+#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                   27
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                                    ((x) + 0x1408)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                                    ((x) + 0x1408)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                                       (0x1408)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                         0x1fffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                                        0x00001000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                                   0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                                    0x3
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                            0x1fe000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                  13
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                              0x1000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                  12
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                            0xc00
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                               10
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                            0x3c0
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                6
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                             0x30
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                4
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                              0xf
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                0
+
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                                ((x) + 0x140c)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                                ((x) + 0x140c)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                                   (0x140c)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                                     0xffffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                                    0x00000fff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                               0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                                0x3
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                          0xfff000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                12
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                 0xfff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                     0
+
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                                    ((x) + 0x1410)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                                    ((x) + 0x1410)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                                       (0x1410)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                         0x1fffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                                        0x00001000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                                   0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                                    0x3
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                            0x1fe000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                  13
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                              0x1000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                  12
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                            0xc00
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                               10
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                            0x3c0
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                6
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                             0x30
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                4
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                              0xf
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                0
+
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                                ((x) + 0x1414)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                                ((x) + 0x1414)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                                   (0x1414)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                                     0xffffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                                    0x00000fff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                               0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                                0x3
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                          0xfff000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                12
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                 0xfff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                     0
+
+#define HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x)                                                                         ((x) + 0x1418)
+#define HWIO_WBM_R0_LPM_FW_CTRL_PHYS(x)                                                                         ((x) + 0x1418)
+#define HWIO_WBM_R0_LPM_FW_CTRL_OFFS                                                                            (0x1418)
+#define HWIO_WBM_R0_LPM_FW_CTRL_RMSK                                                                                  0x3f
+#define HWIO_WBM_R0_LPM_FW_CTRL_POR                                                                             0x00000000
+#define HWIO_WBM_R0_LPM_FW_CTRL_POR_RMSK                                                                        0xffffffff
+#define HWIO_WBM_R0_LPM_FW_CTRL_ATTR                                                                                         0x3
+#define HWIO_WBM_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_WBM_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_WBM_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_WBM_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_WBM_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_BMSK                                                         0x20
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_SHFT                                                            5
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_BMSK                                                         0x10
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_SHFT                                                            4
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                                    0x8
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                                      3
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                                    0x4
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                                      2
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK                                                             0x2
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT                                                               1
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                         0x1
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                           0
+
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x)                                                                  ((x) + 0x141c)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_PHYS(x)                                                                  ((x) + 0x141c)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OFFS                                                                     (0x141c)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RMSK                                                                     0xffffffff
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR                                                                      0x00000000
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR_RMSK                                                                 0xffffffff
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ATTR                                                                                  0x3
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x)            \
+                in_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x))
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x), m)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUT(x, v)            \
+                out_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),v)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x))
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_BMSK                                                          0xffe00000
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_SHFT                                                                  21
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_BMSK                                                            0x1f0000
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_SHFT                                                                  16
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_BMSK                                                                  0xf800
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_SHFT                                                                      11
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_BMSK                                                                   0x7c0
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_SHFT                                                                       6
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_BMSK                                                                    0x3e
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_SHFT                                                                       1
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_BMSK                                                                       0x1
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_SHFT                                                                         0
+
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                              ((x) + 0x2030)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                              ((x) + 0x2030)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                                 (0x2030)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                                      0x3ff
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR                                                                  0x00000000
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                             0xffffffff
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                              0x1
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_BMSK                                                 0x200
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_SHFT                                                     9
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_BMSK                                                 0x100
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_SHFT                                                     8
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                            0x80
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                               7
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                            0x40
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                               6
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK                                                     0x20
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT                                                        5
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                                  0x10
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                                     4
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                                     0x8
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                                       3
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                               0x7
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                                 0
+
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                              ((base) + 0X2034 + (0x4*(n)))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                              ((base) + 0X2034 + (0x4*(n)))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                                   (0X2034 + (0x4*(n)))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK                                                                      0xffffffff
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_MAXn                                                                             255
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR                                                                       0x00000000
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                                  0xffffffff
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ATTR                                                                                   0x1
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK)
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                                 0xffffffff
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                          0
+
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x)                                                                  ((x) + 0x3010)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x)                                                               ((x) + 0x30b8)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x)                                                             ((x) + 0x30c8)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x)                                                             ((x) + 0x30d0)
+#define REO_REG_REG_BASE                                                                                               (UMAC_BASE      + 0x00038000)
+#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x)                                                                             ((x) + 0x0)
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK                                                                    0x8
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT                                                                      3
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK                                                                     0x4
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT                                                                       2
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT                                                        28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT                                                        24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT                                                        20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT                                                        16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT                                                        12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT                                                         8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT                                                         4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT                                                         0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x)                                                                 ((x) + 0xc)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT                                                       28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT                                                       24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT                                                       20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT                                                       16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT                                                       12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT                                                        8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT                                                        4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT                                                        0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x)                                                                 ((x) + 0x10)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT                                                       28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT                                                       24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT                                                       20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT                                                       16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT                                                       12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT                                                        8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT                                                        4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT                                                        0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x)                                                       ((x) + 0x14)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x)                                                       ((x) + 0x14)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS                                                          (0x14)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR                                                           0x76543210
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK                            0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT                                    28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK                             0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT                                    24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK                              0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT                                    20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK                               0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT                                    16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK                                0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT                                    12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK                                 0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT                                     8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK                                  0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT                                     4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK                                   0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT                                     0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x)                                                       ((x) + 0x18)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x)                                                       ((x) + 0x18)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS                                                          (0x18)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR                                                           0x66666a98
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK                           0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT                                   28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK                            0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT                                   24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK                             0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT                                   20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK                              0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT                                   16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK                               0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT                                   12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK                                0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT                                    8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK                                  0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT                                     4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK                                   0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT                                     0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x)                                                       ((x) + 0x1c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x)                                                       ((x) + 0x1c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS                                                          (0x1c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR                                                           0x66666666
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK                           0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT                                   28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK                            0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT                                   24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK                             0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT                                   20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK                              0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT                                   16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK                               0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT                                   12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK                                0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT                                    8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK                                 0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT                                    4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK                                  0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT                                    0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x)                                                       ((x) + 0x20)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x)                                                       ((x) + 0x20)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS                                                          (0x20)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK                                                          0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR                                                           0x66666666
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR                                                                       0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x)            \
+                in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK                           0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT                                   28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK                            0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT                                   24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK                             0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT                                   20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK                              0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT                                   16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK                               0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT                                   12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK                                0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT                                    8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK                                 0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT                                    4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK                                  0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT                                    0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x)                                                             ((x) + 0x38)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK                                       0xf0000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT                                               28
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK                                        0xf000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT                                               24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK                                         0xf00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT                                               20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK                                          0xf0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT                                               16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK                                           0xf000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT                                               12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK                                            0xf00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT                                                8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK                                             0xf0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT                                                4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK                                              0xf
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT                                                0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x)                                                             ((x) + 0x3c)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT                                              24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT                                              20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT                                              16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT                                              12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT                                               8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT                                                4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT                                                0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x)                                                   ((x) + 0x40)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x)                                                   ((x) + 0x40)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS                                                      (0x40)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR                                                       0x55555555
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR                                                                   0x3
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x)            \
+                in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK                   0xf0000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT                           28
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK                    0xf000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT                           24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK                     0xf00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT                           20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK                      0xf0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT                           16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK                       0xf000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT                           12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK                        0xf00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT                            8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK                         0xf0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT                            4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK                          0xf
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT                            0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x)                                                   ((x) + 0x44)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x)                                                   ((x) + 0x44)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS                                                      (0x44)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR                                                       0x55555555
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR                                                                   0x3
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x)            \
+                in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK               0xf0000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT                       28
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK                   0xf000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT                          24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK                    0xf00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT                          20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK                     0xf0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT                          16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK                      0xf000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT                          12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK                       0xf00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT                           8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK                         0xf0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT                            4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK                          0xf
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT                            0
+
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x)                                                                      ((x) + 0x48)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x)                                                                      ((x) + 0x48)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS                                                                         (0x48)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK                                                                            0x1ffff
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR                                                                          0x00000000
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK                                                                     0xffffffff
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR                                                                                      0x3
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x)            \
+                in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x))
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x))
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK                                                                   0x1ffff
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT                                                                         0
+
+#define HWIO_REO_R0_PN_IN_DEST_ADDR(x)                                                                                 ((x) + 0x68)
+#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x)                                                                             ((x) + 0x6c)
+#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x)                                                                             ((x) + 0x70)
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK                                                  0x100000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT                                                        20
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK                                                          0x80000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT                                                               19
+#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK                                                                    0x40000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT                                                                         18
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK                                                                 0x3e000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT                                                                      13
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK                                                                    0x1f00
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT                                                                         8
+#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK                                                             0xff
+#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT                                                                0
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_TRANSACTION_TYPE_BMSK                                                           0x400000
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_TRANSACTION_TYPE_SHFT                                                                 22
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                         0x400000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                               22
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x)                                                                      ((x) + 0x2a8)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK                                                                 0xffff00
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT                                                                        8
+#define HWIO_REO_R0_REO_CMD_RING_MISC_TRANSACTION_TYPE_BMSK                                                              0x400000
+#define HWIO_REO_R0_REO_CMD_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    22
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x)                                                                       ((x) + 0x320)
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK                                                                  0xffff00
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT                                                                         8
+#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_BMSK                                                               0x400000
+#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_SHFT                                                                     22
+#define HWIO_REO_R0_SW2REO1_RING_MISC_TRANSACTION_TYPE_BMSK                                                              0x400000
+#define HWIO_REO_R0_SW2REO1_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    22
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x)                                                                      ((x) + 0x500)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x)                                                                      ((x) + 0x504)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK                                                                0xfffff00
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT                                                                        8
+#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x)                                                                            ((x) + 0x508)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x)                                                                          ((x) + 0x510)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x)                                                                   ((x) + 0x514)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x)                                                                   ((x) + 0x518)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x)                                                            ((x) + 0x524)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x)                                                                 ((x) + 0x548)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x)                                                                 ((x) + 0x54c)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x)                                                                     ((x) + 0x550)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x)                                                           ((x) + 0x554)
+#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x)                                                                 ((x) + 0x558)
+#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x)                                                                 ((x) + 0x55c)
+#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x)                                                                     ((x) + 0x560)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x)                                                                      ((x) + 0x578)
+#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x)                                                                      ((x) + 0x8c0)
+#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK                                                                0xfffff00
+#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT                                                                        8
+#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_BMSK                                                             0x8000000
+#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_SHFT                                                                    27
+#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_BMSK                                                              0x8000000
+#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_SHFT                                                                     27
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                         0x8000000
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                                27
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x)                                                                   ((x) + 0xaa0)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK                                                              0xffff00
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                                                                     8
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK                                                          0x8000000
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT                                                                 27
+#define HWIO_REO_R0_MISC_CFG_ADDR(x)                                                                                   ((x) + 0xb24)
+#define HWIO_REO_R0_MISC_CFG_PHYS(x)                                                                                   ((x) + 0xb24)
+#define HWIO_REO_R0_MISC_CFG_OFFS                                                                                      (0xb24)
+#define HWIO_REO_R0_MISC_CFG_RMSK                                                                                             0x1
+#define HWIO_REO_R0_MISC_CFG_POR                                                                                       0x00000000
+#define HWIO_REO_R0_MISC_CFG_POR_RMSK                                                                                  0xffffffff
+#define HWIO_REO_R0_MISC_CFG_ATTR                                                                                                   0x3
+#define HWIO_REO_R0_MISC_CFG_IN(x)            \
+                in_dword(HWIO_REO_R0_MISC_CFG_ADDR(x))
+#define HWIO_REO_R0_MISC_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_MISC_CFG_ADDR(x), m)
+#define HWIO_REO_R0_MISC_CFG_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_MISC_CFG_ADDR(x),v)
+#define HWIO_REO_R0_MISC_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_IN(x))
+#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_BMSK                                                                        0x1
+#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_SHFT                                                                          0
+
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x)                                                                         ((x) + 0xb28)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x)                                                                         ((x) + 0xb28)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS                                                                            (0xb28)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK                                                                                 0x1ff
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR                                                                             0x0000002d
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK                                                                        0xffffffff
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR                                                                                         0x3
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x)            \
+                in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x))
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x))
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK                                                             0x1fe
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT                                                                 1
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK                                                                           0x1
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT                                                                             0
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x)                                                                       ((x) + 0xb2c)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x)                                                                       ((x) + 0xb30)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x)                                                                       ((x) + 0xb34)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x)                                                                       ((x) + 0xb38)
+#define HWIO_REO_R0_MISC_CTL_ADDR(x)                                                                                   ((x) + 0xba0)
+#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK                                                                         0x1e00000
+#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT                                                                                21
+#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK                                                                     0x1e0000
+#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT                                                                           17
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                                       ((x) + 0xd78)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                                       ((x) + 0xd78)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                                          (0xd78)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                            0x1fffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                                           0x00001000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                                       0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                               0x1fe000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                     13
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                                 0x1000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                     12
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                               0xc00
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                                  10
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                               0x3c0
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                   6
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                                0x30
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                   4
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                                 0xf
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                   0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                                   ((x) + 0xd7c)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                                   ((x) + 0xd7c)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                                      (0xd7c)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                                        0xffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                                       0x00000fff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                                   0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                             0xfff000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                   12
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                    0xfff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                        0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                                       ((x) + 0xd80)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                                       ((x) + 0xd80)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                                          (0xd80)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                            0x1fffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                                           0x00001000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                                       0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                               0x1fe000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                                     13
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                                 0x1000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                                     12
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                               0xc00
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                                  10
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                               0x3c0
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                                   6
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                                0x30
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                                   4
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                                 0xf
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                                   0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                                   ((x) + 0xd84)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                                   ((x) + 0xd84)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                                      (0xd84)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                                        0xffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                                       0x00000fff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                                   0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                             0xfff000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                                   12
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                                    0xfff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                        0
+
+#define HWIO_REO_R0_CREDIT_ADDR(x)                                                                                     ((x) + 0xd88)
+#define HWIO_REO_R0_CREDIT_PHYS(x)                                                                                     ((x) + 0xd88)
+#define HWIO_REO_R0_CREDIT_OFFS                                                                                        (0xd88)
+#define HWIO_REO_R0_CREDIT_RMSK                                                                                        0xffffffff
+#define HWIO_REO_R0_CREDIT_POR                                                                                         0x00000000
+#define HWIO_REO_R0_CREDIT_POR_RMSK                                                                                    0xffffffff
+#define HWIO_REO_R0_CREDIT_ATTR                                                                                                     0x3
+#define HWIO_REO_R0_CREDIT_IN(x)            \
+                in_dword(HWIO_REO_R0_CREDIT_ADDR(x))
+#define HWIO_REO_R0_CREDIT_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_CREDIT_ADDR(x), m)
+#define HWIO_REO_R0_CREDIT_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_CREDIT_ADDR(x),v)
+#define HWIO_REO_R0_CREDIT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_CREDIT_ADDR(x),m,v,HWIO_REO_R0_CREDIT_IN(x))
+#define HWIO_REO_R0_CREDIT_VAL_BMSK                                                                                    0xffffffff
+#define HWIO_REO_R0_CREDIT_VAL_SHFT                                                                                             0
+
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x)                                                                     ((x) + 0xd8c)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_PHYS(x)                                                                     ((x) + 0xd8c)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OFFS                                                                        (0xd8c)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_RMSK                                                                               0x7
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR                                                                         0x00000002
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR_RMSK                                                                    0xffffffff
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ATTR                                                                                     0x3
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x)            \
+                in_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x))
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x), m)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),v)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),m,v,HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x))
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_BMSK                                                                        0x7
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_SHFT                                                                          0
+
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x)                                                                      ((x) + 0xd90)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_PHYS(x)                                                                      ((x) + 0xd90)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_OFFS                                                                         (0xd90)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_RMSK                                                                         0xffffffff
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR                                                                          0x00000000
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR_RMSK                                                                     0xffffffff
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ATTR                                                                                      0x1
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x))
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_BMSK                                                                     0xffffffff
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_SHFT                                                                              0
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_BMSK                                                 0x2000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_SHFT                                                     13
+#define HWIO_REO_R0_LPM_FW_CTRL_ADDR(x)                                                                                ((x) + 0xdbc)
+#define HWIO_REO_R0_LPM_FW_CTRL_PHYS(x)                                                                                ((x) + 0xdbc)
+#define HWIO_REO_R0_LPM_FW_CTRL_OFFS                                                                                   (0xdbc)
+#define HWIO_REO_R0_LPM_FW_CTRL_RMSK                                                                                          0x7
+#define HWIO_REO_R0_LPM_FW_CTRL_POR                                                                                    0x00000000
+#define HWIO_REO_R0_LPM_FW_CTRL_POR_RMSK                                                                               0xffffffff
+#define HWIO_REO_R0_LPM_FW_CTRL_ATTR                                                                                                0x3
+#define HWIO_REO_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_REO_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_REO_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_REO_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_REO_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                                           0x4
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                                             2
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                                           0x2
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                                             1
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                                0x1
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                                  0
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)                                                      ((x) + 0x2054)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x)                                                      ((x) + 0x2054)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS                                                         (0x2054)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK                                                               0xff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR                                                          0x00000000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK                                                     0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR                                                                      0x1
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x)            \
+                in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x))
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK                                                    0xff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT                                                       0
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)                                                       ((x) + 0x2058)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x)                                                       ((x) + 0x2058)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS                                                          (0x2058)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK                                                          0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR                                                           0x00000000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK                                                      0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR                                                                       0x1
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x)            \
+                in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x))
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK                                                0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT                                                         0
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x)                                                   ((x) + 0x205c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x)                                                   ((x) + 0x205c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS                                                      (0x205c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK                                                            0xff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR                                                       0x00000000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK                                                  0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR                                                                   0x2
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v)            \
+                out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK                                                 0xff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT                                                    0
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x)                                                    ((x) + 0x2060)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x)                                                    ((x) + 0x2060)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS                                                       (0x2060)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK                                                       0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR                                                        0x00000000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK                                                   0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR                                                                    0x2
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v)            \
+                out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK                                             0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT                                                      0
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)                                                 ((x) + 0x2064)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x)                                                 ((x) + 0x2064)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS                                                    (0x2064)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK                                                    0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR                                                     0x00000000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK                                                0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR                                                                 0x3
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)            \
+                in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x))
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v)            \
+                out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x))
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK                                          0xffff0000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT                                                  16
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK                                  0xfff0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT                                       4
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK                                        0x8
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT                                          3
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK                                             0x4
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT                                               2
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK                                   0x2
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT                                     1
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK                                               0x1
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT                                                 0
+
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x)                                                                          ((x) + 0x20c0)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x)                                                                          ((x) + 0x20c0)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS                                                                             (0x20c0)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK                                                                                   0x3f
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR                                                                              0x00000000
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK                                                                         0xffffffff
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR                                                                                          0x1
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x))
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK                                                         0x20
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT                                                            5
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK                                                                   0x10
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT                                                                      4
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK                                                                0x8
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT                                                                  3
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK                                                            0x4
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT                                                              2
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK                                                                      0x2
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT                                                                        1
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK                                                                  0x1
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT                                                                    0
+
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x)                                                      ((x) + 0x20c4)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x)                                                      ((x) + 0x20c4)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS                                                         (0x20c4)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK                                                         0xffffffff
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR                                                          0x00000000
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK                                                     0xffffffff
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR                                                                      0x3
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x)            \
+                in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x))
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v)            \
+                out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x))
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK                                                   0xffffffff
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT                                                            0
+
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                                     ((x) + 0x20cc)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                                     ((x) + 0x20cc)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                                        (0x20cc)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                                              0x7f
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR                                                                         0x00000000
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                                    0xffffffff
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                                     0x1
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                                   0x40
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                                      6
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                                   0x20
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                                      5
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                                         0x10
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                                            4
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                                            0x8
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                                              3
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                                      0x7
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                                        0
+
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                                     ((base) + 0X20D0 + (0x4*(n)))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                                     ((base) + 0X20D0 + (0x4*(n)))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                                          (0X20D0 + (0x4*(n)))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK                                                                             0xffffffff
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_MAXn                                                                                    255
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR                                                                              0x00000000
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                                         0xffffffff
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ATTR                                                                                          0x1
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK)
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                                        0xffffffff
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                                 0
+
+#define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x)                                                                            ((x) + 0x3020)
+#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x)                                                                             ((x) + 0x3028)
+#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x)                                                                            ((x) + 0x3048)
+#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x)                                                                            ((x) + 0x304c)
+#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x)                                                                            ((x) + 0x3050)
+#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x)                                                                            ((x) + 0x3088)
+#define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x)                                                                         ((x) + 0x30a8)
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_BMSK                                                             0x80
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_SHFT                                                                7
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_BMSK                                                    0x40
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_SHFT                                                       6
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_BMSK                                                     0x20
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_SHFT                                                        5
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_BMSK                                                           0x10
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_SHFT                                                              4
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_BMSK                                                          0x8
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_SHFT                                                            3
+#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK                                                        0x400000
+#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT                                                              22
+#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_BMSK                                                         0x400000
+#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_SHFT                                                               22
+#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_BMSK                                                         0x400000
+#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_SHFT                                                               22
+#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_BMSK                                                        0x400000
+#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_SHFT                                                              22
+#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x8000000
+#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT                                                          27
+#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK                                                    0x8000000
+#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT                                                           27
+#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x8000000
+#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT                                                          27
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                                 ((x) + 0x3f4)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                                 ((x) + 0x3f4)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                                    (0x3f4)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                      0x1fffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                                     0x00001000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                         0x1fe000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                               13
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                           0x1000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                               12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                         0xc00
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                            10
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                         0x3c0
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                             6
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                          0x30
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                             4
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                           0xf
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                             0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                             ((x) + 0x3f8)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                             ((x) + 0x3f8)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                                (0x3f8)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                                  0xffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                                 0x00000fff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                             0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                       0xfff000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                             12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                              0xfff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                  0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                                 ((x) + 0x3fc)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                                 ((x) + 0x3fc)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                                    (0x3fc)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                      0x1fffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                                     0x00001000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                                 0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                         0x1fe000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                               13
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                           0x1000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                               12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                         0xc00
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                            10
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                         0x3c0
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                             6
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                          0x30
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                             4
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                           0xf
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                             0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                             ((x) + 0x400)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                             ((x) + 0x400)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                                (0x400)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                                  0xffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                                 0x00000fff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                             0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                       0xfff000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                             12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                              0xfff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                  0
+
+#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK                                                          0x80000000
+#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT                                                                  31
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_BMSK                                                            0x8000
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_SHFT                                                                15
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_BMSK                                                        0x4000
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_SHFT                                                            14
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK                                                                0x2000
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT                                                                    13
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK                                                            0x1000
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT                                                                12
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK                                               0x800
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT                                                  11
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK                                               0x400
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT                                                  10
+#define HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x)                                                                          ((x) + 0x480)
+#define HWIO_TQM_R0_LPM_FW_CTRL_PHYS(x)                                                                          ((x) + 0x480)
+#define HWIO_TQM_R0_LPM_FW_CTRL_OFFS                                                                             (0x480)
+#define HWIO_TQM_R0_LPM_FW_CTRL_RMSK                                                                                    0xf
+#define HWIO_TQM_R0_LPM_FW_CTRL_POR                                                                              0x00000000
+#define HWIO_TQM_R0_LPM_FW_CTRL_POR_RMSK                                                                         0xffffffff
+#define HWIO_TQM_R0_LPM_FW_CTRL_ATTR                                                                                          0x3
+#define HWIO_TQM_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_TQM_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TQM_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                                     0x8
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                                       3
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                                     0x4
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                                       2
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK                                                              0x2
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT                                                                1
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                          0x1
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                            0
+
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x)                                                                       ((x) + 0x484)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_PHYS(x)                                                                       ((x) + 0x484)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_OFFS                                                                          (0x484)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_RMSK                                                                                 0x3
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR                                                                           0x00000000
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR_RMSK                                                                      0xffffffff
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_ATTR                                                                                       0x3
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x)            \
+                in_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x))
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x), m)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),v)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x))
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_BMSK                                             0x2
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_SHFT                                               1
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_BMSK                                                     0x1
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_SHFT                                                       0
+
+#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_BMSK                                                     0x20000000
+#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_SHFT                                                             29
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x)                                                  ((x) + 0x508)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x)                                                  ((x) + 0x508)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS                                                     (0x508)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK                                                     0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR                                                      0x00000000
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK                                                 0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR                                                                  0x3
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x)            \
+                in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK                                               0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT                                                        0
+
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x)                                           ((x) + 0x50c)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x)                                           ((x) + 0x50c)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS                                              (0x50c)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK                                              0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR                                               0x00000000
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR                                                           0x3
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x)            \
+                in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT                                                 0
+
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x)                                           ((x) + 0x510)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x)                                           ((x) + 0x510)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS                                              (0x510)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK                                              0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR                                               0x00000000
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR                                                           0x3
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x)            \
+                in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK                                        0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT                                                 0
+
+#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x)                                                                        ((x) + 0x51c)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x)                                                                        ((x) + 0x51c)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS                                                                           (0x51c)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK                                                                                0xfff
+#define HWIO_TQM_R0_WATCHDOG_SRNG_POR                                                                            0x00000710
+#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK                                                                       0xffffffff
+#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR                                                                                        0x3
+#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x)            \
+                in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x))
+#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v)            \
+                out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x))
+#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK                                                                          0xfff
+#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT                                                                              0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)                                                ((x) + 0x204c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x)                                                ((x) + 0x204c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS                                                   (0x204c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK                                                         0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR                                                    0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK                                               0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR                                                                0x1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x)            \
+                in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK                                              0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT                                                 0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)                                                 ((x) + 0x2050)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x)                                                 ((x) + 0x2050)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS                                                    (0x2050)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK                                                    0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR                                                     0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK                                                0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR                                                                 0x1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x)            \
+                in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK                                          0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT                                                   0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x)                                             ((x) + 0x2054)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x)                                             ((x) + 0x2054)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS                                                (0x2054)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK                                                      0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR                                                 0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK                                            0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR                                                             0x2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK                                           0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT                                              0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x)                                              ((x) + 0x2058)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x)                                              ((x) + 0x2058)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS                                                 (0x2058)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK                                                 0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR                                                  0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK                                             0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR                                                              0x2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK                                       0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT                                                0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)                                           ((x) + 0x205c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x)                                           ((x) + 0x205c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS                                              (0x205c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK                                              0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR                                               0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK                                          0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR                                                           0x3
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)            \
+                in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK                                    0xffff0000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT                                            16
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK                            0xfff0
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT                                 4
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK                                  0x8
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT                                    3
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK                                       0x4
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT                                         2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK                             0x2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT                               1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK                                         0x1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT                                           0
+
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x)                                                                    ((x) + 0x2060)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_PHYS(x)                                                                    ((x) + 0x2060)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_OFFS                                                                       (0x2060)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_RMSK                                                                          0x1ffff
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR                                                                        0x00000000
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR_RMSK                                                                   0xffffffff
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_ATTR                                                                                    0x3
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x)            \
+                in_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x))
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x), m)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),v)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x))
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_BMSK                                                              0x1ffff
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_SHFT                                                                    0
+
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x)                                                                   ((x) + 0x2064)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_PHYS(x)                                                                   ((x) + 0x2064)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OFFS                                                                      (0x2064)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_RMSK                                                                         0x1ffff
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR                                                                       0x00000000
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR_RMSK                                                                  0xffffffff
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ATTR                                                                                   0x3
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x)            \
+                in_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x))
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x), m)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),v)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x))
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_BMSK                                                             0x1ffff
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_SHFT                                                                   0
+
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x)                                                                    ((x) + 0x2068)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_PHYS(x)                                                                    ((x) + 0x2068)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_OFFS                                                                       (0x2068)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_RMSK                                                                          0x1ffff
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR                                                                        0x00000000
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR_RMSK                                                                   0xffffffff
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_ATTR                                                                                    0x3
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x)            \
+                in_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x))
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x), m)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUT(x, v)            \
+                out_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),v)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x))
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_BMSK                                                              0x1ffff
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_SHFT                                                                    0
+
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x)                                                              ((x) + 0x206c)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_PHYS(x)                                                              ((x) + 0x206c)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_OFFS                                                                 (0x206c)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_RMSK                                                                        0xf
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR                                                                  0x00000000
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR_RMSK                                                             0xffffffff
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ATTR                                                                              0x1
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x))
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x), m)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_BMSK                                                0x8
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_SHFT                                                  3
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_BMSK                                                 0x4
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_SHFT                                                   2
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_BMSK                                                 0x2
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_SHFT                                                   1
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_BMSK                                              0x1
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_SHFT                                                0
+
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x)                                                                  ((x) + 0x2070)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_PHYS(x)                                                                  ((x) + 0x2070)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_OFFS                                                                     (0x2070)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_RMSK                                                                     0xffffffff
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR                                                                      0x00000000
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR_RMSK                                                                 0xffffffff
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ATTR                                                                                  0x1
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_IN(x)            \
+                in_dword(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x))
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x), m)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_BMSK                                                               0xffffffff
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_SHFT                                                                        0
+
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x)                                                               ((x) + 0x2074)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_PHYS(x)                                                               ((x) + 0x2074)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_OFFS                                                                  (0x2074)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_RMSK                                                                  0xffffffff
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR                                                                   0x00000000
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ATTR                                                                               0x1
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_IN(x)            \
+                in_dword(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x))
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x), m)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_BMSK                                                            0xffffffff
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_SHFT                                                                     0
+
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                               ((x) + 0x2078)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                               ((x) + 0x2078)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                                  (0x2078)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                                        0xff
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR                                                                   0x00000000
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                              0xffffffff
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                               0x1
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                             0x80
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                                7
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                             0x40
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                                6
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK                                                      0x20
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT                                                         5
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                                   0x10
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                                      4
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                                      0x8
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                                        3
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                                0x7
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                                  0
+
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                               ((base) + 0X2114 + (0x4*(n)))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                               ((base) + 0X2114 + (0x4*(n)))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                                    (0X2114 + (0x4*(n)))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK                                                                       0xffffffff
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_MAXn                                                                              127
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR                                                                        0x00000000
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                                   0xffffffff
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ATTR                                                                                    0x1
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK)
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                                  0xffffffff
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                           0
+
+#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_BMSK                                                        0x80
+#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_SHFT                                                           7
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x800000
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                                23
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x400000
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                                22
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                        0x8000000
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               27
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                        0x4000000
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               26
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x80000
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               19
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x40000
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               18
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK                                                       0x100
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT                                                           8
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK                                                        0x80
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT                                                           7
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK                                                        0x40
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT                                                           6
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK                                                        0x20
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT                                                           5
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x20000
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               17
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x10000
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               16
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x800000
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                                23
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x400000
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                                22
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                        0x8000000
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               27
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                        0x4000000
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               26
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x80000
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               19
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x40000
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               18
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK                                                       0x100
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT                                                           8
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK                                                        0x80
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT                                                           7
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK                                                        0x40
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT                                                           6
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK                                                        0x20
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT                                                           5
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK                                          0x20000
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT                                               17
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK                                          0x10000
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT                                               16
+#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK                                             0x40
+#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT                                                6
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x)                                             ((x) + 0x168)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x)                                             ((x) + 0x168)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS                                                (0x168)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK                                                       0xf
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR                                                 0x0000000a
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK                                            0xffffffff
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR                                                             0x3
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x))
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x))
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK                                                 0xf
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT                                                   0
+
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x)                                                                ((x) + 0x16c)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_PHYS(x)                                                                ((x) + 0x16c)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_OFFS                                                                   (0x16c)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_RMSK                                                                         0x1f
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR                                                                    0x00000000
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR_RMSK                                                               0xffffffff
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_ATTR                                                                                0x3
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_BMSK                                                   0x10
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_SHFT                                                      4
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_BMSK                                                    0x8
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_SHFT                                                      3
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_BMSK                                                    0x4
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_SHFT                                                      2
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_BMSK                                                    0x2
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_SHFT                                                      1
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                0x1
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                  0
+
+#define HWIO_UMCMN_R0_LINK_ID_ADDR(x)                                                                    ((x) + 0x170)
+#define HWIO_UMCMN_R0_LINK_ID_PHYS(x)                                                                    ((x) + 0x170)
+#define HWIO_UMCMN_R0_LINK_ID_OFFS                                                                       (0x170)
+#define HWIO_UMCMN_R0_LINK_ID_RMSK                                                                           0xffff
+#define HWIO_UMCMN_R0_LINK_ID_POR                                                                        0x000052c8
+#define HWIO_UMCMN_R0_LINK_ID_POR_RMSK                                                                   0xffffffff
+#define HWIO_UMCMN_R0_LINK_ID_ATTR                                                                                    0x3
+#define HWIO_UMCMN_R0_LINK_ID_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x))
+#define HWIO_UMCMN_R0_LINK_ID_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_LINK_ID_ADDR(x), m)
+#define HWIO_UMCMN_R0_LINK_ID_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x),v)
+#define HWIO_UMCMN_R0_LINK_ID_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_LINK_ID_IN(x))
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_BMSK                                                               0x80
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_SHFT                                                                  7
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_BMSK                                                               0x40
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_SHFT                                                                  6
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_BMSK                                                               0x38
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_SHFT                                                                  3
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_BMSK                                                                0x7
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_SHFT                                                                  0
+
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK                                                    0x4000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT                                                        14
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK                                                0x2000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT                                                    13
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK                                                    0x1000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT                                                        12
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK                                                     0x800
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT                                                        11
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK                                                     0x400
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT                                                        10
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK                                                     0x200
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT                                                         9
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK                                                     0x100
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT                                                         8
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK                                                       0x80
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT                                                          7
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK                                                       0x40
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT                                                          6
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK                                                       0x20
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT                                                          5
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK                                                       0x10
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT                                                          4
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK                                                         0x8
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT                                                           3
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK                                                        0x4
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT                                                          2
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK                                                         0x2
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT                                                           1
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK                                                        0x1
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT                                                          0
+
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x)                                                          ((x) + 0x184)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_PHYS(x)                                                          ((x) + 0x184)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OFFS                                                             (0x184)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_RMSK                                                                    0x1
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR                                                              0x00000000
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR_RMSK                                                         0xffffffff
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ATTR                                                                          0x3
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x))
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x), m)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),v)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x))
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_BMSK                                                                0x1
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_SHFT                                                                  0
+
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x)                                             ((x) + 0x188)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_PHYS(x)                                             ((x) + 0x188)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OFFS                                                (0x188)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_RMSK                                                   0x1ffff
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR                                                 0x00000000
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR_RMSK                                            0xffffffff
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ATTR                                                             0x3
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x)            \
+                in_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x))
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x), m)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUT(x, v)            \
+                out_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),v)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),m,v,HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x))
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_BMSK                   0x1fe00
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_SHFT                         9
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_BMSK                    0x1fe
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_SHFT                        1
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_BMSK                         0x1
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_SHFT                           0
+
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                     ((x) + 0x2010)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                     ((x) + 0x2010)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                        (0x2010)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                             0x1ff
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR                                                         0x00000000
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                    0xffffffff
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                     0x1
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_BMSK                                           0x100
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_SHFT                                               8
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_BMSK                                            0x80
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_SHFT                                               7
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_BMSK                                            0x40
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_SHFT                                               6
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_BMSK                                            0x20
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_SHFT                                               5
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                         0x10
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                            4
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                            0x8
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                              3
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                      0x7
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                        0
+
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n)                                            ((base) + 0X2014 + (0x4*(n)))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_PHYS(base,n)                                            ((base) + 0X2014 + (0x4*(n)))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OFFS(n)                                                 (0X2014 + (0x4*(n)))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK                                                    0xffffffff
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_MAXn                                                             7
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR                                                     0x00000000
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR_RMSK                                                0xffffffff
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ATTR                                                                 0x3
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n)                \
+                in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK)
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), mask)
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTI(base,n,val)        \
+                out_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),val)
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTMI(base,n,mask,val) \
+                out_dword_masked_ns(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),mask,val,HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_BMSK                                                0xffffffff
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_SHFT                                                         0
+
+#define MAC_TCL_REG_REG_BASE                                                                                (UMAC_BASE      + 0x00044000)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x)                                                          ((x) + 0x20)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK                                       0x800000
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT                                             23
+#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK                                          0x8000000
+#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT                                                 27
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n)                                                           ((base) + 0X8C + (0x4*(n)))
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT                                                        17
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT                                                                   15
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT                                                          14
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT                                                               12
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT                                                                  11
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT                                                                  10
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT                                                        9
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT                                                             8
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT                                                            7
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT                                                               3
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT                                                                 1
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT                                                                        0
+
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n)                                                             ((base) + 0X240 + (0x4*(n)))
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK                                                                     0xffffffff
+#define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x)                                                                     ((x) + 0x6c0)
+#define HWIO_TCL_R0_PCP_TID_MAP_RMSK                                                                          0xffffff
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT                                                                          21
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT                                                                          18
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT                                                                          15
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT                                                                          12
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT                                                                           9
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT                                                                           6
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT                                                                           3
+#define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x)                                                                    ((x) + 0x6e8)
+#define HWIO_TCL_R0_TID_MAP_PRTY_RMSK                                                                             0xef
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK                                                   0x800000
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT                                                         23
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_BMSK                                                             0x10
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_SHFT                                                                4
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK                                                          0x8
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT                                                            3
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x)                                                                ((x) + 0x8b4)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_PHYS(x)                                                                ((x) + 0x8b4)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_OFFS                                                                   (0x8b4)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_RMSK                                                                          0x3
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR                                                                    0x00000000
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR_RMSK                                                               0xffffffff
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_ATTR                                                                                0x3
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x)            \
+                in_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x))
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x), m)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),v)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x))
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_BMSK                                                             0x2
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_SHFT                                                               1
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_BMSK                                                             0x1
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_SHFT                                                               0
+
+#define HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x)                                                                     ((x) + 0x914)
+#define HWIO_TCL_R0_LPM_FW_CTRL_PHYS(x)                                                                     ((x) + 0x914)
+#define HWIO_TCL_R0_LPM_FW_CTRL_OFFS                                                                        (0x914)
+#define HWIO_TCL_R0_LPM_FW_CTRL_RMSK                                                                               0x7
+#define HWIO_TCL_R0_LPM_FW_CTRL_POR                                                                         0x00000000
+#define HWIO_TCL_R0_LPM_FW_CTRL_POR_RMSK                                                                    0xffffffff
+#define HWIO_TCL_R0_LPM_FW_CTRL_ATTR                                                                                     0x3
+#define HWIO_TCL_R0_LPM_FW_CTRL_IN(x)            \
+                in_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_TCL_R0_LPM_FW_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_TCL_R0_LPM_FW_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_TCL_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TCL_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK                                                0x4
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT                                                  2
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK                                                0x2
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT                                                  1
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK                                                                     0x1
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT                                                                       0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x)                                                           ((x) + 0x918)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x)                                                           ((x) + 0x91c)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK                                                     0xfffff00
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT                                                             8
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK                                                 0xff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT                                                    0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x)                                                                 ((x) + 0x920)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK                                                               0xff
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT                                                                  0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x)                                                               ((x) + 0x928)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK                                                      0x20
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                                                         5
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK                                                       0x10
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT                                                          4
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK                                                            0x8
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT                                                              3
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK                                                         0x2
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT                                                           1
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK                                                         0x1
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT                                                           0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x)                                                        ((x) + 0x934)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x)                                                        ((x) + 0x938)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)                                             ((x) + 0x948)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK                      0xffff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT                              16
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK                            0x7fff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT                                 0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)                                             ((x) + 0x94c)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK                                      0xffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT                                           0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x)                                                      ((x) + 0x960)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x)                                                      ((x) + 0x964)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK                                                  0x100
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT                                                      8
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK                                                          0xff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT                                                             0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x)                                                          ((x) + 0x968)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x)                                                           ((x) + 0x990)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x)                                                     ((x) + 0xb70)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK                                               0xfffff00
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT                                                       8
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_TRANSACTION_TYPE_BMSK                                             0x400000
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_TRANSACTION_TYPE_SHFT                                                   22
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x400000
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT                                                         22
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK                                                  0x8000000
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT                                                         27
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x)                                                       ((x) + 0xd50)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK                                                  0xffff00
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT                                                         8
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK                                              0x8000000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT                                                     27
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_BMSK                                                   0x8000000
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_SHFT                                                          27
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)                                                ((x) + 0xedc)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x)                                                ((x) + 0xedc)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS                                                   (0xedc)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK                                                     0x1fffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR                                                    0x00001000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK                                               0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR                                                                0x3
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK                                        0x1fe000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT                                              13
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                          0x1000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                              12
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                        0xc00
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                           10
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                        0x3c0
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                            6
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                         0x30
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                            4
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                          0xf
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                            0
+
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)                                            ((x) + 0xee0)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x)                                            ((x) + 0xee0)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS                                               (0xee0)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK                                                 0xffffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR                                                0x00000fff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK                                           0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR                                                            0x3
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                      0xfff000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                            12
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                             0xfff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                 0
+
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)                                                ((x) + 0xee4)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x)                                                ((x) + 0xee4)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS                                                   (0xee4)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK                                                     0x1fffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR                                                    0x00001000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK                                               0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR                                                                0x3
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK                                        0x1fe000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT                                              13
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK                                          0x1000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT                                              12
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK                                        0xc00
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT                                           10
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK                                        0x3c0
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT                                            6
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK                                         0x30
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT                                            4
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK                                          0xf
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT                                            0
+
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)                                            ((x) + 0xee8)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x)                                            ((x) + 0xee8)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS                                               (0xee8)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK                                                 0xffffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR                                                0x00000fff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK                                           0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR                                                            0x3
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)            \
+                in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v)            \
+                out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK                      0xfff000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT                            12
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK                             0xfff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT                                 0
+
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)                                                          ((x) + 0x1000)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_PHYS(x)                                                          ((x) + 0x1000)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_OFFS                                                             (0x1000)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_RMSK                                                                   0x7f
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR                                                              0x00000000
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK                                                         0xffffffff
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ATTR                                                                          0x1
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_IN(x)            \
+                in_dword(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK                                        0x40
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT                                           6
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK                                        0x20
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT                                           5
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK                                              0x10
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT                                                 4
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK                                                 0x8
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT                                                   3
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK                                                           0x7
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT                                                             0
+
+#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK                                                       0x20000
+#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT                                                            17
+#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK                                                  0x20000
+#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT                                                       17
+#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x)                                                                    ((x) + 0x1030)
+#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x)                                                                    ((x) + 0x1030)
+#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS                                                                       (0x1030)
+#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK                                                                            0x1ff
+#define HWIO_TCL_R1_TESTBUS_CTRL_POR                                                                        0x00000000
+#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK                                                                   0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR                                                                                    0x3
+#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x)            \
+                in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x))
+#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m)            \
+                in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m)
+#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v)            \
+                out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v)
+#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \
+                out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x))
+#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK                                       0x100
+#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT                                           8
+#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK                                                                0xc0
+#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT                                                                   6
+#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK                                                             0x3f
+#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT                                                                0
+
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n)                                                          ((base) + 0X1034 + (0x4*(n)))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n)                                                          ((base) + 0X1034 + (0x4*(n)))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n)                                                               (0X1034 + (0x4*(n)))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK                                                                  0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn                                                                         511
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR                                                                   0x00000000
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK                                                              0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR                                                                               0x1
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n)                \
+                in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK)
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask)        \
+                in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK                                                             0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT                                                                      0
+
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x)                                                                 ((x) + 0x2000)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x)                                                                 ((x) + 0x2004)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x)                                                                 ((x) + 0x2008)
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x)                                                           ((x) + 0x2028)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x)                                                             ((x) + 0x2048)
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_NOPX_BMSK                                   0x80000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_NOPX_SHFT                                        19
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWSLVERR_BMSK                               0x40000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWSLVERR_SHFT                                    18
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWDECERR_BMSK                               0x20000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWDECERR_SHFT                                    17
+#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                0x1000000
+#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                       24
+#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                  0x1000000
+#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                         24
+#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                  0x1000000
+#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                         24
+#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                 0x1000000
+#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                        24
+#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK                                                 0x1000000
+#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT                                                        24
+#endif
diff --git a/hw/peach/v1/wcss_version.h b/hw/peach/v1/wcss_version.h
new file mode 100644
index 000000000000..a07cff096e51
--- /dev/null
+++ b/hw/peach/v1/wcss_version.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#define WCSS_VERSION 2544
-- 
GitLab


From dc56b9d07a7af14e824bfa0775be89b9d003e93d Mon Sep 17 00:00:00 2001
From: Prakash Manjunathappa <quic_prakashp@quicinc.com>
Date: Wed, 12 Jul 2023 16:47:18 -0700
Subject: [PATCH 061/298] fw-api: Fix E3.0: E3R44: WCSS_VERSION 2544

Incremental hw header file update to fix compilation errors.

Change-Id: I9c101255444ca892e1a6006a55f11c0de0fbffb4
CRs-Fixed: 3580269
---
 hw/peach/v1/phyrx_rssi_legacy.h         | 98 ++++++++++++-------------
 hw/peach/v1/rx_msdu_desc_info.h         |  4 +-
 hw/peach/v1/rx_msdu_details.h           |  5 ++
 hw/peach/v1/uniform_descriptor_header.h |  7 +-
 hw/peach/v1/wcss_seq_hwioreg_umac.h     |  5 ++
 5 files changed, 66 insertions(+), 53 deletions(-)

diff --git a/hw/peach/v1/phyrx_rssi_legacy.h b/hw/peach/v1/phyrx_rssi_legacy.h
index 9b8faea41c83..61f865a012ce 100644
--- a/hw/peach/v1/phyrx_rssi_legacy.h
+++ b/hw/peach/v1/phyrx_rssi_legacy.h
@@ -58,55 +58,55 @@ struct phyrx_rssi_legacy {
 #endif
 };
 
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET                0x00000000
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB                   0
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB                   3
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK                  0x0000000f
-
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET            0x00000000
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB               4
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB               4
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK              0x00000010
-
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET             0x00000000
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB                5
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB                7
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK               0x000000e0
-
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET                 0x00000000
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB                    8
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB                    15
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK                   0x0000ff00
-
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET                   0x00000000
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB                      16
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB                      31
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK                     0xffff0000
-
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET     0x00000004
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB        0
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB        31
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK       0xffffffff
-
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET    0x00000008
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB       0
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB       31
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK      0xffffffff
-
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET      0x0000000c
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB         0
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB         7
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK        0x000000ff
-
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET       0x0000000c
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB          8
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB          8
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK         0x00000100
-
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET                   0x0000000c
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB                      9
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB                      31
-#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK                     0xfffffe00
+#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_OFFSET                0x00000000
+#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_LSB                   0
+#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MSB                   3
+#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MASK                  0x0000000f
+
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_OFFSET            0x00000000
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_LSB               4
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MSB               4
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MASK              0x00000010
+
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET             0x00000000
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB                5
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB                7
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK               0x000000e0
+
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_OFFSET                 0x00000000
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_LSB                    8
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MSB                    15
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MASK                   0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_OFFSET                   0x00000000
+#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_LSB                      16
+#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MSB                      31
+#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MASK                     0xffff0000
+
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_OFFSET     0x00000004
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_LSB        0
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MSB        31
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MASK       0xffffffff
+
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_OFFSET    0x00000008
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_LSB       0
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MSB       31
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MASK      0xffffffff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_OFFSET      0x0000000c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_LSB         0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MSB         7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MASK        0x000000ff
+
+#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_OFFSET       0x0000000c
+#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_LSB          8
+#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_MSB          8
+#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_MASK         0x00000100
+
+#define PHYRX_RSSI_LEGACY_RESERVED_3A_OFFSET                   0x0000000c
+#define PHYRX_RSSI_LEGACY_RESERVED_3A_LSB                      9
+#define PHYRX_RSSI_LEGACY_RESERVED_3A_MSB                      31
+#define PHYRX_RSSI_LEGACY_RESERVED_3A_MASK                     0xfffffe00
 
 #define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET                                   0x00000010
 #define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB                                      0
diff --git a/hw/peach/v1/rx_msdu_desc_info.h b/hw/peach/v1/rx_msdu_desc_info.h
index bca7ebfd9798..90a3df7973a2 100644
--- a/hw/peach/v1/rx_msdu_desc_info.h
+++ b/hw/peach/v1/rx_msdu_desc_info.h
@@ -38,9 +38,9 @@ struct rx_msdu_desc_info {
                       intra_bss                                               :  1,
                       dest_chip_id                                            :  2,
                       decap_format                                            :  2,
-                      __reserved_g_0015                                       :  1;
+                      reserved_0a                                             :  1;
 #else
-             uint32_t __reserved_g_0015                                       :  1,
+             uint32_t reserved_0a                                             :  1,
                       decap_format                                            :  2,
                       dest_chip_id                                            :  2,
                       intra_bss                                               :  1,
diff --git a/hw/peach/v1/rx_msdu_details.h b/hw/peach/v1/rx_msdu_details.h
index 4c284eb61837..39313f38b3ae 100644
--- a/hw/peach/v1/rx_msdu_details.h
+++ b/hw/peach/v1/rx_msdu_details.h
@@ -135,6 +135,11 @@ struct rx_msdu_details {
 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB                  30
 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK                 0x60000000
 
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET             0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB                31
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB                31
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK               0x80000000
+
 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c
 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
diff --git a/hw/peach/v1/uniform_descriptor_header.h b/hw/peach/v1/uniform_descriptor_header.h
index a00f6b9cd099..efe58926b91f 100644
--- a/hw/peach/v1/uniform_descriptor_header.h
+++ b/hw/peach/v1/uniform_descriptor_header.h
@@ -14,7 +14,6 @@
  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-
 #ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
 #define _UNIFORM_DESCRIPTOR_HEADER_H_
 
@@ -49,8 +48,12 @@ struct uniform_descriptor_header {
 #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB                          27
 #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK                         0x0fffff00
 
+/* RESERVED is overlapping with TX_MPDU_QUEUE_NUMBER
+ * TX_MPDU_QUEUE_NUMBER valid on in Buffer_type is any of Transmit_MPDU_*_descriptor
+ * Where as RESERVED is only used for debugging in REO_QUEUE_Descr reo_queue_desc
+ */
 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET                                0x00000000
-#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB                                   28
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB                                   8
 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB                                   31
 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK                                  0xf0000000
 
diff --git a/hw/peach/v1/wcss_seq_hwioreg_umac.h b/hw/peach/v1/wcss_seq_hwioreg_umac.h
index 422bba82cf92..70f00a564205 100644
--- a/hw/peach/v1/wcss_seq_hwioreg_umac.h
+++ b/hw/peach/v1/wcss_seq_hwioreg_umac.h
@@ -803,6 +803,11 @@
 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x)                                                                 ((x) + 0x548)
 #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x)                                                                 ((x) + 0x54c)
 #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x)                                                                     ((x) + 0x550)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x)                                                                        ((x) + 0x574)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK                                                  0xffff0000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT                                                          16
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK                                                         0x3f
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT                                                            0
 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x)                                                           ((x) + 0x554)
 #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x)                                                                 ((x) + 0x558)
 #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x)                                                                 ((x) + 0x55c)
-- 
GitLab


From 3f751a222fc6e7905cac5b71338d2600055fcca6 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 15 Sep 2023 06:01:32 -0700
Subject: [PATCH 062/298] fw-api: CL 24602439 - update fw common interface
 files

WMI: add erp_standby_mode field in mlo_teardown_fixed_param
Change-Id: I4b76f0c9f71746bcaccc6f104e3d66ad7465e6a2
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 2 ++
 fw/wmi_version.h | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index ff2931a0b49d..20c1b9da01f2 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -44639,6 +44639,8 @@ typedef struct {
     A_UINT32 reason_code;
     /* trigger_umac_reset : of type A_BOOL to indicate the umac reset for the partner chip. */
     A_UINT32 trigger_umac_reset;
+    /* erp_standby_mode : of type A_BOOL to indicate the chip is going to be active in ERP */
+    A_UINT32 erp_standby_mode;
 } wmi_mlo_teardown_fixed_param;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 8918fa58c909..133e1e10ccfc 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1388
+#define __WMI_REVISION_ 1389
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From cbeef8e06022cfee184c1436b2d5623bee913789 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Sat, 16 Sep 2023 18:01:17 -0700
Subject: [PATCH 063/298] fw-api: CL 24620909 - update fw common interface
 files

WMI: add more TLVs to MLO_LINK_SWITCH_CONF_CMD msg
Change-Id: I61de2537b5aff6cf597344ebe6a3faf055fd274e
CRs-Fixed: 2262693
---
 fw/wmi_tlv_defs.h |  6 +++++-
 fw/wmi_unified.h  | 36 ++++++++++++++++++++++++++++++++++++
 fw/wmi_version.h  |  2 +-
 3 files changed, 42 insertions(+), 2 deletions(-)

diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index cfe418c9a509..21ca4d8b1cb1 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -5464,7 +5464,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_BSS_PARAMS_CMDID);
 
 /* MLO link switch confirmation command to inform FW about host side status and reason code */
 #define WMITLV_TABLE_WMI_MLO_LINK_SWITCH_CONF_CMDID(id,op,buf,len) \
-    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_cnf_fixed_param, wmi_mlo_link_switch_cnf_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_cnf_fixed_param, wmi_mlo_link_switch_cnf_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_set_active_cmd_fixed_param, set_link_params, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_set_active_link_number_param, link_number_param,  WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ieee_link_id_bitmap, WMITLV_SIZE_VAR) \
+    WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ieee_link_id_bitmap2, WMITLV_SIZE_VAR)
 WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SWITCH_CONF_CMDID);
 
 /* WMI CMD used to send WSI stats info. */
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 20c1b9da01f2..c5d160eb8a70 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -44448,6 +44448,7 @@ typedef enum {
     WMI_MLO_LINK_FORCE_REASON_NEW_DISCONNECT   = 2, /* Set force specific links because of new dis-connection */
     WMI_MLO_LINK_FORCE_REASON_LINK_REMOVAL     = 3, /* Set force specific links because of AP-side link removal */
     WMI_MLO_LINK_FORCE_REASON_TDLS             = 4, /* Set force specific links because of 11BE MLO TDLS setup/teardown */
+    WMI_MLO_LINK_FORCE_REASON_REVERT_FAILURE   = 5, /* Set force specific links for revert previous failed due to host reject */
 } WMI_MLO_LINK_FORCE_REASON;
 
 #define WMI_MLO_CONTROL_FLAGS_GET_OVERWRITE_FORCE_ACTIVE(mlo_flags) \
@@ -44554,6 +44555,11 @@ typedef struct wmi_mlo_set_active_link_number_param
 
 } wmi_mlo_set_active_link_number_param;
 
+typedef enum {
+    WMI_MLO_LINK_SET_ACTIVE_STATUS_SUCCESS     = 0,
+    WMI_MLO_LINK_SET_ACTIVE_STATUS_HOST_REJECT = 1,
+} WMI_MLO_LINK_SET_ACTIVE_STATUS;
+
 typedef struct wmi_mlo_link_set_active_resp_event
 {
     /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_set_active_resp_event_fixed_param; */
@@ -46519,6 +46525,7 @@ typedef enum _WMI_LINK_SWITCH_CNF_REASON{
     WMI_MLO_LINK_SWITCH_CNF_REASON_BSS_PARAMS_CHANGED = 1,
     WMI_MLO_LINK_SWITCH_CNF_REASON_CONCURRECNY_CONFLICT = 2,
     WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_INTERNAL_ERROR = 3,
+    WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_RESTORE_FORCE = 4,
     WMI_MLO_LINK_SWITCH_CNF_REASON_MAX,
 } WMI_LINK_SWITCH_CNF_REASON;
 
@@ -46533,6 +46540,35 @@ typedef struct {
     A_UINT32 vdev_id;
     A_UINT32 status;  /* see definition of WMI_LINK_SWITCH_CNF_STATUS */
     A_UINT32 reason;  /* see definition of WMI_LINK_SWITCH_CNF_REASON */
+
+/*
+ * The following optional TLVs may follow this fixed_praam TLV,
+ * depending on the value of the reason field.
+ *
+ * wmi_mlo_link_set_active_cmd_fixed_param set_link_params[];
+ *     The set_link_params array has one element when reason is
+ *     WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_RESTORE_FORCE and
+ *     use_ieee_link_id_bitmap should always be filled with 1.
+ *     In other cases the length of the set_link_params array shall be 0.
+ *
+ * wmi_mlo_set_active_link_number_param link_number_param[];
+ *     Link number parameters, optional TLV.
+ *     Present when force type is WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or
+ *     WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM.
+ *     In other cases the length of array shall be 0.
+ *
+ * A_UINT32 ieee_link_id_bitmap[];
+ *     present for  WMI_MLO_LINK_FORCE_ACTIVE
+ *     or WMI_MLO_LINK_FORCE_INACTIVE or WMI_MLO_LINK_NO_FORCE
+ *     or WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or
+ *     WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM
+ *     In other cases the length of array shall be 0.
+ *
+ * A_UINT32 ieee_link_id_bitmap2[];
+ *     For force mode WMI_MLO_LINK_FORCE_ACTIVE_INACTIVE ieee_link_id_bitmap2[]
+ *     carries the inactive linkid bitmap.
+ *     In other cases the length of the array shall be 0.
+ */
 } wmi_mlo_link_switch_cnf_fixed_param;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 133e1e10ccfc..5dc51601afb4 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1389
+#define __WMI_REVISION_ 1390
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From 150f19d7c14006ff70869d996289aee752c7fe28 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 15 Sep 2023 18:02:01 -0700
Subject: [PATCH 064/298] fw-api: CL 24610273 - update fw common interface
 files

HTT stats: add array_gain_cap + other fields to phy_tpc_stats TLV
Change-Id: Ibfb79c9dffe0a02e30263e1e7fecae56b0168e93
CRs-Fixed: 2262693
---
 fw/htt_stats.h | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index fc232a4e903c..66e74b5250f0 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -7953,6 +7953,58 @@ typedef struct {
 /* Considering 320 MHz maximum 16 power levels */
 #define HTT_MAX_CH_PWR_INFO_SIZE    16
 
+#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_M    0x000000ff
+#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_S    0
+
+#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_GET(_var) \
+    (((_var) & HTT_PHY_TPC_STATS_CTL_REGION_GRP_M) >> \
+     HTT_PHY_TPC_STATS_CTL_REGION_GRP_S)
+#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_SET(_var, _val) \
+  do { \
+        HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_REGION_GRP, _val); \
+        ((_var) &= ~(HTT_PHY_TPC_STATS_CTL_REGION_GRP_M)); \
+        ((_var) |= ((_val) << HTT_PHY_TPC_STATS_CTL_REGION_GRP_S)); \
+     } while (0)
+
+#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M    0x0000ff00
+#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S    8
+
+#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_GET(_var) \
+    (((_var) & HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M) >> \
+     HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S)
+#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_SET(_var, _val) \
+  do { \
+        HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_SUB_BAND_INDEX, _val); \
+        ((_var) &= ~(HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M)); \
+        ((_var) |= ((_val) << HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S)); \
+     } while (0)
+
+#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M    0x00ff0000
+#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S    16
+
+#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_GET(_var) \
+    (((_var) & HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M) >> \
+     HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S)
+#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_SET(_var, _val) \
+ do { \
+        HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED, _val); \
+        ((_var) &= ~(HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M)); \
+        ((_var) |= ((_val) << HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S)); \
+    } while (0)
+
+#define HTT_PHY_TPC_STATS_CTL_FLAG_M    0xff000000
+#define HTT_PHY_TPC_STATS_CTL_FLAG_S    24
+
+#define HTT_PHY_TPC_STATS_CTL_FLAG_GET(_var) \
+    (((_var) & HTT_PHY_TPC_STATS_CTL_FLAG_M) >> \
+     HTT_PHY_TPC_STATS_CTL_FLAG_S)
+#define HTT_PHY_TPC_STATS_CTL_FLAG_SET(_var, _val) \
+ do { \
+        HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_FLAG, _val); \
+        ((_var) &= ~(HTT_PHY_TPC_STATS_CTL_FLAG_M)); \
+        ((_var) |= ((_val) << HTT_PHY_TPC_STATS_CTL_FLAG_S)); \
+    } while (0)
+
 typedef struct {
     htt_tlv_hdr_t tlv_hdr;
 
@@ -7991,6 +8043,33 @@ typedef struct {
     /** sub-band channels and corresponding Tx-power */
     A_UINT32 sub_band_cfreq[HTT_MAX_CH_PWR_INFO_SIZE];
     A_UINT32 sub_band_txpower[HTT_MAX_CH_PWR_INFO_SIZE];
+
+    /** array_gain_cap:
+     * CTL Array Gain cap, units are dB
+     * The lower-triangular portion of this square matrix is stored, i.e.
+     *     array element 0 stores matrix element (0,0)
+     *     array element 1 stores matrix element (1,0)
+     *     array element 2 stores matrix element (1,1)
+     *     array element 3 stores matrix element (2,0)
+     *     ...
+     *     array element 35 stores matrix element (7,7)
+     */
+    A_INT32 array_gain_cap[HTT_STATS_MAX_CHAINS * ((HTT_STATS_MAX_CHAINS/2)+1)];
+    union {
+        struct {
+            A_UINT32
+                ctl_region_grp:8, /** Group to which the ctl region belongs */
+                sub_band_index:8, /** Frequency subband index */
+                /** Array Gain Cap Ext2 feature enablement status */
+                array_gain_cap_ext2_enabled:8,
+                /** ctl_flag:
+                 * 1st bit ULOFDMA supported
+                 * 2nd bit DLOFDMA shared Exception supported
+                 */
+                ctl_flag:8;
+        };
+        A_UINT32 ctl_args;
+    };
 } htt_phy_tpc_stats_tlv;
 
 /* NOTE:
-- 
GitLab


From 599ef65ed20bf078a0c8b2f8b7a7de6732d7cdf7 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Mon, 18 Sep 2023 18:01:30 -0700
Subject: [PATCH 065/298] fw-api: CL 24632749 - update fw common interface
 files

HTT stats: add [basic,mu_bar]_trigger counters to tx_selfgen_[ax,be]_stats
Change-Id: Id50afbbab1c40e05ccb9bdacd63ac3c77d5df64d
CRs-Fixed: 2262693
---
 fw/htt_stats.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 66e74b5250f0..c779f6fd16e8 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -2638,6 +2638,14 @@ typedef struct {
     A_UINT32 manual_ax_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM];
     /** 11AX HE Manual Multi-User UL OFDMA Trigger completed with error(s) */
     A_UINT32 manual_ax_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM];
+    /** 11AX HE UL OFDMA Basic Trigger frames per AC */
+    A_UINT32 ax_basic_trigger_per_ac[HTT_NUM_AC_WMM];
+    /** 11AX HE UL OFDMA Basic Trigger frames per AC completed with error(s) */
+    A_UINT32 ax_basic_trigger_errors_per_ac[HTT_NUM_AC_WMM];
+    /** 11AX HE MU-BAR Trigger frames per AC */
+    A_UINT32 ax_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM];
+    /** 11AX HE MU-BAR Trigger frames per AC completed with error(s) */
+    A_UINT32 ax_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM];
 } htt_tx_selfgen_ax_stats_tlv;
 
 typedef struct {
@@ -2693,6 +2701,14 @@ typedef struct {
     A_UINT32 manual_be_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM];
     /** 11BE EHT Manual Multi-User UL OFDMA Trigger completed with error(s) */
     A_UINT32 manual_be_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM];
+    /** 11BE EHT UL OFDMA Basic Trigger frames per AC */
+    A_UINT32 be_basic_trigger_per_ac[HTT_NUM_AC_WMM];
+    /** 11BE EHT UL OFDMA Basic Trigger frames per AC completed with error(s) */
+    A_UINT32 be_basic_trigger_errors_per_ac[HTT_NUM_AC_WMM];
+    /** 11BE EHT MU-BAR Trigger frames per AC */
+    A_UINT32 be_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM];
+    /** 11BE EHT MU-BAR Trigger frames per AC completed with error(s) */
+    A_UINT32 be_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM];
 } htt_tx_selfgen_be_stats_tlv;
 
 typedef struct { /* DEPRECATED */
-- 
GitLab


From 1cb390ca6cab4c6e66e693c0f8126a5975cf78e8 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Mon, 18 Sep 2023 18:02:28 -0700
Subject: [PATCH 066/298] fw-api: CL 24632751 - update fw common interface
 files

Add WMI_ROAM_PARAM_ROAM_UNSUPPORTED_6GHZ_POWERTYPE def

Change-Id: I8cf21a066b61d30edbc6d91702f5ca65d5e078e4
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 16 ++++++++++++++++
 fw/wmi_version.h |  2 +-
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index c5d160eb8a70..06187a29ca7f 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -40351,6 +40351,22 @@ typedef enum {
      */
     WMI_ROAM_PARAM_ROAM_RSSI_BOOST_FOR_6GHZ_CAND_AP = 8,
 
+    /*
+     * Roam param to indicate unsupported Power Type for 6 GHz Candidate AP
+     * found during Roam Scan. If AP operates on the power type disabled by
+     * the host, then that candidate should not be selected.
+     * This unsupported Power Type will be configured based
+     * on disabled 6GHz Power Types in Regdomain
+     *
+     * If below bits in the obtianed Bitmap is set then any AP
+     * broadcasting these Power Types should not be selected
+     * BIT 0   - Indoor Access Point
+     * BIT 1   - Standard Power (SP) Access Point
+     * BIT 2   - Very Low Power (VLP) Access Point
+     * BIT 3-7 - Reserved
+     */
+    WMI_ROAM_PARAM_ROAM_UNSUPPORTED_6GHZ_POWERTYPE = 9,
+
     /*=== END ROAM_PARAM_PROTOTYPE SECTION ===*/
 } WMI_ROAM_PARAM;
 
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 5dc51601afb4..077255dd592a 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1390
+#define __WMI_REVISION_ 1391
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From de59b74d74c7b523b116cf1149a1111ceb56f6a0 Mon Sep 17 00:00:00 2001
From: Pratyush Brahma <quic_pbrahma@quicinc.com>
Date: Fri, 15 Sep 2023 16:14:49 +0530
Subject: [PATCH 067/298] iommu: Fix missing return check of arm_lpae_init_pte

UAF scenario may occur in clients with EL1 privileges for
iova mappings when we miss to check the return value of
arm_lpae_init_pte which may lead to an PTE be counted as
it was set even if it was already existing. This can cause a
dangling IOMMU PTE to be left mapped pointing to a
freed object and cause UAF in the client if the dangling PTE
is accessed after a failed unmap operation.

Fixes: 27de1978c331 ("ANDROID: GKI: iommu/io-pgtable-arm: LPAE related updates by vendor")
Change-Id: I674b9b520e705b8f8e63ba20ed76e64cb2fe0f47
Signed-off-by: Pratyush Brahma <quic_pbrahma@quicinc.com>
---
 drivers/iommu/io-pgtable-arm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index a6fad3ab7315..5b69ba8a9a8f 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -670,9 +670,11 @@ static int arm_lpae_map_sg(struct io_pgtable_ops *ops, unsigned long iova,
 				arm_lpae_iopte *ptep = ms.pgtable +
 					ARM_LPAE_LVL_IDX(iova, MAP_STATE_LVL,
 							 data);
-				arm_lpae_init_pte(
+				ret = arm_lpae_init_pte(
 					data, iova, phys, prot, MAP_STATE_LVL,
 					ptep, ms.prev_pgtable, false);
+				if (ret)
+					goto out_err;
 				ms.num_pte++;
 			} else {
 				ret = __arm_lpae_map(data, iova, phys, pgsize,
-- 
GitLab


From 56a19038c13d8923d208c5eb6a8529987d41a4cf Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Maciej=20=C5=BBenczykowski?= <maze@google.com>
Date: Sun, 26 Apr 2020 09:15:25 -0700
Subject: [PATCH 068/298] BACKPORT: bpf: add bpf_ktime_get_boot_ns()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

On a device like a cellphone which is constantly suspending
and resuming CLOCK_MONOTONIC is not particularly useful for
keeping track of or reacting to external network events.
Instead you want to use CLOCK_BOOTTIME.

Hence add bpf_ktime_get_boot_ns() as a mirror of bpf_ktime_get_ns()
based around CLOCK_BOOTTIME instead of CLOCK_MONOTONIC.

Signed-off-by: Maciej Żenczykowski <maze@google.com>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
(cherry picked from commit 71d19214776e61b33da48f7c1b46e522c7f78221)
Change-Id: Ifd62c410dcc5112fd1a473a7e1f70231ca514bc0
Git-commit: 4812ec50935dfe59ba9f48a572e278dd0b02af68
Git-repo: https://android.googlesource.com/kernel/common
Signed-off-by: Sharath Chandra Vurukala <quic_sharathv@quicinc.com>
---
 drivers/media/rc/bpf-lirc.c    |  2 ++
 include/linux/bpf.h            |  1 +
 include/uapi/linux/bpf.h       | 54 +++++++++++++++++++++++++++++++++-
 kernel/bpf/core.c              |  1 +
 kernel/bpf/helpers.c           | 12 ++++++++
 kernel/trace/bpf_trace.c       |  2 ++
 net/core/filter.c              |  2 ++
 tools/include/uapi/linux/bpf.h | 54 +++++++++++++++++++++++++++++++++-
 8 files changed, 126 insertions(+), 2 deletions(-)

diff --git a/drivers/media/rc/bpf-lirc.c b/drivers/media/rc/bpf-lirc.c
index 8b97fd1f0cea..d9d6f7feb4bf 100644
--- a/drivers/media/rc/bpf-lirc.c
+++ b/drivers/media/rc/bpf-lirc.c
@@ -75,6 +75,8 @@ lirc_mode2_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog)
 		return &bpf_map_delete_elem_proto;
 	case BPF_FUNC_ktime_get_ns:
 		return &bpf_ktime_get_ns_proto;
+	case BPF_FUNC_ktime_get_boot_ns:
+		return &bpf_ktime_get_boot_ns_proto;
 	case BPF_FUNC_tail_call:
 		return &bpf_tail_call_proto;
 	case BPF_FUNC_get_prandom_u32:
diff --git a/include/linux/bpf.h b/include/linux/bpf.h
index 16f6beef5cad..3cefd1bfccf5 100644
--- a/include/linux/bpf.h
+++ b/include/linux/bpf.h
@@ -813,6 +813,7 @@ extern const struct bpf_func_proto bpf_get_smp_processor_id_proto;
 extern const struct bpf_func_proto bpf_get_numa_node_id_proto;
 extern const struct bpf_func_proto bpf_tail_call_proto;
 extern const struct bpf_func_proto bpf_ktime_get_ns_proto;
+extern const struct bpf_func_proto bpf_ktime_get_boot_ns_proto;
 extern const struct bpf_func_proto bpf_get_current_pid_tgid_proto;
 extern const struct bpf_func_proto bpf_get_current_uid_gid_proto;
 extern const struct bpf_func_proto bpf_get_current_comm_proto;
diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h
index 71ca8c4dc290..271f9df82274 100644
--- a/include/uapi/linux/bpf.h
+++ b/include/uapi/linux/bpf.h
@@ -471,6 +471,8 @@ union bpf_attr {
  * u64 bpf_ktime_get_ns(void)
  * 	Description
  * 		Return the time elapsed since system boot, in nanoseconds.
+ * 		Does not include time the system was suspended.
+ * 		See: clock_gettime(CLOCK_MONOTONIC)
  * 	Return
  * 		Current *ktime*.
  *
@@ -2143,6 +2145,14 @@ union bpf_attr {
  *		request in the skb.
  *	Return
  *		0 on success, or a negative error in case of failure.
+ *
+ * u64 bpf_ktime_get_boot_ns(void)
+ * 	Description
+ * 		Return the time elapsed since system boot, in nanoseconds.
+ * 		Does include the time the system was suspended.
+ * 		See: clock_gettime(CLOCK_BOOTTIME)
+ * 	Return
+ * 		Current *ktime*.
  */
 #define __BPF_FUNC_MAPPER(FN)		\
 	FN(unspec),			\
@@ -2228,7 +2238,49 @@ union bpf_attr {
 	FN(get_current_cgroup_id),	\
 	FN(get_local_storage),		\
 	FN(sk_select_reuseport),	\
-	FN(skb_ancestor_cgroup_id),
+	FN(skb_ancestor_cgroup_id),	\
+	FN(sk_lookup_tcp),		\
+	FN(sk_lookup_udp),		\
+	FN(sk_release),			\
+	FN(map_push_elem),		\
+	FN(map_pop_elem),		\
+	FN(map_peek_elem),		\
+	FN(msg_push_data),		\
+	FN(msg_pop_data),		\
+	FN(rc_pointer_rel),		\
+	FN(spin_lock),			\
+	FN(spin_unlock),		\
+	FN(sk_fullsock),		\
+	FN(tcp_sock),			\
+	FN(skb_ecn_set_ce),		\
+	FN(get_listener_sock),		\
+	FN(skc_lookup_tcp),		\
+	FN(tcp_check_syncookie),	\
+	FN(sysctl_get_name),		\
+	FN(sysctl_get_current_value),	\
+	FN(sysctl_get_new_value),	\
+	FN(sysctl_set_new_value),	\
+	FN(strtol),			\
+	FN(strtoul),			\
+	FN(sk_storage_get),		\
+	FN(sk_storage_delete),		\
+	FN(send_signal),		\
+	FN(tcp_gen_syncookie),		\
+	FN(skb_output),			\
+	FN(probe_read_user),		\
+	FN(probe_read_kernel),		\
+	FN(probe_read_user_str),	\
+	FN(probe_read_kernel_str),	\
+	FN(tcp_send_ack),		\
+	FN(send_signal_thread),		\
+	FN(jiffies64),			\
+	FN(read_branch_records),	\
+	FN(get_ns_current_pid_tgid),	\
+	FN(xdp_output),			\
+	FN(get_netns_cookie),		\
+	FN(get_current_ancestor_cgroup_id),	\
+	FN(sk_assign),			\
+	FN(ktime_get_boot_ns),
 
 /* integer value in 'imm' field of BPF_CALL instruction selects which helper
  * function eBPF program intends to call
diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c
index bdfb74d85e22..afeb0a042098 100644
--- a/kernel/bpf/core.c
+++ b/kernel/bpf/core.c
@@ -1869,6 +1869,7 @@ const struct bpf_func_proto bpf_get_prandom_u32_proto __weak;
 const struct bpf_func_proto bpf_get_smp_processor_id_proto __weak;
 const struct bpf_func_proto bpf_get_numa_node_id_proto __weak;
 const struct bpf_func_proto bpf_ktime_get_ns_proto __weak;
+const struct bpf_func_proto bpf_ktime_get_boot_ns_proto __weak;
 
 const struct bpf_func_proto bpf_get_current_pid_tgid_proto __weak;
 const struct bpf_func_proto bpf_get_current_uid_gid_proto __weak;
diff --git a/kernel/bpf/helpers.c b/kernel/bpf/helpers.c
index a3015dcbbb84..c54e3ac03389 100644
--- a/kernel/bpf/helpers.c
+++ b/kernel/bpf/helpers.c
@@ -116,6 +116,18 @@ const struct bpf_func_proto bpf_ktime_get_ns_proto = {
 	.ret_type	= RET_INTEGER,
 };
 
+BPF_CALL_0(bpf_ktime_get_boot_ns)
+{
+	/* NMI safe access to clock boottime */
+	return ktime_get_boot_fast_ns();
+}
+
+const struct bpf_func_proto bpf_ktime_get_boot_ns_proto = {
+	.func		= bpf_ktime_get_boot_ns,
+	.gpl_only	= false,
+	.ret_type	= RET_INTEGER,
+};
+
 BPF_CALL_0(bpf_get_current_pid_tgid)
 {
 	struct task_struct *task = current;
diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c
index 83c4e76f513a..7ecbc464dae6 100644
--- a/kernel/trace/bpf_trace.c
+++ b/kernel/trace/bpf_trace.c
@@ -561,6 +561,8 @@ tracing_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog)
 		return &bpf_probe_read_proto;
 	case BPF_FUNC_ktime_get_ns:
 		return &bpf_ktime_get_ns_proto;
+	case BPF_FUNC_ktime_get_boot_ns:
+		return &bpf_ktime_get_boot_ns_proto;
 	case BPF_FUNC_tail_call:
 		return &bpf_tail_call_proto;
 	case BPF_FUNC_get_current_pid_tgid:
diff --git a/net/core/filter.c b/net/core/filter.c
index a14eecd9e413..5e75bdff5dc9 100644
--- a/net/core/filter.c
+++ b/net/core/filter.c
@@ -4844,6 +4844,8 @@ bpf_base_func_proto(enum bpf_func_id func_id)
 		return &bpf_tail_call_proto;
 	case BPF_FUNC_ktime_get_ns:
 		return &bpf_ktime_get_ns_proto;
+	case BPF_FUNC_ktime_get_boot_ns:
+		return &bpf_ktime_get_boot_ns_proto;
 	case BPF_FUNC_trace_printk:
 		if (capable(CAP_SYS_ADMIN))
 			return bpf_get_trace_printk_proto();
diff --git a/tools/include/uapi/linux/bpf.h b/tools/include/uapi/linux/bpf.h
index 13944978ada5..ff52939004e2 100644
--- a/tools/include/uapi/linux/bpf.h
+++ b/tools/include/uapi/linux/bpf.h
@@ -469,6 +469,8 @@ union bpf_attr {
  * u64 bpf_ktime_get_ns(void)
  * 	Description
  * 		Return the time elapsed since system boot, in nanoseconds.
+ * 		Does not include time the system was suspended.
+ * 		See: clock_gettime(CLOCK_MONOTONIC)
  * 	Return
  * 		Current *ktime*.
  *
@@ -2141,6 +2143,14 @@ union bpf_attr {
  *		request in the skb.
  *	Return
  *		0 on success, or a negative error in case of failure.
+ *
+ * u64 bpf_ktime_get_boot_ns(void)
+ * 	Description
+ * 		Return the time elapsed since system boot, in nanoseconds.
+ * 		Does include the time the system was suspended.
+ * 		See: clock_gettime(CLOCK_BOOTTIME)
+ * 	Return
+ * 		Current *ktime*.
  */
 #define __BPF_FUNC_MAPPER(FN)		\
 	FN(unspec),			\
@@ -2226,7 +2236,49 @@ union bpf_attr {
 	FN(get_current_cgroup_id),	\
 	FN(get_local_storage),		\
 	FN(sk_select_reuseport),	\
-	FN(skb_ancestor_cgroup_id),
+	FN(skb_ancestor_cgroup_id),	\
+	FN(sk_lookup_tcp),		\
+	FN(sk_lookup_udp),		\
+	FN(sk_release),			\
+	FN(map_push_elem),		\
+	FN(map_pop_elem),		\
+	FN(map_peek_elem),		\
+	FN(msg_push_data),		\
+	FN(msg_pop_data),		\
+	FN(rc_pointer_rel),		\
+	FN(spin_lock),			\
+	FN(spin_unlock),		\
+	FN(sk_fullsock),		\
+	FN(tcp_sock),			\
+	FN(skb_ecn_set_ce),		\
+	FN(get_listener_sock),		\
+	FN(skc_lookup_tcp),		\
+	FN(tcp_check_syncookie),	\
+	FN(sysctl_get_name),		\
+	FN(sysctl_get_current_value),	\
+	FN(sysctl_get_new_value),	\
+	FN(sysctl_set_new_value),	\
+	FN(strtol),			\
+	FN(strtoul),			\
+	FN(sk_storage_get),		\
+	FN(sk_storage_delete),		\
+	FN(send_signal),		\
+	FN(tcp_gen_syncookie),		\
+	FN(skb_output),			\
+	FN(probe_read_user),		\
+	FN(probe_read_kernel),		\
+	FN(probe_read_user_str),	\
+	FN(probe_read_kernel_str),	\
+	FN(tcp_send_ack),		\
+	FN(send_signal_thread),		\
+	FN(jiffies64),			\
+	FN(read_branch_records),	\
+	FN(get_ns_current_pid_tgid),	\
+	FN(xdp_output),			\
+	FN(get_netns_cookie),		\
+	FN(get_current_ancestor_cgroup_id),	\
+	FN(sk_assign),			\
+	FN(ktime_get_boot_ns),
 
 /* integer value in 'imm' field of BPF_CALL instruction selects which helper
  * function eBPF program intends to call
-- 
GitLab


From 7b7d8fcd8c62ffc4e2ad734ac8fd206077b48a54 Mon Sep 17 00:00:00 2001
From: spuligil <quic_spuligil@quicinc.com>
Date: Fri, 22 Sep 2023 01:27:49 -0700
Subject: [PATCH 069/298] fw-api: CL 24698636 - update fw common interface
 files

add WMI_COEX_CONFIG_ENABLE_CONT_INFO def

Change-Id: I363342d6e5939adf675e8e1de14eef2aab6aa81a
CRs-Fixed: 2262693
---
 fw/wmi_unified.h | 9 +++++++++
 fw/wmi_version.h | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 06187a29ca7f..65610e75108e 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -34550,6 +34550,15 @@ typedef enum wmi_coex_config_type {
      *         Enable all coex policies.
      */
     WMI_COEX_SET_TRAFFIC_SHAPING_MODE = 50,
+    /* WMI_COEX_CONFIG_ENABLE_CONT_INFO
+     * enable contention info log
+     * arg1:
+     *     0: disable both cont/sched log
+     *     1: enable cont log
+     *     2: enable sched log
+     *     3: enable both cont and sched log
+     */
+    WMI_COEX_CONFIG_ENABLE_CONT_INFO = 51,
 } WMI_COEX_CONFIG_TYPE;
 
 typedef struct {
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 077255dd592a..35aa809e0fc8 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
  *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1391
+#define __WMI_REVISION_ 1392
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
-- 
GitLab


From ce3ab0ecaea52cef334979481360401707d2b349 Mon Sep 17 00:00:00 2001
From: gaoxiang <quic_gaoxiang@quicinc.com>
Date: Wed, 27 Sep 2023 18:52:29 +0800
Subject: [PATCH 070/298] bt: Unset multi channel bit for 44.1/88.2Khz A2DP Rx

When opening port for 44.1/88.2KHz A2DP Rx, explicitly
unset multi channel bit. This is required because for SCO/A2DP
with other sample rates, we set the multi channel bit. The
bit remains set even after the channel is removed and until we
expliciltly unset again.

Change-Id: I76d7a46b107baf811657b7ade307a7dd60a21c4a
Signed-off-by: gaoxiang <quic_gaoxiang@quicinc.com>
---
 drivers/bluetooth/btfm_slim_slave.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/bluetooth/btfm_slim_slave.c b/drivers/bluetooth/btfm_slim_slave.c
index f02e31950093..25f2774b65b7 100644
--- a/drivers/bluetooth/btfm_slim_slave.c
+++ b/drivers/bluetooth/btfm_slim_slave.c
@@ -81,14 +81,12 @@ int btfm_slim_slave_enable_port(struct btfmslim *btfmslim, uint8_t port_num,
 	uint8_t reg_val = 0, en;
 	uint8_t rxport_num = 0;
 	uint16_t reg;
+	uint8_t prev_reg_val = 0;
 
 	BTFMSLIM_DBG("port(%d) enable(%d)", port_num, enable);
 	if (rxport) {
 		BTFMSLIM_DBG("sample rate is %d", btfmslim->sample_rate);
-		if (enable &&
-			btfmslim->sample_rate != 44100 &&
-			btfmslim->sample_rate != 88200) {
-			BTFMSLIM_DBG("setting multichannel bit");
+		if (enable) {
 			/* For SCO Rx, A2DP Rx other than 44.1 and 88.2Khz */
 			if (port_num < 24) {
 				rxport_num = port_num - 16;
@@ -102,6 +100,21 @@ int btfm_slim_slave_enable_port(struct btfmslim *btfmslim, uint8_t port_num,
 					rxport_num);
 			}
 
+			if (btfmslim->sample_rate == 44100 ||
+				btfmslim->sample_rate == 88200) {
+				BTFMSLIM_DBG("unsetting multichannel bit");
+				ret = btfm_slim_read(btfmslim, reg,  1,
+							&prev_reg_val, IFD);
+				if (ret < 0) {
+					BTFMSLIM_ERR("error %d reading", ret);
+					prev_reg_val = 0;
+				}
+				BTFMSLIM_DBG("prev_reg_val (%d) from reg(%x)",
+						prev_reg_val, reg);
+				reg_val = prev_reg_val & ~reg_val;
+			} else
+				BTFMSLIM_DBG("setting multichannel bit");
+
 			BTFMSLIM_DBG("writing reg_val (%d) to reg(%x)",
 				reg_val, reg);
 			ret = btfm_slim_write(btfmslim, reg, 1, &reg_val, IFD);
-- 
GitLab


From d66b799c804083ea5226cfffac6d6c4e7ad4968b Mon Sep 17 00:00:00 2001
From: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Date: Fri, 8 Sep 2023 15:46:15 -0700
Subject: [PATCH 071/298] msm: kgsl: Prevent wrap around during user address
 mapping

When setting svm region during the gpuobj import ioctl call for a usermem
address, there is a possibility of a very large input size causing the
region's 64-bit end address to wrap around. This can cause the region
to incorrectly be considered valid, ultimately allowing a use after free
scenario. To prevent this, detect the occurrence of a wrap and reject the
import.

Change-Id: I4a88f56c58b830d4342e47dc1d1f6290c78ab6b4
Signed-off-by: Mohammed Mirza Mandayappurath Manzoor <quic_mmandaya@quicinc.com>
Signed-off-by: Puranam V G Tejaswi <quic_pvgtejas@quicinc.com>
---
 drivers/gpu/msm/kgsl_iommu.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c
index e4b9924baec2..c54f6edaf6fc 100644
--- a/drivers/gpu/msm/kgsl_iommu.c
+++ b/drivers/gpu/msm/kgsl_iommu.c
@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2011-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/compat.h>
@@ -2428,14 +2428,18 @@ static uint64_t kgsl_iommu_find_svm_region(struct kgsl_pagetable *pagetable,
 static bool iommu_addr_in_svm_ranges(struct kgsl_iommu_pt *pt,
 	u64 gpuaddr, u64 size)
 {
+	u64 end = gpuaddr + size;
+
+	/* Make sure size is not zero and we don't wrap around */
+	if (end <= gpuaddr)
+		return false;
+
 	if ((gpuaddr >= pt->compat_va_start && gpuaddr < pt->compat_va_end) &&
-		((gpuaddr + size) > pt->compat_va_start &&
-			(gpuaddr + size) <= pt->compat_va_end))
+		(end > pt->compat_va_start && end <= pt->compat_va_end))
 		return true;
 
 	if ((gpuaddr >= pt->svm_start && gpuaddr < pt->svm_end) &&
-		((gpuaddr + size) > pt->svm_start &&
-			(gpuaddr + size) <= pt->svm_end))
+		(end > pt->svm_start && end <= pt->svm_end))
 		return true;
 
 	return false;
-- 
GitLab


From 1e46e81dbeb69aafd5842ce779f07e617680fd58 Mon Sep 17 00:00:00 2001
From: Kaushal Sanadhya <quic_ksanadhy@quicinc.com>
Date: Fri, 15 Sep 2023 11:35:16 +0530
Subject: [PATCH 072/298] msm: kgsl: Limit the syncpoint count for AUX commands

KGSL internally has a limit on the length of the list of syncpoints
submitted in a single AUX command. Enforce this limit so we don't
overwrite memory beyond the structures that track these syncpoints.

Change-Id: I261bfd4f786ff7e4fbe07e8bca9e9b8d8b87c950
Signed-off-by: Lynus Vaz <quic_lvaz@quicinc.com>
Signed-off-by: Kaushal Sanadhya <quic_ksanadhy@quicinc.com>
---
 drivers/gpu/msm/kgsl.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index f3c37d7a0670..124244538060 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -2129,6 +2129,10 @@ long kgsl_ioctl_gpu_aux_command(struct kgsl_device_private *dev_priv,
 	if (!(param->flags & KGSL_GPU_AUX_COMMAND_TIMELINE))
 		return -EINVAL;
 
+	if ((param->flags & KGSL_GPU_AUX_COMMAND_SYNC) &&
+		(param->numsyncs > KGSL_MAX_SYNCPOINTS))
+		return -EINVAL;
+
 	context = kgsl_context_get_owner(dev_priv, param->context_id);
 	if (!context)
 		return -EINVAL;
-- 
GitLab


From f8fe0e3aa03be1fd261fcf59ec8aa245c08debd3 Mon Sep 17 00:00:00 2001
From: Krishna Kurapati <quic_kriskura@quicinc.com>
Date: Tue, 3 Oct 2023 18:31:24 +0530
Subject: [PATCH 073/298] usb: dwc3: gadget: Bail out in pullup if soft reset
 timeout happens

If the core soft reset timeout happens, avoid setting up event
buffers and starting gadget as the writes to these registers
may not reflect when in reset and setting the run stop bit
can lead the controller to access wrong event buffer address
resulting in a crash.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20230510075252.31023-2-quic_kriskura@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

(cherry picked from commit 813f44d57e19ccaa7330e829bd913515be42719d
https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/ usb
-next).

Change-Id: I7f17f0bf28f785b0798025476f76b040e8b83e2c
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 drivers/usb/dwc3/gadget.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 12579d7fe365..c32e8bcd7db5 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2472,8 +2472,11 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
 	/* prevent pending bh to run later */
 	flush_work(&dwc->bh_work);
 
-	if (is_on)
-		dwc3_device_core_soft_reset(dwc);
+	if (is_on) {
+		ret = dwc3_device_core_soft_reset(dwc);
+		if (ret != 0)
+			goto done;
+	}
 
 	spin_lock_irqsave(&dwc->lock, flags);
 	if (dwc->ep0state != EP0_SETUP_PHASE)
@@ -2502,6 +2505,7 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
 	}
 	enable_irq(dwc->irq);
 
+done:
 	pm_runtime_mark_last_busy(dwc->dev);
 	pm_runtime_put_autosuspend(dwc->dev);
 	dbg_event(0xFF, "Pullup put",
-- 
GitLab


From 1cebc8ce23ae92c70ccb3a03a42cb7c84cb2764c Mon Sep 17 00:00:00 2001
From: Paras Sharma <quic_parass@quicinc.com>
Date: Fri, 16 Jun 2023 10:27:03 +0530
Subject: [PATCH 074/298] bus: mhi: fix potential out-of-bound access

In the mhi_sat_isvalid_header function if the length is less than
the size of header then there can be out-of-bound access.

So fix the len check in the function.

Change-Id: I80f1556557b1bf2f30c07f6377bd6e3db48712b3
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Paras Sharma <quic_parass@quicinc.com>
---
 drivers/bus/mhi/devices/mhi_satellite.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/bus/mhi/devices/mhi_satellite.c b/drivers/bus/mhi/devices/mhi_satellite.c
index 24621475a268..2f226093157f 100644
--- a/drivers/bus/mhi/devices/mhi_satellite.c
+++ b/drivers/bus/mhi/devices/mhi_satellite.c
@@ -358,7 +358,7 @@ static struct mhi_sat_device *find_sat_dev_by_id(
 static bool mhi_sat_isvalid_header(struct sat_header *hdr, int len)
 {
 	/* validate payload size */
-	if (len >= sizeof(*hdr) && (len != hdr->payload_size + sizeof(*hdr)))
+	if (len < sizeof(*hdr) || len != hdr->payload_size + sizeof(*hdr))
 		return false;
 
 	/* validate SAT IPC version */
-- 
GitLab


From 051fdb19a18cafcc9a7c0956e0eb04986e6ce24b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Maciej=20=C5=BBenczykowski?= <maze@google.com>
Date: Sun, 26 Apr 2020 09:15:25 -0700
Subject: [PATCH 075/298] BACKPORT: bpf: add bpf_ktime_get_boot_ns()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

On a device like a cellphone which is constantly suspending
and resuming CLOCK_MONOTONIC is not particularly useful for
keeping track of or reacting to external network events.
Instead you want to use CLOCK_BOOTTIME.

Hence add bpf_ktime_get_boot_ns() as a mirror of bpf_ktime_get_ns()
based around CLOCK_BOOTTIME instead of CLOCK_MONOTONIC.

Signed-off-by: Maciej Żenczykowski <maze@google.com>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
(cherry picked from commit 71d19214776e61b33da48f7c1b46e522c7f78221)
Change-Id: Ifd62c410dcc5112fd1a473a7e1f70231ca514bc0
Git-commit: 4812ec50935dfe59ba9f48a572e278dd0b02af68
Git-repo: https://android.googlesource.com/kernel/common
Signed-off-by: Sharath Chandra Vurukala <quic_sharathv@quicinc.com>
(cherry picked from commit 56a19038c13d8923d208c5eb6a8529987d41a4cf)
---
 drivers/media/rc/bpf-lirc.c    |  2 ++
 include/linux/bpf.h            |  1 +
 include/uapi/linux/bpf.h       | 54 +++++++++++++++++++++++++++++++++-
 kernel/bpf/core.c              |  1 +
 kernel/bpf/helpers.c           | 12 ++++++++
 kernel/trace/bpf_trace.c       |  2 ++
 net/core/filter.c              |  2 ++
 tools/include/uapi/linux/bpf.h | 54 +++++++++++++++++++++++++++++++++-
 8 files changed, 126 insertions(+), 2 deletions(-)

diff --git a/drivers/media/rc/bpf-lirc.c b/drivers/media/rc/bpf-lirc.c
index 8b97fd1f0cea..d9d6f7feb4bf 100644
--- a/drivers/media/rc/bpf-lirc.c
+++ b/drivers/media/rc/bpf-lirc.c
@@ -75,6 +75,8 @@ lirc_mode2_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog)
 		return &bpf_map_delete_elem_proto;
 	case BPF_FUNC_ktime_get_ns:
 		return &bpf_ktime_get_ns_proto;
+	case BPF_FUNC_ktime_get_boot_ns:
+		return &bpf_ktime_get_boot_ns_proto;
 	case BPF_FUNC_tail_call:
 		return &bpf_tail_call_proto;
 	case BPF_FUNC_get_prandom_u32:
diff --git a/include/linux/bpf.h b/include/linux/bpf.h
index 16f6beef5cad..3cefd1bfccf5 100644
--- a/include/linux/bpf.h
+++ b/include/linux/bpf.h
@@ -813,6 +813,7 @@ extern const struct bpf_func_proto bpf_get_smp_processor_id_proto;
 extern const struct bpf_func_proto bpf_get_numa_node_id_proto;
 extern const struct bpf_func_proto bpf_tail_call_proto;
 extern const struct bpf_func_proto bpf_ktime_get_ns_proto;
+extern const struct bpf_func_proto bpf_ktime_get_boot_ns_proto;
 extern const struct bpf_func_proto bpf_get_current_pid_tgid_proto;
 extern const struct bpf_func_proto bpf_get_current_uid_gid_proto;
 extern const struct bpf_func_proto bpf_get_current_comm_proto;
diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h
index 71ca8c4dc290..271f9df82274 100644
--- a/include/uapi/linux/bpf.h
+++ b/include/uapi/linux/bpf.h
@@ -471,6 +471,8 @@ union bpf_attr {
  * u64 bpf_ktime_get_ns(void)
  * 	Description
  * 		Return the time elapsed since system boot, in nanoseconds.
+ * 		Does not include time the system was suspended.
+ * 		See: clock_gettime(CLOCK_MONOTONIC)
  * 	Return
  * 		Current *ktime*.
  *
@@ -2143,6 +2145,14 @@ union bpf_attr {
  *		request in the skb.
  *	Return
  *		0 on success, or a negative error in case of failure.
+ *
+ * u64 bpf_ktime_get_boot_ns(void)
+ * 	Description
+ * 		Return the time elapsed since system boot, in nanoseconds.
+ * 		Does include the time the system was suspended.
+ * 		See: clock_gettime(CLOCK_BOOTTIME)
+ * 	Return
+ * 		Current *ktime*.
  */
 #define __BPF_FUNC_MAPPER(FN)		\
 	FN(unspec),			\
@@ -2228,7 +2238,49 @@ union bpf_attr {
 	FN(get_current_cgroup_id),	\
 	FN(get_local_storage),		\
 	FN(sk_select_reuseport),	\
-	FN(skb_ancestor_cgroup_id),
+	FN(skb_ancestor_cgroup_id),	\
+	FN(sk_lookup_tcp),		\
+	FN(sk_lookup_udp),		\
+	FN(sk_release),			\
+	FN(map_push_elem),		\
+	FN(map_pop_elem),		\
+	FN(map_peek_elem),		\
+	FN(msg_push_data),		\
+	FN(msg_pop_data),		\
+	FN(rc_pointer_rel),		\
+	FN(spin_lock),			\
+	FN(spin_unlock),		\
+	FN(sk_fullsock),		\
+	FN(tcp_sock),			\
+	FN(skb_ecn_set_ce),		\
+	FN(get_listener_sock),		\
+	FN(skc_lookup_tcp),		\
+	FN(tcp_check_syncookie),	\
+	FN(sysctl_get_name),		\
+	FN(sysctl_get_current_value),	\
+	FN(sysctl_get_new_value),	\
+	FN(sysctl_set_new_value),	\
+	FN(strtol),			\
+	FN(strtoul),			\
+	FN(sk_storage_get),		\
+	FN(sk_storage_delete),		\
+	FN(send_signal),		\
+	FN(tcp_gen_syncookie),		\
+	FN(skb_output),			\
+	FN(probe_read_user),		\
+	FN(probe_read_kernel),		\
+	FN(probe_read_user_str),	\
+	FN(probe_read_kernel_str),	\
+	FN(tcp_send_ack),		\
+	FN(send_signal_thread),		\
+	FN(jiffies64),			\
+	FN(read_branch_records),	\
+	FN(get_ns_current_pid_tgid),	\
+	FN(xdp_output),			\
+	FN(get_netns_cookie),		\
+	FN(get_current_ancestor_cgroup_id),	\
+	FN(sk_assign),			\
+	FN(ktime_get_boot_ns),
 
 /* integer value in 'imm' field of BPF_CALL instruction selects which helper
  * function eBPF program intends to call
diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c
index bdfb74d85e22..afeb0a042098 100644
--- a/kernel/bpf/core.c
+++ b/kernel/bpf/core.c
@@ -1869,6 +1869,7 @@ const struct bpf_func_proto bpf_get_prandom_u32_proto __weak;
 const struct bpf_func_proto bpf_get_smp_processor_id_proto __weak;
 const struct bpf_func_proto bpf_get_numa_node_id_proto __weak;
 const struct bpf_func_proto bpf_ktime_get_ns_proto __weak;
+const struct bpf_func_proto bpf_ktime_get_boot_ns_proto __weak;
 
 const struct bpf_func_proto bpf_get_current_pid_tgid_proto __weak;
 const struct bpf_func_proto bpf_get_current_uid_gid_proto __weak;
diff --git a/kernel/bpf/helpers.c b/kernel/bpf/helpers.c
index a3015dcbbb84..c54e3ac03389 100644
--- a/kernel/bpf/helpers.c
+++ b/kernel/bpf/helpers.c
@@ -116,6 +116,18 @@ const struct bpf_func_proto bpf_ktime_get_ns_proto = {
 	.ret_type	= RET_INTEGER,
 };
 
+BPF_CALL_0(bpf_ktime_get_boot_ns)
+{
+	/* NMI safe access to clock boottime */
+	return ktime_get_boot_fast_ns();
+}
+
+const struct bpf_func_proto bpf_ktime_get_boot_ns_proto = {
+	.func		= bpf_ktime_get_boot_ns,
+	.gpl_only	= false,
+	.ret_type	= RET_INTEGER,
+};
+
 BPF_CALL_0(bpf_get_current_pid_tgid)
 {
 	struct task_struct *task = current;
diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c
index 83c4e76f513a..7ecbc464dae6 100644
--- a/kernel/trace/bpf_trace.c
+++ b/kernel/trace/bpf_trace.c
@@ -561,6 +561,8 @@ tracing_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog)
 		return &bpf_probe_read_proto;
 	case BPF_FUNC_ktime_get_ns:
 		return &bpf_ktime_get_ns_proto;
+	case BPF_FUNC_ktime_get_boot_ns:
+		return &bpf_ktime_get_boot_ns_proto;
 	case BPF_FUNC_tail_call:
 		return &bpf_tail_call_proto;
 	case BPF_FUNC_get_current_pid_tgid:
diff --git a/net/core/filter.c b/net/core/filter.c
index a14eecd9e413..5e75bdff5dc9 100644
--- a/net/core/filter.c
+++ b/net/core/filter.c
@@ -4844,6 +4844,8 @@ bpf_base_func_proto(enum bpf_func_id func_id)
 		return &bpf_tail_call_proto;
 	case BPF_FUNC_ktime_get_ns:
 		return &bpf_ktime_get_ns_proto;
+	case BPF_FUNC_ktime_get_boot_ns:
+		return &bpf_ktime_get_boot_ns_proto;
 	case BPF_FUNC_trace_printk:
 		if (capable(CAP_SYS_ADMIN))
 			return bpf_get_trace_printk_proto();
diff --git a/tools/include/uapi/linux/bpf.h b/tools/include/uapi/linux/bpf.h
index 13944978ada5..ff52939004e2 100644
--- a/tools/include/uapi/linux/bpf.h
+++ b/tools/include/uapi/linux/bpf.h
@@ -469,6 +469,8 @@ union bpf_attr {
  * u64 bpf_ktime_get_ns(void)
  * 	Description
  * 		Return the time elapsed since system boot, in nanoseconds.
+ * 		Does not include time the system was suspended.
+ * 		See: clock_gettime(CLOCK_MONOTONIC)
  * 	Return
  * 		Current *ktime*.
  *
@@ -2141,6 +2143,14 @@ union bpf_attr {
  *		request in the skb.
  *	Return
  *		0 on success, or a negative error in case of failure.
+ *
+ * u64 bpf_ktime_get_boot_ns(void)
+ * 	Description
+ * 		Return the time elapsed since system boot, in nanoseconds.
+ * 		Does include the time the system was suspended.
+ * 		See: clock_gettime(CLOCK_BOOTTIME)
+ * 	Return
+ * 		Current *ktime*.
  */
 #define __BPF_FUNC_MAPPER(FN)		\
 	FN(unspec),			\
@@ -2226,7 +2236,49 @@ union bpf_attr {
 	FN(get_current_cgroup_id),	\
 	FN(get_local_storage),		\
 	FN(sk_select_reuseport),	\
-	FN(skb_ancestor_cgroup_id),
+	FN(skb_ancestor_cgroup_id),	\
+	FN(sk_lookup_tcp),		\
+	FN(sk_lookup_udp),		\
+	FN(sk_release),			\
+	FN(map_push_elem),		\
+	FN(map_pop_elem),		\
+	FN(map_peek_elem),		\
+	FN(msg_push_data),		\
+	FN(msg_pop_data),		\
+	FN(rc_pointer_rel),		\
+	FN(spin_lock),			\
+	FN(spin_unlock),		\
+	FN(sk_fullsock),		\
+	FN(tcp_sock),			\
+	FN(skb_ecn_set_ce),		\
+	FN(get_listener_sock),		\
+	FN(skc_lookup_tcp),		\
+	FN(tcp_check_syncookie),	\
+	FN(sysctl_get_name),		\
+	FN(sysctl_get_current_value),	\
+	FN(sysctl_get_new_value),	\
+	FN(sysctl_set_new_value),	\
+	FN(strtol),			\
+	FN(strtoul),			\
+	FN(sk_storage_get),		\
+	FN(sk_storage_delete),		\
+	FN(send_signal),		\
+	FN(tcp_gen_syncookie),		\
+	FN(skb_output),			\
+	FN(probe_read_user),		\
+	FN(probe_read_kernel),		\
+	FN(probe_read_user_str),	\
+	FN(probe_read_kernel_str),	\
+	FN(tcp_send_ack),		\
+	FN(send_signal_thread),		\
+	FN(jiffies64),			\
+	FN(read_branch_records),	\
+	FN(get_ns_current_pid_tgid),	\
+	FN(xdp_output),			\
+	FN(get_netns_cookie),		\
+	FN(get_current_ancestor_cgroup_id),	\
+	FN(sk_assign),			\
+	FN(ktime_get_boot_ns),
 
 /* integer value in 'imm' field of BPF_CALL instruction selects which helper
  * function eBPF program intends to call
-- 
GitLab


From cc1a40e4cfeb86628495118149fa917df9f53fad Mon Sep 17 00:00:00 2001
From: Madhukumar S J <quic_msj@quicinc.com>
Date: Wed, 6 Sep 2023 11:25:35 +0530
Subject: [PATCH 076/298] msm : Cap framerate for all Intra setting

check the framerate and cap output framerate
based on allintra encoding.

Signed-off-by: Madhukumar S J <quic_msj@quicinc.com>
---
 msm/vidc/msm_venc.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/msm/vidc/msm_venc.c b/msm/vidc/msm_venc.c
index 2e71b924a58f..69c26c565e02 100644
--- a/msm/vidc/msm_venc.c
+++ b/msm/vidc/msm_venc.c
@@ -4628,6 +4628,13 @@ int handle_all_intra_restrictions(struct msm_vidc_inst *inst)
 	fps_max = capability->cap[CAP_ALLINTRA_MAX_FPS].max;
 	s_vpr_h(inst->sid, "%s: rc_type %u, fps %u, fps_max %u\n",
 		__func__, inst->rc_type, n_fps, fps_max);
+	if (inst->all_intra && n_fps > fps_max) {
+		inst->clk_data.frame_rate = fps_max << 16;
+		n_fps = fps_max;
+		s_vpr_h(inst->sid,
+			"%s:cap2 frame rate to %u for allintra encoding",
+			__func__, inst->clk_data.frame_rate >> 16);
+	}
 	if ((inst->rc_type != V4L2_MPEG_VIDEO_BITRATE_MODE_VBR &&
 		inst->rc_type != RATE_CONTROL_OFF &&
 		inst->rc_type != RATE_CONTROL_LOSSLESS) ||
-- 
GitLab


From 06b23a9ca4bf5713bfff85906f360f8e0d2eae33 Mon Sep 17 00:00:00 2001
From: Krishna Kurapati <quic_kriskura@quicinc.com>
Date: Tue, 3 Oct 2023 18:32:15 +0530
Subject: [PATCH 077/298] usb: dwc3-msm-core: Set pipectl susphy in conndone
 interrupt
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

As per DesignWare Cores SuperSpeed USB 3.0 Controller Databook
Version 3.00a May 2015, section 8.1.3: Initialization on Connect
Done (Step-4)

GUSB2CFG/ GUSB3PIPECTL:
Depending on the connected speed, write to the other PHY’s control
register to suspend it

For SMMU Fault issue where the controller was accessing 0th address,
as per tests conducted, during core initialization, if the
GUSB3PIPECTL SUSPHY bit is set, the register writes (including GEVT)
are not going through and causing a CSR Timeout. As per databook, the
USB3 SUSPHY bit must be enabled after the link up happens in high
speed and not during core initialization. Fix this by clearing the
bit before core soft reset and setting it in conndone exit kretprobe
if the link up happens in high speed.

Change-Id: I6d416545220f65064a17248f1b1ba5a3a0a7eac2
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 drivers/usb/dwc3/dwc3-msm.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
index fe47d5ad429e..1360c7d6db59 100644
--- a/drivers/usb/dwc3/dwc3-msm.c
+++ b/drivers/usb/dwc3/dwc3-msm.c
@@ -2005,6 +2005,24 @@ static void dwc3_gsi_event_buf_alloc(struct dwc3 *dwc)
 	}
 }
 
+static void dwc3_msm_modify_pipectl(struct dwc3 *dwc, bool set)
+{
+	struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent);
+	u32 reg;
+
+	reg = dwc3_msm_read_reg(mdwc->base, DWC3_GUSB3PIPECTL(0));
+
+	if (set) {
+		if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
+			(dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
+			reg |= DWC3_GUSB3PIPECTL_SUSPHY;
+	} else {
+		reg &= ~(DWC3_GUSB3PIPECTL_SUSPHY);
+	}
+
+	dwc3_msm_write_reg(mdwc->base, DWC3_GUSB3PIPECTL(0), reg);
+}
+
 static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event,
 							unsigned int value)
 {
@@ -2070,6 +2088,9 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event,
 		break;
 	case DWC3_CONTROLLER_CONNDONE_EVENT:
 		dev_dbg(mdwc->dev, "DWC3_CONTROLLER_CONNDONE_EVENT received\n");
+
+		dwc3_msm_modify_pipectl(dwc, true);
+
 		/*
 		 * Add power event if the dbm indicates coming out of L1 by
 		 * interrupt
@@ -2194,6 +2215,13 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event,
 		break;
 	case DWC3_CONTROLLER_NOTIFY_CLEAR_DB:
 		dev_dbg(mdwc->dev, "DWC3_CONTROLLER_NOTIFY_CLEAR_DB\n");
+
+		/*
+		 * Clear the susphy bit here to ensure it is not set during
+		 * the course of controller initialisation process.
+		 */
+		dwc3_msm_modify_pipectl(dwc, false);
+
 		if (!mdwc->gsi_ev_buff)
 			break;
 
-- 
GitLab


From 5759bbcc0d24a0f84f9021cf06f02a08c4e739fe Mon Sep 17 00:00:00 2001
From: Yumi Yukimura <me.cafebabe@gmail.com>
Date: Sat, 23 Sep 2023 01:20:43 +0800
Subject: [PATCH 078/298] ANDROID: ALSA: jack: Revert mismerge done in
 v4.19.291

This reverts commit 839f4e860eb6aff659ad05900963cf0410063eda

As of the commit 839f4e860eb6 ("ALSA: jack: Fix mutex call in snd_jack_report()"),
the change was introduced in order to fix commit c093b62c4002 ("ALSA: jack: Access input_dev under mutex")
which was later on reverted in commit 9508bececcf5 ("Revert "ALSA: jack: Access input_dev under mutex"")
as of reason that it broke kernel ABI and is not relevant for Android system.

Furthermore, this mismerge also lead to following null pointer dereference
in certain scenarios like plugging in 3.5mm headset.

[ 1142.234701] Unable to handle kernel read from unreadable memory at virtual address 0000000000000028
[ 1142.234720] Mem abort info:
[ 1142.234729] ESR = 0x96000005
[ 1142.234739] Exception class = DABT (current EL), IL = 32 bits
[ 1142.234747] SET = 0, FnV = 0
[ 1142.234755] EA = 0, S1PTW = 0
[ 1142.234762] Data abort info:
[ 1142.234770] ISV = 0, ISS = 0x00000005
[ 1142.234778] CM = 0, WnR = 0
[ 1142.234790] user pgtable: 4k pages, 39-bit VAs, pgdp = 0000000016d049a1
[ 1142.234799] [0000000000000028] pgd=00000000eb5a7003, pud=00000000eb5a7003, pmd=0000000000000000
[ 1142.234817] Internal error: Oops: 96000005 [#1] PREEMPT SMP
[ 1142.234828] Modules linked in:
[ 1142.234839] Process kworker/5:0 (pid: 5915, stack limit = 0x000000000ffb215a)
[ 1142.234853] CPU: 5 PID: 5915 Comm: kworker/5:0 Tainted: G W 4.19.294-Mi8937v2-gb3b17955ff52 #1
[ 1142.234862] Hardware name: Qualcomm Technologies, Inc. MSM8940-PMI8937 MTP (DT)
[ 1142.234886] Workqueue: events wcd_correct_swch_plug
[ 1142.234899] pstate: 80400005 (Nzcv daif +PAN -UAO)
[ 1142.234914] pc : input_event+0x2c/0x84
[ 1142.234929] lr : snd_jack_report+0xc4/0x17c
[ 1142.234937] sp : ffffff801c07bbe0
[ 1142.234945] x29: ffffff801c07bbe0 x28: 0000000000000402
[ 1142.234957] x27: ffffff800a110028 x26: ffffffc0d2e92480
[ 1142.234969] x25: ffffffc0cb9b32c0 x24: ffffff800a46f398
[ 1142.234981] x23: ffffff800a110028 x22: 0000000000000000
[ 1142.234992] x21: 0000000000000005 x20: 000000000000000c
[ 1142.235004] x19: ffffffc0cb9da400 x18: 0000000005f5e100
[ 1142.235015] x17: 0000000000000000 x16: 0000000000000000
[ 1142.235026] x15: ffffffffff21d823 x14: 0000000001312d00
[ 1142.235038] x13: 0000000000000000 x12: 0000000038e38e39
[ 1142.235049] x11: 0000000000000000 x10: 0000000000000003
[ 1142.235060] x9 : ffffff800a4ce000 x8 : 0000000000000000
[ 1142.235072] x7 : 0000000000000001 x6 : ffffffc0ef490a83
[ 1142.235083] x5 : 0000000000000001 x4 : 0000000000000001
[ 1142.235094] x3 : 0000000000000000 x2 : 0000000000000002
[ 1142.235105] x1 : 0000000000000005 x0 : 0000000000000000
[ 1142.235117] Call trace:
[ 1142.235128] input_event+0x2c/0x84
[ 1142.235140] snd_jack_report+0xc4/0x17c
[ 1142.235152] snd_soc_jack_report+0x1ec/0x21c
[ 1142.235164] wcd_mbhc_report_plug+0x414/0x6f4
[ 1142.235176] wcd_mbhc_find_plug_and_report+0xcc/0x27c
[ 1142.235188] wcd_correct_swch_plug+0x198/0xbf0
[ 1142.235203] process_one_work+0x224/0x3ec
[ 1142.235215] worker_thread+0x260/0x4a8
[ 1142.235227] kthread+0x138/0x154
[ 1142.235239] ret_from_fork+0x10/0x18
[ 1142.235254] Code: 53067c28 2a0103f5 aa0003f6 8b284c08 (f9401508)
[ 1142.235265] ---[ end trace 98bff2bd0de72df6 ]---
[ 1142.328772] Kernel panic - not syncing: Fatal exception

Bug: 304056831
Co-authored-by: Hridaya Prajapati <info.hridayaprajapati@gmail.com>
Signed-off-by: Hridaya Prajapati <info.hridayaprajapati@gmail.com>
Signed-off-by: Yumi Yukimura <me.cafebabe@gmail.com>
Change-Id: I146cf474603681243c62672491aaf3c5187551d7
---
 sound/core/jack.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/sound/core/jack.c b/sound/core/jack.c
index 68b098538827..b13b22e993c0 100644
--- a/sound/core/jack.c
+++ b/sound/core/jack.c
@@ -366,7 +366,6 @@ void snd_jack_report(struct snd_jack *jack, int status)
 {
 	struct snd_jack_kctl *jack_kctl;
 #ifdef CONFIG_SND_JACK_INPUT_DEV
-	struct input_dev *idev;
 	int i;
 #endif
 
@@ -385,14 +384,14 @@ void snd_jack_report(struct snd_jack *jack, int status)
 		int testbit = SND_JACK_BTN_0 >> i;
 
 		if (jack->type & testbit)
-			input_report_key(idev, jack->key[i],
+			input_report_key(jack->input_dev, jack->key[i],
 					 status & testbit);
 	}
 
 	for (i = 0; i < ARRAY_SIZE(jack_switch_types); i++) {
 		int testbit = 1 << i;
 		if (jack->type & testbit)
-			input_report_switch(idev,
+			input_report_switch(jack->input_dev,
 					    jack_switch_types[i],
 					    status & testbit);
 	}
-- 
GitLab


From b66a36f38166c314bb7309911e6f684ec473fc06 Mon Sep 17 00:00:00 2001
From: Surapusetty Naresh Babu <quic_snareshb@quicinc.com>
Date: Wed, 6 Sep 2023 11:25:35 +0530
Subject: [PATCH 079/298] msm : Cap framerate for all Intra setting

check the framerate and cap output framerate
based on allintra encoding.

(cherry picked from commit cc1a40e4cfeb86628495118149fa917df9f53fad)

Change-Id: I1d1bf492b8701e52cc2da64e26b085bd0dbc9945
---
 msm/vidc/msm_venc.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/msm/vidc/msm_venc.c b/msm/vidc/msm_venc.c
index 2e71b924a58f..69c26c565e02 100644
--- a/msm/vidc/msm_venc.c
+++ b/msm/vidc/msm_venc.c
@@ -4628,6 +4628,13 @@ int handle_all_intra_restrictions(struct msm_vidc_inst *inst)
 	fps_max = capability->cap[CAP_ALLINTRA_MAX_FPS].max;
 	s_vpr_h(inst->sid, "%s: rc_type %u, fps %u, fps_max %u\n",
 		__func__, inst->rc_type, n_fps, fps_max);
+	if (inst->all_intra && n_fps > fps_max) {
+		inst->clk_data.frame_rate = fps_max << 16;
+		n_fps = fps_max;
+		s_vpr_h(inst->sid,
+			"%s:cap2 frame rate to %u for allintra encoding",
+			__func__, inst->clk_data.frame_rate >> 16);
+	}
 	if ((inst->rc_type != V4L2_MPEG_VIDEO_BITRATE_MODE_VBR &&
 		inst->rc_type != RATE_CONTROL_OFF &&
 		inst->rc_type != RATE_CONTROL_LOSSLESS) ||
-- 
GitLab


From a8140078096adc7475baef9594b933331408cb00 Mon Sep 17 00:00:00 2001
From: Trond Myklebust <trond.myklebust@hammerspace.com>
Date: Mon, 4 Sep 2023 12:43:58 -0400
Subject: [PATCH 080/298] NFS/pNFS: Report EINVAL errors from connect() to the
 server

[ Upstream commit dd7d7ee3ba2a70d12d02defb478790cf57d5b87b ]

With IPv6, connect() can occasionally return EINVAL if a route is
unavailable. If this happens during I/O to a data server, we want to
report it using LAYOUTERROR as an inability to connect.

Fixes: dd52128afdde ("NFSv4.1/pnfs Ensure flexfiles reports all connection related errors")
Signed-off-by: Trond Myklebust <trond.myklebust@hammerspace.com>
Signed-off-by: Anna Schumaker <Anna.Schumaker@Netapp.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 fs/nfs/flexfilelayout/flexfilelayout.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/fs/nfs/flexfilelayout/flexfilelayout.c b/fs/nfs/flexfilelayout/flexfilelayout.c
index fee421da2197..bb10f2b21cc1 100644
--- a/fs/nfs/flexfilelayout/flexfilelayout.c
+++ b/fs/nfs/flexfilelayout/flexfilelayout.c
@@ -1189,6 +1189,7 @@ static void ff_layout_io_track_ds_error(struct pnfs_layout_segment *lseg,
 		case -EPFNOSUPPORT:
 		case -EPROTONOSUPPORT:
 		case -EOPNOTSUPP:
+		case -EINVAL:
 		case -ECONNREFUSED:
 		case -ECONNRESET:
 		case -EHOSTDOWN:
-- 
GitLab


From 36b4cf8da3433090f8cdc89a4a8987bad695ab32 Mon Sep 17 00:00:00 2001
From: Hannes Reinecke <hare@suse.de>
Date: Tue, 21 Dec 2021 08:20:47 +0100
Subject: [PATCH 081/298] ata: ahci: Drop pointless VPRINTK() calls and convert
 the remaining ones

[ Upstream commit 93c7711494f47f9c829321e2a8711671b02f6e4c ]

Drop pointless VPRINTK() calls for entering and existing interrupt
routines and convert the remaining calls to dev_dbg().

Signed-off-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Stable-dep-of: 737dd811a3db ("ata: libahci: clear pending interrupt status")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/ata/ahci.c       |  4 +---
 drivers/ata/ahci_xgene.c |  4 ----
 drivers/ata/libahci.c    | 18 ++++--------------
 3 files changed, 5 insertions(+), 21 deletions(-)

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 13fb983b3413..2e4bcf2d0a51 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -694,7 +694,7 @@ static void ahci_pci_init_controller(struct ata_host *host)
 
 		/* clear port IRQ */
 		tmp = readl(port_mmio + PORT_IRQ_STAT);
-		VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
+		dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
 		if (tmp)
 			writel(tmp, port_mmio + PORT_IRQ_STAT);
 	}
@@ -1504,7 +1504,6 @@ static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
 	u32 irq_stat, irq_masked;
 	unsigned int handled = 1;
 
-	VPRINTK("ENTER\n");
 	hpriv = host->private_data;
 	mmio = hpriv->mmio;
 	irq_stat = readl(mmio + HOST_IRQ_STAT);
@@ -1521,7 +1520,6 @@ static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
 		irq_stat = readl(mmio + HOST_IRQ_STAT);
 		spin_unlock(&host->lock);
 	} while (irq_stat);
-	VPRINTK("EXIT\n");
 
 	return IRQ_RETVAL(handled);
 }
diff --git a/drivers/ata/ahci_xgene.c b/drivers/ata/ahci_xgene.c
index 7e157e1bf65e..04ad6a225014 100644
--- a/drivers/ata/ahci_xgene.c
+++ b/drivers/ata/ahci_xgene.c
@@ -601,8 +601,6 @@ static irqreturn_t xgene_ahci_irq_intr(int irq, void *dev_instance)
 	void __iomem *mmio;
 	u32 irq_stat, irq_masked;
 
-	VPRINTK("ENTER\n");
-
 	hpriv = host->private_data;
 	mmio = hpriv->mmio;
 
@@ -625,8 +623,6 @@ static irqreturn_t xgene_ahci_irq_intr(int irq, void *dev_instance)
 
 	spin_unlock(&host->lock);
 
-	VPRINTK("EXIT\n");
-
 	return IRQ_RETVAL(rc);
 }
 
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index f1153e7ba3b3..00eef92e91e5 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -1226,12 +1226,12 @@ static void ahci_port_init(struct device *dev, struct ata_port *ap,
 
 	/* clear SError */
 	tmp = readl(port_mmio + PORT_SCR_ERR);
-	VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
+	dev_dbg(dev, "PORT_SCR_ERR 0x%x\n", tmp);
 	writel(tmp, port_mmio + PORT_SCR_ERR);
 
 	/* clear port IRQ */
 	tmp = readl(port_mmio + PORT_IRQ_STAT);
-	VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
+	dev_dbg(dev, "PORT_IRQ_STAT 0x%x\n", tmp);
 	if (tmp)
 		writel(tmp, port_mmio + PORT_IRQ_STAT);
 
@@ -1262,10 +1262,10 @@ void ahci_init_controller(struct ata_host *host)
 	}
 
 	tmp = readl(mmio + HOST_CTL);
-	VPRINTK("HOST_CTL 0x%x\n", tmp);
+	dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
 	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
 	tmp = readl(mmio + HOST_CTL);
-	VPRINTK("HOST_CTL 0x%x\n", tmp);
+	dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
 }
 EXPORT_SYMBOL_GPL(ahci_init_controller);
 
@@ -1916,8 +1916,6 @@ static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
 	void __iomem *port_mmio = ahci_port_base(ap);
 	u32 status;
 
-	VPRINTK("ENTER\n");
-
 	status = readl(port_mmio + PORT_IRQ_STAT);
 	writel(status, port_mmio + PORT_IRQ_STAT);
 
@@ -1925,8 +1923,6 @@ static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
 	ahci_handle_port_interrupt(ap, port_mmio, status);
 	spin_unlock(ap->lock);
 
-	VPRINTK("EXIT\n");
-
 	return IRQ_HANDLED;
 }
 
@@ -1943,9 +1939,7 @@ u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
 		ap = host->ports[i];
 		if (ap) {
 			ahci_port_intr(ap);
-			VPRINTK("port %u\n", i);
 		} else {
-			VPRINTK("port %u (no irq)\n", i);
 			if (ata_ratelimit())
 				dev_warn(host->dev,
 					 "interrupt on disabled port %u\n", i);
@@ -1966,8 +1960,6 @@ static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
 	void __iomem *mmio;
 	u32 irq_stat, irq_masked;
 
-	VPRINTK("ENTER\n");
-
 	hpriv = host->private_data;
 	mmio = hpriv->mmio;
 
@@ -1995,8 +1987,6 @@ static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
 
 	spin_unlock(&host->lock);
 
-	VPRINTK("EXIT\n");
-
 	return IRQ_RETVAL(rc);
 }
 
-- 
GitLab


From ec6e1bc8eed3f16ec9713a2ddb2b3bc6a5a655a2 Mon Sep 17 00:00:00 2001
From: Szuying Chen <chensiying21@gmail.com>
Date: Thu, 7 Sep 2023 16:17:10 +0800
Subject: [PATCH 082/298] ata: libahci: clear pending interrupt status

[ Upstream commit 737dd811a3dbfd7edd4ad2ba5152e93d99074f83 ]

When a CRC error occurs, the HBA asserts an interrupt to indicate an
interface fatal error (PxIS.IFS). The ISR clears PxIE and PxIS, then
does error recovery. If the adapter receives another SDB FIS
with an error (PxIS.TFES) from the device before the start of the EH
recovery process, the interrupt signaling the new SDB cannot be
serviced as PxIE was cleared already. This in turn results in the HBA
inability to issue any command during the error recovery process after
setting PxCMD.ST to 1 because PxIS.TFES is still set.

According to AHCI 1.3.1 specifications section 6.2.2, fatal errors
notified by setting PxIS.HBFS, PxIS.HBDS, PxIS.IFS or PxIS.TFES will
cause the HBA to enter the ERR:Fatal state. In this state, the HBA
shall not issue any new commands.

To avoid this situation, introduce the function
ahci_port_clear_pending_irq() to clear pending interrupts before
executing a COMRESET. This follows the AHCI 1.3.1 - section 6.2.2.2
specification.

Signed-off-by: Szuying Chen <Chloe_Chen@asmedia.com.tw>
Fixes: e0bfd149973d ("[PATCH] ahci: stop engine during hard reset")
Cc: stable@vger.kernel.org
Reviewed-by: Niklas Cassel <niklas.cassel@wdc.com>
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/ata/libahci.c | 35 +++++++++++++++++++++++------------
 1 file changed, 23 insertions(+), 12 deletions(-)

diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index 00eef92e91e5..b93fad6939da 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -1210,6 +1210,26 @@ static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
 	return sprintf(buf, "%d\n", emp->blink_policy);
 }
 
+static void ahci_port_clear_pending_irq(struct ata_port *ap)
+{
+	struct ahci_host_priv *hpriv = ap->host->private_data;
+	void __iomem *port_mmio = ahci_port_base(ap);
+	u32 tmp;
+
+	/* clear SError */
+	tmp = readl(port_mmio + PORT_SCR_ERR);
+	dev_dbg(ap->host->dev, "PORT_SCR_ERR 0x%x\n", tmp);
+	writel(tmp, port_mmio + PORT_SCR_ERR);
+
+	/* clear port IRQ */
+	tmp = readl(port_mmio + PORT_IRQ_STAT);
+	dev_dbg(ap->host->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
+	if (tmp)
+		writel(tmp, port_mmio + PORT_IRQ_STAT);
+
+	writel(1 << ap->port_no, hpriv->mmio + HOST_IRQ_STAT);
+}
+
 static void ahci_port_init(struct device *dev, struct ata_port *ap,
 			   int port_no, void __iomem *mmio,
 			   void __iomem *port_mmio)
@@ -1224,18 +1244,7 @@ static void ahci_port_init(struct device *dev, struct ata_port *ap,
 	if (rc)
 		dev_warn(dev, "%s (%d)\n", emsg, rc);
 
-	/* clear SError */
-	tmp = readl(port_mmio + PORT_SCR_ERR);
-	dev_dbg(dev, "PORT_SCR_ERR 0x%x\n", tmp);
-	writel(tmp, port_mmio + PORT_SCR_ERR);
-
-	/* clear port IRQ */
-	tmp = readl(port_mmio + PORT_IRQ_STAT);
-	dev_dbg(dev, "PORT_IRQ_STAT 0x%x\n", tmp);
-	if (tmp)
-		writel(tmp, port_mmio + PORT_IRQ_STAT);
-
-	writel(1 << port_no, mmio + HOST_IRQ_STAT);
+	ahci_port_clear_pending_irq(ap);
 
 	/* mark esata ports */
 	tmp = readl(port_mmio + PORT_CMD);
@@ -1565,6 +1574,8 @@ int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
 	tf.command = ATA_BUSY;
 	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
 
+	ahci_port_clear_pending_irq(ap);
+
 	rc = sata_link_hardreset(link, timing, deadline, online,
 				 ahci_check_ready);
 
-- 
GitLab


From a477402de0e320363699f307810cb315986c4a81 Mon Sep 17 00:00:00 2001
From: Pablo Neira Ayuso <pablo@netfilter.org>
Date: Sun, 10 Sep 2023 19:04:45 +0200
Subject: [PATCH 083/298] netfilter: nf_tables: disallow element removal on
 anonymous sets

[ Upstream commit 23a3bfd4ba7acd36abf52b78605f61b21bdac216 ]

Anonymous sets need to be populated once at creation and then they are
bound to rule since 938154b93be8 ("netfilter: nf_tables: reject unbound
anonymous set before commit phase"), otherwise transaction reports
EINVAL.

Userspace does not need to delete elements of anonymous sets that are
not yet bound, reject this with EOPNOTSUPP.

From flush command path, skip anonymous sets, they are expected to be
bound already. Otherwise, EINVAL is hit at the end of this transaction
for unbound sets.

Fixes: 96518518cc41 ("netfilter: add nftables")
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/netfilter/nf_tables_api.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c
index 0ff8f1006c6b..3e3044116289 100644
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
@@ -993,8 +993,7 @@ static int nft_flush_table(struct nft_ctx *ctx)
 		if (!nft_is_active_next(ctx->net, set))
 			continue;
 
-		if (nft_set_is_anonymous(set) &&
-		    !list_empty(&set->bindings))
+		if (nft_set_is_anonymous(set))
 			continue;
 
 		err = nft_delset(ctx, set);
@@ -4902,8 +4901,10 @@ static int nf_tables_delsetelem(struct net *net, struct sock *nlsk,
 	if (IS_ERR(set))
 		return PTR_ERR(set);
 
-	if (!list_empty(&set->bindings) &&
-	    (set->flags & (NFT_SET_CONSTANT | NFT_SET_ANONYMOUS)))
+	if (nft_set_is_anonymous(set))
+		return -EOPNOTSUPP;
+
+	if (!list_empty(&set->bindings) && (set->flags & NFT_SET_CONSTANT))
 		return -EBUSY;
 
 	if (nla[NFTA_SET_ELEM_LIST_ELEMENTS] == NULL) {
-- 
GitLab


From 97ac63b13904e0f7c18d4a8eee7efd4c50832d70 Mon Sep 17 00:00:00 2001
From: Kees Cook <keescook@chromium.org>
Date: Wed, 26 May 2021 20:27:19 -0700
Subject: [PATCH 084/298] selftests/tls: Add {} to avoid static checker warning

[ Upstream commit f50688b47c5858d2ff315d020332bf4cb6710837 ]

This silences a static checker warning due to the unusual macro
construction of EXPECT_*() by adding explicit {}s around the enclosing
while loop.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Fixes: 7f657d5bf507 ("selftests: tls: add selftests for TLS sockets")
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
Stable-dep-of: c326ca98446e ("selftests: tls: swap the TX and RX sockets in some tests")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 tools/testing/selftests/net/tls.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tools/testing/selftests/net/tls.c b/tools/testing/selftests/net/tls.c
index 7549d39ccaff..43bb9eadf03e 100644
--- a/tools/testing/selftests/net/tls.c
+++ b/tools/testing/selftests/net/tls.c
@@ -202,8 +202,9 @@ TEST_F(tls, sendmsg_large)
 		EXPECT_EQ(sendmsg(self->cfd, &msg, 0), send_len);
 	}
 
-	while (recvs++ < sends)
+	while (recvs++ < sends) {
 		EXPECT_NE(recv(self->fd, mem, send_len, 0), -1);
+	}
 
 	free(mem);
 }
-- 
GitLab


From 83ff1953aca93b7bde599500834be12c860d9e83 Mon Sep 17 00:00:00 2001
From: Sabrina Dubroca <sd@queasysnail.net>
Date: Tue, 12 Sep 2023 16:16:25 +0200
Subject: [PATCH 085/298] selftests: tls: swap the TX and RX sockets in some
 tests

[ Upstream commit c326ca98446e0ae4fee43a40acf79412b74cfedb ]

tls.sendmsg_large and tls.sendmsg_multiple are trying to send through
the self->cfd socket (only configured with TLS_RX) and to receive through
the self->fd socket (only configured with TLS_TX), so they're not using
kTLS at all. Swap the sockets.

Fixes: 7f657d5bf507 ("selftests: tls: add selftests for TLS sockets")
Signed-off-by: Sabrina Dubroca <sd@queasysnail.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 tools/testing/selftests/net/tls.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tools/testing/selftests/net/tls.c b/tools/testing/selftests/net/tls.c
index 43bb9eadf03e..92adfe4df4e6 100644
--- a/tools/testing/selftests/net/tls.c
+++ b/tools/testing/selftests/net/tls.c
@@ -199,11 +199,11 @@ TEST_F(tls, sendmsg_large)
 
 		msg.msg_iov = &vec;
 		msg.msg_iovlen = 1;
-		EXPECT_EQ(sendmsg(self->cfd, &msg, 0), send_len);
+		EXPECT_EQ(sendmsg(self->fd, &msg, 0), send_len);
 	}
 
 	while (recvs++ < sends) {
-		EXPECT_NE(recv(self->fd, mem, send_len, 0), -1);
+		EXPECT_NE(recv(self->cfd, mem, send_len, 0), -1);
 	}
 
 	free(mem);
@@ -232,9 +232,9 @@ TEST_F(tls, sendmsg_multiple)
 	msg.msg_iov = vec;
 	msg.msg_iovlen = iov_len;
 
-	EXPECT_EQ(sendmsg(self->cfd, &msg, 0), total_len);
+	EXPECT_EQ(sendmsg(self->fd, &msg, 0), total_len);
 	buf = malloc(total_len);
-	EXPECT_NE(recv(self->fd, buf, total_len, 0), -1);
+	EXPECT_NE(recv(self->cfd, buf, total_len, 0), -1);
 	for (i = 0; i < iov_len; i++) {
 		EXPECT_EQ(memcmp(test_strs[i], buf + len_cmp,
 				 strlen(test_strs[i])),
-- 
GitLab


From a2cf7bd75b3992e8df68dd5fdc6499b67d45f6e0 Mon Sep 17 00:00:00 2001
From: Kyle Zeng <zengyhkyle@gmail.com>
Date: Thu, 14 Sep 2023 22:12:57 -0700
Subject: [PATCH 086/298] ipv4: fix null-deref in ipv4_link_failure

[ Upstream commit 0113d9c9d1ccc07f5a3710dac4aa24b6d711278c ]

Currently, we assume the skb is associated with a device before calling
__ip_options_compile, which is not always the case if it is re-routed by
ipvs.
When skb->dev is NULL, dev_net(skb->dev) will become null-dereference.
This patch adds a check for the edge case and switch to use the net_device
from the rtable when skb->dev is NULL.

Fixes: ed0de45a1008 ("ipv4: recompile ip options in ipv4_link_failure")
Suggested-by: David Ahern <dsahern@kernel.org>
Signed-off-by: Kyle Zeng <zengyhkyle@gmail.com>
Cc: Stephen Suryaputra <ssuryaextr@gmail.com>
Cc: Vadim Fedorenko <vfedorenko@novek.ru>
Reviewed-by: David Ahern <dsahern@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/ipv4/route.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/net/ipv4/route.c b/net/ipv4/route.c
index 57e2316529d0..9753d07bfc0b 100644
--- a/net/ipv4/route.c
+++ b/net/ipv4/route.c
@@ -1215,6 +1215,7 @@ static struct dst_entry *ipv4_dst_check(struct dst_entry *dst, u32 cookie)
 
 static void ipv4_send_dest_unreach(struct sk_buff *skb)
 {
+	struct net_device *dev;
 	struct ip_options opt;
 	int res;
 
@@ -1232,7 +1233,8 @@ static void ipv4_send_dest_unreach(struct sk_buff *skb)
 		opt.optlen = ip_hdr(skb)->ihl * 4 - sizeof(struct iphdr);
 
 		rcu_read_lock();
-		res = __ip_options_compile(dev_net(skb->dev), &opt, skb, NULL);
+		dev = skb->dev ? skb->dev : skb_rtable(skb)->dst.dev;
+		res = __ip_options_compile(dev_net(dev), &opt, skb, NULL);
 		rcu_read_unlock();
 
 		if (res)
-- 
GitLab


From 76a3e6009929776c2e0bb96f87b391d321c5fc08 Mon Sep 17 00:00:00 2001
From: Kajol Jain <kjain@linux.ibm.com>
Date: Fri, 25 Aug 2023 11:26:01 +0530
Subject: [PATCH 087/298] powerpc/perf/hv-24x7: Update domain value check

[ Upstream commit 4ff3ba4db5943cac1045e3e4a3c0463ea10f6930 ]

Valid domain value is in range 1 to HV_PERF_DOMAIN_MAX. Current code has
check for domain value greater than or equal to HV_PERF_DOMAIN_MAX. But
the check for domain value 0 is missing.

Fix this issue by adding check for domain value 0.

Before:
  # ./perf stat -v -e hv_24x7/CPM_ADJUNCT_INST,domain=0,core=1/ sleep 1
  Using CPUID 00800200
  Control descriptor is not initialized
  Error:
  The sys_perf_event_open() syscall returned with 5 (Input/output error) for
  event (hv_24x7/CPM_ADJUNCT_INST,domain=0,core=1/).
  /bin/dmesg | grep -i perf may provide additional information.

  Result from dmesg:
  [   37.819387] hv-24x7: hcall failed: [0 0x60040000 0x100 0] => ret
  0xfffffffffffffffc (-4) detail=0x2000000 failing ix=0

After:
  # ./perf stat -v -e hv_24x7/CPM_ADJUNCT_INST,domain=0,core=1/ sleep 1
  Using CPUID 00800200
  Control descriptor is not initialized
  Warning:
  hv_24x7/CPM_ADJUNCT_INST,domain=0,core=1/ event is not supported by the kernel.
  failed to read counter hv_24x7/CPM_ADJUNCT_INST,domain=0,core=1/

Fixes: ebd4a5a3ebd9 ("powerpc/perf/hv-24x7: Minor improvements")
Reported-by: Krishan Gopal Sarawast <krishang@linux.vnet.ibm.com>
Signed-off-by: Kajol Jain <kjain@linux.ibm.com>
Tested-by: Disha Goel <disgoel@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/20230825055601.360083-1-kjain@linux.ibm.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 arch/powerpc/perf/hv-24x7.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c
index 2bb798918483..e6eb2b4cf97e 100644
--- a/arch/powerpc/perf/hv-24x7.c
+++ b/arch/powerpc/perf/hv-24x7.c
@@ -1326,7 +1326,7 @@ static int h_24x7_event_init(struct perf_event *event)
 	}
 
 	domain = event_get_domain(event);
-	if (domain >= HV_PERF_DOMAIN_MAX) {
+	if (domain  == 0 || domain >= HV_PERF_DOMAIN_MAX) {
 		pr_devel("invalid domain %d\n", domain);
 		return -EINVAL;
 	}
-- 
GitLab


From 57fb8b599ec66c3dfa5467473994e663036db82a Mon Sep 17 00:00:00 2001
From: Jie Wang <wangjie125@huawei.com>
Date: Mon, 18 Sep 2023 15:48:40 +0800
Subject: [PATCH 088/298] net: hns3: add 5ms delay before clear firmware reset
 irq source

[ Upstream commit 0770063096d5da4a8e467b6e73c1646a75589628 ]

Currently the reset process in hns3 and firmware watchdog init process is
asynchronous. we think firmware watchdog initialization is completed
before hns3 clear the firmware interrupt source. However, firmware
initialization may not complete early.

so we add delay before hns3 clear firmware interrupt source and 5 ms delay
is enough to avoid second firmware reset interrupt.

Fixes: c1a81619d73a ("net: hns3: Add mailbox interrupt handling to PF driver")
Signed-off-by: Jie Wang <wangjie125@huawei.com>
Signed-off-by: Jijie Shao <shaojijie@huawei.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index 2c334b56fd42..d668d25ae7e7 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -2517,8 +2517,13 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
 				    u32 regclr)
 {
+#define HCLGE_IMP_RESET_DELAY		5
+
 	switch (event_type) {
 	case HCLGE_VECTOR0_EVENT_RST:
+		if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B))
+			mdelay(HCLGE_IMP_RESET_DELAY);
+
 		hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
 		break;
 	case HCLGE_VECTOR0_EVENT_MBX:
-- 
GitLab


From 2b601fcacd30ea9b3f777490e7c788b548389991 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Tue, 15 Nov 2022 08:53:55 +0000
Subject: [PATCH 089/298] net: add atomic_long_t to net_device_stats fields

[ Upstream commit 6c1c5097781f563b70a81683ea6fdac21637573b ]

Long standing KCSAN issues are caused by data-race around
some dev->stats changes.

Most performance critical paths already use per-cpu
variables, or per-queue ones.

It is reasonable (and more correct) to use atomic operations
for the slow paths.

This patch adds an union for each field of net_device_stats,
so that we can convert paths that are not yet protected
by a spinlock or a mutex.

netdev_stats_to_stats64() no longer has an #if BITS_PER_LONG==64

Note that the memcpy() we were using on 64bit arches
had no provision to avoid load-tearing,
while atomic_long_read() is providing the needed protection
at no cost.

Signed-off-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Stable-dep-of: 44bdb313da57 ("net: bridge: use DEV_STATS_INC()")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 include/linux/netdevice.h | 58 +++++++++++++++++++++++----------------
 include/net/dst.h         |  5 ++--
 net/core/dev.c            | 14 ++--------
 3 files changed, 40 insertions(+), 37 deletions(-)

diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index 7e9df3854420..e977118111f6 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -162,31 +162,38 @@ static inline bool dev_xmit_complete(int rc)
  *	(unsigned long) so they can be read and written atomically.
  */
 
+#define NET_DEV_STAT(FIELD)			\
+	union {					\
+		unsigned long FIELD;		\
+		atomic_long_t __##FIELD;	\
+	}
+
 struct net_device_stats {
-	unsigned long	rx_packets;
-	unsigned long	tx_packets;
-	unsigned long	rx_bytes;
-	unsigned long	tx_bytes;
-	unsigned long	rx_errors;
-	unsigned long	tx_errors;
-	unsigned long	rx_dropped;
-	unsigned long	tx_dropped;
-	unsigned long	multicast;
-	unsigned long	collisions;
-	unsigned long	rx_length_errors;
-	unsigned long	rx_over_errors;
-	unsigned long	rx_crc_errors;
-	unsigned long	rx_frame_errors;
-	unsigned long	rx_fifo_errors;
-	unsigned long	rx_missed_errors;
-	unsigned long	tx_aborted_errors;
-	unsigned long	tx_carrier_errors;
-	unsigned long	tx_fifo_errors;
-	unsigned long	tx_heartbeat_errors;
-	unsigned long	tx_window_errors;
-	unsigned long	rx_compressed;
-	unsigned long	tx_compressed;
+	NET_DEV_STAT(rx_packets);
+	NET_DEV_STAT(tx_packets);
+	NET_DEV_STAT(rx_bytes);
+	NET_DEV_STAT(tx_bytes);
+	NET_DEV_STAT(rx_errors);
+	NET_DEV_STAT(tx_errors);
+	NET_DEV_STAT(rx_dropped);
+	NET_DEV_STAT(tx_dropped);
+	NET_DEV_STAT(multicast);
+	NET_DEV_STAT(collisions);
+	NET_DEV_STAT(rx_length_errors);
+	NET_DEV_STAT(rx_over_errors);
+	NET_DEV_STAT(rx_crc_errors);
+	NET_DEV_STAT(rx_frame_errors);
+	NET_DEV_STAT(rx_fifo_errors);
+	NET_DEV_STAT(rx_missed_errors);
+	NET_DEV_STAT(tx_aborted_errors);
+	NET_DEV_STAT(tx_carrier_errors);
+	NET_DEV_STAT(tx_fifo_errors);
+	NET_DEV_STAT(tx_heartbeat_errors);
+	NET_DEV_STAT(tx_window_errors);
+	NET_DEV_STAT(rx_compressed);
+	NET_DEV_STAT(tx_compressed);
 };
+#undef NET_DEV_STAT
 
 
 #include <linux/cache.h>
@@ -4842,4 +4849,9 @@ do {								\
 #define PTYPE_HASH_SIZE	(16)
 #define PTYPE_HASH_MASK	(PTYPE_HASH_SIZE - 1)
 
+/* Note: Avoid these macros in fast path, prefer per-cpu or per-queue counters. */
+#define DEV_STATS_INC(DEV, FIELD) atomic_long_inc(&(DEV)->stats.__##FIELD)
+#define DEV_STATS_ADD(DEV, FIELD, VAL) 	\
+		atomic_long_add((VAL), &(DEV)->stats.__##FIELD)
+
 #endif	/* _LINUX_NETDEVICE_H */
diff --git a/include/net/dst.h b/include/net/dst.h
index 50258a813137..97267997601f 100644
--- a/include/net/dst.h
+++ b/include/net/dst.h
@@ -362,9 +362,8 @@ static inline void __skb_tunnel_rx(struct sk_buff *skb, struct net_device *dev,
 static inline void skb_tunnel_rx(struct sk_buff *skb, struct net_device *dev,
 				 struct net *net)
 {
-	/* TODO : stats should be SMP safe */
-	dev->stats.rx_packets++;
-	dev->stats.rx_bytes += skb->len;
+	DEV_STATS_INC(dev, rx_packets);
+	DEV_STATS_ADD(dev, rx_bytes, skb->len);
 	__skb_tunnel_rx(skb, dev, net);
 }
 
diff --git a/net/core/dev.c b/net/core/dev.c
index a9c8660a2570..3bf40c288c03 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -9035,24 +9035,16 @@ void netdev_run_todo(void)
 void netdev_stats_to_stats64(struct rtnl_link_stats64 *stats64,
 			     const struct net_device_stats *netdev_stats)
 {
-#if BITS_PER_LONG == 64
-	BUILD_BUG_ON(sizeof(*stats64) < sizeof(*netdev_stats));
-	memcpy(stats64, netdev_stats, sizeof(*netdev_stats));
-	/* zero out counters that only exist in rtnl_link_stats64 */
-	memset((char *)stats64 + sizeof(*netdev_stats), 0,
-	       sizeof(*stats64) - sizeof(*netdev_stats));
-#else
-	size_t i, n = sizeof(*netdev_stats) / sizeof(unsigned long);
-	const unsigned long *src = (const unsigned long *)netdev_stats;
+	size_t i, n = sizeof(*netdev_stats) / sizeof(atomic_long_t);
+	const atomic_long_t *src = (atomic_long_t *)netdev_stats;
 	u64 *dst = (u64 *)stats64;
 
 	BUILD_BUG_ON(n > sizeof(*stats64) / sizeof(u64));
 	for (i = 0; i < n; i++)
-		dst[i] = src[i];
+		dst[i] = atomic_long_read(&src[i]);
 	/* zero out counters that only exist in rtnl_link_stats64 */
 	memset((char *)stats64 + n * sizeof(u64), 0,
 	       sizeof(*stats64) - n * sizeof(u64));
-#endif
 }
 EXPORT_SYMBOL(netdev_stats_to_stats64);
 
-- 
GitLab


From d2346e6beb699909ca455d9d20c4e577ce900839 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Mon, 18 Sep 2023 09:13:51 +0000
Subject: [PATCH 090/298] net: bridge: use DEV_STATS_INC()

[ Upstream commit 44bdb313da57322c9b3c108eb66981c6ec6509f4 ]

syzbot/KCSAN reported data-races in br_handle_frame_finish() [1]
This function can run from multiple cpus without mutual exclusion.

Adopt SMP safe DEV_STATS_INC() to update dev->stats fields.

Handles updates to dev->stats.tx_dropped while we are at it.

[1]
BUG: KCSAN: data-race in br_handle_frame_finish / br_handle_frame_finish

read-write to 0xffff8881374b2178 of 8 bytes by interrupt on cpu 1:
br_handle_frame_finish+0xd4f/0xef0 net/bridge/br_input.c:189
br_nf_hook_thresh+0x1ed/0x220
br_nf_pre_routing_finish_ipv6+0x50f/0x540
NF_HOOK include/linux/netfilter.h:304 [inline]
br_nf_pre_routing_ipv6+0x1e3/0x2a0 net/bridge/br_netfilter_ipv6.c:178
br_nf_pre_routing+0x526/0xba0 net/bridge/br_netfilter_hooks.c:508
nf_hook_entry_hookfn include/linux/netfilter.h:144 [inline]
nf_hook_bridge_pre net/bridge/br_input.c:272 [inline]
br_handle_frame+0x4c9/0x940 net/bridge/br_input.c:417
__netif_receive_skb_core+0xa8a/0x21e0 net/core/dev.c:5417
__netif_receive_skb_one_core net/core/dev.c:5521 [inline]
__netif_receive_skb+0x57/0x1b0 net/core/dev.c:5637
process_backlog+0x21f/0x380 net/core/dev.c:5965
__napi_poll+0x60/0x3b0 net/core/dev.c:6527
napi_poll net/core/dev.c:6594 [inline]
net_rx_action+0x32b/0x750 net/core/dev.c:6727
__do_softirq+0xc1/0x265 kernel/softirq.c:553
run_ksoftirqd+0x17/0x20 kernel/softirq.c:921
smpboot_thread_fn+0x30a/0x4a0 kernel/smpboot.c:164
kthread+0x1d7/0x210 kernel/kthread.c:388
ret_from_fork+0x48/0x60 arch/x86/kernel/process.c:147
ret_from_fork_asm+0x11/0x20 arch/x86/entry/entry_64.S:304

read-write to 0xffff8881374b2178 of 8 bytes by interrupt on cpu 0:
br_handle_frame_finish+0xd4f/0xef0 net/bridge/br_input.c:189
br_nf_hook_thresh+0x1ed/0x220
br_nf_pre_routing_finish_ipv6+0x50f/0x540
NF_HOOK include/linux/netfilter.h:304 [inline]
br_nf_pre_routing_ipv6+0x1e3/0x2a0 net/bridge/br_netfilter_ipv6.c:178
br_nf_pre_routing+0x526/0xba0 net/bridge/br_netfilter_hooks.c:508
nf_hook_entry_hookfn include/linux/netfilter.h:144 [inline]
nf_hook_bridge_pre net/bridge/br_input.c:272 [inline]
br_handle_frame+0x4c9/0x940 net/bridge/br_input.c:417
__netif_receive_skb_core+0xa8a/0x21e0 net/core/dev.c:5417
__netif_receive_skb_one_core net/core/dev.c:5521 [inline]
__netif_receive_skb+0x57/0x1b0 net/core/dev.c:5637
process_backlog+0x21f/0x380 net/core/dev.c:5965
__napi_poll+0x60/0x3b0 net/core/dev.c:6527
napi_poll net/core/dev.c:6594 [inline]
net_rx_action+0x32b/0x750 net/core/dev.c:6727
__do_softirq+0xc1/0x265 kernel/softirq.c:553
do_softirq+0x5e/0x90 kernel/softirq.c:454
__local_bh_enable_ip+0x64/0x70 kernel/softirq.c:381
__raw_spin_unlock_bh include/linux/spinlock_api_smp.h:167 [inline]
_raw_spin_unlock_bh+0x36/0x40 kernel/locking/spinlock.c:210
spin_unlock_bh include/linux/spinlock.h:396 [inline]
batadv_tt_local_purge+0x1a8/0x1f0 net/batman-adv/translation-table.c:1356
batadv_tt_purge+0x2b/0x630 net/batman-adv/translation-table.c:3560
process_one_work kernel/workqueue.c:2630 [inline]
process_scheduled_works+0x5b8/0xa30 kernel/workqueue.c:2703
worker_thread+0x525/0x730 kernel/workqueue.c:2784
kthread+0x1d7/0x210 kernel/kthread.c:388
ret_from_fork+0x48/0x60 arch/x86/kernel/process.c:147
ret_from_fork_asm+0x11/0x20 arch/x86/entry/entry_64.S:304

value changed: 0x00000000000d7190 -> 0x00000000000d7191

Reported by Kernel Concurrency Sanitizer on:
CPU: 0 PID: 14848 Comm: kworker/u4:11 Not tainted 6.6.0-rc1-syzkaller-00236-gad8a69f361b9 #0

Fixes: 1c29fc4989bc ("[BRIDGE]: keep track of received multicast packets")
Reported-by: syzbot <syzkaller@googlegroups.com>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Roopa Prabhu <roopa@nvidia.com>
Cc: Nikolay Aleksandrov <razor@blackwall.org>
Cc: bridge@lists.linux-foundation.org
Acked-by: Nikolay Aleksandrov <razor@blackwall.org>
Link: https://lore.kernel.org/r/20230918091351.1356153-1-edumazet@google.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/bridge/br_forward.c | 4 ++--
 net/bridge/br_input.c   | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/net/bridge/br_forward.c b/net/bridge/br_forward.c
index 48ddc60b4fbd..c07a47d65c39 100644
--- a/net/bridge/br_forward.c
+++ b/net/bridge/br_forward.c
@@ -122,7 +122,7 @@ static int deliver_clone(const struct net_bridge_port *prev,
 
 	skb = skb_clone(skb, GFP_ATOMIC);
 	if (!skb) {
-		dev->stats.tx_dropped++;
+		DEV_STATS_INC(dev, tx_dropped);
 		return -ENOMEM;
 	}
 
@@ -261,7 +261,7 @@ static void maybe_deliver_addr(struct net_bridge_port *p, struct sk_buff *skb,
 
 	skb = skb_copy(skb, GFP_ATOMIC);
 	if (!skb) {
-		dev->stats.tx_dropped++;
+		DEV_STATS_INC(dev, tx_dropped);
 		return;
 	}
 
diff --git a/net/bridge/br_input.c b/net/bridge/br_input.c
index 14c2fdc268ea..f3938337ff87 100644
--- a/net/bridge/br_input.c
+++ b/net/bridge/br_input.c
@@ -146,12 +146,12 @@ int br_handle_frame_finish(struct net *net, struct sock *sk, struct sk_buff *skb
 			if ((mdst && mdst->host_joined) ||
 			    br_multicast_is_router(br)) {
 				local_rcv = true;
-				br->dev->stats.multicast++;
+				DEV_STATS_INC(br->dev, multicast);
 			}
 			mcast_hit = true;
 		} else {
 			local_rcv = true;
-			br->dev->stats.multicast++;
+			DEV_STATS_INC(br->dev, multicast);
 		}
 		break;
 	case BR_PKT_UNICAST:
-- 
GitLab


From a7fb47b9711101d2405b0eb1276fb1f9b9b270c7 Mon Sep 17 00:00:00 2001
From: Ziyang Xuan <william.xuanziyang@huawei.com>
Date: Mon, 18 Sep 2023 20:30:11 +0800
Subject: [PATCH 091/298] team: fix null-ptr-deref when team device type is
 changed

[ Upstream commit 492032760127251e5540a5716a70996bacf2a3fd ]

Get a null-ptr-deref bug as follows with reproducer [1].

BUG: kernel NULL pointer dereference, address: 0000000000000228
...
RIP: 0010:vlan_dev_hard_header+0x35/0x140 [8021q]
...
Call Trace:
 <TASK>
 ? __die+0x24/0x70
 ? page_fault_oops+0x82/0x150
 ? exc_page_fault+0x69/0x150
 ? asm_exc_page_fault+0x26/0x30
 ? vlan_dev_hard_header+0x35/0x140 [8021q]
 ? vlan_dev_hard_header+0x8e/0x140 [8021q]
 neigh_connected_output+0xb2/0x100
 ip6_finish_output2+0x1cb/0x520
 ? nf_hook_slow+0x43/0xc0
 ? ip6_mtu+0x46/0x80
 ip6_finish_output+0x2a/0xb0
 mld_sendpack+0x18f/0x250
 mld_ifc_work+0x39/0x160
 process_one_work+0x1e6/0x3f0
 worker_thread+0x4d/0x2f0
 ? __pfx_worker_thread+0x10/0x10
 kthread+0xe5/0x120
 ? __pfx_kthread+0x10/0x10
 ret_from_fork+0x34/0x50
 ? __pfx_kthread+0x10/0x10
 ret_from_fork_asm+0x1b/0x30

[1]
$ teamd -t team0 -d -c '{"runner": {"name": "loadbalance"}}'
$ ip link add name t-dummy type dummy
$ ip link add link t-dummy name t-dummy.100 type vlan id 100
$ ip link add name t-nlmon type nlmon
$ ip link set t-nlmon master team0
$ ip link set t-nlmon nomaster
$ ip link set t-dummy up
$ ip link set team0 up
$ ip link set t-dummy.100 down
$ ip link set t-dummy.100 master team0

When enslave a vlan device to team device and team device type is changed
from non-ether to ether, header_ops of team device is changed to
vlan_header_ops. That is incorrect and will trigger null-ptr-deref
for vlan->real_dev in vlan_dev_hard_header() because team device is not
a vlan device.

Cache eth_header_ops in team_setup(), then assign cached header_ops to
header_ops of team net device when its type is changed from non-ether
to ether to fix the bug.

Fixes: 1d76efe1577b ("team: add support for non-ethernet devices")
Suggested-by: Hangbin Liu <liuhangbin@gmail.com>
Reviewed-by: Hangbin Liu <liuhangbin@gmail.com>
Signed-off-by: Ziyang Xuan <william.xuanziyang@huawei.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Link: https://lore.kernel.org/r/20230918123011.1884401-1-william.xuanziyang@huawei.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/net/team/team.c | 10 +++++++++-
 include/linux/if_team.h |  2 ++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/net/team/team.c b/drivers/net/team/team.c
index 8b5e1ec6aabf..08f9530fd5b1 100644
--- a/drivers/net/team/team.c
+++ b/drivers/net/team/team.c
@@ -2095,7 +2095,12 @@ static const struct ethtool_ops team_ethtool_ops = {
 static void team_setup_by_port(struct net_device *dev,
 			       struct net_device *port_dev)
 {
-	dev->header_ops	= port_dev->header_ops;
+	struct team *team = netdev_priv(dev);
+
+	if (port_dev->type == ARPHRD_ETHER)
+		dev->header_ops	= team->header_ops_cache;
+	else
+		dev->header_ops	= port_dev->header_ops;
 	dev->type = port_dev->type;
 	dev->hard_header_len = port_dev->hard_header_len;
 	dev->needed_headroom = port_dev->needed_headroom;
@@ -2142,8 +2147,11 @@ static int team_dev_type_check_change(struct net_device *dev,
 
 static void team_setup(struct net_device *dev)
 {
+	struct team *team = netdev_priv(dev);
+
 	ether_setup(dev);
 	dev->max_mtu = ETH_MAX_MTU;
+	team->header_ops_cache = dev->header_ops;
 
 	dev->netdev_ops = &team_netdev_ops;
 	dev->ethtool_ops = &team_ethtool_ops;
diff --git a/include/linux/if_team.h b/include/linux/if_team.h
index ac42da56f7a2..fd32538ae705 100644
--- a/include/linux/if_team.h
+++ b/include/linux/if_team.h
@@ -196,6 +196,8 @@ struct team {
 	struct net_device *dev; /* associated netdevice */
 	struct team_pcpu_stats __percpu *pcpu_stats;
 
+	const struct header_ops *header_ops_cache;
+
 	struct mutex lock; /* used for overall locking, e.g. port lists write */
 
 	/*
-- 
GitLab


From 8be96f43cc12cb9fabf8bd9962a266c175ca92fb Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Sun, 3 Sep 2023 08:13:21 +0200
Subject: [PATCH 092/298] gpio: tb10x: Fix an error handling path in
 tb10x_gpio_probe()

[ Upstream commit b547b5e52a0587e6b25ea520bf2f9e03d00cbcb6 ]

If an error occurs after a successful irq_domain_add_linear() call, it
should be undone by a corresponding irq_domain_remove(), as already done
in the remove function.

Fixes: c6ce2b6bffe5 ("gpio: add TB10x GPIO driver")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/gpio/gpio-tb10x.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-tb10x.c b/drivers/gpio/gpio-tb10x.c
index a12cd0b5c972..1d80bae86ec9 100644
--- a/drivers/gpio/gpio-tb10x.c
+++ b/drivers/gpio/gpio-tb10x.c
@@ -246,7 +246,7 @@ static int tb10x_gpio_probe(struct platform_device *pdev)
 				handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
 				IRQ_GC_INIT_MASK_CACHE);
 		if (ret)
-			return ret;
+			goto err_remove_domain;
 
 		gc = tb10x_gpio->domain->gc->gc[0];
 		gc->reg_base                         = tb10x_gpio->base;
@@ -260,6 +260,10 @@ static int tb10x_gpio_probe(struct platform_device *pdev)
 	}
 
 	return 0;
+
+err_remove_domain:
+	irq_domain_remove(tb10x_gpio->domain);
+	return ret;
 }
 
 static int tb10x_gpio_remove(struct platform_device *pdev)
-- 
GitLab


From 6e6ebca74ec87622fc442691e24774b00ce1d5ce Mon Sep 17 00:00:00 2001
From: Xiaoke Wang <xkernel.wang@foxmail.com>
Date: Thu, 3 Mar 2022 20:39:14 +0800
Subject: [PATCH 093/298] i2c: mux: demux-pinctrl: check the return value of
 devm_kstrdup()

[ Upstream commit 7c0195fa9a9e263df204963f88a22b21688ffb66 ]

devm_kstrdup() returns pointer to allocated string on success,
NULL on failure. So it is better to check the return value of it.

Fixes: e35478eac030 ("i2c: mux: demux-pinctrl: run properly with multiple instances")
Signed-off-by: Xiaoke Wang <xkernel.wang@foxmail.com>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/i2c/muxes/i2c-demux-pinctrl.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/i2c/muxes/i2c-demux-pinctrl.c b/drivers/i2c/muxes/i2c-demux-pinctrl.c
index 1b99d0b928a0..092ebc08549f 100644
--- a/drivers/i2c/muxes/i2c-demux-pinctrl.c
+++ b/drivers/i2c/muxes/i2c-demux-pinctrl.c
@@ -244,6 +244,10 @@ static int i2c_demux_pinctrl_probe(struct platform_device *pdev)
 
 		props[i].name = devm_kstrdup(&pdev->dev, "status", GFP_KERNEL);
 		props[i].value = devm_kstrdup(&pdev->dev, "ok", GFP_KERNEL);
+		if (!props[i].name || !props[i].value) {
+			err = -ENOMEM;
+			goto err_rollback;
+		}
 		props[i].length = 3;
 
 		of_changeset_init(&priv->chan[i].chgset);
-- 
GitLab


From 8e29477d3f232f67756329ee6241901157725f74 Mon Sep 17 00:00:00 2001
From: Werner Sembach <wse@tuxedocomputers.com>
Date: Wed, 12 Jul 2023 11:56:51 -0700
Subject: [PATCH 094/298] Input: i8042 - add quirk for TUXEDO Gemini 17
 Gen1/Clevo PD70PN

[ Upstream commit eb09074bdb05ffd6bfe77f8b4a41b76ef78c997b ]

The touchpad of this device is both connected via PS/2 and i2c. This causes
strange behavior when both driver fight for control. The easy fix is to
prevent the PS/2 driver from accessing the mouse port as the full feature
set of the touchpad is only supported in the i2c interface anyway.

The strange behavior in this case is, that when an external screen is
connected and the notebook is closed, the pointer on the external screen is
moving to the lower right corner. When the notebook is opened again, this
movement stops, but the touchpad clicks are unresponsive afterwards until
reboot.

Signed-off-by: Werner Sembach <wse@tuxedocomputers.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20230607173331.851192-1-wse@tuxedocomputers.com
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/input/serio/i8042-x86ia64io.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h
index da2bf8259330..0cf9a3787326 100644
--- a/drivers/input/serio/i8042-x86ia64io.h
+++ b/drivers/input/serio/i8042-x86ia64io.h
@@ -1188,6 +1188,13 @@ static const struct dmi_system_id i8042_dmi_quirk_table[] __initconst = {
 		.driver_data = (void *)(SERIO_QUIRK_NOMUX | SERIO_QUIRK_RESET_ALWAYS |
 					SERIO_QUIRK_NOLOOP | SERIO_QUIRK_NOPNP)
 	},
+	/* See comment on TUXEDO InfinityBook S17 Gen6 / Clevo NS70MU above */
+	{
+		.matches = {
+			DMI_MATCH(DMI_BOARD_NAME, "PD5x_7xPNP_PNR_PNN_PNT"),
+		},
+		.driver_data = (void *)(SERIO_QUIRK_NOAUX)
+	},
 	{
 		.matches = {
 			DMI_MATCH(DMI_BOARD_NAME, "X170SM"),
-- 
GitLab


From f892a5b5bc10db973b4059b3b9e809cf3b598328 Mon Sep 17 00:00:00 2001
From: "Martin K. Petersen" <martin.petersen@oracle.com>
Date: Fri, 21 Dec 2018 09:33:44 -0800
Subject: [PATCH 095/298] scsi: qla2xxx: Add protection mask module parameters

[ Upstream commit 7855d2ba1172d716d96a628af7c5bafa5725ac57 ]

Allow user to selectively enable/disable DIF/DIX protection
capabilities mask.

Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Signed-off-by: Himanshu Madhani <hmadhani@marvell.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Stable-dep-of: e9105c4b7a92 ("scsi: qla2xxx: Remove unsupported ql2xenabledif option")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/scsi/qla2xxx/qla_os.c | 36 +++++++++++++++++++++++++++--------
 1 file changed, 28 insertions(+), 8 deletions(-)

diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
index 4580774b2c3e..27514d0abe84 100644
--- a/drivers/scsi/qla2xxx/qla_os.c
+++ b/drivers/scsi/qla2xxx/qla_os.c
@@ -277,6 +277,20 @@ MODULE_PARM_DESC(qla2xuseresexchforels,
 		 "Reserve 1/2 of emergency exchanges for ELS.\n"
 		 " 0 (default): disabled");
 
+int ql2xprotmask;
+module_param(ql2xprotmask, int, 0644);
+MODULE_PARM_DESC(ql2xprotmask,
+		 "Override DIF/DIX protection capabilities mask\n"
+		 "Default is 0 which sets protection mask based on "
+		 "capabilities reported by HBA firmware.\n");
+
+int ql2xprotguard;
+module_param(ql2xprotguard, int, 0644);
+MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
+		 "  0 -- Let HBA firmware decide\n"
+		 "  1 -- Force T10 CRC\n"
+		 "  2 -- Force IP checksum\n");
+
 /*
  * SCSI host template entry points
  */
@@ -3293,13 +3307,16 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
 			    "Registering for DIF/DIX type 1 and 3 protection.\n");
 			if (ql2xenabledif == 1)
 				prot = SHOST_DIX_TYPE0_PROTECTION;
-			scsi_host_set_prot(host,
-			    prot | SHOST_DIF_TYPE1_PROTECTION
-			    | SHOST_DIF_TYPE2_PROTECTION
-			    | SHOST_DIF_TYPE3_PROTECTION
-			    | SHOST_DIX_TYPE1_PROTECTION
-			    | SHOST_DIX_TYPE2_PROTECTION
-			    | SHOST_DIX_TYPE3_PROTECTION);
+			if (ql2xprotmask)
+				scsi_host_set_prot(host, ql2xprotmask);
+			else
+				scsi_host_set_prot(host,
+				    prot | SHOST_DIF_TYPE1_PROTECTION
+				    | SHOST_DIF_TYPE2_PROTECTION
+				    | SHOST_DIF_TYPE3_PROTECTION
+				    | SHOST_DIX_TYPE1_PROTECTION
+				    | SHOST_DIX_TYPE2_PROTECTION
+				    | SHOST_DIX_TYPE3_PROTECTION);
 
 			guard = SHOST_DIX_GUARD_CRC;
 
@@ -3307,7 +3324,10 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
 			    (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
 				guard |= SHOST_DIX_GUARD_IP;
 
-			scsi_host_set_guard(host, guard);
+			if (ql2xprotguard)
+				scsi_host_set_guard(host, ql2xprotguard);
+			else
+				scsi_host_set_guard(host, guard);
 		} else
 			base_vha->flags.difdix_supported = 0;
 	}
-- 
GitLab


From 75d6b6babbea0ed42cc0a60a5f8d30301b1b17fa Mon Sep 17 00:00:00 2001
From: Manish Rangankar <mrangankar@marvell.com>
Date: Mon, 21 Aug 2023 18:30:42 +0530
Subject: [PATCH 096/298] scsi: qla2xxx: Remove unsupported ql2xenabledif
 option

[ Upstream commit e9105c4b7a9208a21a9bda133707624f12ddabc2 ]

User accidently passed module parameter ql2xenabledif=1 which is
unsupported. However, driver still initialized which lead to guard tag
errors during device discovery.

Remove unsupported ql2xenabledif=1 option and validate the user input.

Cc: stable@vger.kernel.org
Signed-off-by: Manish Rangankar <mrangankar@marvell.com>
Signed-off-by: Nilesh Javali <njavali@marvell.com>
Link: https://lore.kernel.org/r/20230821130045.34850-7-njavali@marvell.com
Reviewed-by: Himanshu Madhani <himanshu.madhani@oracle.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/scsi/qla2xxx/qla_attr.c | 2 --
 drivers/scsi/qla2xxx/qla_dbg.c  | 2 +-
 drivers/scsi/qla2xxx/qla_os.c   | 9 +++++++--
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c
index 6c9095d0aa0f..9a25e92ef1ab 100644
--- a/drivers/scsi/qla2xxx/qla_attr.c
+++ b/drivers/scsi/qla2xxx/qla_attr.c
@@ -2088,8 +2088,6 @@ qla24xx_vport_create(struct fc_vport *fc_vport, bool disable)
 			vha->flags.difdix_supported = 1;
 			ql_dbg(ql_dbg_user, vha, 0x7082,
 			    "Registered for DIF/DIX type 1 and 3 protection.\n");
-			if (ql2xenabledif == 1)
-				prot = SHOST_DIX_TYPE0_PROTECTION;
 			scsi_host_set_prot(vha->host,
 			    prot | SHOST_DIF_TYPE1_PROTECTION
 			    | SHOST_DIF_TYPE2_PROTECTION
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
index 36871760a5d3..fcbadd41856c 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.c
+++ b/drivers/scsi/qla2xxx/qla_dbg.c
@@ -22,7 +22,7 @@
  * | Queue Command and IO tracing |       0x3074       | 0x300b         |
  * |                              |                    | 0x3027-0x3028  |
  * |                              |                    | 0x303d-0x3041  |
- * |                              |                    | 0x302d,0x3033  |
+ * |                              |                    | 0x302e,0x3033  |
  * |                              |                    | 0x3036,0x3038  |
  * |                              |                    | 0x303a		|
  * | DPC Thread                   |       0x4023       | 0x4002,0x4013  |
diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
index 27514d0abe84..36dca08166f2 100644
--- a/drivers/scsi/qla2xxx/qla_os.c
+++ b/drivers/scsi/qla2xxx/qla_os.c
@@ -3069,6 +3069,13 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
 	host->max_id = ha->max_fibre_devices;
 	host->cmd_per_lun = 3;
 	host->unique_id = host->host_no;
+
+	if (ql2xenabledif && ql2xenabledif != 2) {
+		ql_log(ql_log_warn, base_vha, 0x302d,
+		       "Invalid value for ql2xenabledif, resetting it to default (2)\n");
+		ql2xenabledif = 2;
+	}
+
 	if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
 		host->max_cmd_len = 32;
 	else
@@ -3305,8 +3312,6 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
 			base_vha->flags.difdix_supported = 1;
 			ql_dbg(ql_dbg_init, base_vha, 0x00f1,
 			    "Registering for DIF/DIX type 1 and 3 protection.\n");
-			if (ql2xenabledif == 1)
-				prot = SHOST_DIX_TYPE0_PROTECTION;
 			if (ql2xprotmask)
 				scsi_host_set_prot(host, ql2xprotmask);
 			else
-- 
GitLab


From c718a19fa2d7c4b8cc8f213cdc2a851a7c26ae3f Mon Sep 17 00:00:00 2001
From: Shivasharan S <shivasharan.srikanteshwara@broadcom.com>
Date: Tue, 7 May 2019 10:05:36 -0700
Subject: [PATCH 097/298] scsi: megaraid_sas: Load balance completions across
 all MSI-X

[ Upstream commit 1d15d9098ad12b0021ac5a6b851f26d1ab021e5a ]

Driver will use "reply descriptor post queues" in round robin fashion when
the combined MSI-X mode is not enabled. With this IO completions are
distributed and load balanced across all the available reply descriptor
post queues equally.

This is enabled only if combined MSI-X mode is not enabled in firmware.
This improves performance and also fixes soft lockups.

When load balancing is enabled, IRQ affinity from driver needs to be
disabled.

Signed-off-by: Kashyap Desai <kashyap.desai@broadcom.com>
Signed-off-by: Shivasharan S <shivasharan.srikanteshwara@broadcom.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Stable-dep-of: 0b0747d507bf ("scsi: megaraid_sas: Fix deadlock on firmware crashdump")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/scsi/megaraid/megaraid_sas.h        |  3 +++
 drivers/scsi/megaraid/megaraid_sas_base.c   | 22 +++++++++++++++++----
 drivers/scsi/megaraid/megaraid_sas_fusion.c | 18 +++++++++++++----
 3 files changed, 35 insertions(+), 8 deletions(-)

diff --git a/drivers/scsi/megaraid/megaraid_sas.h b/drivers/scsi/megaraid/megaraid_sas.h
index 67d356d84717..80ae48b65b60 100644
--- a/drivers/scsi/megaraid/megaraid_sas.h
+++ b/drivers/scsi/megaraid/megaraid_sas.h
@@ -2193,6 +2193,7 @@ struct megasas_instance {
 	u32 secure_jbod_support;
 	u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */
 	bool use_seqnum_jbod_fp;   /* Added for PD sequence */
+	bool smp_affinity_enable;
 	spinlock_t crashdump_lock;
 
 	struct megasas_register_set __iomem *reg_set;
@@ -2210,6 +2211,7 @@ struct megasas_instance {
 	u16 ldio_threshold;
 	u16 cur_can_queue;
 	u32 max_sectors_per_req;
+	bool msix_load_balance;
 	struct megasas_aen_event *ev;
 
 	struct megasas_cmd **cmd_list;
@@ -2246,6 +2248,7 @@ struct megasas_instance {
 	atomic_t sge_holes_type1;
 	atomic_t sge_holes_type2;
 	atomic_t sge_holes_type3;
+	atomic64_t total_io_count;
 
 	struct megasas_instance_template *instancet;
 	struct tasklet_struct isr_tasklet;
diff --git a/drivers/scsi/megaraid/megaraid_sas_base.c b/drivers/scsi/megaraid/megaraid_sas_base.c
index 8d1df03386b4..2b6b6d3deba8 100644
--- a/drivers/scsi/megaraid/megaraid_sas_base.c
+++ b/drivers/scsi/megaraid/megaraid_sas_base.c
@@ -5101,6 +5101,7 @@ megasas_setup_irqs_msix(struct megasas_instance *instance, u8 is_probe)
 					 &instance->irq_context[j]);
 			/* Retry irq register for IO_APIC*/
 			instance->msix_vectors = 0;
+			instance->msix_load_balance = false;
 			if (is_probe) {
 				pci_free_irq_vectors(instance->pdev);
 				return megasas_setup_irqs_ioapic(instance);
@@ -5109,6 +5110,7 @@ megasas_setup_irqs_msix(struct megasas_instance *instance, u8 is_probe)
 			}
 		}
 	}
+
 	return 0;
 }
 
@@ -5364,6 +5366,12 @@ static int megasas_init_fw(struct megasas_instance *instance)
 				if (rdpq_enable)
 					instance->is_rdpq = (scratch_pad_2 & MR_RDPQ_MODE_OFFSET) ?
 								1 : 0;
+
+				if (!instance->msix_combined) {
+					instance->msix_load_balance = true;
+					instance->smp_affinity_enable = false;
+				}
+
 				fw_msix_count = instance->msix_vectors;
 				/* Save 1-15 reply post index address to local memory
 				 * Index 0 is already saved from reg offset
@@ -5382,17 +5390,20 @@ static int megasas_init_fw(struct megasas_instance *instance)
 					instance->msix_vectors);
 		} else /* MFI adapters */
 			instance->msix_vectors = 1;
+
 		/* Don't bother allocating more MSI-X vectors than cpus */
 		instance->msix_vectors = min(instance->msix_vectors,
 					     (unsigned int)num_online_cpus());
-		if (smp_affinity_enable)
+		if (instance->smp_affinity_enable)
 			irq_flags |= PCI_IRQ_AFFINITY;
 		i = pci_alloc_irq_vectors(instance->pdev, 1,
 					  instance->msix_vectors, irq_flags);
-		if (i > 0)
+		if (i > 0) {
 			instance->msix_vectors = i;
-		else
+		} else {
 			instance->msix_vectors = 0;
+			instance->msix_load_balance = false;
+		}
 	}
 	/*
 	 * MSI-X host index 0 is common for all adapter.
@@ -6447,6 +6458,7 @@ static inline void megasas_init_ctrl_params(struct megasas_instance *instance)
 	INIT_LIST_HEAD(&instance->internal_reset_pending_q);
 
 	atomic_set(&instance->fw_outstanding, 0);
+	atomic64_set(&instance->total_io_count, 0);
 
 	init_waitqueue_head(&instance->int_cmd_wait_q);
 	init_waitqueue_head(&instance->abort_cmd_wait_q);
@@ -6469,6 +6481,8 @@ static inline void megasas_init_ctrl_params(struct megasas_instance *instance)
 	instance->last_time = 0;
 	instance->disableOnlineCtrlReset = 1;
 	instance->UnevenSpanSupport = 0;
+	instance->smp_affinity_enable = smp_affinity_enable ? true : false;
+	instance->msix_load_balance = false;
 
 	if (instance->adapter_type != MFI_SERIES) {
 		INIT_WORK(&instance->work_init, megasas_fusion_ocr_wq);
@@ -6818,7 +6832,7 @@ megasas_resume(struct pci_dev *pdev)
 	/* Now re-enable MSI-X */
 	if (instance->msix_vectors) {
 		irq_flags = PCI_IRQ_MSIX;
-		if (smp_affinity_enable)
+		if (instance->smp_affinity_enable)
 			irq_flags |= PCI_IRQ_AFFINITY;
 	}
 	rval = pci_alloc_irq_vectors(instance->pdev, 1,
diff --git a/drivers/scsi/megaraid/megaraid_sas_fusion.c b/drivers/scsi/megaraid/megaraid_sas_fusion.c
index b400167f9ad4..294e1a3a6adf 100644
--- a/drivers/scsi/megaraid/megaraid_sas_fusion.c
+++ b/drivers/scsi/megaraid/megaraid_sas_fusion.c
@@ -2641,8 +2641,13 @@ megasas_build_ldio_fusion(struct megasas_instance *instance,
 			fp_possible = (io_info.fpOkForIo > 0) ? true : false;
 	}
 
-	cmd->request_desc->SCSIIO.MSIxIndex =
-		instance->reply_map[raw_smp_processor_id()];
+	if (instance->msix_load_balance)
+		cmd->request_desc->SCSIIO.MSIxIndex =
+			(mega_mod64(atomic64_add_return(1, &instance->total_io_count),
+				    instance->msix_vectors));
+	else
+		cmd->request_desc->SCSIIO.MSIxIndex =
+			instance->reply_map[raw_smp_processor_id()];
 
 	praid_context = &io_request->RaidContext;
 
@@ -2969,8 +2974,13 @@ megasas_build_syspd_fusion(struct megasas_instance *instance,
 
 	cmd->request_desc->SCSIIO.DevHandle = io_request->DevHandle;
 
-	cmd->request_desc->SCSIIO.MSIxIndex =
-		instance->reply_map[raw_smp_processor_id()];
+	if (instance->msix_load_balance)
+		cmd->request_desc->SCSIIO.MSIxIndex =
+			(mega_mod64(atomic64_add_return(1, &instance->total_io_count),
+				    instance->msix_vectors));
+	else
+		cmd->request_desc->SCSIIO.MSIxIndex =
+			instance->reply_map[raw_smp_processor_id()];
 
 	if (!fp_possible) {
 		/* system pd firmware path */
-- 
GitLab


From a96d7847367b586b3f39c59edde5dc4e2cdaeb08 Mon Sep 17 00:00:00 2001
From: Junxiao Bi <junxiao.bi@oracle.com>
Date: Mon, 28 Aug 2023 15:10:18 -0700
Subject: [PATCH 098/298] scsi: megaraid_sas: Fix deadlock on firmware
 crashdump

[ Upstream commit 0b0747d507bffb827e40fc0f9fb5883fffc23477 ]

The following processes run into a deadlock. CPU 41 was waiting for CPU 29
to handle a CSD request while holding spinlock "crashdump_lock", but CPU 29
was hung by that spinlock with IRQs disabled.

  PID: 17360    TASK: ffff95c1090c5c40  CPU: 41  COMMAND: "mrdiagd"
  !# 0 [ffffb80edbf37b58] __read_once_size at ffffffff9b871a40 include/linux/compiler.h:185:0
  !# 1 [ffffb80edbf37b58] atomic_read at ffffffff9b871a40 arch/x86/include/asm/atomic.h:27:0
  !# 2 [ffffb80edbf37b58] dump_stack at ffffffff9b871a40 lib/dump_stack.c:54:0
   # 3 [ffffb80edbf37b78] csd_lock_wait_toolong at ffffffff9b131ad5 kernel/smp.c:364:0
   # 4 [ffffb80edbf37b78] __csd_lock_wait at ffffffff9b131ad5 kernel/smp.c:384:0
   # 5 [ffffb80edbf37bf8] csd_lock_wait at ffffffff9b13267a kernel/smp.c:394:0
   # 6 [ffffb80edbf37bf8] smp_call_function_many at ffffffff9b13267a kernel/smp.c:843:0
   # 7 [ffffb80edbf37c50] smp_call_function at ffffffff9b13279d kernel/smp.c:867:0
   # 8 [ffffb80edbf37c50] on_each_cpu at ffffffff9b13279d kernel/smp.c:976:0
   # 9 [ffffb80edbf37c78] flush_tlb_kernel_range at ffffffff9b085c4b arch/x86/mm/tlb.c:742:0
   #10 [ffffb80edbf37cb8] __purge_vmap_area_lazy at ffffffff9b23a1e0 mm/vmalloc.c:701:0
   #11 [ffffb80edbf37ce0] try_purge_vmap_area_lazy at ffffffff9b23a2cc mm/vmalloc.c:722:0
   #12 [ffffb80edbf37ce0] free_vmap_area_noflush at ffffffff9b23a2cc mm/vmalloc.c:754:0
   #13 [ffffb80edbf37cf8] free_unmap_vmap_area at ffffffff9b23bb3b mm/vmalloc.c:764:0
   #14 [ffffb80edbf37cf8] remove_vm_area at ffffffff9b23bb3b mm/vmalloc.c:1509:0
   #15 [ffffb80edbf37d18] __vunmap at ffffffff9b23bb8a mm/vmalloc.c:1537:0
   #16 [ffffb80edbf37d40] vfree at ffffffff9b23bc85 mm/vmalloc.c:1612:0
   #17 [ffffb80edbf37d58] megasas_free_host_crash_buffer [megaraid_sas] at ffffffffc020b7f2 drivers/scsi/megaraid/megaraid_sas_fusion.c:3932:0
   #18 [ffffb80edbf37d80] fw_crash_state_store [megaraid_sas] at ffffffffc01f804d drivers/scsi/megaraid/megaraid_sas_base.c:3291:0
   #19 [ffffb80edbf37dc0] dev_attr_store at ffffffff9b56dd7b drivers/base/core.c:758:0
   #20 [ffffb80edbf37dd0] sysfs_kf_write at ffffffff9b326acf fs/sysfs/file.c:144:0
   #21 [ffffb80edbf37de0] kernfs_fop_write at ffffffff9b325fd4 fs/kernfs/file.c:316:0
   #22 [ffffb80edbf37e20] __vfs_write at ffffffff9b29418a fs/read_write.c:480:0
   #23 [ffffb80edbf37ea8] vfs_write at ffffffff9b294462 fs/read_write.c:544:0
   #24 [ffffb80edbf37ee8] SYSC_write at ffffffff9b2946ec fs/read_write.c:590:0
   #25 [ffffb80edbf37ee8] SyS_write at ffffffff9b2946ec fs/read_write.c:582:0
   #26 [ffffb80edbf37f30] do_syscall_64 at ffffffff9b003ca9 arch/x86/entry/common.c:298:0
   #27 [ffffb80edbf37f58] entry_SYSCALL_64 at ffffffff9ba001b1 arch/x86/entry/entry_64.S:238:0

  PID: 17355    TASK: ffff95c1090c3d80  CPU: 29  COMMAND: "mrdiagd"
  !# 0 [ffffb80f2d3c7d30] __read_once_size at ffffffff9b0f2ab0 include/linux/compiler.h:185:0
  !# 1 [ffffb80f2d3c7d30] native_queued_spin_lock_slowpath at ffffffff9b0f2ab0 kernel/locking/qspinlock.c:368:0
   # 2 [ffffb80f2d3c7d58] pv_queued_spin_lock_slowpath at ffffffff9b0f244b arch/x86/include/asm/paravirt.h:674:0
   # 3 [ffffb80f2d3c7d58] queued_spin_lock_slowpath at ffffffff9b0f244b arch/x86/include/asm/qspinlock.h:53:0
   # 4 [ffffb80f2d3c7d68] queued_spin_lock at ffffffff9b8961a6 include/asm-generic/qspinlock.h:90:0
   # 5 [ffffb80f2d3c7d68] do_raw_spin_lock_flags at ffffffff9b8961a6 include/linux/spinlock.h:173:0
   # 6 [ffffb80f2d3c7d68] __raw_spin_lock_irqsave at ffffffff9b8961a6 include/linux/spinlock_api_smp.h:122:0
   # 7 [ffffb80f2d3c7d68] _raw_spin_lock_irqsave at ffffffff9b8961a6 kernel/locking/spinlock.c:160:0
   # 8 [ffffb80f2d3c7d88] fw_crash_buffer_store [megaraid_sas] at ffffffffc01f8129 drivers/scsi/megaraid/megaraid_sas_base.c:3205:0
   # 9 [ffffb80f2d3c7dc0] dev_attr_store at ffffffff9b56dd7b drivers/base/core.c:758:0
   #10 [ffffb80f2d3c7dd0] sysfs_kf_write at ffffffff9b326acf fs/sysfs/file.c:144:0
   #11 [ffffb80f2d3c7de0] kernfs_fop_write at ffffffff9b325fd4 fs/kernfs/file.c:316:0
   #12 [ffffb80f2d3c7e20] __vfs_write at ffffffff9b29418a fs/read_write.c:480:0
   #13 [ffffb80f2d3c7ea8] vfs_write at ffffffff9b294462 fs/read_write.c:544:0
   #14 [ffffb80f2d3c7ee8] SYSC_write at ffffffff9b2946ec fs/read_write.c:590:0
   #15 [ffffb80f2d3c7ee8] SyS_write at ffffffff9b2946ec fs/read_write.c:582:0
   #16 [ffffb80f2d3c7f30] do_syscall_64 at ffffffff9b003ca9 arch/x86/entry/common.c:298:0
   #17 [ffffb80f2d3c7f58] entry_SYSCALL_64 at ffffffff9ba001b1 arch/x86/entry/entry_64.S:238:0

The lock is used to synchronize different sysfs operations, it doesn't
protect any resource that will be touched by an interrupt. Consequently
it's not required to disable IRQs. Replace the spinlock with a mutex to fix
the deadlock.

Signed-off-by: Junxiao Bi <junxiao.bi@oracle.com>
Link: https://lore.kernel.org/r/20230828221018.19471-1-junxiao.bi@oracle.com
Reviewed-by: Mike Christie <michael.christie@oracle.com>
Cc: stable@vger.kernel.org
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/scsi/megaraid/megaraid_sas.h      |  2 +-
 drivers/scsi/megaraid/megaraid_sas_base.c | 21 +++++++++------------
 2 files changed, 10 insertions(+), 13 deletions(-)

diff --git a/drivers/scsi/megaraid/megaraid_sas.h b/drivers/scsi/megaraid/megaraid_sas.h
index 80ae48b65b60..0d7cca9365aa 100644
--- a/drivers/scsi/megaraid/megaraid_sas.h
+++ b/drivers/scsi/megaraid/megaraid_sas.h
@@ -2194,7 +2194,7 @@ struct megasas_instance {
 	u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */
 	bool use_seqnum_jbod_fp;   /* Added for PD sequence */
 	bool smp_affinity_enable;
-	spinlock_t crashdump_lock;
+	struct mutex crashdump_lock;
 
 	struct megasas_register_set __iomem *reg_set;
 	u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
diff --git a/drivers/scsi/megaraid/megaraid_sas_base.c b/drivers/scsi/megaraid/megaraid_sas_base.c
index 2b6b6d3deba8..bdfa36712fcc 100644
--- a/drivers/scsi/megaraid/megaraid_sas_base.c
+++ b/drivers/scsi/megaraid/megaraid_sas_base.c
@@ -3004,14 +3004,13 @@ megasas_fw_crash_buffer_store(struct device *cdev,
 	struct megasas_instance *instance =
 		(struct megasas_instance *) shost->hostdata;
 	int val = 0;
-	unsigned long flags;
 
 	if (kstrtoint(buf, 0, &val) != 0)
 		return -EINVAL;
 
-	spin_lock_irqsave(&instance->crashdump_lock, flags);
+	mutex_lock(&instance->crashdump_lock);
 	instance->fw_crash_buffer_offset = val;
-	spin_unlock_irqrestore(&instance->crashdump_lock, flags);
+	mutex_unlock(&instance->crashdump_lock);
 	return strlen(buf);
 }
 
@@ -3027,17 +3026,16 @@ megasas_fw_crash_buffer_show(struct device *cdev,
 	unsigned long dmachunk = CRASH_DMA_BUF_SIZE;
 	unsigned long chunk_left_bytes;
 	unsigned long src_addr;
-	unsigned long flags;
 	u32 buff_offset;
 
-	spin_lock_irqsave(&instance->crashdump_lock, flags);
+	mutex_lock(&instance->crashdump_lock);
 	buff_offset = instance->fw_crash_buffer_offset;
 	if (!instance->crash_dump_buf ||
 		!((instance->fw_crash_state == AVAILABLE) ||
 		(instance->fw_crash_state == COPYING))) {
 		dev_err(&instance->pdev->dev,
 			"Firmware crash dump is not available\n");
-		spin_unlock_irqrestore(&instance->crashdump_lock, flags);
+		mutex_unlock(&instance->crashdump_lock);
 		return -EINVAL;
 	}
 
@@ -3046,7 +3044,7 @@ megasas_fw_crash_buffer_show(struct device *cdev,
 	if (buff_offset > (instance->fw_crash_buffer_size * dmachunk)) {
 		dev_err(&instance->pdev->dev,
 			"Firmware crash dump offset is out of range\n");
-		spin_unlock_irqrestore(&instance->crashdump_lock, flags);
+		mutex_unlock(&instance->crashdump_lock);
 		return 0;
 	}
 
@@ -3058,7 +3056,7 @@ megasas_fw_crash_buffer_show(struct device *cdev,
 	src_addr = (unsigned long)instance->crash_buf[buff_offset / dmachunk] +
 		(buff_offset % dmachunk);
 	memcpy(buf, (void *)src_addr, size);
-	spin_unlock_irqrestore(&instance->crashdump_lock, flags);
+	mutex_unlock(&instance->crashdump_lock);
 
 	return size;
 }
@@ -3083,7 +3081,6 @@ megasas_fw_crash_state_store(struct device *cdev,
 	struct megasas_instance *instance =
 		(struct megasas_instance *) shost->hostdata;
 	int val = 0;
-	unsigned long flags;
 
 	if (kstrtoint(buf, 0, &val) != 0)
 		return -EINVAL;
@@ -3097,9 +3094,9 @@ megasas_fw_crash_state_store(struct device *cdev,
 	instance->fw_crash_state = val;
 
 	if ((val == COPIED) || (val == COPY_ERROR)) {
-		spin_lock_irqsave(&instance->crashdump_lock, flags);
+		mutex_lock(&instance->crashdump_lock);
 		megasas_free_host_crash_buffer(instance);
-		spin_unlock_irqrestore(&instance->crashdump_lock, flags);
+		mutex_unlock(&instance->crashdump_lock);
 		if (val == COPY_ERROR)
 			dev_info(&instance->pdev->dev, "application failed to "
 				"copy Firmware crash dump\n");
@@ -6463,7 +6460,7 @@ static inline void megasas_init_ctrl_params(struct megasas_instance *instance)
 	init_waitqueue_head(&instance->int_cmd_wait_q);
 	init_waitqueue_head(&instance->abort_cmd_wait_q);
 
-	spin_lock_init(&instance->crashdump_lock);
+	mutex_init(&instance->crashdump_lock);
 	spin_lock_init(&instance->mfi_pool_lock);
 	spin_lock_init(&instance->hba_lock);
 	spin_lock_init(&instance->stream_lock);
-- 
GitLab


From 77e6ea703ced87c0738626f6fe6ff1537d89262c Mon Sep 17 00:00:00 2001
From: Wang Jianchao <wangjianchao@kuaishou.com>
Date: Sat, 24 Jul 2021 15:41:20 +0800
Subject: [PATCH 099/298] ext4: remove the 'group' parameter of
 ext4_trim_extent

[ Upstream commit bd2eea8d0a6b6a9aca22f20bf74f73b71d8808af ]

Get rid of the 'group' parameter of ext4_trim_extent as we can get
it from the 'e4b'.

Reviewed-by: Andreas Dilger <adilger@dilger.ca>
Signed-off-by: Wang Jianchao <wangjianchao@kuaishou.com>
Reviewed-by: Jan Kara <jack@suse.cz>
Link: https://lore.kernel.org/r/20210724074124.25731-2-jianchao.wan9@gmail.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
Stable-dep-of: 45e4ab320c9b ("ext4: move setting of trimmed bit into ext4_try_to_trim_range()")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 fs/ext4/mballoc.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c
index 7692c12b8528..7b8109483175 100644
--- a/fs/ext4/mballoc.c
+++ b/fs/ext4/mballoc.c
@@ -5149,19 +5149,19 @@ int ext4_group_add_blocks(handle_t *handle, struct super_block *sb,
  * @sb:		super block for the file system
  * @start:	starting block of the free extent in the alloc. group
  * @count:	number of blocks to TRIM
- * @group:	alloc. group we are working with
  * @e4b:	ext4 buddy for the group
  *
  * Trim "count" blocks starting at "start" in the "group". To assure that no
  * one will allocate those blocks, mark it as used in buddy bitmap. This must
  * be called with under the group lock.
  */
-static int ext4_trim_extent(struct super_block *sb, int start, int count,
-			     ext4_group_t group, struct ext4_buddy *e4b)
+static int ext4_trim_extent(struct super_block *sb,
+		int start, int count, struct ext4_buddy *e4b)
 __releases(bitlock)
 __acquires(bitlock)
 {
 	struct ext4_free_extent ex;
+	ext4_group_t group = e4b->bd_group;
 	int ret = 0;
 
 	trace_ext4_trim_extent(sb, group, start, count);
@@ -5237,8 +5237,7 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group,
 		next = mb_find_next_bit(bitmap, max + 1, start);
 
 		if ((next - start) >= minblocks) {
-			ret = ext4_trim_extent(sb, start,
-					       next - start, group, &e4b);
+			ret = ext4_trim_extent(sb, start, next - start, &e4b);
 			if (ret && ret != -EOPNOTSUPP)
 				break;
 			ret = 0;
-- 
GitLab


From 4a050f812100857cb7e0474d01a478334831f7eb Mon Sep 17 00:00:00 2001
From: Wang Jianchao <wangjianchao@kuaishou.com>
Date: Sat, 24 Jul 2021 15:41:21 +0800
Subject: [PATCH 100/298] ext4: add new helper interface
 ext4_try_to_trim_range()

[ Upstream commit 6920b3913235f517728bb69abe9b39047a987113 ]

There is no functional change in this patch but just split the
codes, which serachs free block and does trim, into a new function
ext4_try_to_trim_range. This is preparing for the following async
backgroup discard.

Reviewed-by: Andreas Dilger <adilger@dilger.ca>
Signed-off-by: Wang Jianchao <wangjianchao@kuaishou.com>
Reviewed-by: Jan Kara <jack@suse.cz>
Link: https://lore.kernel.org/r/20210724074124.25731-3-jianchao.wan9@gmail.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
Stable-dep-of: 45e4ab320c9b ("ext4: move setting of trimmed bit into ext4_try_to_trim_range()")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 fs/ext4/mballoc.c | 102 ++++++++++++++++++++++++++--------------------
 1 file changed, 57 insertions(+), 45 deletions(-)

diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c
index 7b8109483175..51def652098b 100644
--- a/fs/ext4/mballoc.c
+++ b/fs/ext4/mballoc.c
@@ -5184,6 +5184,54 @@ __acquires(bitlock)
 	return ret;
 }
 
+static int ext4_try_to_trim_range(struct super_block *sb,
+		struct ext4_buddy *e4b, ext4_grpblk_t start,
+		ext4_grpblk_t max, ext4_grpblk_t minblocks)
+{
+	ext4_grpblk_t next, count, free_count;
+	void *bitmap;
+	int ret = 0;
+
+	bitmap = e4b->bd_bitmap;
+	start = (e4b->bd_info->bb_first_free > start) ?
+		e4b->bd_info->bb_first_free : start;
+	count = 0;
+	free_count = 0;
+
+	while (start <= max) {
+		start = mb_find_next_zero_bit(bitmap, max + 1, start);
+		if (start > max)
+			break;
+		next = mb_find_next_bit(bitmap, max + 1, start);
+
+		if ((next - start) >= minblocks) {
+			ret = ext4_trim_extent(sb, start, next - start, e4b);
+			if (ret && ret != -EOPNOTSUPP)
+				break;
+			ret = 0;
+			count += next - start;
+		}
+		free_count += next - start;
+		start = next + 1;
+
+		if (fatal_signal_pending(current)) {
+			count = -ERESTARTSYS;
+			break;
+		}
+
+		if (need_resched()) {
+			ext4_unlock_group(sb, e4b->bd_group);
+			cond_resched();
+			ext4_lock_group(sb, e4b->bd_group);
+		}
+
+		if ((e4b->bd_info->bb_free - free_count) < minblocks)
+			break;
+	}
+
+	return count;
+}
+
 /**
  * ext4_trim_all_free -- function to trim all free space in alloc. group
  * @sb:			super block for file system
@@ -5207,10 +5255,8 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group,
 		   ext4_grpblk_t start, ext4_grpblk_t max,
 		   ext4_grpblk_t minblocks)
 {
-	void *bitmap;
-	ext4_grpblk_t next, count = 0, free_count = 0;
 	struct ext4_buddy e4b;
-	int ret = 0;
+	int ret;
 
 	trace_ext4_trim_all_free(sb, group, start, max);
 
@@ -5220,57 +5266,23 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group,
 			     ret, group);
 		return ret;
 	}
-	bitmap = e4b.bd_bitmap;
 
 	ext4_lock_group(sb, group);
-	if (EXT4_MB_GRP_WAS_TRIMMED(e4b.bd_info) &&
-	    minblocks >= atomic_read(&EXT4_SB(sb)->s_last_trim_minblks))
-		goto out;
-
-	start = (e4b.bd_info->bb_first_free > start) ?
-		e4b.bd_info->bb_first_free : start;
-
-	while (start <= max) {
-		start = mb_find_next_zero_bit(bitmap, max + 1, start);
-		if (start > max)
-			break;
-		next = mb_find_next_bit(bitmap, max + 1, start);
-
-		if ((next - start) >= minblocks) {
-			ret = ext4_trim_extent(sb, start, next - start, &e4b);
-			if (ret && ret != -EOPNOTSUPP)
-				break;
-			ret = 0;
-			count += next - start;
-		}
-		free_count += next - start;
-		start = next + 1;
-
-		if (fatal_signal_pending(current)) {
-			count = -ERESTARTSYS;
-			break;
-		}
-
-		if (need_resched()) {
-			ext4_unlock_group(sb, group);
-			cond_resched();
-			ext4_lock_group(sb, group);
-		}
 
-		if ((e4b.bd_info->bb_free - free_count) < minblocks)
-			break;
+	if (!EXT4_MB_GRP_WAS_TRIMMED(e4b.bd_info) ||
+	    minblocks < atomic_read(&EXT4_SB(sb)->s_last_trim_minblks)) {
+		ret = ext4_try_to_trim_range(sb, &e4b, start, max, minblocks);
+		if (ret >= 0)
+			EXT4_MB_GRP_SET_TRIMMED(e4b.bd_info);
+	} else {
+		ret = 0;
 	}
 
-	if (!ret) {
-		ret = count;
-		EXT4_MB_GRP_SET_TRIMMED(e4b.bd_info);
-	}
-out:
 	ext4_unlock_group(sb, group);
 	ext4_mb_unload_buddy(&e4b);
 
 	ext4_debug("trimmed %d blocks in the group %d\n",
-		count, group);
+		ret, group);
 
 	return ret;
 }
-- 
GitLab


From 15bb69eaaeb24543ade36ffd07e06f690a94a263 Mon Sep 17 00:00:00 2001
From: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Date: Fri, 20 Aug 2021 14:08:53 +0200
Subject: [PATCH 101/298] ext4: scope ret locally in ext4_try_to_trim_range()

[ Upstream commit afcc4e32f606dbfb47aa7309172c89174b86e74c ]

As commit 6920b3913235 ("ext4: add new helper interface
ext4_try_to_trim_range()") moves some code into the separate function
ext4_try_to_trim_range(), the use of the variable ret within that
function is more limited and can be adjusted as well.

Scope the use of the variable ret locally and drop dead assignments.

No functional change.

Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Link: https://lore.kernel.org/r/20210820120853.23134-1-lukas.bulwahn@gmail.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
Stable-dep-of: 45e4ab320c9b ("ext4: move setting of trimmed bit into ext4_try_to_trim_range()")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 fs/ext4/mballoc.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c
index 51def652098b..58a0d2ea314b 100644
--- a/fs/ext4/mballoc.c
+++ b/fs/ext4/mballoc.c
@@ -5190,7 +5190,6 @@ static int ext4_try_to_trim_range(struct super_block *sb,
 {
 	ext4_grpblk_t next, count, free_count;
 	void *bitmap;
-	int ret = 0;
 
 	bitmap = e4b->bd_bitmap;
 	start = (e4b->bd_info->bb_first_free > start) ?
@@ -5205,10 +5204,10 @@ static int ext4_try_to_trim_range(struct super_block *sb,
 		next = mb_find_next_bit(bitmap, max + 1, start);
 
 		if ((next - start) >= minblocks) {
-			ret = ext4_trim_extent(sb, start, next - start, e4b);
+			int ret = ext4_trim_extent(sb, start, next - start, e4b);
+
 			if (ret && ret != -EOPNOTSUPP)
 				break;
-			ret = 0;
 			count += next - start;
 		}
 		free_count += next - start;
-- 
GitLab


From 03b4174c42755f1b3cf125315b26c5f8ce812bf0 Mon Sep 17 00:00:00 2001
From: Lukas Czerner <lczerner@redhat.com>
Date: Wed, 3 Nov 2021 15:51:21 +0100
Subject: [PATCH 102/298] ext4: change s_last_trim_minblks type to unsigned
 long

[ Upstream commit 2327fb2e23416cfb2795ccca2f77d4d65925be99 ]

There is no good reason for the s_last_trim_minblks to be atomic. There is
no data integrity needed and there is no real danger in setting and
reading it in a racy manner. Change it to be unsigned long, the same type
as s_clusters_per_group which is the maximum that's allowed.

Signed-off-by: Lukas Czerner <lczerner@redhat.com>
Suggested-by: Andreas Dilger <adilger@dilger.ca>
Reviewed-by: Andreas Dilger <adilger@dilger.ca>
Link: https://lore.kernel.org/r/20211103145122.17338-1-lczerner@redhat.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
Stable-dep-of: 45e4ab320c9b ("ext4: move setting of trimmed bit into ext4_try_to_trim_range()")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 fs/ext4/ext4.h    | 2 +-
 fs/ext4/mballoc.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/fs/ext4/ext4.h b/fs/ext4/ext4.h
index 909f231a387d..fa2579abea7d 100644
--- a/fs/ext4/ext4.h
+++ b/fs/ext4/ext4.h
@@ -1500,7 +1500,7 @@ struct ext4_sb_info {
 	struct task_struct *s_mmp_tsk;
 
 	/* record the last minlen when FITRIM is called. */
-	atomic_t s_last_trim_minblks;
+	unsigned long s_last_trim_minblks;
 
 	/* Reference to checksum algorithm driver via cryptoapi */
 	struct crypto_shash *s_chksum_driver;
diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c
index 58a0d2ea314b..b76e8b8f01a1 100644
--- a/fs/ext4/mballoc.c
+++ b/fs/ext4/mballoc.c
@@ -5269,7 +5269,7 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group,
 	ext4_lock_group(sb, group);
 
 	if (!EXT4_MB_GRP_WAS_TRIMMED(e4b.bd_info) ||
-	    minblocks < atomic_read(&EXT4_SB(sb)->s_last_trim_minblks)) {
+	    minblocks < EXT4_SB(sb)->s_last_trim_minblks) {
 		ret = ext4_try_to_trim_range(sb, &e4b, start, max, minblocks);
 		if (ret >= 0)
 			EXT4_MB_GRP_SET_TRIMMED(e4b.bd_info);
@@ -5378,7 +5378,7 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
 	}
 
 	if (!ret)
-		atomic_set(&EXT4_SB(sb)->s_last_trim_minblks, minlen);
+		EXT4_SB(sb)->s_last_trim_minblks = minlen;
 
 out:
 	range->len = EXT4_C2B(EXT4_SB(sb), trimmed) << sb->s_blocksize_bits;
-- 
GitLab


From 96b38975a04d18a1d0588801809c1e5c80e2eb6d Mon Sep 17 00:00:00 2001
From: Dmitry Monakhov <dmtrmonakhov@yandex-team.ru>
Date: Sun, 17 Apr 2022 20:03:15 +0300
Subject: [PATCH 103/298] ext4: mark group as trimmed only if it was fully
 scanned

[ Upstream commit d63c00ea435a5352f486c259665a4ced60399421 ]

Otherwise nonaligned fstrim calls will works inconveniently for iterative
scanners, for example:

// trim [0,16MB] for group-1, but mark full group as trimmed
fstrim  -o $((1024*1024*128)) -l $((1024*1024*16)) ./m
// handle [16MB,16MB] for group-1, do nothing because group already has the flag.
fstrim  -o $((1024*1024*144)) -l $((1024*1024*16)) ./m

[ Update function documentation for ext4_trim_all_free -- TYT ]

Signed-off-by: Dmitry Monakhov <dmtrmonakhov@yandex-team.ru>
Link: https://lore.kernel.org/r/1650214995-860245-1-git-send-email-dmtrmonakhov@yandex-team.ru
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
Cc: stable@kernel.org
Stable-dep-of: 45e4ab320c9b ("ext4: move setting of trimmed bit into ext4_try_to_trim_range()")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 fs/ext4/mballoc.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c
index b76e8b8f01a1..e926b8c3ea89 100644
--- a/fs/ext4/mballoc.c
+++ b/fs/ext4/mballoc.c
@@ -5238,6 +5238,7 @@ static int ext4_try_to_trim_range(struct super_block *sb,
  * @start:		first group block to examine
  * @max:		last group block to examine
  * @minblocks:		minimum extent block count
+ * @set_trimmed:	set the trimmed flag if at least one block is trimmed
  *
  * ext4_trim_all_free walks through group's buddy bitmap searching for free
  * extents. When the free block is found, ext4_trim_extent is called to TRIM
@@ -5252,7 +5253,7 @@ static int ext4_try_to_trim_range(struct super_block *sb,
 static ext4_grpblk_t
 ext4_trim_all_free(struct super_block *sb, ext4_group_t group,
 		   ext4_grpblk_t start, ext4_grpblk_t max,
-		   ext4_grpblk_t minblocks)
+		   ext4_grpblk_t minblocks, bool set_trimmed)
 {
 	struct ext4_buddy e4b;
 	int ret;
@@ -5271,7 +5272,7 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group,
 	if (!EXT4_MB_GRP_WAS_TRIMMED(e4b.bd_info) ||
 	    minblocks < EXT4_SB(sb)->s_last_trim_minblks) {
 		ret = ext4_try_to_trim_range(sb, &e4b, start, max, minblocks);
-		if (ret >= 0)
+		if (ret >= 0 && set_trimmed)
 			EXT4_MB_GRP_SET_TRIMMED(e4b.bd_info);
 	} else {
 		ret = 0;
@@ -5308,6 +5309,7 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
 	ext4_fsblk_t first_data_blk =
 			le32_to_cpu(EXT4_SB(sb)->s_es->s_first_data_block);
 	ext4_fsblk_t max_blks = ext4_blocks_count(EXT4_SB(sb)->s_es);
+	bool whole_group, eof = false;
 	int ret = 0;
 
 	start = range->start >> sb->s_blocksize_bits;
@@ -5326,8 +5328,10 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
 		if (minlen > EXT4_CLUSTERS_PER_GROUP(sb))
 			goto out;
 	}
-	if (end >= max_blks)
+	if (end >= max_blks - 1) {
 		end = max_blks - 1;
+		eof = true;
+	}
 	if (end <= first_data_blk)
 		goto out;
 	if (start < first_data_blk)
@@ -5341,6 +5345,7 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
 
 	/* end now represents the last cluster to discard in this group */
 	end = EXT4_CLUSTERS_PER_GROUP(sb) - 1;
+	whole_group = true;
 
 	for (group = first_group; group <= last_group; group++) {
 		grp = ext4_get_group_info(sb, group);
@@ -5357,12 +5362,13 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
 		 * change it for the last group, note that last_cluster is
 		 * already computed earlier by ext4_get_group_no_and_offset()
 		 */
-		if (group == last_group)
+		if (group == last_group) {
 			end = last_cluster;
-
+			whole_group = eof ? true : end == EXT4_CLUSTERS_PER_GROUP(sb) - 1;
+		}
 		if (grp->bb_free >= minlen) {
 			cnt = ext4_trim_all_free(sb, group, first_cluster,
-						end, minlen);
+						 end, minlen, whole_group);
 			if (cnt < 0) {
 				ret = cnt;
 				break;
-- 
GitLab


From 7f880d83f4310a469454ed103cef7292ff98ffb0 Mon Sep 17 00:00:00 2001
From: Kemeng Shi <shikemeng@huaweicloud.com>
Date: Tue, 1 Aug 2023 22:32:00 +0800
Subject: [PATCH 104/298] ext4: replace the traditional ternary conditional
 operator with with max()/min()

[ Upstream commit de8bf0e5ee7482585450357c6d4eddec8efc5cb7 ]

Replace the traditional ternary conditional operator with with max()/min()

Signed-off-by: Kemeng Shi <shikemeng@huaweicloud.com>
Reviewed-by: Ritesh Harjani (IBM) <ritesh.list@gmail.com>
Link: https://lore.kernel.org/r/20230801143204.2284343-7-shikemeng@huaweicloud.com
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
Stable-dep-of: 45e4ab320c9b ("ext4: move setting of trimmed bit into ext4_try_to_trim_range()")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 fs/ext4/mballoc.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c
index e926b8c3ea89..22da6b1143e5 100644
--- a/fs/ext4/mballoc.c
+++ b/fs/ext4/mballoc.c
@@ -5192,8 +5192,7 @@ static int ext4_try_to_trim_range(struct super_block *sb,
 	void *bitmap;
 
 	bitmap = e4b->bd_bitmap;
-	start = (e4b->bd_info->bb_first_free > start) ?
-		e4b->bd_info->bb_first_free : start;
+	start = max(e4b->bd_info->bb_first_free, start);
 	count = 0;
 	free_count = 0;
 
@@ -5413,8 +5412,7 @@ ext4_mballoc_query_range(
 
 	ext4_lock_group(sb, group);
 
-	start = (e4b.bd_info->bb_first_free > start) ?
-		e4b.bd_info->bb_first_free : start;
+	start = max(e4b.bd_info->bb_first_free, start);
 	if (end >= EXT4_CLUSTERS_PER_GROUP(sb))
 		end = EXT4_CLUSTERS_PER_GROUP(sb) - 1;
 
-- 
GitLab


From d61445f6a5c576bbe31c77afc290c428b1ac88a8 Mon Sep 17 00:00:00 2001
From: Jan Kara <jack@suse.cz>
Date: Wed, 13 Sep 2023 17:04:54 +0200
Subject: [PATCH 105/298] ext4: move setting of trimmed bit into
 ext4_try_to_trim_range()

[ Upstream commit 45e4ab320c9b5fa67b1fc3b6a9b381cfcc0c8488 ]

Currently we set the group's trimmed bit in ext4_trim_all_free() based
on return value of ext4_try_to_trim_range(). However when we will want
to abort trimming because of suspend attempt, we want to return success
from ext4_try_to_trim_range() but not set the trimmed bit. Instead
implementing awkward propagation of this information, just move setting
of trimmed bit into ext4_try_to_trim_range() when the whole group is
trimmed.

Cc: stable@kernel.org
Signed-off-by: Jan Kara <jack@suse.cz>
Link: https://lore.kernel.org/r/20230913150504.9054-1-jack@suse.cz
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 fs/ext4/mballoc.c | 46 +++++++++++++++++++++++++---------------------
 1 file changed, 25 insertions(+), 21 deletions(-)

diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c
index 22da6b1143e5..94b3bf8173e2 100644
--- a/fs/ext4/mballoc.c
+++ b/fs/ext4/mballoc.c
@@ -5184,14 +5184,27 @@ __acquires(bitlock)
 	return ret;
 }
 
+static ext4_grpblk_t ext4_last_grp_cluster(struct super_block *sb,
+					   ext4_group_t grp)
+{
+	if (grp < ext4_get_groups_count(sb))
+		return EXT4_CLUSTERS_PER_GROUP(sb) - 1;
+	return (ext4_blocks_count(EXT4_SB(sb)->s_es) -
+		ext4_group_first_block_no(sb, grp) - 1) >>
+					EXT4_CLUSTER_BITS(sb);
+}
+
 static int ext4_try_to_trim_range(struct super_block *sb,
 		struct ext4_buddy *e4b, ext4_grpblk_t start,
 		ext4_grpblk_t max, ext4_grpblk_t minblocks)
 {
 	ext4_grpblk_t next, count, free_count;
+	bool set_trimmed = false;
 	void *bitmap;
 
 	bitmap = e4b->bd_bitmap;
+	if (start == 0 && max >= ext4_last_grp_cluster(sb, e4b->bd_group))
+		set_trimmed = true;
 	start = max(e4b->bd_info->bb_first_free, start);
 	count = 0;
 	free_count = 0;
@@ -5206,16 +5219,14 @@ static int ext4_try_to_trim_range(struct super_block *sb,
 			int ret = ext4_trim_extent(sb, start, next - start, e4b);
 
 			if (ret && ret != -EOPNOTSUPP)
-				break;
+				return count;
 			count += next - start;
 		}
 		free_count += next - start;
 		start = next + 1;
 
-		if (fatal_signal_pending(current)) {
-			count = -ERESTARTSYS;
-			break;
-		}
+		if (fatal_signal_pending(current))
+			return -ERESTARTSYS;
 
 		if (need_resched()) {
 			ext4_unlock_group(sb, e4b->bd_group);
@@ -5227,6 +5238,9 @@ static int ext4_try_to_trim_range(struct super_block *sb,
 			break;
 	}
 
+	if (set_trimmed)
+		EXT4_MB_GRP_SET_TRIMMED(e4b->bd_info);
+
 	return count;
 }
 
@@ -5237,7 +5251,6 @@ static int ext4_try_to_trim_range(struct super_block *sb,
  * @start:		first group block to examine
  * @max:		last group block to examine
  * @minblocks:		minimum extent block count
- * @set_trimmed:	set the trimmed flag if at least one block is trimmed
  *
  * ext4_trim_all_free walks through group's buddy bitmap searching for free
  * extents. When the free block is found, ext4_trim_extent is called to TRIM
@@ -5252,7 +5265,7 @@ static int ext4_try_to_trim_range(struct super_block *sb,
 static ext4_grpblk_t
 ext4_trim_all_free(struct super_block *sb, ext4_group_t group,
 		   ext4_grpblk_t start, ext4_grpblk_t max,
-		   ext4_grpblk_t minblocks, bool set_trimmed)
+		   ext4_grpblk_t minblocks)
 {
 	struct ext4_buddy e4b;
 	int ret;
@@ -5269,13 +5282,10 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group,
 	ext4_lock_group(sb, group);
 
 	if (!EXT4_MB_GRP_WAS_TRIMMED(e4b.bd_info) ||
-	    minblocks < EXT4_SB(sb)->s_last_trim_minblks) {
+	    minblocks < EXT4_SB(sb)->s_last_trim_minblks)
 		ret = ext4_try_to_trim_range(sb, &e4b, start, max, minblocks);
-		if (ret >= 0 && set_trimmed)
-			EXT4_MB_GRP_SET_TRIMMED(e4b.bd_info);
-	} else {
+	else
 		ret = 0;
-	}
 
 	ext4_unlock_group(sb, group);
 	ext4_mb_unload_buddy(&e4b);
@@ -5308,7 +5318,6 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
 	ext4_fsblk_t first_data_blk =
 			le32_to_cpu(EXT4_SB(sb)->s_es->s_first_data_block);
 	ext4_fsblk_t max_blks = ext4_blocks_count(EXT4_SB(sb)->s_es);
-	bool whole_group, eof = false;
 	int ret = 0;
 
 	start = range->start >> sb->s_blocksize_bits;
@@ -5327,10 +5336,8 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
 		if (minlen > EXT4_CLUSTERS_PER_GROUP(sb))
 			goto out;
 	}
-	if (end >= max_blks - 1) {
+	if (end >= max_blks - 1)
 		end = max_blks - 1;
-		eof = true;
-	}
 	if (end <= first_data_blk)
 		goto out;
 	if (start < first_data_blk)
@@ -5344,7 +5351,6 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
 
 	/* end now represents the last cluster to discard in this group */
 	end = EXT4_CLUSTERS_PER_GROUP(sb) - 1;
-	whole_group = true;
 
 	for (group = first_group; group <= last_group; group++) {
 		grp = ext4_get_group_info(sb, group);
@@ -5361,13 +5367,11 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
 		 * change it for the last group, note that last_cluster is
 		 * already computed earlier by ext4_get_group_no_and_offset()
 		 */
-		if (group == last_group) {
+		if (group == last_group)
 			end = last_cluster;
-			whole_group = eof ? true : end == EXT4_CLUSTERS_PER_GROUP(sb) - 1;
-		}
 		if (grp->bb_free >= minlen) {
 			cnt = ext4_trim_all_free(sb, group, first_cluster,
-						 end, minlen, whole_group);
+						 end, minlen);
 			if (cnt < 0) {
 				ret = cnt;
 				break;
-- 
GitLab


From c01fc581338250585f69a7087c6e758d305a543c Mon Sep 17 00:00:00 2001
From: Jan Kara <jack@suse.cz>
Date: Wed, 13 Sep 2023 17:04:55 +0200
Subject: [PATCH 106/298] ext4: do not let fstrim block system suspend

[ Upstream commit 5229a658f6453362fbb9da6bf96872ef25a7097e ]

Len Brown has reported that system suspend sometimes fail due to
inability to freeze a task working in ext4_trim_fs() for one minute.
Trimming a large filesystem on a disk that slowly processes discard
requests can indeed take a long time. Since discard is just an advisory
call, it is perfectly fine to interrupt it at any time and the return
number of discarded blocks until that moment. Do that when we detect the
task is being frozen.

Cc: stable@kernel.org
Reported-by: Len Brown <lenb@kernel.org>
Suggested-by: Dave Chinner <david@fromorbit.com>
References: https://bugzilla.kernel.org/show_bug.cgi?id=216322
Signed-off-by: Jan Kara <jack@suse.cz>
Link: https://lore.kernel.org/r/20230913150504.9054-2-jack@suse.cz
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 fs/ext4/mballoc.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c
index 94b3bf8173e2..fb2f255c48e8 100644
--- a/fs/ext4/mballoc.c
+++ b/fs/ext4/mballoc.c
@@ -16,6 +16,7 @@
 #include <linux/slab.h>
 #include <linux/nospec.h>
 #include <linux/backing-dev.h>
+#include <linux/freezer.h>
 #include <trace/events/ext4.h>
 
 #ifdef CONFIG_EXT4_DEBUG
@@ -5194,6 +5195,11 @@ static ext4_grpblk_t ext4_last_grp_cluster(struct super_block *sb,
 					EXT4_CLUSTER_BITS(sb);
 }
 
+static bool ext4_trim_interrupted(void)
+{
+	return fatal_signal_pending(current) || freezing(current);
+}
+
 static int ext4_try_to_trim_range(struct super_block *sb,
 		struct ext4_buddy *e4b, ext4_grpblk_t start,
 		ext4_grpblk_t max, ext4_grpblk_t minblocks)
@@ -5225,8 +5231,8 @@ static int ext4_try_to_trim_range(struct super_block *sb,
 		free_count += next - start;
 		start = next + 1;
 
-		if (fatal_signal_pending(current))
-			return -ERESTARTSYS;
+		if (ext4_trim_interrupted())
+			return count;
 
 		if (need_resched()) {
 			ext4_unlock_group(sb, e4b->bd_group);
@@ -5353,6 +5359,8 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
 	end = EXT4_CLUSTERS_PER_GROUP(sb) - 1;
 
 	for (group = first_group; group <= last_group; group++) {
+		if (ext4_trim_interrupted())
+			break;
 		grp = ext4_get_group_info(sb, group);
 		/* We only do this if the grp has never been initialized */
 		if (unlikely(EXT4_MB_GRP_NEED_INIT(grp))) {
-- 
GitLab


From 9cd4fadbd20bdd595681297ec6081413d9d96d78 Mon Sep 17 00:00:00 2001
From: Christoph Hellwig <hch@lst.de>
Date: Tue, 5 Sep 2023 09:06:56 +0200
Subject: [PATCH 107/298] MIPS: Alchemy: only build mmc support helpers if
 au1xmmc is enabled

[ Upstream commit ef8f8f04a0b25e8f294b24350e8463a8d6a9ba0b ]

While commit d4a5c59a955b ("mmc: au1xmmc: force non-modular build and
remove symbol_get usage") to be built in, it can still build a kernel
without MMC support and thuse no mmc_detect_change symbol at all.

Add ifdefs to build the mmc support code in the alchemy arch code
conditional on mmc support.

Fixes: d4a5c59a955b ("mmc: au1xmmc: force non-modular build and remove symbol_get usage")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 arch/mips/alchemy/devboards/db1000.c | 4 ++++
 arch/mips/alchemy/devboards/db1200.c | 6 ++++++
 arch/mips/alchemy/devboards/db1300.c | 4 ++++
 3 files changed, 14 insertions(+)

diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c
index 6fe0f0f95ed7..548bd4db0f97 100644
--- a/arch/mips/alchemy/devboards/db1000.c
+++ b/arch/mips/alchemy/devboards/db1000.c
@@ -173,6 +173,7 @@ static struct platform_device db1x00_audio_dev = {
 
 /******************************************************************************/
 
+#ifdef CONFIG_MMC_AU1X
 static irqreturn_t db1100_mmc_cd(int irq, void *ptr)
 {
 	mmc_detect_change(ptr, msecs_to_jiffies(500));
@@ -380,6 +381,7 @@ static struct platform_device db1100_mmc1_dev = {
 	.num_resources	= ARRAY_SIZE(au1100_mmc1_res),
 	.resource	= au1100_mmc1_res,
 };
+#endif /* CONFIG_MMC_AU1X */
 
 /******************************************************************************/
 
@@ -497,9 +499,11 @@ static struct platform_device *db1000_devs[] = {
 
 static struct platform_device *db1100_devs[] = {
 	&au1100_lcd_device,
+#ifdef CONFIG_MMC_AU1X
 	&db1100_mmc0_dev,
 	&db1100_mmc1_dev,
 	&db1000_irda_dev,
+#endif
 };
 
 int __init db1000_dev_setup(void)
diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c
index ae81e05fcb2c..48840e48e79a 100644
--- a/arch/mips/alchemy/devboards/db1200.c
+++ b/arch/mips/alchemy/devboards/db1200.c
@@ -341,6 +341,7 @@ static struct platform_device db1200_ide_dev = {
 
 /**********************************************************************/
 
+#ifdef CONFIG_MMC_AU1X
 /* SD carddetects:  they're supposed to be edge-triggered, but ack
  * doesn't seem to work (CPLD Rev 2).  Instead, the screaming one
  * is disabled and its counterpart enabled.  The 200ms timeout is
@@ -601,6 +602,7 @@ static struct platform_device pb1200_mmc1_dev = {
 	.num_resources	= ARRAY_SIZE(au1200_mmc1_res),
 	.resource	= au1200_mmc1_res,
 };
+#endif /* CONFIG_MMC_AU1X */
 
 /**********************************************************************/
 
@@ -768,7 +770,9 @@ static struct platform_device db1200_audiodma_dev = {
 static struct platform_device *db1200_devs[] __initdata = {
 	NULL,		/* PSC0, selected by S6.8 */
 	&db1200_ide_dev,
+#ifdef CONFIG_MMC_AU1X
 	&db1200_mmc0_dev,
+#endif
 	&au1200_lcd_dev,
 	&db1200_eth_dev,
 	&db1200_nand_dev,
@@ -779,7 +783,9 @@ static struct platform_device *db1200_devs[] __initdata = {
 };
 
 static struct platform_device *pb1200_devs[] __initdata = {
+#ifdef CONFIG_MMC_AU1X
 	&pb1200_mmc1_dev,
+#endif
 };
 
 /* Some peripheral base addresses differ on the PB1200 */
diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c
index 0c12fbc07117..664a5a783d2c 100644
--- a/arch/mips/alchemy/devboards/db1300.c
+++ b/arch/mips/alchemy/devboards/db1300.c
@@ -448,6 +448,7 @@ static struct platform_device db1300_ide_dev = {
 
 /**********************************************************************/
 
+#ifdef CONFIG_MMC_AU1X
 static irqreturn_t db1300_mmc_cd(int irq, void *ptr)
 {
 	disable_irq_nosync(irq);
@@ -626,6 +627,7 @@ static struct platform_device db1300_sd0_dev = {
 	.resource	= au1300_sd0_res,
 	.num_resources	= ARRAY_SIZE(au1300_sd0_res),
 };
+#endif /* CONFIG_MMC_AU1X */
 
 /**********************************************************************/
 
@@ -756,8 +758,10 @@ static struct platform_device *db1300_dev[] __initdata = {
 	&db1300_5waysw_dev,
 	&db1300_nand_dev,
 	&db1300_ide_dev,
+#ifdef CONFIG_MMC_AU1X
 	&db1300_sd0_dev,
 	&db1300_sd1_dev,
+#endif
 	&db1300_lcd_dev,
 	&db1300_ac97_dev,
 	&db1300_i2s_dev,
-- 
GitLab


From 33a760a5fd86267c3b09ff9d9bfb953f10aed02c Mon Sep 17 00:00:00 2001
From: Timo Alho <talho@nvidia.com>
Date: Tue, 12 Sep 2023 14:29:50 +0300
Subject: [PATCH 108/298] clk: tegra: fix error return case for recalc_rate

[ Upstream commit a47b44fbb13f5e7a981b4515dcddc93a321ae89c ]

tegra-bpmp clocks driver makes implicit conversion of signed error
code to unsigned value in recalc_rate operation. The behavior for
recalc_rate, according to it's specification, should be that "If the
driver cannot figure out a rate for this clock, it must return 0."

Fixes: ca6f2796eef7 ("clk: tegra: Add BPMP clock driver")
Signed-off-by: Timo Alho <talho@nvidia.com>
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Link: https://lore.kernel.org/r/20230912112951.2330497-1-cyndis@kapsi.fi
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/clk/tegra/clk-bpmp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-bpmp.c b/drivers/clk/tegra/clk-bpmp.c
index 01dada561c10..3bdd3334b0f9 100644
--- a/drivers/clk/tegra/clk-bpmp.c
+++ b/drivers/clk/tegra/clk-bpmp.c
@@ -162,7 +162,7 @@ static unsigned long tegra_bpmp_clk_recalc_rate(struct clk_hw *hw,
 
 	err = tegra_bpmp_clk_transfer(clk->bpmp, &msg);
 	if (err < 0)
-		return err;
+		return 0;
 
 	return response.rate;
 }
-- 
GitLab


From 90f5eaccf9e769fbb85f4a980de6255339a26ed0 Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Mon, 11 Sep 2023 07:07:38 +0300
Subject: [PATCH 109/298] ARM: dts: ti: omap: motorola-mapphone: Fix
 abe_clkctrl warning on boot

[ Upstream commit ac08bda1569b06b7a62c7b4dd00d4c3b28ceaaec ]

Commit 0840242e8875 ("ARM: dts: Configure clock parent for pwm vibra")
attempted to fix the PWM settings but ended up causin an additional clock
reparenting error:

clk: failed to reparent abe-clkctrl:0060:24 to sys_clkin_ck: -22

Only timer9 is in the PER domain and can use the sys_clkin_ck clock source.
For timer8, the there is no sys_clkin_ck available as it's in the ABE
domain, instead it should use syc_clk_div_ck. However, for power
management, we want to use the always on sys_32k_ck instead.

Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Cc: Carl Philipp Klemm <philipp@uvos.xyz>
Cc: Merlijn Wajer <merlijn@wizzup.org>
Cc: Pavel Machek <pavel@ucw.cz>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Fixes: 0840242e8875 ("ARM: dts: Configure clock parent for pwm vibra")
Depends-on: 61978617e905 ("ARM: dts: Add minimal support for Droid Bionic xt875")
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 arch/arm/boot/dts/omap4-droid4-xt894.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
index 67d77eee9433..459720f5f558 100644
--- a/arch/arm/boot/dts/omap4-droid4-xt894.dts
+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
@@ -647,12 +647,12 @@
 /* Configure pwm clock source for timers 8 & 9 */
 &timer8 {
 	assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
-	assigned-clock-parents = <&sys_clkin_ck>;
+	assigned-clock-parents = <&sys_32k_ck>;
 };
 
 &timer9 {
 	assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
-	assigned-clock-parents = <&sys_clkin_ck>;
+	assigned-clock-parents = <&sys_32k_ck>;
 };
 
 /*
-- 
GitLab


From bcb0575e291ce1359e69cc633040beb09e8cebab Mon Sep 17 00:00:00 2001
From: Wenhua Lin <Wenhua.Lin@unisoc.com>
Date: Thu, 21 Sep 2023 20:25:27 +0800
Subject: [PATCH 110/298] gpio: pmic-eic-sprd: Add can_sleep flag for PMIC EIC
 chip

[ Upstream commit 26d9e5640d2130ee16df7b1fb6a908f460ab004c ]

The drivers uses a mutex and I2C bus access in its PMIC EIC chip
get implementation. This means these functions can sleep and the PMIC EIC
chip should set the can_sleep property to true.

This will ensure that a warning is printed when trying to get the
value from a context that potentially can't sleep.

Fixes: 348f3cde84ab ("gpio: Add Spreadtrum PMIC EIC driver support")
Signed-off-by: Wenhua Lin <Wenhua.Lin@unisoc.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/gpio/gpio-pmic-eic-sprd.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c
index 29e044ff4b17..7697cb96bf36 100644
--- a/drivers/gpio/gpio-pmic-eic-sprd.c
+++ b/drivers/gpio/gpio-pmic-eic-sprd.c
@@ -341,6 +341,7 @@ static int sprd_pmic_eic_probe(struct platform_device *pdev)
 	pmic_eic->chip.set_config = sprd_pmic_eic_set_config;
 	pmic_eic->chip.set = sprd_pmic_eic_set;
 	pmic_eic->chip.get = sprd_pmic_eic_get;
+	pmic_eic->chip.can_sleep = true;
 
 	pmic_eic->intc.name = dev_name(&pdev->dev);
 	pmic_eic->intc.irq_mask = sprd_pmic_eic_irq_mask;
-- 
GitLab


From 8da1ab77083660c996023ed1e2d0922fbb90150a Mon Sep 17 00:00:00 2001
From: Helge Deller <deller@gmx.de>
Date: Wed, 30 Aug 2023 08:10:01 +0200
Subject: [PATCH 111/298] parisc: sba: Fix compile warning wrt list of SBA
 devices

[ Upstream commit eb3255ee8f6f4691471a28fbf22db5e8901116cd ]

Fix this makecheck warning:
drivers/parisc/sba_iommu.c:98:19: warning: symbol 'sba_list'
	was not declared. Should it be static?

Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 arch/parisc/include/asm/ropes.h | 3 +++
 drivers/char/agp/parisc-agp.c   | 2 --
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/parisc/include/asm/ropes.h b/arch/parisc/include/asm/ropes.h
index 8e51c775c80a..62399c7ea94a 100644
--- a/arch/parisc/include/asm/ropes.h
+++ b/arch/parisc/include/asm/ropes.h
@@ -86,6 +86,9 @@ struct sba_device {
 	struct ioc		ioc[MAX_IOC];
 };
 
+/* list of SBA's in system, see drivers/parisc/sba_iommu.c */
+extern struct sba_device *sba_list;
+
 #define ASTRO_RUNWAY_PORT	0x582
 #define IKE_MERCED_PORT		0x803
 #define REO_MERCED_PORT		0x804
diff --git a/drivers/char/agp/parisc-agp.c b/drivers/char/agp/parisc-agp.c
index 1d5510cb6db4..1962ff624b7c 100644
--- a/drivers/char/agp/parisc-agp.c
+++ b/drivers/char/agp/parisc-agp.c
@@ -385,8 +385,6 @@ find_quicksilver(struct device *dev, void *data)
 static int __init
 parisc_agp_init(void)
 {
-	extern struct sba_device *sba_list;
-
 	int err = -1;
 	struct parisc_device *sba = NULL, *lba = NULL;
 	struct lba_device *lbadev = NULL;
-- 
GitLab


From 700f6cee4831476a187012340d72ae3c64e9b222 Mon Sep 17 00:00:00 2001
From: Helge Deller <deller@gmx.de>
Date: Wed, 30 Aug 2023 11:59:55 +0200
Subject: [PATCH 112/298] parisc: iosapic.c: Fix sparse warnings

[ Upstream commit 927c6c8aa27c284a799b8c18784e37d3373af908 ]

Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/parisc/iosapic.c         | 4 ++--
 drivers/parisc/iosapic_private.h | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/parisc/iosapic.c b/drivers/parisc/iosapic.c
index eb9137faccf7..4cc08d13b82f 100644
--- a/drivers/parisc/iosapic.c
+++ b/drivers/parisc/iosapic.c
@@ -216,9 +216,9 @@ static inline void iosapic_write(void __iomem *iosapic, unsigned int reg, u32 va
 
 static DEFINE_SPINLOCK(iosapic_lock);
 
-static inline void iosapic_eoi(void __iomem *addr, unsigned int data)
+static inline void iosapic_eoi(__le32 __iomem *addr, __le32 data)
 {
-	__raw_writel(data, addr);
+	__raw_writel((__force u32)data, addr);
 }
 
 /*
diff --git a/drivers/parisc/iosapic_private.h b/drivers/parisc/iosapic_private.h
index 6e05e30a2450..7a928c03d520 100644
--- a/drivers/parisc/iosapic_private.h
+++ b/drivers/parisc/iosapic_private.h
@@ -132,8 +132,8 @@ struct iosapic_irt {
 struct vector_info {
 	struct iosapic_info *iosapic;	/* I/O SAPIC this vector is on */
 	struct irt_entry *irte;		/* IRT entry */
-	u32 __iomem *eoi_addr;		/* precalculate EOI reg address */
-	u32	eoi_data;		/* IA64: ?       PA: swapped txn_data */
+	__le32 __iomem *eoi_addr;	/* precalculate EOI reg address */
+	__le32	eoi_data;		/* IA64: ?       PA: swapped txn_data */
 	int	txn_irq;		/* virtual IRQ number for processor */
 	ulong	txn_addr;		/* IA64: id_eid  PA: partial HPA */
 	u32	txn_data;		/* CPU interrupt bit */
-- 
GitLab


From c10f7595af65f5481b932daf8bd6998cdffd0ff7 Mon Sep 17 00:00:00 2001
From: Helge Deller <deller@gmx.de>
Date: Thu, 31 Aug 2023 22:08:32 +0200
Subject: [PATCH 113/298] parisc: drivers: Fix sparse warning

[ Upstream commit b137b9d60b8add5620a06c687a71ce18776730b0 ]

Fix "warning: directive in macro's argument list" warning.

Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 arch/parisc/kernel/drivers.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/parisc/kernel/drivers.c b/arch/parisc/kernel/drivers.c
index 01a2ed59d2f2..94037c8512f7 100644
--- a/arch/parisc/kernel/drivers.c
+++ b/arch/parisc/kernel/drivers.c
@@ -903,9 +903,9 @@ static __init void qemu_header(void)
 	pr_info("#define PARISC_MODEL \"%s\"\n\n",
 			boot_cpu_data.pdc.sys_model_name);
 
+	#define p ((unsigned long *)&boot_cpu_data.pdc.model)
 	pr_info("#define PARISC_PDC_MODEL 0x%lx, 0x%lx, 0x%lx, "
 		"0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx\n\n",
-	#define p ((unsigned long *)&boot_cpu_data.pdc.model)
 		p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]);
 	#undef p
 
-- 
GitLab


From b068b4e0cc8e09ebfb43f335f27c51a831a9de50 Mon Sep 17 00:00:00 2001
From: Helge Deller <deller@gmx.de>
Date: Thu, 31 Aug 2023 22:36:12 +0200
Subject: [PATCH 114/298] parisc: irq: Make irq_stack_union static to avoid
 sparse warning

[ Upstream commit b1bef1388c427cdad7331a9c8eb4ebbbe5b954b0 ]

Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 arch/parisc/kernel/irq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c
index c152c30c2d06..11c1505775f8 100644
--- a/arch/parisc/kernel/irq.c
+++ b/arch/parisc/kernel/irq.c
@@ -392,7 +392,7 @@ union irq_stack_union {
 	volatile unsigned int lock[1];
 };
 
-DEFINE_PER_CPU(union irq_stack_union, irq_stack_union) = {
+static DEFINE_PER_CPU(union irq_stack_union, irq_stack_union) = {
 		.slock = { 1,1,1,1 },
 	};
 #endif
-- 
GitLab


From bcf01fe7626a6fe7d06c4a99361efad1b9abc89f Mon Sep 17 00:00:00 2001
From: Zheng Yejian <zhengyejian1@huawei.com>
Date: Mon, 26 Jun 2023 08:11:44 +0800
Subject: [PATCH 115/298] selftests/ftrace: Correctly enable event in
 instance-event.tc

[ Upstream commit f4e4ada586995b17f828c6d147d1800eb1471450 ]

Function instance_set() expects to enable event 'sched_switch', so we
should set 1 to its 'enable' file.

Testcase passed after this patch:
  # ./ftracetest test.d/instances/instance-event.tc
  === Ftrace unit tests ===
  [1] Test creation and deletion of trace instances while setting an event
  [PASS]

  # of passed:  1
  # of failed:  0
  # of unresolved:  0
  # of untested:  0
  # of unsupported:  0
  # of xfailed:  0
  # of undefined(test bug):  0

Signed-off-by: Zheng Yejian <zhengyejian1@huawei.com>
Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Acked-by: Steven Rostedt (Google) <rostedt@goodmis.org>
Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 .../testing/selftests/ftrace/test.d/instances/instance-event.tc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc b/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc
index 4fa0f79144f4..9473934a573a 100644
--- a/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc
+++ b/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc
@@ -43,7 +43,7 @@ instance_read() {
 
 instance_set() {
         while :; do
-                echo 1 > foo/events/sched/sched_switch
+                echo 1 > foo/events/sched/sched_switch/enable
         done 2> /dev/null
 }
 
-- 
GitLab


From d93e05a5219a17703cfe177e50dc453a1e447904 Mon Sep 17 00:00:00 2001
From: Zheng Yejian <zhengyejian1@huawei.com>
Date: Wed, 6 Sep 2023 16:19:30 +0800
Subject: [PATCH 116/298] ring-buffer: Avoid softlockup in ring_buffer_resize()

[ Upstream commit f6bd2c92488c30ef53b5bd80c52f0a7eee9d545a ]

When user resize all trace ring buffer through file 'buffer_size_kb',
then in ring_buffer_resize(), kernel allocates buffer pages for each
cpu in a loop.

If the kernel preemption model is PREEMPT_NONE and there are many cpus
and there are many buffer pages to be allocated, it may not give up cpu
for a long time and finally cause a softlockup.

To avoid it, call cond_resched() after each cpu buffer allocation.

Link: https://lore.kernel.org/linux-trace-kernel/20230906081930.3939106-1-zhengyejian1@huawei.com

Cc: <mhiramat@kernel.org>
Signed-off-by: Zheng Yejian <zhengyejian1@huawei.com>
Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 kernel/trace/ring_buffer.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c
index c8a7de7a1d63..320aa60664dc 100644
--- a/kernel/trace/ring_buffer.c
+++ b/kernel/trace/ring_buffer.c
@@ -1753,6 +1753,8 @@ int ring_buffer_resize(struct ring_buffer *buffer, unsigned long size,
 				err = -ENOMEM;
 				goto out_err;
 			}
+
+			cond_resched();
 		}
 
 		get_online_cpus();
-- 
GitLab


From e2b7e0a9b430e4569dc860a5fc6c8fe0cc87fe31 Mon Sep 17 00:00:00 2001
From: Niklas Cassel <niklas.cassel@wdc.com>
Date: Thu, 14 Sep 2023 00:19:16 +0200
Subject: [PATCH 117/298] ata: libata-eh: do not clear ATA_PFLAG_EH_PENDING in
 ata_eh_reset()

[ Upstream commit 80cc944eca4f0baa9c381d0706f3160e491437f2 ]

ata_scsi_port_error_handler() starts off by clearing ATA_PFLAG_EH_PENDING,
before calling ap->ops->error_handler() (without holding the ap->lock).

If an error IRQ is received while ap->ops->error_handler() is running,
the irq handler will set ATA_PFLAG_EH_PENDING.

Once ap->ops->error_handler() returns, ata_scsi_port_error_handler()
checks if ATA_PFLAG_EH_PENDING is set, and if it is, another iteration
of ATA EH is performed.

The problem is that ATA_PFLAG_EH_PENDING is not only cleared by
ata_scsi_port_error_handler(), it is also cleared by ata_eh_reset().

ata_eh_reset() is called by ap->ops->error_handler(). This additional
clearing done by ata_eh_reset() breaks the whole retry logic in
ata_scsi_port_error_handler(). Thus, if an error IRQ is received while
ap->ops->error_handler() is running, the port will currently remain
frozen and will never get re-enabled.

The additional clearing in ata_eh_reset() was introduced in commit
1e641060c4b5 ("libata: clear eh_info on reset completion").

Looking at the original error report:
https://marc.info/?l=linux-ide&m=124765325828495&w=2

We can see the following happening:
[    1.074659] ata3: XXX port freeze
[    1.074700] ata3: XXX hardresetting link, stopping engine
[    1.074746] ata3: XXX flipping SControl

[    1.411471] ata3: XXX irq_stat=400040 CONN|PHY
[    1.411475] ata3: XXX port freeze

[    1.420049] ata3: XXX starting engine
[    1.420096] ata3: XXX rc=0, class=1
[    1.420142] ata3: XXX clearing IRQs for thawing
[    1.420188] ata3: XXX port thawed
[    1.420234] ata3: SATA link up 3.0 Gbps (SStatus 123 SControl 300)

We are not supposed to be able to receive an error IRQ while the port is
frozen (PxIE is set to 0, i.e. all IRQs for the port are disabled).

AHCI 1.3.1 section 10.7.1.1 First Tier (IS Register) states:
"Each bit location can be thought of as reporting a '1' if the virtual
"interrupt line" for that port is indicating it wishes to generate an
interrupt. That is, if a port has one or more interrupt status bit set,
and the enables for those status bits are set, then this bit shall be set."

Additionally, AHCI state P:ComInit clearly shows that the state machine
will only jump to P:ComInitSetIS (which sets IS.IPS(x) to '1'), if PxIE.PCE
is set to '1'. In our case, PxIE is set to 0, so IS.IPS(x) won't get set.

So IS.IPS(x) only gets set if PxIS and PxIE is set.

AHCI 1.3.1 section 10.7.1.1 First Tier (IS Register) also states:
"The bits in this register are read/write clear. It is set by the level of
the virtual interrupt line being a set, and cleared by a write of '1' from
the software."

So if IS.IPS(x) is set, you need to explicitly clear it by writing a 1 to
IS.IPS(x) for that port.

Since PxIE is cleared, the only way to get an interrupt while the port is
frozen, is if IS.IPS(x) is set, and the only way IS.IPS(x) can be set when
the port is frozen, is if it was set before the port was frozen.

However, since commit 737dd811a3db ("ata: libahci: clear pending interrupt
status"), we clear both PxIS and IS.IPS(x) after freezing the port, but
before the COMRESET, so the problem that commit 1e641060c4b5 ("libata:
clear eh_info on reset completion") fixed can no longer happen.

Thus, revert commit 1e641060c4b5 ("libata: clear eh_info on reset
completion"), so that the retry logic in ata_scsi_port_error_handler()
works once again. (The retry logic is still needed, since we can still
get an error IRQ _after_ the port has been thawed, but before
ata_scsi_port_error_handler() takes the ap->lock in order to check
if ATA_PFLAG_EH_PENDING is set.)

Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/ata/libata-eh.c | 13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c
index fcc3d7985762..73a4dd37d04a 100644
--- a/drivers/ata/libata-eh.c
+++ b/drivers/ata/libata-eh.c
@@ -2922,18 +2922,11 @@ int ata_eh_reset(struct ata_link *link, int classify,
 			postreset(slave, classes);
 	}
 
-	/*
-	 * Some controllers can't be frozen very well and may set spurious
-	 * error conditions during reset.  Clear accumulated error
-	 * information and re-thaw the port if frozen.  As reset is the
-	 * final recovery action and we cross check link onlineness against
-	 * device classification later, no hotplug event is lost by this.
-	 */
+	/* clear cached SError */
 	spin_lock_irqsave(link->ap->lock, flags);
-	memset(&link->eh_info, 0, sizeof(link->eh_info));
+	link->eh_info.serror = 0;
 	if (slave)
-		memset(&slave->eh_info, 0, sizeof(link->eh_info));
-	ap->pflags &= ~ATA_PFLAG_EH_PENDING;
+		slave->eh_info.serror = 0;
 	spin_unlock_irqrestore(link->ap->lock, flags);
 
 	if (ap->pflags & ATA_PFLAG_FROZEN)
-- 
GitLab


From 4f8c4e167ad88387de51da02a1d2d5c366025470 Mon Sep 17 00:00:00 2001
From: Stanislav Fomichev <sdf@google.com>
Date: Mon, 11 Sep 2023 12:47:30 -0700
Subject: [PATCH 118/298] bpf: Clarify error expectations from
 bpf_clone_redirect

[ Upstream commit 7cb779a6867fea00b4209bcf6de2f178a743247d ]

Commit 151e887d8ff9 ("veth: Fixing transmit return status for dropped
packets") exposed the fact that bpf_clone_redirect is capable of
returning raw NET_XMIT_XXX return codes.

This is in the conflict with its UAPI doc which says the following:
"0 on success, or a negative error in case of failure."

Update the UAPI to reflect the fact that bpf_clone_redirect can
return positive error numbers, but don't explicitly define
their meaning.

Reported-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Stanislav Fomichev <sdf@google.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Link: https://lore.kernel.org/bpf/20230911194731.286342-1-sdf@google.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 include/uapi/linux/bpf.h       | 4 +++-
 tools/include/uapi/linux/bpf.h | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h
index 6334aede67fc..91c43f375612 100644
--- a/include/uapi/linux/bpf.h
+++ b/include/uapi/linux/bpf.h
@@ -693,7 +693,9 @@ union bpf_attr {
  * 		performed again, if the helper is used in combination with
  * 		direct packet access.
  * 	Return
- * 		0 on success, or a negative error in case of failure.
+ * 		0 on success, or a negative error in case of failure. Positive
+ * 		error indicates a potential drop or congestion in the target
+ * 		device. The particular positive error codes are not defined.
  *
  * u64 bpf_get_current_pid_tgid(void)
  * 	Return
diff --git a/tools/include/uapi/linux/bpf.h b/tools/include/uapi/linux/bpf.h
index 0c30ab898e2a..37259bae1501 100644
--- a/tools/include/uapi/linux/bpf.h
+++ b/tools/include/uapi/linux/bpf.h
@@ -691,7 +691,9 @@ union bpf_attr {
  * 		performed again, if the helper is used in combination with
  * 		direct packet access.
  * 	Return
- * 		0 on success, or a negative error in case of failure.
+ * 		0 on success, or a negative error in case of failure. Positive
+ * 		error indicates a potential drop or congestion in the target
+ * 		device. The particular positive error codes are not defined.
  *
  * u64 bpf_get_current_pid_tgid(void)
  * 	Return
-- 
GitLab


From 5493dca025f7e9cc2eb6e30e8392a012fe146995 Mon Sep 17 00:00:00 2001
From: Thomas Zimmermann <tzimmermann@suse.de>
Date: Mon, 18 Sep 2023 11:03:49 +0200
Subject: [PATCH 119/298] fbdev/sh7760fb: Depend on FB=y

[ Upstream commit f75f71b2c418a27a7c05139bb27a0c83adf88d19 ]

Fix linker error if FB=m about missing fb_io_read and fb_io_write. The
linker's error message suggests that this config setting has already
been broken for other symbols.

  All errors (new ones prefixed by >>):

     sh4-linux-ld: drivers/video/fbdev/sh7760fb.o: in function `sh7760fb_probe':
     sh7760fb.c:(.text+0x374): undefined reference to `framebuffer_alloc'
     sh4-linux-ld: sh7760fb.c:(.text+0x394): undefined reference to `fb_videomode_to_var'
     sh4-linux-ld: sh7760fb.c:(.text+0x39c): undefined reference to `fb_alloc_cmap'
     sh4-linux-ld: sh7760fb.c:(.text+0x3a4): undefined reference to `register_framebuffer'
     sh4-linux-ld: sh7760fb.c:(.text+0x3ac): undefined reference to `fb_dealloc_cmap'
     sh4-linux-ld: sh7760fb.c:(.text+0x434): undefined reference to `framebuffer_release'
     sh4-linux-ld: drivers/video/fbdev/sh7760fb.o: in function `sh7760fb_remove':
     sh7760fb.c:(.text+0x800): undefined reference to `unregister_framebuffer'
     sh4-linux-ld: sh7760fb.c:(.text+0x804): undefined reference to `fb_dealloc_cmap'
     sh4-linux-ld: sh7760fb.c:(.text+0x814): undefined reference to `framebuffer_release'
  >> sh4-linux-ld: drivers/video/fbdev/sh7760fb.o:(.rodata+0xc): undefined reference to `fb_io_read'
  >> sh4-linux-ld: drivers/video/fbdev/sh7760fb.o:(.rodata+0x10): undefined reference to `fb_io_write'
     sh4-linux-ld: drivers/video/fbdev/sh7760fb.o:(.rodata+0x2c): undefined reference to `cfb_fillrect'
     sh4-linux-ld: drivers/video/fbdev/sh7760fb.o:(.rodata+0x30): undefined reference to `cfb_copyarea'
     sh4-linux-ld: drivers/video/fbdev/sh7760fb.o:(.rodata+0x34): undefined reference to `cfb_imageblit'

Suggested-by: Randy Dunlap <rdunlap@infradead.org>
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202309130632.LS04CPWu-lkp@intel.com/
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Acked-by: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20230918090400.13264-1-tzimmermann@suse.de
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/video/fbdev/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index afb0c9e4d738..8e224ee27ade 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -2085,7 +2085,7 @@ config FB_COBALT
 
 config FB_SH7760
 	bool "SH7760/SH7763/SH7720/SH7721 LCDC support"
-	depends on FB && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763 \
+	depends on FB=y && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763 \
 		|| CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721)
 	select FB_CFB_FILLRECT
 	select FB_CFB_COPYAREA
-- 
GitLab


From c81e46a880bbb9d3a144ab726be12822144c2254 Mon Sep 17 00:00:00 2001
From: Pratyush Yadav <ptyadav@amazon.de>
Date: Tue, 12 Sep 2023 17:52:49 +0200
Subject: [PATCH 120/298] nvme-pci: do not set the NUMA node of device if it
 has none

[ Upstream commit dad651b2a44eb6b201738f810254279dca29d30d ]

If a device has no NUMA node information associated with it, the driver
puts the device in node first_memory_node (say node 0). Not having a
NUMA node and being associated with node 0 are completely different
things and it makes little sense to mix the two.

Signed-off-by: Pratyush Yadav <ptyadav@amazon.de>
Signed-off-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/nvme/host/pci.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index b06d2b6bd3fe..163497ef48fd 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -2501,8 +2501,6 @@ static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	size_t alloc_size;
 
 	node = dev_to_node(&pdev->dev);
-	if (node == NUMA_NO_NODE)
-		set_dev_node(&pdev->dev, first_memory_node);
 
 	dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
 	if (!dev)
-- 
GitLab


From c1c66ab9ea5485b9f8ddf4f346f7ad4e83997cef Mon Sep 17 00:00:00 2001
From: Mika Westerberg <mika.westerberg@linux.intel.com>
Date: Mon, 2 Oct 2023 09:05:39 +0200
Subject: [PATCH 121/298] watchdog: iTCO_wdt: No need to stop the timer in
 probe

commit 1ae3e78c08209ac657c59f6f7ea21bbbd7f6a1d4 upstream.

The watchdog core can handle pinging of the watchdog before userspace
opens the device. For this reason instead of stopping the timer, just
mark it as running and let the watchdog core take care of it.

Cc: Malin Jonsson <malin.jonsson@ericsson.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20210921102900.61586-1-mika.westerberg@linux.intel.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/watchdog/iTCO_wdt.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c
index 347f0389b089..930798bac582 100644
--- a/drivers/watchdog/iTCO_wdt.c
+++ b/drivers/watchdog/iTCO_wdt.c
@@ -401,6 +401,16 @@ static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
 	return time_left;
 }
 
+static void iTCO_wdt_set_running(struct iTCO_wdt_private *p)
+{
+	u16 val;
+
+	/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is * enabled */
+	val = inw(TCO1_CNT(p));
+	if (!(val & BIT(11)))
+		set_bit(WDOG_HW_RUNNING, &p->wddev.status);
+}
+
 /*
  *	Kernel Interfaces
  */
@@ -537,8 +547,7 @@ static int iTCO_wdt_probe(struct platform_device *pdev)
 	watchdog_set_drvdata(&p->wddev, p);
 	platform_set_drvdata(pdev, p);
 
-	/* Make sure the watchdog is not running */
-	iTCO_wdt_stop(&p->wddev);
+	iTCO_wdt_set_running(p);
 
 	/* Check that the heartbeat value is within it's range;
 	   if not reset to the default */
-- 
GitLab


From dd081a3f69b16d559b31be85975e271da917e5dc Mon Sep 17 00:00:00 2001
From: Mika Westerberg <mika.westerberg@linux.intel.com>
Date: Mon, 2 Oct 2023 09:05:40 +0200
Subject: [PATCH 122/298] watchdog: iTCO_wdt: Set NO_REBOOT if the watchdog is
 not already running
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

commit ef9b7bf52c2f47f0a9bf988543c577b92c92d15e upstream.

Daniel reported that the commit 1ae3e78c0820 ("watchdog: iTCO_wdt: No
need to stop the timer in probe") makes QEMU implementation of the iTCO
watchdog not to trigger reboot anymore when NO_REBOOT flag is initially
cleared using this option (in QEMU command line):

  -global ICH9-LPC.noreboot=false

The problem with the commit is that it left the unconditional setting of
NO_REBOOT that is not cleared anymore when the kernel keeps pinging the
watchdog (as opposed to the previous code that called iTCO_wdt_stop()
that cleared it).

Fix this so that we only set NO_REBOOT if the watchdog was not initially
running.

Fixes: 1ae3e78c0820 ("watchdog: iTCO_wdt: No need to stop the timer in probe")
Reported-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Tested-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20221028062750.45451-1-mika.westerberg@linux.intel.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/watchdog/iTCO_wdt.c | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c
index 930798bac582..5ec52032117a 100644
--- a/drivers/watchdog/iTCO_wdt.c
+++ b/drivers/watchdog/iTCO_wdt.c
@@ -401,14 +401,18 @@ static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
 	return time_left;
 }
 
-static void iTCO_wdt_set_running(struct iTCO_wdt_private *p)
+/* Returns true if the watchdog was running */
+static bool iTCO_wdt_set_running(struct iTCO_wdt_private *p)
 {
 	u16 val;
 
-	/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is * enabled */
+	/* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled */
 	val = inw(TCO1_CNT(p));
-	if (!(val & BIT(11)))
+	if (!(val & BIT(11))) {
 		set_bit(WDOG_HW_RUNNING, &p->wddev.status);
+		return true;
+	}
+	return false;
 }
 
 /*
@@ -486,9 +490,6 @@ static int iTCO_wdt_probe(struct platform_device *pdev)
 		return -ENODEV;	/* Cannot reset NO_REBOOT bit */
 	}
 
-	/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
-	p->update_no_reboot_bit(p->no_reboot_priv, true);
-
 	/* The TCO logic uses the TCO_EN bit in the SMI_EN register */
 	if (!devm_request_region(dev, p->smi_res->start,
 				 resource_size(p->smi_res),
@@ -547,7 +548,13 @@ static int iTCO_wdt_probe(struct platform_device *pdev)
 	watchdog_set_drvdata(&p->wddev, p);
 	platform_set_drvdata(pdev, p);
 
-	iTCO_wdt_set_running(p);
+	if (!iTCO_wdt_set_running(p)) {
+		/*
+		 * If the watchdog was not running set NO_REBOOT now to
+		 * prevent later reboots.
+		 */
+		p->update_no_reboot_bit(p->no_reboot_priv, true);
+	}
 
 	/* Check that the heartbeat value is within it's range;
 	   if not reset to the default */
-- 
GitLab


From b17d81b94d24834d0ee038c6e216752f43b67cc9 Mon Sep 17 00:00:00 2001
From: Felix Riemann <felix.riemann@sma.de>
Date: Fri, 10 Feb 2023 13:36:44 +0100
Subject: [PATCH 123/298] net: Fix unwanted sign extension in
 netdev_stats_to_stats64()

[ Upstream commit 9b55d3f0a69af649c62cbc2633e6d695bb3cc583 ]

When converting net_device_stats to rtnl_link_stats64 sign extension
is triggered on ILP32 machines as 6c1c509778 changed the previous
"ulong -> u64" conversion to "long -> u64" by accessing the
net_device_stats fields through a (signed) atomic_long_t.

This causes for example the received bytes counter to jump to 16EiB after
having received 2^31 bytes. Casting the atomic value to "unsigned long"
beforehand converting it into u64 avoids this.

Fixes: 6c1c5097781f ("net: add atomic_long_t to net_device_stats fields")
Signed-off-by: Felix Riemann <felix.riemann@sma.de>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/core/dev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/core/dev.c b/net/core/dev.c
index 3bf40c288c03..0f9214fb36e0 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -9041,7 +9041,7 @@ void netdev_stats_to_stats64(struct rtnl_link_stats64 *stats64,
 
 	BUILD_BUG_ON(n > sizeof(*stats64) / sizeof(u64));
 	for (i = 0; i < n; i++)
-		dst[i] = atomic_long_read(&src[i]);
+		dst[i] = (unsigned long)atomic_long_read(&src[i]);
 	/* zero out counters that only exist in rtnl_link_stats64 */
 	memset((char *)stats64 + n * sizeof(u64), 0,
 	       sizeof(*stats64) - n * sizeof(u64));
-- 
GitLab


From dd1524d5d97f69c1289209eab2449b66ee77cb49 Mon Sep 17 00:00:00 2001
From: Shivasharan S <shivasharan.srikanteshwara@broadcom.com>
Date: Fri, 28 Jun 2019 02:50:39 -0700
Subject: [PATCH 124/298] scsi: megaraid_sas: Enable msix_load_balance for
 Invader and later controllers

[ Upstream commit 1175b88452cad208894412b955ee698934968aed ]

Load balancing IO completions across all available MSI-X vectors should be
enabled for Invader and later generation controllers only.  This needs to
be disabled for older controllers.  Add an adapter type check before
setting msix_load_balance flag.

Fixes: 1d15d9098ad1 ("scsi: megaraid_sas: Load balance completions across all MSI-X")
Signed-off-by: Shivasharan S <shivasharan.srikanteshwara@broadcom.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/scsi/megaraid/megaraid_sas_base.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/scsi/megaraid/megaraid_sas_base.c b/drivers/scsi/megaraid/megaraid_sas_base.c
index bdfa36712fcc..ac4800fb1a7f 100644
--- a/drivers/scsi/megaraid/megaraid_sas_base.c
+++ b/drivers/scsi/megaraid/megaraid_sas_base.c
@@ -5364,7 +5364,8 @@ static int megasas_init_fw(struct megasas_instance *instance)
 					instance->is_rdpq = (scratch_pad_2 & MR_RDPQ_MODE_OFFSET) ?
 								1 : 0;
 
-				if (!instance->msix_combined) {
+				if (instance->adapter_type >= INVADER_SERIES &&
+				    !instance->msix_combined) {
 					instance->msix_load_balance = true;
 					instance->smp_affinity_enable = false;
 				}
-- 
GitLab


From db01c2bf6b934c26ef204b087e776b21285edacd Mon Sep 17 00:00:00 2001
From: Vishal Goel <vishal.goel@samsung.com>
Date: Thu, 28 Sep 2023 18:51:36 -0700
Subject: [PATCH 125/298] Smack:- Use overlay inode label in
 smack_inode_copy_up()

commit 387ef964460f14fe1c1ea29aba70e22731ea7cf7 upstream.

Currently in "smack_inode_copy_up()" function, process label is
changed with the label on parent inode. Due to which,
process is assigned directory label and whatever file or directory
created by the process are also getting directory label
which is wrong label.

Changes has been done to use label of overlay inode instead
of parent inode.

Signed-off-by: Vishal Goel <vishal.goel@samsung.com>
Signed-off-by: Casey Schaufler <casey@schaufler-ca.com>
[4.19: adjusted for the lack of helper functions]
Fixes: d6d80cb57be4 ("Smack: Base support for overlayfs")
Signed-off-by: Munehisa Kamata <kamatam@amazon.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 security/smack/smack_lsm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c
index 4f65d953fe31..a09a9c6bbdf6 100644
--- a/security/smack/smack_lsm.c
+++ b/security/smack/smack_lsm.c
@@ -4612,7 +4612,7 @@ static int smack_inode_copy_up(struct dentry *dentry, struct cred **new)
 	/*
 	 * Get label from overlay inode and set it in create_sid
 	 */
-	isp = d_inode(dentry->d_parent)->i_security;
+	isp = d_inode(dentry)->i_security;
 	skp = isp->smk_inode;
 	tsp->smk_task = skp;
 	*new = new_creds;
-- 
GitLab


From 24416f2ac0604b1db19d956ffd07d0040c920de4 Mon Sep 17 00:00:00 2001
From: Roberto Sassu <roberto.sassu@huawei.com>
Date: Thu, 28 Sep 2023 18:51:37 -0700
Subject: [PATCH 126/298] smack: Retrieve transmuting information in
 smack_inode_getsecurity()

commit 3a3d8fce31a49363cc31880dce5e3b0617c9c38b upstream.

Enhance smack_inode_getsecurity() to retrieve the value for
SMACK64TRANSMUTE from the inode security blob, similarly to SMACK64.

This helps to display accurate values in the situation where the security
labels come from mount options and not from xattrs.

Signed-off-by: Roberto Sassu <roberto.sassu@huawei.com>
Signed-off-by: Casey Schaufler <casey@schaufler-ca.com>
[4.19: adjusted for the lack of helper functions]
Fixes: d6d80cb57be4 ("Smack: Base support for overlayfs")
Signed-off-by: Munehisa Kamata <kamatam@amazon.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 security/smack/smack_lsm.c | 22 ++++++++++++++++++----
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c
index a09a9c6bbdf6..db729834d8ba 100644
--- a/security/smack/smack_lsm.c
+++ b/security/smack/smack_lsm.c
@@ -1490,10 +1490,19 @@ static int smack_inode_getsecurity(struct inode *inode,
 	struct super_block *sbp;
 	struct inode *ip = (struct inode *)inode;
 	struct smack_known *isp;
+	struct inode_smack *ispp;
+	size_t label_len;
+	char *label = NULL;
 
-	if (strcmp(name, XATTR_SMACK_SUFFIX) == 0)
+	if (strcmp(name, XATTR_SMACK_SUFFIX) == 0) {
 		isp = smk_of_inode(inode);
-	else {
+	} else if (strcmp(name, XATTR_SMACK_TRANSMUTE) == 0) {
+		ispp = inode->i_security;
+		if (ispp->smk_flags & SMK_INODE_TRANSMUTE)
+			label = TRANS_TRUE;
+		else
+			label = "";
+	} else {
 		/*
 		 * The rest of the Smack xattrs are only on sockets.
 		 */
@@ -1515,13 +1524,18 @@ static int smack_inode_getsecurity(struct inode *inode,
 			return -EOPNOTSUPP;
 	}
 
+	if (!label)
+		label = isp->smk_known;
+
+	label_len = strlen(label);
+
 	if (alloc) {
-		*buffer = kstrdup(isp->smk_known, GFP_KERNEL);
+		*buffer = kstrdup(label, GFP_KERNEL);
 		if (*buffer == NULL)
 			return -ENOMEM;
 	}
 
-	return strlen(isp->smk_known);
+	return label_len;
 }
 
 
-- 
GitLab


From 3307dd6c104e83a2f9d4a703ae06c8a8d9c11467 Mon Sep 17 00:00:00 2001
From: Roberto Sassu <roberto.sassu@huawei.com>
Date: Thu, 28 Sep 2023 18:51:38 -0700
Subject: [PATCH 127/298] smack: Record transmuting in smk_transmuted

commit 2c085f3a8f23c9b444e8b99d93c15d7ce870fc4e upstream.

smack_dentry_create_files_as() determines whether transmuting should occur
based on the label of the parent directory the new inode will be added to,
and not the label of the directory where it is created.

This helps for example to do transmuting on overlayfs, since the latter
first creates the inode in the working directory, and then moves it to the
correct destination.

However, despite smack_dentry_create_files_as() provides the correct label,
smack_inode_init_security() does not know from passed information whether
or not transmuting occurred. Without this information,
smack_inode_init_security() cannot set SMK_INODE_CHANGED in smk_flags,
which will result in the SMACK64TRANSMUTE xattr not being set in
smack_d_instantiate().

Thus, add the smk_transmuted field to the task_smack structure, and set it
in smack_dentry_create_files_as() to smk_task if transmuting occurred. If
smk_task is equal to smk_transmuted in smack_inode_init_security(), act as
if transmuting was successful but without taking the label from the parent
directory (the inode label was already set correctly from the current
credentials in smack_inode_alloc_security()).

Signed-off-by: Roberto Sassu <roberto.sassu@huawei.com>
Signed-off-by: Casey Schaufler <casey@schaufler-ca.com>
[4.19: adjusted for the lack of helper functions]
Fixes: d6d80cb57be4 ("Smack: Base support for overlayfs")
Signed-off-by: Munehisa Kamata <kamatam@amazon.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 security/smack/smack.h     |  1 +
 security/smack/smack_lsm.c | 41 +++++++++++++++++++++++++++-----------
 2 files changed, 30 insertions(+), 12 deletions(-)

diff --git a/security/smack/smack.h b/security/smack/smack.h
index f7db791fb566..62aa4bc25426 100644
--- a/security/smack/smack.h
+++ b/security/smack/smack.h
@@ -120,6 +120,7 @@ struct inode_smack {
 struct task_smack {
 	struct smack_known	*smk_task;	/* label for access control */
 	struct smack_known	*smk_forked;	/* label when forked */
+	struct smack_known	*smk_transmuted;/* label when transmuted */
 	struct list_head	smk_rules;	/* per task access rules */
 	struct mutex		smk_rules_lock;	/* lock for the rules */
 	struct list_head	smk_relabel;	/* transit allowed labels */
diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c
index db729834d8ba..266eb8ca3381 100644
--- a/security/smack/smack_lsm.c
+++ b/security/smack/smack_lsm.c
@@ -1032,8 +1032,9 @@ static int smack_inode_init_security(struct inode *inode, struct inode *dir,
 				     const struct qstr *qstr, const char **name,
 				     void **value, size_t *len)
 {
+	struct task_smack *tsp = current_security();
 	struct inode_smack *issp = inode->i_security;
-	struct smack_known *skp = smk_of_current();
+	struct smack_known *skp = smk_of_task(tsp);
 	struct smack_known *isp = smk_of_inode(inode);
 	struct smack_known *dsp = smk_of_inode(dir);
 	int may;
@@ -1042,20 +1043,34 @@ static int smack_inode_init_security(struct inode *inode, struct inode *dir,
 		*name = XATTR_SMACK_SUFFIX;
 
 	if (value && len) {
-		rcu_read_lock();
-		may = smk_access_entry(skp->smk_known, dsp->smk_known,
-				       &skp->smk_rules);
-		rcu_read_unlock();
+		/*
+		 * If equal, transmuting already occurred in
+		 * smack_dentry_create_files_as(). No need to check again.
+		 */
+		if (tsp->smk_task != tsp->smk_transmuted) {
+			rcu_read_lock();
+			may = smk_access_entry(skp->smk_known, dsp->smk_known,
+					       &skp->smk_rules);
+			rcu_read_unlock();
+		}
 
 		/*
-		 * If the access rule allows transmutation and
-		 * the directory requests transmutation then
-		 * by all means transmute.
+		 * In addition to having smk_task equal to smk_transmuted,
+		 * if the access rule allows transmutation and the directory
+		 * requests transmutation then by all means transmute.
 		 * Mark the inode as changed.
 		 */
-		if (may > 0 && ((may & MAY_TRANSMUTE) != 0) &&
-		    smk_inode_transmutable(dir)) {
-			isp = dsp;
+		if ((tsp->smk_task == tsp->smk_transmuted) ||
+		    (may > 0 && ((may & MAY_TRANSMUTE) != 0) &&
+		     smk_inode_transmutable(dir))) {
+			/*
+			 * The caller of smack_dentry_create_files_as()
+			 * should have overridden the current cred, so the
+			 * inode label was already set correctly in
+			 * smack_inode_alloc_security().
+			 */
+			if (tsp->smk_task != tsp->smk_transmuted)
+				isp = dsp;
 			issp->smk_flags |= SMK_INODE_CHANGED;
 		}
 
@@ -4677,8 +4692,10 @@ static int smack_dentry_create_files_as(struct dentry *dentry, int mode,
 		 * providing access is transmuting use the containing
 		 * directory label instead of the process label.
 		 */
-		if (may > 0 && (may & MAY_TRANSMUTE))
+		if (may > 0 && (may & MAY_TRANSMUTE)) {
 			ntsp->smk_task = isp->smk_inode;
+			ntsp->smk_transmuted = ntsp->smk_task;
+		}
 	}
 	return 0;
 }
-- 
GitLab


From c334650150c29234b0923476f51573ae1b2f252a Mon Sep 17 00:00:00 2001
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Date: Fri, 1 Sep 2023 01:25:55 +0300
Subject: [PATCH 128/298] serial: 8250_port: Check IRQ data before use

commit cce7fc8b29961b64fadb1ce398dc5ff32a79643b upstream.

In case the leaf driver wants to use IRQ polling (irq = 0) and
IIR register shows that an interrupt happened in the 8250 hardware
the IRQ data can be NULL. In such a case we need to skip the wake
event as we came to this path from the timer interrupt and quite
likely system is already awake.

Without this fix we have got an Oops:

    serial8250: ttyS0 at I/O 0x3f8 (irq = 0, base_baud = 115200) is a 16550A
    ...
    BUG: kernel NULL pointer dereference, address: 0000000000000010
    RIP: 0010:serial8250_handle_irq+0x7c/0x240
    Call Trace:
     ? serial8250_handle_irq+0x7c/0x240
     ? __pfx_serial8250_timeout+0x10/0x10

Fixes: 0ba9e3a13c6a ("serial: 8250: Add missing wakeup event reporting")
Cc: stable <stable@kernel.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://lore.kernel.org/r/20230831222555.614426-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/tty/serial/8250/8250_port.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index d3161be35b1b..7f5d51de622d 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -1910,7 +1910,10 @@ int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
 		skip_rx = true;
 
 	if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
-		if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
+		struct irq_data *d;
+
+		d = irq_get_irq_data(port->irq);
+		if (d && irqd_is_wakeup_set(d))
 			pm_wakeup_event(tport->tty->dev, 0);
 		if (!up->dma || handle_rx_dma(up, iir))
 			status = serial8250_rx_chars(up, status);
-- 
GitLab


From bb61224f6abc8e71bfdf06d7c984e23460875f5b Mon Sep 17 00:00:00 2001
From: Pan Bian <bianpan2016@163.com>
Date: Thu, 21 Sep 2023 23:17:31 +0900
Subject: [PATCH 129/298] nilfs2: fix potential use after free in
 nilfs_gccache_submit_read_data()

commit 7ee29facd8a9c5a26079148e36bcf07141b3a6bc upstream.

In nilfs_gccache_submit_read_data(), brelse(bh) is called to drop the
reference count of bh when the call to nilfs_dat_translate() fails.  If
the reference count hits 0 and its owner page gets unlocked, bh may be
freed.  However, bh->b_page is dereferenced to put the page after that,
which may result in a use-after-free bug.  This patch moves the release
operation after unlocking and putting the page.

NOTE: The function in question is only called in GC, and in combination
with current userland tools, address translation using DAT does not occur
in that function, so the code path that causes this issue will not be
executed.  However, it is possible to run that code path by intentionally
modifying the userland GC library or by calling the GC ioctl directly.

[konishi.ryusuke@gmail.com: NOTE added to the commit log]
Link: https://lkml.kernel.org/r/1543201709-53191-1-git-send-email-bianpan2016@163.com
Link: https://lkml.kernel.org/r/20230921141731.10073-1-konishi.ryusuke@gmail.com
Fixes: a3d93f709e89 ("nilfs2: block cache for garbage collection")
Signed-off-by: Pan Bian <bianpan2016@163.com>
Reported-by: Ferry Meng <mengferry@linux.alibaba.com>
Closes: https://lkml.kernel.org/r/20230818092022.111054-1-mengferry@linux.alibaba.com
Signed-off-by: Ryusuke Konishi <konishi.ryusuke@gmail.com>
Tested-by: Ryusuke Konishi <konishi.ryusuke@gmail.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 fs/nilfs2/gcinode.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/fs/nilfs2/gcinode.c b/fs/nilfs2/gcinode.c
index 114774ac2185..cef46650102e 100644
--- a/fs/nilfs2/gcinode.c
+++ b/fs/nilfs2/gcinode.c
@@ -73,10 +73,8 @@ int nilfs_gccache_submit_read_data(struct inode *inode, sector_t blkoff,
 		struct the_nilfs *nilfs = inode->i_sb->s_fs_info;
 
 		err = nilfs_dat_translate(nilfs->ns_dat, vbn, &pbn);
-		if (unlikely(err)) { /* -EIO, -ENOMEM, -ENOENT */
-			brelse(bh);
+		if (unlikely(err)) /* -EIO, -ENOMEM, -ENOENT */
 			goto failed;
-		}
 	}
 
 	lock_buffer(bh);
@@ -102,6 +100,8 @@ int nilfs_gccache_submit_read_data(struct inode *inode, sector_t blkoff,
  failed:
 	unlock_page(bh->b_page);
 	put_page(bh->b_page);
+	if (unlikely(err))
+		brelse(bh);
 	return err;
 }
 
-- 
GitLab


From 4546f1c4d3353823b3db0c5849de5bbadd687e0c Mon Sep 17 00:00:00 2001
From: Kailang Yang <kailang@realtek.com>
Date: Thu, 7 Sep 2023 15:24:34 +0800
Subject: [PATCH 130/298] ALSA: hda: Disable power save for solving pop issue
 on Lenovo ThinkCentre M70q

commit 057a28ef93bdbe84326d34cdb5543afdaab49fe1 upstream.

Lenovo ThinkCentre M70q had boot up pop noise.
Disable power save will solve pop issue.

Signed-off-by: Kailang Yang <kailang@realtek.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/315900e2efef42fd9855eacfeb443abd@realtek.com
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 sound/pci/hda/hda_intel.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 40d596248fab..aaca36250dda 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -2364,6 +2364,7 @@ static struct snd_pci_quirk power_save_blacklist[] = {
 	SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
 	/* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
 	SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
+	SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0),
 	/* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
 	SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
 	/* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
-- 
GitLab


From 0994f3e464ff05793438d6f20c5658fc9bc22054 Mon Sep 17 00:00:00 2001
From: Niklas Cassel <niklas.cassel@wdc.com>
Date: Mon, 18 Sep 2023 22:24:50 +0200
Subject: [PATCH 131/298] ata: libata-scsi: ignore reserved bits for REPORT
 SUPPORTED OPERATION CODES

commit 3ef600923521616ebe192c893468ad0424de2afb upstream.

For REPORT SUPPORTED OPERATION CODES command, the service action field is
defined as bits 0-4 in the second byte in the CDB. Bits 5-7 in the second
byte are reserved.

Only look at the service action field in the second byte when determining
if the MAINTENANCE IN opcode is a REPORT SUPPORTED OPERATION CODES command.

This matches how we only look at the service action field in the second
byte when determining if the SERVICE ACTION IN(16) opcode is a READ
CAPACITY(16) command (reserved bits 5-7 in the second byte are ignored).

Fixes: 7b2030942859 ("libata: Add support for SCT Write Same")
Cc: stable@vger.kernel.org
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/ata/libata-scsi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index 2295b74714e1..dc5223981270 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -4561,7 +4561,7 @@ void ata_scsi_simulate(struct ata_device *dev, struct scsi_cmnd *cmd)
 		break;
 
 	case MAINTENANCE_IN:
-		if (scsicmd[1] == MI_REPORT_SUPPORTED_OPERATION_CODES)
+		if ((scsicmd[1] & 0x1f) == MI_REPORT_SUPPORTED_OPERATION_CODES)
 			ata_scsi_rbuf_fill(&args, ata_scsiop_maint_in);
 		else
 			ata_scsi_set_invalid_field(dev, cmd, 1, 0xff);
-- 
GitLab


From 602f3633d9043762625b7d0c718823e0607b023e Mon Sep 17 00:00:00 2001
From: Heiner Kallweit <hkallweit1@gmail.com>
Date: Thu, 14 Sep 2023 23:08:44 +0200
Subject: [PATCH 132/298] i2c: i801: unregister tco_pdev in i801_probe() error
 path

commit 3914784553f68c931fc666dbe7e86fe881aada38 upstream.

We have to unregister tco_pdev also if i2c_add_adapter() fails.

Fixes: 9424693035a5 ("i2c: i801: Create iTCO device on newer Intel PCHs")
Cc: stable@vger.kernel.org
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/i2c/busses/i2c-i801.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index fb0ddaad87d2..6017f6aeee89 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -1679,6 +1679,7 @@ static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
 		"SMBus I801 adapter at %04lx", priv->smba);
 	err = i2c_add_adapter(&priv->adapter);
 	if (err) {
+		platform_device_unregister(priv->tco_pdev);
 		i801_acpi_remove(priv);
 		return err;
 	}
-- 
GitLab


From 88fba1c785e4f62acf2b09ab55ed3a1b3a15c51b Mon Sep 17 00:00:00 2001
From: Josef Bacik <josef@toxicpanda.com>
Date: Mon, 18 Sep 2023 10:34:51 -0400
Subject: [PATCH 133/298] btrfs: properly report 0 avail for very full file
 systems

commit 58bfe2ccec5f9f137b41dd38f335290dcc13cd5c upstream.

A user reported some issues with smaller file systems that get very
full.  While investigating this issue I noticed that df wasn't showing
100% full, despite having 0 chunk space and having < 1MiB of available
metadata space.

This turns out to be an overflow issue, we're doing:

  total_available_metadata_space - SZ_4M < global_block_rsv_size

to determine if there's not enough space to make metadata allocations,
which overflows if total_available_metadata_space is < 4M.  Fix this by
checking to see if our available space is greater than the 4M threshold.
This makes df properly report 100% usage on the file system.

CC: stable@vger.kernel.org # 4.14+
Signed-off-by: Josef Bacik <josef@toxicpanda.com>
Reviewed-by: David Sterba <dsterba@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 fs/btrfs/super.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c
index 521f6c2091ad..a59543951851 100644
--- a/fs/btrfs/super.c
+++ b/fs/btrfs/super.c
@@ -2196,7 +2196,7 @@ static int btrfs_statfs(struct dentry *dentry, struct kstatfs *buf)
 	 * calculated f_bavail.
 	 */
 	if (!mixed && block_rsv->space_info->full &&
-	    total_free_meta - thresh < block_rsv->size)
+	    (total_free_meta < thresh || total_free_meta - thresh < block_rsv->size))
 		buf->f_bavail = 0;
 
 	buf->f_type = BTRFS_SUPER_MAGIC;
-- 
GitLab


From 4c97395712ca35f50a222886bdf3004433a22405 Mon Sep 17 00:00:00 2001
From: Mika Westerberg <mika.westerberg@linux.intel.com>
Date: Wed, 13 Sep 2023 08:26:47 +0300
Subject: [PATCH 134/298] net: thunderbolt: Fix TCPv6 GSO checksum calculation

commit e0b65f9b81fef180cf5f103adecbe5505c961153 upstream.

Alex reported that running ssh over IPv6 does not work with
Thunderbolt/USB4 networking driver. The reason for that is that driver
should call skb_is_gso() before calling skb_is_gso_v6(), and it should
not return false after calculates the checksum successfully. This probably
was a copy paste error from the original driver where it was done properly.

Reported-by: Alex Balcanquall <alex@alexbal.com>
Fixes: e69b6c02b4c3 ("net: Add support for networking over Thunderbolt cable")
Cc: stable@vger.kernel.org
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/net/thunderbolt.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/net/thunderbolt.c b/drivers/net/thunderbolt.c
index 51b5442fbc66..e0b4c54e6c08 100644
--- a/drivers/net/thunderbolt.c
+++ b/drivers/net/thunderbolt.c
@@ -961,12 +961,11 @@ static bool tbnet_xmit_csum_and_map(struct tbnet *net, struct sk_buff *skb,
 		*tucso = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
 					    ip_hdr(skb)->daddr, 0,
 					    ip_hdr(skb)->protocol, 0);
-	} else if (skb_is_gso_v6(skb)) {
+	} else if (skb_is_gso(skb) && skb_is_gso_v6(skb)) {
 		tucso = dest + ((void *)&(tcp_hdr(skb)->check) - data);
 		*tucso = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
 					  &ipv6_hdr(skb)->daddr, 0,
 					  IPPROTO_TCP, 0);
-		return false;
 	} else if (protocol == htons(ETH_P_IPV6)) {
 		tucso = dest + skb_checksum_start_offset(skb) + skb->csum_offset;
 		*tucso = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
-- 
GitLab


From af72179da9a317269da808c2b8f853cb2b90a376 Mon Sep 17 00:00:00 2001
From: Damien Le Moal <dlemoal@kernel.org>
Date: Mon, 4 Sep 2023 20:38:13 +0900
Subject: [PATCH 135/298] ata: libata-core: Fix ata_port_request_pm() locking

commit 3b8e0af4a7a331d1510e963b8fd77e2fca0a77f1 upstream.

The function ata_port_request_pm() checks the port flag
ATA_PFLAG_PM_PENDING and calls ata_port_wait_eh() if this flag is set to
ensure that power management operations for a port are not scheduled
simultaneously. However, this flag check is done without holding the
port lock.

Fix this by taking the port lock on entry to the function and checking
the flag under this lock. The lock is released and re-taken if
ata_port_wait_eh() needs to be called. The two WARN_ON() macros checking
that the ATA_PFLAG_PM_PENDING flag was cleared are removed as the first
call is racy and the second one done without holding the port lock.

Fixes: 5ef41082912b ("ata: add ata port system PM callbacks")
Cc: stable@vger.kernel.org
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Tested-by: Chia-Lin Kao (AceLan) <acelan.kao@canonical.com>
Reviewed-by: Niklas Cassel <niklas.cassel@wdc.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Martin K. Petersen <martin.petersen@oracle.com>
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/ata/libata-core.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 4a7da8f744e0..7f7ccfd88920 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -5756,17 +5756,19 @@ static void ata_port_request_pm(struct ata_port *ap, pm_message_t mesg,
 	struct ata_link *link;
 	unsigned long flags;
 
-	/* Previous resume operation might still be in
-	 * progress.  Wait for PM_PENDING to clear.
+	spin_lock_irqsave(ap->lock, flags);
+
+	/*
+	 * A previous PM operation might still be in progress. Wait for
+	 * ATA_PFLAG_PM_PENDING to clear.
 	 */
 	if (ap->pflags & ATA_PFLAG_PM_PENDING) {
+		spin_unlock_irqrestore(ap->lock, flags);
 		ata_port_wait_eh(ap);
-		WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
+		spin_lock_irqsave(ap->lock, flags);
 	}
 
-	/* request PM ops to EH */
-	spin_lock_irqsave(ap->lock, flags);
-
+	/* Request PM operation to EH */
 	ap->pm_mesg = mesg;
 	ap->pflags |= ATA_PFLAG_PM_PENDING;
 	ata_for_each_link(link, ap, HOST_FIRST) {
@@ -5778,10 +5780,8 @@ static void ata_port_request_pm(struct ata_port *ap, pm_message_t mesg,
 
 	spin_unlock_irqrestore(ap->lock, flags);
 
-	if (!async) {
+	if (!async)
 		ata_port_wait_eh(ap);
-		WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
-	}
 }
 
 /*
-- 
GitLab


From 040251185b9d47b3baf7b371a56db3e55137d479 Mon Sep 17 00:00:00 2001
From: Damien Le Moal <dlemoal@kernel.org>
Date: Sat, 26 Aug 2023 13:07:36 +0900
Subject: [PATCH 136/298] ata: libata-core: Fix port and device removal

commit 84d76529c650f887f1e18caee72d6f0589e1baf9 upstream.

Whenever an ATA adapter driver is removed (e.g. rmmod),
ata_port_detach() is called repeatedly for all the adapter ports to
remove (unload) the devices attached to the port and delete the port
device itself. Removing of devices is done using libata EH with the
ATA_PFLAG_UNLOADING port flag set. This causes libata EH to execute
ata_eh_unload() which disables all devices attached to the port.

ata_port_detach() finishes by calling scsi_remove_host() to remove the
scsi host associated with the port. This function will trigger the
removal of all scsi devices attached to the host and in the case of
disks, calls to sd_shutdown() which will flush the device write cache
and stop the device. However, given that the devices were already
disabled by ata_eh_unload(), the synchronize write cache command and
start stop unit commands fail. E.g. running "rmmod ahci" with first
removing sd_mod results in error messages like:

ata13.00: disable device
sd 0:0:0:0: [sda] Synchronizing SCSI cache
sd 0:0:0:0: [sda] Synchronize Cache(10) failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK
sd 0:0:0:0: [sda] Stopping disk
sd 0:0:0:0: [sda] Start/Stop Unit failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK

Fix this by removing all scsi devices of the ata devices connected to
the port before scheduling libata EH to disable the ATA devices.

Fixes: 720ba12620ee ("[PATCH] libata-hp: update unload-unplug")
Cc: stable@vger.kernel.org
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Reviewed-by: Niklas Cassel <niklas.cassel@wdc.com>
Tested-by: Chia-Lin Kao (AceLan) <acelan.kao@canonical.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Martin K. Petersen <martin.petersen@oracle.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/ata/libata-core.c | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 7f7ccfd88920..b7471f732402 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -6750,11 +6750,30 @@ static void ata_port_detach(struct ata_port *ap)
 	if (!ap->ops->error_handler)
 		goto skip_eh;
 
-	/* tell EH we're leaving & flush EH */
+	/* Wait for any ongoing EH */
+	ata_port_wait_eh(ap);
+
+	mutex_lock(&ap->scsi_scan_mutex);
 	spin_lock_irqsave(ap->lock, flags);
+
+	/* Remove scsi devices */
+	ata_for_each_link(link, ap, HOST_FIRST) {
+		ata_for_each_dev(dev, link, ALL) {
+			if (dev->sdev) {
+				spin_unlock_irqrestore(ap->lock, flags);
+				scsi_remove_device(dev->sdev);
+				spin_lock_irqsave(ap->lock, flags);
+				dev->sdev = NULL;
+			}
+		}
+	}
+
+	/* Tell EH to disable all devices */
 	ap->pflags |= ATA_PFLAG_UNLOADING;
 	ata_port_schedule_eh(ap);
+
 	spin_unlock_irqrestore(ap->lock, flags);
+	mutex_unlock(&ap->scsi_scan_mutex);
 
 	/* wait till EH commits suicide */
 	ata_port_wait_eh(ap);
-- 
GitLab


From 678cb24e70ae69a01e43687bffa51a2041eb0b9a Mon Sep 17 00:00:00 2001
From: Damien Le Moal <dlemoal@kernel.org>
Date: Fri, 8 Sep 2023 20:04:52 +0900
Subject: [PATCH 137/298] ata: libata-core: Do not register PM operations for
 SAS ports

commit 75e2bd5f1ede42a2bc88aa34b431e1ace8e0bea0 upstream.

libsas does its own domain based power management of ports. For such
ports, libata should not use a device type defining power management
operations as executing these operations for suspend/resume in addition
to libsas calls to ata_sas_port_suspend() and ata_sas_port_resume() is
not necessary (and likely dangerous to do, even though problems are not
seen currently).

Introduce the new ata_port_sas_type device_type for ports managed by
libsas. This new device type is used in ata_tport_add() and is defined
without power management operations.

Fixes: 2fcbdcb4c802 ("[SCSI] libata: export ata_port suspend/resume infrastructure for sas")
Cc: stable@vger.kernel.org
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Tested-by: Chia-Lin Kao (AceLan) <acelan.kao@canonical.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: John Garry <john.g.garry@oracle.com>
Reviewed-by: Martin K. Petersen <martin.petersen@oracle.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/ata/libata-core.c      | 2 +-
 drivers/ata/libata-transport.c | 9 ++++++++-
 drivers/ata/libata.h           | 2 ++
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index b7471f732402..c563b9545c6c 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -5947,7 +5947,7 @@ void ata_host_resume(struct ata_host *host)
 #endif
 
 const struct device_type ata_port_type = {
-	.name = "ata_port",
+	.name = ATA_PORT_TYPE_NAME,
 #ifdef CONFIG_PM
 	.pm = &ata_port_pm_ops,
 #endif
diff --git a/drivers/ata/libata-transport.c b/drivers/ata/libata-transport.c
index f04f4f977400..5eae76d8b655 100644
--- a/drivers/ata/libata-transport.c
+++ b/drivers/ata/libata-transport.c
@@ -266,6 +266,10 @@ void ata_tport_delete(struct ata_port *ap)
 	put_device(dev);
 }
 
+static const struct device_type ata_port_sas_type = {
+	.name = ATA_PORT_TYPE_NAME,
+};
+
 /** ata_tport_add - initialize a transport ATA port structure
  *
  * @parent:	parent device
@@ -283,7 +287,10 @@ int ata_tport_add(struct device *parent,
 	struct device *dev = &ap->tdev;
 
 	device_initialize(dev);
-	dev->type = &ata_port_type;
+	if (ap->flags & ATA_FLAG_SAS_HOST)
+		dev->type = &ata_port_sas_type;
+	else
+		dev->type = &ata_port_type;
 
 	dev->parent = parent;
 	ata_host_get(ap->host);
diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h
index f953cb4bb1ba..b568d6b9350a 100644
--- a/drivers/ata/libata.h
+++ b/drivers/ata/libata.h
@@ -46,6 +46,8 @@ enum {
 	ATA_DNXFER_QUIET	= (1 << 31),
 };
 
+#define ATA_PORT_TYPE_NAME	"ata_port"
+
 extern atomic_t ata_print_id;
 extern int atapi_passthru16;
 extern int libata_fua;
-- 
GitLab


From 474f306e739d81c4ecb148ae94f2c85415157e23 Mon Sep 17 00:00:00 2001
From: Matthias Schiffer <mschiffer@universe-factory.net>
Date: Fri, 22 Sep 2023 22:55:16 +0200
Subject: [PATCH 138/298] ata: libata-sata: increase PMP SRST timeout to 10s

commit 753a4d531bc518633ea88ac0ed02b25a16823d51 upstream.

On certain SATA controllers, softreset fails after wakeup from S2RAM with
the message "softreset failed (1st FIS failed)", sometimes resulting in
drives not being detected again. With the increased timeout, this issue
is avoided. Instead, "softreset failed (device not ready)" is now
logged 1-2 times; this later failure seems to cause fewer problems
however, and the drives are detected reliably once they've spun up and
the probe is retried.

The issue was observed with the primary SATA controller of the QNAP
TS-453B, which is an "Intel Corporation Celeron/Pentium Silver Processor
SATA Controller [8086:31e3] (rev 06)" integrated in the Celeron J4125 CPU,
and the following drives:

- Seagate IronWolf ST12000VN0008
- Seagate IronWolf ST8000NE0004

The SATA controller seems to be more relevant to this issue than the
drives, as the same drives are always detected reliably on the secondary
SATA controller on the same board (an ASMedia 106x) without any "softreset
failed" errors even without the increased timeout.

Fixes: e7d3ef13d52a ("libata: change drive ready wait after hard reset to 5s")
Cc: stable@vger.kernel.org
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 include/linux/libata.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/libata.h b/include/linux/libata.h
index 73cd0182452c..af50f37d934b 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -311,7 +311,7 @@ enum {
 	 * advised to wait only for the following duration before
 	 * doing SRST.
 	 */
-	ATA_TMOUT_PMP_SRST_WAIT	= 5000,
+	ATA_TMOUT_PMP_SRST_WAIT	= 10000,
 
 	/* When the LPM policy is set to ATA_LPM_MAX_POWER, there might
 	 * be a spurious PHY event, so ignore the first PHY event that
-- 
GitLab


From 3dc98986373e703a2b463e5963ff978469c87b0f Mon Sep 17 00:00:00 2001
From: Greg Ungerer <gerg@kernel.org>
Date: Thu, 7 Sep 2023 11:18:08 +1000
Subject: [PATCH 139/298] fs: binfmt_elf_efpic: fix personality for ELF-FDPIC

commit 7c3151585730b7095287be8162b846d31e6eee61 upstream.

The elf-fdpic loader hard sets the process personality to either
PER_LINUX_FDPIC for true elf-fdpic binaries or to PER_LINUX for normal ELF
binaries (in this case they would be constant displacement compiled with
-pie for example).  The problem with that is that it will lose any other
bits that may be in the ELF header personality (such as the "bug
emulation" bits).

On the ARM architecture the ADDR_LIMIT_32BIT flag is used to signify a
normal 32bit binary - as opposed to a legacy 26bit address binary.  This
matters since start_thread() will set the ARM CPSR register as required
based on this flag.  If the elf-fdpic loader loses this bit the process
will be mis-configured and crash out pretty quickly.

Modify elf-fdpic loader personality setting so that it preserves the upper
three bytes by using the SET_PERSONALITY macro to set it.  This macro in
the generic case sets PER_LINUX and preserves the upper bytes.
Architectures can override this for their specific use case, and ARM does
exactly this.

The problem shows up quite easily running under qemu using the ARM
architecture, but not necessarily on all types of real ARM hardware.  If
the underlying ARM processor does not support the legacy 26-bit addressing
mode then everything will work as expected.

Link: https://lkml.kernel.org/r/20230907011808.2985083-1-gerg@kernel.org
Fixes: 1bde925d23547 ("fs/binfmt_elf_fdpic.c: provide NOMMU loader for regular ELF binaries")
Signed-off-by: Greg Ungerer <gerg@kernel.org>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Cc: Christian Brauner <brauner@kernel.org>
Cc: Eric W. Biederman <ebiederm@xmission.com>
Cc: Greg Ungerer <gerg@kernel.org>
Cc: Kees Cook <keescook@chromium.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 fs/binfmt_elf_fdpic.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/fs/binfmt_elf_fdpic.c b/fs/binfmt_elf_fdpic.c
index 64d0b838085d..a7c2efcd0a4a 100644
--- a/fs/binfmt_elf_fdpic.c
+++ b/fs/binfmt_elf_fdpic.c
@@ -349,10 +349,9 @@ static int load_elf_fdpic_binary(struct linux_binprm *bprm)
 	/* there's now no turning back... the old userspace image is dead,
 	 * defunct, deceased, etc.
 	 */
+	SET_PERSONALITY(exec_params.hdr);
 	if (elf_check_fdpic(&exec_params.hdr))
-		set_personality(PER_LINUX_FDPIC);
-	else
-		set_personality(PER_LINUX);
+		current->personality |= PER_LINUX_FDPIC;
 	if (elf_read_implies_exec(&exec_params.hdr, executable_stack))
 		current->personality |= READ_IMPLIES_EXEC;
 
-- 
GitLab


From 996f30b44369fa2d1fe62d30a14ef27e05b30448 Mon Sep 17 00:00:00 2001
From: Shida Zhang <zhangshida@kylinos.cn>
Date: Thu, 3 Aug 2023 14:09:38 +0800
Subject: [PATCH 140/298] ext4: fix rec_len verify error

commit 7fda67e8c3ab6069f75888f67958a6d30454a9f6 upstream.

With the configuration PAGE_SIZE 64k and filesystem blocksize 64k,
a problem occurred when more than 13 million files were directly created
under a directory:

EXT4-fs error (device xx): ext4_dx_csum_set:492: inode #xxxx: comm xxxxx: dir seems corrupt?  Run e2fsck -D.
EXT4-fs error (device xx): ext4_dx_csum_verify:463: inode #xxxx: comm xxxxx: dir seems corrupt?  Run e2fsck -D.
EXT4-fs error (device xx): dx_probe:856: inode #xxxx: block 8188: comm xxxxx: Directory index failed checksum

When enough files are created, the fake_dirent->reclen will be 0xffff.
it doesn't equal to the blocksize 65536, i.e. 0x10000.

But it is not the same condition when blocksize equals to 4k.
when enough files are created, the fake_dirent->reclen will be 0x1000.
it equals to the blocksize 4k, i.e. 0x1000.

The problem seems to be related to the limitation of the 16-bit field
when the blocksize is set to 64k.
To address this, helpers like ext4_rec_len_{from,to}_disk has already
been introduced to complete the conversion between the encoded and the
plain form of rec_len.

So fix this one by using the helper, and all the other in this file too.

Cc: stable@kernel.org
Fixes: dbe89444042a ("ext4: Calculate and verify checksums for htree nodes")
Suggested-by: Andreas Dilger <adilger@dilger.ca>
Suggested-by: Darrick J. Wong <djwong@kernel.org>
Signed-off-by: Shida Zhang <zhangshida@kylinos.cn>
Reviewed-by: Andreas Dilger <adilger@dilger.ca>
Reviewed-by: Darrick J. Wong <djwong@kernel.org>
Link: https://lore.kernel.org/r/20230803060938.1929759-1-zhangshida@kylinos.cn
Signed-off-by: Theodore Ts'o <tytso@mit.edu>
Signed-off-by: Shida Zhang <zhangshida@kylinos.cn>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 fs/ext4/namei.c | 26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/fs/ext4/namei.c b/fs/ext4/namei.c
index db9bba3473b5..93d392576c12 100644
--- a/fs/ext4/namei.c
+++ b/fs/ext4/namei.c
@@ -322,17 +322,17 @@ static struct ext4_dir_entry_tail *get_dirent_tail(struct inode *inode,
 						   struct ext4_dir_entry *de)
 {
 	struct ext4_dir_entry_tail *t;
+	int blocksize = EXT4_BLOCK_SIZE(inode->i_sb);
 
 #ifdef PARANOID
 	struct ext4_dir_entry *d, *top;
 
 	d = de;
 	top = (struct ext4_dir_entry *)(((void *)de) +
-		(EXT4_BLOCK_SIZE(inode->i_sb) -
-		sizeof(struct ext4_dir_entry_tail)));
-	while (d < top && d->rec_len)
+		(blocksize - sizeof(struct ext4_dir_entry_tail)));
+	while (d < top && ext4_rec_len_from_disk(d->rec_len, blocksize))
 		d = (struct ext4_dir_entry *)(((void *)d) +
-		    le16_to_cpu(d->rec_len));
+		    ext4_rec_len_from_disk(d->rec_len, blocksize));
 
 	if (d != top)
 		return NULL;
@@ -343,7 +343,8 @@ static struct ext4_dir_entry_tail *get_dirent_tail(struct inode *inode,
 #endif
 
 	if (t->det_reserved_zero1 ||
-	    le16_to_cpu(t->det_rec_len) != sizeof(struct ext4_dir_entry_tail) ||
+	    (ext4_rec_len_from_disk(t->det_rec_len, blocksize) !=
+	     sizeof(struct ext4_dir_entry_tail)) ||
 	    t->det_reserved_zero2 ||
 	    t->det_reserved_ft != EXT4_FT_DIR_CSUM)
 		return NULL;
@@ -425,13 +426,14 @@ static struct dx_countlimit *get_dx_countlimit(struct inode *inode,
 	struct ext4_dir_entry *dp;
 	struct dx_root_info *root;
 	int count_offset;
+	int blocksize = EXT4_BLOCK_SIZE(inode->i_sb);
+	unsigned int rlen = ext4_rec_len_from_disk(dirent->rec_len, blocksize);
 
-	if (le16_to_cpu(dirent->rec_len) == EXT4_BLOCK_SIZE(inode->i_sb))
+	if (rlen == blocksize)
 		count_offset = 8;
-	else if (le16_to_cpu(dirent->rec_len) == 12) {
+	else if (rlen == 12) {
 		dp = (struct ext4_dir_entry *)(((void *)dirent) + 12);
-		if (le16_to_cpu(dp->rec_len) !=
-		    EXT4_BLOCK_SIZE(inode->i_sb) - 12)
+		if (ext4_rec_len_from_disk(dp->rec_len, blocksize) != blocksize - 12)
 			return NULL;
 		root = (struct dx_root_info *)(((void *)dp + 12));
 		if (root->reserved_zero ||
@@ -1244,6 +1246,7 @@ static int dx_make_map(struct inode *dir, struct buffer_head *bh,
 	unsigned int buflen = bh->b_size;
 	char *base = bh->b_data;
 	struct dx_hash_info h = *hinfo;
+	int blocksize = EXT4_BLOCK_SIZE(dir->i_sb);
 
 	if (ext4_has_metadata_csum(dir->i_sb))
 		buflen -= sizeof(struct ext4_dir_entry_tail);
@@ -1257,11 +1260,12 @@ static int dx_make_map(struct inode *dir, struct buffer_head *bh,
 			map_tail--;
 			map_tail->hash = h.hash;
 			map_tail->offs = ((char *) de - base)>>2;
-			map_tail->size = le16_to_cpu(de->rec_len);
+			map_tail->size = ext4_rec_len_from_disk(de->rec_len,
+								blocksize);
 			count++;
 			cond_resched();
 		}
-		de = ext4_next_entry(de, dir->i_sb->s_blocksize);
+		de = ext4_next_entry(de, blocksize);
 	}
 	return count;
 }
-- 
GitLab


From 6b6d459bbf6e7365d39c7794c7b556a9bad5d217 Mon Sep 17 00:00:00 2001
From: Niklas Cassel <niklas.cassel@wdc.com>
Date: Mon, 4 Sep 2023 22:42:56 +0200
Subject: [PATCH 141/298] ata: libata: disallow dev-initiated LPM transitions
 to unsupported states
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

commit 24e0e61db3cb86a66824531989f1df80e0939f26 upstream.

In AHCI 1.3.1, the register description for CAP.SSC:
"When cleared to ‘0’, software must not allow the HBA to initiate
transitions to the Slumber state via agressive link power management nor
the PxCMD.ICC field in each port, and the PxSCTL.IPM field in each port
must be programmed to disallow device initiated Slumber requests."

In AHCI 1.3.1, the register description for CAP.PSC:
"When cleared to ‘0’, software must not allow the HBA to initiate
transitions to the Partial state via agressive link power management nor
the PxCMD.ICC field in each port, and the PxSCTL.IPM field in each port
must be programmed to disallow device initiated Partial requests."

Ensure that we always set the corresponding bits in PxSCTL.IPM, such that
a device is not allowed to initiate transitions to power states which are
unsupported by the HBA.

DevSleep is always initiated by the HBA, however, for completeness, set the
corresponding bit in PxSCTL.IPM such that agressive link power management
cannot transition to DevSleep if DevSleep is not supported.

sata_link_scr_lpm() is used by libahci, ata_piix and libata-pmp.
However, only libahci has the ability to read the CAP/CAP2 register to see
if these features are supported. Therefore, in order to not introduce any
regressions on ata_piix or libata-pmp, create flags that indicate that the
respective feature is NOT supported. This way, the behavior for ata_piix
and libata-pmp should remain unchanged.

This change is based on a patch originally submitted by Runa Guo-oc.

Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Fixes: 1152b2617a6e ("libata: implement sata_link_scr_lpm() and make ata_dev_set_feature() global")
Cc: stable@vger.kernel.org
Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/ata/ahci.c        |  9 +++++++++
 drivers/ata/libata-core.c | 19 ++++++++++++++++---
 include/linux/libata.h    |  4 ++++
 3 files changed, 29 insertions(+), 3 deletions(-)

diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 2e4bcf2d0a51..ab3ea47ecce3 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1864,6 +1864,15 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 	else
 		dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
 
+	if (!(hpriv->cap & HOST_CAP_PART))
+		host->flags |= ATA_HOST_NO_PART;
+
+	if (!(hpriv->cap & HOST_CAP_SSC))
+		host->flags |= ATA_HOST_NO_SSC;
+
+	if (!(hpriv->cap2 & HOST_CAP2_SDS))
+		host->flags |= ATA_HOST_NO_DEVSLP;
+
 	if (pi.flags & ATA_FLAG_EM)
 		ahci_reset_em(host);
 
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index c563b9545c6c..2b9f6769f80d 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -3997,10 +3997,23 @@ int sata_link_scr_lpm(struct ata_link *link, enum ata_lpm_policy policy,
 	case ATA_LPM_MED_POWER_WITH_DIPM:
 	case ATA_LPM_MIN_POWER_WITH_PARTIAL:
 	case ATA_LPM_MIN_POWER:
-		if (ata_link_nr_enabled(link) > 0)
-			/* no restrictions on LPM transitions */
+		if (ata_link_nr_enabled(link) > 0) {
+			/* assume no restrictions on LPM transitions */
 			scontrol &= ~(0x7 << 8);
-		else {
+
+			/*
+			 * If the controller does not support partial, slumber,
+			 * or devsleep, then disallow these transitions.
+			 */
+			if (link->ap->host->flags & ATA_HOST_NO_PART)
+				scontrol |= (0x1 << 8);
+
+			if (link->ap->host->flags & ATA_HOST_NO_SSC)
+				scontrol |= (0x2 << 8);
+
+			if (link->ap->host->flags & ATA_HOST_NO_DEVSLP)
+				scontrol |= (0x4 << 8);
+		} else {
 			/* empty port, power off */
 			scontrol &= ~0xf;
 			scontrol |= (0x1 << 2);
diff --git a/include/linux/libata.h b/include/linux/libata.h
index af50f37d934b..361a52e418f7 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -278,6 +278,10 @@ enum {
 	ATA_HOST_PARALLEL_SCAN	= (1 << 2),	/* Ports on this host can be scanned in parallel */
 	ATA_HOST_IGNORE_ATA	= (1 << 3),	/* Ignore ATA devices on this host. */
 
+	ATA_HOST_NO_PART	= (1 << 4), /* Host does not support partial */
+	ATA_HOST_NO_SSC		= (1 << 5), /* Host does not support slumber */
+	ATA_HOST_NO_DEVSLP	= (1 << 6), /* Host does not support devslp */
+
 	/* bits 24:31 of host->flags are reserved for LLD specific flags */
 
 	/* various lengths of time */
-- 
GitLab


From ce63d45f45ae8b03f28b3329f6b6e4d072f7d2c5 Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Sat, 7 Oct 2023 13:46:47 +0200
Subject: [PATCH 142/298] Revert "drivers core: Use sysfs_emit and
 sysfs_emit_at for show(device *...) functions"

This reverts commit 3ce2cd63e8ee037644db0cbea65e6c40ab6cc178 which is
commit aa838896d87af561a33ecefea1caa4c15a68bc47 upstream.

Ben writes:
	When I looked into the referenced security issue, it seemed to only be
	exploitable through wakelock names, and in the upstream kernel only
	after commit c8377adfa781 "PM / wakeup: Show wakeup sources stats in
	sysfs" (first included in 5.4).  So I would be interested to know if
	and why a fix was needed for 4.19.

	More importantly, this backported version uniformly converts to
	sysfs_emit(), but there are 3 places sysfs_emit_at() must be used
	instead:

Reported-by: Ben Hutchings <ben@decadent.org.uk>
Link: https://lore.kernel.org/r/95831df76c41a53bc3e1ac8ece64915dd63763a1.camel@decadent.org.uk
Cc: Joe Perches <joe@perches.com>
Cc: Brennan Lamoreaux <blamoreaux@vmware.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/base/arch_topology.c            |  2 +-
 drivers/base/cacheinfo.c                | 18 ++++-----
 drivers/base/core.c                     |  8 ++--
 drivers/base/cpu.c                      | 34 ++++++++---------
 drivers/base/firmware_loader/fallback.c |  2 +-
 drivers/base/memory.c                   | 24 ++++++------
 drivers/base/node.c                     | 34 ++++++++---------
 drivers/base/platform.c                 |  2 +-
 drivers/base/power/sysfs.c              | 50 ++++++++++++-------------
 drivers/base/soc.c                      |  8 ++--
 10 files changed, 91 insertions(+), 91 deletions(-)

diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
index d89f618231cb..e7cb0c6ade81 100644
--- a/drivers/base/arch_topology.c
+++ b/drivers/base/arch_topology.c
@@ -44,7 +44,7 @@ static ssize_t cpu_capacity_show(struct device *dev,
 {
 	struct cpu *cpu = container_of(dev, struct cpu, dev);
 
-	return sysfs_emit(buf, "%lu\n", topology_get_cpu_scale(NULL, cpu->dev.id));
+	return sprintf(buf, "%lu\n", topology_get_cpu_scale(NULL, cpu->dev.id));
 }
 
 static ssize_t cpu_capacity_store(struct device *dev,
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index 51eb403f89de..ce015ce2977c 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -372,7 +372,7 @@ static ssize_t size_show(struct device *dev,
 {
 	struct cacheinfo *this_leaf = dev_get_drvdata(dev);
 
-	return sysfs_emit(buf, "%uK\n", this_leaf->size >> 10);
+	return sprintf(buf, "%uK\n", this_leaf->size >> 10);
 }
 
 static ssize_t shared_cpumap_show_func(struct device *dev, bool list, char *buf)
@@ -402,11 +402,11 @@ static ssize_t type_show(struct device *dev,
 
 	switch (this_leaf->type) {
 	case CACHE_TYPE_DATA:
-		return sysfs_emit(buf, "Data\n");
+		return sprintf(buf, "Data\n");
 	case CACHE_TYPE_INST:
-		return sysfs_emit(buf, "Instruction\n");
+		return sprintf(buf, "Instruction\n");
 	case CACHE_TYPE_UNIFIED:
-		return sysfs_emit(buf, "Unified\n");
+		return sprintf(buf, "Unified\n");
 	default:
 		return -EINVAL;
 	}
@@ -420,11 +420,11 @@ static ssize_t allocation_policy_show(struct device *dev,
 	int n = 0;
 
 	if ((ci_attr & CACHE_READ_ALLOCATE) && (ci_attr & CACHE_WRITE_ALLOCATE))
-		n = sysfs_emit(buf, "ReadWriteAllocate\n");
+		n = sprintf(buf, "ReadWriteAllocate\n");
 	else if (ci_attr & CACHE_READ_ALLOCATE)
-		n = sysfs_emit(buf, "ReadAllocate\n");
+		n = sprintf(buf, "ReadAllocate\n");
 	else if (ci_attr & CACHE_WRITE_ALLOCATE)
-		n = sysfs_emit(buf, "WriteAllocate\n");
+		n = sprintf(buf, "WriteAllocate\n");
 	return n;
 }
 
@@ -436,9 +436,9 @@ static ssize_t write_policy_show(struct device *dev,
 	int n = 0;
 
 	if (ci_attr & CACHE_WRITE_THROUGH)
-		n = sysfs_emit(buf, "WriteThrough\n");
+		n = sprintf(buf, "WriteThrough\n");
 	else if (ci_attr & CACHE_WRITE_BACK)
-		n = sysfs_emit(buf, "WriteBack\n");
+		n = sprintf(buf, "WriteBack\n");
 	return n;
 }
 
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 0332800dffd8..6e380ad9d08a 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -994,7 +994,7 @@ ssize_t device_show_ulong(struct device *dev,
 			  char *buf)
 {
 	struct dev_ext_attribute *ea = to_ext_attr(attr);
-	return sysfs_emit(buf, "%lx\n", *(unsigned long *)(ea->var));
+	return snprintf(buf, PAGE_SIZE, "%lx\n", *(unsigned long *)(ea->var));
 }
 EXPORT_SYMBOL_GPL(device_show_ulong);
 
@@ -1019,7 +1019,7 @@ ssize_t device_show_int(struct device *dev,
 {
 	struct dev_ext_attribute *ea = to_ext_attr(attr);
 
-	return sysfs_emit(buf, "%d\n", *(int *)(ea->var));
+	return snprintf(buf, PAGE_SIZE, "%d\n", *(int *)(ea->var));
 }
 EXPORT_SYMBOL_GPL(device_show_int);
 
@@ -1040,7 +1040,7 @@ ssize_t device_show_bool(struct device *dev, struct device_attribute *attr,
 {
 	struct dev_ext_attribute *ea = to_ext_attr(attr);
 
-	return sysfs_emit(buf, "%d\n", *(bool *)(ea->var));
+	return snprintf(buf, PAGE_SIZE, "%d\n", *(bool *)(ea->var));
 }
 EXPORT_SYMBOL_GPL(device_show_bool);
 
@@ -1273,7 +1273,7 @@ static ssize_t online_show(struct device *dev, struct device_attribute *attr,
 	device_lock(dev);
 	val = !dev->offline;
 	device_unlock(dev);
-	return sysfs_emit(buf, "%u\n", val);
+	return sprintf(buf, "%u\n", val);
 }
 
 static ssize_t online_store(struct device *dev, struct device_attribute *attr,
diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c
index 607fc189e57c..b1bb6f43f896 100644
--- a/drivers/base/cpu.c
+++ b/drivers/base/cpu.c
@@ -156,7 +156,7 @@ static ssize_t show_crash_notes(struct device *dev, struct device_attribute *att
 	 * operation should be safe. No locking required.
 	 */
 	addr = per_cpu_ptr_to_phys(per_cpu_ptr(crash_notes, cpunum));
-	rc = sysfs_emit(buf, "%Lx\n", addr);
+	rc = sprintf(buf, "%Lx\n", addr);
 	return rc;
 }
 static DEVICE_ATTR(crash_notes, 0400, show_crash_notes, NULL);
@@ -167,7 +167,7 @@ static ssize_t show_crash_notes_size(struct device *dev,
 {
 	ssize_t rc;
 
-	rc = sysfs_emit(buf, "%zu\n", sizeof(note_buf_t));
+	rc = sprintf(buf, "%zu\n", sizeof(note_buf_t));
 	return rc;
 }
 static DEVICE_ATTR(crash_notes_size, 0400, show_crash_notes_size, NULL);
@@ -264,7 +264,7 @@ static ssize_t print_cpus_offline(struct device *dev,
 						      nr_cpu_ids, total_cpus-1);
 	}
 
-	n += sysfs_emit(&buf[n], "\n");
+	n += snprintf(&buf[n], len - n, "\n");
 	return n;
 }
 static DEVICE_ATTR(offline, 0444, print_cpus_offline, NULL);
@@ -272,7 +272,7 @@ static DEVICE_ATTR(offline, 0444, print_cpus_offline, NULL);
 static ssize_t print_cpus_isolated(struct device *dev,
 				  struct device_attribute *attr, char *buf)
 {
-	int n = 0;
+	int n = 0, len = PAGE_SIZE-2;
 	cpumask_var_t isolated;
 
 	if (!alloc_cpumask_var(&isolated, GFP_KERNEL))
@@ -280,7 +280,7 @@ static ssize_t print_cpus_isolated(struct device *dev,
 
 	cpumask_andnot(isolated, cpu_possible_mask,
 		       housekeeping_cpumask(HK_FLAG_DOMAIN));
-	n = sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(isolated));
+	n = scnprintf(buf, len, "%*pbl\n", cpumask_pr_args(isolated));
 
 	free_cpumask_var(isolated);
 
@@ -292,9 +292,9 @@ static DEVICE_ATTR(isolated, 0444, print_cpus_isolated, NULL);
 static ssize_t print_cpus_nohz_full(struct device *dev,
 				  struct device_attribute *attr, char *buf)
 {
-	int n = 0;
+	int n = 0, len = PAGE_SIZE-2;
 
-	n = sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(tick_nohz_full_mask));
+	n = scnprintf(buf, len, "%*pbl\n", cpumask_pr_args(tick_nohz_full_mask));
 
 	return n;
 }
@@ -328,7 +328,7 @@ static ssize_t print_cpu_modalias(struct device *dev,
 	ssize_t n;
 	u32 i;
 
-	n = sysfs_emit(buf, "cpu:type:" CPU_FEATURE_TYPEFMT ":feature:",
+	n = sprintf(buf, "cpu:type:" CPU_FEATURE_TYPEFMT ":feature:",
 		    CPU_FEATURE_TYPEVAL);
 
 	for (i = 0; i < MAX_CPU_FEATURES; i++)
@@ -520,56 +520,56 @@ static void __init cpu_dev_register_generic(void)
 ssize_t __weak cpu_show_meltdown(struct device *dev,
 				 struct device_attribute *attr, char *buf)
 {
-	return sysfs_emit(buf, "Not affected\n");
+	return sprintf(buf, "Not affected\n");
 }
 
 ssize_t __weak cpu_show_spectre_v1(struct device *dev,
 				   struct device_attribute *attr, char *buf)
 {
-	return sysfs_emit(buf, "Not affected\n");
+	return sprintf(buf, "Not affected\n");
 }
 
 ssize_t __weak cpu_show_spectre_v2(struct device *dev,
 				   struct device_attribute *attr, char *buf)
 {
-	return sysfs_emit(buf, "Not affected\n");
+	return sprintf(buf, "Not affected\n");
 }
 
 ssize_t __weak cpu_show_spec_store_bypass(struct device *dev,
 					  struct device_attribute *attr, char *buf)
 {
-	return sysfs_emit(buf, "Not affected\n");
+	return sprintf(buf, "Not affected\n");
 }
 
 ssize_t __weak cpu_show_l1tf(struct device *dev,
 			     struct device_attribute *attr, char *buf)
 {
-	return sysfs_emit(buf, "Not affected\n");
+	return sprintf(buf, "Not affected\n");
 }
 
 ssize_t __weak cpu_show_mds(struct device *dev,
 			    struct device_attribute *attr, char *buf)
 {
-	return sysfs_emit(buf, "Not affected\n");
+	return sprintf(buf, "Not affected\n");
 }
 
 ssize_t __weak cpu_show_tsx_async_abort(struct device *dev,
 					struct device_attribute *attr,
 					char *buf)
 {
-	return sysfs_emit(buf, "Not affected\n");
+	return sprintf(buf, "Not affected\n");
 }
 
 ssize_t __weak cpu_show_itlb_multihit(struct device *dev,
 			    struct device_attribute *attr, char *buf)
 {
-	return sysfs_emit(buf, "Not affected\n");
+	return sprintf(buf, "Not affected\n");
 }
 
 ssize_t __weak cpu_show_srbds(struct device *dev,
 			      struct device_attribute *attr, char *buf)
 {
-	return sysfs_emit(buf, "Not affected\n");
+	return sprintf(buf, "Not affected\n");
 }
 
 ssize_t __weak cpu_show_mmio_stale_data(struct device *dev,
diff --git a/drivers/base/firmware_loader/fallback.c b/drivers/base/firmware_loader/fallback.c
index 2116926cc1d5..821e27bda4ca 100644
--- a/drivers/base/firmware_loader/fallback.c
+++ b/drivers/base/firmware_loader/fallback.c
@@ -215,7 +215,7 @@ static ssize_t firmware_loading_show(struct device *dev,
 		loading = fw_sysfs_loading(fw_sysfs->fw_priv);
 	mutex_unlock(&fw_lock);
 
-	return sysfs_emit(buf, "%d\n", loading);
+	return sprintf(buf, "%d\n", loading);
 }
 
 /* one pages buffer should be mapped/unmapped only once */
diff --git a/drivers/base/memory.c b/drivers/base/memory.c
index 5dbe00a5c7c1..e270abc86d46 100644
--- a/drivers/base/memory.c
+++ b/drivers/base/memory.c
@@ -121,7 +121,7 @@ static ssize_t show_mem_start_phys_index(struct device *dev,
 	unsigned long phys_index;
 
 	phys_index = mem->start_section_nr / sections_per_block;
-	return sysfs_emit(buf, "%08lx\n", phys_index);
+	return sprintf(buf, "%08lx\n", phys_index);
 }
 
 /*
@@ -145,7 +145,7 @@ static ssize_t show_mem_removable(struct device *dev,
 	}
 
 out:
-	return sysfs_emit(buf, "%d\n", ret);
+	return sprintf(buf, "%d\n", ret);
 }
 
 /*
@@ -163,17 +163,17 @@ static ssize_t show_mem_state(struct device *dev,
 	 */
 	switch (mem->state) {
 	case MEM_ONLINE:
-		len = sysfs_emit(buf, "online\n");
+		len = sprintf(buf, "online\n");
 		break;
 	case MEM_OFFLINE:
-		len = sysfs_emit(buf, "offline\n");
+		len = sprintf(buf, "offline\n");
 		break;
 	case MEM_GOING_OFFLINE:
-		len = sysfs_emit(buf, "going-offline\n");
+		len = sprintf(buf, "going-offline\n");
 		break;
 	default:
-		len = sysfs_emit(buf, "ERROR-UNKNOWN-%ld\n",
-				 mem->state);
+		len = sprintf(buf, "ERROR-UNKNOWN-%ld\n",
+				mem->state);
 		WARN_ON(1);
 		break;
 	}
@@ -384,7 +384,7 @@ static ssize_t show_phys_device(struct device *dev,
 				struct device_attribute *attr, char *buf)
 {
 	struct memory_block *mem = to_memory_block(dev);
-	return sysfs_emit(buf, "%d\n", mem->phys_device);
+	return sprintf(buf, "%d\n", mem->phys_device);
 }
 
 #ifdef CONFIG_MEMORY_HOTREMOVE
@@ -422,7 +422,7 @@ static ssize_t show_valid_zones(struct device *dev,
 		 */
 		if (!test_pages_in_a_zone(start_pfn, start_pfn + nr_pages,
 					  &valid_start_pfn, &valid_end_pfn))
-			return sysfs_emit(buf, "none\n");
+			return sprintf(buf, "none\n");
 		start_pfn = valid_start_pfn;
 		strcat(buf, page_zone(pfn_to_page(start_pfn))->name);
 		goto out;
@@ -456,7 +456,7 @@ static ssize_t
 print_block_size(struct device *dev, struct device_attribute *attr,
 		 char *buf)
 {
-	return sysfs_emit(buf, "%lx\n", get_memory_block_size());
+	return sprintf(buf, "%lx\n", get_memory_block_size());
 }
 
 static DEVICE_ATTR(block_size_bytes, 0444, print_block_size, NULL);
@@ -470,9 +470,9 @@ show_auto_online_blocks(struct device *dev, struct device_attribute *attr,
 			char *buf)
 {
 	if (memhp_auto_online)
-		return sysfs_emit(buf, "online\n");
+		return sprintf(buf, "online\n");
 	else
-		return sysfs_emit(buf, "offline\n");
+		return sprintf(buf, "offline\n");
 }
 
 static ssize_t
diff --git a/drivers/base/node.c b/drivers/base/node.c
index 8defeace001e..60c2e32f9f61 100644
--- a/drivers/base/node.c
+++ b/drivers/base/node.c
@@ -69,7 +69,7 @@ static ssize_t node_read_meminfo(struct device *dev,
 	struct sysinfo i;
 
 	si_meminfo_node(&i, nid);
-	n = sysfs_emit(buf,
+	n = sprintf(buf,
 		       "Node %d MemTotal:       %8lu kB\n"
 		       "Node %d MemFree:        %8lu kB\n"
 		       "Node %d MemUsed:        %8lu kB\n"
@@ -96,7 +96,7 @@ static ssize_t node_read_meminfo(struct device *dev,
 		       nid, K(sum_zone_node_page_state(nid, NR_MLOCK)));
 
 #ifdef CONFIG_HIGHMEM
-	n += sysfs_emit(buf + n,
+	n += sprintf(buf + n,
 		       "Node %d HighTotal:      %8lu kB\n"
 		       "Node %d HighFree:       %8lu kB\n"
 		       "Node %d LowTotal:       %8lu kB\n"
@@ -106,7 +106,7 @@ static ssize_t node_read_meminfo(struct device *dev,
 		       nid, K(i.totalram - i.totalhigh),
 		       nid, K(i.freeram - i.freehigh));
 #endif
-	n += sysfs_emit(buf + n,
+	n += sprintf(buf + n,
 		       "Node %d Dirty:          %8lu kB\n"
 		       "Node %d Writeback:      %8lu kB\n"
 		       "Node %d FilePages:      %8lu kB\n"
@@ -162,19 +162,19 @@ static DEVICE_ATTR(meminfo, S_IRUGO, node_read_meminfo, NULL);
 static ssize_t node_read_numastat(struct device *dev,
 				struct device_attribute *attr, char *buf)
 {
-	return sysfs_emit(buf,
-			  "numa_hit %lu\n"
-			  "numa_miss %lu\n"
-			  "numa_foreign %lu\n"
-			  "interleave_hit %lu\n"
-			  "local_node %lu\n"
-			  "other_node %lu\n",
-			  sum_zone_numa_state(dev->id, NUMA_HIT),
-			  sum_zone_numa_state(dev->id, NUMA_MISS),
-			  sum_zone_numa_state(dev->id, NUMA_FOREIGN),
-			  sum_zone_numa_state(dev->id, NUMA_INTERLEAVE_HIT),
-			  sum_zone_numa_state(dev->id, NUMA_LOCAL),
-			  sum_zone_numa_state(dev->id, NUMA_OTHER));
+	return sprintf(buf,
+		       "numa_hit %lu\n"
+		       "numa_miss %lu\n"
+		       "numa_foreign %lu\n"
+		       "interleave_hit %lu\n"
+		       "local_node %lu\n"
+		       "other_node %lu\n",
+		       sum_zone_numa_state(dev->id, NUMA_HIT),
+		       sum_zone_numa_state(dev->id, NUMA_MISS),
+		       sum_zone_numa_state(dev->id, NUMA_FOREIGN),
+		       sum_zone_numa_state(dev->id, NUMA_INTERLEAVE_HIT),
+		       sum_zone_numa_state(dev->id, NUMA_LOCAL),
+		       sum_zone_numa_state(dev->id, NUMA_OTHER));
 }
 static DEVICE_ATTR(numastat, S_IRUGO, node_read_numastat, NULL);
 
@@ -612,7 +612,7 @@ static ssize_t print_nodes_state(enum node_states state, char *buf)
 {
 	int n;
 
-	n = sysfs_emit(buf, "%*pbl",
+	n = scnprintf(buf, PAGE_SIZE - 1, "%*pbl",
 		      nodemask_pr_args(&node_states[state]));
 	buf[n++] = '\n';
 	buf[n] = '\0';
diff --git a/drivers/base/platform.c b/drivers/base/platform.c
index 1819da6889a7..2f89e618b142 100644
--- a/drivers/base/platform.c
+++ b/drivers/base/platform.c
@@ -927,7 +927,7 @@ static ssize_t driver_override_show(struct device *dev,
 	ssize_t len;
 
 	device_lock(dev);
-	len = sysfs_emit(buf, "%s\n", pdev->driver_override);
+	len = sprintf(buf, "%s\n", pdev->driver_override);
 	device_unlock(dev);
 	return len;
 }
diff --git a/drivers/base/power/sysfs.c b/drivers/base/power/sysfs.c
index c61b50aa1d81..d713738ce796 100644
--- a/drivers/base/power/sysfs.c
+++ b/drivers/base/power/sysfs.c
@@ -101,7 +101,7 @@ static const char ctrl_on[] = "on";
 static ssize_t control_show(struct device *dev, struct device_attribute *attr,
 			    char *buf)
 {
-	return sysfs_emit(buf, "%s\n",
+	return sprintf(buf, "%s\n",
 				dev->power.runtime_auto ? ctrl_auto : ctrl_on);
 }
 
@@ -127,7 +127,7 @@ static ssize_t runtime_active_time_show(struct device *dev,
 	int ret;
 	spin_lock_irq(&dev->power.lock);
 	update_pm_runtime_accounting(dev);
-	ret = sysfs_emit(buf, "%i\n", jiffies_to_msecs(dev->power.active_jiffies));
+	ret = sprintf(buf, "%i\n", jiffies_to_msecs(dev->power.active_jiffies));
 	spin_unlock_irq(&dev->power.lock);
 	return ret;
 }
@@ -140,7 +140,7 @@ static ssize_t runtime_suspended_time_show(struct device *dev,
 	int ret;
 	spin_lock_irq(&dev->power.lock);
 	update_pm_runtime_accounting(dev);
-	ret = sysfs_emit(buf, "%i\n",
+	ret = sprintf(buf, "%i\n",
 		jiffies_to_msecs(dev->power.suspended_jiffies));
 	spin_unlock_irq(&dev->power.lock);
 	return ret;
@@ -175,7 +175,7 @@ static ssize_t runtime_status_show(struct device *dev,
 			return -EIO;
 		}
 	}
-	return sysfs_emit(buf, p);
+	return sprintf(buf, p);
 }
 
 static DEVICE_ATTR_RO(runtime_status);
@@ -185,7 +185,7 @@ static ssize_t autosuspend_delay_ms_show(struct device *dev,
 {
 	if (!dev->power.use_autosuspend)
 		return -EIO;
-	return sysfs_emit(buf, "%d\n", dev->power.autosuspend_delay);
+	return sprintf(buf, "%d\n", dev->power.autosuspend_delay);
 }
 
 static ssize_t autosuspend_delay_ms_store(struct device *dev,
@@ -214,11 +214,11 @@ static ssize_t pm_qos_resume_latency_us_show(struct device *dev,
 	s32 value = dev_pm_qos_requested_resume_latency(dev);
 
 	if (value == 0)
-		return sysfs_emit(buf, "n/a\n");
+		return sprintf(buf, "n/a\n");
 	if (value == PM_QOS_RESUME_LATENCY_NO_CONSTRAINT)
 		value = 0;
 
-	return sysfs_emit(buf, "%d\n", value);
+	return sprintf(buf, "%d\n", value);
 }
 
 static ssize_t pm_qos_resume_latency_us_store(struct device *dev,
@@ -258,11 +258,11 @@ static ssize_t pm_qos_latency_tolerance_us_show(struct device *dev,
 	s32 value = dev_pm_qos_get_user_latency_tolerance(dev);
 
 	if (value < 0)
-		return sysfs_emit(buf, "auto\n");
+		return sprintf(buf, "auto\n");
 	if (value == PM_QOS_LATENCY_ANY)
-		return sysfs_emit(buf, "any\n");
+		return sprintf(buf, "any\n");
 
-	return sysfs_emit(buf, "%d\n", value);
+	return sprintf(buf, "%d\n", value);
 }
 
 static ssize_t pm_qos_latency_tolerance_us_store(struct device *dev,
@@ -294,8 +294,8 @@ static ssize_t pm_qos_no_power_off_show(struct device *dev,
 					struct device_attribute *attr,
 					char *buf)
 {
-	return sysfs_emit(buf, "%d\n", !!(dev_pm_qos_requested_flags(dev)
-					  & PM_QOS_FLAG_NO_POWER_OFF));
+	return sprintf(buf, "%d\n", !!(dev_pm_qos_requested_flags(dev)
+					& PM_QOS_FLAG_NO_POWER_OFF));
 }
 
 static ssize_t pm_qos_no_power_off_store(struct device *dev,
@@ -323,9 +323,9 @@ static const char _disabled[] = "disabled";
 static ssize_t wakeup_show(struct device *dev, struct device_attribute *attr,
 			   char *buf)
 {
-	return sysfs_emit(buf, "%s\n", device_can_wakeup(dev)
-			  ? (device_may_wakeup(dev) ? _enabled : _disabled)
-			  : "");
+	return sprintf(buf, "%s\n", device_can_wakeup(dev)
+		? (device_may_wakeup(dev) ? _enabled : _disabled)
+		: "");
 }
 
 static ssize_t wakeup_store(struct device *dev, struct device_attribute *attr,
@@ -511,7 +511,7 @@ static DEVICE_ATTR_RO(wakeup_prevent_sleep_time_ms);
 static ssize_t runtime_usage_show(struct device *dev,
 				  struct device_attribute *attr, char *buf)
 {
-	return sysfs_emit(buf, "%d\n", atomic_read(&dev->power.usage_count));
+	return sprintf(buf, "%d\n", atomic_read(&dev->power.usage_count));
 }
 static DEVICE_ATTR_RO(runtime_usage);
 
@@ -519,8 +519,8 @@ static ssize_t runtime_active_kids_show(struct device *dev,
 					struct device_attribute *attr,
 					char *buf)
 {
-	return sysfs_emit(buf, "%d\n", dev->power.ignore_children ?
-			  0 : atomic_read(&dev->power.child_count));
+	return sprintf(buf, "%d\n", dev->power.ignore_children ?
+		0 : atomic_read(&dev->power.child_count));
 }
 static DEVICE_ATTR_RO(runtime_active_kids);
 
@@ -528,12 +528,12 @@ static ssize_t runtime_enabled_show(struct device *dev,
 				    struct device_attribute *attr, char *buf)
 {
 	if (dev->power.disable_depth && (dev->power.runtime_auto == false))
-		return sysfs_emit(buf, "disabled & forbidden\n");
+		return sprintf(buf, "disabled & forbidden\n");
 	if (dev->power.disable_depth)
-		return sysfs_emit(buf, "disabled\n");
+		return sprintf(buf, "disabled\n");
 	if (dev->power.runtime_auto == false)
-		return sysfs_emit(buf, "forbidden\n");
-	return sysfs_emit(buf, "enabled\n");
+		return sprintf(buf, "forbidden\n");
+	return sprintf(buf, "enabled\n");
 }
 static DEVICE_ATTR_RO(runtime_enabled);
 
@@ -541,9 +541,9 @@ static DEVICE_ATTR_RO(runtime_enabled);
 static ssize_t async_show(struct device *dev, struct device_attribute *attr,
 			  char *buf)
 {
-	return sysfs_emit(buf, "%s\n",
-			  device_async_suspend_enabled(dev) ?
-			  _enabled : _disabled);
+	return sprintf(buf, "%s\n",
+			device_async_suspend_enabled(dev) ?
+				_enabled : _disabled);
 }
 
 static ssize_t async_store(struct device *dev, struct device_attribute *attr,
diff --git a/drivers/base/soc.c b/drivers/base/soc.c
index 23bc9eb794a2..7e91894a380b 100644
--- a/drivers/base/soc.c
+++ b/drivers/base/soc.c
@@ -72,13 +72,13 @@ static ssize_t soc_info_get(struct device *dev,
 	struct soc_device *soc_dev = container_of(dev, struct soc_device, dev);
 
 	if (attr == &dev_attr_machine)
-		return sysfs_emit(buf, "%s\n", soc_dev->attr->machine);
+		return sprintf(buf, "%s\n", soc_dev->attr->machine);
 	if (attr == &dev_attr_family)
-		return sysfs_emit(buf, "%s\n", soc_dev->attr->family);
+		return sprintf(buf, "%s\n", soc_dev->attr->family);
 	if (attr == &dev_attr_revision)
-		return sysfs_emit(buf, "%s\n", soc_dev->attr->revision);
+		return sprintf(buf, "%s\n", soc_dev->attr->revision);
 	if (attr == &dev_attr_soc_id)
-		return sysfs_emit(buf, "%s\n", soc_dev->attr->soc_id);
+		return sprintf(buf, "%s\n", soc_dev->attr->soc_id);
 
 	return -EINVAL;
 
-- 
GitLab


From ed829c9e67470baa7400b7455bf0098176ed4c6f Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Sat, 7 Oct 2023 13:50:27 +0200
Subject: [PATCH 143/298] media: dvb: symbol fixup for dvb_attach() - again

In commit f296b374b9c1 ("media: dvb: symbol fixup for dvb_attach()") in
the 4.19.y tree, a few symbols were missed due to files being renamed in
newer kernel versions.  Fix this up by properly marking up the
sp8870_attach and xc2028_attach symbols.

Reported-by: Ben Hutchings <ben@decadent.org.uk>
Link: https://lore.kernel.org/r/b12435b2311ada131db05d3cf195b4b5d87708eb.camel@decadent.org.uk
Fixes: f296b374b9c1 ("media: dvb: symbol fixup for dvb_attach()")
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/media/dvb-frontends/sp8870.c | 2 +-
 drivers/media/tuners/tuner-xc2028.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/media/dvb-frontends/sp8870.c b/drivers/media/dvb-frontends/sp8870.c
index 3a577788041d..c55bcd809458 100644
--- a/drivers/media/dvb-frontends/sp8870.c
+++ b/drivers/media/dvb-frontends/sp8870.c
@@ -619,4 +619,4 @@ MODULE_DESCRIPTION("Spase SP8870 DVB-T Demodulator driver");
 MODULE_AUTHOR("Juergen Peitz");
 MODULE_LICENSE("GPL");
 
-EXPORT_SYMBOL(sp8870_attach);
+EXPORT_SYMBOL_GPL(sp8870_attach);
diff --git a/drivers/media/tuners/tuner-xc2028.c b/drivers/media/tuners/tuner-xc2028.c
index aa6861dcd3fd..802a4d77f26b 100644
--- a/drivers/media/tuners/tuner-xc2028.c
+++ b/drivers/media/tuners/tuner-xc2028.c
@@ -1513,7 +1513,7 @@ struct dvb_frontend *xc2028_attach(struct dvb_frontend *fe,
 	return NULL;
 }
 
-EXPORT_SYMBOL(xc2028_attach);
+EXPORT_SYMBOL_GPL(xc2028_attach);
 
 MODULE_DESCRIPTION("Xceive xc2028/xc3028 tuner driver");
 MODULE_AUTHOR("Michel Ludwig <michel.ludwig@gmail.com>");
-- 
GitLab


From f736f1e791dbd953f920dbfaa37c9c689aa962ef Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Sat, 7 Oct 2023 13:57:34 +0200
Subject: [PATCH 144/298] Revert "PCI: qcom: Disable write access to read only
 registers for IP v2.3.3"

This reverts commit 3a4ecf4c9d793d0ecd07fc49cd76a2e24652d3b7 which is
commit a33d700e8eea76c62120cb3dbf5e01328f18319a upstream.

It was applied to the incorrect function as the original function the
commit changed is not in this kernel branch.

Reported-by: Ben Hutchings <ben@decadent.org.uk>
Link: https://lore.kernel.org/r/f23affddab4d8b3cc07508f2d8735d88d823821d.camel@decadent.org.uk
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index ea0cd2401d6b..133fad284c9f 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -758,8 +758,6 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
 	if (IS_ERR(res->phy_ahb_reset))
 		return PTR_ERR(res->phy_ahb_reset);
 
-	dw_pcie_dbi_ro_wr_dis(pci);
-
 	return 0;
 }
 
-- 
GitLab


From 7a65ee164a073eab2efd90c671905ef96957149d Mon Sep 17 00:00:00 2001
From: Dinghao Liu <dinghao.liu@zju.edu.cn>
Date: Sat, 23 Sep 2023 18:37:23 +0800
Subject: [PATCH 145/298] scsi: zfcp: Fix a double put in zfcp_port_enqueue()

commit b481f644d9174670b385c3a699617052cd2a79d3 upstream.

When device_register() fails, zfcp_port_release() will be called after
put_device(). As a result, zfcp_ccw_adapter_put() will be called twice: one
in zfcp_port_release() and one in the error path after device_register().
So the reference on the adapter object is doubly put, which may lead to a
premature free. Fix this by adjusting the error tag after
device_register().

Fixes: f3450c7b9172 ("[SCSI] zfcp: Replace local reference counting with common kref")
Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn>
Link: https://lore.kernel.org/r/20230923103723.10320-1-dinghao.liu@zju.edu.cn
Acked-by: Benjamin Block <bblock@linux.ibm.com>
Cc: stable@vger.kernel.org # v2.6.33+
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/s390/scsi/zfcp_aux.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/s390/scsi/zfcp_aux.c b/drivers/s390/scsi/zfcp_aux.c
index d1b531fe9ada..e5697ae9b4a3 100644
--- a/drivers/s390/scsi/zfcp_aux.c
+++ b/drivers/s390/scsi/zfcp_aux.c
@@ -493,12 +493,12 @@ struct zfcp_port *zfcp_port_enqueue(struct zfcp_adapter *adapter, u64 wwpn,
 	if (port) {
 		put_device(&port->dev);
 		retval = -EEXIST;
-		goto err_out;
+		goto err_put;
 	}
 
 	port = kzalloc(sizeof(struct zfcp_port), GFP_KERNEL);
 	if (!port)
-		goto err_out;
+		goto err_put;
 
 	rwlock_init(&port->unit_list_lock);
 	INIT_LIST_HEAD(&port->unit_list);
@@ -521,7 +521,7 @@ struct zfcp_port *zfcp_port_enqueue(struct zfcp_adapter *adapter, u64 wwpn,
 
 	if (dev_set_name(&port->dev, "0x%016llx", (unsigned long long)wwpn)) {
 		kfree(port);
-		goto err_out;
+		goto err_put;
 	}
 	retval = -EINVAL;
 
@@ -538,8 +538,9 @@ struct zfcp_port *zfcp_port_enqueue(struct zfcp_adapter *adapter, u64 wwpn,
 
 	return port;
 
-err_out:
+err_put:
 	zfcp_ccw_adapter_put(adapter);
+err_out:
 	return ERR_PTR(retval);
 }
 
-- 
GitLab


From 83f7ba5b02449727f03fbe7daee90f3bfa75cde3 Mon Sep 17 00:00:00 2001
From: "Gustavo A. R. Silva" <gustavoars@kernel.org>
Date: Sat, 23 Sep 2023 19:15:59 -0600
Subject: [PATCH 146/298] qed/red_ll2: Fix undefined behavior bug in struct
 qed_ll2_info

commit eea03d18af9c44235865a4bc9bec4d780ef6cf21 upstream.

The flexible structure (a structure that contains a flexible-array member
at the end) `qed_ll2_tx_packet` is nested within the second layer of
`struct qed_ll2_info`:

struct qed_ll2_tx_packet {
	...
        /* Flexible Array of bds_set determined by max_bds_per_packet */
        struct {
                struct core_tx_bd *txq_bd;
                dma_addr_t tx_frag;
                u16 frag_len;
        } bds_set[];
};

struct qed_ll2_tx_queue {
	...
	struct qed_ll2_tx_packet cur_completing_packet;
};

struct qed_ll2_info {
	...
	struct qed_ll2_tx_queue tx_queue;
        struct qed_ll2_cbs cbs;
};

The problem is that member `cbs` in `struct qed_ll2_info` is placed just
after an object of type `struct qed_ll2_tx_queue`, which is in itself
an implicit flexible structure, which by definition ends in a flexible
array member, in this case `bds_set`. This causes an undefined behavior
bug at run-time when dynamic memory is allocated for `bds_set`, which
could lead to a serious issue if `cbs` in `struct qed_ll2_info` is
overwritten by the contents of `bds_set`. Notice that the type of `cbs`
is a structure full of function pointers (and a cookie :) ):

include/linux/qed/qed_ll2_if.h:
107 typedef
108 void (*qed_ll2_complete_rx_packet_cb)(void *cxt,
109                                       struct qed_ll2_comp_rx_data *data);
110
111 typedef
112 void (*qed_ll2_release_rx_packet_cb)(void *cxt,
113                                      u8 connection_handle,
114                                      void *cookie,
115                                      dma_addr_t rx_buf_addr,
116                                      bool b_last_packet);
117
118 typedef
119 void (*qed_ll2_complete_tx_packet_cb)(void *cxt,
120                                       u8 connection_handle,
121                                       void *cookie,
122                                       dma_addr_t first_frag_addr,
123                                       bool b_last_fragment,
124                                       bool b_last_packet);
125
126 typedef
127 void (*qed_ll2_release_tx_packet_cb)(void *cxt,
128                                      u8 connection_handle,
129                                      void *cookie,
130                                      dma_addr_t first_frag_addr,
131                                      bool b_last_fragment, bool b_last_packet);
132
133 typedef
134 void (*qed_ll2_slowpath_cb)(void *cxt, u8 connection_handle,
135                             u32 opaque_data_0, u32 opaque_data_1);
136
137 struct qed_ll2_cbs {
138         qed_ll2_complete_rx_packet_cb rx_comp_cb;
139         qed_ll2_release_rx_packet_cb rx_release_cb;
140         qed_ll2_complete_tx_packet_cb tx_comp_cb;
141         qed_ll2_release_tx_packet_cb tx_release_cb;
142         qed_ll2_slowpath_cb slowpath_cb;
143         void *cookie;
144 };

Fix this by moving the declaration of `cbs` to the  middle of its
containing structure `qed_ll2_info`, preventing it from being
overwritten by the contents of `bds_set` at run-time.

This bug was introduced in 2017, when `bds_set` was converted to a
one-element array, and started to be used as a Variable Length Object
(VLO) at run-time.

Fixes: f5823fe6897c ("qed: Add ll2 option to limit the number of bds per packet")
Cc: stable@vger.kernel.org
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Reviewed-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://lore.kernel.org/r/ZQ+Nz8DfPg56pIzr@work
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/net/ethernet/qlogic/qed/qed_ll2.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/qlogic/qed/qed_ll2.h b/drivers/net/ethernet/qlogic/qed/qed_ll2.h
index f65817012e97..785899d3511c 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_ll2.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_ll2.h
@@ -122,9 +122,9 @@ struct qed_ll2_info {
 	enum core_tx_dest tx_dest;
 	u8 tx_stats_en;
 	bool main_func_queue;
+	struct qed_ll2_cbs cbs;
 	struct qed_ll2_rx_queue rx_queue;
 	struct qed_ll2_tx_queue tx_queue;
-	struct qed_ll2_cbs cbs;
 };
 
 /**
-- 
GitLab


From 284b51858f295815c98b3e8033d11b14853c35ce Mon Sep 17 00:00:00 2001
From: "Gustavo A. R. Silva" <gustavoars@kernel.org>
Date: Thu, 24 Aug 2023 21:06:51 -0600
Subject: [PATCH 147/298] wifi: mwifiex: Fix tlv_buf_left calculation

commit eec679e4ac5f47507774956fb3479c206e761af7 upstream.

In a TLV encoding scheme, the Length part represents the length after
the header containing the values for type and length. In this case,
`tlv_len` should be:

tlv_len == (sizeof(*tlv_rxba) - 1) - sizeof(tlv_rxba->header) + tlv_bitmap_len

Notice that the `- 1` accounts for the one-element array `bitmap`, which
1-byte size is already included in `sizeof(*tlv_rxba)`.

So, if the above is correct, there is a double-counting of some members
in `struct mwifiex_ie_types_rxba_sync`, when `tlv_buf_left` and `tmp`
are calculated:

968                 tlv_buf_left -= (sizeof(*tlv_rxba) + tlv_len);
969                 tmp = (u8 *)tlv_rxba + tlv_len + sizeof(*tlv_rxba);

in specific, members:

drivers/net/wireless/marvell/mwifiex/fw.h:777
 777         u8 mac[ETH_ALEN];
 778         u8 tid;
 779         u8 reserved;
 780         __le16 seq_num;
 781         __le16 bitmap_len;

This is clearly wrong, and affects the subsequent decoding of data in
`event_buf` through `tlv_rxba`:

970                 tlv_rxba = (struct mwifiex_ie_types_rxba_sync *)tmp;

Fix this by using `sizeof(tlv_rxba->header)` instead of `sizeof(*tlv_rxba)`
in the calculation of `tlv_buf_left` and `tmp`.

This results in the following binary differences before/after changes:

| drivers/net/wireless/marvell/mwifiex/11n_rxreorder.o
| @@ -4698,11 +4698,11 @@
|  drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c:968
|                 tlv_buf_left -= (sizeof(tlv_rxba->header) + tlv_len);
| -    1da7:      lea    -0x11(%rbx),%edx
| +    1da7:      lea    -0x4(%rbx),%edx
|      1daa:      movzwl %bp,%eax
|  drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c:969
|                 tmp = (u8 *)tlv_rxba  + sizeof(tlv_rxba->header) + tlv_len;
| -    1dad:      lea    0x11(%r15,%rbp,1),%r15
| +    1dad:      lea    0x4(%r15,%rbp,1),%r15

The above reflects the desired change: avoid counting 13 too many bytes;
which is the total size of the double-counted members in
`struct mwifiex_ie_types_rxba_sync`:

$ pahole -C mwifiex_ie_types_rxba_sync drivers/net/wireless/marvell/mwifiex/11n_rxreorder.o
struct mwifiex_ie_types_rxba_sync {
	struct mwifiex_ie_types_header header;           /*     0     4 */

     |-----------------------------------------------------------------------
     |  u8                         mac[6];               /*     4     6 */  |
     |	u8                         tid;                  /*    10     1 */  |
     |  u8                         reserved;             /*    11     1 */  |
     | 	__le16                     seq_num;              /*    12     2 */  |
     | 	__le16                     bitmap_len;           /*    14     2 */  |
     |  u8                         bitmap[1];            /*    16     1 */  |
     |----------------------------------------------------------------------|
								  | 13 bytes|
								  -----------

	/* size: 17, cachelines: 1, members: 7 */
	/* last cacheline: 17 bytes */
} __attribute__((__packed__));

Fixes: 99ffe72cdae4 ("mwifiex: process rxba_sync event")
Cc: stable@vger.kernel.org
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/06668edd68e7a26bbfeebd1201ae077a2a7a8bce.1692931954.git.gustavoars@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c b/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c
index 5380fba652cc..1aa0bcdab8ef 100644
--- a/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c
+++ b/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c
@@ -986,8 +986,8 @@ void mwifiex_11n_rxba_sync_event(struct mwifiex_private *priv,
 			}
 		}
 
-		tlv_buf_left -= (sizeof(*tlv_rxba) + tlv_len);
-		tmp = (u8 *)tlv_rxba + tlv_len + sizeof(*tlv_rxba);
+		tlv_buf_left -= (sizeof(tlv_rxba->header) + tlv_len);
+		tmp = (u8 *)tlv_rxba  + sizeof(tlv_rxba->header) + tlv_len;
 		tlv_rxba = (struct mwifiex_ie_types_rxba_sync *)tmp;
 	}
 }
-- 
GitLab


From 8ea00e1ba5aa2feccf6933b67828e98ace32112b Mon Sep 17 00:00:00 2001
From: Jordan Rife <jrife@google.com>
Date: Thu, 21 Sep 2023 18:46:40 -0500
Subject: [PATCH 148/298] net: replace calls to sock->ops->connect() with
 kernel_connect()

commit 26297b4ce1ce4ea40bc9a48ec99f45da3f64d2e2 upstream.

commit 0bdf399342c5 ("net: Avoid address overwrite in kernel_connect")
ensured that kernel_connect() will not overwrite the address parameter
in cases where BPF connect hooks perform an address rewrite. This change
replaces direct calls to sock->ops->connect() in net with kernel_connect()
to make these call safe.

Link: https://lore.kernel.org/netdev/20230912013332.2048422-1-jrife@google.com/
Fixes: d74bad4e74ee ("bpf: Hooks for sys_connect")
Cc: stable@vger.kernel.org
Reviewed-by: Willem de Bruijn <willemb@google.com>
Signed-off-by: Jordan Rife <jrife@google.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/netfilter/ipvs/ip_vs_sync.c | 4 ++--
 net/rds/tcp_connect.c           | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/net/netfilter/ipvs/ip_vs_sync.c b/net/netfilter/ipvs/ip_vs_sync.c
index f6af13c16cf5..e0a4f59a68a2 100644
--- a/net/netfilter/ipvs/ip_vs_sync.c
+++ b/net/netfilter/ipvs/ip_vs_sync.c
@@ -1510,8 +1510,8 @@ static int make_send_sock(struct netns_ipvs *ipvs, int id,
 	}
 
 	get_mcast_sockaddr(&mcast_addr, &salen, &ipvs->mcfg, id);
-	result = sock->ops->connect(sock, (struct sockaddr *) &mcast_addr,
-				    salen, 0);
+	result = kernel_connect(sock, (struct sockaddr *)&mcast_addr,
+				salen, 0);
 	if (result < 0) {
 		pr_err("Error connecting to the multicast addr\n");
 		goto error;
diff --git a/net/rds/tcp_connect.c b/net/rds/tcp_connect.c
index 008f50fb25dd..23d6d2612708 100644
--- a/net/rds/tcp_connect.c
+++ b/net/rds/tcp_connect.c
@@ -169,7 +169,7 @@ int rds_tcp_conn_path_connect(struct rds_conn_path *cp)
 	 * own the socket
 	 */
 	rds_tcp_set_callbacks(sock, cp);
-	ret = sock->ops->connect(sock, addr, addrlen, O_NONBLOCK);
+	ret = kernel_connect(sock, addr, addrlen, O_NONBLOCK);
 
 	rdsdebug("connect to address %pI6c returned %d\n", &conn->c_faddr, ret);
 	if (ret == -EINPROGRESS)
-- 
GitLab


From a0d71e9e61da8a85a46774c67549739e28fda795 Mon Sep 17 00:00:00 2001
From: Zhihao Cheng <chengzhihao1@huawei.com>
Date: Sun, 23 Apr 2023 19:10:41 +0800
Subject: [PATCH 149/298] ubi: Refuse attaching if mtd's erasesize is 0

[ Upstream commit 017c73a34a661a861712f7cc1393a123e5b2208c ]

There exists mtd devices with zero erasesize, which will trigger a
divide-by-zero exception while attaching ubi device.
Fix it by refusing attaching if mtd's erasesize is 0.

Fixes: 801c135ce73d ("UBI: Unsorted Block Images")
Reported-by: Yu Hao <yhao016@ucr.edu>
Link: https://lore.kernel.org/lkml/977347543.226888.1682011999468.JavaMail.zimbra@nod.at/T/
Signed-off-by: Zhihao Cheng <chengzhihao1@huawei.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Richard Weinberger <richard@nod.at>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/mtd/ubi/build.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index 3eb14c68cb9b..3e7e5b51eafd 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -878,6 +878,13 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num,
 		return -EINVAL;
 	}
 
+	/* UBI cannot work on flashes with zero erasesize. */
+	if (!mtd->erasesize) {
+		pr_err("ubi: refuse attaching mtd%d - zero erasesize flash is not supported\n",
+			mtd->index);
+		return -EINVAL;
+	}
+
 	if (ubi_num == UBI_DEV_NUM_AUTO) {
 		/* Search for an empty slot in the @ubi_devices array */
 		for (ubi_num = 0; ubi_num < UBI_MAX_DEVICES; ubi_num++)
-- 
GitLab


From 16cc18b9080892d1a0200a38e36ae52e464bc555 Mon Sep 17 00:00:00 2001
From: Pin-yen Lin <treapking@chromium.org>
Date: Fri, 8 Sep 2023 18:41:12 +0800
Subject: [PATCH 150/298] wifi: mwifiex: Fix oob check condition in
 mwifiex_process_rx_packet

[ Upstream commit aef7a0300047e7b4707ea0411dc9597cba108fc8 ]

Only skip the code path trying to access the rfc1042 headers when the
buffer is too small, so the driver can still process packets without
rfc1042 headers.

Fixes: 119585281617 ("wifi: mwifiex: Fix OOB and integer underflow when rx packets")
Signed-off-by: Pin-yen Lin <treapking@chromium.org>
Acked-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Matthew Wang <matthewmwang@chromium.org>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20230908104308.1546501-1-treapking@chromium.org
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/net/wireless/marvell/mwifiex/sta_rx.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/net/wireless/marvell/mwifiex/sta_rx.c b/drivers/net/wireless/marvell/mwifiex/sta_rx.c
index f3c6daeba1b8..346e91b9f2ad 100644
--- a/drivers/net/wireless/marvell/mwifiex/sta_rx.c
+++ b/drivers/net/wireless/marvell/mwifiex/sta_rx.c
@@ -98,7 +98,8 @@ int mwifiex_process_rx_packet(struct mwifiex_private *priv,
 	rx_pkt_len = le16_to_cpu(local_rx_pd->rx_pkt_length);
 	rx_pkt_hdr = (void *)local_rx_pd + rx_pkt_off;
 
-	if (sizeof(*rx_pkt_hdr) + rx_pkt_off > skb->len) {
+	if (sizeof(rx_pkt_hdr->eth803_hdr) + sizeof(rfc1042_header) +
+	    rx_pkt_off > skb->len) {
 		mwifiex_dbg(priv->adapter, ERROR,
 			    "wrong rx packet offset: len=%d, rx_pkt_off=%d\n",
 			    skb->len, rx_pkt_off);
@@ -107,12 +108,13 @@ int mwifiex_process_rx_packet(struct mwifiex_private *priv,
 		return -1;
 	}
 
-	if ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header,
-		     sizeof(bridge_tunnel_header))) ||
-	    (!memcmp(&rx_pkt_hdr->rfc1042_hdr, rfc1042_header,
-		     sizeof(rfc1042_header)) &&
-	     ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_AARP &&
-	     ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_IPX)) {
+	if (sizeof(*rx_pkt_hdr) + rx_pkt_off <= skb->len &&
+	    ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header,
+		      sizeof(bridge_tunnel_header))) ||
+	     (!memcmp(&rx_pkt_hdr->rfc1042_hdr, rfc1042_header,
+		      sizeof(rfc1042_header)) &&
+	      ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_AARP &&
+	      ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_IPX))) {
 		/*
 		 *  Replace the 803 header and rfc1042 header (llc/snap) with an
 		 *    EthernetII header, keep the src/dst and snap_type
-- 
GitLab


From ded67599d61cb9c7986c50a46a6f1043da56f57d Mon Sep 17 00:00:00 2001
From: Alexandra Diupina <adiupina@astralinux.ru>
Date: Tue, 19 Sep 2023 17:25:02 +0300
Subject: [PATCH 151/298] drivers/net: process the result of hdlc_open() and
 add call of hdlc_close() in uhdlc_close()

[ Upstream commit a59addacf899b1b21a7b7449a1c52c98704c2472 ]

Process the result of hdlc_open() and call uhdlc_close()
in case of an error. It is necessary to pass the error
code up the control flow, similar to a possible
error in request_irq().
Also add a hdlc_close() call to the uhdlc_close()
because the comment to hdlc_close() says it must be called
by the hardware driver when the HDLC device is being closed

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Fixes: c19b6d246a35 ("drivers/net: support hdlc function for QE-UCC")
Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/net/wan/fsl_ucc_hdlc.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
index 5df6e85e7ccb..c8cff000a931 100644
--- a/drivers/net/wan/fsl_ucc_hdlc.c
+++ b/drivers/net/wan/fsl_ucc_hdlc.c
@@ -37,6 +37,8 @@
 
 #define TDM_PPPOHT_SLIC_MAXIN
 
+static int uhdlc_close(struct net_device *dev);
+
 static struct ucc_tdm_info utdm_primary_info = {
 	.uf_info = {
 		.tsa = 0,
@@ -661,6 +663,7 @@ static int uhdlc_open(struct net_device *dev)
 	hdlc_device *hdlc = dev_to_hdlc(dev);
 	struct ucc_hdlc_private *priv = hdlc->priv;
 	struct ucc_tdm *utdm = priv->utdm;
+	int rc = 0;
 
 	if (priv->hdlc_busy != 1) {
 		if (request_irq(priv->ut_info->uf_info.irq,
@@ -683,10 +686,13 @@ static int uhdlc_open(struct net_device *dev)
 		netif_device_attach(priv->ndev);
 		napi_enable(&priv->napi);
 		netif_start_queue(dev);
-		hdlc_open(dev);
+
+		rc = hdlc_open(dev);
+		if (rc)
+			uhdlc_close(dev);
 	}
 
-	return 0;
+	return rc;
 }
 
 static void uhdlc_memclean(struct ucc_hdlc_private *priv)
@@ -775,6 +781,8 @@ static int uhdlc_close(struct net_device *dev)
 	netif_stop_queue(dev);
 	priv->hdlc_busy = 0;
 
+	hdlc_close(dev);
+
 	return 0;
 }
 
-- 
GitLab


From 1bddd95376c4bdb84fa5c53f641799925a537014 Mon Sep 17 00:00:00 2001
From: Richard Fitzgerald <rf@opensource.cirrus.com>
Date: Fri, 22 Sep 2023 16:37:11 +0100
Subject: [PATCH 152/298] regmap: rbtree: Fix wrong register marked as in-cache
 when creating new node

[ Upstream commit 7a795ac8d49e2433e1b97caf5e99129daf8e1b08 ]

When regcache_rbtree_write() creates a new rbtree_node it was passing the
wrong bit number to regcache_rbtree_set_register(). The bit number is the
offset __in number of registers__, but in the case of creating a new block
regcache_rbtree_write() was not dividing by the address stride to get the
number of registers.

Fix this by dividing by map->reg_stride.
Compare with regcache_rbtree_read() where the bit is checked.

This bug meant that the wrong register was marked as present. The register
that was written to the cache could not be read from the cache because it
was not marked as cached. But a nearby register could be marked as having
a cached value even if it was never written to the cache.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Fixes: 3f4ff561bc88 ("regmap: rbtree: Make cache_present bitmap per node")
Link: https://lore.kernel.org/r/20230922153711.28103-1-rf@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/base/regmap/regcache-rbtree.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/base/regmap/regcache-rbtree.c b/drivers/base/regmap/regcache-rbtree.c
index 7353c5527087..b6f8f4059e25 100644
--- a/drivers/base/regmap/regcache-rbtree.c
+++ b/drivers/base/regmap/regcache-rbtree.c
@@ -467,7 +467,8 @@ static int regcache_rbtree_write(struct regmap *map, unsigned int reg,
 		if (!rbnode)
 			return -ENOMEM;
 		regcache_rbtree_set_register(map, rbnode,
-					     reg - rbnode->base_reg, value);
+					     (reg - rbnode->base_reg) / map->reg_stride,
+					     value);
 		regcache_rbtree_insert(map, &rbtree_ctx->root, rbnode);
 		rbtree_ctx->cached_rbnode = rbnode;
 	}
-- 
GitLab


From e5ccce2c1d54c9303eb923554bb8412de5f8100e Mon Sep 17 00:00:00 2001
From: Junxiao Bi <junxiao.bi@oracle.com>
Date: Mon, 18 Sep 2023 15:58:48 -0700
Subject: [PATCH 153/298] scsi: target: core: Fix deadlock due to recursive
 locking

[ Upstream commit a154f5f643c6ecddd44847217a7a3845b4350003 ]

The following call trace shows a deadlock issue due to recursive locking of
mutex "device_mutex". First lock acquire is in target_for_each_device() and
second in target_free_device().

 PID: 148266   TASK: ffff8be21ffb5d00  CPU: 10   COMMAND: "iscsi_ttx"
  #0 [ffffa2bfc9ec3b18] __schedule at ffffffffa8060e7f
  #1 [ffffa2bfc9ec3ba0] schedule at ffffffffa8061224
  #2 [ffffa2bfc9ec3bb8] schedule_preempt_disabled at ffffffffa80615ee
  #3 [ffffa2bfc9ec3bc8] __mutex_lock at ffffffffa8062fd7
  #4 [ffffa2bfc9ec3c40] __mutex_lock_slowpath at ffffffffa80631d3
  #5 [ffffa2bfc9ec3c50] mutex_lock at ffffffffa806320c
  #6 [ffffa2bfc9ec3c68] target_free_device at ffffffffc0935998 [target_core_mod]
  #7 [ffffa2bfc9ec3c90] target_core_dev_release at ffffffffc092f975 [target_core_mod]
  #8 [ffffa2bfc9ec3ca0] config_item_put at ffffffffa79d250f
  #9 [ffffa2bfc9ec3cd0] config_item_put at ffffffffa79d2583
 #10 [ffffa2bfc9ec3ce0] target_devices_idr_iter at ffffffffc0933f3a [target_core_mod]
 #11 [ffffa2bfc9ec3d00] idr_for_each at ffffffffa803f6fc
 #12 [ffffa2bfc9ec3d60] target_for_each_device at ffffffffc0935670 [target_core_mod]
 #13 [ffffa2bfc9ec3d98] transport_deregister_session at ffffffffc0946408 [target_core_mod]
 #14 [ffffa2bfc9ec3dc8] iscsit_close_session at ffffffffc09a44a6 [iscsi_target_mod]
 #15 [ffffa2bfc9ec3df0] iscsit_close_connection at ffffffffc09a4a88 [iscsi_target_mod]
 #16 [ffffa2bfc9ec3df8] finish_task_switch at ffffffffa76e5d07
 #17 [ffffa2bfc9ec3e78] iscsit_take_action_for_connection_exit at ffffffffc0991c23 [iscsi_target_mod]
 #18 [ffffa2bfc9ec3ea0] iscsi_target_tx_thread at ffffffffc09a403b [iscsi_target_mod]
 #19 [ffffa2bfc9ec3f08] kthread at ffffffffa76d8080
 #20 [ffffa2bfc9ec3f50] ret_from_fork at ffffffffa8200364

Fixes: 36d4cb460bcb ("scsi: target: Avoid that EXTENDED COPY commands trigger lock inversion")
Signed-off-by: Junxiao Bi <junxiao.bi@oracle.com>
Link: https://lore.kernel.org/r/20230918225848.66463-1-junxiao.bi@oracle.com
Reviewed-by: Mike Christie <michael.christie@oracle.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/target/target_core_device.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/target/target_core_device.c b/drivers/target/target_core_device.c
index 1b381519c164..a23dcbe79e14 100644
--- a/drivers/target/target_core_device.c
+++ b/drivers/target/target_core_device.c
@@ -881,7 +881,6 @@ sector_t target_to_linux_sector(struct se_device *dev, sector_t lb)
 EXPORT_SYMBOL(target_to_linux_sector);
 
 struct devices_idr_iter {
-	struct config_item *prev_item;
 	int (*fn)(struct se_device *dev, void *data);
 	void *data;
 };
@@ -891,11 +890,9 @@ static int target_devices_idr_iter(int id, void *p, void *data)
 {
 	struct devices_idr_iter *iter = data;
 	struct se_device *dev = p;
+	struct config_item *item;
 	int ret;
 
-	config_item_put(iter->prev_item);
-	iter->prev_item = NULL;
-
 	/*
 	 * We add the device early to the idr, so it can be used
 	 * by backend modules during configuration. We do not want
@@ -905,12 +902,13 @@ static int target_devices_idr_iter(int id, void *p, void *data)
 	if (!target_dev_configured(dev))
 		return 0;
 
-	iter->prev_item = config_item_get_unless_zero(&dev->dev_group.cg_item);
-	if (!iter->prev_item)
+	item = config_item_get_unless_zero(&dev->dev_group.cg_item);
+	if (!item)
 		return 0;
 	mutex_unlock(&device_mutex);
 
 	ret = iter->fn(dev, iter->data);
+	config_item_put(item);
 
 	mutex_lock(&device_mutex);
 	return ret;
@@ -933,7 +931,6 @@ int target_for_each_device(int (*fn)(struct se_device *dev, void *data),
 	mutex_lock(&device_mutex);
 	ret = idr_for_each(&devices_idr, target_devices_idr_iter, &iter);
 	mutex_unlock(&device_mutex);
-	config_item_put(iter.prev_item);
 	return ret;
 }
 
-- 
GitLab


From 272ba9ebfb35b27c6bf31304e68b51fcc3bf5a95 Mon Sep 17 00:00:00 2001
From: Mauricio Faria de Oliveira <mfo@canonical.com>
Date: Thu, 28 Sep 2023 17:28:07 -0300
Subject: [PATCH 154/298] modpost: add missing else to the "of" check

[ Upstream commit cbc3d00cf88fda95dbcafee3b38655b7a8f2650a ]

Without this 'else' statement, an "usb" name goes into two handlers:
the first/previous 'if' statement _AND_ the for-loop over 'devtable',
but the latter is useless as it has no 'usb' device_id entry anyway.

Tested with allmodconfig before/after patch; no changes to *.mod.c:

    git checkout v6.6-rc3
    make -j$(nproc) allmodconfig
    make -j$(nproc) olddefconfig

    make -j$(nproc)
    find . -name '*.mod.c' | cpio -pd /tmp/before

    # apply patch

    make -j$(nproc)
    find . -name '*.mod.c' | cpio -pd /tmp/after

    diff -r /tmp/before/ /tmp/after/
    # no difference

Fixes: acbef7b76629 ("modpost: fix module autoloading for OF devices with generic compatible property")
Signed-off-by: Mauricio Faria de Oliveira <mfo@canonical.com>
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 scripts/mod/file2alias.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c
index 7f40b6aab689..90868df7865e 100644
--- a/scripts/mod/file2alias.c
+++ b/scripts/mod/file2alias.c
@@ -1395,7 +1395,7 @@ void handle_moddevtable(struct module *mod, struct elf_info *info,
 	/* First handle the "special" cases */
 	if (sym_is(name, namelen, "usb"))
 		do_usb_table(symval, sym->st_size, mod);
-	if (sym_is(name, namelen, "of"))
+	else if (sym_is(name, namelen, "of"))
 		do_of_table(symval, sym->st_size, mod);
 	else if (sym_is(name, namelen, "pnp"))
 		do_pnp_device_entry(symval, sym->st_size, mod);
-- 
GitLab


From 559d697c5d072593d22b3e0bd8b8081108aeaf59 Mon Sep 17 00:00:00 2001
From: David Howells <dhowells@redhat.com>
Date: Thu, 21 Sep 2023 11:41:19 +0100
Subject: [PATCH 155/298] ipv4, ipv6: Fix handling of transhdrlen in
 __ip{,6}_append_data()

[ Upstream commit 9d4c75800f61e5d75c1659ba201b6c0c7ead3070 ]

Including the transhdrlen in length is a problem when the packet is
partially filled (e.g. something like send(MSG_MORE) happened previously)
when appending to an IPv4 or IPv6 packet as we don't want to repeat the
transport header or account for it twice.  This can happen under some
circumstances, such as splicing into an L2TP socket.

The symptom observed is a warning in __ip6_append_data():

    WARNING: CPU: 1 PID: 5042 at net/ipv6/ip6_output.c:1800 __ip6_append_data.isra.0+0x1be8/0x47f0 net/ipv6/ip6_output.c:1800

that occurs when MSG_SPLICE_PAGES is used to append more data to an already
partially occupied skbuff.  The warning occurs when 'copy' is larger than
the amount of data in the message iterator.  This is because the requested
length includes the transport header length when it shouldn't.  This can be
triggered by, for example:

        sfd = socket(AF_INET6, SOCK_DGRAM, IPPROTO_L2TP);
        bind(sfd, ...); // ::1
        connect(sfd, ...); // ::1 port 7
        send(sfd, buffer, 4100, MSG_MORE);
        sendfile(sfd, dfd, NULL, 1024);

Fix this by only adding transhdrlen into the length if the write queue is
empty in l2tp_ip6_sendmsg(), analogously to how UDP does things.

l2tp_ip_sendmsg() looks like it won't suffer from this problem as it builds
the UDP packet itself.

Fixes: a32e0eec7042 ("l2tp: introduce L2TPv3 IP encapsulation support for IPv6")
Reported-by: syzbot+62cbf263225ae13ff153@syzkaller.appspotmail.com
Link: https://lore.kernel.org/r/0000000000001c12b30605378ce8@google.com/
Suggested-by: Willem de Bruijn <willemdebruijn.kernel@gmail.com>
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Eric Dumazet <edumazet@google.com>
cc: Willem de Bruijn <willemdebruijn.kernel@gmail.com>
cc: "David S. Miller" <davem@davemloft.net>
cc: David Ahern <dsahern@kernel.org>
cc: Paolo Abeni <pabeni@redhat.com>
cc: Jakub Kicinski <kuba@kernel.org>
cc: netdev@vger.kernel.org
cc: bpf@vger.kernel.org
cc: syzkaller-bugs@googlegroups.com
Reviewed-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/l2tp/l2tp_ip6.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/l2tp/l2tp_ip6.c b/net/l2tp/l2tp_ip6.c
index f3f0b4b7c386..7342344d99a9 100644
--- a/net/l2tp/l2tp_ip6.c
+++ b/net/l2tp/l2tp_ip6.c
@@ -525,7 +525,6 @@ static int l2tp_ip6_sendmsg(struct sock *sk, struct msghdr *msg, size_t len)
 	 */
 	if (len > INT_MAX - transhdrlen)
 		return -EMSGSIZE;
-	ulen = len + transhdrlen;
 
 	/* Mirror BSD error message compatibility */
 	if (msg->msg_flags & MSG_OOB)
@@ -649,6 +648,7 @@ static int l2tp_ip6_sendmsg(struct sock *sk, struct msghdr *msg, size_t len)
 
 back_from_confirm:
 	lock_sock(sk);
+	ulen = len + skb_queue_empty(&sk->sk_write_queue) ? transhdrlen : 0;
 	err = ip6_append_data(sk, ip_generic_getfrag, msg,
 			      ulen, transhdrlen, &ipc6,
 			      &fl6, (struct rt6_info *)dst,
-- 
GitLab


From 2a36d9e2995c8c3c3f179aab1215a69cff06cbed Mon Sep 17 00:00:00 2001
From: Shigeru Yoshida <syoshida@redhat.com>
Date: Sun, 24 Sep 2023 02:35:49 +0900
Subject: [PATCH 156/298] net: usb: smsc75xx: Fix uninit-value access in
 __smsc75xx_read_reg

[ Upstream commit e9c65989920f7c28775ec4e0c11b483910fb67b8 ]

syzbot reported the following uninit-value access issue:

=====================================================
BUG: KMSAN: uninit-value in smsc75xx_wait_ready drivers/net/usb/smsc75xx.c:975 [inline]
BUG: KMSAN: uninit-value in smsc75xx_bind+0x5c9/0x11e0 drivers/net/usb/smsc75xx.c:1482
CPU: 0 PID: 8696 Comm: kworker/0:3 Not tainted 5.8.0-rc5-syzkaller #0
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011
Workqueue: usb_hub_wq hub_event
Call Trace:
 __dump_stack lib/dump_stack.c:77 [inline]
 dump_stack+0x21c/0x280 lib/dump_stack.c:118
 kmsan_report+0xf7/0x1e0 mm/kmsan/kmsan_report.c:121
 __msan_warning+0x58/0xa0 mm/kmsan/kmsan_instr.c:215
 smsc75xx_wait_ready drivers/net/usb/smsc75xx.c:975 [inline]
 smsc75xx_bind+0x5c9/0x11e0 drivers/net/usb/smsc75xx.c:1482
 usbnet_probe+0x1152/0x3f90 drivers/net/usb/usbnet.c:1737
 usb_probe_interface+0xece/0x1550 drivers/usb/core/driver.c:374
 really_probe+0xf20/0x20b0 drivers/base/dd.c:529
 driver_probe_device+0x293/0x390 drivers/base/dd.c:701
 __device_attach_driver+0x63f/0x830 drivers/base/dd.c:807
 bus_for_each_drv+0x2ca/0x3f0 drivers/base/bus.c:431
 __device_attach+0x4e2/0x7f0 drivers/base/dd.c:873
 device_initial_probe+0x4a/0x60 drivers/base/dd.c:920
 bus_probe_device+0x177/0x3d0 drivers/base/bus.c:491
 device_add+0x3b0e/0x40d0 drivers/base/core.c:2680
 usb_set_configuration+0x380f/0x3f10 drivers/usb/core/message.c:2032
 usb_generic_driver_probe+0x138/0x300 drivers/usb/core/generic.c:241
 usb_probe_device+0x311/0x490 drivers/usb/core/driver.c:272
 really_probe+0xf20/0x20b0 drivers/base/dd.c:529
 driver_probe_device+0x293/0x390 drivers/base/dd.c:701
 __device_attach_driver+0x63f/0x830 drivers/base/dd.c:807
 bus_for_each_drv+0x2ca/0x3f0 drivers/base/bus.c:431
 __device_attach+0x4e2/0x7f0 drivers/base/dd.c:873
 device_initial_probe+0x4a/0x60 drivers/base/dd.c:920
 bus_probe_device+0x177/0x3d0 drivers/base/bus.c:491
 device_add+0x3b0e/0x40d0 drivers/base/core.c:2680
 usb_new_device+0x1bd4/0x2a30 drivers/usb/core/hub.c:2554
 hub_port_connect drivers/usb/core/hub.c:5208 [inline]
 hub_port_connect_change drivers/usb/core/hub.c:5348 [inline]
 port_event drivers/usb/core/hub.c:5494 [inline]
 hub_event+0x5e7b/0x8a70 drivers/usb/core/hub.c:5576
 process_one_work+0x1688/0x2140 kernel/workqueue.c:2269
 worker_thread+0x10bc/0x2730 kernel/workqueue.c:2415
 kthread+0x551/0x590 kernel/kthread.c:292
 ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:293

Local variable ----buf.i87@smsc75xx_bind created at:
 __smsc75xx_read_reg drivers/net/usb/smsc75xx.c:83 [inline]
 smsc75xx_wait_ready drivers/net/usb/smsc75xx.c:968 [inline]
 smsc75xx_bind+0x485/0x11e0 drivers/net/usb/smsc75xx.c:1482
 __smsc75xx_read_reg drivers/net/usb/smsc75xx.c:83 [inline]
 smsc75xx_wait_ready drivers/net/usb/smsc75xx.c:968 [inline]
 smsc75xx_bind+0x485/0x11e0 drivers/net/usb/smsc75xx.c:1482

This issue is caused because usbnet_read_cmd() reads less bytes than requested
(zero byte in the reproducer). In this case, 'buf' is not properly filled.

This patch fixes the issue by returning -ENODATA if usbnet_read_cmd() reads
less bytes than requested.

Fixes: d0cad871703b ("smsc75xx: SMSC LAN75xx USB gigabit ethernet adapter driver")
Reported-and-tested-by: syzbot+6966546b78d050bb0b5d@syzkaller.appspotmail.com
Closes: https://syzkaller.appspot.com/bug?extid=6966546b78d050bb0b5d
Signed-off-by: Shigeru Yoshida <syoshida@redhat.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://lore.kernel.org/r/20230923173549.3284502-1-syoshida@redhat.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/net/usb/smsc75xx.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/usb/smsc75xx.c b/drivers/net/usb/smsc75xx.c
index 313a4b0edc6b..573d7ad2e708 100644
--- a/drivers/net/usb/smsc75xx.c
+++ b/drivers/net/usb/smsc75xx.c
@@ -102,7 +102,9 @@ static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
 	ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
 		 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
 		 0, index, &buf, 4);
-	if (unlikely(ret < 0)) {
+	if (unlikely(ret < 4)) {
+		ret = ret < 0 ? ret : -ENODATA;
+
 		netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
 			    index, ret);
 		return ret;
-- 
GitLab


From 770cc2ea5a1dff5f211e120bd598a0daa37c5f53 Mon Sep 17 00:00:00 2001
From: Ben Wolsieffer <ben.wolsieffer@hefring.com>
Date: Wed, 27 Sep 2023 13:57:49 -0400
Subject: [PATCH 157/298] net: stmmac: dwmac-stm32: fix resume on STM32 MCU

[ Upstream commit 6f195d6b0da3b689922ba9e302af2f49592fa9fc ]

The STM32MP1 keeps clk_rx enabled during suspend, and therefore the
driver does not enable the clock in stm32_dwmac_init() if the device was
suspended. The problem is that this same code runs on STM32 MCUs, which
do disable clk_rx during suspend, causing the clock to never be
re-enabled on resume.

This patch adds a variant flag to indicate that clk_rx remains enabled
during suspend, and uses this to decide whether to enable the clock in
stm32_dwmac_init() if the device was suspended.

This approach fixes this specific bug with limited opportunity for
unintended side-effects, but I have a follow up patch that will refactor
the clock configuration and hopefully make it less error prone.

Fixes: 6528e02cc9ff ("net: ethernet: stmmac: add adaptation for stm32mp157c.")
Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com>
Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
Link: https://lore.kernel.org/r/20230927175749.1419774-1-ben.wolsieffer@hefring.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 7e2e79dedebf..df7fc6b675a5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -57,6 +57,7 @@ struct stm32_ops {
 	int (*parse_data)(struct stm32_dwmac *dwmac,
 			  struct device *dev);
 	u32 syscfg_eth_mask;
+	bool clk_rx_enable_in_suspend;
 };
 
 static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat)
@@ -74,7 +75,8 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat)
 	if (ret)
 		return ret;
 
-	if (!dwmac->dev->power.is_suspended) {
+	if (!dwmac->ops->clk_rx_enable_in_suspend ||
+	    !dwmac->dev->power.is_suspended) {
 		ret = clk_prepare_enable(dwmac->clk_rx);
 		if (ret) {
 			clk_disable_unprepare(dwmac->clk_tx);
@@ -413,7 +415,8 @@ static struct stm32_ops stm32mp1_dwmac_data = {
 	.suspend = stm32mp1_suspend,
 	.resume = stm32mp1_resume,
 	.parse_data = stm32mp1_parse_data,
-	.syscfg_eth_mask = SYSCFG_MP1_ETH_MASK
+	.syscfg_eth_mask = SYSCFG_MP1_ETH_MASK,
+	.clk_rx_enable_in_suspend = true
 };
 
 static const struct of_device_id stm32_dwmac_match[] = {
-- 
GitLab


From b86bfa833405ee615a5758cbe890ceb955dd7235 Mon Sep 17 00:00:00 2001
From: Neal Cardwell <ncardwell@google.com>
Date: Sun, 1 Oct 2023 11:12:38 -0400
Subject: [PATCH 158/298] tcp: fix quick-ack counting to count actual ACKs of
 new data

[ Upstream commit 059217c18be6757b95bfd77ba53fb50b48b8a816 ]

This commit fixes quick-ack counting so that it only considers that a
quick-ack has been provided if we are sending an ACK that newly
acknowledges data.

The code was erroneously using the number of data segments in outgoing
skbs when deciding how many quick-ack credits to remove. This logic
does not make sense, and could cause poor performance in
request-response workloads, like RPC traffic, where requests or
responses can be multi-segment skbs.

When a TCP connection decides to send N quick-acks, that is to
accelerate the cwnd growth of the congestion control module
controlling the remote endpoint of the TCP connection. That quick-ack
decision is purely about the incoming data and outgoing ACKs. It has
nothing to do with the outgoing data or the size of outgoing data.

And in particular, an ACK only serves the intended purpose of allowing
the remote congestion control to grow the congestion window quickly if
the ACK is ACKing or SACKing new data.

The fix is simple: only count packets as serving the goal of the
quickack mechanism if they are ACKing/SACKing new data. We can tell
whether this is the case by checking inet_csk_ack_scheduled(), since
we schedule an ACK exactly when we are ACKing/SACKing new data.

Fixes: fc6415bcb0f5 ("[TCP]: Fix quick-ack decrementing with TSO.")
Signed-off-by: Neal Cardwell <ncardwell@google.com>
Reviewed-by: Yuchung Cheng <ycheng@google.com>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Link: https://lore.kernel.org/r/20231001151239.1866845-1-ncardwell.sw@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 include/net/tcp.h     | 6 ++++--
 net/ipv4/tcp_output.c | 7 +++----
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/include/net/tcp.h b/include/net/tcp.h
index 9c43299ff870..427553adf82c 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -346,12 +346,14 @@ ssize_t tcp_splice_read(struct socket *sk, loff_t *ppos,
 			struct pipe_inode_info *pipe, size_t len,
 			unsigned int flags);
 
-static inline void tcp_dec_quickack_mode(struct sock *sk,
-					 const unsigned int pkts)
+static inline void tcp_dec_quickack_mode(struct sock *sk)
 {
 	struct inet_connection_sock *icsk = inet_csk(sk);
 
 	if (icsk->icsk_ack.quick) {
+		/* How many ACKs S/ACKing new data have we sent? */
+		const unsigned int pkts = inet_csk_ack_scheduled(sk) ? 1 : 0;
+
 		if (pkts >= icsk->icsk_ack.quick) {
 			icsk->icsk_ack.quick = 0;
 			/* Leaving quickack mode we deflate ATO. */
diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
index 9299de0da351..dcca9554071d 100644
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -164,8 +164,7 @@ static void tcp_event_data_sent(struct tcp_sock *tp,
 }
 
 /* Account for an ACK we sent. */
-static inline void tcp_event_ack_sent(struct sock *sk, unsigned int pkts,
-				      u32 rcv_nxt)
+static inline void tcp_event_ack_sent(struct sock *sk, u32 rcv_nxt)
 {
 	struct tcp_sock *tp = tcp_sk(sk);
 
@@ -179,7 +178,7 @@ static inline void tcp_event_ack_sent(struct sock *sk, unsigned int pkts,
 
 	if (unlikely(rcv_nxt != tp->rcv_nxt))
 		return;  /* Special ACK sent by DCTCP to reflect ECN */
-	tcp_dec_quickack_mode(sk, pkts);
+	tcp_dec_quickack_mode(sk);
 	inet_csk_clear_xmit_timer(sk, ICSK_TIME_DACK);
 }
 
@@ -1139,7 +1138,7 @@ static int __tcp_transmit_skb(struct sock *sk, struct sk_buff *skb,
 	icsk->icsk_af_ops->send_check(sk, skb);
 
 	if (likely(tcb->tcp_flags & TCPHDR_ACK))
-		tcp_event_ack_sent(sk, tcp_skb_pcount(skb), rcv_nxt);
+		tcp_event_ack_sent(sk, rcv_nxt);
 
 	if (skb->len != tcp_header_size) {
 		tcp_event_data_sent(tp, sk);
-- 
GitLab


From 9041b39020c2672f1ee7ca539aba09fdfd69e364 Mon Sep 17 00:00:00 2001
From: Neal Cardwell <ncardwell@google.com>
Date: Sun, 1 Oct 2023 11:12:39 -0400
Subject: [PATCH 159/298] tcp: fix delayed ACKs for MSS boundary condition

[ Upstream commit 4720852ed9afb1c5ab84e96135cb5b73d5afde6f ]

This commit fixes poor delayed ACK behavior that can cause poor TCP
latency in a particular boundary condition: when an application makes
a TCP socket write that is an exact multiple of the MSS size.

The problem is that there is painful boundary discontinuity in the
current delayed ACK behavior. With the current delayed ACK behavior,
we have:

(1) If an app reads data when > 1*MSS is unacknowledged, then
    tcp_cleanup_rbuf() ACKs immediately because of:

     tp->rcv_nxt - tp->rcv_wup > icsk->icsk_ack.rcv_mss ||

(2) If an app reads all received data, and the packets were < 1*MSS,
    and either (a) the app is not ping-pong or (b) we received two
    packets < 1*MSS, then tcp_cleanup_rbuf() ACKs immediately beecause
    of:

     ((icsk->icsk_ack.pending & ICSK_ACK_PUSHED2) ||
      ((icsk->icsk_ack.pending & ICSK_ACK_PUSHED) &&
       !inet_csk_in_pingpong_mode(sk))) &&

(3) *However*: if an app reads exactly 1*MSS of data,
    tcp_cleanup_rbuf() does not send an immediate ACK. This is true
    even if the app is not ping-pong and the 1*MSS of data had the PSH
    bit set, suggesting the sending application completed an
    application write.

Thus if the app is not ping-pong, we have this painful case where
>1*MSS gets an immediate ACK, and <1*MSS gets an immediate ACK, but a
write whose last skb is an exact multiple of 1*MSS can get a 40ms
delayed ACK. This means that any app that transfers data in one
direction and takes care to align write size or packet size with MSS
can suffer this problem. With receive zero copy making 4KB MSS values
more common, it is becoming more common to have application writes
naturally align with MSS, and more applications are likely to
encounter this delayed ACK problem.

The fix in this commit is to refine the delayed ACK heuristics with a
simple check: immediately ACK a received 1*MSS skb with PSH bit set if
the app reads all data. Why? If an skb has a len of exactly 1*MSS and
has the PSH bit set then it is likely the end of an application
write. So more data may not be arriving soon, and yet the data sender
may be waiting for an ACK if cwnd-bound or using TX zero copy. Thus we
set ICSK_ACK_PUSHED in this case so that tcp_cleanup_rbuf() will send
an ACK immediately if the app reads all of the data and is not
ping-pong. Note that this logic is also executed for the case where
len > MSS, but in that case this logic does not matter (and does not
hurt) because tcp_cleanup_rbuf() will always ACK immediately if the
app reads data and there is more than an MSS of unACKed data.

Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Signed-off-by: Neal Cardwell <ncardwell@google.com>
Reviewed-by: Yuchung Cheng <ycheng@google.com>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Cc: Xin Guo <guoxin0309@gmail.com>
Link: https://lore.kernel.org/r/20231001151239.1866845-2-ncardwell.sw@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/ipv4/tcp_input.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c
index 9e1ec69fe5b4..0052a6194cc1 100644
--- a/net/ipv4/tcp_input.c
+++ b/net/ipv4/tcp_input.c
@@ -172,6 +172,19 @@ static void tcp_measure_rcv_mss(struct sock *sk, const struct sk_buff *skb)
 		if (unlikely(len > icsk->icsk_ack.rcv_mss +
 				   MAX_TCP_OPTION_SPACE))
 			tcp_gro_dev_warn(sk, skb, len);
+		/* If the skb has a len of exactly 1*MSS and has the PSH bit
+		 * set then it is likely the end of an application write. So
+		 * more data may not be arriving soon, and yet the data sender
+		 * may be waiting for an ACK if cwnd-bound or using TX zero
+		 * copy. So we set ICSK_ACK_PUSHED here so that
+		 * tcp_cleanup_rbuf() will send an ACK immediately if the app
+		 * reads all of the data and is not ping-pong. If len > MSS
+		 * then this logic does not matter (and does not hurt) because
+		 * tcp_cleanup_rbuf() will always ACK immediately if the app
+		 * reads data and there is more than an MSS of unACKed data.
+		 */
+		if (TCP_SKB_CB(skb)->tcp_flags & TCPHDR_PSH)
+			icsk->icsk_ack.pending |= ICSK_ACK_PUSHED;
 	} else {
 		/* Otherwise, we make more careful check taking into account,
 		 * that SACKs block is variable.
-- 
GitLab


From 698c4642055a0266029d28ee157f2b599051c6f6 Mon Sep 17 00:00:00 2001
From: Xin Long <lucien.xin@gmail.com>
Date: Sun, 1 Oct 2023 10:58:45 -0400
Subject: [PATCH 160/298] sctp: update transport state when processing a
 dupcook packet

[ Upstream commit 2222a78075f0c19ca18db53fd6623afb4aff602d ]

During the 4-way handshake, the transport's state is set to ACTIVE in
sctp_process_init() when processing INIT_ACK chunk on client or
COOKIE_ECHO chunk on server.

In the collision scenario below:

  192.168.1.2 > 192.168.1.1: sctp (1) [INIT] [init tag: 3922216408]
    192.168.1.1 > 192.168.1.2: sctp (1) [INIT] [init tag: 144230885]
    192.168.1.2 > 192.168.1.1: sctp (1) [INIT ACK] [init tag: 3922216408]
    192.168.1.1 > 192.168.1.2: sctp (1) [COOKIE ECHO]
    192.168.1.2 > 192.168.1.1: sctp (1) [COOKIE ACK]
  192.168.1.1 > 192.168.1.2: sctp (1) [INIT ACK] [init tag: 3914796021]

when processing COOKIE_ECHO on 192.168.1.2, as it's in COOKIE_WAIT state,
sctp_sf_do_dupcook_b() is called by sctp_sf_do_5_2_4_dupcook() where it
creates a new association and sets its transport to ACTIVE then updates
to the old association in sctp_assoc_update().

However, in sctp_assoc_update(), it will skip the transport update if it
finds a transport with the same ipaddr already existing in the old asoc,
and this causes the old asoc's transport state not to move to ACTIVE
after the handshake.

This means if DATA retransmission happens at this moment, it won't be able
to enter PF state because of the check 'transport->state == SCTP_ACTIVE'
in sctp_do_8_2_transport_strike().

This patch fixes it by updating the transport in sctp_assoc_update() with
sctp_assoc_add_peer() where it updates the transport state if there is
already a transport with the same ipaddr exists in the old asoc.

Signed-off-by: Xin Long <lucien.xin@gmail.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Link: https://lore.kernel.org/r/fd17356abe49713ded425250cc1ae51e9f5846c6.1696172325.git.lucien.xin@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/sctp/associola.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/net/sctp/associola.c b/net/sctp/associola.c
index d17708800652..78c1429d1301 100644
--- a/net/sctp/associola.c
+++ b/net/sctp/associola.c
@@ -1181,8 +1181,7 @@ int sctp_assoc_update(struct sctp_association *asoc,
 		/* Add any peer addresses from the new association. */
 		list_for_each_entry(trans, &new->peer.transport_addr_list,
 				    transports)
-			if (!sctp_assoc_lookup_paddr(asoc, &trans->ipaddr) &&
-			    !sctp_assoc_add_peer(asoc, &trans->ipaddr,
+			if (!sctp_assoc_add_peer(asoc, &trans->ipaddr,
 						 GFP_ATOMIC, trans->state))
 				return -ENOMEM;
 
-- 
GitLab


From 84b62072e3062ce60d2268383ad9ede92a2d03bc Mon Sep 17 00:00:00 2001
From: Xin Long <lucien.xin@gmail.com>
Date: Sun, 1 Oct 2023 11:04:20 -0400
Subject: [PATCH 161/298] sctp: update hb timer immediately after users change
 hb_interval

[ Upstream commit 1f4e803cd9c9166eb8b6c8b0b8e4124f7499fc07 ]

Currently, when hb_interval is changed by users, it won't take effect
until the next expiry of hb timer. As the default value is 30s, users
have to wait up to 30s to wait its hb_interval update to work.

This becomes pretty bad in containers where a much smaller value is
usually set on hb_interval. This patch improves it by resetting the
hb timer immediately once the value of hb_interval is updated by users.

Note that we don't address the already existing 'problem' when sending
a heartbeat 'on demand' if one hb has just been sent(from the timer)
mentioned in:

  https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg590224.html

Signed-off-by: Xin Long <lucien.xin@gmail.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2")
Link: https://lore.kernel.org/r/75465785f8ee5df2fb3acdca9b8fafdc18984098.1696172660.git.lucien.xin@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/sctp/socket.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/net/sctp/socket.c b/net/sctp/socket.c
index 432dccd37506..f954d3c8876d 100644
--- a/net/sctp/socket.c
+++ b/net/sctp/socket.c
@@ -2578,6 +2578,7 @@ static int sctp_apply_peer_addr_params(struct sctp_paddrparams *params,
 			if (trans) {
 				trans->hbinterval =
 				    msecs_to_jiffies(params->spp_hbinterval);
+				sctp_transport_reset_hb_timer(trans);
 			} else if (asoc) {
 				asoc->hbinterval =
 				    msecs_to_jiffies(params->spp_hbinterval);
-- 
GitLab


From 5500293194dfacb4f46a88ba909ae2eb5b3e7b7f Mon Sep 17 00:00:00 2001
From: Ivan Babrou <ivan@cloudflare.com>
Date: Mon, 4 Jan 2021 15:57:18 -0800
Subject: [PATCH 162/298] cpupower: add Makefile dependencies for install
 targets

commit fb7791e213a64495ec2336869b868fcd8af14346 upstream.

This allows building cpupower in parallel rather than serially.

Signed-off-by: Ivan Babrou <ivan@cloudflare.com>
Signed-off-by: Shuah Khan <skhan@linuxfoundation.org>
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 tools/power/cpupower/Makefile       | 8 ++++----
 tools/power/cpupower/bench/Makefile | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/tools/power/cpupower/Makefile b/tools/power/cpupower/Makefile
index 1dd5f4fcffd5..392906c8d3a6 100644
--- a/tools/power/cpupower/Makefile
+++ b/tools/power/cpupower/Makefile
@@ -278,14 +278,14 @@ clean:
 	$(MAKE) -C bench O=$(OUTPUT) clean
 
 
-install-lib:
+install-lib: libcpupower
 	$(INSTALL) -d $(DESTDIR)${libdir}
 	$(CP) $(OUTPUT)libcpupower.so* $(DESTDIR)${libdir}/
 	$(INSTALL) -d $(DESTDIR)${includedir}
 	$(INSTALL_DATA) lib/cpufreq.h $(DESTDIR)${includedir}/cpufreq.h
 	$(INSTALL_DATA) lib/cpuidle.h $(DESTDIR)${includedir}/cpuidle.h
 
-install-tools:
+install-tools: $(OUTPUT)cpupower
 	$(INSTALL) -d $(DESTDIR)${bindir}
 	$(INSTALL_PROGRAM) $(OUTPUT)cpupower $(DESTDIR)${bindir}
 
@@ -299,14 +299,14 @@ install-man:
 	$(INSTALL_DATA) -D man/cpupower-info.1 $(DESTDIR)${mandir}/man1/cpupower-info.1
 	$(INSTALL_DATA) -D man/cpupower-monitor.1 $(DESTDIR)${mandir}/man1/cpupower-monitor.1
 
-install-gmo:
+install-gmo: create-gmo
 	$(INSTALL) -d $(DESTDIR)${localedir}
 	for HLANG in $(LANGUAGES); do \
 		echo '$(INSTALL_DATA) -D $(OUTPUT)po/$$HLANG.gmo $(DESTDIR)${localedir}/$$HLANG/LC_MESSAGES/cpupower.mo'; \
 		$(INSTALL_DATA) -D $(OUTPUT)po/$$HLANG.gmo $(DESTDIR)${localedir}/$$HLANG/LC_MESSAGES/cpupower.mo; \
 	done;
 
-install-bench:
+install-bench: compile-bench
 	@#DESTDIR must be set from outside to survive
 	@sbindir=$(sbindir) bindir=$(bindir) docdir=$(docdir) confdir=$(confdir) $(MAKE) -C bench O=$(OUTPUT) install
 
diff --git a/tools/power/cpupower/bench/Makefile b/tools/power/cpupower/bench/Makefile
index f68b4bc55273..d9d9923af85c 100644
--- a/tools/power/cpupower/bench/Makefile
+++ b/tools/power/cpupower/bench/Makefile
@@ -27,7 +27,7 @@ $(OUTPUT)cpufreq-bench: $(OBJS)
 
 all: $(OUTPUT)cpufreq-bench
 
-install:
+install: $(OUTPUT)cpufreq-bench
 	mkdir -p $(DESTDIR)/$(sbindir)
 	mkdir -p $(DESTDIR)/$(bindir)
 	mkdir -p $(DESTDIR)/$(docdir)
-- 
GitLab


From 7ddb0a57f66928958a82d1e8cc4558da8a1bf1ee Mon Sep 17 00:00:00 2001
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Date: Sat, 23 Sep 2023 07:55:56 +0200
Subject: [PATCH 163/298] IB/mlx4: Fix the size of a buffer in
 add_port_entries()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

commit d7f393430a17c2bfcdf805462a5aa80be4285b27 upstream.

In order to be sure that 'buff' is never truncated, its size should be
12, not 11.

When building with W=1, this fixes the following warnings:

  drivers/infiniband/hw/mlx4/sysfs.c: In function ‘add_port_entries’:
  drivers/infiniband/hw/mlx4/sysfs.c:268:34: error: ‘sprintf’ may write a terminating nul past the end of the destination [-Werror=format-overflow=]
    268 |                 sprintf(buff, "%d", i);
        |                                  ^
  drivers/infiniband/hw/mlx4/sysfs.c:268:17: note: ‘sprintf’ output between 2 and 12 bytes into a destination of size 11
    268 |                 sprintf(buff, "%d", i);
        |                 ^~~~~~~~~~~~~~~~~~~~~~
  drivers/infiniband/hw/mlx4/sysfs.c:286:34: error: ‘sprintf’ may write a terminating nul past the end of the destination [-Werror=format-overflow=]
    286 |                 sprintf(buff, "%d", i);
        |                                  ^
  drivers/infiniband/hw/mlx4/sysfs.c:286:17: note: ‘sprintf’ output between 2 and 12 bytes into a destination of size 11
    286 |                 sprintf(buff, "%d", i);
        |                 ^~~~~~~~~~~~~~~~~~~~~~

Fixes: c1e7e466120b ("IB/mlx4: Add iov directory in sysfs under the ib device")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/0bb1443eb47308bc9be30232cc23004c4d4cf43e.1695448530.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/infiniband/hw/mlx4/sysfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/infiniband/hw/mlx4/sysfs.c b/drivers/infiniband/hw/mlx4/sysfs.c
index d2da28d613f2..eb95292d12dc 100644
--- a/drivers/infiniband/hw/mlx4/sysfs.c
+++ b/drivers/infiniband/hw/mlx4/sysfs.c
@@ -221,7 +221,7 @@ void del_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num,
 static int add_port_entries(struct mlx4_ib_dev *device, int port_num)
 {
 	int i;
-	char buff[11];
+	char buff[12];
 	struct mlx4_ib_iov_port *port = NULL;
 	int ret = 0 ;
 	struct ib_port_attr attr;
-- 
GitLab


From 007282b8b1e016c818126ae2dffe804359d3ef1c Mon Sep 17 00:00:00 2001
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Date: Tue, 3 Oct 2023 09:39:26 +0200
Subject: [PATCH 164/298] gpio: aspeed: fix the GPIO number passed to
 pinctrl_gpio_set_config()

commit f9315f17bf778cb8079a29639419fcc8a41a3c84 upstream.

pinctrl_gpio_set_config() expects the GPIO number from the global GPIO
numberspace, not the controller-relative offset, which needs to be added
to the chip base.

Fixes: 5ae4cb94b313 ("gpio: aspeed: Add debounce support")
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/gpio/gpio-aspeed.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
index e627e0e9001a..ba1cd971d50b 100644
--- a/drivers/gpio/gpio-aspeed.c
+++ b/drivers/gpio/gpio-aspeed.c
@@ -999,7 +999,7 @@ static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
 	else if (param == PIN_CONFIG_BIAS_DISABLE ||
 			param == PIN_CONFIG_BIAS_PULL_DOWN ||
 			param == PIN_CONFIG_DRIVE_STRENGTH)
-		return pinctrl_gpio_set_config(offset, config);
+		return pinctrl_gpio_set_config(chip->base + offset, config);
 	else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN ||
 			param == PIN_CONFIG_DRIVE_OPEN_SOURCE)
 		/* Return -ENOTSUPP to trigger emulation, as per datasheet */
-- 
GitLab


From 0db6d5496a1918a0f322a4a4cfa23cd16f0bc464 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= <duje.mihanovic@skole.hr>
Date: Fri, 29 Sep 2023 17:41:57 +0200
Subject: [PATCH 165/298] gpio: pxa: disable pinctrl calls for MMP_GPIO
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

commit f0575116507b981e6a810e78ce3c9040395b958b upstream.

Similarly to PXA3xx and MMP2, pinctrl-single isn't capable of setting
pin direction on MMP either.

Fixes: a770d946371e ("gpio: pxa: add pin control gpio direction and request")
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/gpio/gpio-pxa.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index bcc6be4a5cb2..61df316e0d17 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -246,6 +246,7 @@ static bool pxa_gpio_has_pinctrl(void)
 	switch (gpio_type) {
 	case PXA3XX_GPIO:
 	case MMP2_GPIO:
+	case MMP_GPIO:
 		return false;
 
 	default:
-- 
GitLab


From c0dab6e9284eff3d4203beb787a4f761a5091dd2 Mon Sep 17 00:00:00 2001
From: Leon Romanovsky <leonro@nvidia.com>
Date: Mon, 11 Sep 2023 15:18:06 +0300
Subject: [PATCH 166/298] RDMA/cma: Fix truncation compilation warning in
 make_cma_ports
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

commit 18126c767658ae8a831257c6cb7776c5ba5e7249 upstream.

The following compilation error is false alarm as RDMA devices don't
have such large amount of ports to actually cause to format truncation.

drivers/infiniband/core/cma_configfs.c: In function ‘make_cma_ports’:
drivers/infiniband/core/cma_configfs.c:223:57: error: ‘snprintf’ output may be truncated before the last format character [-Werror=format-truncation=]
  223 |                 snprintf(port_str, sizeof(port_str), "%u", i + 1);
      |                                                         ^
drivers/infiniband/core/cma_configfs.c:223:17: note: ‘snprintf’ output between 2 and 11 bytes into a destination of size 10
  223 |                 snprintf(port_str, sizeof(port_str), "%u", i + 1);
      |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
make[5]: *** [scripts/Makefile.build:243: drivers/infiniband/core/cma_configfs.o] Error 1

Fixes: 045959db65c6 ("IB/cma: Add configfs for rdma_cm")
Link: https://lore.kernel.org/r/a7e3b347ee134167fa6a3787c56ef231a04bc8c2.1694434639.git.leonro@nvidia.com
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/infiniband/core/cma_configfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/infiniband/core/cma_configfs.c b/drivers/infiniband/core/cma_configfs.c
index ce183d054785..f9b0303b3a01 100644
--- a/drivers/infiniband/core/cma_configfs.c
+++ b/drivers/infiniband/core/cma_configfs.c
@@ -215,7 +215,7 @@ static int make_cma_ports(struct cma_dev_group *cma_dev_group,
 	}
 
 	for (i = 0; i < ports_num; i++) {
-		char port_str[10];
+		char port_str[11];
 
 		ports[i].port_num = i + 1;
 		snprintf(port_str, sizeof(port_str), "%u", i + 1);
-- 
GitLab


From 423667bfe9304530d0c3dfd35669421d9d825d9a Mon Sep 17 00:00:00 2001
From: Shay Drory <shayd@nvidia.com>
Date: Wed, 20 Sep 2023 13:01:56 +0300
Subject: [PATCH 167/298] RDMA/mlx5: Fix NULL string error

commit dab994bcc609a172bfdab15a0d4cb7e50e8b5458 upstream.

checkpath is complaining about NULL string, change it to 'Unknown'.

Fixes: 37aa5c36aa70 ("IB/mlx5: Add UARs write-combining and non-cached mapping")
Signed-off-by: Shay Drory <shayd@nvidia.com>
Link: https://lore.kernel.org/r/8638e5c14fadbde5fa9961874feae917073af920.1695203958.git.leonro@nvidia.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/infiniband/hw/mlx5/main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c
index 1688c06d5c3c..f7df27c7c634 100644
--- a/drivers/infiniband/hw/mlx5/main.c
+++ b/drivers/infiniband/hw/mlx5/main.c
@@ -2005,7 +2005,7 @@ static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
 	case MLX5_IB_MMAP_DEVICE_MEM:
 		return "Device Memory";
 	default:
-		return NULL;
+		return "Unknown";
 	}
 }
 
-- 
GitLab


From a7796ccd3b5731fc1e065c12c313e987c0daecdc Mon Sep 17 00:00:00 2001
From: John David Anglin <dave@parisc-linux.org>
Date: Tue, 19 Sep 2023 17:51:40 +0000
Subject: [PATCH 168/298] parisc: Restore __ldcw_align for PA-RISC 2.0
 processors

commit 914988e099fc658436fbd7b8f240160c352b6552 upstream.

Back in 2005, Kyle McMartin removed the 16-byte alignment for
ldcw semaphores on PA 2.0 machines (CONFIG_PA20). This broke
spinlocks on pre PA8800 processors. The main symptom was random
faults in mmap'd memory (e.g., gcc compilations, etc).

Unfortunately, the errata for this ldcw change is lost.

The issue is the 16-byte alignment required for ldcw semaphore
instructions can only be reduced to natural alignment when the
ldcw operation can be handled coherently in cache. Only PA8800
and PA8900 processors actually support doing the operation in
cache.

Aligning the spinlock dynamically adds two integer instructions
to each spinlock.

Tested on rp3440, c8000 and a500.

Signed-off-by: John David Anglin <dave.anglin@bell.net>
Link: https://lore.kernel.org/linux-parisc/6b332788-2227-127f-ba6d-55e99ecf4ed8@bell.net/T/#t
Link: https://lore.kernel.org/linux-parisc/20050609050702.GB4641@roadwarrior.mcmartin.ca/
Cc: stable@vger.kernel.org
Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 arch/parisc/include/asm/ldcw.h           | 36 +++++++++++++-----------
 arch/parisc/include/asm/spinlock_types.h |  5 ----
 2 files changed, 20 insertions(+), 21 deletions(-)

diff --git a/arch/parisc/include/asm/ldcw.h b/arch/parisc/include/asm/ldcw.h
index 3eb4bfc1fb36..5ed52819e956 100644
--- a/arch/parisc/include/asm/ldcw.h
+++ b/arch/parisc/include/asm/ldcw.h
@@ -2,14 +2,28 @@
 #ifndef __PARISC_LDCW_H
 #define __PARISC_LDCW_H
 
-#ifndef CONFIG_PA20
 /* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
    and GCC only guarantees 8-byte alignment for stack locals, we can't
    be assured of 16-byte alignment for atomic lock data even if we
    specify "__attribute ((aligned(16)))" in the type declaration.  So,
    we use a struct containing an array of four ints for the atomic lock
    type and dynamically select the 16-byte aligned int from the array
-   for the semaphore.  */
+   for the semaphore. */
+
+/* From: "Jim Hull" <jim.hull of hp.com>
+   I've attached a summary of the change, but basically, for PA 2.0, as
+   long as the ",CO" (coherent operation) completer is implemented, then the
+   16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
+   they only require "natural" alignment (4-byte for ldcw, 8-byte for
+   ldcd).
+
+   Although the cache control hint is accepted by all PA 2.0 processors,
+   it is only implemented on PA8800/PA8900 CPUs. Prior PA8X00 CPUs still
+   require 16-byte alignment. If the address is unaligned, the operation
+   of the instruction is undefined. The ldcw instruction does not generate
+   unaligned data reference traps so misaligned accesses are not detected.
+   This hid the problem for years. So, restore the 16-byte alignment dropped
+   by Kyle McMartin in "Remove __ldcw_align for PA-RISC 2.0 processors". */
 
 #define __PA_LDCW_ALIGNMENT	16
 #define __PA_LDCW_ALIGN_ORDER	4
@@ -19,22 +33,12 @@
 		& ~(__PA_LDCW_ALIGNMENT - 1);			\
 	(volatile unsigned int *) __ret;			\
 })
-#define __LDCW	"ldcw"
 
-#else /*CONFIG_PA20*/
-/* From: "Jim Hull" <jim.hull of hp.com>
-   I've attached a summary of the change, but basically, for PA 2.0, as
-   long as the ",CO" (coherent operation) completer is specified, then the
-   16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
-   they only require "natural" alignment (4-byte for ldcw, 8-byte for
-   ldcd). */
-
-#define __PA_LDCW_ALIGNMENT	4
-#define __PA_LDCW_ALIGN_ORDER	2
-#define __ldcw_align(a) (&(a)->slock)
+#ifdef CONFIG_PA20
 #define __LDCW	"ldcw,co"
-
-#endif /*!CONFIG_PA20*/
+#else
+#define __LDCW	"ldcw"
+#endif
 
 /* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.
    We don't explicitly expose that "*a" may be written as reload
diff --git a/arch/parisc/include/asm/spinlock_types.h b/arch/parisc/include/asm/spinlock_types.h
index 42979c5704dc..82d2384c3f22 100644
--- a/arch/parisc/include/asm/spinlock_types.h
+++ b/arch/parisc/include/asm/spinlock_types.h
@@ -3,13 +3,8 @@
 #define __ASM_SPINLOCK_TYPES_H
 
 typedef struct {
-#ifdef CONFIG_PA20
-	volatile unsigned int slock;
-# define __ARCH_SPIN_LOCK_UNLOCKED { 1 }
-#else
 	volatile unsigned int lock[4];
 # define __ARCH_SPIN_LOCK_UNLOCKED	{ { 1, 1, 1, 1 } }
-#endif
 } arch_spinlock_t;
 
 typedef struct {
-- 
GitLab


From 62c218124fe58372e0e1f60d5b634d21c264b337 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Fri, 15 Sep 2023 19:00:35 +0000
Subject: [PATCH 169/298] dccp: fix dccp_v4_err()/dccp_v6_err() again

commit 6af289746a636f71f4c0535a9801774118486c7a upstream.

dh->dccph_x is the 9th byte (offset 8) in "struct dccp_hdr",
not in the "byte 7" as Jann claimed.

We need to make sure the ICMP messages are big enough,
using more standard ways (no more assumptions).

syzbot reported:
BUG: KMSAN: uninit-value in pskb_may_pull_reason include/linux/skbuff.h:2667 [inline]
BUG: KMSAN: uninit-value in pskb_may_pull include/linux/skbuff.h:2681 [inline]
BUG: KMSAN: uninit-value in dccp_v6_err+0x426/0x1aa0 net/dccp/ipv6.c:94
pskb_may_pull_reason include/linux/skbuff.h:2667 [inline]
pskb_may_pull include/linux/skbuff.h:2681 [inline]
dccp_v6_err+0x426/0x1aa0 net/dccp/ipv6.c:94
icmpv6_notify+0x4c7/0x880 net/ipv6/icmp.c:867
icmpv6_rcv+0x19d5/0x30d0
ip6_protocol_deliver_rcu+0xda6/0x2a60 net/ipv6/ip6_input.c:438
ip6_input_finish net/ipv6/ip6_input.c:483 [inline]
NF_HOOK include/linux/netfilter.h:304 [inline]
ip6_input+0x15d/0x430 net/ipv6/ip6_input.c:492
ip6_mc_input+0xa7e/0xc80 net/ipv6/ip6_input.c:586
dst_input include/net/dst.h:468 [inline]
ip6_rcv_finish+0x5db/0x870 net/ipv6/ip6_input.c:79
NF_HOOK include/linux/netfilter.h:304 [inline]
ipv6_rcv+0xda/0x390 net/ipv6/ip6_input.c:310
__netif_receive_skb_one_core net/core/dev.c:5523 [inline]
__netif_receive_skb+0x1a6/0x5a0 net/core/dev.c:5637
netif_receive_skb_internal net/core/dev.c:5723 [inline]
netif_receive_skb+0x58/0x660 net/core/dev.c:5782
tun_rx_batched+0x83b/0x920
tun_get_user+0x564c/0x6940 drivers/net/tun.c:2002
tun_chr_write_iter+0x3af/0x5d0 drivers/net/tun.c:2048
call_write_iter include/linux/fs.h:1985 [inline]
new_sync_write fs/read_write.c:491 [inline]
vfs_write+0x8ef/0x15c0 fs/read_write.c:584
ksys_write+0x20f/0x4c0 fs/read_write.c:637
__do_sys_write fs/read_write.c:649 [inline]
__se_sys_write fs/read_write.c:646 [inline]
__x64_sys_write+0x93/0xd0 fs/read_write.c:646
do_syscall_x64 arch/x86/entry/common.c:50 [inline]
do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80
entry_SYSCALL_64_after_hwframe+0x63/0xcd

Uninit was created at:
slab_post_alloc_hook+0x12f/0xb70 mm/slab.h:767
slab_alloc_node mm/slub.c:3478 [inline]
kmem_cache_alloc_node+0x577/0xa80 mm/slub.c:3523
kmalloc_reserve+0x13d/0x4a0 net/core/skbuff.c:559
__alloc_skb+0x318/0x740 net/core/skbuff.c:650
alloc_skb include/linux/skbuff.h:1286 [inline]
alloc_skb_with_frags+0xc8/0xbd0 net/core/skbuff.c:6313
sock_alloc_send_pskb+0xa80/0xbf0 net/core/sock.c:2795
tun_alloc_skb drivers/net/tun.c:1531 [inline]
tun_get_user+0x23cf/0x6940 drivers/net/tun.c:1846
tun_chr_write_iter+0x3af/0x5d0 drivers/net/tun.c:2048
call_write_iter include/linux/fs.h:1985 [inline]
new_sync_write fs/read_write.c:491 [inline]
vfs_write+0x8ef/0x15c0 fs/read_write.c:584
ksys_write+0x20f/0x4c0 fs/read_write.c:637
__do_sys_write fs/read_write.c:649 [inline]
__se_sys_write fs/read_write.c:646 [inline]
__x64_sys_write+0x93/0xd0 fs/read_write.c:646
do_syscall_x64 arch/x86/entry/common.c:50 [inline]
do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80
entry_SYSCALL_64_after_hwframe+0x63/0xcd

CPU: 0 PID: 4995 Comm: syz-executor153 Not tainted 6.6.0-rc1-syzkaller-00014-ga747acc0b752 #0
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 08/04/2023

Fixes: 977ad86c2a1b ("dccp: Fix out of bounds access in DCCP error handler")
Reported-by: syzbot <syzkaller@googlegroups.com>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Jann Horn <jannh@google.com>
Reviewed-by: Jann Horn <jannh@google.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/dccp/ipv4.c | 9 ++-------
 net/dccp/ipv6.c | 9 ++-------
 2 files changed, 4 insertions(+), 14 deletions(-)

diff --git a/net/dccp/ipv4.c b/net/dccp/ipv4.c
index b2fc9ef7708f..892fbd1f650d 100644
--- a/net/dccp/ipv4.c
+++ b/net/dccp/ipv4.c
@@ -247,13 +247,8 @@ static void dccp_v4_err(struct sk_buff *skb, u32 info)
 	int err;
 	struct net *net = dev_net(skb->dev);
 
-	/* For the first __dccp_basic_hdr_len() check, we only need dh->dccph_x,
-	 * which is in byte 7 of the dccp header.
-	 * Our caller (icmp_socket_deliver()) already pulled 8 bytes for us.
-	 *
-	 * Later on, we want to access the sequence number fields, which are
-	 * beyond 8 bytes, so we have to pskb_may_pull() ourselves.
-	 */
+	if (!pskb_may_pull(skb, offset + sizeof(*dh)))
+		return;
 	dh = (struct dccp_hdr *)(skb->data + offset);
 	if (!pskb_may_pull(skb, offset + __dccp_basic_hdr_len(dh)))
 		return;
diff --git a/net/dccp/ipv6.c b/net/dccp/ipv6.c
index f8d8caa967b1..9b8c6cf0e5ee 100644
--- a/net/dccp/ipv6.c
+++ b/net/dccp/ipv6.c
@@ -80,13 +80,8 @@ static void dccp_v6_err(struct sk_buff *skb, struct inet6_skb_parm *opt,
 	__u64 seq;
 	struct net *net = dev_net(skb->dev);
 
-	/* For the first __dccp_basic_hdr_len() check, we only need dh->dccph_x,
-	 * which is in byte 7 of the dccp header.
-	 * Our caller (icmpv6_notify()) already pulled 8 bytes for us.
-	 *
-	 * Later on, we want to access the sequence number fields, which are
-	 * beyond 8 bytes, so we have to pskb_may_pull() ourselves.
-	 */
+	if (!pskb_may_pull(skb, offset + sizeof(*dh)))
+		return;
 	dh = (struct dccp_hdr *)(skb->data + offset);
 	if (!pskb_may_pull(skb, offset + __dccp_basic_hdr_len(dh)))
 		return;
-- 
GitLab


From 88f8a01c42535285bcf2666d1f7eb9ada0de88cc Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Mon, 9 Oct 2023 20:25:00 +0200
Subject: [PATCH 170/298] Revert "rtnetlink: Reject negative ifindexes in
 RTM_NEWLINK"

This reverts commit 42c8406432e730cb7442d97ecfdbf47084a5af4d which is
commit 30188bd7838c16a98a520db1fe9df01ffc6ed368 upstream.

It was improperly backported to 4.19.y, and applied to the wrong
function, which obviously causes problems.  A fixed version will be
applied as a separate commit later.

Reported-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Link: https://lore.kernel.org/r/ZSQeA8fhUT++iZvz@ostr-mac
Cc: Ido Schimmel <idosch@nvidia.com>
Cc: Jiri Pirko <jiri@nvidia.com>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Paolo Abeni <pabeni@redhat.com>
Cc: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/core/rtnetlink.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c
index 794db633f1c9..79f62517e24a 100644
--- a/net/core/rtnetlink.c
+++ b/net/core/rtnetlink.c
@@ -2702,10 +2702,7 @@ static int rtnl_setlink(struct sk_buff *skb, struct nlmsghdr *nlh,
 	ifm = nlmsg_data(nlh);
 	if (ifm->ifi_index > 0)
 		dev = __dev_get_by_index(net, ifm->ifi_index);
-	else if (ifm->ifi_index < 0) {
-		NL_SET_ERR_MSG(extack, "ifindex can't be negative");
-		return -EINVAL;
-	} else if (tb[IFLA_IFNAME])
+	else if (tb[IFLA_IFNAME])
 		dev = __dev_get_by_name(net, ifname);
 	else
 		goto errout;
-- 
GitLab


From 8180d4b00f4cbc05e7e74a8e063e46070f39269f Mon Sep 17 00:00:00 2001
From: Ido Schimmel <idosch@nvidia.com>
Date: Wed, 23 Aug 2023 09:43:48 +0300
Subject: [PATCH 171/298] rtnetlink: Reject negative ifindexes in RTM_NEWLINK

commit 30188bd7838c16a98a520db1fe9df01ffc6ed368 upstream.

Negative ifindexes are illegal, but the kernel does not validate the
ifindex in the ancillary header of RTM_NEWLINK messages, resulting in
the kernel generating a warning [1] when such an ifindex is specified.

Fix by rejecting negative ifindexes.

[1]
WARNING: CPU: 0 PID: 5031 at net/core/dev.c:9593 dev_index_reserve+0x1a2/0x1c0 net/core/dev.c:9593
[...]
Call Trace:
 <TASK>
 register_netdevice+0x69a/0x1490 net/core/dev.c:10081
 br_dev_newlink+0x27/0x110 net/bridge/br_netlink.c:1552
 rtnl_newlink_create net/core/rtnetlink.c:3471 [inline]
 __rtnl_newlink+0x115e/0x18c0 net/core/rtnetlink.c:3688
 rtnl_newlink+0x67/0xa0 net/core/rtnetlink.c:3701
 rtnetlink_rcv_msg+0x439/0xd30 net/core/rtnetlink.c:6427
 netlink_rcv_skb+0x16b/0x440 net/netlink/af_netlink.c:2545
 netlink_unicast_kernel net/netlink/af_netlink.c:1342 [inline]
 netlink_unicast+0x536/0x810 net/netlink/af_netlink.c:1368
 netlink_sendmsg+0x93c/0xe40 net/netlink/af_netlink.c:1910
 sock_sendmsg_nosec net/socket.c:728 [inline]
 sock_sendmsg+0xd9/0x180 net/socket.c:751
 ____sys_sendmsg+0x6ac/0x940 net/socket.c:2538
 ___sys_sendmsg+0x135/0x1d0 net/socket.c:2592
 __sys_sendmsg+0x117/0x1e0 net/socket.c:2621
 do_syscall_x64 arch/x86/entry/common.c:50 [inline]
 do_syscall_64+0x38/0xb0 arch/x86/entry/common.c:80
 entry_SYSCALL_64_after_hwframe+0x63/0xcd

Fixes: 38f7b870d4a6 ("[RTNETLINK]: Link creation API")
Reported-by: syzbot+5ba06978f34abb058571@syzkaller.appspotmail.com
Signed-off-by: Ido Schimmel <idosch@nvidia.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Reviewed-by: Jakub Kicinski <kuba@kernel.org>
Link: https://lore.kernel.org/r/20230823064348.2252280-1-idosch@nvidia.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/core/rtnetlink.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c
index 79f62517e24a..0d3f724da78b 100644
--- a/net/core/rtnetlink.c
+++ b/net/core/rtnetlink.c
@@ -2970,9 +2970,12 @@ static int rtnl_newlink(struct sk_buff *skb, struct nlmsghdr *nlh,
 		ifname[0] = '\0';
 
 	ifm = nlmsg_data(nlh);
-	if (ifm->ifi_index > 0)
+	if (ifm->ifi_index > 0) {
 		dev = __dev_get_by_index(net, ifm->ifi_index);
-	else {
+	} else if (ifm->ifi_index < 0) {
+		NL_SET_ERR_MSG(extack, "ifindex can't be negative");
+		return -EINVAL;
+	} else {
 		if (ifname[0])
 			dev = __dev_get_by_name(net, ifname);
 		else
-- 
GitLab


From 3fdf2be9089b5096a28e76376656c60ce410ac4a Mon Sep 17 00:00:00 2001
From: Juergen Gross <jgross@suse.com>
Date: Mon, 28 Aug 2023 08:09:47 +0200
Subject: [PATCH 172/298] xen/events: replace evtchn_rwlock with RCU
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

commit 87797fad6cce28ec9be3c13f031776ff4f104cfc upstream.

In unprivileged Xen guests event handling can cause a deadlock with
Xen console handling. The evtchn_rwlock and the hvc_lock are taken in
opposite sequence in __hvc_poll() and in Xen console IRQ handling.
Normally this is no problem, as the evtchn_rwlock is taken as a reader
in both paths, but as soon as an event channel is being closed, the
lock will be taken as a writer, which will cause read_lock() to block:

CPU0                     CPU1                CPU2
(IRQ handling)           (__hvc_poll())      (closing event channel)

read_lock(evtchn_rwlock)
                         spin_lock(hvc_lock)
                                             write_lock(evtchn_rwlock)
                                                 [blocks]
spin_lock(hvc_lock)
    [blocks]
                        read_lock(evtchn_rwlock)
                            [blocks due to writer waiting,
                             and not in_interrupt()]

This issue can be avoided by replacing evtchn_rwlock with RCU in
xen_free_irq(). Note that RCU is used only to delay freeing of the
irq_info memory. There is no RCU based dereferencing or replacement of
pointers involved.

In order to avoid potential races between removing the irq_info
reference and handling of interrupts, set the irq_info pointer to NULL
only when freeing its memory. The IRQ itself must be freed at that
time, too, as otherwise the same IRQ number could be allocated again
before handling of the old instance would have been finished.

This is XSA-441 / CVE-2023-34324.

Fixes: 54c9de89895e ("xen/events: add a new "late EOI" evtchn framework")
Reported-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Julien Grall <jgrall@amazon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/xen/events/events_base.c     | 85 ++++++++++++++--------------
 drivers/xen/events/events_internal.h |  2 +
 2 files changed, 46 insertions(+), 41 deletions(-)

diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c
index b6b3131cb079..960666aba12b 100644
--- a/drivers/xen/events/events_base.c
+++ b/drivers/xen/events/events_base.c
@@ -82,23 +82,13 @@ const struct evtchn_ops *evtchn_ops;
  */
 static DEFINE_MUTEX(irq_mapping_update_lock);
 
-/*
- * Lock protecting event handling loop against removing event channels.
- * Adding of event channels is no issue as the associated IRQ becomes active
- * only after everything is setup (before request_[threaded_]irq() the handler
- * can't be entered for an event, as the event channel will be unmasked only
- * then).
- */
-static DEFINE_RWLOCK(evtchn_rwlock);
-
 /*
  * Lock hierarchy:
  *
  * irq_mapping_update_lock
- *   evtchn_rwlock
- *     IRQ-desc lock
- *       percpu eoi_list_lock
- *         irq_info->lock
+ *   IRQ-desc lock
+ *     percpu eoi_list_lock
+ *       irq_info->lock
  */
 
 static LIST_HEAD(xen_irq_list_head);
@@ -213,6 +203,22 @@ static void set_info_for_irq(unsigned int irq, struct irq_info *info)
 		irq_set_chip_data(irq, info);
 }
 
+static void delayed_free_irq(struct work_struct *work)
+{
+	struct irq_info *info = container_of(to_rcu_work(work), struct irq_info,
+					     rwork);
+	unsigned int irq = info->irq;
+
+	/* Remove the info pointer only now, with no potential users left. */
+	set_info_for_irq(irq, NULL);
+
+	kfree(info);
+
+	/* Legacy IRQ descriptors are managed by the arch. */
+	if (irq >= nr_legacy_irqs())
+		irq_free_desc(irq);
+}
+
 /* Constructors for packed IRQ information. */
 static int xen_irq_info_common_setup(struct irq_info *info,
 				     unsigned irq,
@@ -547,33 +553,36 @@ static void xen_irq_lateeoi_worker(struct work_struct *work)
 
 	eoi = container_of(to_delayed_work(work), struct lateeoi_work, delayed);
 
-	read_lock_irqsave(&evtchn_rwlock, flags);
+	rcu_read_lock();
 
 	while (true) {
-		spin_lock(&eoi->eoi_list_lock);
+		spin_lock_irqsave(&eoi->eoi_list_lock, flags);
 
 		info = list_first_entry_or_null(&eoi->eoi_list, struct irq_info,
 						eoi_list);
 
-		if (info == NULL || now < info->eoi_time) {
-			spin_unlock(&eoi->eoi_list_lock);
+		if (info == NULL)
+			break;
+
+		if (now < info->eoi_time) {
+			mod_delayed_work_on(info->eoi_cpu, system_wq,
+					    &eoi->delayed,
+					    info->eoi_time - now);
 			break;
 		}
 
 		list_del_init(&info->eoi_list);
 
-		spin_unlock(&eoi->eoi_list_lock);
+		spin_unlock_irqrestore(&eoi->eoi_list_lock, flags);
 
 		info->eoi_time = 0;
 
 		xen_irq_lateeoi_locked(info, false);
 	}
 
-	if (info)
-		mod_delayed_work_on(info->eoi_cpu, system_wq,
-				    &eoi->delayed, info->eoi_time - now);
+	spin_unlock_irqrestore(&eoi->eoi_list_lock, flags);
 
-	read_unlock_irqrestore(&evtchn_rwlock, flags);
+	rcu_read_unlock();
 }
 
 static void xen_cpu_init_eoi(unsigned int cpu)
@@ -588,16 +597,15 @@ static void xen_cpu_init_eoi(unsigned int cpu)
 void xen_irq_lateeoi(unsigned int irq, unsigned int eoi_flags)
 {
 	struct irq_info *info;
-	unsigned long flags;
 
-	read_lock_irqsave(&evtchn_rwlock, flags);
+	rcu_read_lock();
 
 	info = info_for_irq(irq);
 
 	if (info)
 		xen_irq_lateeoi_locked(info, eoi_flags & XEN_EOI_FLAG_SPURIOUS);
 
-	read_unlock_irqrestore(&evtchn_rwlock, flags);
+	rcu_read_unlock();
 }
 EXPORT_SYMBOL_GPL(xen_irq_lateeoi);
 
@@ -616,6 +624,7 @@ static void xen_irq_init(unsigned irq)
 
 	info->type = IRQT_UNBOUND;
 	info->refcnt = -1;
+	INIT_RCU_WORK(&info->rwork, delayed_free_irq);
 
 	set_info_for_irq(irq, info);
 
@@ -668,31 +677,18 @@ static int __must_check xen_allocate_irq_gsi(unsigned gsi)
 static void xen_free_irq(unsigned irq)
 {
 	struct irq_info *info = info_for_irq(irq);
-	unsigned long flags;
 
 	if (WARN_ON(!info))
 		return;
 
-	write_lock_irqsave(&evtchn_rwlock, flags);
-
 	if (!list_empty(&info->eoi_list))
 		lateeoi_list_del(info);
 
 	list_del(&info->list);
 
-	set_info_for_irq(irq, NULL);
-
 	WARN_ON(info->refcnt > 0);
 
-	write_unlock_irqrestore(&evtchn_rwlock, flags);
-
-	kfree(info);
-
-	/* Legacy IRQ descriptors are managed by the arch. */
-	if (irq < nr_legacy_irqs())
-		return;
-
-	irq_free_desc(irq);
+	queue_rcu_work(system_wq, &info->rwork);
 }
 
 static void xen_evtchn_close(unsigned int port)
@@ -1603,7 +1599,14 @@ static void __xen_evtchn_do_upcall(void)
 	unsigned count;
 	struct evtchn_loop_ctrl ctrl = { 0 };
 
-	read_lock(&evtchn_rwlock);
+	/*
+	 * When closing an event channel the associated IRQ must not be freed
+	 * until all cpus have left the event handling loop. This is ensured
+	 * by taking the rcu_read_lock() while handling events, as freeing of
+	 * the IRQ is handled via queue_rcu_work() _after_ closing the event
+	 * channel.
+	 */
+	rcu_read_lock();
 
 	do {
 		vcpu_info->evtchn_upcall_pending = 0;
@@ -1620,7 +1623,7 @@ static void __xen_evtchn_do_upcall(void)
 	} while (count != 1 || vcpu_info->evtchn_upcall_pending);
 
 out:
-	read_unlock(&evtchn_rwlock);
+	rcu_read_unlock();
 
 	/*
 	 * Increment irq_epoch only now to defer EOIs only for
diff --git a/drivers/xen/events/events_internal.h b/drivers/xen/events/events_internal.h
index cc37b711491c..1d9d9e6f1dee 100644
--- a/drivers/xen/events/events_internal.h
+++ b/drivers/xen/events/events_internal.h
@@ -8,6 +8,7 @@
  */
 #ifndef __EVENTS_INTERNAL_H__
 #define __EVENTS_INTERNAL_H__
+#include <linux/rcupdate.h>
 
 /* Interrupt types. */
 enum xen_irq_type {
@@ -33,6 +34,7 @@ enum xen_irq_type {
 struct irq_info {
 	struct list_head list;
 	struct list_head eoi_list;
+	struct rcu_work rwork;
 	short refcnt;
 	short spurious_cnt;
 	short type;		/* type */
-- 
GitLab


From 1b540579cf668bd805cdcca5285f579dcf6e4312 Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Tue, 10 Oct 2023 21:45:02 +0200
Subject: [PATCH 173/298] Linux 4.19.296

Link: https://lore.kernel.org/r/20231009130111.518916887@linuxfoundation.org
Tested-by: Shuah Khan <skhan@linuxfoundation.org>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 6eb08388fa15..002d81755142 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 VERSION = 4
 PATCHLEVEL = 19
-SUBLEVEL = 295
+SUBLEVEL = 296
 EXTRAVERSION =
 NAME = "People's Front"
 
-- 
GitLab


From 1b36874123cf758ac1e2a8d9c8b24394ded60da7 Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman <gregkh@google.com>
Date: Thu, 12 Oct 2023 09:05:47 +0000
Subject: [PATCH 174/298] Revert "net: bridge: use DEV_STATS_INC()"

This reverts commit d2346e6beb699909ca455d9d20c4e577ce900839 which is
commit 44bdb313da57322c9b3c108eb66981c6ec6509f4 upstream.

It is needed to be reverted as it relies on an abi-breaking change that
also must be reverted.  It's not really needed for Android systems, but
if it is needed to come back, it can be reworked to be a CRC-abi neutral
change if so desired.

Bug: 161946584
Change-Id: I8a9f35972d5ade06a3bafd6a965ac2430ad0e63d
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
---
 net/bridge/br_forward.c | 4 ++--
 net/bridge/br_input.c   | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/net/bridge/br_forward.c b/net/bridge/br_forward.c
index c07a47d65c39..48ddc60b4fbd 100644
--- a/net/bridge/br_forward.c
+++ b/net/bridge/br_forward.c
@@ -122,7 +122,7 @@ static int deliver_clone(const struct net_bridge_port *prev,
 
 	skb = skb_clone(skb, GFP_ATOMIC);
 	if (!skb) {
-		DEV_STATS_INC(dev, tx_dropped);
+		dev->stats.tx_dropped++;
 		return -ENOMEM;
 	}
 
@@ -261,7 +261,7 @@ static void maybe_deliver_addr(struct net_bridge_port *p, struct sk_buff *skb,
 
 	skb = skb_copy(skb, GFP_ATOMIC);
 	if (!skb) {
-		DEV_STATS_INC(dev, tx_dropped);
+		dev->stats.tx_dropped++;
 		return;
 	}
 
diff --git a/net/bridge/br_input.c b/net/bridge/br_input.c
index f3938337ff87..14c2fdc268ea 100644
--- a/net/bridge/br_input.c
+++ b/net/bridge/br_input.c
@@ -146,12 +146,12 @@ int br_handle_frame_finish(struct net *net, struct sock *sk, struct sk_buff *skb
 			if ((mdst && mdst->host_joined) ||
 			    br_multicast_is_router(br)) {
 				local_rcv = true;
-				DEV_STATS_INC(br->dev, multicast);
+				br->dev->stats.multicast++;
 			}
 			mcast_hit = true;
 		} else {
 			local_rcv = true;
-			DEV_STATS_INC(br->dev, multicast);
+			br->dev->stats.multicast++;
 		}
 		break;
 	case BR_PKT_UNICAST:
-- 
GitLab


From cb7655a9477536b7ff0bf55c60180cda632c3d2a Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman <gregkh@google.com>
Date: Thu, 12 Oct 2023 09:04:16 +0000
Subject: [PATCH 175/298] Revert "net: Fix unwanted sign extension in
 netdev_stats_to_stats64()"

This reverts commit b17d81b94d24834d0ee038c6e216752f43b67cc9 which is
commit 9b55d3f0a69af649c62cbc2633e6d695bb3cc583 upstream.

It is needed to be reverted as it relies on an abi-breaking change that
also must be reverted.  It's not really needed for Android systems, but
if it is needed to come back, it can be reworked to be a CRC-abi neutral
change if so desired.

Bug: 161946584
Change-Id: I375a29e01f3758f89f74bea69183e3990e01043c
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
---
 net/core/dev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/core/dev.c b/net/core/dev.c
index 2c40a46f10c3..8a14b634549b 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -9056,7 +9056,7 @@ void netdev_stats_to_stats64(struct rtnl_link_stats64 *stats64,
 
 	BUILD_BUG_ON(n > sizeof(*stats64) / sizeof(u64));
 	for (i = 0; i < n; i++)
-		dst[i] = (unsigned long)atomic_long_read(&src[i]);
+		dst[i] = atomic_long_read(&src[i]);
 	/* zero out counters that only exist in rtnl_link_stats64 */
 	memset((char *)stats64 + n * sizeof(u64), 0,
 	       sizeof(*stats64) - n * sizeof(u64));
-- 
GitLab


From b5a7a8659f6e97d3bee101f4b2cf7e7856014a1c Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman <gregkh@google.com>
Date: Thu, 12 Oct 2023 09:04:50 +0000
Subject: [PATCH 176/298] Revert "net: add atomic_long_t to net_device_stats
 fields"

This reverts commit 2b601fcacd30ea9b3f777490e7c788b548389991 which is
commit 6c1c5097781f563b70a81683ea6fdac21637573b upstream.

It breaks the CRC checking for the Android KABI (doesn't really break
any actual ABI, but it isn't nice.)  As this isn't needed for Android
systems at this point in time, just revert it to keep the CRC abi
stable.

If it is needed to come back, it can be reworked to be a CRC-abi neutral
change if so desired.

Bug: 161946584
Fixes: 2b601fcacd30 ("net: add atomic_long_t to net_device_stats fields")
Cc: Eric Dumazet <edumazet@google.com>
Change-Id: I9d3d9fb55ab5482a4ea92fcc4a2fb70c4471edec
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
---
 include/linux/netdevice.h | 58 ++++++++++++++++-----------------------
 include/net/dst.h         |  5 ++--
 net/core/dev.c            | 14 ++++++++--
 3 files changed, 37 insertions(+), 40 deletions(-)

diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index d03511e6e458..f545baf757e7 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -163,38 +163,31 @@ static inline bool dev_xmit_complete(int rc)
  *	(unsigned long) so they can be read and written atomically.
  */
 
-#define NET_DEV_STAT(FIELD)			\
-	union {					\
-		unsigned long FIELD;		\
-		atomic_long_t __##FIELD;	\
-	}
-
 struct net_device_stats {
-	NET_DEV_STAT(rx_packets);
-	NET_DEV_STAT(tx_packets);
-	NET_DEV_STAT(rx_bytes);
-	NET_DEV_STAT(tx_bytes);
-	NET_DEV_STAT(rx_errors);
-	NET_DEV_STAT(tx_errors);
-	NET_DEV_STAT(rx_dropped);
-	NET_DEV_STAT(tx_dropped);
-	NET_DEV_STAT(multicast);
-	NET_DEV_STAT(collisions);
-	NET_DEV_STAT(rx_length_errors);
-	NET_DEV_STAT(rx_over_errors);
-	NET_DEV_STAT(rx_crc_errors);
-	NET_DEV_STAT(rx_frame_errors);
-	NET_DEV_STAT(rx_fifo_errors);
-	NET_DEV_STAT(rx_missed_errors);
-	NET_DEV_STAT(tx_aborted_errors);
-	NET_DEV_STAT(tx_carrier_errors);
-	NET_DEV_STAT(tx_fifo_errors);
-	NET_DEV_STAT(tx_heartbeat_errors);
-	NET_DEV_STAT(tx_window_errors);
-	NET_DEV_STAT(rx_compressed);
-	NET_DEV_STAT(tx_compressed);
+	unsigned long	rx_packets;
+	unsigned long	tx_packets;
+	unsigned long	rx_bytes;
+	unsigned long	tx_bytes;
+	unsigned long	rx_errors;
+	unsigned long	tx_errors;
+	unsigned long	rx_dropped;
+	unsigned long	tx_dropped;
+	unsigned long	multicast;
+	unsigned long	collisions;
+	unsigned long	rx_length_errors;
+	unsigned long	rx_over_errors;
+	unsigned long	rx_crc_errors;
+	unsigned long	rx_frame_errors;
+	unsigned long	rx_fifo_errors;
+	unsigned long	rx_missed_errors;
+	unsigned long	tx_aborted_errors;
+	unsigned long	tx_carrier_errors;
+	unsigned long	tx_fifo_errors;
+	unsigned long	tx_heartbeat_errors;
+	unsigned long	tx_window_errors;
+	unsigned long	rx_compressed;
+	unsigned long	tx_compressed;
 };
-#undef NET_DEV_STAT
 
 
 #include <linux/cache.h>
@@ -4896,9 +4889,4 @@ do {								\
 #define PTYPE_HASH_SIZE	(16)
 #define PTYPE_HASH_MASK	(PTYPE_HASH_SIZE - 1)
 
-/* Note: Avoid these macros in fast path, prefer per-cpu or per-queue counters. */
-#define DEV_STATS_INC(DEV, FIELD) atomic_long_inc(&(DEV)->stats.__##FIELD)
-#define DEV_STATS_ADD(DEV, FIELD, VAL) 	\
-		atomic_long_add((VAL), &(DEV)->stats.__##FIELD)
-
 #endif	/* _LINUX_NETDEVICE_H */
diff --git a/include/net/dst.h b/include/net/dst.h
index 97267997601f..50258a813137 100644
--- a/include/net/dst.h
+++ b/include/net/dst.h
@@ -362,8 +362,9 @@ static inline void __skb_tunnel_rx(struct sk_buff *skb, struct net_device *dev,
 static inline void skb_tunnel_rx(struct sk_buff *skb, struct net_device *dev,
 				 struct net *net)
 {
-	DEV_STATS_INC(dev, rx_packets);
-	DEV_STATS_ADD(dev, rx_bytes, skb->len);
+	/* TODO : stats should be SMP safe */
+	dev->stats.rx_packets++;
+	dev->stats.rx_bytes += skb->len;
 	__skb_tunnel_rx(skb, dev, net);
 }
 
diff --git a/net/core/dev.c b/net/core/dev.c
index 8a14b634549b..b4a6337aba7e 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -9050,16 +9050,24 @@ void netdev_run_todo(void)
 void netdev_stats_to_stats64(struct rtnl_link_stats64 *stats64,
 			     const struct net_device_stats *netdev_stats)
 {
-	size_t i, n = sizeof(*netdev_stats) / sizeof(atomic_long_t);
-	const atomic_long_t *src = (atomic_long_t *)netdev_stats;
+#if BITS_PER_LONG == 64
+	BUILD_BUG_ON(sizeof(*stats64) < sizeof(*netdev_stats));
+	memcpy(stats64, netdev_stats, sizeof(*netdev_stats));
+	/* zero out counters that only exist in rtnl_link_stats64 */
+	memset((char *)stats64 + sizeof(*netdev_stats), 0,
+	       sizeof(*stats64) - sizeof(*netdev_stats));
+#else
+	size_t i, n = sizeof(*netdev_stats) / sizeof(unsigned long);
+	const unsigned long *src = (const unsigned long *)netdev_stats;
 	u64 *dst = (u64 *)stats64;
 
 	BUILD_BUG_ON(n > sizeof(*stats64) / sizeof(u64));
 	for (i = 0; i < n; i++)
-		dst[i] = atomic_long_read(&src[i]);
+		dst[i] = src[i];
 	/* zero out counters that only exist in rtnl_link_stats64 */
 	memset((char *)stats64 + n * sizeof(u64), 0,
 	       sizeof(*stats64) - n * sizeof(u64));
+#endif
 }
 EXPORT_SYMBOL(netdev_stats_to_stats64);
 
-- 
GitLab


From f11ebfaabffc65fe58fea6b29e3a242a5e887dd8 Mon Sep 17 00:00:00 2001
From: Saranya R <quic_sarar@quicinc.com>
Date: Wed, 11 Oct 2023 17:11:44 +0530
Subject: [PATCH 177/298] defconfig: kona: Fix for SonyDualSenseEdge cts
 failures

Removed CONFIG_HID_PLAYSTATION support to pass
SonyDualSenseEdge cts testcases.

Change-Id: Ibe688eaf737c82b37eaae9d11a05022ab1494b91
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
---
 arch/arm64/configs/vendor/kona-perf_defconfig | 2 --
 arch/arm64/configs/vendor/kona_defconfig      | 2 --
 2 files changed, 4 deletions(-)

diff --git a/arch/arm64/configs/vendor/kona-perf_defconfig b/arch/arm64/configs/vendor/kona-perf_defconfig
index 672cd6013c8f..5e4ff5807167 100644
--- a/arch/arm64/configs/vendor/kona-perf_defconfig
+++ b/arch/arm64/configs/vendor/kona-perf_defconfig
@@ -466,8 +466,6 @@ CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MULTITOUCH=y
 CONFIG_HID_NINTENDO=y
 CONFIG_HID_PLANTRONICS=y
-CONFIG_HID_PLAYSTATION=y
-CONFIG_PLAYSTATION_FF=y
 CONFIG_HID_SONY=y
 CONFIG_SONY_FF=y
 CONFIG_HID_QVR=y
diff --git a/arch/arm64/configs/vendor/kona_defconfig b/arch/arm64/configs/vendor/kona_defconfig
index 0658ee79c0e6..bb9a6048cbc9 100644
--- a/arch/arm64/configs/vendor/kona_defconfig
+++ b/arch/arm64/configs/vendor/kona_defconfig
@@ -484,8 +484,6 @@ CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MULTITOUCH=y
 CONFIG_HID_NINTENDO=y
 CONFIG_HID_PLANTRONICS=y
-CONFIG_HID_PLAYSTATION=y
-CONFIG_PLAYSTATION_FF=y
 CONFIG_HID_SONY=y
 CONFIG_SONY_FF=y
 CONFIG_HID_QVR=y
-- 
GitLab


From c6644c7af74954ced99919c3e0daf4c5a7fdc3a4 Mon Sep 17 00:00:00 2001
From: Saranya R <quic_sarar@quicinc.com>
Date: Wed, 11 Oct 2023 17:11:44 +0530
Subject: [PATCH 178/298] defconfig: kona: Fix for SonyDualSenseEdge cts
 failures

Removed CONFIG_HID_PLAYSTATION support to pass
SonyDualSenseEdge cts testcases.

Change-Id: Ibe688eaf737c82b37eaae9d11a05022ab1494b91
Signed-off-by: Saranya R <quic_sarar@quicinc.com>
---
 arch/arm64/configs/vendor/kona-perf_defconfig | 2 --
 arch/arm64/configs/vendor/kona_defconfig      | 2 --
 2 files changed, 4 deletions(-)

diff --git a/arch/arm64/configs/vendor/kona-perf_defconfig b/arch/arm64/configs/vendor/kona-perf_defconfig
index 672cd6013c8f..5e4ff5807167 100644
--- a/arch/arm64/configs/vendor/kona-perf_defconfig
+++ b/arch/arm64/configs/vendor/kona-perf_defconfig
@@ -466,8 +466,6 @@ CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MULTITOUCH=y
 CONFIG_HID_NINTENDO=y
 CONFIG_HID_PLANTRONICS=y
-CONFIG_HID_PLAYSTATION=y
-CONFIG_PLAYSTATION_FF=y
 CONFIG_HID_SONY=y
 CONFIG_SONY_FF=y
 CONFIG_HID_QVR=y
diff --git a/arch/arm64/configs/vendor/kona_defconfig b/arch/arm64/configs/vendor/kona_defconfig
index 0658ee79c0e6..bb9a6048cbc9 100644
--- a/arch/arm64/configs/vendor/kona_defconfig
+++ b/arch/arm64/configs/vendor/kona_defconfig
@@ -484,8 +484,6 @@ CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MULTITOUCH=y
 CONFIG_HID_NINTENDO=y
 CONFIG_HID_PLANTRONICS=y
-CONFIG_HID_PLAYSTATION=y
-CONFIG_PLAYSTATION_FF=y
 CONFIG_HID_SONY=y
 CONFIG_SONY_FF=y
 CONFIG_HID_QVR=y
-- 
GitLab


From 261fd07e49cd990829ae7bc3fef190c41924023a Mon Sep 17 00:00:00 2001
From: Krishna Kurapati <quic_kriskura@quicinc.com>
Date: Fri, 6 Oct 2023 19:12:19 +0530
Subject: [PATCH 179/298] dwc3-msm-core: Remove usage of DWC31_LINK_GDBGLTSSM
 with POR

USB SSPHY is still not initialized when reading DWC31_LINK_GDBGLTSSM
register (which is USB controller based LINK register, applicable for
USB SS only). This register read shall take more time which shall result
into other master read on CNOC seeing higher latency. Hence remove
usage of DWC31_LINK_GDBGLTSSM read as purpose to mark state as IN_P3
doesn't hold good here until USB PHYs are initialized.

Change-Id: Ic0f00e5f61e53feb71c8fa17cbfee06b6506efae
Signed-off-by: Mayank Rana <quic_mrana@quicinc.com>
Signed-off-by: Udipto Goswami <quic_ugoswami@quicinc.com>
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
---
 drivers/usb/dwc3/dwc3-msm.c | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
index 1360c7d6db59..fff116fa1a8c 100644
--- a/drivers/usb/dwc3/dwc3-msm.c
+++ b/drivers/usb/dwc3/dwc3-msm.c
@@ -2294,15 +2294,6 @@ static void dwc3_msm_power_collapse_por(struct dwc3_msm *mdwc)
 		dev_err(mdwc->dev, "%s: dwc3_core init failed (%d)\n",
 							__func__, ret);
 
-	/* Get initial P3 status and enable IN_P3 event */
-	if (dwc3_is_usb31(dwc))
-		val = dwc3_msm_read_reg_field(mdwc->base,
-			DWC31_LINK_GDBGLTSSM,
-			DWC3_GDBGLTSSM_LINKSTATE_MASK);
-	else
-		val = dwc3_msm_read_reg_field(mdwc->base,
-			DWC3_GDBGLTSSM, DWC3_GDBGLTSSM_LINKSTATE_MASK);
-	atomic_set(&mdwc->in_p3, val == DWC3_LINK_STATE_U3);
 	dwc3_msm_write_reg_field(mdwc->base, PWR_EVNT_IRQ_MASK_REG,
 				PWR_EVNT_POWERDOWN_IN_P3_MASK, 1);
 
-- 
GitLab


From a2fcb34c9a73479001ba010ca487833decad94b0 Mon Sep 17 00:00:00 2001
From: Paolo Abeni <pabeni@redhat.com>
Date: Fri, 14 Dec 2018 11:51:57 +0100
Subject: [PATCH 180/298] indirect call wrappers: helpers to speed-up indirect
 calls of builtin

[ Upstream commit 283c16a2dfd332bf5610c874f7b9f9c8b601ce53 ]

This header define a bunch of helpers that allow avoiding the
retpoline overhead when calling builtin functions via function pointers.
It boils down to explicitly comparing the function pointers to
known builtin functions and eventually invoke directly the latter.

The macros defined here implement the boilerplate for the above schema
and will be used by the next patches.

rfc -> v1:
 - use branch prediction hint, as suggested by Eric
v1  -> v2:
 - list explicitly the builtin function names in INDIRECT_CALL_*(),
   as suggested by Ed Cree

Suggested-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Stable-dep-of: 86a7e0b69bd5 ("net: prevent rewrite of msg_name in sock_sendmsg()")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 include/linux/indirect_call_wrapper.h | 51 +++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 include/linux/indirect_call_wrapper.h

diff --git a/include/linux/indirect_call_wrapper.h b/include/linux/indirect_call_wrapper.h
new file mode 100644
index 000000000000..7c8b7f4948af
--- /dev/null
+++ b/include/linux/indirect_call_wrapper.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _LINUX_INDIRECT_CALL_WRAPPER_H
+#define _LINUX_INDIRECT_CALL_WRAPPER_H
+
+#ifdef CONFIG_RETPOLINE
+
+/*
+ * INDIRECT_CALL_$NR - wrapper for indirect calls with $NR known builtin
+ *  @f: function pointer
+ *  @f$NR: builtin functions names, up to $NR of them
+ *  @__VA_ARGS__: arguments for @f
+ *
+ * Avoid retpoline overhead for known builtin, checking @f vs each of them and
+ * eventually invoking directly the builtin function. The functions are check
+ * in the given order. Fallback to the indirect call.
+ */
+#define INDIRECT_CALL_1(f, f1, ...)					\
+	({								\
+		likely(f == f1) ? f1(__VA_ARGS__) : f(__VA_ARGS__);	\
+	})
+#define INDIRECT_CALL_2(f, f2, f1, ...)					\
+	({								\
+		likely(f == f2) ? f2(__VA_ARGS__) :			\
+				  INDIRECT_CALL_1(f, f1, __VA_ARGS__);	\
+	})
+
+#define INDIRECT_CALLABLE_DECLARE(f)	f
+#define INDIRECT_CALLABLE_SCOPE
+
+#else
+#define INDIRECT_CALL_1(f, name, ...) f(__VA_ARGS__)
+#define INDIRECT_CALL_2(f, name, ...) f(__VA_ARGS__)
+#define INDIRECT_CALLABLE_DECLARE(f)
+#define INDIRECT_CALLABLE_SCOPE		static
+#endif
+
+/*
+ * We can use INDIRECT_CALL_$NR for ipv6 related functions only if ipv6 is
+ * builtin, this macro simplify dealing with indirect calls with only ipv4/ipv6
+ * alternatives
+ */
+#if IS_BUILTIN(CONFIG_IPV6)
+#define INDIRECT_CALL_INET(f, f2, f1, ...) \
+	INDIRECT_CALL_2(f, f2, f1, __VA_ARGS__)
+#elif IS_ENABLED(CONFIG_INET)
+#define INDIRECT_CALL_INET(f, f2, f1, ...) INDIRECT_CALL_1(f, f1, __VA_ARGS__)
+#else
+#define INDIRECT_CALL_INET(f, f2, f1, ...) f(__VA_ARGS__)
+#endif
+
+#endif
-- 
GitLab


From 8dd19eb37825b12ae92903a19bd7a51c880ca987 Mon Sep 17 00:00:00 2001
From: Paolo Abeni <pabeni@redhat.com>
Date: Fri, 3 May 2019 17:01:39 +0200
Subject: [PATCH 181/298] net: use indirect calls helpers at the socket layer

[ Upstream commit 8c3c447b3cec27cf6f77080f4d157d53b64e9555 ]

This avoids an indirect call per {send,recv}msg syscall in
the common (IPv6 or IPv4 socket) case.

Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Stable-dep-of: 86a7e0b69bd5 ("net: prevent rewrite of msg_name in sock_sendmsg()")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/socket.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/net/socket.c b/net/socket.c
index db9d908198f2..dc4d4ecd6cea 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -90,6 +90,7 @@
 #include <linux/slab.h>
 #include <linux/xattr.h>
 #include <linux/nospec.h>
+#include <linux/indirect_call_wrapper.h>
 
 #include <linux/uaccess.h>
 #include <asm/unistd.h>
@@ -108,6 +109,13 @@
 #include <net/busy_poll.h>
 #include <linux/errqueue.h>
 
+/* proto_ops for ipv4 and ipv6 use the same {recv,send}msg function */
+#if IS_ENABLED(CONFIG_INET)
+#define INDIRECT_CALL_INET4(f, f1, ...) INDIRECT_CALL_1(f, f1, __VA_ARGS__)
+#else
+#define INDIRECT_CALL_INET4(f, f1, ...) f(__VA_ARGS__)
+#endif
+
 #ifdef CONFIG_NET_RX_BUSY_POLL
 unsigned int sysctl_net_busy_read __read_mostly;
 unsigned int sysctl_net_busy_poll __read_mostly;
@@ -645,10 +653,12 @@ EXPORT_SYMBOL(__sock_tx_timestamp);
  *	Sends @msg through @sock, passing through LSM.
  *	Returns the number of bytes sent, or an error code.
  */
-
+INDIRECT_CALLABLE_DECLARE(int inet_sendmsg(struct socket *, struct msghdr *,
+					   size_t));
 static inline int sock_sendmsg_nosec(struct socket *sock, struct msghdr *msg)
 {
-	int ret = sock->ops->sendmsg(sock, msg, msg_data_left(msg));
+	int ret = INDIRECT_CALL_INET4(sock->ops->sendmsg, inet_sendmsg, sock,
+				      msg, msg_data_left(msg));
 	BUG_ON(ret == -EIOCBQUEUED);
 	return ret;
 }
@@ -852,11 +862,13 @@ EXPORT_SYMBOL_GPL(__sock_recv_ts_and_drops);
  *	Receives @msg from @sock, passing through LSM. Returns the total number
  *	of bytes received, or an error.
  */
-
+INDIRECT_CALLABLE_DECLARE(int inet_recvmsg(struct socket *, struct msghdr *,
+					   size_t , int ));
 static inline int sock_recvmsg_nosec(struct socket *sock, struct msghdr *msg,
 				     int flags)
 {
-	return sock->ops->recvmsg(sock, msg, msg_data_left(msg), flags);
+	return INDIRECT_CALL_INET4(sock->ops->recvmsg, inet_recvmsg, sock, msg,
+				   msg_data_left(msg), flags);
 }
 
 int sock_recvmsg(struct socket *sock, struct msghdr *msg, int flags)
-- 
GitLab


From 977f725689129fde7f69626d4bdc216da118279d Mon Sep 17 00:00:00 2001
From: Randy Dunlap <rdunlap@infradead.org>
Date: Sat, 18 May 2019 21:23:07 -0700
Subject: [PATCH 182/298] net: fix kernel-doc warnings for socket.c

[ Upstream commit 85806af0c6bac0feb777e255a25fd5d0cf6ad38e ]

Fix kernel-doc warnings by moving the kernel-doc notation to be
immediately above the functions that it describes.

Fixes these warnings for sock_sendmsg() and sock_recvmsg():

../net/socket.c:658: warning: Excess function parameter 'sock' description in 'INDIRECT_CALLABLE_DECLARE'
../net/socket.c:658: warning: Excess function parameter 'msg' description in 'INDIRECT_CALLABLE_DECLARE'
../net/socket.c:889: warning: Excess function parameter 'sock' description in 'INDIRECT_CALLABLE_DECLARE'
../net/socket.c:889: warning: Excess function parameter 'msg' description in 'INDIRECT_CALLABLE_DECLARE'
../net/socket.c:889: warning: Excess function parameter 'flags' description in 'INDIRECT_CALLABLE_DECLARE'

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Stable-dep-of: 86a7e0b69bd5 ("net: prevent rewrite of msg_name in sock_sendmsg()")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/socket.c | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/net/socket.c b/net/socket.c
index dc4d4ecd6cea..adf1fb37c17c 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -645,14 +645,6 @@ void __sock_tx_timestamp(__u16 tsflags, __u8 *tx_flags)
 }
 EXPORT_SYMBOL(__sock_tx_timestamp);
 
-/**
- *	sock_sendmsg - send a message through @sock
- *	@sock: socket
- *	@msg: message to send
- *
- *	Sends @msg through @sock, passing through LSM.
- *	Returns the number of bytes sent, or an error code.
- */
 INDIRECT_CALLABLE_DECLARE(int inet_sendmsg(struct socket *, struct msghdr *,
 					   size_t));
 static inline int sock_sendmsg_nosec(struct socket *sock, struct msghdr *msg)
@@ -663,6 +655,14 @@ static inline int sock_sendmsg_nosec(struct socket *sock, struct msghdr *msg)
 	return ret;
 }
 
+/**
+ *	sock_sendmsg - send a message through @sock
+ *	@sock: socket
+ *	@msg: message to send
+ *
+ *	Sends @msg through @sock, passing through LSM.
+ *	Returns the number of bytes sent, or an error code.
+ */
 int sock_sendmsg(struct socket *sock, struct msghdr *msg)
 {
 	int err = security_socket_sendmsg(sock, msg,
@@ -853,15 +853,6 @@ void __sock_recv_ts_and_drops(struct msghdr *msg, struct sock *sk,
 }
 EXPORT_SYMBOL_GPL(__sock_recv_ts_and_drops);
 
-/**
- *	sock_recvmsg - receive a message from @sock
- *	@sock: socket
- *	@msg: message to receive
- *	@flags: message flags
- *
- *	Receives @msg from @sock, passing through LSM. Returns the total number
- *	of bytes received, or an error.
- */
 INDIRECT_CALLABLE_DECLARE(int inet_recvmsg(struct socket *, struct msghdr *,
 					   size_t , int ));
 static inline int sock_recvmsg_nosec(struct socket *sock, struct msghdr *msg,
@@ -871,6 +862,15 @@ static inline int sock_recvmsg_nosec(struct socket *sock, struct msghdr *msg,
 				   msg_data_left(msg), flags);
 }
 
+/**
+ *	sock_recvmsg - receive a message from @sock
+ *	@sock: socket
+ *	@msg: message to receive
+ *	@flags: message flags
+ *
+ *	Receives @msg from @sock, passing through LSM. Returns the total number
+ *	of bytes received, or an error.
+ */
 int sock_recvmsg(struct socket *sock, struct msghdr *msg, int flags)
 {
 	int err = security_socket_recvmsg(sock, msg, msg_data_left(msg), flags);
-- 
GitLab


From 3d62f2577c7414e5b94e4baad6eb621165960f30 Mon Sep 17 00:00:00 2001
From: Jordan Rife <jrife@google.com>
Date: Thu, 21 Sep 2023 18:46:41 -0500
Subject: [PATCH 183/298] net: prevent rewrite of msg_name in sock_sendmsg()

[ Upstream commit 86a7e0b69bd5b812e48a20c66c2161744f3caa16 ]

Callers of sock_sendmsg(), and similarly kernel_sendmsg(), in kernel
space may observe their value of msg_name change in cases where BPF
sendmsg hooks rewrite the send address. This has been confirmed to break
NFS mounts running in UDP mode and has the potential to break other
systems.

This patch:

1) Creates a new function called __sock_sendmsg() with same logic as the
   old sock_sendmsg() function.
2) Replaces calls to sock_sendmsg() made by __sys_sendto() and
   __sys_sendmsg() with __sock_sendmsg() to avoid an unnecessary copy,
   as these system calls are already protected.
3) Modifies sock_sendmsg() so that it makes a copy of msg_name if
   present before passing it down the stack to insulate callers from
   changes to the send address.

Link: https://lore.kernel.org/netdev/20230912013332.2048422-1-jrife@google.com/
Fixes: 1cedee13d25a ("bpf: Hooks for sys_sendmsg")
Cc: stable@vger.kernel.org
Reviewed-by: Willem de Bruijn <willemb@google.com>
Signed-off-by: Jordan Rife <jrife@google.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/socket.c | 29 +++++++++++++++++++++++------
 1 file changed, 23 insertions(+), 6 deletions(-)

diff --git a/net/socket.c b/net/socket.c
index adf1fb37c17c..d9eaab948d69 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -655,6 +655,14 @@ static inline int sock_sendmsg_nosec(struct socket *sock, struct msghdr *msg)
 	return ret;
 }
 
+static int __sock_sendmsg(struct socket *sock, struct msghdr *msg)
+{
+	int err = security_socket_sendmsg(sock, msg,
+					  msg_data_left(msg));
+
+	return err ?: sock_sendmsg_nosec(sock, msg);
+}
+
 /**
  *	sock_sendmsg - send a message through @sock
  *	@sock: socket
@@ -665,10 +673,19 @@ static inline int sock_sendmsg_nosec(struct socket *sock, struct msghdr *msg)
  */
 int sock_sendmsg(struct socket *sock, struct msghdr *msg)
 {
-	int err = security_socket_sendmsg(sock, msg,
-					  msg_data_left(msg));
+	struct sockaddr_storage *save_addr = (struct sockaddr_storage *)msg->msg_name;
+	struct sockaddr_storage address;
+	int ret;
 
-	return err ?: sock_sendmsg_nosec(sock, msg);
+	if (msg->msg_name) {
+		memcpy(&address, msg->msg_name, msg->msg_namelen);
+		msg->msg_name = &address;
+	}
+
+	ret = __sock_sendmsg(sock, msg);
+	msg->msg_name = save_addr;
+
+	return ret;
 }
 EXPORT_SYMBOL(sock_sendmsg);
 
@@ -975,7 +992,7 @@ static ssize_t sock_write_iter(struct kiocb *iocb, struct iov_iter *from)
 	if (sock->type == SOCK_SEQPACKET)
 		msg.msg_flags |= MSG_EOR;
 
-	res = sock_sendmsg(sock, &msg);
+	res = __sock_sendmsg(sock, &msg);
 	*from = msg.msg_iter;
 	return res;
 }
@@ -1908,7 +1925,7 @@ int __sys_sendto(int fd, void __user *buff, size_t len, unsigned int flags,
 	if (sock->file->f_flags & O_NONBLOCK)
 		flags |= MSG_DONTWAIT;
 	msg.msg_flags = flags;
-	err = sock_sendmsg(sock, &msg);
+	err = __sock_sendmsg(sock, &msg);
 
 out_put:
 	fput_light(sock->file, fput_needed);
@@ -2236,7 +2253,7 @@ static int ___sys_sendmsg(struct socket *sock, struct user_msghdr __user *msg,
 		err = sock_sendmsg_nosec(sock, msg_sys);
 		goto out_freectl;
 	}
-	err = sock_sendmsg(sock, msg_sys);
+	err = __sock_sendmsg(sock, msg_sys);
 	/*
 	 * If this is sendmmsg() and sending to current destination address was
 	 * successful, remember it.
-- 
GitLab


From 234720cb2d0ca060621aa1800546d18ef360491b Mon Sep 17 00:00:00 2001
From: Artem Chernyshev <artem.chernyshev@red-soft.ru>
Date: Tue, 5 Sep 2023 15:40:48 +0300
Subject: [PATCH 184/298] RDMA/cxgb4: Check skb value for failure to allocate

[ Upstream commit 8fb8a82086f5bda6893ea6557c5a458e4549c6d7 ]

get_skb() can fail to allocate skb, so check it.

Found by Linux Verification Center (linuxtesting.org) with SVACE.

Fixes: 5be78ee924ae ("RDMA/cxgb4: Fix LE hash collision bug for active open connection")
Signed-off-by: Artem Chernyshev <artem.chernyshev@red-soft.ru>
Link: https://lore.kernel.org/r/20230905124048.284165-1-artem.chernyshev@red-soft.ru
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/infiniband/hw/cxgb4/cm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/infiniband/hw/cxgb4/cm.c b/drivers/infiniband/hw/cxgb4/cm.c
index a252b13958b3..e8d2135df22d 100644
--- a/drivers/infiniband/hw/cxgb4/cm.c
+++ b/drivers/infiniband/hw/cxgb4/cm.c
@@ -1922,6 +1922,9 @@ static int send_fw_act_open_req(struct c4iw_ep *ep, unsigned int atid)
 	int win;
 
 	skb = get_skb(NULL, sizeof(*req), GFP_KERNEL);
+	if (!skb)
+		return -ENOMEM;
+
 	req = __skb_put_zero(skb, sizeof(*req));
 	req->op_compl = htonl(WR_OP_V(FW_OFLD_CONNECTION_WR));
 	req->len16_pkd = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*req), 16)));
-- 
GitLab


From 44481b244fcaa2b895a53081d6204c574720c38c Mon Sep 17 00:00:00 2001
From: Hans de Goede <hdegoede@redhat.com>
Date: Thu, 5 Oct 2023 20:26:38 +0200
Subject: [PATCH 185/298] HID: logitech-hidpp: Fix kernel crash on receiver USB
 disconnect

commit dac501397b9d81e4782232c39f94f4307b137452 upstream.

hidpp_connect_event() has *four* time-of-check vs time-of-use (TOCTOU)
races when it races with itself.

hidpp_connect_event() primarily runs from a workqueue but it also runs
on probe() and if a "device-connected" packet is received by the hw
when the thread running hidpp_connect_event() from probe() is waiting on
the hw, then a second thread running hidpp_connect_event() will be
started from the workqueue.

This opens the following races (note the below code is simplified):

1. Retrieving + printing the protocol (harmless race):

	if (!hidpp->protocol_major) {
		hidpp_root_get_protocol_version()
		hidpp->protocol_major = response.rap.params[0];
	}

We can actually see this race hit in the dmesg in the abrt output
attached to rhbz#2227968:

[ 3064.624215] logitech-hidpp-device 0003:046D:4071.0049: HID++ 4.5 device connected.
[ 3064.658184] logitech-hidpp-device 0003:046D:4071.0049: HID++ 4.5 device connected.

Testing with extra logging added has shown that after this the 2 threads
take turn grabbing the hw access mutex (send_mutex) so they ping-pong
through all the other TOCTOU cases managing to hit all of them:

2. Updating the name to the HIDPP name (harmless race):

	if (hidpp->name == hdev->name) {
		...
		hidpp->name = new_name;
	}

3. Initializing the power_supply class for the battery (problematic!):

hidpp_initialize_battery()
{
        if (hidpp->battery.ps)
                return 0;

	probe_battery(); /* Blocks, threads take turns executing this */

	hidpp->battery.desc.properties =
		devm_kmemdup(dev, hidpp_battery_props, cnt, GFP_KERNEL);

	hidpp->battery.ps =
		devm_power_supply_register(&hidpp->hid_dev->dev,
					   &hidpp->battery.desc, cfg);
}

4. Creating delayed input_device (potentially problematic):

	if (hidpp->delayed_input)
		return;

	hidpp->delayed_input = hidpp_allocate_input(hdev);

The really big problem here is 3. Hitting the race leads to the following
sequence:

	hidpp->battery.desc.properties =
		devm_kmemdup(dev, hidpp_battery_props, cnt, GFP_KERNEL);

	hidpp->battery.ps =
		devm_power_supply_register(&hidpp->hid_dev->dev,
					   &hidpp->battery.desc, cfg);

	...

	hidpp->battery.desc.properties =
		devm_kmemdup(dev, hidpp_battery_props, cnt, GFP_KERNEL);

	hidpp->battery.ps =
		devm_power_supply_register(&hidpp->hid_dev->dev,
					   &hidpp->battery.desc, cfg);

So now we have registered 2 power supplies for the same battery,
which looks a bit weird from userspace's pov but this is not even
the really big problem.

Notice how:

1. This is all devm-maganaged
2. The hidpp->battery.desc struct is shared between the 2 power supplies
3. hidpp->battery.desc.properties points to the result from the second
   devm_kmemdup()

This causes a use after free scenario on USB disconnect of the receiver:
1. The last registered power supply class device gets unregistered
2. The memory from the last devm_kmemdup() call gets freed,
   hidpp->battery.desc.properties now points to freed memory
3. The first registered power supply class device gets unregistered,
   this involves sending a remove uevent to userspace which invokes
   power_supply_uevent() to fill the uevent data
4. power_supply_uevent() uses hidpp->battery.desc.properties which
   now points to freed memory leading to backtraces like this one:

Sep 22 20:01:35 eric kernel: BUG: unable to handle page fault for address: ffffb2140e017f08
...
Sep 22 20:01:35 eric kernel: Workqueue: usb_hub_wq hub_event
Sep 22 20:01:35 eric kernel: RIP: 0010:power_supply_uevent+0xee/0x1d0
...
Sep 22 20:01:35 eric kernel:  ? asm_exc_page_fault+0x26/0x30
Sep 22 20:01:35 eric kernel:  ? power_supply_uevent+0xee/0x1d0
Sep 22 20:01:35 eric kernel:  ? power_supply_uevent+0x10d/0x1d0
Sep 22 20:01:35 eric kernel:  dev_uevent+0x10f/0x2d0
Sep 22 20:01:35 eric kernel:  kobject_uevent_env+0x291/0x680
Sep 22 20:01:35 eric kernel:  power_supply_unregister+0x8e/0xa0
Sep 22 20:01:35 eric kernel:  release_nodes+0x3d/0xb0
Sep 22 20:01:35 eric kernel:  devres_release_group+0xfc/0x130
Sep 22 20:01:35 eric kernel:  hid_device_remove+0x56/0xa0
Sep 22 20:01:35 eric kernel:  device_release_driver_internal+0x19f/0x200
Sep 22 20:01:35 eric kernel:  bus_remove_device+0xc6/0x130
Sep 22 20:01:35 eric kernel:  device_del+0x15c/0x3f0
Sep 22 20:01:35 eric kernel:  ? __queue_work+0x1df/0x440
Sep 22 20:01:35 eric kernel:  hid_destroy_device+0x4b/0x60
Sep 22 20:01:35 eric kernel:  logi_dj_remove+0x9a/0x100 [hid_logitech_dj 5c91534a0ead2b65e04dd799a0437e3b99b21bc4]
Sep 22 20:01:35 eric kernel:  hid_device_remove+0x44/0xa0
Sep 22 20:01:35 eric kernel:  device_release_driver_internal+0x19f/0x200
Sep 22 20:01:35 eric kernel:  bus_remove_device+0xc6/0x130
Sep 22 20:01:35 eric kernel:  device_del+0x15c/0x3f0
Sep 22 20:01:35 eric kernel:  ? __queue_work+0x1df/0x440
Sep 22 20:01:35 eric kernel:  hid_destroy_device+0x4b/0x60
Sep 22 20:01:35 eric kernel:  usbhid_disconnect+0x47/0x60 [usbhid 727dcc1c0b94e6b4418727a468398ac3bca492f3]
Sep 22 20:01:35 eric kernel:  usb_unbind_interface+0x90/0x270
Sep 22 20:01:35 eric kernel:  device_release_driver_internal+0x19f/0x200
Sep 22 20:01:35 eric kernel:  bus_remove_device+0xc6/0x130
Sep 22 20:01:35 eric kernel:  device_del+0x15c/0x3f0
Sep 22 20:01:35 eric kernel:  ? kobject_put+0xa0/0x1d0
Sep 22 20:01:35 eric kernel:  usb_disable_device+0xcd/0x1e0
Sep 22 20:01:35 eric kernel:  usb_disconnect+0xde/0x2c0
Sep 22 20:01:35 eric kernel:  usb_disconnect+0xc3/0x2c0
Sep 22 20:01:35 eric kernel:  hub_event+0xe80/0x1c10

There have been quite a few bug reports (see Link tags) about this crash.

Fix all the TOCTOU issues, including the really bad power-supply related
system crash on USB disconnect, by making probe() use the workqueue for
running hidpp_connect_event() too, so that it can never run more then once.

Link: https://bugzilla.redhat.com/show_bug.cgi?id=2227221
Link: https://bugzilla.redhat.com/show_bug.cgi?id=2227968
Link: https://bugzilla.redhat.com/show_bug.cgi?id=2227968
Link: https://bugzilla.redhat.com/show_bug.cgi?id=2242189
Link: https://bugzilla.kernel.org/show_bug.cgi?id=217412#c58
Cc: stable@vger.kernel.org
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20231005182638.3776-1-hdegoede@redhat.com
Signed-off-by: Benjamin Tissoires <bentiss@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/hid/hid-logitech-hidpp.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c
index 5b6bb24df63e..f2982784c4fe 100644
--- a/drivers/hid/hid-logitech-hidpp.c
+++ b/drivers/hid/hid-logitech-hidpp.c
@@ -3129,7 +3129,8 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id)
 	/* Allow incoming packets */
 	hid_device_io_start(hdev);
 
-	hidpp_connect_event(hidpp);
+	schedule_work(&hidpp->work);
+	flush_work(&hidpp->work);
 
 	return ret;
 
-- 
GitLab


From bb7e3a019b52d829949d02b64ebab37838148fbf Mon Sep 17 00:00:00 2001
From: Jan Kara <jack@suse.cz>
Date: Wed, 4 Oct 2023 15:32:01 +0200
Subject: [PATCH 186/298] quota: Fix slow quotaoff

commit 869b6ea1609f655a43251bf41757aa44e5350a8f upstream.

Eric has reported that commit dabc8b207566 ("quota: fix dqput() to
follow the guarantees dquot_srcu should provide") heavily increases
runtime of generic/270 xfstest for ext4 in nojournal mode. The reason
for this is that ext4 in nojournal mode leaves dquots dirty until the last
dqput() and thus the cleanup done in quota_release_workfn() has to write
them all. Due to the way quota_release_workfn() is written this results
in synchronize_srcu() call for each dirty dquot which makes the dquot
cleanup when turning quotas off extremely slow.

To be able to avoid synchronize_srcu() for each dirty dquot we need to
rework how we track dquots to be cleaned up. Instead of keeping the last
dquot reference while it is on releasing_dquots list, we drop it right
away and mark the dquot with new DQ_RELEASING_B bit instead. This way we
can we can remove dquot from releasing_dquots list when new reference to
it is acquired and thus there's no need to call synchronize_srcu() each
time we drop dq_list_lock.

References: https://lore.kernel.org/all/ZRytn6CxFK2oECUt@debian-BULLSEYE-live-builder-AMD64
Reported-by: Eric Whitney <enwlinux@gmail.com>
Fixes: dabc8b207566 ("quota: fix dqput() to follow the guarantees dquot_srcu should provide")
CC: stable@vger.kernel.org
Signed-off-by: Jan Kara <jack@suse.cz>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 fs/quota/dquot.c         | 66 ++++++++++++++++++++++++----------------
 include/linux/quota.h    |  4 ++-
 include/linux/quotaops.h |  2 +-
 3 files changed, 43 insertions(+), 29 deletions(-)

diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c
index 25bd1fdaebac..190aee02bd6c 100644
--- a/fs/quota/dquot.c
+++ b/fs/quota/dquot.c
@@ -231,19 +231,18 @@ static void put_quota_format(struct quota_format_type *fmt)
  * All dquots are placed to the end of inuse_list when first created, and this
  * list is used for invalidate operation, which must look at every dquot.
  *
- * When the last reference of a dquot will be dropped, the dquot will be
- * added to releasing_dquots. We'd then queue work item which would call
+ * When the last reference of a dquot is dropped, the dquot is added to
+ * releasing_dquots. We'll then queue work item which will call
  * synchronize_srcu() and after that perform the final cleanup of all the
- * dquots on the list. Both releasing_dquots and free_dquots use the
- * dq_free list_head in the dquot struct. When a dquot is removed from
- * releasing_dquots, a reference count is always subtracted, and if
- * dq_count == 0 at that point, the dquot will be added to the free_dquots.
+ * dquots on the list. Each cleaned up dquot is moved to free_dquots list.
+ * Both releasing_dquots and free_dquots use the dq_free list_head in the dquot
+ * struct.
  *
- * Unused dquots (dq_count == 0) are added to the free_dquots list when freed,
- * and this list is searched whenever we need an available dquot.  Dquots are
- * removed from the list as soon as they are used again, and
- * dqstats.free_dquots gives the number of dquots on the list. When
- * dquot is invalidated it's completely released from memory.
+ * Unused and cleaned up dquots are in the free_dquots list and this list is
+ * searched whenever we need an available dquot. Dquots are removed from the
+ * list as soon as they are used again and dqstats.free_dquots gives the number
+ * of dquots on the list. When dquot is invalidated it's completely released
+ * from memory.
  *
  * Dirty dquots are added to the dqi_dirty_list of quota_info when mark
  * dirtied, and this list is searched when writing dirty dquots back to
@@ -321,6 +320,7 @@ static inline void put_dquot_last(struct dquot *dquot)
 static inline void put_releasing_dquots(struct dquot *dquot)
 {
 	list_add_tail(&dquot->dq_free, &releasing_dquots);
+	set_bit(DQ_RELEASING_B, &dquot->dq_flags);
 }
 
 static inline void remove_free_dquot(struct dquot *dquot)
@@ -328,8 +328,10 @@ static inline void remove_free_dquot(struct dquot *dquot)
 	if (list_empty(&dquot->dq_free))
 		return;
 	list_del_init(&dquot->dq_free);
-	if (!atomic_read(&dquot->dq_count))
+	if (!test_bit(DQ_RELEASING_B, &dquot->dq_flags))
 		dqstats_dec(DQST_FREE_DQUOTS);
+	else
+		clear_bit(DQ_RELEASING_B, &dquot->dq_flags);
 }
 
 static inline void put_inuse(struct dquot *dquot)
@@ -571,12 +573,6 @@ static void invalidate_dquots(struct super_block *sb, int type)
 			continue;
 		/* Wait for dquot users */
 		if (atomic_read(&dquot->dq_count)) {
-			/* dquot in releasing_dquots, flush and retry */
-			if (!list_empty(&dquot->dq_free)) {
-				spin_unlock(&dq_list_lock);
-				goto restart;
-			}
-
 			atomic_inc(&dquot->dq_count);
 			spin_unlock(&dq_list_lock);
 			/*
@@ -595,6 +591,15 @@ static void invalidate_dquots(struct super_block *sb, int type)
 			 * restart. */
 			goto restart;
 		}
+		/*
+		 * The last user already dropped its reference but dquot didn't
+		 * get fully cleaned up yet. Restart the scan which flushes the
+		 * work cleaning up released dquots.
+		 */
+		if (test_bit(DQ_RELEASING_B, &dquot->dq_flags)) {
+			spin_unlock(&dq_list_lock);
+			goto restart;
+		}
 		/*
 		 * Quota now has no users and it has been written on last
 		 * dqput()
@@ -686,6 +691,13 @@ int dquot_writeback_dquots(struct super_block *sb, int type)
 						 dq_dirty);
 
 			WARN_ON(!dquot_active(dquot));
+			/* If the dquot is releasing we should not touch it */
+			if (test_bit(DQ_RELEASING_B, &dquot->dq_flags)) {
+				spin_unlock(&dq_list_lock);
+				flush_delayed_work(&quota_release_work);
+				spin_lock(&dq_list_lock);
+				continue;
+			}
 
 			/* Now we have active dquot from which someone is
  			 * holding reference so we can safely just increase
@@ -799,18 +811,18 @@ static void quota_release_workfn(struct work_struct *work)
 	/* Exchange the list head to avoid livelock. */
 	list_replace_init(&releasing_dquots, &rls_head);
 	spin_unlock(&dq_list_lock);
+	synchronize_srcu(&dquot_srcu);
 
 restart:
-	synchronize_srcu(&dquot_srcu);
 	spin_lock(&dq_list_lock);
 	while (!list_empty(&rls_head)) {
 		dquot = list_first_entry(&rls_head, struct dquot, dq_free);
-		/* Dquot got used again? */
-		if (atomic_read(&dquot->dq_count) > 1) {
-			remove_free_dquot(dquot);
-			atomic_dec(&dquot->dq_count);
-			continue;
-		}
+		WARN_ON_ONCE(atomic_read(&dquot->dq_count));
+		/*
+		 * Note that DQ_RELEASING_B protects us from racing with
+		 * invalidate_dquots() calls so we are safe to work with the
+		 * dquot even after we drop dq_list_lock.
+		 */
 		if (dquot_dirty(dquot)) {
 			spin_unlock(&dq_list_lock);
 			/* Commit dquot before releasing */
@@ -824,7 +836,6 @@ static void quota_release_workfn(struct work_struct *work)
 		}
 		/* Dquot is inactive and clean, now move it to free list */
 		remove_free_dquot(dquot);
-		atomic_dec(&dquot->dq_count);
 		put_dquot_last(dquot);
 	}
 	spin_unlock(&dq_list_lock);
@@ -865,6 +876,7 @@ void dqput(struct dquot *dquot)
 	BUG_ON(!list_empty(&dquot->dq_free));
 #endif
 	put_releasing_dquots(dquot);
+	atomic_dec(&dquot->dq_count);
 	spin_unlock(&dq_list_lock);
 	queue_delayed_work(system_unbound_wq, &quota_release_work, 1);
 }
@@ -953,7 +965,7 @@ struct dquot *dqget(struct super_block *sb, struct kqid qid)
 		dqstats_inc(DQST_LOOKUPS);
 	}
 	/* Wait for dq_lock - after this we know that either dquot_release() is
-	 * already finished or it will be canceled due to dq_count > 1 test */
+	 * already finished or it will be canceled due to dq_count > 0 test */
 	wait_on_dquot(dquot);
 	/* Read the dquot / allocate space in quota file */
 	if (!dquot_active(dquot)) {
diff --git a/include/linux/quota.h b/include/linux/quota.h
index 27aab84fcbaa..b93cb93d1956 100644
--- a/include/linux/quota.h
+++ b/include/linux/quota.h
@@ -285,7 +285,9 @@ static inline void dqstats_dec(unsigned int type)
 #define DQ_FAKE_B	3	/* no limits only usage */
 #define DQ_READ_B	4	/* dquot was read into memory */
 #define DQ_ACTIVE_B	5	/* dquot is active (dquot_release not called) */
-#define DQ_LASTSET_B	6	/* Following 6 bits (see QIF_) are reserved\
+#define DQ_RELEASING_B	6	/* dquot is in releasing_dquots list waiting
+				 * to be cleaned up */
+#define DQ_LASTSET_B	7	/* Following 6 bits (see QIF_) are reserved\
 				 * for the mask of entries set via SETQUOTA\
 				 * quotactl. They are set under dq_data_lock\
 				 * and the quota format handling dquot can\
diff --git a/include/linux/quotaops.h b/include/linux/quotaops.h
index ec10897f7f60..844b5836d11d 100644
--- a/include/linux/quotaops.h
+++ b/include/linux/quotaops.h
@@ -59,7 +59,7 @@ static inline bool dquot_is_busy(struct dquot *dquot)
 {
 	if (test_bit(DQ_MOD_B, &dquot->dq_flags))
 		return true;
-	if (atomic_read(&dquot->dq_count) > 1)
+	if (atomic_read(&dquot->dq_count) > 0)
 		return true;
 	return false;
 }
-- 
GitLab


From 9b0cdcc969dbf373a70b3433cbacc204c65be592 Mon Sep 17 00:00:00 2001
From: Jordan Rife <jrife@google.com>
Date: Thu, 21 Sep 2023 18:46:42 -0500
Subject: [PATCH 187/298] net: prevent address rewrite in kernel_bind()

commit c889a99a21bf124c3db08d09df919f0eccc5ea4c upstream.

Similar to the change in commit 0bdf399342c5("net: Avoid address
overwrite in kernel_connect"), BPF hooks run on bind may rewrite the
address passed to kernel_bind(). This change

1) Makes a copy of the bind address in kernel_bind() to insulate
   callers.
2) Replaces direct calls to sock->ops->bind() in net with kernel_bind()

Link: https://lore.kernel.org/netdev/20230912013332.2048422-1-jrife@google.com/
Fixes: 4fbac77d2d09 ("bpf: Hooks for sys_bind")
Cc: stable@vger.kernel.org
Reviewed-by: Willem de Bruijn <willemb@google.com>
Signed-off-by: Jordan Rife <jrife@google.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/netfilter/ipvs/ip_vs_sync.c | 4 ++--
 net/rds/tcp_connect.c           | 2 +-
 net/rds/tcp_listen.c            | 2 +-
 net/socket.c                    | 6 +++++-
 4 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/net/netfilter/ipvs/ip_vs_sync.c b/net/netfilter/ipvs/ip_vs_sync.c
index e0a4f59a68a2..c133ce825c2d 100644
--- a/net/netfilter/ipvs/ip_vs_sync.c
+++ b/net/netfilter/ipvs/ip_vs_sync.c
@@ -1444,7 +1444,7 @@ static int bind_mcastif_addr(struct socket *sock, struct net_device *dev)
 	sin.sin_addr.s_addr  = addr;
 	sin.sin_port         = 0;
 
-	return sock->ops->bind(sock, (struct sockaddr*)&sin, sizeof(sin));
+	return kernel_bind(sock, (struct sockaddr *)&sin, sizeof(sin));
 }
 
 static void get_mcast_sockaddr(union ipvs_sockaddr *sa, int *salen,
@@ -1551,7 +1551,7 @@ static int make_receive_sock(struct netns_ipvs *ipvs, int id,
 
 	get_mcast_sockaddr(&mcast_addr, &salen, &ipvs->bcfg, id);
 	sock->sk->sk_bound_dev_if = dev->ifindex;
-	result = sock->ops->bind(sock, (struct sockaddr *)&mcast_addr, salen);
+	result = kernel_bind(sock, (struct sockaddr *)&mcast_addr, salen);
 	if (result < 0) {
 		pr_err("Error binding to the multicast addr\n");
 		goto error;
diff --git a/net/rds/tcp_connect.c b/net/rds/tcp_connect.c
index 23d6d2612708..63efe60fda1f 100644
--- a/net/rds/tcp_connect.c
+++ b/net/rds/tcp_connect.c
@@ -141,7 +141,7 @@ int rds_tcp_conn_path_connect(struct rds_conn_path *cp)
 		addrlen = sizeof(sin);
 	}
 
-	ret = sock->ops->bind(sock, addr, addrlen);
+	ret = kernel_bind(sock, addr, addrlen);
 	if (ret) {
 		rdsdebug("bind failed with %d at address %pI6c\n",
 			 ret, &conn->c_laddr);
diff --git a/net/rds/tcp_listen.c b/net/rds/tcp_listen.c
index 0d095d3f5fee..37f4a8ca3ac8 100644
--- a/net/rds/tcp_listen.c
+++ b/net/rds/tcp_listen.c
@@ -332,7 +332,7 @@ struct socket *rds_tcp_listen_init(struct net *net, bool isv6)
 		addr_len = sizeof(*sin);
 	}
 
-	ret = sock->ops->bind(sock, (struct sockaddr *)&ss, addr_len);
+	ret = kernel_bind(sock, (struct sockaddr *)&ss, addr_len);
 	if (ret < 0) {
 		rdsdebug("could not bind %s listener socket: %d\n",
 			 isv6 ? "IPv6" : "IPv4", ret);
diff --git a/net/socket.c b/net/socket.c
index d9eaab948d69..328f584345fb 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -3427,7 +3427,11 @@ static long compat_sock_ioctl(struct file *file, unsigned int cmd,
 
 int kernel_bind(struct socket *sock, struct sockaddr *addr, int addrlen)
 {
-	return sock->ops->bind(sock, addr, addrlen);
+	struct sockaddr_storage address;
+
+	memcpy(&address, addr, addrlen);
+
+	return sock->ops->bind(sock, (struct sockaddr *)&address, addrlen);
 }
 EXPORT_SYMBOL(kernel_bind);
 
-- 
GitLab


From 0abc6ed322027bea272f59452a1736a1727c0407 Mon Sep 17 00:00:00 2001
From: Martin Fuzzey <martin.fuzzey@flowbird.group>
Date: Tue, 10 Oct 2023 15:19:28 +0200
Subject: [PATCH 188/298] drm: etvnaviv: fix bad backport leading to warning

When updating from 5.4.219 -> 5.4.256 I started getting a runtime warning:

[   58.229857] ------------[ cut here ]------------
[   58.234599] WARNING: CPU: 1 PID: 565 at drivers/gpu/drm/drm_gem.c:1020 drm_gem_object_put+0x90/0x98
[   58.249935] Modules linked in: qmi_wwan cdc_wdm option usb_wwan smsc95xx rsi_usb rsi_91x btrsi ci_hdrc_imx ci_hdrc
[   58.260499] ueventd: modprobe usb:v2F8Fp7FFFd0200dc00dsc00dp00icFEisc01ip02in00 done
[   58.288877] CPU: 1 PID: 565 Comm: android.display Not tainted 5.4.256pkn-5.4-bsp-snapshot-svn-7423 #2195
[   58.288883] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree)
[   58.288888] Backtrace:
[   58.288912] [<c010e784>] (dump_backtrace) from [<c010eaa4>] (show_stack+0x20/0x24)
[   58.288920]  r7:00000000 r6:60010013 r5:00000000 r4:c14cd224
[   58.328337] [<c010ea84>] (show_stack) from [<c0cf9ca4>] (dump_stack+0xe8/0x120)
[   58.335661] [<c0cf9bbc>] (dump_stack) from [<c012efd0>] (__warn+0xd4/0xe8)
[   58.342542]  r10:eda54000 r9:c06ca53c r8:000003fc r7:00000009 r6:c111ed54 r5:00000000
[   58.350374]  r4:00000000 r3:76cf564a
[   58.353957] [<c012eefc>] (__warn) from [<c012f094>] (warn_slowpath_fmt+0xb0/0xc0)
[   58.361445]  r9:00000009 r8:c06ca53c r7:000003fc r6:c111ed54 r5:c1406048 r4:00000000
[   58.369198] [<c012efe8>] (warn_slowpath_fmt) from [<c06ca53c>] (drm_gem_object_put+0x90/0x98)
[   58.377728]  r9:edda7e40 r8:edd39360 r7:ad16e000 r6:edda7eb0 r5:00000000 r4:edaa3200
[   58.385524] [<c06ca4ac>] (drm_gem_object_put) from [<bf0125a8>] (etnaviv_gem_prime_mmap_obj+0x34/0x3c [etnaviv])
[   58.395704]  r5:00000000 r4:edaa3200
[   58.399334] [<bf012574>] (etnaviv_gem_prime_mmap_obj [etnaviv]) from [<bf0143a0>] (etnaviv_gem_mmap+0x3c/0x60 [etnaviv])
[   58.410205]  r5:edd39360 r4:00000000
[   58.413816] [<bf014364>] (etnaviv_gem_mmap [etnaviv]) from [<c02c5e08>] (mmap_region+0x37c/0x67c)
[   58.422689]  r5:ad16d000 r4:edda7eb8
[   58.426272] [<c02c5a8c>] (mmap_region) from [<c02c6528>] (do_mmap+0x420/0x544)
[   58.433500]  r10:000000fb r9:000fffff r8:ffffffff r7:00000001 r6:00000003 r5:00000001
[   58.441330]  r4:00001000
[   58.443876] [<c02c6108>] (do_mmap) from [<c02a5b2c>] (vm_mmap_pgoff+0xd0/0x100)
[   58.451190]  r10:eda54040 r9:00001000 r8:00000000 r7:00000000 r6:00000003 r5:c1406048
[   58.459020]  r4:edb8ff24
[   58.461561] [<c02a5a5c>] (vm_mmap_pgoff) from [<c02c3ac8>] (ksys_mmap_pgoff+0xdc/0x10c)
[   58.469570]  r10:000000c0 r9:edb8e000 r8:ed650b40 r7:00000003 r6:00001000 r5:00000000
[   58.477400]  r4:00000001
[   58.479941] [<c02c39ec>] (ksys_mmap_pgoff) from [<c02c3b24>] (sys_mmap_pgoff+0x2c/0x34)
[   58.487949]  r8:c0101224 r7:000000c0 r6:951ece38 r5:00010001 r4:00000065
[   58.494658] [<c02c3af8>] (sys_mmap_pgoff) from [<c0101000>] (ret_fast_syscall+0x0/0x28)

It looks like this was a backporting error for the upstream patch
963b2e8c428f "drm/etnaviv: fix reference leak when mmaping imported buffer"

In the 5.4 kernel there are 2 variants of the object put function:
	drm_gem_object_put() [which requires lock to be held]
	drm_gem_object_put_unlocked() [which requires lock to be NOT held]

In later kernels [5.14+] this has gone and there just drm_gem_object_put()
which requires lock to be NOT held.

So the memory leak pach, which added a call to drm_gem_object_put() was correct
on newer kernels but wrong on 5.4 and earlier ones.

So switch back to using the _unlocked variant for old kernels.
This should only be applied to the 5.4, 4.19 and 4.14 longterm branches;
mainline and more recent longterms already have the correct fix.

Signed-off-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Fixes: 0c6df5364798 "drm/etnaviv: fix reference leak when mmaping imported buffer" [5.4.y]
Fixes: 0838cb217a52 "drm/etnaviv: fix reference leak when mmaping imported buffer" [4.19.y]
Fixes: 1c9544fbc979 "drm/etnaviv: fix reference leak when mmaping imported buffer" [4.14.y]
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c
index a9506a390f98..3f9ff6bc7644 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c
@@ -96,7 +96,7 @@ static int etnaviv_gem_prime_mmap_obj(struct etnaviv_gem_object *etnaviv_obj,
 	ret = dma_buf_mmap(etnaviv_obj->base.dma_buf, vma, 0);
 	if (!ret) {
 		/* Drop the reference acquired by drm_gem_mmap_obj(). */
-		drm_gem_object_put(&etnaviv_obj->base);
+		drm_gem_object_put_unlocked(&etnaviv_obj->base);
 	}
 
 	return ret;
-- 
GitLab


From 7f1ff35da2258861c796de589d4a81f5c048587a Mon Sep 17 00:00:00 2001
From: Abhinav Kumar <quic_abhinavk@quicinc.com>
Date: Fri, 15 Sep 2023 13:44:25 -0700
Subject: [PATCH 189/298] drm/msm/dsi: skip the wait for video mode done if not
 applicable

[ Upstream commit ab483e3adcc178254eb1ce0fbdfbea65f86f1006 ]

dsi_wait4video_done() API waits for the DSI video mode engine to
become idle so that we can transmit the DCS commands in the
beginning of BLLP. However, with the current sequence, the MDP
timing engine is turned on after the panel's pre_enable() callback
which can send out the DCS commands needed to power up the panel.

During those cases, this API will always timeout and print out the
error spam leading to long bootup times and log flooding.

Fix this by checking if the DSI video engine was actually busy before
waiting for it to become idle otherwise this is a redundant wait.

changes in v2:
	- move the reg read below the video mode check
	- minor fixes in commit text

Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/34
Fixes: a689554ba6ed ("drm/msm: Initial add DSI connector support")
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/557853/
Link: https://lore.kernel.org/r/20230915204426.19011-1-quic_abhinavk@quicinc.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/gpu/drm/msm/dsi/dsi_host.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 059578faa1c6..5f4dd3659bf9 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1059,9 +1059,21 @@ static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
 
 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
 {
+	u32 data;
+
 	if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
 		return;
 
+	data = dsi_read(msm_host, REG_DSI_STATUS0);
+
+	/* if video mode engine is not busy, its because
+	 * either timing engine was not turned on or the
+	 * DSI controller has finished transmitting the video
+	 * data already, so no need to wait in those cases
+	 */
+	if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY))
+		return;
+
 	if (msm_host->power_on && msm_host->enabled) {
 		dsi_wait4video_done(msm_host);
 		/* delay 4 ms to skip BLLP */
-- 
GitLab


From cdb46be93c1f7bbf2c4649e9fc5fb147cfb5245d Mon Sep 17 00:00:00 2001
From: Dinghao Liu <dinghao.liu@zju.edu.cn>
Date: Sat, 7 Oct 2023 11:30:49 +0800
Subject: [PATCH 190/298] ieee802154: ca8210: Fix a potential UAF in
 ca8210_probe

[ Upstream commit f990874b1c98fe8e57ee9385669f501822979258 ]

If of_clk_add_provider() fails in ca8210_register_ext_clock(),
it calls clk_unregister() to release priv->clk and returns an
error. However, the caller ca8210_probe() then calls ca8210_remove(),
where priv->clk is freed again in ca8210_unregister_ext_clock(). In
this case, a use-after-free may happen in the second time we call
clk_unregister().

Fix this by removing the first clk_unregister(). Also, priv->clk could
be an error code on failure of clk_register_fixed_rate(). Use
IS_ERR_OR_NULL to catch this case in ca8210_unregister_ext_clock().

Fixes: ded845a781a5 ("ieee802154: Add CA8210 IEEE 802.15.4 device driver")
Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn>
Message-ID: <20231007033049.22353-1-dinghao.liu@zju.edu.cn>
Signed-off-by: Stefan Schmidt <stefan@datenfreihafen.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/net/ieee802154/ca8210.c | 17 +++--------------
 1 file changed, 3 insertions(+), 14 deletions(-)

diff --git a/drivers/net/ieee802154/ca8210.c b/drivers/net/ieee802154/ca8210.c
index f75faec23cc9..525f92e89669 100644
--- a/drivers/net/ieee802154/ca8210.c
+++ b/drivers/net/ieee802154/ca8210.c
@@ -2781,7 +2781,6 @@ static int ca8210_register_ext_clock(struct spi_device *spi)
 	struct device_node *np = spi->dev.of_node;
 	struct ca8210_priv *priv = spi_get_drvdata(spi);
 	struct ca8210_platform_data *pdata = spi->dev.platform_data;
-	int ret = 0;
 
 	if (!np)
 		return -EFAULT;
@@ -2798,18 +2797,8 @@ static int ca8210_register_ext_clock(struct spi_device *spi)
 		dev_crit(&spi->dev, "Failed to register external clk\n");
 		return PTR_ERR(priv->clk);
 	}
-	ret = of_clk_add_provider(np, of_clk_src_simple_get, priv->clk);
-	if (ret) {
-		clk_unregister(priv->clk);
-		dev_crit(
-			&spi->dev,
-			"Failed to register external clock as clock provider\n"
-		);
-	} else {
-		dev_info(&spi->dev, "External clock set as clock provider\n");
-	}
 
-	return ret;
+	return of_clk_add_provider(np, of_clk_src_simple_get, priv->clk);
 }
 
 /**
@@ -2821,8 +2810,8 @@ static void ca8210_unregister_ext_clock(struct spi_device *spi)
 {
 	struct ca8210_priv *priv = spi_get_drvdata(spi);
 
-	if (!priv->clk)
-		return
+	if (IS_ERR_OR_NULL(priv->clk))
+		return;
 
 	of_clk_del_provider(spi->dev.of_node);
 	clk_unregister(priv->clk);
-- 
GitLab


From b42515434f8fd84c2fdb748a47730c9e95289bfd Mon Sep 17 00:00:00 2001
From: Roger Pau Monne <roger.pau@citrix.com>
Date: Thu, 5 Oct 2023 16:08:31 +0200
Subject: [PATCH 191/298] xen-netback: use default TX queue size for vifs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

[ Upstream commit 66cf7435a26917c0c4d6245ad9137e7606e84fdf ]

Do not set netback interfaces (vifs) default TX queue size to the ring size.
The TX queue size is not related to the ring size, and using the ring size (32)
as the queue size can lead to packet drops.  Note the TX side of the vif
interface in the netback domain is the one receiving packets to be injected
to the guest.

Do not explicitly set the TX queue length to any value when creating the
interface, and instead use the system default.  Note that the queue length can
also be adjusted at runtime.

Fixes: f942dc2552b8 ('xen network backend driver')
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Ross Lagerwall <ross.lagerwall@citrix.com>
Acked-by: Wei Liu <wei.liu@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/net/xen-netback/interface.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/net/xen-netback/interface.c b/drivers/net/xen-netback/interface.c
index df2027082763..fadbde1d21ad 100644
--- a/drivers/net/xen-netback/interface.c
+++ b/drivers/net/xen-netback/interface.c
@@ -41,7 +41,6 @@
 #include <asm/xen/hypercall.h>
 #include <xen/balloon.h>
 
-#define XENVIF_QUEUE_LENGTH 32
 #define XENVIF_NAPI_WEIGHT  64
 
 /* Number of bytes allowed on the internal guest Rx queue. */
@@ -526,8 +525,6 @@ struct xenvif *xenvif_alloc(struct device *parent, domid_t domid,
 	dev->features = dev->hw_features | NETIF_F_RXCSUM;
 	dev->ethtool_ops = &xenvif_ethtool_ops;
 
-	dev->tx_queue_len = XENVIF_QUEUE_LENGTH;
-
 	dev->min_mtu = ETH_MIN_MTU;
 	dev->max_mtu = ETH_MAX_MTU - VLAN_ETH_HLEN;
 
-- 
GitLab


From ee5a2b98693b150a32e2741c2f87895ccd78249b Mon Sep 17 00:00:00 2001
From: Konstantin Meskhidze <konstantin.meskhidze@huawei.com>
Date: Tue, 5 Sep 2023 18:02:03 +0800
Subject: [PATCH 192/298] drm/vmwgfx: fix typo of sizeof argument

[ Upstream commit 39465cac283702a7d4a507a558db81898029c6d3 ]

Since size of 'header' pointer and '*header' structure is equal on 64-bit
machines issue probably didn't cause any wrong behavior. But anyway,
fixing typo is required.

Fixes: 7a73ba7469cb ("drm/vmwgfx: Use TTM handles instead of SIDs as user-space surface handles.")
Co-developed-by: Ivanov Mikhail <ivanov.mikhail1@huawei-partners.com>
Signed-off-by: Konstantin Meskhidze <konstantin.meskhidze@huawei.com>
Reviewed-by: Zack Rusin <zackr@vmware.com>
Signed-off-by: Zack Rusin <zackr@vmware.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230905100203.1716731-1-konstantin.meskhidze@huawei.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index e65554f5a89d..2480afa466f2 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -1834,7 +1834,7 @@ static int vmw_cmd_tex_state(struct vmw_private *dev_priv,
 	} *cmd;
 
 	SVGA3dTextureState *last_state = (SVGA3dTextureState *)
-	  ((unsigned long) header + header->size + sizeof(header));
+	  ((unsigned long) header + header->size + sizeof(*header));
 	SVGA3dTextureState *cur_state = (SVGA3dTextureState *)
 		((unsigned long) header + sizeof(struct vmw_tex_state_cmd));
 	struct vmw_resource_val_node *ctx_node;
-- 
GitLab


From b4208fa6e2c86583e30a03020d82790ce044694a Mon Sep 17 00:00:00 2001
From: Dan Carpenter <dan.carpenter@linaro.org>
Date: Fri, 6 Oct 2023 15:53:09 +0300
Subject: [PATCH 193/298] ixgbe: fix crash with empty VF macvlan list

[ Upstream commit 7b5add9af567c44e12196107f0fe106e194034fd ]

The adapter->vf_mvs.l list needs to be initialized even if the list is
empty.  Otherwise it will lead to crashes.

Fixes: a1cbb15c1397 ("ixgbe: Add macvlan support for VF")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Simon Horman <horms@kernel.org>
Reviewed-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
Link: https://lore.kernel.org/r/ZSADNdIw8zFx1xw2@kadam
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
index 6055a4917ff6..9b463ef62be5 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
@@ -28,6 +28,9 @@ static inline void ixgbe_alloc_vf_macvlans(struct ixgbe_adapter *adapter,
 	struct vf_macvlans *mv_list;
 	int num_vf_macvlans, i;
 
+	/* Initialize list of VF macvlans */
+	INIT_LIST_HEAD(&adapter->vf_mvs.l);
+
 	num_vf_macvlans = hw->mac.num_rar_entries -
 			  (IXGBE_MAX_PF_MACVLANS + 1 + num_vfs);
 	if (!num_vf_macvlans)
@@ -36,8 +39,6 @@ static inline void ixgbe_alloc_vf_macvlans(struct ixgbe_adapter *adapter,
 	mv_list = kcalloc(num_vf_macvlans, sizeof(struct vf_macvlans),
 			  GFP_KERNEL);
 	if (mv_list) {
-		/* Initialize list of VF macvlans */
-		INIT_LIST_HEAD(&adapter->vf_mvs.l);
 		for (i = 0; i < num_vf_macvlans; i++) {
 			mv_list[i].vf = -1;
 			mv_list[i].free = true;
-- 
GitLab


From e863f5720a5680e50c4cecf12424d7cc31b3eb0a Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Mon, 9 Oct 2023 12:31:10 +0000
Subject: [PATCH 194/298] net: nfc: fix races in nfc_llcp_sock_get() and
 nfc_llcp_sock_get_sn()

[ Upstream commit 31c07dffafce914c1d1543c135382a11ff058d93 ]

Sili Luo reported a race in nfc_llcp_sock_get(), leading to UAF.

Getting a reference on the socket found in a lookup while
holding a lock should happen before releasing the lock.

nfc_llcp_sock_get_sn() has a similar problem.

Finally nfc_llcp_recv_snl() needs to make sure the socket
found by nfc_llcp_sock_from_sn() does not disappear.

Fixes: 8f50020ed9b8 ("NFC: LLCP late binding")
Reported-by: Sili Luo <rootlab@huawei.com>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Willy Tarreau <w@1wt.eu>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231009123110.3735515-1-edumazet@google.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/nfc/llcp_core.c | 30 ++++++++++++------------------
 1 file changed, 12 insertions(+), 18 deletions(-)

diff --git a/net/nfc/llcp_core.c b/net/nfc/llcp_core.c
index bdc1a9d0965a..c30b28465e64 100644
--- a/net/nfc/llcp_core.c
+++ b/net/nfc/llcp_core.c
@@ -216,17 +216,13 @@ static struct nfc_llcp_sock *nfc_llcp_sock_get(struct nfc_llcp_local *local,
 
 		if (tmp_sock->ssap == ssap && tmp_sock->dsap == dsap) {
 			llcp_sock = tmp_sock;
+			sock_hold(&llcp_sock->sk);
 			break;
 		}
 	}
 
 	read_unlock(&local->sockets.lock);
 
-	if (llcp_sock == NULL)
-		return NULL;
-
-	sock_hold(&llcp_sock->sk);
-
 	return llcp_sock;
 }
 
@@ -338,7 +334,8 @@ static int nfc_llcp_wks_sap(const char *service_name, size_t service_name_len)
 
 static
 struct nfc_llcp_sock *nfc_llcp_sock_from_sn(struct nfc_llcp_local *local,
-					    const u8 *sn, size_t sn_len)
+					    const u8 *sn, size_t sn_len,
+					    bool needref)
 {
 	struct sock *sk;
 	struct nfc_llcp_sock *llcp_sock, *tmp_sock;
@@ -374,6 +371,8 @@ struct nfc_llcp_sock *nfc_llcp_sock_from_sn(struct nfc_llcp_local *local,
 
 		if (memcmp(sn, tmp_sock->service_name, sn_len) == 0) {
 			llcp_sock = tmp_sock;
+			if (needref)
+				sock_hold(&llcp_sock->sk);
 			break;
 		}
 	}
@@ -415,7 +414,8 @@ u8 nfc_llcp_get_sdp_ssap(struct nfc_llcp_local *local,
 		 * to this service name.
 		 */
 		if (nfc_llcp_sock_from_sn(local, sock->service_name,
-					  sock->service_name_len) != NULL) {
+					  sock->service_name_len,
+					  false) != NULL) {
 			mutex_unlock(&local->sdp_lock);
 
 			return LLCP_SAP_MAX;
@@ -816,16 +816,7 @@ static struct nfc_llcp_sock *nfc_llcp_connecting_sock_get(struct nfc_llcp_local
 static struct nfc_llcp_sock *nfc_llcp_sock_get_sn(struct nfc_llcp_local *local,
 						  const u8 *sn, size_t sn_len)
 {
-	struct nfc_llcp_sock *llcp_sock;
-
-	llcp_sock = nfc_llcp_sock_from_sn(local, sn, sn_len);
-
-	if (llcp_sock == NULL)
-		return NULL;
-
-	sock_hold(&llcp_sock->sk);
-
-	return llcp_sock;
+	return nfc_llcp_sock_from_sn(local, sn, sn_len, true);
 }
 
 static const u8 *nfc_llcp_connect_sn(const struct sk_buff *skb, size_t *sn_len)
@@ -1290,7 +1281,8 @@ static void nfc_llcp_recv_snl(struct nfc_llcp_local *local,
 			}
 
 			llcp_sock = nfc_llcp_sock_from_sn(local, service_name,
-							  service_name_len);
+							  service_name_len,
+							  true);
 			if (!llcp_sock) {
 				sap = 0;
 				goto add_snl;
@@ -1310,6 +1302,7 @@ static void nfc_llcp_recv_snl(struct nfc_llcp_local *local,
 
 				if (sap == LLCP_SAP_MAX) {
 					sap = 0;
+					nfc_llcp_sock_put(llcp_sock);
 					goto add_snl;
 				}
 
@@ -1327,6 +1320,7 @@ static void nfc_llcp_recv_snl(struct nfc_llcp_local *local,
 
 			pr_debug("%p %d\n", llcp_sock, sap);
 
+			nfc_llcp_sock_put(llcp_sock);
 add_snl:
 			sdp = nfc_llcp_build_sdres_tlv(tid, sap);
 			if (sdp == NULL)
-- 
GitLab


From a686f84101680b8442181a8846fbd3c934653729 Mon Sep 17 00:00:00 2001
From: Jeremy Cline <jeremy@jcline.org>
Date: Mon, 9 Oct 2023 16:00:54 -0400
Subject: [PATCH 195/298] nfc: nci: assert requested protocol is valid

[ Upstream commit 354a6e707e29cb0c007176ee5b8db8be7bd2dee0 ]

The protocol is used in a bit mask to determine if the protocol is
supported. Assert the provided protocol is less than the maximum
defined so it doesn't potentially perform a shift-out-of-bounds and
provide a clearer error for undefined protocols vs unsupported ones.

Fixes: 6a2968aaf50c ("NFC: basic NCI protocol implementation")
Reported-and-tested-by: syzbot+0839b78e119aae1fec78@syzkaller.appspotmail.com
Closes: https://syzkaller.appspot.com/bug?extid=0839b78e119aae1fec78
Signed-off-by: Jeremy Cline <jeremy@jcline.org>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://lore.kernel.org/r/20231009200054.82557-1-jeremy@jcline.org
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/nfc/nci/core.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/net/nfc/nci/core.c b/net/nfc/nci/core.c
index 66608e6c5b0e..33723d843e47 100644
--- a/net/nfc/nci/core.c
+++ b/net/nfc/nci/core.c
@@ -906,6 +906,11 @@ static int nci_activate_target(struct nfc_dev *nfc_dev,
 		return -EINVAL;
 	}
 
+	if (protocol >= NFC_PROTO_MAX) {
+		pr_err("the requested nfc protocol is invalid\n");
+		return -EINVAL;
+	}
+
 	if (!(nci_target->supported_protocols & (1 << protocol))) {
 		pr_err("target does not support the requested protocol 0x%x\n",
 		       protocol);
-- 
GitLab


From 55d1e6231a0b98ffcc5eacdae995fa7bd74bf6a0 Mon Sep 17 00:00:00 2001
From: Waiman Long <longman@redhat.com>
Date: Tue, 10 Oct 2023 22:48:42 -0400
Subject: [PATCH 196/298] workqueue: Override implicit ordered attribute in
 workqueue_apply_unbound_cpumask()

[ Upstream commit ca10d851b9ad0338c19e8e3089e24d565ebfffd7 ]

Commit 5c0338c68706 ("workqueue: restore WQ_UNBOUND/max_active==1
to be ordered") enabled implicit ordered attribute to be added to
WQ_UNBOUND workqueues with max_active of 1. This prevented the changing
of attributes to these workqueues leading to fix commit 0a94efb5acbb
("workqueue: implicit ordered attribute should be overridable").

However, workqueue_apply_unbound_cpumask() was not updated at that time.
So sysfs changes to wq_unbound_cpumask has no effect on WQ_UNBOUND
workqueues with implicit ordered attribute. Since not all WQ_UNBOUND
workqueues are visible on sysfs, we are not able to make all the
necessary cpumask changes even if we iterates all the workqueue cpumasks
in sysfs and changing them one by one.

Fix this problem by applying the corresponding change made
to apply_workqueue_attrs_locked() in the fix commit to
workqueue_apply_unbound_cpumask().

Fixes: 5c0338c68706 ("workqueue: restore WQ_UNBOUND/max_active==1 to be ordered")
Signed-off-by: Waiman Long <longman@redhat.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 kernel/workqueue.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/kernel/workqueue.c b/kernel/workqueue.c
index 5533206cb6f4..017939097451 100644
--- a/kernel/workqueue.c
+++ b/kernel/workqueue.c
@@ -5087,9 +5087,13 @@ static int workqueue_apply_unbound_cpumask(void)
 	list_for_each_entry(wq, &workqueues, list) {
 		if (!(wq->flags & WQ_UNBOUND))
 			continue;
+
 		/* creating multiple pwqs breaks ordering guarantee */
-		if (wq->flags & __WQ_ORDERED)
-			continue;
+		if (!list_empty(&wq->pwqs)) {
+			if (wq->flags & __WQ_ORDERED_EXPLICIT)
+				continue;
+			wq->flags &= ~__WQ_ORDERED;
+		}
 
 		ctx = apply_wqattrs_prepare(wq, wq->unbound_attrs);
 		if (!ctx) {
-- 
GitLab


From 788621afda4101ca0fae48de424040cda78193fe Mon Sep 17 00:00:00 2001
From: Peter Zijlstra <peterz@infradead.org>
Date: Fri, 7 Aug 2020 20:50:19 +0200
Subject: [PATCH 197/298] sched,idle,rcu: Push rcu_idle deeper into the idle
 path

commit 1098582a0f6c4e8fd28da0a6305f9233d02c9c1d upstream.

Lots of things take locks, due to a wee bug, rcu_lockdep didn't notice
that the locking tracepoints were using RCU.

Push rcu_idle_{enter,exit}() as deep as possible into the idle paths,
this also resolves a lot of _rcuidle()/RCU_NONIDLE() usage.

Specifically, sched_clock_idle_wakeup_event() will use ktime which
will use seqlocks which will tickle lockdep, and
stop_critical_timings() uses lock.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Tested-by: Marco Elver <elver@google.com>
Link: https://lkml.kernel.org/r/20200821085348.310943801@infradead.org
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/cpuidle/cpuidle.c | 12 ++++++++----
 kernel/sched/idle.c       | 22 ++++++++--------------
 2 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index 2d182dc1b49e..01bde6dec13a 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -140,13 +140,14 @@ static void enter_s2idle_proper(struct cpuidle_driver *drv,
 	 * executing it contains RCU usage regarded as invalid in the idle
 	 * context, so tell RCU about that.
 	 */
-	RCU_NONIDLE(tick_freeze());
+	tick_freeze();
 	/*
 	 * The state used here cannot be a "coupled" one, because the "coupled"
 	 * cpuidle mechanism enables interrupts and doing that with timekeeping
 	 * suspended is generally unsafe.
 	 */
 	stop_critical_timings();
+	rcu_idle_enter();
 	drv->states[index].enter_s2idle(dev, drv, index);
 	if (WARN_ON_ONCE(!irqs_disabled()))
 		local_irq_disable();
@@ -155,7 +156,8 @@ static void enter_s2idle_proper(struct cpuidle_driver *drv,
 	 * first CPU executing it calls functions containing RCU read-side
 	 * critical sections, so tell RCU about that.
 	 */
-	RCU_NONIDLE(tick_unfreeze());
+	rcu_idle_exit();
+	tick_unfreeze();
 	start_critical_timings();
 
 	time_end = ns_to_ktime(local_clock());
@@ -224,16 +226,18 @@ int cpuidle_enter_state(struct cpuidle_device *dev, struct cpuidle_driver *drv,
 	/* Take note of the planned idle state. */
 	sched_idle_set_state(target_state);
 
-	trace_cpu_idle_rcuidle(index, dev->cpu);
+	trace_cpu_idle(index, dev->cpu);
 	time_start = ns_to_ktime(local_clock());
 
 	stop_critical_timings();
+	rcu_idle_enter();
 	entered_state = target_state->enter(dev, drv, index);
+	rcu_idle_exit();
 	start_critical_timings();
 
 	sched_clock_idle_wakeup_event();
 	time_end = ns_to_ktime(local_clock());
-	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, dev->cpu);
+	trace_cpu_idle(PWR_EVENT_EXIT, dev->cpu);
 
 	/* The cpu is no longer idle or about to enter idle. */
 	sched_idle_set_state(NULL);
diff --git a/kernel/sched/idle.c b/kernel/sched/idle.c
index 44a17366c8ec..4e3d149d64ad 100644
--- a/kernel/sched/idle.c
+++ b/kernel/sched/idle.c
@@ -53,17 +53,18 @@ __setup("hlt", cpu_idle_nopoll_setup);
 
 static noinline int __cpuidle cpu_idle_poll(void)
 {
+	trace_cpu_idle(0, smp_processor_id());
+	stop_critical_timings();
 	rcu_idle_enter();
-	trace_cpu_idle_rcuidle(0, smp_processor_id());
 	local_irq_enable();
-	stop_critical_timings();
 
 	while (!tif_need_resched() &&
-		(cpu_idle_force_poll || tick_check_broadcast_expired()))
+	       (cpu_idle_force_poll || tick_check_broadcast_expired()))
 		cpu_relax();
-	start_critical_timings();
-	trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
+
 	rcu_idle_exit();
+	start_critical_timings();
+	trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 
 	return 1;
 }
@@ -90,7 +91,9 @@ void __cpuidle default_idle_call(void)
 		local_irq_enable();
 	} else {
 		stop_critical_timings();
+		rcu_idle_enter();
 		arch_cpu_idle();
+		rcu_idle_exit();
 		start_critical_timings();
 	}
 }
@@ -148,7 +151,6 @@ static void cpuidle_idle_call(void)
 
 	if (cpuidle_not_available(drv, dev)) {
 		tick_nohz_idle_stop_tick();
-		rcu_idle_enter();
 
 		default_idle_call();
 		goto exit_idle;
@@ -166,19 +168,15 @@ static void cpuidle_idle_call(void)
 
 	if (idle_should_enter_s2idle() || dev->use_deepest_state) {
 		if (idle_should_enter_s2idle()) {
-			rcu_idle_enter();
 
 			entered_state = cpuidle_enter_s2idle(drv, dev);
 			if (entered_state > 0) {
 				local_irq_enable();
 				goto exit_idle;
 			}
-
-			rcu_idle_exit();
 		}
 
 		tick_nohz_idle_stop_tick();
-		rcu_idle_enter();
 
 		next_state = cpuidle_find_deepest_state(drv, dev);
 		call_cpuidle(drv, dev, next_state);
@@ -195,8 +193,6 @@ static void cpuidle_idle_call(void)
 		else
 			tick_nohz_idle_retain_tick();
 
-		rcu_idle_enter();
-
 		entered_state = call_cpuidle(drv, dev, next_state);
 		/*
 		 * Give the governor an opportunity to reflect on the outcome
@@ -212,8 +208,6 @@ static void cpuidle_idle_call(void)
 	 */
 	if (WARN_ON_ONCE(irqs_disabled()))
 		local_irq_enable();
-
-	rcu_idle_exit();
 }
 
 /*
-- 
GitLab


From 9022970a454b0eb1091693629437add7f5dbb8bd Mon Sep 17 00:00:00 2001
From: Amelie Delaunay <amelie.delaunay@foss.st.com>
Date: Wed, 4 Oct 2023 18:35:28 +0200
Subject: [PATCH 198/298] dmaengine: stm32-mdma: abort resume if no ongoing
 transfer

commit 81337b9a72dc58a5fa0ae8a042e8cb59f9bdec4a upstream.

chan->desc can be null, if transfer is terminated when resume is called,
leading to a NULL pointer when retrieving the hwdesc.
To avoid this case, check that chan->desc is not null and channel is
disabled (transfer previously paused or terminated).

Fixes: a4ffb13c8946 ("dmaengine: Add STM32 MDMA driver")
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20231004163531.2864160-1-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/dma/stm32-mdma.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c
index 3259c450544c..ad9be6ed47a3 100644
--- a/drivers/dma/stm32-mdma.c
+++ b/drivers/dma/stm32-mdma.c
@@ -1217,6 +1217,10 @@ static int stm32_mdma_resume(struct dma_chan *c)
 	unsigned long flags;
 	u32 status, reg;
 
+	/* Transfer can be terminated */
+	if (!chan->desc || (stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & STM32_MDMA_CCR_EN))
+		return -EPERM;
+
 	hwdesc = chan->desc->node[chan->curr_hwdesc].hwdesc;
 
 	spin_lock_irqsave(&chan->vchan.lock, flags);
-- 
GitLab


From 02db98cb303fedb5e21c093c2951ad70fa8f4ab3 Mon Sep 17 00:00:00 2001
From: Wesley Cheng <quic_wcheng@quicinc.com>
Date: Fri, 15 Sep 2023 17:31:05 +0300
Subject: [PATCH 199/298] usb: xhci: xhci-ring: Use sysdev for mapping bounce
 buffer

commit 41a43013d2366db5b88b42bbcd8e8f040b6ccf21 upstream.

As mentioned in:
  commit 474ed23a6257 ("xhci: align the last trb before link if it is
easily splittable.")

A bounce buffer is utilized for ensuring that transfers that span across
ring segments are aligned to the EP's max packet size.  However, the device
that is used to map the DMA buffer to is currently using the XHCI HCD,
which does not carry any DMA operations in certain configrations.
Migration to using the sysdev entry was introduced for DWC3 based
implementations where the IOMMU operations are present.

Replace the reference to the controller device to sysdev instead.  This
allows the bounce buffer to be properly mapped to any implementations that
have an IOMMU involved.

cc: stable@vger.kernel.org
Fixes: 4c39d4b949d3 ("usb: xhci: use bus->sysdev for DMA configuration")
Signed-off-by: Wesley Cheng <quic_wcheng@quicinc.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Link: https://lore.kernel.org/r/20230915143108.1532163-2-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/host/xhci-ring.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index aa4c5b43fb78..8723c7f1c24f 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -689,7 +689,7 @@ static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
 		struct xhci_ring *ring, struct xhci_td *td)
 {
-	struct device *dev = xhci_to_hcd(xhci)->self.controller;
+	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
 	struct xhci_segment *seg = td->bounce_seg;
 	struct urb *urb = td->urb;
 	size_t len;
@@ -3199,7 +3199,7 @@ static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
 			 u32 *trb_buff_len, struct xhci_segment *seg)
 {
-	struct device *dev = xhci_to_hcd(xhci)->self.controller;
+	struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
 	unsigned int unalign;
 	unsigned int max_pkt;
 	u32 new_buff_len;
-- 
GitLab


From bff8bc72c2c44fccee5fa48bea361ef27bcf86ce Mon Sep 17 00:00:00 2001
From: Javier Carrasco <javier.carrasco.cruz@gmail.com>
Date: Tue, 10 Oct 2023 00:26:14 +0200
Subject: [PATCH 200/298] net: usb: dm9601: fix uninitialized variable use in
 dm9601_mdio_read

commit 8f8abb863fa5a4cc18955c6a0e17af0ded3e4a76 upstream.

syzbot has found an uninit-value bug triggered by the dm9601 driver [1].

This error happens because the variable res is not updated if the call
to dm_read_shared_word returns an error. In this particular case -EPROTO
was returned and res stayed uninitialized.

This can be avoided by checking the return value of dm_read_shared_word
and propagating the error if the read operation failed.

[1] https://syzkaller.appspot.com/bug?extid=1f53a30781af65d2c955

Cc: stable@vger.kernel.org
Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
Reported-and-tested-by: syzbot+1f53a30781af65d2c955@syzkaller.appspotmail.com
Acked-by: Peter Korsgaard <peter@korsgaard.com>
Fixes: d0374f4f9c35cdfbee0 ("USB: Davicom DM9601 usbnet driver")
Link: https://lore.kernel.org/r/20231009-topic-dm9601_uninit_mdio_read-v2-1-f2fe39739b6c@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/net/usb/dm9601.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/net/usb/dm9601.c b/drivers/net/usb/dm9601.c
index 915ac75b55fc..5aad26600b03 100644
--- a/drivers/net/usb/dm9601.c
+++ b/drivers/net/usb/dm9601.c
@@ -221,13 +221,18 @@ static int dm9601_mdio_read(struct net_device *netdev, int phy_id, int loc)
 	struct usbnet *dev = netdev_priv(netdev);
 
 	__le16 res;
+	int err;
 
 	if (phy_id) {
 		netdev_dbg(dev->net, "Only internal phy supported\n");
 		return 0;
 	}
 
-	dm_read_shared_word(dev, 1, loc, &res);
+	err = dm_read_shared_word(dev, 1, loc, &res);
+	if (err < 0) {
+		netdev_err(dev->net, "MDIO read error: %d\n", err);
+		return err;
+	}
 
 	netdev_dbg(dev->net,
 		   "dm9601_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
-- 
GitLab


From 2966f373a3af5c5878bae54d4ce81d06557e624b Mon Sep 17 00:00:00 2001
From: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Date: Wed, 13 Sep 2023 00:52:15 +0000
Subject: [PATCH 201/298] usb: dwc3: Soft reset phy on probe for host

commit 8bea147dfdf823eaa8d3baeccc7aeb041b41944b upstream.

When there's phy initialization, we need to initiate a soft-reset
sequence. That's done through USBCMD.HCRST in the xHCI driver and its
initialization, However, the dwc3 driver may modify core configs before
the soft-reset. This may result in some connection instability. So,
ensure the phy is ready before the controller updates the GCTL.PRTCAPDIR
or other settings by issuing phy soft-reset.

Note that some host-mode configurations may not expose device registers
to initiate the controller soft-reset (via DCTL.CoreSftRst). So we reset
through GUSB3PIPECTL and GUSB2PHYCFG instead.

Cc: stable@vger.kernel.org
Fixes: e835c0a4e23c ("usb: dwc3: don't reset device side if dwc3 was configured as host-only")
Reported-by: Kenta Sato <tosainu.maple@gmail.com>
Closes: https://lore.kernel.org/linux-usb/ZPUciRLUcjDywMVS@debian.me/
Signed-off-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Tested-by: Kenta Sato <tosainu.maple@gmail.com>
Link: https://lore.kernel.org/r/70aea513215d273669152696cc02b20ddcdb6f1a.1694564261.git.Thinh.Nguyen@synopsys.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/dwc3/core.c | 39 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index d31cc8d75595..2f3bbf73656b 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -244,9 +244,46 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
 	 * XHCI driver will reset the host block. If dwc3 was configured for
 	 * host-only mode or current role is host, then we can return early.
 	 */
-	if (dwc->dr_mode == USB_DR_MODE_HOST || dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
+	if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 		return 0;
 
+	/*
+	 * If the dr_mode is host and the dwc->current_dr_role is not the
+	 * corresponding DWC3_GCTL_PRTCAP_HOST, then the dwc3_core_init_mode
+	 * isn't executed yet. Ensure the phy is ready before the controller
+	 * updates the GCTL.PRTCAPDIR or other settings by soft-resetting
+	 * the phy.
+	 *
+	 * Note: GUSB3PIPECTL[n] and GUSB2PHYCFG[n] are port settings where n
+	 * is port index. If this is a multiport host, then we need to reset
+	 * all active ports.
+	 */
+	if (dwc->dr_mode == USB_DR_MODE_HOST) {
+		u32 usb3_port;
+		u32 usb2_port;
+
+		usb3_port = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
+		usb3_port |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
+		dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);
+
+		usb2_port = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+		usb2_port |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
+		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);
+
+		/* Small delay for phy reset assertion */
+		usleep_range(1000, 2000);
+
+		usb3_port &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
+		dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);
+
+		usb2_port &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
+		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);
+
+		/* Wait for clock synchronization */
+		msleep(50);
+		return 0;
+	}
+
 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 	reg |= DWC3_DCTL_CSFTRST;
 	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
-- 
GitLab


From 04bafe15b7f21701e1af5372da6aa0b97c3a8a90 Mon Sep 17 00:00:00 2001
From: Xingxing Luo <xingxing.luo@unisoc.com>
Date: Tue, 19 Sep 2023 11:30:55 +0800
Subject: [PATCH 202/298] usb: musb: Get the musb_qh poniter after
 musb_giveback

commit 33d7e37232155aadebe4145dcc592f00dabd7a2b upstream.

When multiple threads are performing USB transmission, musb->lock will be
unlocked when musb_giveback is executed. At this time, qh may be released
in the dequeue process in other threads, resulting in a wild pointer, so
it needs to be here get qh again, and judge whether qh is NULL, and when
dequeue, you need to set qh to NULL.

Fixes: dbac5d07d13e ("usb: musb: host: don't start next rx urb if current one failed")
Cc: stable@vger.kernel.org
Signed-off-by: Xingxing Luo <xingxing.luo@unisoc.com>
Link: https://lore.kernel.org/r/20230919033055.14085-1-xingxing.luo@unisoc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/musb/musb_host.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index 68f18afa8b2c..b35b6cb24e8c 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -339,10 +339,16 @@ static void musb_advance_schedule(struct musb *musb, struct urb *urb,
 	musb_giveback(musb, urb, status);
 	qh->is_ready = ready;
 
+	/*
+	 * musb->lock had been unlocked in musb_giveback, so qh may
+	 * be freed, need to get it again
+	 */
+	qh = musb_ep_get_qh(hw_ep, is_in);
+
 	/* reclaim resources (and bandwidth) ASAP; deschedule it, and
 	 * invalidate qh as soon as list_empty(&hep->urb_list)
 	 */
-	if (list_empty(&qh->hep->urb_list)) {
+	if (qh && list_empty(&qh->hep->urb_list)) {
 		struct list_head	*head;
 		struct dma_controller	*dma = musb->dma_controller;
 
@@ -2424,6 +2430,7 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
 		 * and its URB list has emptied, recycle this qh.
 		 */
 		if (ready && list_empty(&qh->hep->urb_list)) {
+			musb_ep_set_qh(qh->hw_ep, is_in, NULL);
 			qh->hep->hcpriv = NULL;
 			list_del(&qh->ring);
 			kfree(qh);
-- 
GitLab


From c4e925cc7ff44556560aa58cbfa1abaaf7a35670 Mon Sep 17 00:00:00 2001
From: Xingxing Luo <xingxing.luo@unisoc.com>
Date: Fri, 22 Sep 2023 15:59:29 +0800
Subject: [PATCH 203/298] usb: musb: Modify the "HWVers" register address

commit 6658a62e1ddf726483cb2d8bf45ea3f9bd533074 upstream.

musb HWVers rgister address is not 0x69, if we operate the
wrong address 0x69, it will cause a kernel crash, because
there is no register corresponding to this address in the
additional control register of musb. In fact, HWVers has
been defined in musb_register.h, and the name is
"MUSB_HWVERS", so We need to use this macro instead of 0x69.

Fixes: c2365ce5d5a0 ("usb: musb: replace hard coded registers with defines")
Cc: stable@vger.kernel.org
Signed-off-by: Xingxing Luo <xingxing.luo@unisoc.com>
Link: https://lore.kernel.org/r/20230922075929.31074-1-xingxing.luo@unisoc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/musb/musb_debugfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/usb/musb/musb_debugfs.c b/drivers/usb/musb/musb_debugfs.c
index 0c6204add616..1efd5ce48f89 100644
--- a/drivers/usb/musb/musb_debugfs.c
+++ b/drivers/usb/musb/musb_debugfs.c
@@ -39,7 +39,7 @@ static const struct musb_register_map musb_regmap[] = {
 	{ "IntrUsbE",	MUSB_INTRUSBE,	8 },
 	{ "DevCtl",	MUSB_DEVCTL,	8 },
 	{ "VControl",	0x68,		32 },
-	{ "HWVers",	0x69,		16 },
+	{ "HWVers",	MUSB_HWVERS,	16 },
 	{ "LinkInfo",	MUSB_LINKINFO,	8 },
 	{ "VPLen",	MUSB_VPLEN,	8 },
 	{ "HS_EOF1",	MUSB_HS_EOF1,	8 },
-- 
GitLab


From 3f234895e313a8ea45b3e5668c311fbf4a7999a8 Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.com>
Date: Fri, 11 Aug 2023 16:58:29 +0100
Subject: [PATCH 204/298] iio: pressure: bmp280: Fix NULL pointer exception

commit 85dfb43bf69281adb1f345dfd9a39faf2e5a718d upstream.

The bmp085 EOC IRQ support is optional, but the driver's common probe
function queries the IRQ properties whether or not it exists, which
can trigger a NULL pointer exception. Avoid any exception by making
the query conditional on the possession of a valid IRQ.

Fixes: aae953949651 ("iio: pressure: bmp280: add support for BMP085 EOC interrupt")
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20230811155829.51208-1-phil@raspberrypi.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/iio/pressure/bmp280-core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/pressure/bmp280-core.c b/drivers/iio/pressure/bmp280-core.c
index 074f6f865008..5efc50d93d1c 100644
--- a/drivers/iio/pressure/bmp280-core.c
+++ b/drivers/iio/pressure/bmp280-core.c
@@ -1110,7 +1110,7 @@ int bmp280_common_probe(struct device *dev,
 	 * however as it happens, the BMP085 shares the chip ID of BMP180
 	 * so we look for an IRQ if we have that.
 	 */
-	if (irq > 0 || (chip_id  == BMP180_CHIP_ID)) {
+	if (irq > 0 && (chip_id  == BMP180_CHIP_ID)) {
 		ret = bmp085_fetch_eoc_irq(dev, name, irq, data);
 		if (ret)
 			goto out_disable_vdda;
-- 
GitLab


From adcece2b95b63a0c118daa57acc1413b7ad75324 Mon Sep 17 00:00:00 2001
From: Alexander Zangerl <az@breathe-safe.com>
Date: Wed, 20 Sep 2023 10:01:10 +1000
Subject: [PATCH 205/298] iio: pressure: ms5611: ms5611_prom_is_valid false
 negative bug

commit fd39d9668f2ce9f4b05ad55e8c8d80c098073e0b upstream.

The ms5611 driver falsely rejects lots of MS5607-02BA03-50 chips
with "PROM integrity check failed" because it doesn't accept a prom crc
value of zero as legitimate.

According to the datasheet for this chip (and the manufacturer's
application note about the PROM CRC), none of the possible values for the
CRC are excluded - but the current code in ms5611_prom_is_valid() ends with

return crc_orig != 0x0000 && crc == crc_orig

Discussed with the driver author (Tomasz Duszynski) and he indicated that
at that time (2015) he was dealing with some faulty chip samples which
returned blank data under some circumstances and/or followed example code
which indicated CRC zero being bad.

As far as I can tell this exception should not be applied anymore; We've
got a few hundred custom boards here with this chip where large numbers
of the prom have a legitimate CRC value 0, and do work fine, but which the
current driver code wrongly rejects.

Signed-off-by: Alexander Zangerl <az@breathe-safe.com>
Fixes: c0644160a8b5 ("iio: pressure: add support for MS5611 pressure and temperature sensor")
Link: https://lore.kernel.org/r/2535-1695168070.831792@Ze3y.dhYT.s3fx
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/iio/pressure/ms5611_core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/pressure/ms5611_core.c b/drivers/iio/pressure/ms5611_core.c
index 5c7a734ede54..9980c6f3335e 100644
--- a/drivers/iio/pressure/ms5611_core.c
+++ b/drivers/iio/pressure/ms5611_core.c
@@ -79,7 +79,7 @@ static bool ms5611_prom_is_valid(u16 *prom, size_t len)
 
 	crc = (crc >> 12) & 0x000F;
 
-	return crc_orig != 0x0000 && crc == crc_orig;
+	return crc == crc_orig;
 }
 
 static int ms5611_read_prom(struct iio_dev *indio_dev)
-- 
GitLab


From c691fe37c3e9d5670a2552f990b38a4582e47aee Mon Sep 17 00:00:00 2001
From: Jorge Sanjuan Garcia <jorge.sanjuangarcia@duagon.com>
Date: Wed, 6 Sep 2023 11:49:26 +0000
Subject: [PATCH 206/298] mcb: remove is_added flag from mcb_device struct

commit 0f28ada1fbf0054557cddcdb93ad17f767105208 upstream.

When calling mcb_bus_add_devices(), both mcb devices and the mcb
bus will attempt to attach a device to a driver because they share
the same bus_type. This causes an issue when trying to cast the
container of the device to mcb_device struct using to_mcb_device(),
leading to a wrong cast when the mcb_bus is added. A crash occurs
when freing the ida resources as the bus numbering of mcb_bus gets
confused with the is_added flag on the mcb_device struct.

The only reason for this cast was to keep an is_added flag on the
mcb_device struct that does not seem necessary. The function
device_attach() handles already bound devices and the mcb subsystem
does nothing special with this is_added flag so remove it completely.

Fixes: 18d288198099 ("mcb: Correctly initialize the bus's device")
Cc: stable <stable@kernel.org>
Signed-off-by: Jorge Sanjuan Garcia <jorge.sanjuangarcia@duagon.com>
Co-developed-by: Jose Javier Rodriguez Barbarin <JoseJavier.Rodriguez@duagon.com>
Signed-off-by: Jose Javier Rodriguez Barbarin <JoseJavier.Rodriguez@duagon.com>
Link: https://lore.kernel.org/r/20230906114901.63174-2-JoseJavier.Rodriguez@duagon.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/mcb/mcb-core.c  | 10 +++-------
 drivers/mcb/mcb-parse.c |  2 --
 include/linux/mcb.h     |  1 -
 3 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/mcb/mcb-core.c b/drivers/mcb/mcb-core.c
index 7fd32b0183dc..6e7e91387f3c 100644
--- a/drivers/mcb/mcb-core.c
+++ b/drivers/mcb/mcb-core.c
@@ -392,17 +392,13 @@ EXPORT_SYMBOL_GPL(mcb_free_dev);
 
 static int __mcb_bus_add_devices(struct device *dev, void *data)
 {
-	struct mcb_device *mdev = to_mcb_device(dev);
 	int retval;
 
-	if (mdev->is_added)
-		return 0;
-
 	retval = device_attach(dev);
-	if (retval < 0)
+	if (retval < 0) {
 		dev_err(dev, "Error adding device (%d)\n", retval);
-
-	mdev->is_added = true;
+		return retval;
+	}
 
 	return 0;
 }
diff --git a/drivers/mcb/mcb-parse.c b/drivers/mcb/mcb-parse.c
index 3636349648b4..08a85e43ef88 100644
--- a/drivers/mcb/mcb-parse.c
+++ b/drivers/mcb/mcb-parse.c
@@ -98,8 +98,6 @@ static int chameleon_parse_gdd(struct mcb_bus *bus,
 	mdev->mem.end = mdev->mem.start + size - 1;
 	mdev->mem.flags = IORESOURCE_MEM;
 
-	mdev->is_added = false;
-
 	ret = mcb_device_register(bus, mdev);
 	if (ret < 0)
 		goto err;
diff --git a/include/linux/mcb.h b/include/linux/mcb.h
index b1a0ad9d23b3..8052e5f20630 100644
--- a/include/linux/mcb.h
+++ b/include/linux/mcb.h
@@ -66,7 +66,6 @@ static inline struct mcb_bus *to_mcb_bus(struct device *dev)
 struct mcb_device {
 	struct device dev;
 	struct mcb_bus *bus;
-	bool is_added;
 	struct mcb_driver *driver;
 	u16 id;
 	int inst;
-- 
GitLab


From 2d0507cdd6a3f4f7eac776ffb8b9e7f79398dc94 Mon Sep 17 00:00:00 2001
From: Xiubo Li <xiubli@redhat.com>
Date: Wed, 6 Sep 2023 14:22:07 +0800
Subject: [PATCH 207/298] ceph: fix incorrect revoked caps assert in
 ceph_fill_file_size()

commit 15c0a870dc44ed14e01efbdd319d232234ee639f upstream.

When truncating the inode the MDS will acquire the xlock for the
ifile Locker, which will revoke the 'Frwsxl' caps from the clients.
But when the client just releases and flushes the 'Fw' caps to MDS,
for exmaple, and once the MDS receives the caps flushing msg it
just thought the revocation has finished. Then the MDS will continue
truncating the inode and then issued the truncate notification to
all the clients. While just before the clients receives the cap
flushing ack they receive the truncation notification, the clients
will detecte that the 'issued | dirty' is still holding the 'Fw'
caps.

Cc: stable@vger.kernel.org
Link: https://tracker.ceph.com/issues/56693
Fixes: b0d7c2231015 ("ceph: introduce i_truncate_mutex")
Signed-off-by: Xiubo Li <xiubli@redhat.com>
Reviewed-by: Milind Changire <mchangir@redhat.com>
Signed-off-by: Ilya Dryomov <idryomov@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 fs/ceph/inode.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/fs/ceph/inode.c b/fs/ceph/inode.c
index 5f041fede7aa..d6f181e3c1ac 100644
--- a/fs/ceph/inode.c
+++ b/fs/ceph/inode.c
@@ -631,9 +631,7 @@ int ceph_fill_file_size(struct inode *inode, int issued,
 			ci->i_truncate_seq = truncate_seq;
 
 			/* the MDS should have revoked these caps */
-			WARN_ON_ONCE(issued & (CEPH_CAP_FILE_EXCL |
-					       CEPH_CAP_FILE_RD |
-					       CEPH_CAP_FILE_WR |
+			WARN_ON_ONCE(issued & (CEPH_CAP_FILE_RD |
 					       CEPH_CAP_FILE_LAZYIO));
 			/*
 			 * If we hold relevant caps, or in the case where we're
-- 
GitLab


From 67cace72606baf1758fd60feb358f4c6be92e1cc Mon Sep 17 00:00:00 2001
From: Javier Carrasco <javier.carrasco.cruz@gmail.com>
Date: Fri, 13 Oct 2023 20:11:33 -0700
Subject: [PATCH 208/298] Input: powermate - fix use-after-free in
 powermate_config_complete

commit 5c15c60e7be615f05a45cd905093a54b11f461bc upstream.

syzbot has found a use-after-free bug [1] in the powermate driver. This
happens when the device is disconnected, which leads to a memory free from
the powermate_device struct.  When an asynchronous control message
completes after the kfree and its callback is invoked, the lock does not
exist anymore and hence the bug.

Use usb_kill_urb() on pm->config to cancel any in-progress requests upon
device disconnection.

[1] https://syzkaller.appspot.com/bug?extid=0434ac83f907a1dbdd1e

Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
Reported-by: syzbot+0434ac83f907a1dbdd1e@syzkaller.appspotmail.com
Link: https://lore.kernel.org/r/20230916-topic-powermate_use_after_free-v3-1-64412b81a7a2@gmail.com
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/input/misc/powermate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/input/misc/powermate.c b/drivers/input/misc/powermate.c
index e8de3aaf9f63..14f48e10f589 100644
--- a/drivers/input/misc/powermate.c
+++ b/drivers/input/misc/powermate.c
@@ -424,6 +424,7 @@ static void powermate_disconnect(struct usb_interface *intf)
 		pm->requires_update = 0;
 		usb_kill_urb(pm->irq);
 		input_unregister_device(pm->input);
+		usb_kill_urb(pm->config);
 		usb_free_urb(pm->irq);
 		usb_free_urb(pm->config);
 		powermate_free_buffers(interface_to_usbdev(intf), pm);
-- 
GitLab


From dd1a5db2fcfca6484b20d8a579897ba10acb3709 Mon Sep 17 00:00:00 2001
From: Jeffery Miller <jefferymiller@google.com>
Date: Fri, 13 Oct 2023 15:23:49 -0700
Subject: [PATCH 209/298] Input: psmouse - fix fast_reconnect function for PS/2
 mode

commit e2cb5cc822b6c9ee72c56ce1d81671b22c05406a upstream.

When the SMBus connection is attempted psmouse_smbus_init() sets
the fast_reconnect pointer to psmouse_smbus_reconnecti(). If SMBus
initialization fails, elantech_setup_ps2() and synaptics_init_ps2() will
fallback to PS/2 mode, replacing the psmouse private data. This can cause
issues on resume, since psmouse_smbus_reconnect() expects to find an
instance of struct psmouse_smbus_dev in psmouse->private.

The issue was uncovered when in 92e24e0e57f7 ("Input: psmouse - add
delay when deactivating for SMBus mode") psmouse_smbus_reconnect()
started attempting to use more of the data structure. The commit was
since reverted, not because it was at fault, but because there was found
a better way of doing what it was attempting to do.

Fix the problem by resetting the fast_reconnect pointer in psmouse
structure in elantech_setup_ps2() and synaptics_init_ps2() when the PS/2
mode is used.

Reported-by: Thorsten Leemhuis <linux@leemhuis.info>
Tested-by: Thorsten Leemhuis <linux@leemhuis.info>
Signed-off-by: Jeffery Miller <jefferymiller@google.com>
Fixes: bf232e460a35 ("Input: psmouse-smbus - allow to control psmouse_deactivate")
Link: https://lore.kernel.org/r/20231005002249.554877-1-jefferymiller@google.com
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/input/mouse/elantech.c  | 1 +
 drivers/input/mouse/synaptics.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/input/mouse/elantech.c b/drivers/input/mouse/elantech.c
index e78db2dd0348..6759cab82a72 100644
--- a/drivers/input/mouse/elantech.c
+++ b/drivers/input/mouse/elantech.c
@@ -1996,6 +1996,7 @@ static int elantech_setup_ps2(struct psmouse *psmouse,
 	psmouse->protocol_handler = elantech_process_byte;
 	psmouse->disconnect = elantech_disconnect;
 	psmouse->reconnect = elantech_reconnect;
+	psmouse->fast_reconnect = NULL;
 	psmouse->pktsize = info->hw_version > 1 ? 6 : 4;
 
 	return 0;
diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c
index c6d393114502..794a7f17d024 100644
--- a/drivers/input/mouse/synaptics.c
+++ b/drivers/input/mouse/synaptics.c
@@ -1620,6 +1620,7 @@ static int synaptics_init_ps2(struct psmouse *psmouse,
 	psmouse->set_rate = synaptics_set_rate;
 	psmouse->disconnect = synaptics_disconnect;
 	psmouse->reconnect = synaptics_reconnect;
+	psmouse->fast_reconnect = NULL;
 	psmouse->cleanup = synaptics_reset;
 	/* Synaptics can usually stay in sync without extra help */
 	psmouse->resync_time = 0;
-- 
GitLab


From e09dd4e76ddf9b081f988396b05499f022a85d41 Mon Sep 17 00:00:00 2001
From: Matthias Berndt <matthias_berndt@gmx.de>
Date: Fri, 13 Oct 2023 15:04:36 -0700
Subject: [PATCH 210/298] Input: xpad - add PXN V900 support

commit a65cd7ef5a864bdbbe037267c327786b7759d4c6 upstream.

Add VID and PID to the xpad_device table to allow driver to use the PXN
V900 steering wheel, which is XTYPE_XBOX360 compatible in xinput mode.

Signed-off-by: Matthias Berndt <matthias_berndt@gmx.de>
Link: https://lore.kernel.org/r/4932699.31r3eYUQgx@fedora
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/input/joystick/xpad.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c
index 1537ce627238..4591f60dd6e2 100644
--- a/drivers/input/joystick/xpad.c
+++ b/drivers/input/joystick/xpad.c
@@ -266,6 +266,7 @@ static const struct xpad_device {
 	{ 0x1038, 0x1430, "SteelSeries Stratus Duo", 0, XTYPE_XBOX360 },
 	{ 0x1038, 0x1431, "SteelSeries Stratus Duo", 0, XTYPE_XBOX360 },
 	{ 0x11c9, 0x55f0, "Nacon GC-100XF", 0, XTYPE_XBOX360 },
+	{ 0x11ff, 0x0511, "PXN V900", 0, XTYPE_XBOX360 },
 	{ 0x1209, 0x2882, "Ardwiino Controller", 0, XTYPE_XBOX360 },
 	{ 0x12ab, 0x0004, "Honey Bee Xbox360 dancepad", MAP_DPAD_TO_BUTTONS, XTYPE_XBOX360 },
 	{ 0x12ab, 0x0301, "PDP AFTERGLOW AX.1", 0, XTYPE_XBOX360 },
@@ -460,6 +461,7 @@ static const struct usb_device_id xpad_table[] = {
 	XPAD_XBOXONE_VENDOR(0x0f0d),		/* Hori Controllers */
 	XPAD_XBOX360_VENDOR(0x1038),		/* SteelSeries Controllers */
 	XPAD_XBOX360_VENDOR(0x11c9),		/* Nacon GC100XF */
+	XPAD_XBOX360_VENDOR(0x11ff),		/* PXN V900 */
 	XPAD_XBOX360_VENDOR(0x1209),		/* Ardwiino Controllers */
 	XPAD_XBOX360_VENDOR(0x12ab),		/* X-Box 360 dance pads */
 	XPAD_XBOX360_VENDOR(0x1430),		/* RedOctane X-Box 360 controllers */
-- 
GitLab


From 987fb4353c3bcfdc80e960419eee70e824cdde2c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michal=20Koutn=C3=BD?= <mkoutny@suse.com>
Date: Mon, 9 Oct 2023 15:58:11 +0200
Subject: [PATCH 211/298] cgroup: Remove duplicates in cgroup v1 tasks file
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

commit 1ca0b605150501b7dc59f3016271da4eb3e96fce upstream.

One PID may appear multiple times in a preloaded pidlist.
(Possibly due to PID recycling but we have reports of the same
task_struct appearing with different PIDs, thus possibly involving
transfer of PID via de_thread().)

Because v1 seq_file iterator uses PIDs as position, it leads to
a message:
> seq_file: buggy .next function kernfs_seq_next did not update position index

Conservative and quick fix consists of removing duplicates from `tasks`
file (as opposed to removing pidlists altogether). It doesn't affect
correctness (it's sufficient to show a PID once), performance impact
would be hidden by unconditional sorting of the pidlist already in place
(asymptotically).

Link: https://lore.kernel.org/r/20230823174804.23632-1-mkoutny@suse.com/
Suggested-by: Firo Yang <firo.yang@suse.com>
Signed-off-by: Michal Koutný <mkoutny@suse.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 kernel/cgroup/cgroup-v1.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/kernel/cgroup/cgroup-v1.c b/kernel/cgroup/cgroup-v1.c
index c0ebb70808b6..55a61deb3d04 100644
--- a/kernel/cgroup/cgroup-v1.c
+++ b/kernel/cgroup/cgroup-v1.c
@@ -395,10 +395,9 @@ static int pidlist_array_load(struct cgroup *cgrp, enum cgroup_filetype type,
 	}
 	css_task_iter_end(&it);
 	length = n;
-	/* now sort & (if procs) strip out duplicates */
+	/* now sort & strip out duplicates (tgids or recycled thread PIDs) */
 	sort(array, length, sizeof(pid_t), cmppid, NULL);
-	if (type == CGROUP_FILE_PROCS)
-		length = pidlist_uniq(array, length);
+	length = pidlist_uniq(array, length);
 
 	l = cgroup_pidlist_find_create(cgrp, type);
 	if (!l) {
-- 
GitLab


From 0a33a61e25867a2b7e171d9b1af9984fad6fcf69 Mon Sep 17 00:00:00 2001
From: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Date: Wed, 20 Sep 2023 11:09:10 -0700
Subject: [PATCH 212/298] pinctrl: avoid unsafe code pattern in find_pinctrl()

commit c153a4edff6ab01370fcac8e46f9c89cca1060c2 upstream.

The code in find_pinctrl() takes a mutex and traverses a list of pinctrl
structures. Later the caller bumps up reference count on the found
structure. Such pattern is not safe as pinctrl that was found may get
deleted before the caller gets around to increasing the reference count.

Fix this by taking the reference count in find_pinctrl(), while it still
holds the mutex.

Cc: stable@vger.kernel.org
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Link: https://lore.kernel.org/r/ZQs1RgTKg6VJqmPs@google.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/pinctrl/core.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index a8148460f99f..597a8546fc4b 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -1001,17 +1001,20 @@ static int add_setting(struct pinctrl *p, struct pinctrl_dev *pctldev,
 
 static struct pinctrl *find_pinctrl(struct device *dev)
 {
-	struct pinctrl *p;
+	struct pinctrl *entry, *p = NULL;
 
 	mutex_lock(&pinctrl_list_mutex);
-	list_for_each_entry(p, &pinctrl_list, node)
-		if (p->dev == dev) {
-			mutex_unlock(&pinctrl_list_mutex);
-			return p;
+
+	list_for_each_entry(entry, &pinctrl_list, node) {
+		if (entry->dev == dev) {
+			p = entry;
+			kref_get(&p->users);
+			break;
 		}
+	}
 
 	mutex_unlock(&pinctrl_list_mutex);
-	return NULL;
+	return p;
 }
 
 static void pinctrl_free(struct pinctrl *p, bool inlist);
@@ -1120,7 +1123,6 @@ struct pinctrl *pinctrl_get(struct device *dev)
 	p = find_pinctrl(dev);
 	if (p) {
 		dev_dbg(dev, "obtain a copy of previously claimed pinctrl\n");
-		kref_get(&p->users);
 		return p;
 	}
 
-- 
GitLab


From 05868a16aab502d48a05a9528f23002fbf830335 Mon Sep 17 00:00:00 2001
From: "Borislav Petkov (AMD)" <bp@alien8.de>
Date: Sat, 7 Oct 2023 12:57:02 +0200
Subject: [PATCH 213/298] x86/cpu: Fix AMD erratum #1485 on Zen4-based CPUs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

commit f454b18e07f518bcd0c05af17a2239138bff52de upstream.

Fix erratum #1485 on Zen4 parts where running with STIBP disabled can
cause an #UD exception. The performance impact of the fix is negligible.

Reported-by: René Rebe <rene@exactcode.de>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Tested-by: René Rebe <rene@exactcode.de>
Cc: <stable@kernel.org>
Link: https://lore.kernel.org/r/D99589F4-BC5D-430B-87B2-72C20370CF57@exactcode.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 arch/x86/include/asm/msr-index.h | 4 ++++
 arch/x86/kernel/cpu/amd.c        | 8 ++++++++
 2 files changed, 12 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index efedd16231ff..2ee7b3e0dcc1 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -446,6 +446,10 @@
 
 #define MSR_AMD64_VIRT_SPEC_CTRL	0xc001011f
 
+/* Zen4 */
+#define MSR_ZEN4_BP_CFG			0xc001102e
+#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
+
 /* Fam 17h MSRs */
 #define MSR_F17H_IRPERF			0xc00000e9
 
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 69eb6a804d1d..dc41d4d7836e 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -72,6 +72,10 @@ static const int amd_zenbleed[] =
 			   AMD_MODEL_RANGE(0x17, 0x90, 0x0, 0x91, 0xf),
 			   AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
 
+static const int amd_erratum_1485[] =
+	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
+			   AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));
+
 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
 {
 	int osvw_id = *erratum++;
@@ -1122,6 +1126,10 @@ static void init_amd(struct cpuinfo_x86 *c)
 	check_null_seg_clears_base(c);
 
 	zenbleed_check(c);
+
+	if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
+	     cpu_has_amd_erratum(c, amd_erratum_1485))
+		msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
 }
 
 #ifdef CONFIG_X86_32
-- 
GitLab


From b3c4460e3c50cb16117ac48a0ce56adb75fa6720 Mon Sep 17 00:00:00 2001
From: Piyush Mehta <piyush.mehta@amd.com>
Date: Fri, 29 Sep 2023 17:45:14 +0530
Subject: [PATCH 214/298] usb: gadget: udc-xilinx: replace memcpy with
 memcpy_toio

commit 3061b6491f491197a35e14e49f805d661b02acd4 upstream.

For ARM processor, unaligned access to device memory is not allowed.
Method memcpy does not take care of alignment.

USB detection failure with the unalingned address of memory, with
below kernel crash. To fix the unalingned address kernel panic,
replace memcpy with memcpy_toio method.

Kernel crash:
Unable to handle kernel paging request at virtual address ffff80000c05008a
Mem abort info:
  ESR = 0x96000061
  EC = 0x25: DABT (current EL), IL = 32 bits
  SET = 0, FnV = 0
  EA = 0, S1PTW = 0
  FSC = 0x21: alignment fault
Data abort info:
  ISV = 0, ISS = 0x00000061
  CM = 0, WnR = 1
swapper pgtable: 4k pages, 48-bit VAs, pgdp=000000000143b000
[ffff80000c05008a] pgd=100000087ffff003, p4d=100000087ffff003,
pud=100000087fffe003, pmd=1000000800bcc003, pte=00680000a0010713
Internal error: Oops: 96000061 [#1] SMP
Modules linked in:
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.15.19-xilinx-v2022.1 #1
Hardware name: ZynqMP ZCU102 Rev1.0 (DT)
pstate: 200000c5 (nzCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
pc : __memcpy+0x30/0x260
lr : __xudc_ep0_queue+0xf0/0x110
sp : ffff800008003d00
x29: ffff800008003d00 x28: ffff800009474e80 x27: 00000000000000a0
x26: 0000000000000100 x25: 0000000000000012 x24: ffff000800bc8080
x23: 0000000000000001 x22: 0000000000000012 x21: ffff000800bc8080
x20: 0000000000000012 x19: ffff000800bc8080 x18: 0000000000000000
x17: ffff800876482000 x16: ffff800008004000 x15: 0000000000004000
x14: 00001f09785d0400 x13: 0103020101005567 x12: 0781400000000200
x11: 00000000c5672a10 x10: 00000000000008d0 x9 : ffff800009463cf0
x8 : ffff8000094757b0 x7 : 0201010055670781 x6 : 4000000002000112
x5 : ffff80000c05009a x4 : ffff000800a15012 x3 : ffff00080362ad80
x2 : 0000000000000012 x1 : ffff000800a15000 x0 : ffff80000c050088
Call trace:
 __memcpy+0x30/0x260
 xudc_ep0_queue+0x3c/0x60
 usb_ep_queue+0x38/0x44
 composite_ep0_queue.constprop.0+0x2c/0xc0
 composite_setup+0x8d0/0x185c
 configfs_composite_setup+0x74/0xb0
 xudc_irq+0x570/0xa40
 __handle_irq_event_percpu+0x58/0x170
 handle_irq_event+0x60/0x120
 handle_fasteoi_irq+0xc0/0x220
 handle_domain_irq+0x60/0x90
 gic_handle_irq+0x74/0xa0
 call_on_irq_stack+0x2c/0x60
 do_interrupt_handler+0x54/0x60
 el1_interrupt+0x30/0x50
 el1h_64_irq_handler+0x18/0x24
 el1h_64_irq+0x78/0x7c
 arch_cpu_idle+0x18/0x2c
 do_idle+0xdc/0x15c
 cpu_startup_entry+0x28/0x60
 rest_init+0xc8/0xe0
 arch_call_rest_init+0x10/0x1c
 start_kernel+0x694/0x6d4
 __primary_switched+0xa4/0xac

Fixes: 1f7c51660034 ("usb: gadget: Add xilinx usb2 device support")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/all/202209020044.CX2PfZzM-lkp@intel.com/
Cc: stable@vger.kernel.org
Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Link: https://lore.kernel.org/r/20230929121514.13475-1-piyush.mehta@amd.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/gadget/udc/udc-xilinx.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/usb/gadget/udc/udc-xilinx.c b/drivers/usb/gadget/udc/udc-xilinx.c
index 72f1bc6a680e..5b73a2aecf7a 100644
--- a/drivers/usb/gadget/udc/udc-xilinx.c
+++ b/drivers/usb/gadget/udc/udc-xilinx.c
@@ -496,11 +496,13 @@ static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req,
 		/* Get the Buffer address and copy the transmit data.*/
 		eprambase = (u32 __force *)(udc->addr + ep->rambase);
 		if (ep->is_in) {
-			memcpy(eprambase, bufferptr, bytestosend);
+			memcpy_toio((void __iomem *)eprambase, bufferptr,
+				    bytestosend);
 			udc->write_fn(udc->addr, ep->offset +
 				      XUSB_EP_BUF0COUNT_OFFSET, bufferlen);
 		} else {
-			memcpy(bufferptr, eprambase, bytestosend);
+			memcpy_toio((void __iomem *)bufferptr, eprambase,
+				    bytestosend);
 		}
 		/*
 		 * Enable the buffer for transmission.
@@ -514,11 +516,13 @@ static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req,
 		eprambase = (u32 __force *)(udc->addr + ep->rambase +
 			     ep->ep_usb.maxpacket);
 		if (ep->is_in) {
-			memcpy(eprambase, bufferptr, bytestosend);
+			memcpy_toio((void __iomem *)eprambase, bufferptr,
+				    bytestosend);
 			udc->write_fn(udc->addr, ep->offset +
 				      XUSB_EP_BUF1COUNT_OFFSET, bufferlen);
 		} else {
-			memcpy(bufferptr, eprambase, bytestosend);
+			memcpy_toio((void __iomem *)bufferptr, eprambase,
+				    bytestosend);
 		}
 		/*
 		 * Enable the buffer for transmission.
@@ -1020,7 +1024,7 @@ static int __xudc_ep0_queue(struct xusb_ep *ep0, struct xusb_req *req)
 			   udc->addr);
 		length = req->usb_req.actual = min_t(u32, length,
 						     EP0_MAX_PACKET);
-		memcpy(corebuf, req->usb_req.buf, length);
+		memcpy_toio((void __iomem *)corebuf, req->usb_req.buf, length);
 		udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, length);
 		udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
 	} else {
@@ -1746,7 +1750,7 @@ static void xudc_handle_setup(struct xusb_udc *udc)
 
 	/* Load up the chapter 9 command buffer.*/
 	ep0rambase = (u32 __force *) (udc->addr + XUSB_SETUP_PKT_ADDR_OFFSET);
-	memcpy(&setup, ep0rambase, 8);
+	memcpy_toio((void __iomem *)&setup, ep0rambase, 8);
 
 	udc->setup = setup;
 	udc->setup.wValue = cpu_to_le16(setup.wValue);
@@ -1833,7 +1837,7 @@ static void xudc_ep0_out(struct xusb_udc *udc)
 			     (ep0->rambase << 2));
 		buffer = req->usb_req.buf + req->usb_req.actual;
 		req->usb_req.actual = req->usb_req.actual + bytes_to_rx;
-		memcpy(buffer, ep0rambase, bytes_to_rx);
+		memcpy_toio((void __iomem *)buffer, ep0rambase, bytes_to_rx);
 
 		if (req->usb_req.length == req->usb_req.actual) {
 			/* Data transfer completed get ready for Status stage */
@@ -1909,7 +1913,7 @@ static void xudc_ep0_in(struct xusb_udc *udc)
 				     (ep0->rambase << 2));
 			buffer = req->usb_req.buf + req->usb_req.actual;
 			req->usb_req.actual = req->usb_req.actual + length;
-			memcpy(ep0rambase, buffer, length);
+			memcpy_toio((void __iomem *)ep0rambase, buffer, length);
 		}
 		udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, count);
 		udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
-- 
GitLab


From ff3ba016263ee93a1c6209bf5ab1599de7ab1512 Mon Sep 17 00:00:00 2001
From: Krishna Kurapati <quic_kriskura@quicinc.com>
Date: Wed, 27 Sep 2023 16:28:58 +0530
Subject: [PATCH 215/298] usb: gadget: ncm: Handle decoding of multiple NTB's
 in unwrap call
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

commit 427694cfaafa565a3db5c5ea71df6bc095dca92f upstream.

When NCM is used with hosts like Windows PC, it is observed that there are
multiple NTB's contained in one usb request giveback. Since the driver
unwraps the obtained request data assuming only one NTB is present, we
loose the subsequent NTB's present resulting in data loss.

Fix this by checking the parsed block length with the obtained data
length in usb request and continue parsing after the last byte of current
NTB.

Cc: stable@vger.kernel.org
Fixes: 9f6ce4240a2b ("usb: gadget: f_ncm.c added")
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Maciej Żenczykowski <maze@google.com>
Link: https://lore.kernel.org/r/20230927105858.12950-1-quic_kriskura@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/gadget/function/f_ncm.c | 26 +++++++++++++++++++-------
 1 file changed, 19 insertions(+), 7 deletions(-)

diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c
index 5558ea5ac77a..8d23a870b7b7 100644
--- a/drivers/usb/gadget/function/f_ncm.c
+++ b/drivers/usb/gadget/function/f_ncm.c
@@ -1180,7 +1180,8 @@ static int ncm_unwrap_ntb(struct gether *port,
 			  struct sk_buff_head *list)
 {
 	struct f_ncm	*ncm = func_to_ncm(&port->func);
-	__le16		*tmp = (void *) skb->data;
+	unsigned char	*ntb_ptr = skb->data;
+	__le16		*tmp;
 	unsigned	index, index2;
 	int		ndp_index;
 	unsigned	dg_len, dg_len2;
@@ -1193,6 +1194,10 @@ static int ncm_unwrap_ntb(struct gether *port,
 	const struct ndp_parser_opts *opts = ncm->parser_opts;
 	unsigned	crc_len = ncm->is_crc ? sizeof(uint32_t) : 0;
 	int		dgram_counter;
+	int		to_process = skb->len;
+
+parse_ntb:
+	tmp = (__le16 *)ntb_ptr;
 
 	/* dwSignature */
 	if (get_unaligned_le32(tmp) != opts->nth_sign) {
@@ -1239,7 +1244,7 @@ static int ncm_unwrap_ntb(struct gether *port,
 		 * walk through NDP
 		 * dwSignature
 		 */
-		tmp = (void *)(skb->data + ndp_index);
+		tmp = (__le16 *)(ntb_ptr + ndp_index);
 		if (get_unaligned_le32(tmp) != ncm->ndp_sign) {
 			INFO(port->func.config->cdev, "Wrong NDP SIGN\n");
 			goto err;
@@ -1296,11 +1301,11 @@ static int ncm_unwrap_ntb(struct gether *port,
 			if (ncm->is_crc) {
 				uint32_t crc, crc2;
 
-				crc = get_unaligned_le32(skb->data +
+				crc = get_unaligned_le32(ntb_ptr +
 							 index + dg_len -
 							 crc_len);
 				crc2 = ~crc32_le(~0,
-						 skb->data + index,
+						 ntb_ptr + index,
 						 dg_len - crc_len);
 				if (crc != crc2) {
 					INFO(port->func.config->cdev,
@@ -1327,7 +1332,7 @@ static int ncm_unwrap_ntb(struct gether *port,
 							 dg_len - crc_len);
 			if (skb2 == NULL)
 				goto err;
-			skb_put_data(skb2, skb->data + index,
+			skb_put_data(skb2, ntb_ptr + index,
 				     dg_len - crc_len);
 
 			skb_queue_tail(list, skb2);
@@ -1340,10 +1345,17 @@ static int ncm_unwrap_ntb(struct gether *port,
 		} while (ndp_len > 2 * (opts->dgram_item_len * 2));
 	} while (ndp_index);
 
-	dev_consume_skb_any(skb);
-
 	VDBG(port->func.config->cdev,
 	     "Parsed NTB with %d frames\n", dgram_counter);
+
+	to_process -= block_len;
+	if (to_process != 0) {
+		ntb_ptr = (unsigned char *)(ntb_ptr + block_len);
+		goto parse_ntb;
+	}
+
+	dev_consume_skb_any(skb);
+
 	return 0;
 err:
 	skb_queue_purge(list);
-- 
GitLab


From a7bd88de46fd70f553209d383d0e3ec0b77979c8 Mon Sep 17 00:00:00 2001
From: Christophe Leroy <christophe.leroy@csgroup.eu>
Date: Mon, 25 Sep 2023 20:31:16 +0200
Subject: [PATCH 216/298] powerpc/64e: Fix wrong test in
 __ptep_test_and_clear_young()

[ Upstream commit 5ea0bbaa32e8f54e9a57cfee4a3b8769b80be0d2 ]

Commit 45201c879469 ("powerpc/nohash: Remove hash related code from
nohash headers.") replaced:

  if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
	return 0;

By:

  if (pte_young(*ptep))
	return 0;

But it should be:

  if (!pte_young(*ptep))
	return 0;

Fix it.

Fixes: 45201c879469 ("powerpc/nohash: Remove hash related code from nohash headers.")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/8bb7f06494e21adada724ede47a4c3d97e879d40.1695659959.git.christophe.leroy@csgroup.eu
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 arch/powerpc/include/asm/nohash/64/pgtable.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h b/arch/powerpc/include/asm/nohash/64/pgtable.h
index 7cd6809f4d33..30fcffc02caa 100644
--- a/arch/powerpc/include/asm/nohash/64/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/64/pgtable.h
@@ -215,7 +215,7 @@ static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
 {
 	unsigned long old;
 
-	if (pte_young(*ptep))
+	if (!pte_young(*ptep))
 		return 0;
 	old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
 	return (old & _PAGE_ACCESSED) != 0;
-- 
GitLab


From 3719d3c36aa853d5a2401af9f8d6b116c91ad5ae Mon Sep 17 00:00:00 2001
From: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Date: Thu, 12 Oct 2023 13:04:24 +0300
Subject: [PATCH 217/298] x86/alternatives: Disable KASAN in
 apply_alternatives()

commit d35652a5fc9944784f6f50a5c979518ff8dacf61 upstream.

Fei has reported that KASAN triggers during apply_alternatives() on
a 5-level paging machine:

	BUG: KASAN: out-of-bounds in rcu_is_watching()
	Read of size 4 at addr ff110003ee6419a0 by task swapper/0/0
	...
	__asan_load4()
	rcu_is_watching()
	trace_hardirqs_on()
	text_poke_early()
	apply_alternatives()
	...

On machines with 5-level paging, cpu_feature_enabled(X86_FEATURE_LA57)
gets patched. It includes KASAN code, where KASAN_SHADOW_START depends on
__VIRTUAL_MASK_SHIFT, which is defined with cpu_feature_enabled().

KASAN gets confused when apply_alternatives() patches the
KASAN_SHADOW_START users. A test patch that makes KASAN_SHADOW_START
static, by replacing __VIRTUAL_MASK_SHIFT with 56, works around the issue.

Fix it for real by disabling KASAN while the kernel is patching alternatives.

[ mingo: updated the changelog ]

Fixes: 6657fca06e3f ("x86/mm: Allow to boot without LA57 if CONFIG_X86_5LEVEL=y")
Reported-by: Fei Yang <fei.yang@intel.com>
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20231012100424.1456-1-kirill.shutemov@linux.intel.com
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 arch/x86/kernel/alternative.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 918a23704c0c..dee94961a667 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -366,6 +366,17 @@ void __init_or_module noinline apply_alternatives(struct alt_instr *start,
 	u8 insnbuf[MAX_PATCH_LEN];
 
 	DPRINTK("alt table %px, -> %px", start, end);
+
+	/*
+	 * In the case CONFIG_X86_5LEVEL=y, KASAN_SHADOW_START is defined using
+	 * cpu_feature_enabled(X86_FEATURE_LA57) and is therefore patched here.
+	 * During the process, KASAN becomes confused seeing partial LA57
+	 * conversion and triggers a false-positive out-of-bound report.
+	 *
+	 * Disable KASAN until the patching is complete.
+	 */
+	kasan_disable_current();
+
 	/*
 	 * The scan order should be from start to end. A later scanned
 	 * alternative code can overwrite previously scanned alternative code.
@@ -426,6 +437,8 @@ void __init_or_module noinline apply_alternatives(struct alt_instr *start,
 
 		text_poke_early(instr, insnbuf, insnbuf_sz);
 	}
+
+	kasan_enable_current();
 }
 
 #ifdef CONFIG_SMP
-- 
GitLab


From 0be01dc898df6a2f7c4f19d70af9a7e8c99bf264 Mon Sep 17 00:00:00 2001
From: Nicolas Dichtel <nicolas.dichtel@6wind.com>
Date: Thu, 24 Jun 2021 10:05:05 +0200
Subject: [PATCH 218/298] dev_forward_skb: do not scrub skb mark within the
 same name space

commit ff70202b2d1ad522275c6aadc8c53519b6a22c57 upstream.

The goal is to keep the mark during a bpf_redirect(), like it is done for
legacy encapsulation / decapsulation, when there is no x-netns.
This was initially done in commit 213dd74aee76 ("skbuff: Do not scrub skb
mark within the same name space").

When the call to skb_scrub_packet() was added in dev_forward_skb() (commit
8b27f27797ca ("skb: allow skb_scrub_packet() to be used by tunnels")), the
second argument (xnet) was set to true to force a call to skb_orphan(). At
this time, the mark was always cleanned up by skb_scrub_packet(), whatever
xnet value was.
This call to skb_orphan() was removed later in commit
9c4c325252c5 ("skbuff: preserve sock reference when scrubbing the skb.").
But this 'true' stayed here without any real reason.

Let's correctly set xnet in ____dev_forward_skb(), this function has access
to the previous interface and to the new interface.

Signed-off-by: Nicolas Dichtel <nicolas.dichtel@6wind.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Cc: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 include/linux/netdevice.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index e977118111f6..744017475b1d 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -3661,7 +3661,7 @@ static __always_inline int ____dev_forward_skb(struct net_device *dev,
 		return NET_RX_DROP;
 	}
 
-	skb_scrub_packet(skb, true);
+	skb_scrub_packet(skb, !net_eq(dev_net(dev), dev_net(skb->dev)));
 	skb->priority = 0;
 	return 0;
 }
-- 
GitLab


From 8e7346bfea56453e31b7421c1c17ca2fb9ed613d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ricardo=20Ca=C3=B1uelo?= <ricardo.canuelo@collabora.com>
Date: Wed, 30 Aug 2023 12:04:18 +0200
Subject: [PATCH 219/298] usb: hub: Guard against accesses to uninitialized BOS
 descriptors
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

commit f74a7afc224acd5e922c7a2e52244d891bbe44ee upstream.

Many functions in drivers/usb/core/hub.c and drivers/usb/core/hub.h
access fields inside udev->bos without checking if it was allocated and
initialized. If usb_get_bos_descriptor() fails for whatever
reason, udev->bos will be NULL and those accesses will result in a
crash:

BUG: kernel NULL pointer dereference, address: 0000000000000018
PGD 0 P4D 0
Oops: 0000 [#1] PREEMPT SMP NOPTI
CPU: 5 PID: 17818 Comm: kworker/5:1 Tainted: G W 5.15.108-18910-gab0e1cb584e1 #1 <HASH:1f9e 1>
Hardware name: Google Kindred/Kindred, BIOS Google_Kindred.12672.413.0 02/03/2021
Workqueue: usb_hub_wq hub_event
RIP: 0010:hub_port_reset+0x193/0x788
Code: 89 f7 e8 20 f7 15 00 48 8b 43 08 80 b8 96 03 00 00 03 75 36 0f b7 88 92 03 00 00 81 f9 10 03 00 00 72 27 48 8b 80 a8 03 00 00 <48> 83 78 18 00 74 19 48 89 df 48 8b 75 b0 ba 02 00 00 00 4c 89 e9
RSP: 0018:ffffab740c53fcf8 EFLAGS: 00010246
RAX: 0000000000000000 RBX: ffffa1bc5f678000 RCX: 0000000000000310
RDX: fffffffffffffdff RSI: 0000000000000286 RDI: ffffa1be9655b840
RBP: ffffab740c53fd70 R08: 00001b7d5edaa20c R09: ffffffffb005e060
R10: 0000000000000001 R11: 0000000000000000 R12: 0000000000000000
R13: ffffab740c53fd3e R14: 0000000000000032 R15: 0000000000000000
FS: 0000000000000000(0000) GS:ffffa1be96540000(0000) knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 0000000000000018 CR3: 000000022e80c005 CR4: 00000000003706e0
Call Trace:
hub_event+0x73f/0x156e
? hub_activate+0x5b7/0x68f
process_one_work+0x1a2/0x487
worker_thread+0x11a/0x288
kthread+0x13a/0x152
? process_one_work+0x487/0x487
? kthread_associate_blkcg+0x70/0x70
ret_from_fork+0x1f/0x30

Fall back to a default behavior if the BOS descriptor isn't accessible
and skip all the functionalities that depend on it: LPM support checks,
Super Speed capabilitiy checks, U1/U2 states setup.

Signed-off-by: Ricardo Cañuelo <ricardo.canuelo@collabora.com>
Cc: stable <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20230830100418.1952143-1-ricardo.canuelo@collabora.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/core/hub.c | 28 ++++++++++++++++++++++++----
 drivers/usb/core/hub.h |  2 +-
 2 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 619e80783866..898df2e43945 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -147,6 +147,10 @@ int usb_device_supports_lpm(struct usb_device *udev)
 	if (udev->quirks & USB_QUIRK_NO_LPM)
 		return 0;
 
+	/* Skip if the device BOS descriptor couldn't be read */
+	if (!udev->bos)
+		return 0;
+
 	/* USB 2.1 (and greater) devices indicate LPM support through
 	 * their USB 2.0 Extended Capabilities BOS descriptor.
 	 */
@@ -323,6 +327,10 @@ static void usb_set_lpm_parameters(struct usb_device *udev)
 	if (!udev->lpm_capable || udev->speed < USB_SPEED_SUPER)
 		return;
 
+	/* Skip if the device BOS descriptor couldn't be read */
+	if (!udev->bos)
+		return;
+
 	hub = usb_hub_to_struct_hub(udev->parent);
 	/* It doesn't take time to transition the roothub into U0, since it
 	 * doesn't have an upstream link.
@@ -2644,7 +2652,8 @@ int usb_authorize_device(struct usb_device *usb_dev)
 }
 
 /*
- * Return 1 if port speed is SuperSpeedPlus, 0 otherwise
+ * Return 1 if port speed is SuperSpeedPlus, 0 otherwise or if the
+ * capability couldn't be checked.
  * check it from the link protocol field of the current speed ID attribute.
  * current speed ID is got from ext port status request. Sublink speed attribute
  * table is returned with the hub BOS SSP device capability descriptor
@@ -2654,8 +2663,12 @@ static int port_speed_is_ssp(struct usb_device *hdev, int speed_id)
 	int ssa_count;
 	u32 ss_attr;
 	int i;
-	struct usb_ssp_cap_descriptor *ssp_cap = hdev->bos->ssp_cap;
+	struct usb_ssp_cap_descriptor *ssp_cap;
 
+	if (!hdev->bos)
+		return 0;
+
+	ssp_cap = hdev->bos->ssp_cap;
 	if (!ssp_cap)
 		return 0;
 
@@ -4057,8 +4070,15 @@ static void usb_enable_link_state(struct usb_hcd *hcd, struct usb_device *udev,
 		enum usb3_link_state state)
 {
 	int timeout, ret;
-	__u8 u1_mel = udev->bos->ss_cap->bU1devExitLat;
-	__le16 u2_mel = udev->bos->ss_cap->bU2DevExitLat;
+	__u8 u1_mel;
+	__le16 u2_mel;
+
+	/* Skip if the device BOS descriptor couldn't be read */
+	if (!udev->bos)
+		return;
+
+	u1_mel = udev->bos->ss_cap->bU1devExitLat;
+	u2_mel = udev->bos->ss_cap->bU2DevExitLat;
 
 	/* If the device says it doesn't have *any* exit latency to come out of
 	 * U1 or U2, it's probably lying.  Assume it doesn't implement that link
diff --git a/drivers/usb/core/hub.h b/drivers/usb/core/hub.h
index df3aa0b69188..d1845e5ff700 100644
--- a/drivers/usb/core/hub.h
+++ b/drivers/usb/core/hub.h
@@ -139,7 +139,7 @@ static inline int hub_is_superspeedplus(struct usb_device *hdev)
 {
 	return (hdev->descriptor.bDeviceProtocol == USB_HUB_PR_SS &&
 		le16_to_cpu(hdev->descriptor.bcdUSB) >= 0x0310 &&
-		hdev->bos->ssp_cap);
+		hdev->bos && hdev->bos->ssp_cap);
 }
 
 static inline unsigned hub_power_on_good_delay(struct usb_hub *hub)
-- 
GitLab


From 2f83067d8647ef984c7ff729843f1cf3eb309a07 Mon Sep 17 00:00:00 2001
From: "Lee, Chun-Yi" <jlee@suse.com>
Date: Sun, 1 Oct 2023 16:59:31 +0800
Subject: [PATCH 220/298] Bluetooth: hci_event: Ignore NULL link key

commit 33155c4aae5260475def6f7438e4e35564f4f3ba upstream.

This change is used to relieve CVE-2020-26555. The description of the
CVE:

Bluetooth legacy BR/EDR PIN code pairing in Bluetooth Core Specification
1.0B through 5.2 may permit an unauthenticated nearby device to spoof
the BD_ADDR of the peer device to complete pairing without knowledge
of the PIN. [1]

The detail of this attack is in IEEE paper:
BlueMirror: Reflections on Bluetooth Pairing and Provisioning Protocols
[2]

It's a reflection attack. The paper mentioned that attacker can induce
the attacked target to generate null link key (zero key) without PIN
code. In BR/EDR, the key generation is actually handled in the controller
which is below HCI.

Thus, we can ignore null link key in the handler of "Link Key Notification
event" to relieve the attack. A similar implementation also shows in
btstack project. [3]

v3: Drop the connection when null link key be detected.

v2:
- Used Link: tag instead of Closes:
- Used bt_dev_dbg instead of BT_DBG
- Added Fixes: tag

Cc: stable@vger.kernel.org
Fixes: 55ed8ca10f35 ("Bluetooth: Implement link key handling for the management interface")
Link: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2020-26555 [1]
Link: https://ieeexplore.ieee.org/abstract/document/9474325/authors#authors [2]
Link: https://github.com/bluekitchen/btstack/blob/master/src/hci.c#L3722 [3]
Signed-off-by: Lee, Chun-Yi <jlee@suse.com>
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/bluetooth/hci_event.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
index dd7bf437d88e..e333b8136436 100644
--- a/net/bluetooth/hci_event.c
+++ b/net/bluetooth/hci_event.c
@@ -3816,6 +3816,15 @@ static void hci_link_key_notify_evt(struct hci_dev *hdev, struct sk_buff *skb)
 	if (!conn)
 		goto unlock;
 
+	/* Ignore NULL link key against CVE-2020-26555 */
+	if (!memcmp(ev->link_key, ZERO_KEY, HCI_LINK_KEY_SIZE)) {
+		bt_dev_dbg(hdev, "Ignore NULL link key (ZERO KEY) for %pMR",
+			   &ev->bdaddr);
+		hci_disconnect(conn, HCI_ERROR_AUTH_FAILURE);
+		hci_conn_drop(conn);
+		goto unlock;
+	}
+
 	hci_conn_hold(conn);
 	conn->disc_timeout = HCI_DISCONN_TIMEOUT;
 	hci_conn_drop(conn);
-- 
GitLab


From 9fc2677622d46aac3083ed595b801ad90b86ed71 Mon Sep 17 00:00:00 2001
From: "Lee, Chun-Yi" <jlee@suse.com>
Date: Sun, 1 Oct 2023 16:59:58 +0800
Subject: [PATCH 221/298] Bluetooth: Reject connection with the device which
 has same BD_ADDR

commit 1ffc6f8cc33268731fcf9629fc4438f6db1191fc upstream.

This change is used to relieve CVE-2020-26555. The description of
the CVE:

Bluetooth legacy BR/EDR PIN code pairing in Bluetooth Core Specification
1.0B through 5.2 may permit an unauthenticated nearby device to spoof
the BD_ADDR of the peer device to complete pairing without knowledge
of the PIN. [1]

The detail of this attack is in IEEE paper:
BlueMirror: Reflections on Bluetooth Pairing and Provisioning Protocols
[2]

It's a reflection attack. The paper mentioned that attacker can induce
the attacked target to generate null link key (zero key) without PIN
code. In BR/EDR, the key generation is actually handled in the controller
which is below HCI.

A condition of this attack is that attacker should change the
BR_ADDR of his hacking device (Host B) to equal to the BR_ADDR with
the target device being attacked (Host A).

Thus, we reject the connection with device which has same BD_ADDR
both on HCI_Create_Connection and HCI_Connection_Request to prevent
the attack. A similar implementation also shows in btstack project.
[3][4]

Cc: stable@vger.kernel.org
Link: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2020-26555 [1]
Link: https://ieeexplore.ieee.org/abstract/document/9474325/authors#authors [2]
Link: https://github.com/bluekitchen/btstack/blob/master/src/hci.c#L3523 [3]
Link: https://github.com/bluekitchen/btstack/blob/master/src/hci.c#L7297 [4]
Signed-off-by: Lee, Chun-Yi <jlee@suse.com>
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/bluetooth/hci_conn.c  |  9 +++++++++
 net/bluetooth/hci_event.c | 11 +++++++++++
 2 files changed, 20 insertions(+)

diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c
index 1b50e4ef2c68..9d01cccc84ad 100644
--- a/net/bluetooth/hci_conn.c
+++ b/net/bluetooth/hci_conn.c
@@ -1204,6 +1204,15 @@ struct hci_conn *hci_connect_acl(struct hci_dev *hdev, bdaddr_t *dst,
 		return ERR_PTR(-EOPNOTSUPP);
 	}
 
+	/* Reject outgoing connection to device with same BD ADDR against
+	 * CVE-2020-26555
+	 */
+	if (!bacmp(&hdev->bdaddr, dst)) {
+		bt_dev_dbg(hdev, "Reject connection with same BD_ADDR %pMR\n",
+			   dst);
+		return ERR_PTR(-ECONNREFUSED);
+	}
+
 	acl = hci_conn_hash_lookup_ba(hdev, ACL_LINK, dst);
 	if (!acl) {
 		acl = hci_conn_add(hdev, ACL_LINK, dst, HCI_ROLE_MASTER);
diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
index e333b8136436..46c2d8ed66bf 100644
--- a/net/bluetooth/hci_event.c
+++ b/net/bluetooth/hci_event.c
@@ -2510,6 +2510,17 @@ static void hci_conn_request_evt(struct hci_dev *hdev, struct sk_buff *skb)
 	BT_DBG("%s bdaddr %pMR type 0x%x", hdev->name, &ev->bdaddr,
 	       ev->link_type);
 
+	/* Reject incoming connection from device with same BD ADDR against
+	 * CVE-2020-26555
+	 */
+	if (!bacmp(&hdev->bdaddr, &ev->bdaddr))
+	{
+		bt_dev_dbg(hdev, "Reject connection with same BD_ADDR %pMR\n",
+			   &ev->bdaddr);
+		hci_reject_conn(hdev, &ev->bdaddr);
+		return;
+	}
+
 	mask |= hci_proto_connect_ind(hdev, &ev->bdaddr, ev->link_type,
 				      &flags);
 
-- 
GitLab


From ccb8618c972f941ebc6b2b9db491025b3369efcb Mon Sep 17 00:00:00 2001
From: Ziyang Xuan <william.xuanziyang@huawei.com>
Date: Wed, 4 Oct 2023 20:42:24 +0800
Subject: [PATCH 222/298] Bluetooth: Fix a refcnt underflow problem for
 hci_conn

commit c7f59461f5a78994613afc112cdd73688aef9076 upstream.

Syzbot reports a warning as follows:

WARNING: CPU: 1 PID: 26946 at net/bluetooth/hci_conn.c:619
hci_conn_timeout+0x122/0x210 net/bluetooth/hci_conn.c:619
...
Call Trace:
 <TASK>
 process_one_work+0x884/0x15c0 kernel/workqueue.c:2630
 process_scheduled_works kernel/workqueue.c:2703 [inline]
 worker_thread+0x8b9/0x1290 kernel/workqueue.c:2784
 kthread+0x33c/0x440 kernel/kthread.c:388
 ret_from_fork+0x45/0x80 arch/x86/kernel/process.c:147
 ret_from_fork_asm+0x11/0x20 arch/x86/entry/entry_64.S:304
 </TASK>

It is because the HCI_EV_SIMPLE_PAIR_COMPLETE event handler drops
hci_conn directly without check Simple Pairing whether be enabled. But
the Simple Pairing process can only be used if both sides have the
support enabled in the host stack.

Add hci_conn_ssp_enabled() for hci_conn in HCI_EV_IO_CAPA_REQUEST and
HCI_EV_SIMPLE_PAIR_COMPLETE event handlers to fix the problem.

Fixes: 0493684ed239 ("[Bluetooth] Disable disconnect timer during Simple Pairing")
Signed-off-by: Ziyang Xuan <william.xuanziyang@huawei.com>
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/bluetooth/hci_event.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
index 46c2d8ed66bf..cd8708f1bdfb 100644
--- a/net/bluetooth/hci_event.c
+++ b/net/bluetooth/hci_event.c
@@ -4342,7 +4342,7 @@ static void hci_io_capa_request_evt(struct hci_dev *hdev, struct sk_buff *skb)
 	hci_dev_lock(hdev);
 
 	conn = hci_conn_hash_lookup_ba(hdev, ACL_LINK, &ev->bdaddr);
-	if (!conn)
+	if (!conn || !hci_conn_ssp_enabled(conn))
 		goto unlock;
 
 	hci_conn_hold(conn);
@@ -4577,7 +4577,7 @@ static void hci_simple_pair_complete_evt(struct hci_dev *hdev,
 	hci_dev_lock(hdev);
 
 	conn = hci_conn_hash_lookup_ba(hdev, ACL_LINK, &ev->bdaddr);
-	if (!conn)
+	if (!conn || !hci_conn_ssp_enabled(conn))
 		goto unlock;
 
 	/* Reset the authentication requirement to unknown */
-- 
GitLab


From 4e31ae6c402ddf07dccb4fd6323499dffca34cc9 Mon Sep 17 00:00:00 2001
From: Arkadiusz Bokowy <arkadiusz.bokowy@gmail.com>
Date: Wed, 20 Sep 2023 17:30:07 +0200
Subject: [PATCH 223/298] Bluetooth: vhci: Fix race when opening vhci device

commit 92d4abd66f7080075793970fc8f241239e58a9e7 upstream.

When the vhci device is opened in the two-step way, i.e.: open device
then write a vendor packet with requested controller type, the device
shall respond with a vendor packet which includes HCI index of created
interface.

When the virtual HCI is created, the host sends a reset request to the
controller. This request is processed by the vhci_send_frame() function.
However, this request is send by a different thread, so it might happen
that this HCI request will be received before the vendor response is
queued in the read queue. This results in the HCI vendor response and
HCI reset request inversion in the read queue which leads to improper
behavior of btvirt:

> dmesg
[1754256.640122] Bluetooth: MGMT ver 1.22
[1754263.023806] Bluetooth: MGMT ver 1.22
[1754265.043775] Bluetooth: hci1: Opcode 0x c03 failed: -110

In order to synchronize vhci two-step open/setup process with virtual
HCI initialization, this patch adds internal lock when queuing data in
the vhci_send_frame() function.

Signed-off-by: Arkadiusz Bokowy <arkadiusz.bokowy@gmail.com>
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/bluetooth/hci_vhci.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/bluetooth/hci_vhci.c b/drivers/bluetooth/hci_vhci.c
index 22f9145a426f..29d8b5896d6e 100644
--- a/drivers/bluetooth/hci_vhci.c
+++ b/drivers/bluetooth/hci_vhci.c
@@ -82,7 +82,10 @@ static int vhci_send_frame(struct hci_dev *hdev, struct sk_buff *skb)
 	struct vhci_data *data = hci_get_drvdata(hdev);
 
 	memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1);
+
+	mutex_lock(&data->open_mutex);
 	skb_queue_tail(&data->readq, skb);
+	mutex_unlock(&data->open_mutex);
 
 	wake_up_interruptible(&data->read_wait);
 	return 0;
-- 
GitLab


From 4f0f93e15321285da012ef6798866c93a19c6855 Mon Sep 17 00:00:00 2001
From: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Date: Thu, 5 Oct 2023 14:12:19 -0700
Subject: [PATCH 224/298] Bluetooth: hci_event: Fix coding style

commit 35d91d95a0cd61ebb90e0246dc917fd25e519b8c upstream.

This fixes the following code style problem:

ERROR: that open brace { should be on the previous line
+	if (!bacmp(&hdev->bdaddr, &ev->bdaddr))
+	{

Fixes: 1ffc6f8cc332 ("Bluetooth: Reject connection with the device which has same BD_ADDR")
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/bluetooth/hci_event.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
index cd8708f1bdfb..e6855f2c9660 100644
--- a/net/bluetooth/hci_event.c
+++ b/net/bluetooth/hci_event.c
@@ -2513,8 +2513,7 @@ static void hci_conn_request_evt(struct hci_dev *hdev, struct sk_buff *skb)
 	/* Reject incoming connection from device with same BD ADDR against
 	 * CVE-2020-26555
 	 */
-	if (!bacmp(&hdev->bdaddr, &ev->bdaddr))
-	{
+	if (!bacmp(&hdev->bdaddr, &ev->bdaddr)) {
 		bt_dev_dbg(hdev, "Reject connection with same BD_ADDR %pMR\n",
 			   &ev->bdaddr);
 		hci_reject_conn(hdev, &ev->bdaddr);
-- 
GitLab


From 5afc7720e77d81cfdff6d64567b141aec0b1ad64 Mon Sep 17 00:00:00 2001
From: Arnd Bergmann <arnd@arndb.de>
Date: Mon, 9 Oct 2023 22:31:31 +0200
Subject: [PATCH 225/298] Bluetooth: avoid memcmp() out of bounds warning

commit 9d1a3c74746428102d55371fbf74b484733937d9 upstream.

bacmp() is a wrapper around memcpy(), which contain compile-time
checks for buffer overflow. Since the hci_conn_request_evt() also calls
bt_dev_dbg() with an implicit NULL pointer check, the compiler is now
aware of a case where 'hdev' is NULL and treats this as meaning that
zero bytes are available:

In file included from net/bluetooth/hci_event.c:32:
In function 'bacmp',
    inlined from 'hci_conn_request_evt' at net/bluetooth/hci_event.c:3276:7:
include/net/bluetooth/bluetooth.h:364:16: error: 'memcmp' specified bound 6 exceeds source size 0 [-Werror=stringop-overread]
  364 |         return memcmp(ba1, ba2, sizeof(bdaddr_t));
      |                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Add another NULL pointer check before the bacmp() to ensure the compiler
understands the code flow enough to not warn about it.  Since the patch
that introduced the warning is marked for stable backports, this one
should also go that way to avoid introducing build regressions.

Fixes: 1ffc6f8cc332 ("Bluetooth: Reject connection with the device which has same BD_ADDR")
Cc: Kees Cook <keescook@chromium.org>
Cc: "Lee, Chun-Yi" <jlee@suse.com>
Cc: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Cc: Marcel Holtmann <marcel@holtmann.org>
Cc: stable@vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/bluetooth/hci_event.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
index e6855f2c9660..843502783b26 100644
--- a/net/bluetooth/hci_event.c
+++ b/net/bluetooth/hci_event.c
@@ -2513,7 +2513,7 @@ static void hci_conn_request_evt(struct hci_dev *hdev, struct sk_buff *skb)
 	/* Reject incoming connection from device with same BD ADDR against
 	 * CVE-2020-26555
 	 */
-	if (!bacmp(&hdev->bdaddr, &ev->bdaddr)) {
+	if (hdev && !bacmp(&hdev->bdaddr, &ev->bdaddr)) {
 		bt_dev_dbg(hdev, "Reject connection with same BD_ADDR %pMR\n",
 			   &ev->bdaddr);
 		hci_reject_conn(hdev, &ev->bdaddr);
-- 
GitLab


From 5622592f8f74ae3e594379af02e64ea84772d0dd Mon Sep 17 00:00:00 2001
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Date: Fri, 13 Oct 2023 20:41:29 +0200
Subject: [PATCH 226/298] nfc: nci: fix possible NULL pointer dereference in
 send_acknowledge()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

commit 7937609cd387246aed994e81aa4fa951358fba41 upstream.

Handle memory allocation failure from nci_skb_alloc() (calling
alloc_skb()) to avoid possible NULL pointer dereference.

Reported-by: 黄思聪 <huangsicong@iie.ac.cn>
Fixes: 391d8a2da787 ("NFC: Add NCI over SPI receive")
Cc: <stable@vger.kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://lore.kernel.org/r/20231013184129.18738-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/nfc/nci/spi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/net/nfc/nci/spi.c b/net/nfc/nci/spi.c
index 452f4c16b7a9..d2de7fc226f0 100644
--- a/net/nfc/nci/spi.c
+++ b/net/nfc/nci/spi.c
@@ -163,6 +163,8 @@ static int send_acknowledge(struct nci_spi *nspi, u8 acknowledge)
 	int ret;
 
 	skb = nci_skb_alloc(nspi->ndev, 0, GFP_KERNEL);
+	if (!skb)
+		return -ENOMEM;
 
 	/* add the NCI SPI header to the start of the buffer */
 	hdr = skb_push(skb, NCI_SPI_HDR_LEN);
-- 
GitLab


From 7219c6b8fa24ec55a19d7a5ea58fb09151e37950 Mon Sep 17 00:00:00 2001
From: Johan Hovold <johan+linaro@kernel.org>
Date: Fri, 6 Oct 2023 10:21:04 +0200
Subject: [PATCH 227/298] regmap: fix NULL deref on lookup

commit c6df843348d6b71ea986266c12831cb60c2cf325 upstream.

Not all regmaps have a name so make sure to check for that to avoid
dereferencing a NULL pointer when dev_get_regmap() is used to lookup a
named regmap.

Fixes: e84861fec32d ("regmap: dev_get_regmap_match(): fix string comparison")
Cc: stable@vger.kernel.org      # 5.8
Cc: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20231006082104.16707-1-johan+linaro@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/base/regmap/regmap.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index 540c879abe52..5e03735374ae 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -1343,7 +1343,7 @@ static int dev_get_regmap_match(struct device *dev, void *res, void *data)
 
 	/* If the user didn't specify a name match any */
 	if (data)
-		return !strcmp((*r)->name, data);
+		return (*r)->name && !strcmp((*r)->name, data);
 	else
 		return 1;
 }
-- 
GitLab


From 79f52485a0aa4019525c411a8d4fa4df2ae95121 Mon Sep 17 00:00:00 2001
From: Jim Mattson <jmattson@google.com>
Date: Mon, 25 Sep 2023 17:34:47 +0000
Subject: [PATCH 228/298] KVM: x86: Mask LVTPC when handling a PMI

commit a16eb25b09c02a54c1c1b449d4b6cfa2cf3f013a upstream.

Per the SDM, "When the local APIC handles a performance-monitoring
counters interrupt, it automatically sets the mask flag in the LVT
performance counter register."  Add this behavior to KVM's local APIC
emulation.

Failure to mask the LVTPC entry results in spurious PMIs, e.g. when
running Linux as a guest, PMI handlers that do a "late_ack" spew a large
number of "dazed and confused" spurious NMI warnings.

Fixes: f5132b01386b ("KVM: Expose a version 2 architectural PMU to a guests")
Cc: stable@vger.kernel.org
Signed-off-by: Jim Mattson <jmattson@google.com>
Tested-by: Mingwei Zhang <mizhang@google.com>
Signed-off-by: Mingwei Zhang <mizhang@google.com>
Link: https://lore.kernel.org/r/20230925173448.3518223-3-mizhang@google.com
[sean: massage changelog, correct Fixes]
Signed-off-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 arch/x86/kvm/lapic.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 027941e3df68..256b00f456e6 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2201,13 +2201,17 @@ int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
 {
 	u32 reg = kvm_lapic_get_reg(apic, lvt_type);
 	int vector, mode, trig_mode;
+	int r;
 
 	if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
 		vector = reg & APIC_VECTOR_MASK;
 		mode = reg & APIC_MODE_MASK;
 		trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
-		return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
-					NULL);
+
+		r = __apic_accept_irq(apic, mode, vector, 1, trig_mode, NULL);
+		if (r && lvt_type == APIC_LVTPC)
+			kvm_lapic_set_reg(apic, APIC_LVTPC, reg | APIC_LVT_MASKED);
+		return r;
 	}
 	return 0;
 }
-- 
GitLab


From 34bc213fc4b4858df588020cc810072c1e2bf6ef Mon Sep 17 00:00:00 2001
From: Florian Westphal <fw@strlen.de>
Date: Sun, 8 Oct 2023 19:36:53 +0200
Subject: [PATCH 229/298] netfilter: nft_payload: fix wrong mac header matching
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

commit d351c1ea2de3e36e608fc355d8ae7d0cc80e6cd6 upstream.

mcast packets get looped back to the local machine.
Such packets have a 0-length mac header, we should treat
this like "mac header not set" and abort rule evaluation.

As-is, we just copy data from the network header instead.

Fixes: 96518518cc41 ("netfilter: add nftables")
Reported-by: Blažej Krajňák <krajnak@levonet.sk>
Signed-off-by: Florian Westphal <fw@strlen.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/netfilter/nft_payload.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/netfilter/nft_payload.c b/net/netfilter/nft_payload.c
index 77cfd5182784..0ef51c81ec94 100644
--- a/net/netfilter/nft_payload.c
+++ b/net/netfilter/nft_payload.c
@@ -84,7 +84,7 @@ static void nft_payload_eval(const struct nft_expr *expr,
 
 	switch (priv->base) {
 	case NFT_PAYLOAD_LL_HEADER:
-		if (!skb_mac_header_was_set(skb))
+		if (!skb_mac_header_was_set(skb) || skb_mac_header_len(skb) == 0)
 			goto err;
 
 		if (skb_vlan_tag_present(skb)) {
-- 
GitLab


From 17c75411e25a84ed25fe6bbbcf707e1068ff985c Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Fri, 8 Sep 2023 18:13:59 +0000
Subject: [PATCH 230/298] xfrm: fix a data-race in xfrm_gen_index()

commit 3e4bc23926b83c3c67e5f61ae8571602754131a6 upstream.

xfrm_gen_index() mutual exclusion uses net->xfrm.xfrm_policy_lock.

This means we must use a per-netns idx_generator variable,
instead of a static one.
Alternative would be to use an atomic variable.

syzbot reported:

BUG: KCSAN: data-race in xfrm_sk_policy_insert / xfrm_sk_policy_insert

write to 0xffffffff87005938 of 4 bytes by task 29466 on cpu 0:
xfrm_gen_index net/xfrm/xfrm_policy.c:1385 [inline]
xfrm_sk_policy_insert+0x262/0x640 net/xfrm/xfrm_policy.c:2347
xfrm_user_policy+0x413/0x540 net/xfrm/xfrm_state.c:2639
do_ipv6_setsockopt+0x1317/0x2ce0 net/ipv6/ipv6_sockglue.c:943
ipv6_setsockopt+0x57/0x130 net/ipv6/ipv6_sockglue.c:1012
rawv6_setsockopt+0x21e/0x410 net/ipv6/raw.c:1054
sock_common_setsockopt+0x61/0x70 net/core/sock.c:3697
__sys_setsockopt+0x1c9/0x230 net/socket.c:2263
__do_sys_setsockopt net/socket.c:2274 [inline]
__se_sys_setsockopt net/socket.c:2271 [inline]
__x64_sys_setsockopt+0x66/0x80 net/socket.c:2271
do_syscall_x64 arch/x86/entry/common.c:50 [inline]
do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80
entry_SYSCALL_64_after_hwframe+0x63/0xcd

read to 0xffffffff87005938 of 4 bytes by task 29460 on cpu 1:
xfrm_sk_policy_insert+0x13e/0x640
xfrm_user_policy+0x413/0x540 net/xfrm/xfrm_state.c:2639
do_ipv6_setsockopt+0x1317/0x2ce0 net/ipv6/ipv6_sockglue.c:943
ipv6_setsockopt+0x57/0x130 net/ipv6/ipv6_sockglue.c:1012
rawv6_setsockopt+0x21e/0x410 net/ipv6/raw.c:1054
sock_common_setsockopt+0x61/0x70 net/core/sock.c:3697
__sys_setsockopt+0x1c9/0x230 net/socket.c:2263
__do_sys_setsockopt net/socket.c:2274 [inline]
__se_sys_setsockopt net/socket.c:2271 [inline]
__x64_sys_setsockopt+0x66/0x80 net/socket.c:2271
do_syscall_x64 arch/x86/entry/common.c:50 [inline]
do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80
entry_SYSCALL_64_after_hwframe+0x63/0xcd

value changed: 0x00006ad8 -> 0x00006b18

Reported by Kernel Concurrency Sanitizer on:
CPU: 1 PID: 29460 Comm: syz-executor.1 Not tainted 6.5.0-rc5-syzkaller-00243-g9106536c1aa3 #0
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 07/26/2023

Fixes: 1121994c803f ("netns xfrm: policy insertion in netns")
Reported-by: syzbot <syzkaller@googlegroups.com>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Steffen Klassert <steffen.klassert@secunet.com>
Cc: Herbert Xu <herbert@gondor.apana.org.au>
Acked-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 include/net/netns/xfrm.h | 1 +
 net/xfrm/xfrm_policy.c   | 6 ++----
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/include/net/netns/xfrm.h b/include/net/netns/xfrm.h
index fbfa59801454..9a5212b46118 100644
--- a/include/net/netns/xfrm.h
+++ b/include/net/netns/xfrm.h
@@ -48,6 +48,7 @@ struct netns_xfrm {
 	struct list_head	policy_all;
 	struct hlist_head	*policy_byidx;
 	unsigned int		policy_idx_hmask;
+	unsigned int		idx_generator;
 	struct hlist_head	policy_inexact[XFRM_POLICY_MAX];
 	struct xfrm_policy_hash	policy_bydst[XFRM_POLICY_MAX];
 	unsigned int		policy_count[XFRM_POLICY_MAX * 2];
diff --git a/net/xfrm/xfrm_policy.c b/net/xfrm/xfrm_policy.c
index 6fe578773a51..c8a7a5739425 100644
--- a/net/xfrm/xfrm_policy.c
+++ b/net/xfrm/xfrm_policy.c
@@ -654,8 +654,6 @@ EXPORT_SYMBOL(xfrm_policy_hash_rebuild);
  * of an absolute inpredictability of ordering of rules. This will not pass. */
 static u32 xfrm_gen_index(struct net *net, int dir, u32 index)
 {
-	static u32 idx_generator;
-
 	for (;;) {
 		struct hlist_head *list;
 		struct xfrm_policy *p;
@@ -663,8 +661,8 @@ static u32 xfrm_gen_index(struct net *net, int dir, u32 index)
 		int found;
 
 		if (!index) {
-			idx = (idx_generator | dir);
-			idx_generator += 8;
+			idx = (net->xfrm.idx_generator | dir);
+			net->xfrm.idx_generator += 8;
 		} else {
 			idx = index;
 			index = 0;
-- 
GitLab


From d4d40dc75d861c831779c103151ade62005b74af Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Tue, 5 Sep 2023 13:23:03 +0000
Subject: [PATCH 231/298] xfrm: interface: use DEV_STATS_INC()

commit f7c4e3e5d4f6609b4725a97451948ca2e425379a upstream.

syzbot/KCSAN reported data-races in xfrm whenever dev->stats fields
are updated.

It appears all of these updates can happen from multiple cpus.

Adopt SMP safe DEV_STATS_INC() to update dev->stats fields.

BUG: KCSAN: data-race in xfrmi_xmit / xfrmi_xmit

read-write to 0xffff88813726b160 of 8 bytes by task 23986 on cpu 1:
xfrmi_xmit+0x74e/0xb20 net/xfrm/xfrm_interface_core.c:583
__netdev_start_xmit include/linux/netdevice.h:4889 [inline]
netdev_start_xmit include/linux/netdevice.h:4903 [inline]
xmit_one net/core/dev.c:3544 [inline]
dev_hard_start_xmit+0x11b/0x3f0 net/core/dev.c:3560
__dev_queue_xmit+0xeee/0x1de0 net/core/dev.c:4340
dev_queue_xmit include/linux/netdevice.h:3082 [inline]
neigh_connected_output+0x231/0x2a0 net/core/neighbour.c:1581
neigh_output include/net/neighbour.h:542 [inline]
ip_finish_output2+0x74a/0x850 net/ipv4/ip_output.c:230
ip_finish_output+0xf4/0x240 net/ipv4/ip_output.c:318
NF_HOOK_COND include/linux/netfilter.h:293 [inline]
ip_output+0xe5/0x1b0 net/ipv4/ip_output.c:432
dst_output include/net/dst.h:458 [inline]
ip_local_out net/ipv4/ip_output.c:127 [inline]
ip_send_skb+0x72/0xe0 net/ipv4/ip_output.c:1487
udp_send_skb+0x6a4/0x990 net/ipv4/udp.c:963
udp_sendmsg+0x1249/0x12d0 net/ipv4/udp.c:1246
inet_sendmsg+0x63/0x80 net/ipv4/af_inet.c:840
sock_sendmsg_nosec net/socket.c:730 [inline]
sock_sendmsg net/socket.c:753 [inline]
____sys_sendmsg+0x37c/0x4d0 net/socket.c:2540
___sys_sendmsg net/socket.c:2594 [inline]
__sys_sendmmsg+0x269/0x500 net/socket.c:2680
__do_sys_sendmmsg net/socket.c:2709 [inline]
__se_sys_sendmmsg net/socket.c:2706 [inline]
__x64_sys_sendmmsg+0x57/0x60 net/socket.c:2706
do_syscall_x64 arch/x86/entry/common.c:50 [inline]
do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80
entry_SYSCALL_64_after_hwframe+0x63/0xcd

read-write to 0xffff88813726b160 of 8 bytes by task 23987 on cpu 0:
xfrmi_xmit+0x74e/0xb20 net/xfrm/xfrm_interface_core.c:583
__netdev_start_xmit include/linux/netdevice.h:4889 [inline]
netdev_start_xmit include/linux/netdevice.h:4903 [inline]
xmit_one net/core/dev.c:3544 [inline]
dev_hard_start_xmit+0x11b/0x3f0 net/core/dev.c:3560
__dev_queue_xmit+0xeee/0x1de0 net/core/dev.c:4340
dev_queue_xmit include/linux/netdevice.h:3082 [inline]
neigh_connected_output+0x231/0x2a0 net/core/neighbour.c:1581
neigh_output include/net/neighbour.h:542 [inline]
ip_finish_output2+0x74a/0x850 net/ipv4/ip_output.c:230
ip_finish_output+0xf4/0x240 net/ipv4/ip_output.c:318
NF_HOOK_COND include/linux/netfilter.h:293 [inline]
ip_output+0xe5/0x1b0 net/ipv4/ip_output.c:432
dst_output include/net/dst.h:458 [inline]
ip_local_out net/ipv4/ip_output.c:127 [inline]
ip_send_skb+0x72/0xe0 net/ipv4/ip_output.c:1487
udp_send_skb+0x6a4/0x990 net/ipv4/udp.c:963
udp_sendmsg+0x1249/0x12d0 net/ipv4/udp.c:1246
inet_sendmsg+0x63/0x80 net/ipv4/af_inet.c:840
sock_sendmsg_nosec net/socket.c:730 [inline]
sock_sendmsg net/socket.c:753 [inline]
____sys_sendmsg+0x37c/0x4d0 net/socket.c:2540
___sys_sendmsg net/socket.c:2594 [inline]
__sys_sendmmsg+0x269/0x500 net/socket.c:2680
__do_sys_sendmmsg net/socket.c:2709 [inline]
__se_sys_sendmmsg net/socket.c:2706 [inline]
__x64_sys_sendmmsg+0x57/0x60 net/socket.c:2706
do_syscall_x64 arch/x86/entry/common.c:50 [inline]
do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80
entry_SYSCALL_64_after_hwframe+0x63/0xcd

value changed: 0x00000000000010d7 -> 0x00000000000010d8

Reported by Kernel Concurrency Sanitizer on:
CPU: 0 PID: 23987 Comm: syz-executor.5 Not tainted 6.5.0-syzkaller-10885-g0468be89b3fa #0
Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 07/26/2023

Fixes: f203b76d7809 ("xfrm: Add virtual xfrm interfaces")
Reported-by: syzbot <syzkaller@googlegroups.com>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Cc: Steffen Klassert <steffen.klassert@secunet.com>
Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/xfrm/xfrm_interface_core.c | 22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

diff --git a/net/xfrm/xfrm_interface_core.c b/net/xfrm/xfrm_interface_core.c
index 40081af62b68..10fa26103bdf 100644
--- a/net/xfrm/xfrm_interface_core.c
+++ b/net/xfrm/xfrm_interface_core.c
@@ -219,8 +219,8 @@ static int xfrmi_rcv_cb(struct sk_buff *skb, int err)
 	skb->dev = dev;
 
 	if (err) {
-		dev->stats.rx_errors++;
-		dev->stats.rx_dropped++;
+		DEV_STATS_INC(dev, rx_errors);
+		DEV_STATS_INC(dev, rx_dropped);
 
 		return 0;
 	}
@@ -260,7 +260,6 @@ static int
 xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl)
 {
 	struct xfrm_if *xi = netdev_priv(dev);
-	struct net_device_stats *stats = &xi->dev->stats;
 	struct dst_entry *dst = skb_dst(skb);
 	unsigned int length = skb->len;
 	struct net_device *tdev;
@@ -286,7 +285,7 @@ xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl)
 	tdev = dst->dev;
 
 	if (tdev == dev) {
-		stats->collisions++;
+		DEV_STATS_INC(dev, collisions);
 		net_warn_ratelimited("%s: Local routing loop detected!\n",
 				     dev->name);
 		goto tx_err_dst_release;
@@ -329,13 +328,13 @@ xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl)
 		tstats->tx_packets++;
 		u64_stats_update_end(&tstats->syncp);
 	} else {
-		stats->tx_errors++;
-		stats->tx_aborted_errors++;
+		DEV_STATS_INC(dev, tx_errors);
+		DEV_STATS_INC(dev, tx_aborted_errors);
 	}
 
 	return 0;
 tx_err_link_failure:
-	stats->tx_carrier_errors++;
+	DEV_STATS_INC(dev, tx_carrier_errors);
 	dst_link_failure(skb);
 tx_err_dst_release:
 	dst_release(dst);
@@ -345,7 +344,6 @@ xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl)
 static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev)
 {
 	struct xfrm_if *xi = netdev_priv(dev);
-	struct net_device_stats *stats = &xi->dev->stats;
 	struct dst_entry *dst = skb_dst(skb);
 	struct flowi fl;
 	int ret;
@@ -362,7 +360,7 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev)
 			dst = ip6_route_output(dev_net(dev), NULL, &fl.u.ip6);
 			if (dst->error) {
 				dst_release(dst);
-				stats->tx_carrier_errors++;
+				DEV_STATS_INC(dev, tx_carrier_errors);
 				goto tx_err;
 			}
 			skb_dst_set(skb, dst);
@@ -378,7 +376,7 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev)
 			fl.u.ip4.flowi4_flags |= FLOWI_FLAG_ANYSRC;
 			rt = __ip_route_output_key(dev_net(dev), &fl.u.ip4);
 			if (IS_ERR(rt)) {
-				stats->tx_carrier_errors++;
+				DEV_STATS_INC(dev, tx_carrier_errors);
 				goto tx_err;
 			}
 			skb_dst_set(skb, &rt->dst);
@@ -397,8 +395,8 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev)
 	return NETDEV_TX_OK;
 
 tx_err:
-	stats->tx_errors++;
-	stats->tx_dropped++;
+	DEV_STATS_INC(dev, tx_errors);
+	DEV_STATS_INC(dev, tx_dropped);
 	kfree_skb(skb);
 	return NETDEV_TX_OK;
 }
-- 
GitLab


From 8cd11a024745c863f67f1de369a84372d399a885 Mon Sep 17 00:00:00 2001
From: Ma Ke <make_ruc2021@163.com>
Date: Mon, 9 Oct 2023 09:13:37 +0800
Subject: [PATCH 232/298] net: ipv4: fix return value check in
 esp_remove_trailer

commit 513f61e2193350c7a345da98559b80f61aec4fa6 upstream.

In esp_remove_trailer(), to avoid an unexpected result returned by
pskb_trim, we should check the return value of pskb_trim().

Signed-off-by: Ma Ke <make_ruc2021@163.com>
Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/ipv4/esp4.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/net/ipv4/esp4.c b/net/ipv4/esp4.c
index 203569500b91..24cd5c9c7839 100644
--- a/net/ipv4/esp4.c
+++ b/net/ipv4/esp4.c
@@ -565,7 +565,9 @@ static inline int esp_remove_trailer(struct sk_buff *skb)
 		skb->csum = csum_block_sub(skb->csum, csumdiff,
 					   skb->len - trimlen);
 	}
-	pskb_trim(skb, skb->len - trimlen);
+	ret = pskb_trim(skb, skb->len - trimlen);
+	if (unlikely(ret))
+		return ret;
 
 	ret = nexthdr[1];
 
-- 
GitLab


From 2756641a204e791c12aad56e7992a5e5e9f09227 Mon Sep 17 00:00:00 2001
From: Ma Ke <make_ruc2021@163.com>
Date: Sat, 7 Oct 2023 08:59:53 +0800
Subject: [PATCH 233/298] net: ipv6: fix return value check in
 esp_remove_trailer

commit dad4e491e30b20f4dc615c9da65d2142d703b5c2 upstream.

In esp_remove_trailer(), to avoid an unexpected result returned by
pskb_trim, we should check the return value of pskb_trim().

Signed-off-by: Ma Ke <make_ruc2021@163.com>
Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/ipv6/esp6.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/net/ipv6/esp6.c b/net/ipv6/esp6.c
index d847ffbe9745..6529e46ad091 100644
--- a/net/ipv6/esp6.c
+++ b/net/ipv6/esp6.c
@@ -517,7 +517,9 @@ static inline int esp_remove_trailer(struct sk_buff *skb)
 		skb->csum = csum_block_sub(skb->csum, csumdiff,
 					   skb->len - trimlen);
 	}
-	pskb_trim(skb, skb->len - trimlen);
+	ret = pskb_trim(skb, skb->len - trimlen);
+	if (unlikely(ret))
+		return ret;
 
 	ret = nexthdr[1];
 
-- 
GitLab


From 160ad7ba7a706c19acff1db532c67c0cc02177ab Mon Sep 17 00:00:00 2001
From: Josua Mayer <josua@solid-run.com>
Date: Wed, 4 Oct 2023 18:39:28 +0200
Subject: [PATCH 234/298] net: rfkill: gpio: prevent value glitch during probe

commit b2f750c3a80b285cd60c9346f8c96bd0a2a66cde upstream.

When either reset- or shutdown-gpio have are initially deasserted,
e.g. after a reboot - or when the hardware does not include pull-down,
there will be a short toggle of both IOs to logical 0 and back to 1.

It seems that the rfkill default is unblocked, so the driver should not
glitch to output low during probe.
It can lead e.g. to unexpected lte modem reconnect:

[1] root@localhost:~# dmesg | grep "usb 2-1"
[    2.136124] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
[   21.215278] usb 2-1: USB disconnect, device number 2
[   28.833977] usb 2-1: new SuperSpeed USB device number 3 using xhci-hcd

The glitch has been discovered on an arm64 board, now that device-tree
support for the rfkill-gpio driver has finally appeared :).

Change the flags for devm_gpiod_get_optional from GPIOD_OUT_LOW to
GPIOD_ASIS to avoid any glitches.
The rfkill driver will set the intended value during rfkill_sync_work.

Fixes: 7176ba23f8b5 ("net: rfkill: add generic gpio rfkill driver")
Signed-off-by: Josua Mayer <josua@solid-run.com>
Link: https://lore.kernel.org/r/20231004163928.14609-1-josua@solid-run.com
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/rfkill/rfkill-gpio.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/net/rfkill/rfkill-gpio.c b/net/rfkill/rfkill-gpio.c
index 0f8465852254..af0842744fc8 100644
--- a/net/rfkill/rfkill-gpio.c
+++ b/net/rfkill/rfkill-gpio.c
@@ -112,13 +112,13 @@ static int rfkill_gpio_probe(struct platform_device *pdev)
 
 	rfkill->clk = devm_clk_get(&pdev->dev, NULL);
 
-	gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
+	gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_ASIS);
 	if (IS_ERR(gpio))
 		return PTR_ERR(gpio);
 
 	rfkill->reset_gpio = gpio;
 
-	gpio = devm_gpiod_get_optional(&pdev->dev, "shutdown", GPIOD_OUT_LOW);
+	gpio = devm_gpiod_get_optional(&pdev->dev, "shutdown", GPIOD_ASIS);
 	if (IS_ERR(gpio))
 		return PTR_ERR(gpio);
 
-- 
GitLab


From 6d022a7abf7278f5317bf3000e4ba5d8e55875dc Mon Sep 17 00:00:00 2001
From: Neal Cardwell <ncardwell@google.com>
Date: Sun, 15 Oct 2023 13:47:00 -0400
Subject: [PATCH 235/298] tcp: fix excessive TLP and RACK timeouts from HZ
 rounding

commit 1c2709cfff1dedbb9591e989e2f001484208d914 upstream.

We discovered from packet traces of slow loss recovery on kernels with
the default HZ=250 setting (and min_rtt < 1ms) that after reordering,
when receiving a SACKed sequence range, the RACK reordering timer was
firing after about 16ms rather than the desired value of roughly
min_rtt/4 + 2ms. The problem is largely due to the RACK reorder timer
calculation adding in TCP_TIMEOUT_MIN, which is 2 jiffies. On kernels
with HZ=250, this is 2*4ms = 8ms. The TLP timer calculation has the
exact same issue.

This commit fixes the TLP transmit timer and RACK reordering timer
floor calculation to more closely match the intended 2ms floor even on
kernels with HZ=250. It does this by adding in a new
TCP_TIMEOUT_MIN_US floor of 2000 us and then converting to jiffies,
instead of the current approach of converting to jiffies and then
adding th TCP_TIMEOUT_MIN value of 2 jiffies.

Our testing has verified that on kernels with HZ=1000, as expected,
this does not produce significant changes in behavior, but on kernels
with the default HZ=250 the latency improvement can be large. For
example, our tests show that for HZ=250 kernels at low RTTs this fix
roughly halves the latency for the RACK reorder timer: instead of
mostly firing at 16ms it mostly fires at 8ms.

Suggested-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: Neal Cardwell <ncardwell@google.com>
Signed-off-by: Yuchung Cheng <ycheng@google.com>
Fixes: bb4d991a28cc ("tcp: adjust tail loss probe timeout")
Reviewed-by: Eric Dumazet <edumazet@google.com>
Link: https://lore.kernel.org/r/20231015174700.2206872-1-ncardwell.sw@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 include/net/tcp.h       | 3 +++
 net/ipv4/tcp_output.c   | 9 +++++----
 net/ipv4/tcp_recovery.c | 2 +-
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/include/net/tcp.h b/include/net/tcp.h
index 427553adf82c..49da4d4a3c3d 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -141,6 +141,9 @@ void tcp_time_wait(struct sock *sk, int state, int timeo);
 #define TCP_RTO_MAX	((unsigned)(120*HZ))
 #define TCP_RTO_MIN	((unsigned)(HZ/5))
 #define TCP_TIMEOUT_MIN	(2U) /* Min timeout for TCP timers in jiffies */
+
+#define TCP_TIMEOUT_MIN_US (2*USEC_PER_MSEC) /* Min TCP timeout in microsecs */
+
 #define TCP_TIMEOUT_INIT ((unsigned)(1*HZ))	/* RFC6298 2.1 initial RTO value	*/
 #define TCP_TIMEOUT_FALLBACK ((unsigned)(3*HZ))	/* RFC 1122 initial RTO value, now
 						 * used as a fallback RTO for the
diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
index dcca9554071d..7c7f2d63a12f 100644
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -2449,7 +2449,7 @@ bool tcp_schedule_loss_probe(struct sock *sk, bool advancing_rto)
 {
 	struct inet_connection_sock *icsk = inet_csk(sk);
 	struct tcp_sock *tp = tcp_sk(sk);
-	u32 timeout, rto_delta_us;
+	u32 timeout, timeout_us, rto_delta_us;
 	int early_retrans;
 
 	/* Don't do any loss probe on a Fast Open connection before 3WHS
@@ -2473,11 +2473,12 @@ bool tcp_schedule_loss_probe(struct sock *sk, bool advancing_rto)
 	 * sample is available then probe after TCP_TIMEOUT_INIT.
 	 */
 	if (tp->srtt_us) {
-		timeout = usecs_to_jiffies(tp->srtt_us >> 2);
+		timeout_us = tp->srtt_us >> 2;
 		if (tp->packets_out == 1)
-			timeout += TCP_RTO_MIN;
+			timeout_us += tcp_rto_min_us(sk);
 		else
-			timeout += TCP_TIMEOUT_MIN;
+			timeout_us += TCP_TIMEOUT_MIN_US;
+		timeout = usecs_to_jiffies(timeout_us);
 	} else {
 		timeout = TCP_TIMEOUT_INIT;
 	}
diff --git a/net/ipv4/tcp_recovery.c b/net/ipv4/tcp_recovery.c
index 61969bb9395c..844ff390f726 100644
--- a/net/ipv4/tcp_recovery.c
+++ b/net/ipv4/tcp_recovery.c
@@ -122,7 +122,7 @@ bool tcp_rack_mark_lost(struct sock *sk)
 	tp->rack.advanced = 0;
 	tcp_rack_detect_loss(sk, &timeout);
 	if (timeout) {
-		timeout = usecs_to_jiffies(timeout) + TCP_TIMEOUT_MIN;
+		timeout = usecs_to_jiffies(timeout + TCP_TIMEOUT_MIN_US);
 		inet_csk_reset_xmit_timer(sk, ICSK_TIME_REO_TIMEOUT,
 					  timeout, inet_csk(sk)->icsk_rto);
 	}
-- 
GitLab


From e480bfcf5fec910730b7eae6984bd2ea33d7a4d7 Mon Sep 17 00:00:00 2001
From: Eric Dumazet <edumazet@google.com>
Date: Tue, 17 Oct 2023 12:45:26 +0000
Subject: [PATCH 236/298] tcp: tsq: relax tcp_small_queue_check() when rtx
 queue contains a single skb

commit f921a4a5bffa8a0005b190fb9421a7fc1fd716b6 upstream.

In commit 75eefc6c59fd ("tcp: tsq: add a shortcut in tcp_small_queue_check()")
we allowed to send an skb regardless of TSQ limits being hit if rtx queue
was empty or had a single skb, in order to better fill the pipe
when/if TX completions were slow.

Then later, commit 75c119afe14f ("tcp: implement rb-tree based
retransmit queue") accidentally removed the special case for
one skb in rtx queue.

Stefan Wahren reported a regression in single TCP flow throughput
using a 100Mbit fec link, starting from commit 65466904b015 ("tcp: adjust
TSO packet sizes based on min_rtt"). This last commit only made the
regression more visible, because it locked the TCP flow on a particular
behavior where TSQ prevented two skbs being pushed downstream,
adding silences on the wire between each TSO packet.

Many thanks to Stefan for his invaluable help !

Fixes: 75c119afe14f ("tcp: implement rb-tree based retransmit queue")
Link: https://lore.kernel.org/netdev/7f31ddc8-9971-495e-a1f6-819df542e0af@gmx.net/
Reported-by: Stefan Wahren <wahrenst@gmx.net>
Tested-by: Stefan Wahren <wahrenst@gmx.net>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Acked-by: Neal Cardwell <ncardwell@google.com>
Link: https://lore.kernel.org/r/20231017124526.4060202-1-edumazet@google.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/ipv4/tcp_output.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
index 7c7f2d63a12f..3dd62cf739e3 100644
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -2220,6 +2220,18 @@ static int tcp_mtu_probe(struct sock *sk)
 	return -1;
 }
 
+static bool tcp_rtx_queue_empty_or_single_skb(const struct sock *sk)
+{
+	const struct rb_node *node = sk->tcp_rtx_queue.rb_node;
+
+	/* No skb in the rtx queue. */
+	if (!node)
+		return true;
+
+	/* Only one skb in rtx queue. */
+	return !node->rb_left && !node->rb_right;
+}
+
 /* TCP Small Queues :
  * Control number of packets in qdisc/devices to two packets / or ~1 ms.
  * (These limits are doubled for retransmits)
@@ -2242,12 +2254,12 @@ static bool tcp_small_queue_check(struct sock *sk, const struct sk_buff *skb,
 	limit <<= factor;
 
 	if (refcount_read(&sk->sk_wmem_alloc) > limit) {
-		/* Always send skb if rtx queue is empty.
+		/* Always send skb if rtx queue is empty or has one skb.
 		 * No need to wait for TX completion to call us back,
 		 * after softirq/tasklet schedule.
 		 * This helps when TX completions are delayed too much.
 		 */
-		if (tcp_rtx_queue_empty(sk))
+		if (tcp_rtx_queue_empty_or_single_skb(sk))
 			return false;
 
 		set_bit(TSQ_THROTTLED, &sk->sk_tsq_flags);
-- 
GitLab


From db6f0d5d807357d3ae0ed0062605b87ff3f48e5a Mon Sep 17 00:00:00 2001
From: Dan Carpenter <dan.carpenter@linaro.org>
Date: Mon, 16 Oct 2023 20:28:10 +0300
Subject: [PATCH 237/298] net: usb: smsc95xx: Fix an error code in
 smsc95xx_reset()

commit c53647a5df9e66dd9fedf240198e1fe50d88c286 upstream.

Return a negative error code instead of success.

Fixes: 2f7ca802bdae ("net: Add SMSC LAN9500 USB2.0 10/100 ethernet adapter driver")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://lore.kernel.org/r/147927f0-9ada-45cc-81ff-75a19dd30b76@moroto.mountain
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/net/usb/smsc95xx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/usb/smsc95xx.c b/drivers/net/usb/smsc95xx.c
index 085048686413..37547ac72840 100644
--- a/drivers/net/usb/smsc95xx.c
+++ b/drivers/net/usb/smsc95xx.c
@@ -1054,7 +1054,7 @@ static int smsc95xx_reset(struct usbnet *dev)
 
 	if (timeout >= 100) {
 		netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n");
-		return ret;
+		return -ETIMEDOUT;
 	}
 
 	ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_);
-- 
GitLab


From 1f1f8702d73dc65d92ab53c74be0355b237ad067 Mon Sep 17 00:00:00 2001
From: Michal Schmidt <mschmidt@redhat.com>
Date: Wed, 11 Oct 2023 16:33:32 -0700
Subject: [PATCH 238/298] i40e: prevent crash on probe if hw registers have
 invalid values

commit fc6f716a5069180c40a8c9b63631e97da34f64a3 upstream.

The hardware provides the indexes of the first and the last available
queue and VF. From the indexes, the driver calculates the numbers of
queues and VFs. In theory, a faulty device might say the last index is
smaller than the first index. In that case, the driver's calculation
would underflow, it would attempt to write to non-existent registers
outside of the ioremapped range and crash.

I ran into this not by having a faulty device, but by an operator error.
I accidentally ran a QE test meant for i40e devices on an ice device.
The test used 'echo i40e > /sys/...ice PCI device.../driver_override',
bound the driver to the device and crashed in one of the wr32 calls in
i40e_clear_hw.

Add checks to prevent underflows in the calculations of num_queues and
num_vfs. With this fix, the wrong device probing reports errors and
returns a failure without crashing.

Fixes: 838d41d92a90 ("i40e: clear all queues and interrupts")
Signed-off-by: Michal Schmidt <mschmidt@redhat.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
Link: https://lore.kernel.org/r/20231011233334.336092-2-jacob.e.keller@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/net/ethernet/intel/i40e/i40e_common.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c
index e75b4c4872c0..95cd3c35b003 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_common.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c
@@ -1332,7 +1332,7 @@ void i40e_clear_hw(struct i40e_hw *hw)
 		     I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
 	j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
 	    I40E_PFLAN_QALLOC_LASTQ_SHIFT;
-	if (val & I40E_PFLAN_QALLOC_VALID_MASK)
+	if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue)
 		num_queues = (j - base_queue) + 1;
 	else
 		num_queues = 0;
@@ -1342,7 +1342,7 @@ void i40e_clear_hw(struct i40e_hw *hw)
 	    I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
 	j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
 	    I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
-	if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
+	if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i)
 		num_vfs = (j - i) + 1;
 	else
 		num_vfs = 0;
-- 
GitLab


From a39a303c06dffaf851e418d814808f5eae669de2 Mon Sep 17 00:00:00 2001
From: Pedro Tammela <pctammela@mojatatu.com>
Date: Tue, 17 Oct 2023 11:36:02 -0300
Subject: [PATCH 239/298] net/sched: sch_hfsc: upgrade 'rt' to 'sc' when it
 becomes a inner curve

commit a13b67c9a015c4e21601ef9aa4ec9c5d972df1b4 upstream.

Christian Theune says:
   I upgraded from 6.1.38 to 6.1.55 this morning and it broke my traffic shaping script,
   leaving me with a non-functional uplink on a remote router.

A 'rt' curve cannot be used as a inner curve (parent class), but we were
allowing such configurations since the qdisc was introduced. Such
configurations would trigger a UAF as Budimir explains:
   The parent will have vttree_insert() called on it in init_vf(),
   but will not have vttree_remove() called on it in update_vf()
   because it does not have the HFSC_FSC flag set.

The qdisc always assumes that inner classes have the HFSC_FSC flag set.
This is by design as it doesn't make sense 'qdisc wise' for an 'rt'
curve to be an inner curve.

Budimir's original patch disallows users to add classes with a 'rt'
parent, but this is too strict as it breaks users that have been using
'rt' as a inner class. Another approach, taken by this patch, is to
upgrade the inner 'rt' into a 'sc', warning the user in the process.
It avoids the UAF reported by Budimir while also being more permissive
to bad scripts/users/code using 'rt' as a inner class.

Users checking the `tc class ls [...]` or `tc class get [...]` dumps would
observe the curve change and are potentially breaking with this change.

v1->v2: https://lore.kernel.org/all/20231013151057.2611860-1-pctammela@mojatatu.com/
- Correct 'Fixes' tag and merge with revert (Jakub)

Cc: Christian Theune <ct@flyingcircus.io>
Cc: Budimir Markovic <markovicbudimir@gmail.com>
Fixes: b3d26c5702c7 ("net/sched: sch_hfsc: Ensure inner classes have fsc curve")
Signed-off-by: Pedro Tammela <pctammela@mojatatu.com>
Acked-by: Jamal Hadi Salim <jhs@mojatatu.com>
Link: https://lore.kernel.org/r/20231017143602.3191556-1-pctammela@mojatatu.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/sched/sch_hfsc.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/net/sched/sch_hfsc.c b/net/sched/sch_hfsc.c
index fa3d2fd4990c..e71443623d67 100644
--- a/net/sched/sch_hfsc.c
+++ b/net/sched/sch_hfsc.c
@@ -913,6 +913,14 @@ hfsc_change_usc(struct hfsc_class *cl, struct tc_service_curve *usc,
 	cl->cl_flags |= HFSC_USC;
 }
 
+static void
+hfsc_upgrade_rt(struct hfsc_class *cl)
+{
+	cl->cl_fsc = cl->cl_rsc;
+	rtsc_init(&cl->cl_virtual, &cl->cl_fsc, cl->cl_vt, cl->cl_total);
+	cl->cl_flags |= HFSC_FSC;
+}
+
 static const struct nla_policy hfsc_policy[TCA_HFSC_MAX + 1] = {
 	[TCA_HFSC_RSC]	= { .len = sizeof(struct tc_service_curve) },
 	[TCA_HFSC_FSC]	= { .len = sizeof(struct tc_service_curve) },
@@ -1021,10 +1029,6 @@ hfsc_change_class(struct Qdisc *sch, u32 classid, u32 parentid,
 		if (parent == NULL)
 			return -ENOENT;
 	}
-	if (!(parent->cl_flags & HFSC_FSC) && parent != &q->root) {
-		NL_SET_ERR_MSG(extack, "Invalid parent - parent class must have FSC");
-		return -EINVAL;
-	}
 
 	if (classid == 0 || TC_H_MAJ(classid ^ sch->handle) != 0)
 		return -EINVAL;
@@ -1077,6 +1081,12 @@ hfsc_change_class(struct Qdisc *sch, u32 classid, u32 parentid,
 	cl->cf_tree = RB_ROOT;
 
 	sch_tree_lock(sch);
+	/* Check if the inner class is a misconfigured 'rt' */
+	if (!(parent->cl_flags & HFSC_FSC) && parent != &q->root) {
+		NL_SET_ERR_MSG(extack,
+			       "Forced curve change on parent 'rt' to 'sc'");
+		hfsc_upgrade_rt(parent);
+	}
 	qdisc_class_hash_insert(&q->clhash, &cl->cl_common);
 	list_add_tail(&cl->siblings, &parent->children);
 	if (parent->level == 0)
-- 
GitLab


From 7ee82e80c2a6814168000927ec01876b89e46b0f Mon Sep 17 00:00:00 2001
From: Pablo Neira Ayuso <pablo@netfilter.org>
Date: Tue, 17 Oct 2023 12:28:27 +0200
Subject: [PATCH 240/298] netfilter: nft_set_rbtree: .deactivate fails if
 element has expired

commit d111692a59c1470ae530cbb39bcf0346c950ecc7 upstream.

This allows to remove an expired element which is not possible in other
existing set backends, this is more noticeable if gc-interval is high so
expired elements remain in the tree. On-demand gc also does not help in
this case, because this is delete element path. Return NULL if element
has expired.

Fixes: 8d8540c4f5e0 ("netfilter: nft_set_rbtree: add timeout support")
Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
Signed-off-by: Florian Westphal <fw@strlen.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/netfilter/nft_set_rbtree.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/net/netfilter/nft_set_rbtree.c b/net/netfilter/nft_set_rbtree.c
index 78a0f4283787..9c7ec2ec1fcf 100644
--- a/net/netfilter/nft_set_rbtree.c
+++ b/net/netfilter/nft_set_rbtree.c
@@ -326,6 +326,8 @@ static void *nft_rbtree_deactivate(const struct net *net,
 				   nft_rbtree_interval_end(this)) {
 				parent = parent->rb_right;
 				continue;
+			} else if (nft_set_elem_expired(&rbe->ext)) {
+				break;
 			} else if (!nft_set_elem_active(&rbe->ext, genmask)) {
 				parent = parent->rb_left;
 				continue;
-- 
GitLab


From fb74be5e99f7780518b4c0fa50e21d0e9fb90640 Mon Sep 17 00:00:00 2001
From: Gavrilov Ilia <Ilia.Gavrilov@infotecs.ru>
Date: Mon, 16 Oct 2023 14:08:59 +0000
Subject: [PATCH 241/298] net: pktgen: Fix interface flags printing

commit 1d30162f35c7a73fc2f8cdcdcdbd690bedb99d1a upstream.

Device flags are displayed incorrectly:
1) The comparison (i == F_FLOW_SEQ) is always false, because F_FLOW_SEQ
is equal to (1 << FLOW_SEQ_SHIFT) == 2048, and the maximum value
of the 'i' variable is (NR_PKT_FLAG - 1) == 17. It should be compared
with FLOW_SEQ_SHIFT.

2) Similarly to the F_IPSEC flag.

3) Also add spaces to the print end of the string literal "spi:%u"
to prevent the output from merging with the flag that follows.

Found by InfoTeCS on behalf of Linux Verification Center
(linuxtesting.org) with SVACE.

Fixes: 99c6d3d20d62 ("pktgen: Remove brute-force printing of flags")
Signed-off-by: Gavrilov Ilia <Ilia.Gavrilov@infotecs.ru>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/core/pktgen.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/net/core/pktgen.c b/net/core/pktgen.c
index 3714cd9e3111..3ade60ec4512 100644
--- a/net/core/pktgen.c
+++ b/net/core/pktgen.c
@@ -651,19 +651,19 @@ static int pktgen_if_show(struct seq_file *seq, void *v)
 	seq_puts(seq, "     Flags: ");
 
 	for (i = 0; i < NR_PKT_FLAGS; i++) {
-		if (i == F_FLOW_SEQ)
+		if (i == FLOW_SEQ_SHIFT)
 			if (!pkt_dev->cflows)
 				continue;
 
-		if (pkt_dev->flags & (1 << i))
+		if (pkt_dev->flags & (1 << i)) {
 			seq_printf(seq, "%s  ", pkt_flag_names[i]);
-		else if (i == F_FLOW_SEQ)
-			seq_puts(seq, "FLOW_RND  ");
-
 #ifdef CONFIG_XFRM
-		if (i == F_IPSEC && pkt_dev->spi)
-			seq_printf(seq, "spi:%u", pkt_dev->spi);
+			if (i == IPSEC_SHIFT && pkt_dev->spi)
+				seq_printf(seq, "spi:%u  ", pkt_dev->spi);
 #endif
+		} else if (i == FLOW_SEQ_SHIFT) {
+			seq_puts(seq, "FLOW_RND  ");
+		}
 	}
 
 	seq_puts(seq, "\n");
-- 
GitLab


From 8d7eef327b9faaea7254e0d514576de128c86ab1 Mon Sep 17 00:00:00 2001
From: Jeff Layton <jlayton@kernel.org>
Date: Mon, 6 May 2019 09:38:46 -0400
Subject: [PATCH 242/298] libceph: fix unaligned accesses in ceph_entity_addr
 handling

[ Upstream commit cede185b1ba3118e1912385db4812a37d9e9b205 ]

GCC9 is throwing a lot of warnings about unaligned access. This patch
fixes some of them by changing most of the sockaddr handling functions
to take a pointer to struct ceph_entity_addr instead of struct
sockaddr_storage.  The lower functions can then make copies or do
unaligned accesses as needed.

Signed-off-by: Jeff Layton <jlayton@kernel.org>
Reviewed-by: Ilya Dryomov <idryomov@gmail.com>
Signed-off-by: Ilya Dryomov <idryomov@gmail.com>
Stable-dep-of: 7563cf17dce0 ("libceph: use kernel_connect()")
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/ceph/messenger.c | 77 +++++++++++++++++++++-----------------------
 1 file changed, 37 insertions(+), 40 deletions(-)

diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c
index 21bd37ec5511..53ab8fc713a3 100644
--- a/net/ceph/messenger.c
+++ b/net/ceph/messenger.c
@@ -462,7 +462,7 @@ static void set_sock_callbacks(struct socket *sock,
  */
 static int ceph_tcp_connect(struct ceph_connection *con)
 {
-	struct sockaddr_storage *paddr = &con->peer_addr.in_addr;
+	struct sockaddr_storage ss = con->peer_addr.in_addr; /* align */
 	struct socket *sock;
 	unsigned int noio_flag;
 	int ret;
@@ -471,7 +471,7 @@ static int ceph_tcp_connect(struct ceph_connection *con)
 
 	/* sock_create_kern() allocates with GFP_KERNEL */
 	noio_flag = memalloc_noio_save();
-	ret = sock_create_kern(read_pnet(&con->msgr->net), paddr->ss_family,
+	ret = sock_create_kern(read_pnet(&con->msgr->net), ss.ss_family,
 			       SOCK_STREAM, IPPROTO_TCP, &sock);
 	memalloc_noio_restore(noio_flag);
 	if (ret)
@@ -487,7 +487,7 @@ static int ceph_tcp_connect(struct ceph_connection *con)
 	dout("connect %s\n", ceph_pr_addr(&con->peer_addr.in_addr));
 
 	con_sock_state_connecting(con);
-	ret = sock->ops->connect(sock, (struct sockaddr *)paddr, sizeof(*paddr),
+	ret = sock->ops->connect(sock, (struct sockaddr *)&ss, sizeof(ss),
 				 O_NONBLOCK);
 	if (ret == -EINPROGRESS) {
 		dout("connect %s EINPROGRESS sk_state = %u\n",
@@ -1824,14 +1824,15 @@ static int verify_hello(struct ceph_connection *con)
 	return 0;
 }
 
-static bool addr_is_blank(struct sockaddr_storage *ss)
+static bool addr_is_blank(struct ceph_entity_addr *addr)
 {
-	struct in_addr *addr = &((struct sockaddr_in *)ss)->sin_addr;
-	struct in6_addr *addr6 = &((struct sockaddr_in6 *)ss)->sin6_addr;
+	struct sockaddr_storage ss = addr->in_addr; /* align */
+	struct in_addr *addr4 = &((struct sockaddr_in *)&ss)->sin_addr;
+	struct in6_addr *addr6 = &((struct sockaddr_in6 *)&ss)->sin6_addr;
 
-	switch (ss->ss_family) {
+	switch (ss.ss_family) {
 	case AF_INET:
-		return addr->s_addr == htonl(INADDR_ANY);
+		return addr4->s_addr == htonl(INADDR_ANY);
 	case AF_INET6:
 		return ipv6_addr_any(addr6);
 	default:
@@ -1839,25 +1840,25 @@ static bool addr_is_blank(struct sockaddr_storage *ss)
 	}
 }
 
-static int addr_port(struct sockaddr_storage *ss)
+static int addr_port(struct ceph_entity_addr *addr)
 {
-	switch (ss->ss_family) {
+	switch (get_unaligned(&addr->in_addr.ss_family)) {
 	case AF_INET:
-		return ntohs(((struct sockaddr_in *)ss)->sin_port);
+		return ntohs(get_unaligned(&((struct sockaddr_in *)&addr->in_addr)->sin_port));
 	case AF_INET6:
-		return ntohs(((struct sockaddr_in6 *)ss)->sin6_port);
+		return ntohs(get_unaligned(&((struct sockaddr_in6 *)&addr->in_addr)->sin6_port));
 	}
 	return 0;
 }
 
-static void addr_set_port(struct sockaddr_storage *ss, int p)
+static void addr_set_port(struct ceph_entity_addr *addr, int p)
 {
-	switch (ss->ss_family) {
+	switch (get_unaligned(&addr->in_addr.ss_family)) {
 	case AF_INET:
-		((struct sockaddr_in *)ss)->sin_port = htons(p);
+		put_unaligned(htons(p), &((struct sockaddr_in *)&addr->in_addr)->sin_port);
 		break;
 	case AF_INET6:
-		((struct sockaddr_in6 *)ss)->sin6_port = htons(p);
+		put_unaligned(htons(p), &((struct sockaddr_in6 *)&addr->in_addr)->sin6_port);
 		break;
 	}
 }
@@ -1865,21 +1866,18 @@ static void addr_set_port(struct sockaddr_storage *ss, int p)
 /*
  * Unlike other *_pton function semantics, zero indicates success.
  */
-static int ceph_pton(const char *str, size_t len, struct sockaddr_storage *ss,
+static int ceph_pton(const char *str, size_t len, struct ceph_entity_addr *addr,
 		char delim, const char **ipend)
 {
-	struct sockaddr_in *in4 = (struct sockaddr_in *) ss;
-	struct sockaddr_in6 *in6 = (struct sockaddr_in6 *) ss;
-
-	memset(ss, 0, sizeof(*ss));
+	memset(&addr->in_addr, 0, sizeof(addr->in_addr));
 
-	if (in4_pton(str, len, (u8 *)&in4->sin_addr.s_addr, delim, ipend)) {
-		ss->ss_family = AF_INET;
+	if (in4_pton(str, len, (u8 *)&((struct sockaddr_in *)&addr->in_addr)->sin_addr.s_addr, delim, ipend)) {
+		put_unaligned(AF_INET, &addr->in_addr.ss_family);
 		return 0;
 	}
 
-	if (in6_pton(str, len, (u8 *)&in6->sin6_addr.s6_addr, delim, ipend)) {
-		ss->ss_family = AF_INET6;
+	if (in6_pton(str, len, (u8 *)&((struct sockaddr_in6 *)&addr->in_addr)->sin6_addr.s6_addr, delim, ipend)) {
+		put_unaligned(AF_INET6, &addr->in_addr.ss_family);
 		return 0;
 	}
 
@@ -1891,7 +1889,7 @@ static int ceph_pton(const char *str, size_t len, struct sockaddr_storage *ss,
  */
 #ifdef CONFIG_CEPH_LIB_USE_DNS_RESOLVER
 static int ceph_dns_resolve_name(const char *name, size_t namelen,
-		struct sockaddr_storage *ss, char delim, const char **ipend)
+		struct ceph_entity_addr *addr, char delim, const char **ipend)
 {
 	const char *end, *delim_p;
 	char *colon_p, *ip_addr = NULL;
@@ -1920,7 +1918,7 @@ static int ceph_dns_resolve_name(const char *name, size_t namelen,
 	/* do dns_resolve upcall */
 	ip_len = dns_query(NULL, name, end - name, NULL, &ip_addr, NULL);
 	if (ip_len > 0)
-		ret = ceph_pton(ip_addr, ip_len, ss, -1, NULL);
+		ret = ceph_pton(ip_addr, ip_len, addr, -1, NULL);
 	else
 		ret = -ESRCH;
 
@@ -1929,13 +1927,13 @@ static int ceph_dns_resolve_name(const char *name, size_t namelen,
 	*ipend = end;
 
 	pr_info("resolve '%.*s' (ret=%d): %s\n", (int)(end - name), name,
-			ret, ret ? "failed" : ceph_pr_addr(ss));
+			ret, ret ? "failed" : ceph_pr_addr(&addr->in_addr));
 
 	return ret;
 }
 #else
 static inline int ceph_dns_resolve_name(const char *name, size_t namelen,
-		struct sockaddr_storage *ss, char delim, const char **ipend)
+		struct ceph_entity_addr *addr, char delim, const char **ipend)
 {
 	return -EINVAL;
 }
@@ -1946,13 +1944,13 @@ static inline int ceph_dns_resolve_name(const char *name, size_t namelen,
  * then try to extract a hostname to resolve using userspace DNS upcall.
  */
 static int ceph_parse_server_name(const char *name, size_t namelen,
-			struct sockaddr_storage *ss, char delim, const char **ipend)
+		struct ceph_entity_addr *addr, char delim, const char **ipend)
 {
 	int ret;
 
-	ret = ceph_pton(name, namelen, ss, delim, ipend);
+	ret = ceph_pton(name, namelen, addr, delim, ipend);
 	if (ret)
-		ret = ceph_dns_resolve_name(name, namelen, ss, delim, ipend);
+		ret = ceph_dns_resolve_name(name, namelen, addr, delim, ipend);
 
 	return ret;
 }
@@ -1971,7 +1969,6 @@ int ceph_parse_ips(const char *c, const char *end,
 	dout("parse_ips on '%.*s'\n", (int)(end-c), c);
 	for (i = 0; i < max_count; i++) {
 		const char *ipend;
-		struct sockaddr_storage *ss = &addr[i].in_addr;
 		int port;
 		char delim = ',';
 
@@ -1980,7 +1977,7 @@ int ceph_parse_ips(const char *c, const char *end,
 			p++;
 		}
 
-		ret = ceph_parse_server_name(p, end - p, ss, delim, &ipend);
+		ret = ceph_parse_server_name(p, end - p, &addr[i], delim, &ipend);
 		if (ret)
 			goto bad;
 		ret = -EINVAL;
@@ -2011,9 +2008,9 @@ int ceph_parse_ips(const char *c, const char *end,
 			port = CEPH_MON_PORT;
 		}
 
-		addr_set_port(ss, port);
+		addr_set_port(&addr[i], port);
 
-		dout("parse_ips got %s\n", ceph_pr_addr(ss));
+		dout("parse_ips got %s\n", ceph_pr_addr(&addr[i].in_addr));
 
 		if (p == end)
 			break;
@@ -2052,7 +2049,7 @@ static int process_banner(struct ceph_connection *con)
 	 */
 	if (memcmp(&con->peer_addr, &con->actual_peer_addr,
 		   sizeof(con->peer_addr)) != 0 &&
-	    !(addr_is_blank(&con->actual_peer_addr.in_addr) &&
+	    !(addr_is_blank(&con->actual_peer_addr) &&
 	      con->actual_peer_addr.nonce == con->peer_addr.nonce)) {
 		pr_warn("wrong peer, want %s/%d, got %s/%d\n",
 			ceph_pr_addr(&con->peer_addr.in_addr),
@@ -2066,13 +2063,13 @@ static int process_banner(struct ceph_connection *con)
 	/*
 	 * did we learn our address?
 	 */
-	if (addr_is_blank(&con->msgr->inst.addr.in_addr)) {
-		int port = addr_port(&con->msgr->inst.addr.in_addr);
+	if (addr_is_blank(&con->msgr->inst.addr)) {
+		int port = addr_port(&con->msgr->inst.addr);
 
 		memcpy(&con->msgr->inst.addr.in_addr,
 		       &con->peer_addr_for_me.in_addr,
 		       sizeof(con->peer_addr_for_me.in_addr));
-		addr_set_port(&con->msgr->inst.addr.in_addr, port);
+		addr_set_port(&con->msgr->inst.addr, port);
 		encode_my_addr(con->msgr);
 		dout("process_banner learned my addr is %s\n",
 		     ceph_pr_addr(&con->msgr->inst.addr.in_addr));
-- 
GitLab


From 476589a280e2ecffd68e5e7116ec847eea89e5c5 Mon Sep 17 00:00:00 2001
From: Jordan Rife <jrife@google.com>
Date: Wed, 4 Oct 2023 18:38:27 -0500
Subject: [PATCH 243/298] libceph: use kernel_connect()

[ Upstream commit 7563cf17dce0a875ba3d872acdc63a78ea344019 ]

Direct calls to ops->connect() can overwrite the address parameter when
used in conjunction with BPF SOCK_ADDR hooks. Recent changes to
kernel_connect() ensure that callers are insulated from such side
effects. This patch wraps the direct call to ops->connect() with
kernel_connect() to prevent unexpected changes to the address passed to
ceph_tcp_connect().

This change was originally part of a larger patch targeting the net tree
addressing all instances of unprotected calls to ops->connect()
throughout the kernel, but this change was split up into several patches
targeting various trees.

Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/netdev/20230821100007.559638-1-jrife@google.com/
Link: https://lore.kernel.org/netdev/9944248dba1bce861375fcce9de663934d933ba9.camel@redhat.com/
Fixes: d74bad4e74ee ("bpf: Hooks for sys_connect")
Signed-off-by: Jordan Rife <jrife@google.com>
Reviewed-by: Ilya Dryomov <idryomov@gmail.com>
Signed-off-by: Ilya Dryomov <idryomov@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/ceph/messenger.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c
index 53ab8fc713a3..7fd18e10755e 100644
--- a/net/ceph/messenger.c
+++ b/net/ceph/messenger.c
@@ -487,8 +487,8 @@ static int ceph_tcp_connect(struct ceph_connection *con)
 	dout("connect %s\n", ceph_pr_addr(&con->peer_addr.in_addr));
 
 	con_sock_state_connecting(con);
-	ret = sock->ops->connect(sock, (struct sockaddr *)&ss, sizeof(ss),
-				 O_NONBLOCK);
+	ret = kernel_connect(sock, (struct sockaddr *)&ss, sizeof(ss),
+			     O_NONBLOCK);
 	if (ret == -EINPROGRESS) {
 		dout("connect %s EINPROGRESS sk_state = %u\n",
 		     ceph_pr_addr(&con->peer_addr.in_addr),
-- 
GitLab


From deae6fa1eaef9bbd852c4c6b15cec457dd91cf9b Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Mon, 11 Sep 2023 07:07:38 +0300
Subject: [PATCH 244/298] ARM: dts: ti: omap: Fix noisy serial with
 overrun-throttle-ms for mapphone

[ Upstream commit 5ad37b5e30433afa7a5513e3eb61f69fa0976785 ]

On mapphone devices we may get lots of noise on the micro-USB port in debug
uart mode until the phy-cpcap-usb driver probes. Let's limit the noise by
using overrun-throttle-ms.

Note that there is also a related separate issue where the charger cable
connected may cause random sysrq requests until phy-cpcap-usb probes that
still remains.

Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Cc: Carl Philipp Klemm <philipp@uvos.xyz>
Cc: Merlijn Wajer <merlijn@wizzup.org>
Cc: Pavel Machek <pavel@ucw.cz>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 arch/arm/boot/dts/omap4-droid4-xt894.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
index 459720f5f558..91c8a05ab67a 100644
--- a/arch/arm/boot/dts/omap4-droid4-xt894.dts
+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
@@ -669,6 +669,7 @@
 &uart3 {
 	interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
 			       &omap4_pmx_core 0x17c>;
+	overrun-throttle-ms = <500>;
 };
 
 &uart4 {
-- 
GitLab


From 7cfa71318cecc3af064341d84931aaa95d97c4f2 Mon Sep 17 00:00:00 2001
From: Filipe Manana <fdmanana@suse.com>
Date: Fri, 8 Sep 2023 18:20:23 +0100
Subject: [PATCH 245/298] btrfs: return -EUCLEAN for delayed tree ref with a
 ref count not equals to 1

[ Upstream commit 1bf76df3fee56d6637718e267f7c34ed70d0c7dc ]

When running a delayed tree reference, if we find a ref count different
from 1, we return -EIO. This isn't an IO error, as it indicates either a
bug in the delayed refs code or a memory corruption, so change the error
code from -EIO to -EUCLEAN. Also tag the branch as 'unlikely' as this is
not expected to ever happen, and change the error message to print the
tree block's bytenr without the parenthesis (and there was a missing space
between the 'block' word and the opening parenthesis), for consistency as
that's the style we used everywhere else.

Reviewed-by: Josef Bacik <josef@toxicpanda.com>
Signed-off-by: Filipe Manana <fdmanana@suse.com>
Reviewed-by: David Sterba <dsterba@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 fs/btrfs/extent-tree.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c
index bb05b0a82c8b..902ab00bfd7a 100644
--- a/fs/btrfs/extent-tree.c
+++ b/fs/btrfs/extent-tree.c
@@ -2327,12 +2327,12 @@ static int run_delayed_tree_ref(struct btrfs_trans_handle *trans,
 		parent = ref->parent;
 	ref_root = ref->root;
 
-	if (node->ref_mod != 1) {
+	if (unlikely(node->ref_mod != 1)) {
 		btrfs_err(trans->fs_info,
-	"btree block(%llu) has %d references rather than 1: action %d ref_root %llu parent %llu",
+	"btree block %llu has %d references rather than 1: action %d ref_root %llu parent %llu",
 			  node->bytenr, node->ref_mod, node->action, ref_root,
 			  parent);
-		return -EIO;
+		return -EUCLEAN;
 	}
 	if (node->action == BTRFS_ADD_DELAYED_REF && insert_reserved) {
 		BUG_ON(!extent_op || !extent_op->update_flags);
-- 
GitLab


From c2088392ac058bd9be3b339ab3beb4c65b7308a6 Mon Sep 17 00:00:00 2001
From: Josef Bacik <josef@toxicpanda.com>
Date: Tue, 5 Sep 2023 12:15:24 -0400
Subject: [PATCH 246/298] btrfs: initialize start_slot in
 btrfs_log_prealloc_extents
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

[ Upstream commit b4c639f699349880b7918b861e1bd360442ec450 ]

Jens reported a compiler warning when using
CONFIG_CC_OPTIMIZE_FOR_SIZE=y that looks like this

  fs/btrfs/tree-log.c: In function ‘btrfs_log_prealloc_extents’:
  fs/btrfs/tree-log.c:4828:23: warning: ‘start_slot’ may be used
  uninitialized [-Wmaybe-uninitialized]
   4828 |                 ret = copy_items(trans, inode, dst_path, path,
	|                       ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   4829 |                                  start_slot, ins_nr, 1, 0);
	|                                  ~~~~~~~~~~~~~~~~~~~~~~~~~
  fs/btrfs/tree-log.c:4725:13: note: ‘start_slot’ was declared here
   4725 |         int start_slot;
	|             ^~~~~~~~~~

The compiler is incorrect, as we only use this code when ins_len > 0,
and when ins_len > 0 we have start_slot properly initialized.  However
we generally find the -Wmaybe-uninitialized warnings valuable, so
initialize start_slot to get rid of the warning.

Reported-by: Jens Axboe <axboe@kernel.dk>
Tested-by: Jens Axboe <axboe@kernel.dk>
Signed-off-by: Josef Bacik <josef@toxicpanda.com>
Reviewed-by: David Sterba <dsterba@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 fs/btrfs/tree-log.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/btrfs/tree-log.c b/fs/btrfs/tree-log.c
index 0fe32c567ed7..23ec766eeb0a 100644
--- a/fs/btrfs/tree-log.c
+++ b/fs/btrfs/tree-log.c
@@ -4236,7 +4236,7 @@ static int btrfs_log_prealloc_extents(struct btrfs_trans_handle *trans,
 	struct extent_buffer *leaf;
 	int slot;
 	int ins_nr = 0;
-	int start_slot;
+	int start_slot = 0;
 	int ret;
 
 	if (!(inode->flags & BTRFS_INODE_PREALLOC))
-- 
GitLab


From f65bed0696f7046c800a708d956a16192534bcec Mon Sep 17 00:00:00 2001
From: Heiner Kallweit <hkallweit1@gmail.com>
Date: Sat, 23 Sep 2023 23:54:06 +0200
Subject: [PATCH 247/298] i2c: mux: Avoid potential false error message in
 i2c_mux_add_adapter

[ Upstream commit b13e59e74ff71a1004e0508107e91e9a84fd7388 ]

I2C_CLASS_DEPRECATED is a flag and not an actual class.
There's nothing speaking against both, parent and child, having
I2C_CLASS_DEPRECATED set. Therefore exclude it from the check.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Acked-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/i2c/i2c-mux.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c
index f330690b4125..83a79bcb71ea 100644
--- a/drivers/i2c/i2c-mux.c
+++ b/drivers/i2c/i2c-mux.c
@@ -334,7 +334,7 @@ int i2c_mux_add_adapter(struct i2c_mux_core *muxc,
 		priv->adap.lock_ops = &i2c_parent_lock_ops;
 
 	/* Sanity check on class */
-	if (i2c_mux_parent_classes(parent) & class)
+	if (i2c_mux_parent_classes(parent) & class & ~I2C_CLASS_DEPRECATED)
 		dev_err(&parent->dev,
 			"Segment %d behind mux can't share classes with ancestors\n",
 			chan_id);
-- 
GitLab


From 55fabed6352309cb71e0c76814f1f7023250ebf0 Mon Sep 17 00:00:00 2001
From: Jeff Layton <jlayton@kernel.org>
Date: Wed, 13 Sep 2023 09:33:12 -0400
Subject: [PATCH 248/298] overlayfs: set ctime when setting mtime and atime

[ Upstream commit 03dbab3bba5f009d053635c729d1244f2c8bad38 ]

Nathan reported that he was seeing the new warning in
setattr_copy_mgtime pop when starting podman containers. Overlayfs is
trying to set the atime and mtime via notify_change without also
setting the ctime.

POSIX states that when the atime and mtime are updated via utimes() that
we must also update the ctime to the current time. The situation with
overlayfs copy-up is analogies, so add ATTR_CTIME to the bitmask.
notify_change will fill in the value.

Reported-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Jeff Layton <jlayton@kernel.org>
Tested-by: Nathan Chancellor <nathan@kernel.org>
Acked-by: Christian Brauner <brauner@kernel.org>
Acked-by: Amir Goldstein <amir73il@gmail.com>
Message-Id: <20230913-ctime-v1-1-c6bc509cbc27@kernel.org>
Signed-off-by: Christian Brauner <brauner@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 fs/overlayfs/copy_up.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/overlayfs/copy_up.c b/fs/overlayfs/copy_up.c
index 3d7a700350c1..debcac35a51d 100644
--- a/fs/overlayfs/copy_up.c
+++ b/fs/overlayfs/copy_up.c
@@ -195,7 +195,7 @@ static int ovl_set_timestamps(struct dentry *upperdentry, struct kstat *stat)
 {
 	struct iattr attr = {
 		.ia_valid =
-		     ATTR_ATIME | ATTR_MTIME | ATTR_ATIME_SET | ATTR_MTIME_SET,
+		     ATTR_ATIME | ATTR_MTIME | ATTR_ATIME_SET | ATTR_MTIME_SET | ATTR_CTIME,
 		.ia_atime = stat->atime,
 		.ia_mtime = stat->mtime,
 	};
-- 
GitLab


From 640ec4ff29a687e8bee3bb4a4e5d6567ac1b2d11 Mon Sep 17 00:00:00 2001
From: Chengfeng Ye <dg573847474@gmail.com>
Date: Tue, 26 Sep 2023 10:29:14 +0000
Subject: [PATCH 249/298] gpio: timberdale: Fix potential deadlock on
 &tgpio->lock

[ Upstream commit 9e8bc2dda5a7a8e2babc9975f4b11c9a6196e490 ]

As timbgpio_irq_enable()/timbgpio_irq_disable() callback could be
executed under irq context, it could introduce double locks on
&tgpio->lock if it preempts other execution units requiring
the same locks.

timbgpio_gpio_set()
--> timbgpio_update_bit()
--> spin_lock(&tgpio->lock)
<interrupt>
   --> timbgpio_irq_disable()
   --> spin_lock_irqsave(&tgpio->lock)

This flaw was found by an experimental static analysis tool I am
developing for irq-related deadlock.

To prevent the potential deadlock, the patch uses spin_lock_irqsave()
on &tgpio->lock inside timbgpio_gpio_set() to prevent the possible
deadlock scenario.

Signed-off-by: Chengfeng Ye <dg573847474@gmail.com>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/gpio/gpio-timberdale.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-timberdale.c b/drivers/gpio/gpio-timberdale.c
index 314e300d6ba3..1e6925c27ae2 100644
--- a/drivers/gpio/gpio-timberdale.c
+++ b/drivers/gpio/gpio-timberdale.c
@@ -55,9 +55,10 @@ static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
 	unsigned offset, bool enabled)
 {
 	struct timbgpio *tgpio = gpiochip_get_data(gpio);
+	unsigned long flags;
 	u32 reg;
 
-	spin_lock(&tgpio->lock);
+	spin_lock_irqsave(&tgpio->lock, flags);
 	reg = ioread32(tgpio->membase + offset);
 
 	if (enabled)
@@ -66,7 +67,7 @@ static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
 		reg &= ~(1 << index);
 
 	iowrite32(reg, tgpio->membase + offset);
-	spin_unlock(&tgpio->lock);
+	spin_unlock_irqrestore(&tgpio->lock, flags);
 
 	return 0;
 }
-- 
GitLab


From ea7df52089490a703be5b7188f1a067c9b2b8ed7 Mon Sep 17 00:00:00 2001
From: Damien Le Moal <dlemoal@kernel.org>
Date: Tue, 12 Sep 2023 09:08:40 +0900
Subject: [PATCH 250/298] ata: libata-eh: Fix compilation warning in
 ata_eh_link_report()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

[ Upstream commit 49728bdc702391902a473b9393f1620eea32acb0 ]

The 6 bytes length of the tries_buf string in ata_eh_link_report() is
too short and results in a gcc compilation warning with W-!:

drivers/ata/libata-eh.c: In function ‘ata_eh_link_report’:
drivers/ata/libata-eh.c:2371:59: warning: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size 4 [-Wformat-truncation=]
 2371 |                 snprintf(tries_buf, sizeof(tries_buf), " t%d",
      |                                                           ^~
drivers/ata/libata-eh.c:2371:56: note: directive argument in the range [-2147483648, 4]
 2371 |                 snprintf(tries_buf, sizeof(tries_buf), " t%d",
      |                                                        ^~~~~~
drivers/ata/libata-eh.c:2371:17: note: ‘snprintf’ output between 4 and 14 bytes into a destination of size 6
 2371 |                 snprintf(tries_buf, sizeof(tries_buf), " t%d",
      |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 2372 |                          ap->eh_tries);
      |                          ~~~~~~~~~~~~~

Avoid this warning by increasing the string size to 16B.

Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Martin K. Petersen <martin.petersen@oracle.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/ata/libata-eh.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c
index 73a4dd37d04a..63423d9e1457 100644
--- a/drivers/ata/libata-eh.c
+++ b/drivers/ata/libata-eh.c
@@ -2443,7 +2443,7 @@ static void ata_eh_link_report(struct ata_link *link)
 	struct ata_eh_context *ehc = &link->eh_context;
 	struct ata_queued_cmd *qc;
 	const char *frozen, *desc;
-	char tries_buf[6] = "";
+	char tries_buf[16] = "";
 	int tag, nr_failed = 0;
 
 	if (ehc->i.flags & ATA_EHI_QUIET)
-- 
GitLab


From 79700b56f17ddc28ca9f2b4c63d8dca288754897 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= <cleger@rivosinc.com>
Date: Fri, 29 Sep 2023 21:16:37 +0200
Subject: [PATCH 251/298] tracing: relax trace_event_eval_update() execution
 with cond_resched()
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

[ Upstream commit 23cce5f25491968b23fb9c399bbfb25f13870cd9 ]

When kernel is compiled without preemption, the eval_map_work_func()
(which calls trace_event_eval_update()) will not be preempted up to its
complete execution. This can actually cause a problem since if another
CPU call stop_machine(), the call will have to wait for the
eval_map_work_func() function to finish executing in the workqueue
before being able to be scheduled. This problem was observe on a SMP
system at boot time, when the CPU calling the initcalls executed
clocksource_done_booting() which in the end calls stop_machine(). We
observed a 1 second delay because one CPU was executing
eval_map_work_func() and was not preempted by the stop_machine() task.

Adding a call to cond_resched() in trace_event_eval_update() allows
other tasks to be executed and thus continue working asynchronously
like before without blocking any pending task at boot time.

Link: https://lore.kernel.org/linux-trace-kernel/20230929191637.416931-1-cleger@rivosinc.com

Cc: Masami Hiramatsu <mhiramat@kernel.org>
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 kernel/trace/trace_events.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/kernel/trace/trace_events.c b/kernel/trace/trace_events.c
index a3dc6c126b3e..ed39d3ec202e 100644
--- a/kernel/trace/trace_events.c
+++ b/kernel/trace/trace_events.c
@@ -2242,6 +2242,7 @@ void trace_event_eval_update(struct trace_eval_map **map, int len)
 				update_event_printk(call, map[i]);
 			}
 		}
+		cond_resched();
 	}
 	up_write(&trace_event_sem);
 }
-- 
GitLab


From a9856853173eb074ba9038c9da94f173e45e9564 Mon Sep 17 00:00:00 2001
From: Ma Ke <make_ruc2021@163.com>
Date: Mon, 18 Sep 2023 10:40:59 +0800
Subject: [PATCH 252/298] HID: holtek: fix slab-out-of-bounds Write in
 holtek_kbd_input_event

[ Upstream commit ffe3b7837a2bb421df84d0177481db9f52c93a71 ]

There is a slab-out-of-bounds Write bug in hid-holtek-kbd driver.
The problem is the driver assumes the device must have an input
but some malicious devices violate this assumption.

Fix this by checking hid_device's input is non-empty before its usage.

Signed-off-by: Ma Ke <make_ruc2021@163.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/hid/hid-holtek-kbd.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/hid/hid-holtek-kbd.c b/drivers/hid/hid-holtek-kbd.c
index 2f8eb6639744..72788ca260e0 100644
--- a/drivers/hid/hid-holtek-kbd.c
+++ b/drivers/hid/hid-holtek-kbd.c
@@ -133,6 +133,10 @@ static int holtek_kbd_input_event(struct input_dev *dev, unsigned int type,
 		return -ENODEV;
 
 	boot_hid = usb_get_intfdata(boot_interface);
+	if (list_empty(&boot_hid->inputs)) {
+		hid_err(hid, "no inputs found\n");
+		return -ENODEV;
+	}
 	boot_hid_input = list_first_entry(&boot_hid->inputs,
 		struct hid_input, list);
 
-- 
GitLab


From 8afe901e0a100547b735dc638ab8213632a3dda6 Mon Sep 17 00:00:00 2001
From: Ying Hsu <yinghsu@chromium.org>
Date: Thu, 7 Sep 2023 04:39:34 +0000
Subject: [PATCH 253/298] Bluetooth: Avoid redundant authentication

[ Upstream commit 1d8e801422d66e4b8c7b187c52196bef94eed887 ]

While executing the Android 13 CTS Verifier Secure Server test on a
ChromeOS device, it was observed that the Bluetooth host initiates
authentication for an RFCOMM connection after SSP completes.
When this happens, some Intel Bluetooth controllers, like AC9560, would
disconnect with "Connection Rejected due to Security Reasons (0x0e)".

Historically, BlueZ did not mandate this authentication while an
authenticated combination key was already in use for the connection.
This behavior was changed since commit 7b5a9241b780
("Bluetooth: Introduce requirements for security level 4").
So, this patch addresses the aforementioned disconnection issue by
restoring the previous behavior.

Signed-off-by: Ying Hsu <yinghsu@chromium.org>
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/bluetooth/hci_conn.c | 63 ++++++++++++++++++++++------------------
 1 file changed, 35 insertions(+), 28 deletions(-)

diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c
index 9d01cccc84ad..b876e97b61c9 100644
--- a/net/bluetooth/hci_conn.c
+++ b/net/bluetooth/hci_conn.c
@@ -1388,34 +1388,41 @@ int hci_conn_security(struct hci_conn *conn, __u8 sec_level, __u8 auth_type,
 	if (!test_bit(HCI_CONN_AUTH, &conn->flags))
 		goto auth;
 
-	/* An authenticated FIPS approved combination key has sufficient
-	 * security for security level 4. */
-	if (conn->key_type == HCI_LK_AUTH_COMBINATION_P256 &&
-	    sec_level == BT_SECURITY_FIPS)
-		goto encrypt;
-
-	/* An authenticated combination key has sufficient security for
-	   security level 3. */
-	if ((conn->key_type == HCI_LK_AUTH_COMBINATION_P192 ||
-	     conn->key_type == HCI_LK_AUTH_COMBINATION_P256) &&
-	    sec_level == BT_SECURITY_HIGH)
-		goto encrypt;
-
-	/* An unauthenticated combination key has sufficient security for
-	   security level 1 and 2. */
-	if ((conn->key_type == HCI_LK_UNAUTH_COMBINATION_P192 ||
-	     conn->key_type == HCI_LK_UNAUTH_COMBINATION_P256) &&
-	    (sec_level == BT_SECURITY_MEDIUM || sec_level == BT_SECURITY_LOW))
-		goto encrypt;
-
-	/* A combination key has always sufficient security for the security
-	   levels 1 or 2. High security level requires the combination key
-	   is generated using maximum PIN code length (16).
-	   For pre 2.1 units. */
-	if (conn->key_type == HCI_LK_COMBINATION &&
-	    (sec_level == BT_SECURITY_MEDIUM || sec_level == BT_SECURITY_LOW ||
-	     conn->pin_length == 16))
-		goto encrypt;
+	switch (conn->key_type) {
+	case HCI_LK_AUTH_COMBINATION_P256:
+		/* An authenticated FIPS approved combination key has
+		 * sufficient security for security level 4 or lower.
+		 */
+		if (sec_level <= BT_SECURITY_FIPS)
+			goto encrypt;
+		break;
+	case HCI_LK_AUTH_COMBINATION_P192:
+		/* An authenticated combination key has sufficient security for
+		 * security level 3 or lower.
+		 */
+		if (sec_level <= BT_SECURITY_HIGH)
+			goto encrypt;
+		break;
+	case HCI_LK_UNAUTH_COMBINATION_P192:
+	case HCI_LK_UNAUTH_COMBINATION_P256:
+		/* An unauthenticated combination key has sufficient security
+		 * for security level 2 or lower.
+		 */
+		if (sec_level <= BT_SECURITY_MEDIUM)
+			goto encrypt;
+		break;
+	case HCI_LK_COMBINATION:
+		/* A combination key has always sufficient security for the
+		 * security levels 2 or lower. High security level requires the
+		 * combination key is generated using maximum PIN code length
+		 * (16). For pre 2.1 units.
+		 */
+		if (sec_level <= BT_SECURITY_MEDIUM || conn->pin_length == 16)
+			goto encrypt;
+		break;
+	default:
+		break;
+	}
 
 auth:
 	if (test_bit(HCI_CONN_ENCRYPT_PEND, &conn->flags))
-- 
GitLab


From 194ab82c1ea187512ff2f822124bd05b63fc9f76 Mon Sep 17 00:00:00 2001
From: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Date: Fri, 15 Sep 2023 14:42:27 -0700
Subject: [PATCH 254/298] Bluetooth: hci_core: Fix build warnings
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

[ Upstream commit dcda165706b9fbfd685898d46a6749d7d397e0c0 ]

This fixes the following warnings:

net/bluetooth/hci_core.c: In function ‘hci_register_dev’:
net/bluetooth/hci_core.c:2620:54: warning: ‘%d’ directive output may
be truncated writing between 1 and 10 bytes into a region of size 5
[-Wformat-truncation=]
 2620 |         snprintf(hdev->name, sizeof(hdev->name), "hci%d", id);
      |                                                      ^~
net/bluetooth/hci_core.c:2620:50: note: directive argument in the range
[0, 2147483647]
 2620 |         snprintf(hdev->name, sizeof(hdev->name), "hci%d", id);
      |                                                  ^~~~~~~
net/bluetooth/hci_core.c:2620:9: note: ‘snprintf’ output between 5 and
14 bytes into a destination of size 8
 2620 |         snprintf(hdev->name, sizeof(hdev->name), "hci%d", id);
      |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 include/net/bluetooth/hci_core.h | 2 +-
 net/bluetooth/hci_core.c         | 8 +++++---
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h
index 464a78200a31..d3503f8c054e 100644
--- a/include/net/bluetooth/hci_core.h
+++ b/include/net/bluetooth/hci_core.h
@@ -209,7 +209,7 @@ struct hci_dev {
 	struct list_head list;
 	struct mutex	lock;
 
-	char		name[8];
+	const char	*name;
 	unsigned long	flags;
 	__u16		id;
 	__u8		bus;
diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
index 9fdc772ab32e..4d89e38dceec 100644
--- a/net/bluetooth/hci_core.c
+++ b/net/bluetooth/hci_core.c
@@ -3193,7 +3193,11 @@ int hci_register_dev(struct hci_dev *hdev)
 	if (id < 0)
 		return id;
 
-	snprintf(hdev->name, sizeof(hdev->name), "hci%d", id);
+	error = dev_set_name(&hdev->dev, "hci%u", id);
+	if (error)
+		return error;
+
+	hdev->name = dev_name(&hdev->dev);
 	hdev->id = id;
 
 	BT_DBG("%p name %s bus %d", hdev, hdev->name, hdev->bus);
@@ -3215,8 +3219,6 @@ int hci_register_dev(struct hci_dev *hdev)
 	if (!IS_ERR_OR_NULL(bt_debugfs))
 		hdev->debugfs = debugfs_create_dir(hdev->name, bt_debugfs);
 
-	dev_set_name(&hdev->dev, "%s", hdev->name);
-
 	error = device_add(&hdev->dev);
 	if (error < 0)
 		goto err_wqueue;
-- 
GitLab


From 77043e2b71c3241777f0e344cc72952403fe40d1 Mon Sep 17 00:00:00 2001
From: Wen Gong <quic_wgong@quicinc.com>
Date: Tue, 1 Aug 2023 02:47:51 -0400
Subject: [PATCH 255/298] wifi: mac80211: allow transmitting EAPOL frames with
 tainted key

[ Upstream commit 61304336c67358d49a989e5e0060d8c99bad6ca8 ]

Lower layer device driver stop/wake TX by calling ieee80211_stop_queue()/
ieee80211_wake_queue() while hw scan. Sometimes hw scan and PTK rekey are
running in parallel, when M4 sent from wpa_supplicant arrive while the TX
queue is stopped, then the M4 will pending send, and then new key install
from wpa_supplicant. After TX queue wake up by lower layer device driver,
the M4 will be dropped by below call stack.

When key install started, the current key flag is set KEY_FLAG_TAINTED in
ieee80211_pairwise_rekey(), and then mac80211 wait key install complete by
lower layer device driver. Meanwhile ieee80211_tx_h_select_key() will return
TX_DROP for the M4 in step 12 below, and then ieee80211_free_txskb() called
by ieee80211_tx_dequeue(), so the M4 will not send and free, then the rekey
process failed becaue AP not receive M4. Please see details in steps below.

There are a interval between KEY_FLAG_TAINTED set for current key flag and
install key complete by lower layer device driver, the KEY_FLAG_TAINTED is
set in this interval, all packet including M4 will be dropped in this
interval, the interval is step 8~13 as below.

issue steps:
      TX thread                 install key thread
1.   stop_queue                      -idle-
2.   sending M4                      -idle-
3.   M4 pending                      -idle-
4.     -idle-                  starting install key from wpa_supplicant
5.     -idle-                  =>ieee80211_key_replace()
6.     -idle-                  =>ieee80211_pairwise_rekey() and set
                                 currently key->flags |= KEY_FLAG_TAINTED
7.     -idle-                  =>ieee80211_key_enable_hw_accel()
8.     -idle-                  =>drv_set_key() and waiting key install
                                 complete from lower layer device driver
9.   wake_queue                     -waiting state-
10.  re-sending M4                  -waiting state-
11.  =>ieee80211_tx_h_select_key()  -waiting state-
12.  drop M4 by KEY_FLAG_TAINTED    -waiting state-
13.    -idle-                   install key complete with success/fail
                                  success: clear flag KEY_FLAG_TAINTED
                                  fail: start disconnect

Hence add check in step 11 above to allow the EAPOL send out in the
interval. If lower layer device driver use the old key/cipher to encrypt
the M4, then AP received/decrypt M4 correctly, after M4 send out, lower
layer device driver install the new key/cipher to hardware and return
success.

If lower layer device driver use new key/cipher to send the M4, then AP
will/should drop the M4, then it is same result with this issue, AP will/
should kick out station as well as this issue.

issue log:
kworker/u16:4-5238  [000]  6456.108926: stop_queue:           phy1 queue:0, reason:0
wpa_supplicant-961  [003]  6456.119737: rdev_tx_control_port: wiphy_name=phy1 name=wlan0 ifindex=6 dest=ARRAY[9e, 05, 31, 20, 9b, d0] proto=36488 unencrypted=0
wpa_supplicant-961  [003]  6456.119839: rdev_return_int_cookie: phy1, returned 0, cookie: 504
wpa_supplicant-961  [003]  6456.120287: rdev_add_key:         phy1, netdev:wlan0(6), key_index: 0, mode: 0, pairwise: true, mac addr: 9e:05:31:20:9b:d0
wpa_supplicant-961  [003]  6456.120453: drv_set_key:          phy1 vif:wlan0(2) sta:9e:05:31:20:9b:d0 cipher:0xfac04, flags=0x9, keyidx=0, hw_key_idx=0
kworker/u16:9-3829  [001]  6456.168240: wake_queue:           phy1 queue:0, reason:0
kworker/u16:9-3829  [001]  6456.168255: drv_wake_tx_queue:    phy1 vif:wlan0(2) sta:9e:05:31:20:9b:d0 ac:0 tid:7
kworker/u16:9-3829  [001]  6456.168305: cfg80211_control_port_tx_status: wdev(1), cookie: 504, ack: false
wpa_supplicant-961  [003]  6459.167982: drv_return_int:       phy1 - -110

issue call stack:
nl80211_frame_tx_status+0x230/0x340 [cfg80211]
cfg80211_control_port_tx_status+0x1c/0x28 [cfg80211]
ieee80211_report_used_skb+0x374/0x3e8 [mac80211]
ieee80211_free_txskb+0x24/0x40 [mac80211]
ieee80211_tx_dequeue+0x644/0x954 [mac80211]
ath10k_mac_tx_push_txq+0xac/0x238 [ath10k_core]
ath10k_mac_op_wake_tx_queue+0xac/0xe0 [ath10k_core]
drv_wake_tx_queue+0x80/0x168 [mac80211]
__ieee80211_wake_txqs+0xe8/0x1c8 [mac80211]
_ieee80211_wake_txqs+0xb4/0x120 [mac80211]
ieee80211_wake_txqs+0x48/0x80 [mac80211]
tasklet_action_common+0xa8/0x254
tasklet_action+0x2c/0x38
__do_softirq+0xdc/0x384

Signed-off-by: Wen Gong <quic_wgong@quicinc.com>
Link: https://lore.kernel.org/r/20230801064751.25803-1-quic_wgong@quicinc.com
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/mac80211/tx.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/net/mac80211/tx.c b/net/mac80211/tx.c
index 74045e927e04..3a0aadf881fc 100644
--- a/net/mac80211/tx.c
+++ b/net/mac80211/tx.c
@@ -654,7 +654,8 @@ ieee80211_tx_h_select_key(struct ieee80211_tx_data *tx)
 		}
 
 		if (unlikely(tx->key && tx->key->flags & KEY_FLAG_TAINTED &&
-			     !ieee80211_is_deauth(hdr->frame_control)))
+			     !ieee80211_is_deauth(hdr->frame_control)) &&
+			     tx->skb->protocol != tx->sdata->control_port_protocol)
 			return TX_DROP;
 
 		if (!skip_hw && tx->key &&
-- 
GitLab


From b1c345db2e5a4c40bc17cd3cd4aadba1f51e8292 Mon Sep 17 00:00:00 2001
From: Benjamin Berg <benjamin.berg@intel.com>
Date: Mon, 25 Sep 2023 17:18:56 +0200
Subject: [PATCH 256/298] wifi: cfg80211: avoid leaking stack data into trace

[ Upstream commit 334bf33eec5701a1e4e967bcb7cc8611a998334b ]

If the structure is not initialized then boolean types might be copied
into the tracing data without being initialised. This causes data from
the stack to leak into the trace and also triggers a UBSAN failure which
can easily be avoided here.

Signed-off-by: Benjamin Berg <benjamin.berg@intel.com>
Link: https://lore.kernel.org/r/20230925171855.a9271ef53b05.I8180bae663984c91a3e036b87f36a640ba409817@changeid
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/wireless/nl80211.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
index 534f57363f4a..e33c1175b158 100644
--- a/net/wireless/nl80211.c
+++ b/net/wireless/nl80211.c
@@ -6504,7 +6504,7 @@ static int nl80211_update_mesh_config(struct sk_buff *skb,
 	struct cfg80211_registered_device *rdev = info->user_ptr[0];
 	struct net_device *dev = info->user_ptr[1];
 	struct wireless_dev *wdev = dev->ieee80211_ptr;
-	struct mesh_config cfg;
+	struct mesh_config cfg = {};
 	u32 mask;
 	int err;
 
-- 
GitLab


From 2e69b1803e9203ed4421988652ab35f450c77960 Mon Sep 17 00:00:00 2001
From: Kees Cook <keescook@chromium.org>
Date: Fri, 22 Sep 2023 09:50:39 -0700
Subject: [PATCH 257/298] sky2: Make sure there is at least one frag_addr
 available

[ Upstream commit 6a70e5cbedaf8ad10528ac9ac114f3ec20f422df ]

In the pathological case of building sky2 with 16k PAGE_SIZE, the
frag_addr[] array would never be used, so the original code was correct
that size should be 0. But the compiler now gets upset with 0 size arrays
in places where it hasn't eliminated the code that might access such an
array (it can't figure out that in this case an rx skb with fragments
would never be created). To keep the compiler happy, make sure there is
at least 1 frag_addr in struct rx_ring_info:

   In file included from include/linux/skbuff.h:28,
                    from include/net/net_namespace.h:43,
                    from include/linux/netdevice.h:38,
                    from drivers/net/ethernet/marvell/sky2.c:18:
   drivers/net/ethernet/marvell/sky2.c: In function 'sky2_rx_unmap_skb':
   include/linux/dma-mapping.h:416:36: warning: array subscript i is outside array bounds of 'dma_addr_t[0]' {aka 'long long unsigned int[]'} [-Warray-bounds=]
     416 | #define dma_unmap_page(d, a, s, r) dma_unmap_page_attrs(d, a, s, r, 0)
         |                                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   drivers/net/ethernet/marvell/sky2.c:1257:17: note: in expansion of macro 'dma_unmap_page'
    1257 |                 dma_unmap_page(&pdev->dev, re->frag_addr[i],
         |                 ^~~~~~~~~~~~~~
   In file included from drivers/net/ethernet/marvell/sky2.c:41:
   drivers/net/ethernet/marvell/sky2.h:2198:25: note: while referencing 'frag_addr'
    2198 |         dma_addr_t      frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT];
         |                         ^~~~~~~~~

With CONFIG_PAGE_SIZE_16KB=y, PAGE_SHIFT == 14, so:

  #define ETH_JUMBO_MTU   9000

causes "ETH_JUMBO_MTU >> PAGE_SHIFT" to be 0. Use "?: 1" to solve this build warning.

Cc: Mirko Lindner <mlindner@marvell.com>
Cc: Stephen Hemminger <stephen@networkplumber.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Eric Dumazet <edumazet@google.com>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Paolo Abeni <pabeni@redhat.com>
Cc: netdev@vger.kernel.org
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202309191958.UBw1cjXk-lkp@intel.com/
Reviewed-by: Alexander Lobakin <aleksander.lobakin@intel.com>
Signed-off-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/net/ethernet/marvell/sky2.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/marvell/sky2.h b/drivers/net/ethernet/marvell/sky2.h
index b02b6523083c..99451585a45f 100644
--- a/drivers/net/ethernet/marvell/sky2.h
+++ b/drivers/net/ethernet/marvell/sky2.h
@@ -2201,7 +2201,7 @@ struct rx_ring_info {
 	struct sk_buff	*skb;
 	dma_addr_t	data_addr;
 	DEFINE_DMA_UNMAP_LEN(data_size);
-	dma_addr_t	frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT];
+	dma_addr_t	frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT ?: 1];
 };
 
 enum flow_control {
-- 
GitLab


From 513e97e5a2c9713d77620b7a81b528c582ac074f Mon Sep 17 00:00:00 2001
From: Kai Uwe Broulik <foss-linux@broulik.de>
Date: Sun, 1 Oct 2023 13:47:10 +0200
Subject: [PATCH 258/298] drm: panel-orientation-quirks: Add quirk for One Mix
 2S

[ Upstream commit cbb7eb2dbd9472816e42a1b0fdb51af49abbf812 ]

The One Mix 2S is a mini laptop with a 1200x1920 portrait screen
mounted in a landscape oriented clamshell case. Because of the too
generic DMI strings this entry is also doing bios-date matching.

Signed-off-by: Kai Uwe Broulik <foss-linux@broulik.de>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231001114710.336172-1-foss-linux@broulik.de
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/gpu/drm/drm_panel_orientation_quirks.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c
index 7a2a148b8ec6..597db0acef95 100644
--- a/drivers/gpu/drm/drm_panel_orientation_quirks.c
+++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c
@@ -44,6 +44,14 @@ static const struct drm_dmi_panel_orientation_data gpd_micropc = {
 	.orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
 };
 
+static const struct drm_dmi_panel_orientation_data gpd_onemix2s = {
+	.width = 1200,
+	.height = 1920,
+	.bios_dates = (const char * const []){ "05/21/2018", "10/26/2018",
+		"03/04/2019", NULL },
+	.orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
+};
+
 static const struct drm_dmi_panel_orientation_data gpd_pocket = {
 	.width = 1200,
 	.height = 1920,
@@ -219,6 +227,14 @@ static const struct dmi_system_id orientation_data[] = {
 		  DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "LTH17"),
 		},
 		.driver_data = (void *)&lcd800x1280_rightside_up,
+	}, {	/* One Mix 2S (generic strings, also match on bios date) */
+		.matches = {
+		  DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Default string"),
+		  DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Default string"),
+		  DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Default string"),
+		  DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"),
+		},
+		.driver_data = (void *)&gpd_onemix2s,
 	},
 	{}
 };
-- 
GitLab


From ae60ba4566d2b1c9230f404d3073bc6b8514a02a Mon Sep 17 00:00:00 2001
From: Josef Bacik <josef@toxicpanda.com>
Date: Tue, 26 Sep 2023 15:47:27 -0400
Subject: [PATCH 259/298] btrfs: fix some -Wmaybe-uninitialized warnings in
 ioctl.c
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

[ Upstream commit 9147b9ded499d9853bdf0e9804b7eaa99c4429ed ]

Jens reported the following warnings from -Wmaybe-uninitialized recent
Linus' branch.

  In file included from ./include/asm-generic/rwonce.h:26,
		   from ./arch/arm64/include/asm/rwonce.h:71,
		   from ./include/linux/compiler.h:246,
		   from ./include/linux/export.h:5,
		   from ./include/linux/linkage.h:7,
		   from ./include/linux/kernel.h:17,
		   from fs/btrfs/ioctl.c:6:
  In function ‘instrument_copy_from_user_before’,
      inlined from ‘_copy_from_user’ at ./include/linux/uaccess.h:148:3,
      inlined from ‘copy_from_user’ at ./include/linux/uaccess.h:183:7,
      inlined from ‘btrfs_ioctl_space_info’ at fs/btrfs/ioctl.c:2999:6,
      inlined from ‘btrfs_ioctl’ at fs/btrfs/ioctl.c:4616:10:
  ./include/linux/kasan-checks.h:38:27: warning: ‘space_args’ may be used
  uninitialized [-Wmaybe-uninitialized]
     38 | #define kasan_check_write __kasan_check_write
  ./include/linux/instrumented.h:129:9: note: in expansion of macro
  ‘kasan_check_write’
    129 |         kasan_check_write(to, n);
	|         ^~~~~~~~~~~~~~~~~
  ./include/linux/kasan-checks.h: In function ‘btrfs_ioctl’:
  ./include/linux/kasan-checks.h:20:6: note: by argument 1 of type ‘const
  volatile void *’ to ‘__kasan_check_write’ declared here
     20 | bool __kasan_check_write(const volatile void *p, unsigned int
	size);
	|      ^~~~~~~~~~~~~~~~~~~
  fs/btrfs/ioctl.c:2981:39: note: ‘space_args’ declared here
   2981 |         struct btrfs_ioctl_space_args space_args;
	|                                       ^~~~~~~~~~
  In function ‘instrument_copy_from_user_before’,
      inlined from ‘_copy_from_user’ at ./include/linux/uaccess.h:148:3,
      inlined from ‘copy_from_user’ at ./include/linux/uaccess.h:183:7,
      inlined from ‘_btrfs_ioctl_send’ at fs/btrfs/ioctl.c:4343:9,
      inlined from ‘btrfs_ioctl’ at fs/btrfs/ioctl.c:4658:10:
  ./include/linux/kasan-checks.h:38:27: warning: ‘args32’ may be used
  uninitialized [-Wmaybe-uninitialized]
     38 | #define kasan_check_write __kasan_check_write
  ./include/linux/instrumented.h:129:9: note: in expansion of macro
  ‘kasan_check_write’
    129 |         kasan_check_write(to, n);
	|         ^~~~~~~~~~~~~~~~~
  ./include/linux/kasan-checks.h: In function ‘btrfs_ioctl’:
  ./include/linux/kasan-checks.h:20:6: note: by argument 1 of type ‘const
  volatile void *’ to ‘__kasan_check_write’ declared here
     20 | bool __kasan_check_write(const volatile void *p, unsigned int
	size);
	|      ^~~~~~~~~~~~~~~~~~~
  fs/btrfs/ioctl.c:4341:49: note: ‘args32’ declared here
   4341 |                 struct btrfs_ioctl_send_args_32 args32;
	|                                                 ^~~~~~

This was due to his config options and having KASAN turned on,
which adds some extra checks around copy_from_user(), which then
triggered the -Wmaybe-uninitialized checker for these cases.

Fix the warnings by initializing the different structs we're copying
into.

Reported-by: Jens Axboe <axboe@kernel.dk>
Signed-off-by: Josef Bacik <josef@toxicpanda.com>
Reviewed-by: David Sterba <dsterba@suse.com>
Signed-off-by: David Sterba <dsterba@suse.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 fs/btrfs/ioctl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/fs/btrfs/ioctl.c b/fs/btrfs/ioctl.c
index f009d585e72f..e3f18edc1afe 100644
--- a/fs/btrfs/ioctl.c
+++ b/fs/btrfs/ioctl.c
@@ -4526,7 +4526,7 @@ static void get_block_group_info(struct list_head *groups_list,
 static long btrfs_ioctl_space_info(struct btrfs_fs_info *fs_info,
 				   void __user *arg)
 {
-	struct btrfs_ioctl_space_args space_args;
+	struct btrfs_ioctl_space_args space_args = { 0 };
 	struct btrfs_ioctl_space_info space;
 	struct btrfs_ioctl_space_info *dest;
 	struct btrfs_ioctl_space_info *dest_orig;
@@ -5884,7 +5884,7 @@ static int _btrfs_ioctl_send(struct file *file, void __user *argp, bool compat)
 
 	if (compat) {
 #if defined(CONFIG_64BIT) && defined(CONFIG_COMPAT)
-		struct btrfs_ioctl_send_args_32 args32;
+		struct btrfs_ioctl_send_args_32 args32 = { 0 };
 
 		ret = copy_from_user(&args32, argp, sizeof(args32));
 		if (ret)
-- 
GitLab


From 91f48261e7fa4b7b460e89aeb2db92985802ca81 Mon Sep 17 00:00:00 2001
From: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Date: Thu, 5 Oct 2023 13:59:59 -0700
Subject: [PATCH 260/298] Bluetooth: hci_event: Fix using memcmp when comparing
 keys

[ Upstream commit b541260615f601ae1b5d6d0cc54e790de706303b ]

memcmp is not consider safe to use with cryptographic secrets:

 'Do  not  use memcmp() to compare security critical data, such as
 cryptographic secrets, because the required CPU time depends on the
 number of equal bytes.'

While usage of memcmp for ZERO_KEY may not be considered a security
critical data, it can lead to more usage of memcmp with pairing keys
which could introduce more security problems.

Fixes: 455c2ff0a558 ("Bluetooth: Fix BR/EDR out-of-band pairing with only initiator data")
Fixes: 33155c4aae52 ("Bluetooth: hci_event: Ignore NULL link key")
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 net/bluetooth/hci_event.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
index 843502783b26..8b59f7808628 100644
--- a/net/bluetooth/hci_event.c
+++ b/net/bluetooth/hci_event.c
@@ -25,6 +25,8 @@
 /* Bluetooth HCI event handling. */
 
 #include <asm/unaligned.h>
+#include <linux/crypto.h>
+#include <crypto/algapi.h>
 
 #include <net/bluetooth/bluetooth.h>
 #include <net/bluetooth/hci_core.h>
@@ -3827,7 +3829,7 @@ static void hci_link_key_notify_evt(struct hci_dev *hdev, struct sk_buff *skb)
 		goto unlock;
 
 	/* Ignore NULL link key against CVE-2020-26555 */
-	if (!memcmp(ev->link_key, ZERO_KEY, HCI_LINK_KEY_SIZE)) {
+	if (!crypto_memneq(ev->link_key, ZERO_KEY, HCI_LINK_KEY_SIZE)) {
 		bt_dev_dbg(hdev, "Ignore NULL link key (ZERO KEY) for %pMR",
 			   &ev->bdaddr);
 		hci_disconnect(conn, HCI_ERROR_AUTH_FAILURE);
@@ -4313,8 +4315,8 @@ static u8 bredr_oob_data_present(struct hci_conn *conn)
 		 * available, then do not declare that OOB data is
 		 * present.
 		 */
-		if (!memcmp(data->rand256, ZERO_KEY, 16) ||
-		    !memcmp(data->hash256, ZERO_KEY, 16))
+		if (!crypto_memneq(data->rand256, ZERO_KEY, 16) ||
+		    !crypto_memneq(data->hash256, ZERO_KEY, 16))
 			return 0x00;
 
 		return 0x02;
@@ -4324,8 +4326,8 @@ static u8 bredr_oob_data_present(struct hci_conn *conn)
 	 * not supported by the hardware, then check that if
 	 * P-192 data values are present.
 	 */
-	if (!memcmp(data->rand192, ZERO_KEY, 16) ||
-	    !memcmp(data->hash192, ZERO_KEY, 16))
+	if (!crypto_memneq(data->rand192, ZERO_KEY, 16) ||
+	    !crypto_memneq(data->hash192, ZERO_KEY, 16))
 		return 0x00;
 
 	return 0x01;
-- 
GitLab


From a9b937dfbc3a73accc64c12546cb300a0d77fce0 Mon Sep 17 00:00:00 2001
From: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
Date: Wed, 13 Sep 2023 12:37:02 +0530
Subject: [PATCH 261/298] mtd: rawnand: qcom: Unmap the right resource upon
 probe failure

commit 5279f4a9eed3ee7d222b76511ea7a22c89e7eefd upstream.

We currently provide the physical address of the DMA region
rather than the output of dma_map_resource() which is obviously wrong.

Fixes: 7330fc505af4 ("mtd: rawnand: qcom: stop using phys_to_dma()")
Cc: stable@vger.kernel.org
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20230913070702.12707-1-quic_bibekkum@quicinc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/mtd/nand/raw/qcom_nandc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index c64b408f080a..783cdc8728cb 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -2987,7 +2987,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
 err_aon_clk:
 	clk_disable_unprepare(nandc->core_clk);
 err_core_clk:
-	dma_unmap_resource(dev, res->start, resource_size(res),
+	dma_unmap_resource(dev, nandc->base_dma, resource_size(res),
 			   DMA_BIDIRECTIONAL, 0);
 	return ret;
 }
-- 
GitLab


From 7b70f98311ceece8d152c2f04766f54d460ffc53 Mon Sep 17 00:00:00 2001
From: Martin Kurbanov <mmkurbanov@sberdevices.ru>
Date: Tue, 5 Sep 2023 17:56:37 +0300
Subject: [PATCH 262/298] mtd: spinand: micron: correct bitmask for ecc status

commit 9836a987860e33943945d4b257729a4f94eae576 upstream.

Valid bitmask is 0x70 in the status register.

Fixes: a508e8875e13 ("mtd: spinand: Add initial support for Micron MT29F2G01ABAGD")
Signed-off-by: Martin Kurbanov <mmkurbanov@sberdevices.ru>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20230905145637.139068-1-mmkurbanov@sberdevices.ru
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/mtd/nand/spi/micron.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index 9c4381d6847b..fabca2c36321 100644
--- a/drivers/mtd/nand/spi/micron.c
+++ b/drivers/mtd/nand/spi/micron.c
@@ -12,7 +12,7 @@
 
 #define SPINAND_MFR_MICRON		0x2c
 
-#define MICRON_STATUS_ECC_MASK		GENMASK(7, 4)
+#define MICRON_STATUS_ECC_MASK		GENMASK(6, 4)
 #define MICRON_STATUS_ECC_NO_BITFLIPS	(0 << 4)
 #define MICRON_STATUS_ECC_1TO3_BITFLIPS	(1 << 4)
 #define MICRON_STATUS_ECC_4TO6_BITFLIPS	(3 << 4)
-- 
GitLab


From f08a3b9c5c635074c5d630dfd507a1acfd6e0a7d Mon Sep 17 00:00:00 2001
From: Avri Altman <avri.altman@wdc.com>
Date: Wed, 27 Sep 2023 10:15:00 +0300
Subject: [PATCH 263/298] mmc: core: Capture correct oemid-bits for eMMC cards

commit 84ee19bffc9306128cd0f1c650e89767079efeff upstream.

The OEMID is an 8-bit binary number rather than 16-bit as the current code
parses for. The OEMID occupies bits [111:104] in the CID register, see the
eMMC spec JESD84-B51 paragraph 7.2.3. It seems that the 16-bit comes from
the legacy MMC specs (v3.31 and before).

Let's fix the parsing by simply move to use 8-bit instead of 16-bit. This
means we ignore the impact on some of those old MMC cards that may be out
there, but on the other hand this shouldn't be a problem as the OEMID seems
not be an important feature for these cards.

Signed-off-by: Avri Altman <avri.altman@wdc.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20230927071500.1791882-1-avri.altman@wdc.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/mmc/core/mmc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 745a4b07faff..20856a7734a9 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -98,7 +98,7 @@ static int mmc_decode_cid(struct mmc_card *card)
 	case 3: /* MMC v3.1 - v3.3 */
 	case 4: /* MMC v4 */
 		card->cid.manfid	= UNSTUFF_BITS(resp, 120, 8);
-		card->cid.oemid		= UNSTUFF_BITS(resp, 104, 16);
+		card->cid.oemid		= UNSTUFF_BITS(resp, 104, 8);
 		card->cid.prod_name[0]	= UNSTUFF_BITS(resp, 96, 8);
 		card->cid.prod_name[1]	= UNSTUFF_BITS(resp, 88, 8);
 		card->cid.prod_name[2]	= UNSTUFF_BITS(resp, 80, 8);
-- 
GitLab


From db5c90d31ed8c47dfb5d11c703dcc017b440438d Mon Sep 17 00:00:00 2001
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Date: Tue, 17 Oct 2023 17:18:06 +0300
Subject: [PATCH 264/298] Revert "pinctrl: avoid unsafe code pattern in
 find_pinctrl()"

commit 62140a1e4dec4594d5d1e1d353747bf2ef434e8b upstream.

The commit breaks MMC enumeration on the Intel Merrifield
plaform.

Before:
[   36.439057] mmc0: SDHCI controller on PCI [0000:00:01.0] using ADMA
[   36.450924] mmc2: SDHCI controller on PCI [0000:00:01.3] using ADMA
[   36.459355] mmc1: SDHCI controller on PCI [0000:00:01.2] using ADMA
[   36.706399] mmc0: new DDR MMC card at address 0001
[   37.058972] mmc2: new ultra high speed DDR50 SDIO card at address 0001
[   37.278977] mmcblk0: mmc0:0001 H4G1d 3.64 GiB
[   37.297300]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10

After:
[   36.436704] mmc2: SDHCI controller on PCI [0000:00:01.3] using ADMA
[   36.436720] mmc1: SDHCI controller on PCI [0000:00:01.0] using ADMA
[   36.463685] mmc0: SDHCI controller on PCI [0000:00:01.2] using ADMA
[   36.720627] mmc1: new DDR MMC card at address 0001
[   37.068181] mmc2: new ultra high speed DDR50 SDIO card at address 0001
[   37.279998] mmcblk1: mmc1:0001 H4G1d 3.64 GiB
[   37.302670]  mmcblk1: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10

This reverts commit c153a4edff6ab01370fcac8e46f9c89cca1060c2.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20231017141806.535191-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/pinctrl/core.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 597a8546fc4b..a8148460f99f 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -1001,20 +1001,17 @@ static int add_setting(struct pinctrl *p, struct pinctrl_dev *pctldev,
 
 static struct pinctrl *find_pinctrl(struct device *dev)
 {
-	struct pinctrl *entry, *p = NULL;
+	struct pinctrl *p;
 
 	mutex_lock(&pinctrl_list_mutex);
-
-	list_for_each_entry(entry, &pinctrl_list, node) {
-		if (entry->dev == dev) {
-			p = entry;
-			kref_get(&p->users);
-			break;
+	list_for_each_entry(p, &pinctrl_list, node)
+		if (p->dev == dev) {
+			mutex_unlock(&pinctrl_list_mutex);
+			return p;
 		}
-	}
 
 	mutex_unlock(&pinctrl_list_mutex);
-	return p;
+	return NULL;
 }
 
 static void pinctrl_free(struct pinctrl *p, bool inlist);
@@ -1123,6 +1120,7 @@ struct pinctrl *pinctrl_get(struct device *dev)
 	p = find_pinctrl(dev);
 	if (p) {
 		dev_dbg(dev, "obtain a copy of previously claimed pinctrl\n");
+		kref_get(&p->users);
 		return p;
 	}
 
-- 
GitLab


From 3ed90437a117336d7e6858d0464d7c2953868778 Mon Sep 17 00:00:00 2001
From: Sunil V L <sunilvl@ventanamicro.com>
Date: Mon, 16 Oct 2023 22:39:39 +0530
Subject: [PATCH 265/298] ACPI: irq: Fix incorrect return value in
 acpi_register_gsi()

commit 0c21a18d5d6c6a73d098fb9b4701572370942df9 upstream.

acpi_register_gsi() should return a negative value in case of failure.

Currently, it returns the return value from irq_create_fwspec_mapping().
However, irq_create_fwspec_mapping() returns 0 for failure. Fix the
issue by returning -EINVAL if irq_create_fwspec_mapping() returns zero.

Fixes: d44fa3d46079 ("ACPI: Add support for ResourceSource/IRQ domain mapping")
Cc: 4.11+ <stable@vger.kernel.org> # 4.11+
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
[ rjw: Rename a new local variable ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/acpi/irq.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c
index 7c352cba0528..8ac01375fe8f 100644
--- a/drivers/acpi/irq.c
+++ b/drivers/acpi/irq.c
@@ -55,6 +55,7 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger,
 		      int polarity)
 {
 	struct irq_fwspec fwspec;
+	unsigned int irq;
 
 	if (WARN_ON(!acpi_gsi_domain_id)) {
 		pr_warn("GSI: No registered irqchip, giving up\n");
@@ -66,7 +67,11 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger,
 	fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity);
 	fwspec.param_count = 2;
 
-	return irq_create_fwspec_mapping(&fwspec);
+	irq = irq_create_fwspec_mapping(&fwspec);
+	if (!irq)
+		return -EINVAL;
+
+	return irq;
 }
 EXPORT_SYMBOL_GPL(acpi_register_gsi);
 
-- 
GitLab


From 56008596241e1c7fbf22531cce3598a5e9562f6e Mon Sep 17 00:00:00 2001
From: Fabio Porcedda <fabio.porcedda@gmail.com>
Date: Tue, 5 Sep 2023 09:37:24 +0200
Subject: [PATCH 266/298] USB: serial: option: add Telit LE910C4-WWX 0x1035
 composition

commit 6a7be48e9bd18d309ba25c223a27790ad1bf0fa3 upstream.

Add support for the following Telit LE910C4-WWX composition:

0x1035: TTY, TTY, ECM

T:  Bus=01 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#=  5 Spd=480 MxCh= 0
D:  Ver= 2.00 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs=  1
P:  Vendor=1bc7 ProdID=1035 Rev=00.00
S:  Manufacturer=Telit
S:  Product=LE910C4-WWX
S:  SerialNumber=e1b117c7
C:  #Ifs= 4 Cfg#= 1 Atr=e0 MxPwr=500mA
I:  If#= 0 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=option
E:  Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=81(I) Atr=03(Int.) MxPS=  64 Ivl=2ms
E:  Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:  If#= 1 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=fe Prot=ff Driver=option
E:  Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=83(I) Atr=03(Int.) MxPS=  64 Ivl=2ms
E:  Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:  If#= 2 Alt= 0 #EPs= 1 Cls=02(commc) Sub=06 Prot=00 Driver=cdc_ether
E:  Ad=85(I) Atr=03(Int.) MxPS=  64 Ivl=2ms
I:  If#= 3 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=cdc_ether
E:  Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms

Signed-off-by: Fabio Porcedda <fabio.porcedda@gmail.com>
Cc: stable@vger.kernel.org
Reviewed-by: Daniele Palmas <dnlplm@gmail.com>
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/serial/option.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index a4787fcf6ba9..c87f6ac86409 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -1290,6 +1290,7 @@ static const struct usb_device_id option_ids[] = {
 	 .driver_info = NCTRL(0) | RSVD(3) },
 	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1033, 0xff),	/* Telit LE910C1-EUX (ECM) */
 	 .driver_info = NCTRL(0) },
+	{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1035, 0xff) }, /* Telit LE910C4-WWX (ECM) */
 	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_LE922_USBCFG0),
 	  .driver_info = RSVD(0) | RSVD(1) | NCTRL(2) | RSVD(3) },
 	{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_LE922_USBCFG1),
-- 
GitLab


From fa31878d558080c5435fa3e4de81c201e1a17641 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Beno=C3=AEt=20Monin?= <benoit.monin@gmx.fr>
Date: Mon, 2 Oct 2023 17:51:40 +0200
Subject: [PATCH 267/298] USB: serial: option: add entry for Sierra EM9191 with
 new firmware
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

commit 064f6e2ba9eb59b2c87b866e1e968e79ccedf9dd upstream.

Following a firmware update of the modem, the interface for the AT
command port changed, so add it back.

T:  Bus=08 Lev=01 Prnt=01 Port=01 Cnt=02 Dev#=  2 Spd=5000 MxCh= 0
D:  Ver= 3.20 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs=  1
P:  Vendor=1199 ProdID=90d3 Rev=00.06
S:  Manufacturer=Sierra Wireless, Incorporated
S:  Product=Sierra Wireless EM9191
S:  SerialNumber=xxxxxxxxxxxxxxxx
C:  #Ifs= 4 Cfg#= 1 Atr=a0 MxPwr=896mA
I:  If#=0x0 Alt= 0 #EPs= 1 Cls=02(commc) Sub=0e Prot=00 Driver=cdc_mbim
I:  If#=0x1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim
I:  If#=0x3 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=40 Driver=(none)
I:  If#=0x4 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=30 Driver=option

Signed-off-by: Benoît Monin <benoit.monin@gmx.fr>
Cc: stable@vger.kernel.org
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/serial/option.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index c87f6ac86409..ef8340972322 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -2263,6 +2263,7 @@ static const struct usb_device_id option_ids[] = {
 	{ USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1406, 0xff) },			/* GosunCn GM500 ECM/NCM */
 	{ USB_DEVICE_AND_INTERFACE_INFO(OPPO_VENDOR_ID, OPPO_PRODUCT_R11, 0xff, 0xff, 0x30) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0xff, 0x30) },
+	{ USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0xff, 0x40) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0, 0) },
 	{ USB_DEVICE_AND_INTERFACE_INFO(UNISOC_VENDOR_ID, TOZED_PRODUCT_LT70C, 0xff, 0, 0) },
 	{ } /* Terminating entry */
-- 
GitLab


From 78695075850e0c616e0108a1dbce6dd1606c87e4 Mon Sep 17 00:00:00 2001
From: Puliang Lu <puliang.lu@fibocom.com>
Date: Mon, 16 Oct 2023 15:36:16 +0800
Subject: [PATCH 268/298] USB: serial: option: add Fibocom to DELL custom modem
 FM101R-GL

commit 52480e1f1a259c93d749ba3961af0bffedfe7a7a upstream.

Update the USB serial option driver support for the Fibocom
FM101R-GL LTE modules as there are actually several different variants.

- VID:PID 413C:8213, FM101R-GL are laptop M.2 cards (with
  MBIM interfaces for Linux)

- VID:PID 413C:8215, FM101R-GL ESIM are laptop M.2 cards (with
  MBIM interface for Linux)

0x8213: mbim, tty
0x8215: mbim, tty

T:  Bus=04 Lev=01 Prnt=01 Port=01 Cnt=01 Dev#=  2 Spd=5000 MxCh= 0
D:  Ver= 3.20 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs=  1
P:  Vendor=413c ProdID=8213 Rev= 5.04
S:  Manufacturer=Fibocom Wireless Inc.
S:  Product=Fibocom FM101-GL Module
S:  SerialNumber=a3b7cbf0
C:* #Ifs= 3 Cfg#= 1 Atr=a0 MxPwr=896mA
A:  FirstIf#= 0 IfCount= 2 Cls=02(comm.) Sub=0e Prot=00
I:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=0e Prot=00 Driver=cdc_mbim
E:  Ad=81(I) Atr=03(Int.) MxPS=  64 Ivl=32ms
I:  If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim
I:* If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim
E:  Ad=8e(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
E:  Ad=0f(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms
I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=40 Driver=(none)
E:  Ad=83(I) Atr=03(Int.) MxPS=  10 Ivl=32ms
E:  Ad=82(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
E:  Ad=01(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms

T:  Bus=04 Lev=01 Prnt=01 Port=01 Cnt=01 Dev#=  3 Spd=5000 MxCh= 0
D:  Ver= 3.20 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs=  1
P:  Vendor=413c ProdID=8215 Rev= 5.04
S:  Manufacturer=Fibocom Wireless Inc.
S:  Product=Fibocom FM101-GL Module
S:  SerialNumber=a3b7cbf0
C:* #Ifs= 3 Cfg#= 1 Atr=a0 MxPwr=896mA
A:  FirstIf#= 0 IfCount= 2 Cls=02(comm.) Sub=0e Prot=00
I:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=0e Prot=00 Driver=cdc_mbim
E:  Ad=81(I) Atr=03(Int.) MxPS=  64 Ivl=32ms
I:  If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim
I:* If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim
E:  Ad=8e(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
E:  Ad=0f(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms
I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=40 Driver=(none)
E:  Ad=83(I) Atr=03(Int.) MxPS=  10 Ivl=32ms
E:  Ad=82(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
E:  Ad=01(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms

Signed-off-by: Puliang Lu <puliang.lu@fibocom.com>
Cc: stable@vger.kernel.org
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/usb/serial/option.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index ef8340972322..7fab049e790f 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -203,6 +203,9 @@ static void option_instat_callback(struct urb *urb);
 #define DELL_PRODUCT_5829E_ESIM			0x81e4
 #define DELL_PRODUCT_5829E			0x81e6
 
+#define DELL_PRODUCT_FM101R			0x8213
+#define DELL_PRODUCT_FM101R_ESIM		0x8215
+
 #define KYOCERA_VENDOR_ID			0x0c88
 #define KYOCERA_PRODUCT_KPC650			0x17da
 #define KYOCERA_PRODUCT_KPC680			0x180a
@@ -1108,6 +1111,8 @@ static const struct usb_device_id option_ids[] = {
 	  .driver_info = RSVD(0) | RSVD(6) },
 	{ USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5829E_ESIM),
 	  .driver_info = RSVD(0) | RSVD(6) },
+	{ USB_DEVICE_INTERFACE_CLASS(DELL_VENDOR_ID, DELL_PRODUCT_FM101R, 0xff) },
+	{ USB_DEVICE_INTERFACE_CLASS(DELL_VENDOR_ID, DELL_PRODUCT_FM101R_ESIM, 0xff) },
 	{ USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_E100A) },	/* ADU-E100, ADU-310 */
 	{ USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_500A) },
 	{ USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_620UW) },
-- 
GitLab


From a714491fa92d2068358dd603cc50bf2062517bd8 Mon Sep 17 00:00:00 2001
From: Peter Zijlstra <peterz@infradead.org>
Date: Wed, 18 Oct 2023 13:56:54 +0200
Subject: [PATCH 269/298] perf: Disallow mis-matched inherited group reads

commit 32671e3799ca2e4590773fd0e63aaa4229e50c06 upstream.

Because group consistency is non-atomic between parent (filedesc) and children
(inherited) events, it is possible for PERF_FORMAT_GROUP read() to try and sum
non-matching counter groups -- with non-sensical results.

Add group_generation to distinguish the case where a parent group removes and
adds an event and thus has the same number, but a different configuration of
events as inherited groups.

This became a problem when commit fa8c269353d5 ("perf/core: Invert
perf_read_group() loops") flipped the order of child_list and sibling_list.
Previously it would iterate the group (sibling_list) first, and for each
sibling traverse the child_list. In this order, only the group composition of
the parent is relevant. By flipping the order the group composition of the
child (inherited) events becomes an issue and the mis-match in group
composition becomes evident.

That said; even prior to this commit, while reading of a group that is not
equally inherited was not broken, it still made no sense.

(Ab)use ECHILD as error return to indicate issues with child process group
composition.

Fixes: fa8c269353d5 ("perf/core: Invert perf_read_group() loops")
Reported-by: Budimir Markovic <markovicbudimir@gmail.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20231018115654.GK33217@noisy.programming.kicks-ass.net
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 include/linux/perf_event.h |  1 +
 kernel/events/core.c       | 39 ++++++++++++++++++++++++++++++++------
 2 files changed, 34 insertions(+), 6 deletions(-)

diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index f17e08bd294c..d46eeddeb859 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -593,6 +593,7 @@ struct perf_event {
 	/* The cumulative AND of all event_caps for events in this group. */
 	int				group_caps;
 
+	unsigned int			group_generation;
 	struct perf_event		*group_leader;
 	struct pmu			*pmu;
 	void				*pmu_private;
diff --git a/kernel/events/core.c b/kernel/events/core.c
index cb2b717666ce..8f3f3cc08496 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -1848,6 +1848,7 @@ static void perf_group_attach(struct perf_event *event)
 
 	list_add_tail(&event->sibling_list, &group_leader->sibling_list);
 	group_leader->nr_siblings++;
+	group_leader->group_generation++;
 
 	perf_event__header_size(group_leader);
 
@@ -1918,6 +1919,7 @@ static void perf_group_detach(struct perf_event *event)
 	if (event->group_leader != event) {
 		list_del_init(&event->sibling_list);
 		event->group_leader->nr_siblings--;
+		event->group_leader->group_generation++;
 		goto out;
 	}
 
@@ -4755,7 +4757,7 @@ static int __perf_read_group_add(struct perf_event *leader,
 					u64 read_format, u64 *values)
 {
 	struct perf_event_context *ctx = leader->ctx;
-	struct perf_event *sub;
+	struct perf_event *sub, *parent;
 	unsigned long flags;
 	int n = 1; /* skip @nr */
 	int ret;
@@ -4765,6 +4767,33 @@ static int __perf_read_group_add(struct perf_event *leader,
 		return ret;
 
 	raw_spin_lock_irqsave(&ctx->lock, flags);
+	/*
+	 * Verify the grouping between the parent and child (inherited)
+	 * events is still in tact.
+	 *
+	 * Specifically:
+	 *  - leader->ctx->lock pins leader->sibling_list
+	 *  - parent->child_mutex pins parent->child_list
+	 *  - parent->ctx->mutex pins parent->sibling_list
+	 *
+	 * Because parent->ctx != leader->ctx (and child_list nests inside
+	 * ctx->mutex), group destruction is not atomic between children, also
+	 * see perf_event_release_kernel(). Additionally, parent can grow the
+	 * group.
+	 *
+	 * Therefore it is possible to have parent and child groups in a
+	 * different configuration and summing over such a beast makes no sense
+	 * what so ever.
+	 *
+	 * Reject this.
+	 */
+	parent = leader->parent;
+	if (parent &&
+	    (parent->group_generation != leader->group_generation ||
+	     parent->nr_siblings != leader->nr_siblings)) {
+		ret = -ECHILD;
+		goto unlock;
+	}
 
 	/*
 	 * Since we co-schedule groups, {enabled,running} times of siblings
@@ -4794,8 +4823,9 @@ static int __perf_read_group_add(struct perf_event *leader,
 			values[n++] = primary_event_id(sub);
 	}
 
+unlock:
 	raw_spin_unlock_irqrestore(&ctx->lock, flags);
-	return 0;
+	return ret;
 }
 
 static int perf_read_group(struct perf_event *event,
@@ -4814,10 +4844,6 @@ static int perf_read_group(struct perf_event *event,
 
 	values[0] = 1 + leader->nr_siblings;
 
-	/*
-	 * By locking the child_mutex of the leader we effectively
-	 * lock the child list of all siblings.. XXX explain how.
-	 */
 	mutex_lock(&leader->child_mutex);
 
 	ret = __perf_read_group_add(leader, read_format, values);
@@ -11603,6 +11629,7 @@ static int inherit_group(struct perf_event *parent_event,
 		if (IS_ERR(child_ctr))
 			return PTR_ERR(child_ctr);
 	}
+	leader->group_generation = parent_event->group_generation;
 	return 0;
 }
 
-- 
GitLab


From 138da55940e65f48171c8fdcb8b0d84f75596466 Mon Sep 17 00:00:00 2001
From: Niklas Schnelle <schnelle@linux.ibm.com>
Date: Tue, 17 Oct 2023 15:37:29 +0200
Subject: [PATCH 270/298] s390/pci: fix iommu bitmap allocation

commit c1ae1c59c8c6e0b66a718308c623e0cb394dab6b upstream.

Since the fixed commits both zdev->iommu_bitmap and zdev->lazy_bitmap
are allocated as vzalloc(zdev->iommu_pages / 8). The problem is that
zdev->iommu_bitmap is a pointer to unsigned long but the above only
yields an allocation that is a multiple of sizeof(unsigned long) which
is 8 on s390x if the number of IOMMU pages is a multiple of 64.
This in turn is the case only if the effective IOMMU aperture is
a multiple of 64 * 4K = 256K. This is usually the case and so didn't
cause visible issues since both the virt_to_phys(high_memory) reduced
limit and hardware limits use nice numbers.

Under KVM, and in particular with QEMU limiting the IOMMU aperture to
the vfio DMA limit (default 65535), it is possible for the reported
aperture not to be a multiple of 256K however. In this case we end up
with an iommu_bitmap whose allocation is not a multiple of
8 causing bitmap operations to access it out of bounds.

Sadly we can't just fix this in the obvious way and use bitmap_zalloc()
because for large RAM systems (tested on 8 TiB) the zdev->iommu_bitmap
grows too large for kmalloc(). So add our own bitmap_vzalloc() wrapper.
This might be a candidate for common code, but this area of code will
be replaced by the upcoming conversion to use the common code DMA API on
s390 so just add a local routine.

Fixes: 224593215525 ("s390/pci: use virtual memory for iommu bitmap")
Fixes: 13954fd6913a ("s390/pci_dma: improve lazy flush for unmap")
Cc: stable@vger.kernel.org
Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com>
Signed-off-by: Niklas Schnelle <schnelle@linux.ibm.com>
Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 arch/s390/pci/pci_dma.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/s390/pci/pci_dma.c b/arch/s390/pci/pci_dma.c
index d387a0fbdd7e..76d27a5947d5 100644
--- a/arch/s390/pci/pci_dma.c
+++ b/arch/s390/pci/pci_dma.c
@@ -545,6 +545,17 @@ static void s390_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
 		s->dma_length = 0;
 	}
 }
+
+static unsigned long *bitmap_vzalloc(size_t bits, gfp_t flags)
+{
+	size_t n = BITS_TO_LONGS(bits);
+	size_t bytes;
+
+	if (unlikely(check_mul_overflow(n, sizeof(unsigned long), &bytes)))
+		return NULL;
+
+	return vzalloc(bytes);
+}
 	
 static int s390_mapping_error(struct device *dev, dma_addr_t dma_addr)
 {
@@ -586,13 +597,13 @@ int zpci_dma_init_device(struct zpci_dev *zdev)
 				zdev->end_dma - zdev->start_dma + 1);
 	zdev->end_dma = zdev->start_dma + zdev->iommu_size - 1;
 	zdev->iommu_pages = zdev->iommu_size >> PAGE_SHIFT;
-	zdev->iommu_bitmap = vzalloc(zdev->iommu_pages / 8);
+	zdev->iommu_bitmap = bitmap_vzalloc(zdev->iommu_pages, GFP_KERNEL);
 	if (!zdev->iommu_bitmap) {
 		rc = -ENOMEM;
 		goto free_dma_table;
 	}
 	if (!s390_iommu_strict) {
-		zdev->lazy_bitmap = vzalloc(zdev->iommu_pages / 8);
+		zdev->lazy_bitmap = bitmap_vzalloc(zdev->iommu_pages, GFP_KERNEL);
 		if (!zdev->lazy_bitmap) {
 			rc = -ENOMEM;
 			goto free_bitmap;
-- 
GitLab


From 450aac072e0f10c9ecc1c1d9d5d33811739a3cae Mon Sep 17 00:00:00 2001
From: Haibo Chen <haibo.chen@nxp.com>
Date: Wed, 18 Oct 2023 11:00:17 +0200
Subject: [PATCH 271/298] gpio: vf610: set value before the direction to avoid
 a glitch

commit fc363413ef8ea842ae7a99e3caf5465dafdd3a49 upstream.

We found a glitch when configuring the pad as output high. To avoid this
glitch, move the data value setting before direction config in the
function vf610_gpio_direction_output().

Fixes: 659d8a62311f ("gpio: vf610: add imx7ulp support")
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
[Bartosz: tweak the commit message]
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/gpio/gpio-vf610.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
index 01865b3e0a5f..df400d14ed17 100644
--- a/drivers/gpio/gpio-vf610.c
+++ b/drivers/gpio/gpio-vf610.c
@@ -137,14 +137,14 @@ static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
 	unsigned long mask = BIT(gpio);
 	u32 val;
 
+	vf610_gpio_set(chip, gpio, value);
+
 	if (port->sdata && port->sdata->have_paddr) {
 		val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
 		val |= mask;
 		vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
 	}
 
-	vf610_gpio_set(chip, gpio, value);
-
 	return pinctrl_gpio_direction_output(chip->base + gpio);
 }
 
-- 
GitLab


From 4daaa482fba067b453075f011842ccf81128dcbd Mon Sep 17 00:00:00 2001
From: Dan Carpenter <dan.carpenter@linaro.org>
Date: Thu, 5 Oct 2023 17:00:24 +0300
Subject: [PATCH 272/298] ASoC: pxa: fix a memory leak in probe()

[ Upstream commit aa6464edbd51af4a2f8db43df866a7642b244b5f ]

Free the "priv" pointer before returning the error code.

Fixes: 90eb6b59d311 ("ASoC: pxa-ssp: add support for an external clock in devicetree")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/r/84ac2313-1420-471a-b2cb-3269a2e12a7c@moroto.mountain
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 sound/soc/pxa/pxa-ssp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/pxa/pxa-ssp.c b/sound/soc/pxa/pxa-ssp.c
index 69033e1a84e6..49481dadb923 100644
--- a/sound/soc/pxa/pxa-ssp.c
+++ b/sound/soc/pxa/pxa-ssp.c
@@ -795,7 +795,7 @@ static int pxa_ssp_probe(struct snd_soc_dai *dai)
 		if (IS_ERR(priv->extclk)) {
 			ret = PTR_ERR(priv->extclk);
 			if (ret == -EPROBE_DEFER)
-				return ret;
+				goto err_priv;
 
 			priv->extclk = NULL;
 		}
-- 
GitLab


From 2c8544a0336cf9b8b672b1ccc733f7968db13929 Mon Sep 17 00:00:00 2001
From: Tony Lindgren <tony@atomide.com>
Date: Wed, 13 Sep 2023 09:04:28 +0300
Subject: [PATCH 273/298] phy: mapphone-mdm6600: Fix runtime PM for remove

[ Upstream commit b99e0ba9633af51638e5ee1668da2e33620c134f ]

Otherwise we will get an underflow on remove.

Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Cc: Merlijn Wajer <merlijn@wizzup.org>
Cc: Pavel Machek <pavel@ucw.cz>
Cc: Sebastian Reichel <sre@kernel.org>
Fixes: f7f50b2a7b05 ("phy: mapphone-mdm6600: Add runtime PM support for n_gsm on USB suspend")
Signed-off-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20230913060433.48373-2-tony@atomide.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/phy/motorola/phy-mapphone-mdm6600.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/phy/motorola/phy-mapphone-mdm6600.c b/drivers/phy/motorola/phy-mapphone-mdm6600.c
index 77518010adc8..44ad15ca881e 100644
--- a/drivers/phy/motorola/phy-mapphone-mdm6600.c
+++ b/drivers/phy/motorola/phy-mapphone-mdm6600.c
@@ -612,6 +612,7 @@ static int phy_mdm6600_remove(struct platform_device *pdev)
 	struct phy_mdm6600 *ddata = platform_get_drvdata(pdev);
 	struct gpio_desc *reset_gpio = ddata->ctrl_gpios[PHY_MDM6600_RESET];
 
+	pm_runtime_get_noresume(ddata->dev);
 	pm_runtime_dont_use_autosuspend(ddata->dev);
 	pm_runtime_put_sync(ddata->dev);
 	pm_runtime_disable(ddata->dev);
-- 
GitLab


From 8f5abc380f789be8d2c9893044fd044bceeb16a4 Mon Sep 17 00:00:00 2001
From: Edward AD <twuufnxlz@gmail.com>
Date: Tue, 10 Oct 2023 13:36:57 +0800
Subject: [PATCH 274/298] Bluetooth: hci_sock: fix slab oob read in
 create_monitor_event

commit 18f547f3fc074500ab5d419cf482240324e73a7e upstream.

When accessing hdev->name, the actual string length should prevail

Reported-by: syzbot+c90849c50ed209d77689@syzkaller.appspotmail.com
Fixes: dcda165706b9 ("Bluetooth: hci_core: Fix build warnings")
Signed-off-by: Edward AD <twuufnxlz@gmail.com>
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/bluetooth/hci_sock.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/net/bluetooth/hci_sock.c b/net/bluetooth/hci_sock.c
index 182c3c5b8385..ab4533244950 100644
--- a/net/bluetooth/hci_sock.c
+++ b/net/bluetooth/hci_sock.c
@@ -430,7 +430,7 @@ static struct sk_buff *create_monitor_event(struct hci_dev *hdev, int event)
 		ni->type = hdev->dev_type;
 		ni->bus = hdev->bus;
 		bacpy(&ni->bdaddr, &hdev->bdaddr);
-		memcpy(ni->name, hdev->name, 8);
+		memcpy(ni->name, hdev->name, strlen(hdev->name));
 
 		opcode = cpu_to_le16(HCI_MON_NEW_INDEX);
 		break;
-- 
GitLab


From 942cab53cc51b20dfb9f51172e10fb6fe1d3b19f Mon Sep 17 00:00:00 2001
From: Kees Cook <keescook@chromium.org>
Date: Wed, 11 Oct 2023 09:31:44 -0700
Subject: [PATCH 275/298] Bluetooth: hci_sock: Correctly bounds check and pad
 HCI_MON_NEW_INDEX name

commit cb3871b1cd135a6662b732fbc6b3db4afcdb4a64 upstream.

The code pattern of memcpy(dst, src, strlen(src)) is almost always
wrong. In this case it is wrong because it leaves memory uninitialized
if it is less than sizeof(ni->name), and overflows ni->name when longer.

Normally strtomem_pad() could be used here, but since ni->name is a
trailing array in struct hci_mon_new_index, compilers that don't support
-fstrict-flex-arrays=3 can't tell how large this array is via
__builtin_object_size(). Instead, open-code the helper and use sizeof()
since it will work correctly.

Additionally mark ni->name as __nonstring since it appears to not be a
%NUL terminated C string.

Cc: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Cc: Edward AD <twuufnxlz@gmail.com>
Cc: Marcel Holtmann <marcel@holtmann.org>
Cc: Johan Hedberg <johan.hedberg@gmail.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Eric Dumazet <edumazet@google.com>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Paolo Abeni <pabeni@redhat.com>
Cc: linux-bluetooth@vger.kernel.org
Cc: netdev@vger.kernel.org
Fixes: 18f547f3fc07 ("Bluetooth: hci_sock: fix slab oob read in create_monitor_event")
Link: https://lore.kernel.org/lkml/202310110908.F2639D3276@keescook/
Signed-off-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/bluetooth/hci_sock.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/net/bluetooth/hci_sock.c b/net/bluetooth/hci_sock.c
index ab4533244950..a7e5bca9f7e4 100644
--- a/net/bluetooth/hci_sock.c
+++ b/net/bluetooth/hci_sock.c
@@ -430,7 +430,8 @@ static struct sk_buff *create_monitor_event(struct hci_dev *hdev, int event)
 		ni->type = hdev->dev_type;
 		ni->bus = hdev->bus;
 		bacpy(&ni->bdaddr, &hdev->bdaddr);
-		memcpy(ni->name, hdev->name, strlen(hdev->name));
+		memcpy_and_pad(ni->name, sizeof(ni->name), hdev->name,
+			       strnlen(hdev->name, sizeof(ni->name)), '\0');
 
 		opcode = cpu_to_le16(HCI_MON_NEW_INDEX);
 		break;
-- 
GitLab


From 0939d7817d5c0dc3900527a54d1cdec2e9f8fe78 Mon Sep 17 00:00:00 2001
From: Zhang Changzhong <zhangchangzhong@huawei.com>
Date: Fri, 15 Sep 2023 19:20:41 +0800
Subject: [PATCH 276/298] xfrm6: fix inet6_dev refcount underflow problem

[ Upstream commit cc9b364bb1d58d3dae270c7a931a8cc717dc2b3b ]

There are race conditions that may lead to inet6_dev refcount underflow
in xfrm6_dst_destroy() and rt6_uncached_list_flush_dev().

One of the refcount underflow bugs is shown below:
	(cpu 1)                	|	(cpu 2)
xfrm6_dst_destroy()             |
  ...                           |
  in6_dev_put()                 |
				|  rt6_uncached_list_flush_dev()
  ...				|    ...
				|    in6_dev_put()
  rt6_uncached_list_del()       |    ...
  ...                           |

xfrm6_dst_destroy() calls rt6_uncached_list_del() after in6_dev_put(),
so rt6_uncached_list_flush_dev() has a chance to call in6_dev_put()
again for the same inet6_dev.

Fix it by moving in6_dev_put() after rt6_uncached_list_del() in
xfrm6_dst_destroy().

Fixes: 510c321b5571 ("xfrm: reuse uncached_list to track xdsts")
Signed-off-by: Zhang Changzhong <zhangchangzhong@huawei.com>
Reviewed-by: Xin Long <lucien.xin@gmail.com>
Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 net/ipv6/xfrm6_policy.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/net/ipv6/xfrm6_policy.c b/net/ipv6/xfrm6_policy.c
index 1925fb91e514..a1dfe4f5ed3a 100644
--- a/net/ipv6/xfrm6_policy.c
+++ b/net/ipv6/xfrm6_policy.c
@@ -243,11 +243,11 @@ static void xfrm6_dst_destroy(struct dst_entry *dst)
 {
 	struct xfrm_dst *xdst = (struct xfrm_dst *)dst;
 
-	if (likely(xdst->u.rt6.rt6i_idev))
-		in6_dev_put(xdst->u.rt6.rt6i_idev);
 	dst_destroy_metrics_generic(dst);
 	if (xdst->u.rt6.rt6i_uncached_list)
 		rt6_uncached_list_del(&xdst->u.rt6);
+	if (likely(xdst->u.rt6.rt6i_idev))
+		in6_dev_put(xdst->u.rt6.rt6i_idev);
 	xfrm_dst_destroy(xdst);
 }
 
-- 
GitLab


From 4a82dfcb8b4d07331d1db05a36f7d87013787e9e Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date: Wed, 25 Oct 2023 11:17:03 +0200
Subject: [PATCH 277/298] Linux 4.19.297

Link: https://lore.kernel.org/r/20231023104813.580375891@linuxfoundation.org
Tested-by: Pavel Machek (CIP) <pavel@denx.de>
Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
Tested-by: Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 002d81755142..72313a351445 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 VERSION = 4
 PATCHLEVEL = 19
-SUBLEVEL = 296
+SUBLEVEL = 297
 EXTRAVERSION =
 NAME = "People's Front"
 
-- 
GitLab


From 3ef5fd7197000eec2728165118407f07d1f410f5 Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman <gregkh@google.com>
Date: Thu, 26 Oct 2023 18:29:18 +0000
Subject: [PATCH 278/298] Revert "xfrm: interface: use DEV_STATS_INC()"

This reverts commit d4d40dc75d861c831779c103151ade62005b74af which is
commit f7c4e3e5d4f6609b4725a97451948ca2e425379a upstream.

It breaks the build due to a previous abi-breaking change being dropped
from the tree.  If this is needed in the future, it can come back in an
abi-safe way.

Change-Id: I5fab397dfff850ab54026e62930bec9b0655cf62
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
---
 net/xfrm/xfrm_interface_core.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/net/xfrm/xfrm_interface_core.c b/net/xfrm/xfrm_interface_core.c
index 10fa26103bdf..40081af62b68 100644
--- a/net/xfrm/xfrm_interface_core.c
+++ b/net/xfrm/xfrm_interface_core.c
@@ -219,8 +219,8 @@ static int xfrmi_rcv_cb(struct sk_buff *skb, int err)
 	skb->dev = dev;
 
 	if (err) {
-		DEV_STATS_INC(dev, rx_errors);
-		DEV_STATS_INC(dev, rx_dropped);
+		dev->stats.rx_errors++;
+		dev->stats.rx_dropped++;
 
 		return 0;
 	}
@@ -260,6 +260,7 @@ static int
 xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl)
 {
 	struct xfrm_if *xi = netdev_priv(dev);
+	struct net_device_stats *stats = &xi->dev->stats;
 	struct dst_entry *dst = skb_dst(skb);
 	unsigned int length = skb->len;
 	struct net_device *tdev;
@@ -285,7 +286,7 @@ xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl)
 	tdev = dst->dev;
 
 	if (tdev == dev) {
-		DEV_STATS_INC(dev, collisions);
+		stats->collisions++;
 		net_warn_ratelimited("%s: Local routing loop detected!\n",
 				     dev->name);
 		goto tx_err_dst_release;
@@ -328,13 +329,13 @@ xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl)
 		tstats->tx_packets++;
 		u64_stats_update_end(&tstats->syncp);
 	} else {
-		DEV_STATS_INC(dev, tx_errors);
-		DEV_STATS_INC(dev, tx_aborted_errors);
+		stats->tx_errors++;
+		stats->tx_aborted_errors++;
 	}
 
 	return 0;
 tx_err_link_failure:
-	DEV_STATS_INC(dev, tx_carrier_errors);
+	stats->tx_carrier_errors++;
 	dst_link_failure(skb);
 tx_err_dst_release:
 	dst_release(dst);
@@ -344,6 +345,7 @@ xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl)
 static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev)
 {
 	struct xfrm_if *xi = netdev_priv(dev);
+	struct net_device_stats *stats = &xi->dev->stats;
 	struct dst_entry *dst = skb_dst(skb);
 	struct flowi fl;
 	int ret;
@@ -360,7 +362,7 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev)
 			dst = ip6_route_output(dev_net(dev), NULL, &fl.u.ip6);
 			if (dst->error) {
 				dst_release(dst);
-				DEV_STATS_INC(dev, tx_carrier_errors);
+				stats->tx_carrier_errors++;
 				goto tx_err;
 			}
 			skb_dst_set(skb, dst);
@@ -376,7 +378,7 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev)
 			fl.u.ip4.flowi4_flags |= FLOWI_FLAG_ANYSRC;
 			rt = __ip_route_output_key(dev_net(dev), &fl.u.ip4);
 			if (IS_ERR(rt)) {
-				DEV_STATS_INC(dev, tx_carrier_errors);
+				stats->tx_carrier_errors++;
 				goto tx_err;
 			}
 			skb_dst_set(skb, &rt->dst);
@@ -395,8 +397,8 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev)
 	return NETDEV_TX_OK;
 
 tx_err:
-	DEV_STATS_INC(dev, tx_errors);
-	DEV_STATS_INC(dev, tx_dropped);
+	stats->tx_errors++;
+	stats->tx_dropped++;
 	kfree_skb(skb);
 	return NETDEV_TX_OK;
 }
-- 
GitLab


From b95e67a557335a14b0ef732708f4bc0f5f7fb773 Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman <gregkh@google.com>
Date: Thu, 26 Oct 2023 10:15:15 +0000
Subject: [PATCH 279/298] Revert "Bluetooth: hci_core: Fix build warnings"

This reverts commit 194ab82c1ea187512ff2f822124bd05b63fc9f76 which is
commit dcda165706b9fbfd685898d46a6749d7d397e0c0 upstream.

It breaks the android ABI and if this is needed in the future, can be
brought back in an abi-safe way.

Bug: 161946584
Change-Id: I4a64dca20bcdfe9cbe33fc23c7d3d1b252f4b873
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
---
 include/net/bluetooth/hci_core.h | 2 +-
 net/bluetooth/hci_core.c         | 8 +++-----
 2 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h
index d3503f8c054e..464a78200a31 100644
--- a/include/net/bluetooth/hci_core.h
+++ b/include/net/bluetooth/hci_core.h
@@ -209,7 +209,7 @@ struct hci_dev {
 	struct list_head list;
 	struct mutex	lock;
 
-	const char	*name;
+	char		name[8];
 	unsigned long	flags;
 	__u16		id;
 	__u8		bus;
diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c
index 4d89e38dceec..9fdc772ab32e 100644
--- a/net/bluetooth/hci_core.c
+++ b/net/bluetooth/hci_core.c
@@ -3193,11 +3193,7 @@ int hci_register_dev(struct hci_dev *hdev)
 	if (id < 0)
 		return id;
 
-	error = dev_set_name(&hdev->dev, "hci%u", id);
-	if (error)
-		return error;
-
-	hdev->name = dev_name(&hdev->dev);
+	snprintf(hdev->name, sizeof(hdev->name), "hci%d", id);
 	hdev->id = id;
 
 	BT_DBG("%p name %s bus %d", hdev, hdev->name, hdev->bus);
@@ -3219,6 +3215,8 @@ int hci_register_dev(struct hci_dev *hdev)
 	if (!IS_ERR_OR_NULL(bt_debugfs))
 		hdev->debugfs = debugfs_create_dir(hdev->name, bt_debugfs);
 
+	dev_set_name(&hdev->dev, "%s", hdev->name);
+
 	error = device_add(&hdev->dev);
 	if (error < 0)
 		goto err_wqueue;
-- 
GitLab


From 1427d077a096af6830c5f79aa2f6663bf908969a Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman <gregkh@google.com>
Date: Thu, 26 Oct 2023 10:16:50 +0000
Subject: [PATCH 280/298] Revert "xfrm: fix a data-race in xfrm_gen_index()"

This reverts commit 17c75411e25a84ed25fe6bbbcf707e1068ff985c which is
commit 3e4bc23926b83c3c67e5f61ae8571602754131a6 upstream.

It breaks the android ABI and if this is needed in the future, can be
brought back in an abi-safe way.

Bug: 161946584
Change-Id: I6af8ce540570c756ea9f16526c36f8815971e216
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
---
 include/net/netns/xfrm.h | 1 -
 net/xfrm/xfrm_policy.c   | 6 ++++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/include/net/netns/xfrm.h b/include/net/netns/xfrm.h
index e3775b260bb3..9991e5ef52cc 100644
--- a/include/net/netns/xfrm.h
+++ b/include/net/netns/xfrm.h
@@ -48,7 +48,6 @@ struct netns_xfrm {
 	struct list_head	policy_all;
 	struct hlist_head	*policy_byidx;
 	unsigned int		policy_idx_hmask;
-	unsigned int		idx_generator;
 	struct hlist_head	policy_inexact[XFRM_POLICY_MAX];
 	struct xfrm_policy_hash	policy_bydst[XFRM_POLICY_MAX];
 	unsigned int		policy_count[XFRM_POLICY_MAX * 2];
diff --git a/net/xfrm/xfrm_policy.c b/net/xfrm/xfrm_policy.c
index c8a7a5739425..6fe578773a51 100644
--- a/net/xfrm/xfrm_policy.c
+++ b/net/xfrm/xfrm_policy.c
@@ -654,6 +654,8 @@ EXPORT_SYMBOL(xfrm_policy_hash_rebuild);
  * of an absolute inpredictability of ordering of rules. This will not pass. */
 static u32 xfrm_gen_index(struct net *net, int dir, u32 index)
 {
+	static u32 idx_generator;
+
 	for (;;) {
 		struct hlist_head *list;
 		struct xfrm_policy *p;
@@ -661,8 +663,8 @@ static u32 xfrm_gen_index(struct net *net, int dir, u32 index)
 		int found;
 
 		if (!index) {
-			idx = (net->xfrm.idx_generator | dir);
-			net->xfrm.idx_generator += 8;
+			idx = (idx_generator | dir);
+			idx_generator += 8;
 		} else {
 			idx = index;
 			index = 0;
-- 
GitLab


From 9c20bfd64d3f79d929a37d70e8aaaad5405d4d6e Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman <gregkh@google.com>
Date: Thu, 26 Oct 2023 10:18:26 +0000
Subject: [PATCH 281/298] Revert "perf: Disallow mis-matched inherited group
 reads"

This reverts commit a714491fa92d2068358dd603cc50bf2062517bd8 which is
commit 32671e3799ca2e4590773fd0e63aaa4229e50c06 upstream.

It breaks the android ABI and if this is needed in the future, can be
brought back in an abi-safe way.

Bug: 161946584
Change-Id: Ia00890aeeef6153c7f3462a2a2189149734ac28a
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
---
 include/linux/perf_event.h |  1 -
 kernel/events/core.c       | 39 ++++++--------------------------------
 2 files changed, 6 insertions(+), 34 deletions(-)

diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 090ac3be7ab7..bac97441074a 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -597,7 +597,6 @@ struct perf_event {
 	/* The cumulative AND of all event_caps for events in this group. */
 	int				group_caps;
 
-	unsigned int			group_generation;
 	struct perf_event		*group_leader;
 	struct pmu			*pmu;
 	void				*pmu_private;
diff --git a/kernel/events/core.c b/kernel/events/core.c
index cb9b49a5d71c..5fc26042a906 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -1848,7 +1848,6 @@ static void perf_group_attach(struct perf_event *event)
 
 	list_add_tail(&event->sibling_list, &group_leader->sibling_list);
 	group_leader->nr_siblings++;
-	group_leader->group_generation++;
 
 	perf_event__header_size(group_leader);
 
@@ -1919,7 +1918,6 @@ static void perf_group_detach(struct perf_event *event)
 	if (event->group_leader != event) {
 		list_del_init(&event->sibling_list);
 		event->group_leader->nr_siblings--;
-		event->group_leader->group_generation++;
 		goto out;
 	}
 
@@ -4738,7 +4736,7 @@ static int __perf_read_group_add(struct perf_event *leader,
 					u64 read_format, u64 *values)
 {
 	struct perf_event_context *ctx = leader->ctx;
-	struct perf_event *sub, *parent;
+	struct perf_event *sub;
 	unsigned long flags;
 	int n = 1; /* skip @nr */
 	int ret;
@@ -4748,33 +4746,6 @@ static int __perf_read_group_add(struct perf_event *leader,
 		return ret;
 
 	raw_spin_lock_irqsave(&ctx->lock, flags);
-	/*
-	 * Verify the grouping between the parent and child (inherited)
-	 * events is still in tact.
-	 *
-	 * Specifically:
-	 *  - leader->ctx->lock pins leader->sibling_list
-	 *  - parent->child_mutex pins parent->child_list
-	 *  - parent->ctx->mutex pins parent->sibling_list
-	 *
-	 * Because parent->ctx != leader->ctx (and child_list nests inside
-	 * ctx->mutex), group destruction is not atomic between children, also
-	 * see perf_event_release_kernel(). Additionally, parent can grow the
-	 * group.
-	 *
-	 * Therefore it is possible to have parent and child groups in a
-	 * different configuration and summing over such a beast makes no sense
-	 * what so ever.
-	 *
-	 * Reject this.
-	 */
-	parent = leader->parent;
-	if (parent &&
-	    (parent->group_generation != leader->group_generation ||
-	     parent->nr_siblings != leader->nr_siblings)) {
-		ret = -ECHILD;
-		goto unlock;
-	}
 
 	/*
 	 * Since we co-schedule groups, {enabled,running} times of siblings
@@ -4804,9 +4775,8 @@ static int __perf_read_group_add(struct perf_event *leader,
 			values[n++] = primary_event_id(sub);
 	}
 
-unlock:
 	raw_spin_unlock_irqrestore(&ctx->lock, flags);
-	return ret;
+	return 0;
 }
 
 static int perf_read_group(struct perf_event *event,
@@ -4825,6 +4795,10 @@ static int perf_read_group(struct perf_event *event,
 
 	values[0] = 1 + leader->nr_siblings;
 
+	/*
+	 * By locking the child_mutex of the leader we effectively
+	 * lock the child list of all siblings.. XXX explain how.
+	 */
 	mutex_lock(&leader->child_mutex);
 
 	ret = __perf_read_group_add(leader, read_format, values);
@@ -11613,7 +11587,6 @@ static int inherit_group(struct perf_event *parent_event,
 		if (IS_ERR(child_ctr))
 			return PTR_ERR(child_ctr);
 	}
-	leader->group_generation = parent_event->group_generation;
 	return 0;
 }
 
-- 
GitLab


From 9a12a0dfcaa32afe8ce4ea2aec418331c8032712 Mon Sep 17 00:00:00 2001
From: Alessio Balsini <balsini@google.com>
Date: Thu, 4 Feb 2021 17:59:23 +0000
Subject: [PATCH 282/298] BACKPORT: fs: align IOCB_* flags with RWF_* flags

We have a set of flags that are shared between the two and inherired
in kiocb_set_rw_flags(), but we check and set these individually.
Reorder the IOCB flags so that the bottom part of the space is synced
with the RWF flag space, and then we can do them all in one mask and
set operation.

The only exception is RWF_SYNC, which needs to mark IOCB_SYNC and
IOCB_DSYNC. Do that one separately.

This shaves 15 bytes of text from kiocb_set_rw_flags() for me.

(cherry picked from commit ce71bfea207b4d7c21d36f24ec37618ffcea1da8)
Suggested-by: Matthew Wilcox (Oracle) <willy@infradead.org>
Signed-off-by: Jens Axboe <axboe@kernel.dk>
Change-Id: Ib6316ae5cb3f8a14fabef5492e79783c9e6d3c4d
Signed-off-by: Alessio Balsini <balsini@google.com>
---
 include/linux/fs.h | 42 ++++++++++++++++++++++++++----------------
 1 file changed, 26 insertions(+), 16 deletions(-)

diff --git a/include/linux/fs.h b/include/linux/fs.h
index d01fc2c6a40a..c3fb84f748c4 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -299,14 +299,20 @@ enum rw_hint {
 	WRITE_LIFE_EXTREME	= RWH_WRITE_LIFE_EXTREME,
 };
 
-#define IOCB_EVENTFD		(1 << 0)
-#define IOCB_APPEND		(1 << 1)
-#define IOCB_DIRECT		(1 << 2)
-#define IOCB_HIPRI		(1 << 3)
-#define IOCB_DSYNC		(1 << 4)
-#define IOCB_SYNC		(1 << 5)
-#define IOCB_WRITE		(1 << 6)
-#define IOCB_NOWAIT		(1 << 7)
+/* Match RWF_* bits to IOCB bits */
+#define IOCB_HIPRI		(__force int) RWF_HIPRI
+#define IOCB_DSYNC		(__force int) RWF_DSYNC
+#define IOCB_SYNC		(__force int) RWF_SYNC
+#define IOCB_NOWAIT		(__force int) RWF_NOWAIT
+#define IOCB_APPEND		(__force int) RWF_APPEND
+
+/* non-RWF related bits - start at 16 */
+#define IOCB_EVENTFD		(1 << 16)
+#define IOCB_DIRECT		(1 << 17)
+#define IOCB_WRITE		(1 << 18)
+/* iocb->ki_waitq is valid */
+#define IOCB_WAITQ		(1 << 19)
+#define IOCB_NOIO		(1 << 20)
 
 struct kiocb {
 	struct file		*ki_filp;
@@ -3400,22 +3406,26 @@ static inline int iocb_flags(struct file *file)
 
 static inline int kiocb_set_rw_flags(struct kiocb *ki, rwf_t flags)
 {
+	int kiocb_flags = 0;
+
+	/* make sure there's no overlap between RWF and private IOCB flags */
+	BUILD_BUG_ON((__force int)RWF_SUPPORTED & IOCB_EVENTFD);
+
+	if (!flags)
+		return 0;
 	if (unlikely(flags & ~RWF_SUPPORTED))
 		return -EOPNOTSUPP;
 
 	if (flags & RWF_NOWAIT) {
 		if (!(ki->ki_filp->f_mode & FMODE_NOWAIT))
 			return -EOPNOTSUPP;
-		ki->ki_flags |= IOCB_NOWAIT;
+		kiocb_flags |= IOCB_NOIO;
 	}
-	if (flags & RWF_HIPRI)
-		ki->ki_flags |= IOCB_HIPRI;
-	if (flags & RWF_DSYNC)
-		ki->ki_flags |= IOCB_DSYNC;
+	kiocb_flags |= (__force int)(flags & RWF_SUPPORTED);
 	if (flags & RWF_SYNC)
-		ki->ki_flags |= (IOCB_DSYNC | IOCB_SYNC);
-	if (flags & RWF_APPEND)
-		ki->ki_flags |= IOCB_APPEND;
+		kiocb_flags |= IOCB_DSYNC;
+
+	ki->ki_flags |= kiocb_flags;
 	return 0;
 }
 
-- 
GitLab


From 8aca09569693cd9b07fa8642a3792601079f6b0f Mon Sep 17 00:00:00 2001
From: Alessio Balsini <balsini@google.com>
Date: Mon, 25 Jan 2021 16:58:50 +0000
Subject: [PATCH 283/298] FROMLIST: fs: Generic function to convert iocb to rw
 flags

OverlayFS implements its own function to translate iocb flags into rw
flags, so that they can be passed into another vfs call.
With commit ce71bfea207b4 ("fs: align IOCB_* flags with RWF_* flags")
Jens created a 1:1 matching between the iocb flags and rw flags,
simplifying the conversion.

Reduce the OverlayFS code by making the flag conversion function generic
and reusable.

Bug: 179164095
Link: https://lore.kernel.org/lkml/20210125153057.3623715-2-balsini@android.com/
Signed-off-by: Alessio Balsini <balsini@android.com>
Change-Id: I74aefeafd6ebbda2fbabee9024474dfe4cc6c2a7
Signed-off-by: Alessio Balsini <balsini@google.com>
---
 fs/overlayfs/file.c | 23 ++++-------------------
 include/linux/fs.h  |  5 +++++
 2 files changed, 9 insertions(+), 19 deletions(-)

diff --git a/fs/overlayfs/file.c b/fs/overlayfs/file.c
index 818a8ee4357b..7e22ae7a83bc 100644
--- a/fs/overlayfs/file.c
+++ b/fs/overlayfs/file.c
@@ -14,6 +14,8 @@
 #include <linux/uaccess.h>
 #include "overlayfs.h"
 
+#define OVL_IOCB_MASK (IOCB_DSYNC | IOCB_HIPRI | IOCB_NOWAIT | IOCB_SYNC)
+
 static char ovl_whatisit(struct inode *inode, struct inode *realinode)
 {
 	if (realinode != ovl_inode_upper(inode))
@@ -213,23 +215,6 @@ static void ovl_file_accessed(struct file *file)
 	touch_atime(&file->f_path);
 }
 
-static rwf_t ovl_iocb_to_rwf(struct kiocb *iocb)
-{
-	int ifl = iocb->ki_flags;
-	rwf_t flags = 0;
-
-	if (ifl & IOCB_NOWAIT)
-		flags |= RWF_NOWAIT;
-	if (ifl & IOCB_HIPRI)
-		flags |= RWF_HIPRI;
-	if (ifl & IOCB_DSYNC)
-		flags |= RWF_DSYNC;
-	if (ifl & IOCB_SYNC)
-		flags |= RWF_SYNC;
-
-	return flags;
-}
-
 static ssize_t ovl_read_iter(struct kiocb *iocb, struct iov_iter *iter)
 {
 	struct file *file = iocb->ki_filp;
@@ -246,7 +231,7 @@ static ssize_t ovl_read_iter(struct kiocb *iocb, struct iov_iter *iter)
 
 	old_cred = ovl_override_creds(file_inode(file)->i_sb);
 	ret = vfs_iter_read(real.file, iter, &iocb->ki_pos,
-			    ovl_iocb_to_rwf(iocb));
+			    iocb_to_rw_flags(iocb->ki_flags, OVL_IOCB_MASK));
 	ovl_revert_creds(old_cred);
 
 	ovl_file_accessed(file);
@@ -281,7 +266,7 @@ static ssize_t ovl_write_iter(struct kiocb *iocb, struct iov_iter *iter)
 	old_cred = ovl_override_creds(file_inode(file)->i_sb);
 	file_start_write(real.file);
 	ret = vfs_iter_write(real.file, iter, &iocb->ki_pos,
-			     ovl_iocb_to_rwf(iocb));
+			     iocb_to_rw_flags(iocb->ki_flags, OVL_IOCB_MASK));
 	file_end_write(real.file);
 	ovl_revert_creds(old_cred);
 
diff --git a/include/linux/fs.h b/include/linux/fs.h
index c3fb84f748c4..bd0fc51c708d 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -3429,6 +3429,11 @@ static inline int kiocb_set_rw_flags(struct kiocb *ki, rwf_t flags)
 	return 0;
 }
 
+static inline rwf_t iocb_to_rw_flags(int ifl, int iocb_mask)
+{
+	return ifl & iocb_mask;
+}
+
 static inline ino_t parent_ino(struct dentry *dentry)
 {
 	ino_t res;
-- 
GitLab


From 759f0722974a44d3aac67f8d6a2a53e5d1571fe9 Mon Sep 17 00:00:00 2001
From: Alessio Balsini <balsini@google.com>
Date: Mon, 25 Jan 2021 17:01:30 +0000
Subject: [PATCH 284/298] FROMLIST: fuse: 32-bit user space ioctl compat for
 fuse device

With a 64-bit kernel build the FUSE device cannot handle ioctl requests
coming from 32-bit user space.
This is due to the ioctl command translation that generates different
command identifiers that thus cannot be used for direct comparisons
without proper manipulation.

Explicitly extract type and number from the ioctl command to enable
32-bit user space compatibility on 64-bit kernel builds.

Bug: 179164095
Link: https://lore.kernel.org/lkml/20210125153057.3623715-3-balsini@android.com/
Signed-off-by: Alessio Balsini <balsini@android.com>
Change-Id: I595517c54d551be70e83c7fcb4b62397a3615004
Signed-off-by: Alessio Balsini <balsini@google.com>
---
 fs/fuse/dev.c             | 29 ++++++++++++++++++-----------
 include/uapi/linux/fuse.h |  3 ++-
 2 files changed, 20 insertions(+), 12 deletions(-)

diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c
index 39b11571bcef..2d6cb9705149 100644
--- a/fs/fuse/dev.c
+++ b/fs/fuse/dev.c
@@ -2290,37 +2290,44 @@ static int fuse_device_clone(struct fuse_conn *fc, struct file *new)
 static long fuse_dev_ioctl(struct file *file, unsigned int cmd,
 			   unsigned long arg)
 {
-	int err = -ENOTTY;
+	int res;
+	int oldfd;
+	struct fuse_dev *fud = NULL;
 
-	if (cmd == FUSE_DEV_IOC_CLONE) {
-		int oldfd;
+	if (_IOC_TYPE(cmd) != FUSE_DEV_IOC_MAGIC)
+		return -EINVAL;
 
-		err = -EFAULT;
-		if (!get_user(oldfd, (__u32 __user *) arg)) {
+	switch (_IOC_NR(cmd)) {
+	case _IOC_NR(FUSE_DEV_IOC_CLONE):
+		res = -EFAULT;
+		if (!get_user(oldfd, (__u32 __user *)arg)) {
 			struct file *old = fget(oldfd);
 
-			err = -EINVAL;
+			res = -EINVAL;
 			if (old) {
-				struct fuse_dev *fud = NULL;
-
 				/*
 				 * Check against file->f_op because CUSE
 				 * uses the same ioctl handler.
 				 */
 				if (old->f_op == file->f_op &&
-				    old->f_cred->user_ns == file->f_cred->user_ns)
+				    old->f_cred->user_ns ==
+					    file->f_cred->user_ns)
 					fud = fuse_get_dev(old);
 
 				if (fud) {
 					mutex_lock(&fuse_mutex);
-					err = fuse_device_clone(fud->fc, file);
+					res = fuse_device_clone(fud->fc, file);
 					mutex_unlock(&fuse_mutex);
 				}
 				fput(old);
 			}
 		}
+		break;
+	default:
+		res = -ENOTTY;
+		break;
 	}
-	return err;
+	return res;
 }
 
 const struct file_operations fuse_dev_operations = {
diff --git a/include/uapi/linux/fuse.h b/include/uapi/linux/fuse.h
index 24af4edfc98c..c155f7d08606 100644
--- a/include/uapi/linux/fuse.h
+++ b/include/uapi/linux/fuse.h
@@ -782,7 +782,8 @@ struct fuse_notify_retrieve_in {
 };
 
 /* Device ioctls: */
-#define FUSE_DEV_IOC_CLONE	_IOR(229, 0, uint32_t)
+#define FUSE_DEV_IOC_MAGIC		229
+#define FUSE_DEV_IOC_CLONE		_IOR(FUSE_DEV_IOC_MAGIC, 0, uint32_t)
 
 struct fuse_lseek_in {
 	uint64_t	fh;
-- 
GitLab


From 0d86dc020b476b0084bccf74c73913f65762ca90 Mon Sep 17 00:00:00 2001
From: Alessio Balsini <balsini@google.com>
Date: Mon, 25 Jan 2021 17:02:28 +0000
Subject: [PATCH 285/298] FROMLIST: fuse: Definitions and ioctl for passthrough

Expose the FUSE_PASSTHROUGH interface to user space and declare all the
basic data structures and functions as the skeleton on top of which the
FUSE passthrough functionality will be built.

As part of this, introduce the new FUSE passthrough ioctl, which allows
the FUSE daemon to specify a direct connection between a FUSE file and a
lower file system file. Such ioctl requires user space to pass the file
descriptor of one of its opened files through the fuse_passthrough_out
data structure introduced in this patch. This structure includes extra
fields for possible future extensions.
Also, add the passthrough functions for the set-up and tear-down of the
data structures and locks that will be used both when fuse_conns and
fuse_files are created/deleted.

Bug: 179164095
Link: https://lore.kernel.org/lkml/20210125153057.3623715-4-balsini@android.com/
Signed-off-by: Alessio Balsini <balsini@android.com>
Change-Id: I732532581348adadda5b5048a9346c2b0868d539
Signed-off-by: Alessio Balsini <balsini@google.com>
---
 fs/fuse/Makefile          |  1 +
 fs/fuse/dev.c             | 12 ++++++++++++
 fs/fuse/dir.c             |  1 +
 fs/fuse/file.c            |  4 +++-
 fs/fuse/fuse_i.h          | 27 +++++++++++++++++++++++++++
 fs/fuse/inode.c           | 17 ++++++++++++++++-
 fs/fuse/passthrough.c     | 21 +++++++++++++++++++++
 include/uapi/linux/fuse.h | 13 ++++++++++++-
 8 files changed, 93 insertions(+), 3 deletions(-)
 create mode 100644 fs/fuse/passthrough.c

diff --git a/fs/fuse/Makefile b/fs/fuse/Makefile
index 60da84a86dab..9b0821548ab4 100644
--- a/fs/fuse/Makefile
+++ b/fs/fuse/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_FUSE_FS) += fuse.o
 obj-$(CONFIG_CUSE) += cuse.o
 
 fuse-objs := dev.o dir.o file.o inode.o control.o xattr.o acl.o
+fuse-objs += passthrough.o
diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c
index 2d6cb9705149..08dcd7102159 100644
--- a/fs/fuse/dev.c
+++ b/fs/fuse/dev.c
@@ -2293,6 +2293,7 @@ static long fuse_dev_ioctl(struct file *file, unsigned int cmd,
 	int res;
 	int oldfd;
 	struct fuse_dev *fud = NULL;
+	struct fuse_passthrough_out pto;
 
 	if (_IOC_TYPE(cmd) != FUSE_DEV_IOC_MAGIC)
 		return -EINVAL;
@@ -2323,6 +2324,17 @@ static long fuse_dev_ioctl(struct file *file, unsigned int cmd,
 			}
 		}
 		break;
+	case _IOC_NR(FUSE_DEV_IOC_PASSTHROUGH_OPEN):
+		res = -EFAULT;
+		if (!copy_from_user(&pto,
+				    (struct fuse_passthrough_out __user *)arg,
+				    sizeof(pto))) {
+			res = -EINVAL;
+			fud = fuse_get_dev(file);
+			if (fud)
+				res = fuse_passthrough_open(fud, &pto);
+		}
+		break;
 	default:
 		res = -ENOTTY;
 		break;
diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c
index 6b25788ab9bc..77824b96514c 100644
--- a/fs/fuse/dir.c
+++ b/fs/fuse/dir.c
@@ -508,6 +508,7 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry,
 	ff->fh = outopen.fh;
 	ff->nodeid = outentry.nodeid;
 	ff->open_flags = outopen.open_flags;
+	fuse_passthrough_setup(fc, ff, &outopen);
 	inode = fuse_iget(dir->i_sb, outentry.nodeid, outentry.generation,
 			  &outentry.attr, entry_attr_timeout(&outentry), 0);
 	if (!inode) {
diff --git a/fs/fuse/file.c b/fs/fuse/file.c
index 549979a0bb9d..1cc8c9753251 100644
--- a/fs/fuse/file.c
+++ b/fs/fuse/file.c
@@ -136,7 +136,7 @@ int fuse_do_open(struct fuse_conn *fc, u64 nodeid, struct file *file,
 		if (!err) {
 			ff->fh = outarg.fh;
 			ff->open_flags = outarg.open_flags;
-
+			fuse_passthrough_setup(fc, ff, &outarg);
 		} else if (err != -ENOSYS || isdir) {
 			fuse_file_free(ff);
 			return err;
@@ -264,6 +264,8 @@ void fuse_release_common(struct file *file, bool isdir)
 	struct fuse_req *req = ff->reserved_req;
 	int opcode = isdir ? FUSE_RELEASEDIR : FUSE_RELEASE;
 
+	fuse_passthrough_release(&ff->passthrough);
+
 	fuse_prepare_release(ff, file->f_flags, opcode);
 
 	if (ff->flock) {
diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h
index 3704ae529737..78416b079431 100644
--- a/fs/fuse/fuse_i.h
+++ b/fs/fuse/fuse_i.h
@@ -124,6 +124,14 @@ enum {
 
 struct fuse_conn;
 
+/**
+ * Reference to lower filesystem file for read/write operations handled in
+ * passthrough mode
+ */
+struct fuse_passthrough {
+	struct file *filp;
+};
+
 /** FUSE specific file data */
 struct fuse_file {
 	/** Fuse connection for this file */
@@ -150,6 +158,9 @@ struct fuse_file {
 	/** Entry on inode's write_files list */
 	struct list_head write_entry;
 
+	/** Container for data related to the passthrough functionality */
+	struct fuse_passthrough passthrough;
+
 	/** RB node to be linked on fuse_conn->polled_files */
 	struct rb_node polled_node;
 
@@ -650,6 +661,9 @@ struct fuse_conn {
 	/** Allow other than the mounter user to access the filesystem ? */
 	unsigned allow_other:1;
 
+	/** Passthrough mode for read/write IO */
+	unsigned int passthrough:1;
+
 	/** The number of requests waiting for completion */
 	atomic_t num_waiting;
 
@@ -688,6 +702,12 @@ struct fuse_conn {
 
 	/** List of device instances belonging to this connection */
 	struct list_head devices;
+
+	/** IDR for passthrough requests */
+	struct idr passthrough_req;
+
+	/** Protects passthrough_req */
+	spinlock_t passthrough_req_lock;
 };
 
 static inline struct fuse_conn *get_fuse_conn_super(struct super_block *sb)
@@ -1019,4 +1039,11 @@ struct posix_acl;
 struct posix_acl *fuse_get_acl(struct inode *inode, int type);
 int fuse_set_acl(struct inode *inode, struct posix_acl *acl, int type);
 
+/* passthrough.c */
+int fuse_passthrough_open(struct fuse_dev *fud,
+			  struct fuse_passthrough_out *pto);
+int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff,
+			   struct fuse_open_out *openarg);
+void fuse_passthrough_release(struct fuse_passthrough *passthrough);
+
 #endif /* _FS_FUSE_I_H */
diff --git a/fs/fuse/inode.c b/fs/fuse/inode.c
index 57208ff9ccc8..95c3519cf726 100644
--- a/fs/fuse/inode.c
+++ b/fs/fuse/inode.c
@@ -615,6 +615,7 @@ void fuse_conn_init(struct fuse_conn *fc, struct user_namespace *user_ns)
 {
 	memset(fc, 0, sizeof(*fc));
 	spin_lock_init(&fc->lock);
+	spin_lock_init(&fc->passthrough_req_lock);
 	init_rwsem(&fc->killsb);
 	refcount_set(&fc->count, 1);
 	atomic_set(&fc->dev_count, 1);
@@ -624,6 +625,7 @@ void fuse_conn_init(struct fuse_conn *fc, struct user_namespace *user_ns)
 	INIT_LIST_HEAD(&fc->bg_queue);
 	INIT_LIST_HEAD(&fc->entry);
 	INIT_LIST_HEAD(&fc->devices);
+	idr_init(&fc->passthrough_req);
 	atomic_set(&fc->num_waiting, 0);
 	fc->max_background = FUSE_DEFAULT_MAX_BACKGROUND;
 	fc->congestion_threshold = FUSE_DEFAULT_CONGESTION_THRESHOLD;
@@ -936,6 +938,12 @@ static void process_init_reply(struct fuse_conn *fc, struct fuse_req *req)
 			}
 			if (arg->flags & FUSE_ABORT_ERROR)
 				fc->abort_err = 1;
+			if (arg->flags & FUSE_PASSTHROUGH) {
+				fc->passthrough = 1;
+				/* Prevent further stacking */
+				fc->sb->s_stack_depth =
+					FILESYSTEM_MAX_STACK_DEPTH;
+			}
 		} else {
 			ra_pages = fc->max_read / PAGE_SIZE;
 			fc->no_lock = 1;
@@ -967,7 +975,7 @@ static void fuse_send_init(struct fuse_conn *fc, struct fuse_req *req)
 		FUSE_DO_READDIRPLUS | FUSE_READDIRPLUS_AUTO | FUSE_ASYNC_DIO |
 		FUSE_WRITEBACK_CACHE | FUSE_NO_OPEN_SUPPORT |
 		FUSE_PARALLEL_DIROPS | FUSE_HANDLE_KILLPRIV | FUSE_POSIX_ACL |
-		FUSE_ABORT_ERROR;
+		FUSE_ABORT_ERROR | FUSE_PASSTHROUGH;
 	req->in.h.opcode = FUSE_INIT;
 	req->in.numargs = 1;
 	req->in.args[0].size = sizeof(*arg);
@@ -983,9 +991,16 @@ static void fuse_send_init(struct fuse_conn *fc, struct fuse_req *req)
 	fuse_request_send_background(fc, req);
 }
 
+static int free_fuse_passthrough(int id, void *p, void *data)
+{
+	return 0;
+}
+
 static void fuse_free_conn(struct fuse_conn *fc)
 {
 	WARN_ON(!list_empty(&fc->devices));
+	idr_for_each(&fc->passthrough_req, free_fuse_passthrough, NULL);
+	idr_destroy(&fc->passthrough_req);
 	kfree_rcu(fc, rcu);
 }
 
diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c
new file mode 100644
index 000000000000..594060c654f8
--- /dev/null
+++ b/fs/fuse/passthrough.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "fuse_i.h"
+
+#include <linux/fuse.h>
+
+int fuse_passthrough_open(struct fuse_dev *fud,
+			  struct fuse_passthrough_out *pto)
+{
+	return -EINVAL;
+}
+
+int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff,
+			   struct fuse_open_out *openarg)
+{
+	return -EINVAL;
+}
+
+void fuse_passthrough_release(struct fuse_passthrough *passthrough)
+{
+}
diff --git a/include/uapi/linux/fuse.h b/include/uapi/linux/fuse.h
index c155f7d08606..6184f67ede10 100644
--- a/include/uapi/linux/fuse.h
+++ b/include/uapi/linux/fuse.h
@@ -274,6 +274,7 @@ struct fuse_file_lock {
 #define FUSE_HANDLE_KILLPRIV	(1 << 19)
 #define FUSE_POSIX_ACL		(1 << 20)
 #define FUSE_ABORT_ERROR	(1 << 21)
+#define FUSE_PASSTHROUGH	(1 << 31)
 
 /**
  * CUSE INIT request/reply flags
@@ -506,7 +507,7 @@ struct fuse_create_in {
 struct fuse_open_out {
 	uint64_t	fh;
 	uint32_t	open_flags;
-	uint32_t	padding;
+	uint32_t	passthrough_fh;
 };
 
 struct fuse_release_in {
@@ -707,6 +708,14 @@ struct fuse_in_header {
 	uint32_t	padding;
 };
 
+/* fuse_passthrough_out for passthrough V1 */
+struct fuse_passthrough_out {
+	uint32_t	fd;
+	/* For future implementation */
+	uint32_t	len;
+	void		*vec;
+};
+
 struct fuse_out_header {
 	uint32_t	len;
 	int32_t		error;
@@ -784,6 +793,8 @@ struct fuse_notify_retrieve_in {
 /* Device ioctls: */
 #define FUSE_DEV_IOC_MAGIC		229
 #define FUSE_DEV_IOC_CLONE		_IOR(FUSE_DEV_IOC_MAGIC, 0, uint32_t)
+/* 127 is reserved for the V1 interface implementation in Android */
+#define FUSE_DEV_IOC_PASSTHROUGH_OPEN	_IOW(FUSE_DEV_IOC_MAGIC, 127, struct fuse_passthrough_out)
 
 struct fuse_lseek_in {
 	uint64_t	fh;
-- 
GitLab


From 78d08aa2c6e771df3aba105d43f2921936bc41c0 Mon Sep 17 00:00:00 2001
From: Alessio Balsini <balsini@google.com>
Date: Mon, 25 Jan 2021 17:02:57 +0000
Subject: [PATCH 286/298] FROMLIST: fuse: Passthrough initialization and
 release

Implement the FUSE passthrough ioctl that associates the lower
(passthrough) file system file with the fuse_file.

The file descriptor passed to the ioctl by the FUSE daemon is used to
access the relative file pointer, that will be copied to the fuse_file
data structure to consolidate the link between the FUSE and lower file
system.

To enable the passthrough mode, user space triggers the
FUSE_DEV_IOC_PASSTHROUGH_OPEN ioctl and, if the call succeeds, receives
back an identifier that will be used at open/create response time in the
fuse_open_out field to associate the FUSE file to the lower file system
file.
The value returned by the ioctl to user space can be:
- > 0: success, the identifier can be used as part of an open/create
reply.
- <= 0: an error occurred.
The value 0 represents an error to preserve backward compatibility: the
fuse_open_out field that is used to pass the passthrough_fh back to the
kernel uses the same bits that were previously as struct padding, and is
commonly zero-initialized (e.g., in the libfuse implementation).
Removing 0 from the correct values fixes the ambiguity between the case
in which 0 corresponds to a real passthrough_fh, a missing
implementation of FUSE passthrough or a request for a normal FUSE file,
simplifying the user space implementation.

For the passthrough mode to be successfully activated, the lower file
system file must implement both read_iter and write_iter file
operations. This extra check avoids special pseudo files to be targeted
for this feature.
Passthrough comes with another limitation: no further file system
stacking is allowed for those FUSE file systems using passthrough.

Bug: 179164095
Link: https://lore.kernel.org/lkml/20210125153057.3623715-5-balsini@android.com/
Signed-off-by: Alessio Balsini <balsini@android.com>
Change-Id: I4d8290012302fb4547bce9bb261a03cc4f66b5aa
Signed-off-by: Alessio Balsini <balsini@google.com>
---
 fs/fuse/inode.c       |  5 +++
 fs/fuse/passthrough.c | 88 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 91 insertions(+), 2 deletions(-)

diff --git a/fs/fuse/inode.c b/fs/fuse/inode.c
index 95c3519cf726..9754c437dc60 100644
--- a/fs/fuse/inode.c
+++ b/fs/fuse/inode.c
@@ -993,6 +993,11 @@ static void fuse_send_init(struct fuse_conn *fc, struct fuse_req *req)
 
 static int free_fuse_passthrough(int id, void *p, void *data)
 {
+	struct fuse_passthrough *passthrough = (struct fuse_passthrough *)p;
+
+	fuse_passthrough_release(passthrough);
+	kfree(p);
+
 	return 0;
 }
 
diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c
index 594060c654f8..b2a19e18a319 100644
--- a/fs/fuse/passthrough.c
+++ b/fs/fuse/passthrough.c
@@ -2,20 +2,104 @@
 
 #include "fuse_i.h"
 
+#include <linux/file.h>
 #include <linux/fuse.h>
+#include <linux/idr.h>
 
 int fuse_passthrough_open(struct fuse_dev *fud,
 			  struct fuse_passthrough_out *pto)
 {
-	return -EINVAL;
+	int res;
+	struct file *passthrough_filp;
+	struct fuse_conn *fc = fud->fc;
+	struct inode *passthrough_inode;
+	struct super_block *passthrough_sb;
+	struct fuse_passthrough *passthrough;
+
+	if (!fc->passthrough)
+		return -EPERM;
+
+	/* This field is reserved for future implementation */
+	if (pto->len != 0)
+		return -EINVAL;
+
+	passthrough_filp = fget(pto->fd);
+	if (!passthrough_filp) {
+		pr_err("FUSE: invalid file descriptor for passthrough.\n");
+		return -EBADF;
+	}
+
+	if (!passthrough_filp->f_op->read_iter ||
+	    !passthrough_filp->f_op->write_iter) {
+		pr_err("FUSE: passthrough file misses file operations.\n");
+		res = -EBADF;
+		goto err_free_file;
+	}
+
+	passthrough_inode = file_inode(passthrough_filp);
+	passthrough_sb = passthrough_inode->i_sb;
+	if (passthrough_sb->s_stack_depth >= FILESYSTEM_MAX_STACK_DEPTH) {
+		pr_err("FUSE: fs stacking depth exceeded for passthrough\n");
+		res = -EINVAL;
+		goto err_free_file;
+	}
+
+	passthrough = kmalloc(sizeof(struct fuse_passthrough), GFP_KERNEL);
+	if (!passthrough) {
+		res = -ENOMEM;
+		goto err_free_file;
+	}
+
+	passthrough->filp = passthrough_filp;
+
+	idr_preload(GFP_KERNEL);
+	spin_lock(&fc->passthrough_req_lock);
+	res = idr_alloc(&fc->passthrough_req, passthrough, 1, 0, GFP_ATOMIC);
+	spin_unlock(&fc->passthrough_req_lock);
+	idr_preload_end();
+
+	if (res > 0)
+		return res;
+
+	fuse_passthrough_release(passthrough);
+	kfree(passthrough);
+
+err_free_file:
+	fput(passthrough_filp);
+
+	return res;
 }
 
 int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff,
 			   struct fuse_open_out *openarg)
 {
-	return -EINVAL;
+	struct fuse_passthrough *passthrough;
+	int passthrough_fh = openarg->passthrough_fh;
+
+	if (!fc->passthrough)
+		return -EPERM;
+
+	/* Default case, passthrough is not requested */
+	if (passthrough_fh <= 0)
+		return -EINVAL;
+
+	spin_lock(&fc->passthrough_req_lock);
+	passthrough = idr_remove(&fc->passthrough_req, passthrough_fh);
+	spin_unlock(&fc->passthrough_req_lock);
+
+	if (!passthrough)
+		return -EINVAL;
+
+	ff->passthrough = *passthrough;
+	kfree(passthrough);
+
+	return 0;
 }
 
 void fuse_passthrough_release(struct fuse_passthrough *passthrough)
 {
+	if (passthrough->filp) {
+		fput(passthrough->filp);
+		passthrough->filp = NULL;
+	}
 }
-- 
GitLab


From b3825c61231be4ee591283c55d0996f731c50511 Mon Sep 17 00:00:00 2001
From: Alessio Balsini <balsini@google.com>
Date: Mon, 25 Jan 2021 17:03:31 +0000
Subject: [PATCH 287/298] FROMLIST: fuse: Introduce synchronous read and write
 for passthrough

All the read and write operations performed on fuse_files which have the
passthrough feature enabled are forwarded to the associated lower file
system file via VFS.

Sending the request directly to the lower file system avoids the
userspace round-trip that, because of possible context switches and
additional operations might reduce the overall performance, especially
in those cases where caching doesn't help, for example in reads at
random offsets.

Verifying if a fuse_file has a lower file system file associated with
can be done by checking the validity of its passthrough_filp pointer.
This pointer is not NULL only if passthrough has been successfully
enabled via the appropriate ioctl().
When a read/write operation is requested for a FUSE file with
passthrough enabled, a new equivalent VFS request is generated, which
instead targets the lower file system file.
The VFS layer performs additional checks that allow for safer operations
but may cause the operation to fail if the process accessing the FUSE
file system does not have access to the lower file system.

This change only implements synchronous requests in passthrough,
returning an error in the case of asynchronous operations, yet covering
the majority of the use cases.

Bug: 179164095
Link: https://lore.kernel.org/lkml/20210125153057.3623715-6-balsini@android.com/
Signed-off-by: Alessio Balsini <balsini@android.com>
Change-Id: Ifbe6a247fe7338f87d078fde923f0252eeaeb668
Signed-off-by: Alessio Balsini <balsini@google.com>
---
 fs/fuse/file.c        |  7 ++++++
 fs/fuse/fuse_i.h      |  2 ++
 fs/fuse/passthrough.c | 57 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 66 insertions(+)

diff --git a/fs/fuse/file.c b/fs/fuse/file.c
index 1cc8c9753251..93f3b91ad9ce 100644
--- a/fs/fuse/file.c
+++ b/fs/fuse/file.c
@@ -935,6 +935,7 @@ static ssize_t fuse_file_read_iter(struct kiocb *iocb, struct iov_iter *to)
 {
 	struct inode *inode = iocb->ki_filp->f_mapping->host;
 	struct fuse_conn *fc = get_fuse_conn(inode);
+	struct fuse_file *ff = iocb->ki_filp->private_data;
 
 	if (fuse_is_bad(inode))
 		return -EIO;
@@ -952,6 +953,8 @@ static ssize_t fuse_file_read_iter(struct kiocb *iocb, struct iov_iter *to)
 			return err;
 	}
 
+	if (ff->passthrough.filp)
+		return fuse_passthrough_read_iter(iocb, to);
 	return generic_file_read_iter(iocb, to);
 }
 
@@ -1195,6 +1198,10 @@ static ssize_t fuse_file_write_iter(struct kiocb *iocb, struct iov_iter *from)
 	struct inode *inode = mapping->host;
 	ssize_t err;
 	loff_t endbyte = 0;
+	struct fuse_file *ff = file->private_data;
+
+	if (ff->passthrough.filp)
+		return fuse_passthrough_write_iter(iocb, from);
 
 	if (fuse_is_bad(inode))
 		return -EIO;
diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h
index 78416b079431..4b30ed07a80e 100644
--- a/fs/fuse/fuse_i.h
+++ b/fs/fuse/fuse_i.h
@@ -1045,5 +1045,7 @@ int fuse_passthrough_open(struct fuse_dev *fud,
 int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff,
 			   struct fuse_open_out *openarg);
 void fuse_passthrough_release(struct fuse_passthrough *passthrough);
+ssize_t fuse_passthrough_read_iter(struct kiocb *iocb, struct iov_iter *to);
+ssize_t fuse_passthrough_write_iter(struct kiocb *iocb, struct iov_iter *from);
 
 #endif /* _FS_FUSE_I_H */
diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c
index b2a19e18a319..52041cd1a359 100644
--- a/fs/fuse/passthrough.c
+++ b/fs/fuse/passthrough.c
@@ -5,6 +5,63 @@
 #include <linux/file.h>
 #include <linux/fuse.h>
 #include <linux/idr.h>
+#include <linux/uio.h>
+
+#define PASSTHROUGH_IOCB_MASK                                                  \
+	(IOCB_APPEND | IOCB_DSYNC | IOCB_HIPRI | IOCB_NOWAIT | IOCB_SYNC)
+
+static void fuse_copyattr(struct file *dst_file, struct file *src_file)
+{
+	struct inode *dst = file_inode(dst_file);
+	struct inode *src = file_inode(src_file);
+
+	i_size_write(dst, i_size_read(src));
+}
+
+ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse,
+				   struct iov_iter *iter)
+{
+	ssize_t ret;
+	struct file *fuse_filp = iocb_fuse->ki_filp;
+	struct fuse_file *ff = fuse_filp->private_data;
+	struct file *passthrough_filp = ff->passthrough.filp;
+
+	if (!iov_iter_count(iter))
+		return 0;
+
+	ret = vfs_iter_read(passthrough_filp, iter, &iocb_fuse->ki_pos,
+			    iocb_to_rw_flags(iocb_fuse->ki_flags,
+					     PASSTHROUGH_IOCB_MASK));
+
+	return ret;
+}
+
+ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse,
+				    struct iov_iter *iter)
+{
+	ssize_t ret;
+	struct file *fuse_filp = iocb_fuse->ki_filp;
+	struct fuse_file *ff = fuse_filp->private_data;
+	struct inode *fuse_inode = file_inode(fuse_filp);
+	struct file *passthrough_filp = ff->passthrough.filp;
+
+	if (!iov_iter_count(iter))
+		return 0;
+
+	inode_lock(fuse_inode);
+
+	file_start_write(passthrough_filp);
+	ret = vfs_iter_write(passthrough_filp, iter, &iocb_fuse->ki_pos,
+			     iocb_to_rw_flags(iocb_fuse->ki_flags,
+					      PASSTHROUGH_IOCB_MASK));
+	file_end_write(passthrough_filp);
+	if (ret > 0)
+		fuse_copyattr(fuse_filp, passthrough_filp);
+
+	inode_unlock(fuse_inode);
+
+	return ret;
+}
 
 int fuse_passthrough_open(struct fuse_dev *fud,
 			  struct fuse_passthrough_out *pto)
-- 
GitLab


From b5eead7ccbcb679983e95134f6b494ff1bff0e1a Mon Sep 17 00:00:00 2001
From: Alessio Balsini <balsini@google.com>
Date: Mon, 25 Jan 2021 17:03:51 +0000
Subject: [PATCH 288/298] FROMLIST: fuse: Handle asynchronous read and write in
 passthrough

Extend the passthrough feature by handling asynchronous IO both for read
and write operations.

When an AIO request is received, if the request targets a FUSE file with
the passthrough functionality enabled, a new identical AIO request is
created. The new request targets the lower file system file and gets
assigned a special FUSE passthrough AIO completion callback.
When the lower file system AIO request is completed, the FUSE
passthrough AIO completion callback is executed and propagates the
completion signal to the FUSE AIO request by triggering its completion
callback as well.

Bug: 179164095
Link: https://lore.kernel.org/lkml/20210125153057.3623715-7-balsini@android.com/
Signed-off-by: Alessio Balsini <balsini@android.com>
Change-Id: I47671ef36211102da6dd3ee8b2f226d1e6cd9d5c
Signed-off-by: Alessio Balsini <balsini@google.com>
---
 fs/fuse/passthrough.c | 101 +++++++++++++++++++++++++++++++++++++-----
 1 file changed, 90 insertions(+), 11 deletions(-)

diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c
index 52041cd1a359..8e0540ffabdd 100644
--- a/fs/fuse/passthrough.c
+++ b/fs/fuse/passthrough.c
@@ -10,6 +10,23 @@
 #define PASSTHROUGH_IOCB_MASK                                                  \
 	(IOCB_APPEND | IOCB_DSYNC | IOCB_HIPRI | IOCB_NOWAIT | IOCB_SYNC)
 
+struct fuse_aio_req {
+	struct kiocb iocb;
+	struct kiocb *iocb_fuse;
+};
+
+static inline void kiocb_clone(struct kiocb *kiocb, struct kiocb *kiocb_src,
+			       struct file *filp)
+{
+	*kiocb = (struct kiocb){
+		.ki_filp = filp,
+		.ki_flags = kiocb_src->ki_flags,
+		.ki_hint = kiocb_src->ki_hint,
+		.ki_ioprio = kiocb_src->ki_ioprio,
+		.ki_pos = kiocb_src->ki_pos,
+	};
+}
+
 static void fuse_copyattr(struct file *dst_file, struct file *src_file)
 {
 	struct inode *dst = file_inode(dst_file);
@@ -18,6 +35,32 @@ static void fuse_copyattr(struct file *dst_file, struct file *src_file)
 	i_size_write(dst, i_size_read(src));
 }
 
+static void fuse_aio_cleanup_handler(struct fuse_aio_req *aio_req)
+{
+	struct kiocb *iocb = &aio_req->iocb;
+	struct kiocb *iocb_fuse = aio_req->iocb_fuse;
+
+	if (iocb->ki_flags & IOCB_WRITE) {
+		__sb_writers_acquired(file_inode(iocb->ki_filp)->i_sb,
+				      SB_FREEZE_WRITE);
+		file_end_write(iocb->ki_filp);
+		fuse_copyattr(iocb_fuse->ki_filp, iocb->ki_filp);
+	}
+
+	iocb_fuse->ki_pos = iocb->ki_pos;
+	kfree(aio_req);
+}
+
+static void fuse_aio_rw_complete(struct kiocb *iocb, long res, long res2)
+{
+	struct fuse_aio_req *aio_req =
+		container_of(iocb, struct fuse_aio_req, iocb);
+	struct kiocb *iocb_fuse = aio_req->iocb_fuse;
+
+	fuse_aio_cleanup_handler(aio_req);
+	iocb_fuse->ki_complete(iocb_fuse, res, res2);
+}
+
 ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse,
 				   struct iov_iter *iter)
 {
@@ -29,9 +72,24 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse,
 	if (!iov_iter_count(iter))
 		return 0;
 
-	ret = vfs_iter_read(passthrough_filp, iter, &iocb_fuse->ki_pos,
-			    iocb_to_rw_flags(iocb_fuse->ki_flags,
-					     PASSTHROUGH_IOCB_MASK));
+	if (is_sync_kiocb(iocb_fuse)) {
+		ret = vfs_iter_read(passthrough_filp, iter, &iocb_fuse->ki_pos,
+				    iocb_to_rw_flags(iocb_fuse->ki_flags,
+						     PASSTHROUGH_IOCB_MASK));
+	} else {
+		struct fuse_aio_req *aio_req;
+
+		aio_req = kmalloc(sizeof(struct fuse_aio_req), GFP_KERNEL);
+		if (!aio_req)
+			return -ENOMEM;
+
+		aio_req->iocb_fuse = iocb_fuse;
+		kiocb_clone(&aio_req->iocb, iocb_fuse, passthrough_filp);
+		aio_req->iocb.ki_complete = fuse_aio_rw_complete;
+		ret = call_read_iter(passthrough_filp, &aio_req->iocb, iter);
+		if (ret != -EIOCBQUEUED)
+			fuse_aio_cleanup_handler(aio_req);
+	}
 
 	return ret;
 }
@@ -44,20 +102,41 @@ ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse,
 	struct fuse_file *ff = fuse_filp->private_data;
 	struct inode *fuse_inode = file_inode(fuse_filp);
 	struct file *passthrough_filp = ff->passthrough.filp;
+	struct inode *passthrough_inode = file_inode(passthrough_filp);
 
 	if (!iov_iter_count(iter))
 		return 0;
 
 	inode_lock(fuse_inode);
 
-	file_start_write(passthrough_filp);
-	ret = vfs_iter_write(passthrough_filp, iter, &iocb_fuse->ki_pos,
-			     iocb_to_rw_flags(iocb_fuse->ki_flags,
-					      PASSTHROUGH_IOCB_MASK));
-	file_end_write(passthrough_filp);
-	if (ret > 0)
-		fuse_copyattr(fuse_filp, passthrough_filp);
-
+	if (is_sync_kiocb(iocb_fuse)) {
+		file_start_write(passthrough_filp);
+		ret = vfs_iter_write(passthrough_filp, iter, &iocb_fuse->ki_pos,
+				     iocb_to_rw_flags(iocb_fuse->ki_flags,
+						      PASSTHROUGH_IOCB_MASK));
+		file_end_write(passthrough_filp);
+		if (ret > 0)
+			fuse_copyattr(fuse_filp, passthrough_filp);
+	} else {
+		struct fuse_aio_req *aio_req;
+
+		aio_req = kmalloc(sizeof(struct fuse_aio_req), GFP_KERNEL);
+		if (!aio_req) {
+			ret = -ENOMEM;
+			goto out;
+		}
+
+		file_start_write(passthrough_filp);
+		__sb_writers_release(passthrough_inode->i_sb, SB_FREEZE_WRITE);
+
+		aio_req->iocb_fuse = iocb_fuse;
+		kiocb_clone(&aio_req->iocb, iocb_fuse, passthrough_filp);
+		aio_req->iocb.ki_complete = fuse_aio_rw_complete;
+		ret = call_write_iter(passthrough_filp, &aio_req->iocb, iter);
+		if (ret != -EIOCBQUEUED)
+			fuse_aio_cleanup_handler(aio_req);
+	}
+out:
 	inode_unlock(fuse_inode);
 
 	return ret;
-- 
GitLab


From a775ee4f1f186919d24fbb3abcb7263433ca8d02 Mon Sep 17 00:00:00 2001
From: Alessio Balsini <balsini@google.com>
Date: Mon, 25 Jan 2021 17:04:38 +0000
Subject: [PATCH 289/298] FROMLIST: fuse: Use daemon creds in passthrough mode

When using FUSE passthrough, read/write operations are directly
forwarded to the lower file system file through VFS, but there is no
guarantee that the process that is triggering the request has the right
permissions to access the lower file system. This would cause the
read/write access to fail.

In passthrough file systems, where the FUSE daemon is responsible for
the enforcement of the lower file system access policies, often happens
that the process dealing with the FUSE file system doesn't have access
to the lower file system.
Being the FUSE daemon in charge of implementing the FUSE file
operations, that in the case of read/write operations usually simply
results in the copy of memory buffers from/to the lower file system
respectively, these operations are executed with the FUSE daemon
privileges.

This patch adds a reference to the FUSE daemon credentials, referenced
at FUSE_DEV_IOC_PASSTHROUGH_OPEN ioctl() time so that they can be used
to temporarily raise the user credentials when accessing lower file
system files in passthrough.
The process accessing the FUSE file with passthrough enabled temporarily
receives the privileges of the FUSE daemon while performing read/write
operations. Similar behavior is implemented in overlayfs.
These privileges will be reverted as soon as the IO operation completes.
This feature does not provide any higher security privileges to those
processes accessing the FUSE file system with passthrough enabled. This
is because it is still the FUSE daemon responsible for enabling or not
the passthrough feature at file open time, and should enable the feature
only after appropriate access policy checks.

Bug: 179164095
Link: https://lore.kernel.org/lkml/20210125153057.3623715-8-balsini@android.com/
Signed-off-by: Alessio Balsini <balsini@android.com>
Change-Id: Idb4f03a2ce7c536691e5eaf8fadadfcf002e1677
Signed-off-by: Alessio Balsini <balsini@google.com>
---
 fs/fuse/fuse_i.h      |  5 ++++-
 fs/fuse/passthrough.c | 11 +++++++++++
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h
index 4b30ed07a80e..e556c256e9b2 100644
--- a/fs/fuse/fuse_i.h
+++ b/fs/fuse/fuse_i.h
@@ -126,10 +126,13 @@ struct fuse_conn;
 
 /**
  * Reference to lower filesystem file for read/write operations handled in
- * passthrough mode
+ * passthrough mode.
+ * This struct also tracks the credentials to be used for handling read/write
+ * operations.
  */
 struct fuse_passthrough {
 	struct file *filp;
+	struct cred *cred;
 };
 
 /** FUSE specific file data */
diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c
index 8e0540ffabdd..05d22f16c824 100644
--- a/fs/fuse/passthrough.c
+++ b/fs/fuse/passthrough.c
@@ -65,6 +65,7 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse,
 				   struct iov_iter *iter)
 {
 	ssize_t ret;
+	const struct cred *old_cred;
 	struct file *fuse_filp = iocb_fuse->ki_filp;
 	struct fuse_file *ff = fuse_filp->private_data;
 	struct file *passthrough_filp = ff->passthrough.filp;
@@ -72,6 +73,7 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse,
 	if (!iov_iter_count(iter))
 		return 0;
 
+	old_cred = override_creds(ff->passthrough.cred);
 	if (is_sync_kiocb(iocb_fuse)) {
 		ret = vfs_iter_read(passthrough_filp, iter, &iocb_fuse->ki_pos,
 				    iocb_to_rw_flags(iocb_fuse->ki_flags,
@@ -90,6 +92,7 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse,
 		if (ret != -EIOCBQUEUED)
 			fuse_aio_cleanup_handler(aio_req);
 	}
+	revert_creds(old_cred);
 
 	return ret;
 }
@@ -98,6 +101,7 @@ ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse,
 				    struct iov_iter *iter)
 {
 	ssize_t ret;
+	const struct cred *old_cred;
 	struct file *fuse_filp = iocb_fuse->ki_filp;
 	struct fuse_file *ff = fuse_filp->private_data;
 	struct inode *fuse_inode = file_inode(fuse_filp);
@@ -109,6 +113,7 @@ ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse,
 
 	inode_lock(fuse_inode);
 
+	old_cred = override_creds(ff->passthrough.cred);
 	if (is_sync_kiocb(iocb_fuse)) {
 		file_start_write(passthrough_filp);
 		ret = vfs_iter_write(passthrough_filp, iter, &iocb_fuse->ki_pos,
@@ -137,6 +142,7 @@ ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse,
 			fuse_aio_cleanup_handler(aio_req);
 	}
 out:
+	revert_creds(old_cred);
 	inode_unlock(fuse_inode);
 
 	return ret;
@@ -187,6 +193,7 @@ int fuse_passthrough_open(struct fuse_dev *fud,
 	}
 
 	passthrough->filp = passthrough_filp;
+	passthrough->cred = prepare_creds();
 
 	idr_preload(GFP_KERNEL);
 	spin_lock(&fc->passthrough_req_lock);
@@ -238,4 +245,8 @@ void fuse_passthrough_release(struct fuse_passthrough *passthrough)
 		fput(passthrough->filp);
 		passthrough->filp = NULL;
 	}
+	if (passthrough->cred) {
+		put_cred(passthrough->cred);
+		passthrough->cred = NULL;
+	}
 }
-- 
GitLab


From dec187a4591ec94652315975ec5a92643b2fd574 Mon Sep 17 00:00:00 2001
From: Alessio Balsini <balsini@google.com>
Date: Mon, 25 Jan 2021 17:05:31 +0000
Subject: [PATCH 290/298] FROMLIST: fuse: Introduce passthrough for mmap

Enabling FUSE passthrough for mmap-ed operations not only affects
performance, but has also been shown as mandatory for the correct
functioning of FUSE passthrough.
yanwu noticed [1] that a FUSE file with passthrough enabled may suffer
data inconsistencies if the same file is also accessed with mmap. What
happens is that read/write operations are directly applied to the lower
file system (and its cache), while mmap-ed operations are affecting the
FUSE cache.

Extend the FUSE passthrough implementation to also handle memory-mapped
FUSE file, to both fix the cache inconsistencies and extend the
passthrough performance benefits to mmap-ed operations.

[1] https://lore.kernel.org/lkml/20210119110654.11817-1-wu-yan@tcl.com/

Bug: 179164095
Link: https://lore.kernel.org/lkml/20210125153057.3623715-9-balsini@android.com/
Signed-off-by: Alessio Balsini <balsini@android.com>
Change-Id: Ifad4698b0380f6e004c487940ac6907b9a9f2964
Signed-off-by: Alessio Balsini <balsini@google.com>
---
 fs/fuse/file.c        |  5 +++++
 fs/fuse/fuse_i.h      |  1 +
 fs/fuse/passthrough.c | 41 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 47 insertions(+)

diff --git a/fs/fuse/file.c b/fs/fuse/file.c
index 93f3b91ad9ce..82a46db963be 100644
--- a/fs/fuse/file.c
+++ b/fs/fuse/file.c
@@ -2117,6 +2117,11 @@ static const struct vm_operations_struct fuse_file_vm_ops = {
 
 static int fuse_file_mmap(struct file *file, struct vm_area_struct *vma)
 {
+	struct fuse_file *ff = file->private_data;
+
+	if (ff->passthrough.filp)
+		return fuse_passthrough_mmap(file, vma);
+
 	if ((vma->vm_flags & VM_SHARED) && (vma->vm_flags & VM_MAYWRITE))
 		fuse_link_write_file(file);
 
diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h
index e556c256e9b2..dec2e1f5a0b5 100644
--- a/fs/fuse/fuse_i.h
+++ b/fs/fuse/fuse_i.h
@@ -1050,5 +1050,6 @@ int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff,
 void fuse_passthrough_release(struct fuse_passthrough *passthrough);
 ssize_t fuse_passthrough_read_iter(struct kiocb *iocb, struct iov_iter *to);
 ssize_t fuse_passthrough_write_iter(struct kiocb *iocb, struct iov_iter *from);
+ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma);
 
 #endif /* _FS_FUSE_I_H */
diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c
index 05d22f16c824..39d9a77c5454 100644
--- a/fs/fuse/passthrough.c
+++ b/fs/fuse/passthrough.c
@@ -148,6 +148,47 @@ ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse,
 	return ret;
 }
 
+ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	int ret;
+	const struct cred *old_cred;
+	struct fuse_file *ff = file->private_data;
+	struct inode *fuse_inode = file_inode(file);
+	struct file *passthrough_filp = ff->passthrough.filp;
+	struct inode *passthrough_inode = file_inode(passthrough_filp);
+
+	if (!passthrough_filp->f_op->mmap)
+		return -ENODEV;
+
+	if (WARN_ON(file != vma->vm_file))
+		return -EIO;
+
+	vma->vm_file = get_file(passthrough_filp);
+
+	old_cred = override_creds(ff->passthrough.cred);
+	ret = call_mmap(vma->vm_file, vma);
+	revert_creds(old_cred);
+
+	if (ret)
+		fput(passthrough_filp);
+	else
+		fput(file);
+
+	if (file->f_flags & O_NOATIME)
+		return ret;
+
+	if ((!timespec64_equal(&fuse_inode->i_mtime,
+			       &passthrough_inode->i_mtime) ||
+	     !timespec64_equal(&fuse_inode->i_ctime,
+			       &passthrough_inode->i_ctime))) {
+		fuse_inode->i_mtime = passthrough_inode->i_mtime;
+		fuse_inode->i_ctime = passthrough_inode->i_ctime;
+	}
+	touch_atime(&file->f_path);
+
+	return ret;
+}
+
 int fuse_passthrough_open(struct fuse_dev *fud,
 			  struct fuse_passthrough_out *pto)
 {
-- 
GitLab


From cfaa5c31a7e454e04b741232dc39dc57e45de843 Mon Sep 17 00:00:00 2001
From: Alessio Balsini <balsini@android.com>
Date: Fri, 5 Feb 2021 10:58:49 +0000
Subject: [PATCH 291/298] FROMLIST: fuse: Fix crediantials leak in passthrough
 read_iter

If the system doesn't have enough memory when fuse_passthrough_read_iter
is requested in asynchronous IO, an error is directly returned without
restoring the caller's credentials.
Fix by always ensuring credentials are restored.

Fixes: aa29f32988c1f84c96e2457b049dea437601f2cc ("FROMLIST: fuse: Use daemon creds in passthrough mode")
Link: https://lore.kernel.org/lkml/YB0qPHVORq7bJy6G@google.com/
Reported-by: Peng Tao <bergwolf@gmail.com>
Signed-off-by: Alessio Balsini <balsini@android.com>
Signed-off-by: Alessio Balsini <balsini@google.com>
Change-Id: I4aff43f5dd8ddab2cc8871cd9f81438963ead5b6
---
 fs/fuse/passthrough.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c
index 39d9a77c5454..f7138d2abce1 100644
--- a/fs/fuse/passthrough.c
+++ b/fs/fuse/passthrough.c
@@ -82,8 +82,10 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse,
 		struct fuse_aio_req *aio_req;
 
 		aio_req = kmalloc(sizeof(struct fuse_aio_req), GFP_KERNEL);
-		if (!aio_req)
-			return -ENOMEM;
+		if (!aio_req) {
+			ret = -ENOMEM;
+			goto out;
+		}
 
 		aio_req->iocb_fuse = iocb_fuse;
 		kiocb_clone(&aio_req->iocb, iocb_fuse, passthrough_filp);
@@ -92,6 +94,7 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse,
 		if (ret != -EIOCBQUEUED)
 			fuse_aio_cleanup_handler(aio_req);
 	}
+out:
 	revert_creds(old_cred);
 
 	return ret;
-- 
GitLab


From 5648a504996f5a88f443febe906f7c30788b828d Mon Sep 17 00:00:00 2001
From: Alessio Balsini <balsini@google.com>
Date: Thu, 13 May 2021 11:58:16 +0100
Subject: [PATCH 292/298] ANDROID: fuse/passthrough: API V2 with __u32 open
 argument

The initial FUSE passthrough interface has the issue of introducing an
ioctl which receives as a parameter a data structure containing a
pointer. What happens is that, depending on the architecture, the size
of this struct might change, and especially for 32-bit userspace running
on 64-bit kernel, the size mismatch results into different a single
ioctl the behavior of which depends on the data that is passed (e.g.,
with an enum). This is just a poor ioctl design as mentioned by Arnd
Bergmann [1].

Introduce the new FUSE_PASSTHROUGH_OPEN ioctl which only gets the fd of
the lower file system, which is a fixed-size __u32, dropping the
confusing fuse_passthrough_out data structure.

[1] https://lore.kernel.org/lkml/CAK8P3a2K2FzPvqBYL9W=Yut58SFXyetXwU4Fz50G5O3TsS0pPQ@mail.gmail.com/

Bug: 175195837
Signed-off-by: Alessio Balsini <balsini@google.com>
Change-Id: I486d71cbe20f3c0c87544fa75da4e2704fe57c7c
---
 fs/fuse/dev.c             |  7 ++-----
 fs/fuse/fuse_i.h          |  3 +--
 fs/fuse/passthrough.c     |  9 ++-------
 include/uapi/linux/fuse.h | 13 +++----------
 4 files changed, 8 insertions(+), 24 deletions(-)

diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c
index 08dcd7102159..8305c9053a1c 100644
--- a/fs/fuse/dev.c
+++ b/fs/fuse/dev.c
@@ -2293,7 +2293,6 @@ static long fuse_dev_ioctl(struct file *file, unsigned int cmd,
 	int res;
 	int oldfd;
 	struct fuse_dev *fud = NULL;
-	struct fuse_passthrough_out pto;
 
 	if (_IOC_TYPE(cmd) != FUSE_DEV_IOC_MAGIC)
 		return -EINVAL;
@@ -2326,13 +2325,11 @@ static long fuse_dev_ioctl(struct file *file, unsigned int cmd,
 		break;
 	case _IOC_NR(FUSE_DEV_IOC_PASSTHROUGH_OPEN):
 		res = -EFAULT;
-		if (!copy_from_user(&pto,
-				    (struct fuse_passthrough_out __user *)arg,
-				    sizeof(pto))) {
+		if (!get_user(oldfd, (__u32 __user *)arg)) {
 			res = -EINVAL;
 			fud = fuse_get_dev(file);
 			if (fud)
-				res = fuse_passthrough_open(fud, &pto);
+				res = fuse_passthrough_open(fud, oldfd);
 		}
 		break;
 	default:
diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h
index dec2e1f5a0b5..9edd2e68fcd8 100644
--- a/fs/fuse/fuse_i.h
+++ b/fs/fuse/fuse_i.h
@@ -1043,8 +1043,7 @@ struct posix_acl *fuse_get_acl(struct inode *inode, int type);
 int fuse_set_acl(struct inode *inode, struct posix_acl *acl, int type);
 
 /* passthrough.c */
-int fuse_passthrough_open(struct fuse_dev *fud,
-			  struct fuse_passthrough_out *pto);
+int fuse_passthrough_open(struct fuse_dev *fud, u32 lower_fd);
 int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff,
 			   struct fuse_open_out *openarg);
 void fuse_passthrough_release(struct fuse_passthrough *passthrough);
diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c
index f7138d2abce1..1d1253e78484 100644
--- a/fs/fuse/passthrough.c
+++ b/fs/fuse/passthrough.c
@@ -192,8 +192,7 @@ ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma)
 	return ret;
 }
 
-int fuse_passthrough_open(struct fuse_dev *fud,
-			  struct fuse_passthrough_out *pto)
+int fuse_passthrough_open(struct fuse_dev *fud, u32 lower_fd)
 {
 	int res;
 	struct file *passthrough_filp;
@@ -205,11 +204,7 @@ int fuse_passthrough_open(struct fuse_dev *fud,
 	if (!fc->passthrough)
 		return -EPERM;
 
-	/* This field is reserved for future implementation */
-	if (pto->len != 0)
-		return -EINVAL;
-
-	passthrough_filp = fget(pto->fd);
+	passthrough_filp = fget(lower_fd);
 	if (!passthrough_filp) {
 		pr_err("FUSE: invalid file descriptor for passthrough.\n");
 		return -EBADF;
diff --git a/include/uapi/linux/fuse.h b/include/uapi/linux/fuse.h
index 6184f67ede10..7210b489c629 100644
--- a/include/uapi/linux/fuse.h
+++ b/include/uapi/linux/fuse.h
@@ -708,14 +708,6 @@ struct fuse_in_header {
 	uint32_t	padding;
 };
 
-/* fuse_passthrough_out for passthrough V1 */
-struct fuse_passthrough_out {
-	uint32_t	fd;
-	/* For future implementation */
-	uint32_t	len;
-	void		*vec;
-};
-
 struct fuse_out_header {
 	uint32_t	len;
 	int32_t		error;
@@ -793,8 +785,9 @@ struct fuse_notify_retrieve_in {
 /* Device ioctls: */
 #define FUSE_DEV_IOC_MAGIC		229
 #define FUSE_DEV_IOC_CLONE		_IOR(FUSE_DEV_IOC_MAGIC, 0, uint32_t)
-/* 127 is reserved for the V1 interface implementation in Android */
-#define FUSE_DEV_IOC_PASSTHROUGH_OPEN	_IOW(FUSE_DEV_IOC_MAGIC, 127, struct fuse_passthrough_out)
+/* 127 is reserved for the V1 interface implementation in Android (deprecated) */
+/* 126 is reserved for the V2 interface implementation in Android */
+#define FUSE_DEV_IOC_PASSTHROUGH_OPEN	_IOW(FUSE_DEV_IOC_MAGIC, 126, __u32)
 
 struct fuse_lseek_in {
 	uint64_t	fh;
-- 
GitLab


From 20169b222bb74edf4f683346e028a4f035e75bce Mon Sep 17 00:00:00 2001
From: Alessio Balsini <balsini@android.com>
Date: Fri, 19 Mar 2021 15:05:14 +0000
Subject: [PATCH 293/298] UPSTREAM: fuse: fix matching of FUSE_DEV_IOC_CLONE
 command

With commit f8425c939663 ("fuse: 32-bit user space ioctl compat for fuse
device") the matching constraints for the FUSE_DEV_IOC_CLONE ioctl command
are relaxed, limited to the testing of command type and number.  As Arnd
noticed, this is wrong as it wouldn't ensure the correctness of the data
size or direction for the received FUSE device ioctl.

Fix by bringing back the comparison of the ioctl received by the FUSE
device to the originally generated FUSE_DEV_IOC_CLONE.

Fixes: f8425c939663 ("fuse: 32-bit user space ioctl compat for fuse device")
Reported-by: Arnd Bergmann <arnd@kernel.org>
Signed-off-by: Alessio Balsini <balsini@android.com>
Signed-off-by: Miklos Szeredi <mszeredi@redhat.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Alessio Balsini <balsini@android.com>
Change-Id: I372d8399db6d603ba20ef50528acf6645e4d3c66
(cherry picked from commit 6076f5f341e612152879bfda99f0b76c1953bf0b)
---
 fs/fuse/dev.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c
index 8305c9053a1c..0fca941a2a80 100644
--- a/fs/fuse/dev.c
+++ b/fs/fuse/dev.c
@@ -2294,11 +2294,8 @@ static long fuse_dev_ioctl(struct file *file, unsigned int cmd,
 	int oldfd;
 	struct fuse_dev *fud = NULL;
 
-	if (_IOC_TYPE(cmd) != FUSE_DEV_IOC_MAGIC)
-		return -EINVAL;
-
-	switch (_IOC_NR(cmd)) {
-	case _IOC_NR(FUSE_DEV_IOC_CLONE):
+	switch (cmd) {
+	case FUSE_DEV_IOC_CLONE:
 		res = -EFAULT;
 		if (!get_user(oldfd, (__u32 __user *)arg)) {
 			struct file *old = fget(oldfd);
@@ -2323,7 +2320,7 @@ static long fuse_dev_ioctl(struct file *file, unsigned int cmd,
 			}
 		}
 		break;
-	case _IOC_NR(FUSE_DEV_IOC_PASSTHROUGH_OPEN):
+	case FUSE_DEV_IOC_PASSTHROUGH_OPEN:
 		res = -EFAULT;
 		if (!get_user(oldfd, (__u32 __user *)arg)) {
 			res = -EINVAL;
-- 
GitLab


From e61b11a7370f7da5a0dc6a17d9d3941073c51303 Mon Sep 17 00:00:00 2001
From: Biao Li <libiao@allwinnertech.com>
Date: Wed, 4 Aug 2021 17:29:31 +0800
Subject: [PATCH 294/298] ANDROID: fuse: Allocate zeroed memory for canonical
 path
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The page used to contain the fuse_dentry_canonical_path to be handled in
fuse_dev_do_write is allocated using __get_free_pages(GFP_KERNEL).
The returned page may contain undefined data, that by chance may be
considered as a valid path name that is not in the cache. In that case,
if the FUSE daemon mistakenly doesn't fill the canonical path buffer,
the FUSE driver may fall into two blocking

  request_wait_answer(fuse_dev_write->kern_path->fuse_lookup_name)

causing a deadlock condition.

The stack is as follows：
find            S    0 20511  20117 0x00000000
Call trace:
[<ffffff8008085e78>] __switch_to+0xb8/0xd4
[<ffffff8008a0cac4>] __schedule+0x458/0x714
[<ffffff8008a0ce0c>] schedule+0x8c/0xa8
[<ffffff800833865c>] request_wait_answer+0x74/0x220
[<ffffff8008339f70>] __fuse_request_send+0x8c/0xa0
[<ffffff8008339fe4>] fuse_request_send+0x60/0x6c
[<ffffff800833c1a8>] fuse_dentry_canonical_path+0xb8/0x104
[<ffffff800820b14c>] do_sys_open+0x1b4/0x260
[<ffffff800820b27c>] SyS_openat+0x3c/0x4c
[<ffffff8008083540>] el0_svc_naked+0x34/0x38
mount.ntfs-3g   S    0  5845      1 0x00000000
Call trace:
[<ffffff8008085e78>] __switch_to+0xb8/0xd4
[<ffffff8008a0cac4>] __schedule+0x458/0x714
[<ffffff8008a0ce0c>] schedule+0x8c/0xa8
[<ffffff800833865c>] request_wait_answer+0x74/0x220
[<ffffff8008339f70>] __fuse_request_send+0x8c/0xa0
[<ffffff8008339fe4>] fuse_request_send+0x60/0x6c
[<ffffff800833bdb0>] fuse_simple_request+0x128/0x16c
[<ffffff800833dddc>] fuse_lookup_name+0x104/0x1b0
[<ffffff800833dee4>] fuse_lookup+0x5c/0x11c
[<ffffff800821861c>] lookup_slow+0xfc/0x174
[<ffffff800821b474>] walk_component+0xf0/0x290
[<ffffff800821bbac>] path_lookupat+0xa0/0x128
[<ffffff800821c7f4>] filename_lookup+0x84/0x124
[<ffffff800821c8d8>] kern_path+0x44/0x54
[<ffffff800833b0c8>] fuse_dev_do_write+0x828/0xa0c
[<ffffff800833b610>] fuse_dev_write+0x90/0xb4
[<ffffff800820b770>] do_iter_readv_writev+0xf4/0x13c
[<ffffff800820cc88>] do_readv_writev+0xec/0x220
[<ffffff800820d05c>] vfs_writev+0x60/0x74
[<ffffff800820d0ec>] do_writev+0x7c/0x100
[<ffffff800820e348>] SyS_writev+0x38/0x48
[<ffffff8008083540>] el0_svc_naked+0x34/0x38

Fix by ensuring that the page allocated for the canonical path is zeroed.

Bug: 194856119
Bug: 196051870
Fixes: 24ab59f6bb42 ("ANDROID: fuse: Add support for d_canonical_path")
Signed-off-by: Biao Li <libiao@allwinnertech.com>
Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com>
Signed-off-by: Alessio Balsini <balsini@google.com>
Change-Id: I400815dc1049d90c308f5cf87ce60de97ff82131
---
 fs/fuse/dir.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c
index 77824b96514c..cdb3a7022412 100644
--- a/fs/fuse/dir.c
+++ b/fs/fuse/dir.c
@@ -296,7 +296,7 @@ static void fuse_dentry_canonical_path(const struct path *path,
 	char *path_name;
 	int err;
 
-	path_name = (char *)__get_free_page(GFP_KERNEL);
+	path_name = (char *)get_zeroed_page(GFP_KERNEL);
 	if (!path_name)
 		goto default_path;
 
-- 
GitLab


From f8e5d81956112e8a96df2b7c196cb677894106e2 Mon Sep 17 00:00:00 2001
From: Alessio Balsini <balsini@google.com>
Date: Thu, 23 Sep 2021 11:05:08 +0100
Subject: [PATCH 295/298] ANDROID: fs/fuse: Keep FUSE file times consistent
 with lower file

When FUSE passthrough is used, the lower file system file is manipulated
directly, but neither mtime, atime or ctime of the referencing FUSE file
is updated.

Fix by updating the file times when passthrough operations are
performed.

Bug: 200779468
Bug: 201730208
Reported-by: Fengnan Chang <changfengnan@vivo.com>
Reported-by: Ed Tsai <ed.tsai@mediatek.com>
Signed-off-by: Alessio Balsini <balsini@google.com>
Change-Id: I35b72196b2cc1d79a9f62ddb32e2cfa934c3b6d3
---
 fs/fuse/passthrough.c | 41 ++++++++++++++++++++++++++++-------------
 1 file changed, 28 insertions(+), 13 deletions(-)

diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c
index 1d1253e78484..f344f917d037 100644
--- a/fs/fuse/passthrough.c
+++ b/fs/fuse/passthrough.c
@@ -27,11 +27,34 @@ static inline void kiocb_clone(struct kiocb *kiocb, struct kiocb *kiocb_src,
 	};
 }
 
+static void fuse_file_accessed(struct file *dst_file, struct file *src_file)
+{
+	struct inode *dst_inode;
+	struct inode *src_inode;
+
+	if (dst_file->f_flags & O_NOATIME)
+		return;
+
+	dst_inode = file_inode(dst_file);
+	src_inode = file_inode(src_file);
+
+	if ((!timespec64_equal(&dst_inode->i_mtime, &src_inode->i_mtime) ||
+	     !timespec64_equal(&dst_inode->i_ctime, &src_inode->i_ctime))) {
+		dst_inode->i_mtime = src_inode->i_mtime;
+		dst_inode->i_ctime = src_inode->i_ctime;
+	}
+
+	touch_atime(&dst_file->f_path);
+}
+
 static void fuse_copyattr(struct file *dst_file, struct file *src_file)
 {
 	struct inode *dst = file_inode(dst_file);
 	struct inode *src = file_inode(src_file);
 
+	dst->i_atime = src->i_atime;
+	dst->i_mtime = src->i_mtime;
+	dst->i_ctime = src->i_ctime;
 	i_size_write(dst, i_size_read(src));
 }
 
@@ -97,6 +120,8 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse,
 out:
 	revert_creds(old_cred);
 
+	fuse_file_accessed(fuse_filp, passthrough_filp);
+
 	return ret;
 }
 
@@ -116,6 +141,8 @@ ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse,
 
 	inode_lock(fuse_inode);
 
+	fuse_copyattr(fuse_filp, passthrough_filp);
+
 	old_cred = override_creds(ff->passthrough.cred);
 	if (is_sync_kiocb(iocb_fuse)) {
 		file_start_write(passthrough_filp);
@@ -156,9 +183,7 @@ ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma)
 	int ret;
 	const struct cred *old_cred;
 	struct fuse_file *ff = file->private_data;
-	struct inode *fuse_inode = file_inode(file);
 	struct file *passthrough_filp = ff->passthrough.filp;
-	struct inode *passthrough_inode = file_inode(passthrough_filp);
 
 	if (!passthrough_filp->f_op->mmap)
 		return -ENODEV;
@@ -177,17 +202,7 @@ ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma)
 	else
 		fput(file);
 
-	if (file->f_flags & O_NOATIME)
-		return ret;
-
-	if ((!timespec64_equal(&fuse_inode->i_mtime,
-			       &passthrough_inode->i_mtime) ||
-	     !timespec64_equal(&fuse_inode->i_ctime,
-			       &passthrough_inode->i_ctime))) {
-		fuse_inode->i_mtime = passthrough_inode->i_mtime;
-		fuse_inode->i_ctime = passthrough_inode->i_ctime;
-	}
-	touch_atime(&file->f_path);
+	fuse_file_accessed(file, passthrough_filp);
 
 	return ret;
 }
-- 
GitLab


From aeb761e164439419e10b8006322268f73cd738e7 Mon Sep 17 00:00:00 2001
From: Todd Poynor <toddpoynor@google.com>
Date: Wed, 24 Aug 2011 15:01:30 -0700
Subject: [PATCH 296/298] ANDROID: fs: fuse: Freeze client on suspend when
 request sent to userspace

Suspend attempts can abort when the FUSE daemon is already frozen
and a client is waiting uninterruptibly for a response, causing
freezing of tasks to fail.

Use the freeze-friendly wait API, but disregard other signals.

Change-Id: Icefb7e4bbc718ccb76bf3c04daaa5eeea7e0e63c
Signed-off-by: Todd Poynor <toddpoynor@google.com>
Signed-off-by: Tashfin Shakeer Rhythm <tashfinshakeerrhythm@gmail.com>
---
 fs/fuse/dev.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c
index 0fca941a2a80..a047a7f62f8f 100644
--- a/fs/fuse/dev.c
+++ b/fs/fuse/dev.c
@@ -22,6 +22,7 @@
 #include <linux/swap.h>
 #include <linux/splice.h>
 #include <linux/sched.h>
+#include <linux/freezer.h>
 
 MODULE_ALIAS_MISCDEV(FUSE_MINOR);
 MODULE_ALIAS("devname:fuse");
@@ -487,7 +488,9 @@ static void request_wait_answer(struct fuse_conn *fc, struct fuse_req *req)
 	 * Either request is already in userspace, or it was forced.
 	 * Wait it out.
 	 */
-	wait_event(req->waitq, test_bit(FR_FINISHED, &req->flags));
+	while (!test_bit(FR_FINISHED, &req->flags))
+		wait_event_freezable(req->waitq,
+				test_bit(FR_FINISHED, &req->flags));
 }
 
 static void __fuse_request_send(struct fuse_conn *fc, struct fuse_req *req)
-- 
GitLab


From c666f11f2e581c5d527e46130cf771208b5d1367 Mon Sep 17 00:00:00 2001
From: Greg Kroah-Hartman <gregkh@google.com>
Date: Fri, 3 Nov 2023 14:17:13 +0100
Subject: [PATCH 297/298] Reapply "perf: Disallow mis-matched inherited group
 reads"

This reverts commit 9c20bfd64d3f79d929a37d70e8aaaad5405d4d6e.

It's needed back in the tree as it fixes a real issue, and it turns out
to nicely fit into an unused slot within the structure, so there's no
ABI breakage.

Update the .xml file with the new structure field:

Leaf changes summary: 1 artifact changed
Changed leaf types summary: 1 leaf type changed
Removed/Changed/Added functions summary: 0 Removed, 0 Changed, 0 Added function
Removed/Changed/Added variables summary: 0 Removed, 0 Changed, 0 Added variable

'struct perf_event at perf_event.h:564:1' changed:
  type size hasn't changed
  1 data member insertion:
    'unsigned int group_generation', at offset 1120 (in bits) at perf_event.h:601:1
  1242 impacted interfaces

Bug: 307236803
Change-Id: I921c19d115869d8b0517d44d271d56d557da4167
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
---
 android/abi_gki_aarch64.xml | 7157 ++++++++++++++++++-----------------
 include/linux/perf_event.h  |    3 +
 kernel/events/core.c        |   39 +-
 3 files changed, 3644 insertions(+), 3555 deletions(-)

diff --git a/android/abi_gki_aarch64.xml b/android/abi_gki_aarch64.xml
index 18c8d22e584d..20921dd6c6f6 100644
--- a/android/abi_gki_aarch64.xml
+++ b/android/abi_gki_aarch64.xml
@@ -3793,259 +3793,262 @@
         <data-member access='public' layout-offset-in-bits='1088'>
           <var-decl name='group_caps' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='598' column='1'/>
         </data-member>
+        <data-member access='public' layout-offset-in-bits='1120'>
+          <var-decl name='group_generation' type-id='f0981eeb' visibility='default' filepath='include/linux/perf_event.h' line='601' column='1'/>
+        </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='group_leader' type-id='2bf16f59' visibility='default' filepath='include/linux/perf_event.h' line='600' column='1'/>
+          <var-decl name='group_leader' type-id='2bf16f59' visibility='default' filepath='include/linux/perf_event.h' line='603' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='pmu' type-id='0906f5b9' visibility='default' filepath='include/linux/perf_event.h' line='601' column='1'/>
+          <var-decl name='pmu' type-id='0906f5b9' visibility='default' filepath='include/linux/perf_event.h' line='604' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='pmu_private' type-id='eaa32e2f' visibility='default' filepath='include/linux/perf_event.h' line='602' column='1'/>
+          <var-decl name='pmu_private' type-id='eaa32e2f' visibility='default' filepath='include/linux/perf_event.h' line='605' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='state' type-id='31fdb95a' visibility='default' filepath='include/linux/perf_event.h' line='604' column='1'/>
+          <var-decl name='state' type-id='31fdb95a' visibility='default' filepath='include/linux/perf_event.h' line='607' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1376'>
-          <var-decl name='attach_state' type-id='f0981eeb' visibility='default' filepath='include/linux/perf_event.h' line='605' column='1'/>
+          <var-decl name='attach_state' type-id='f0981eeb' visibility='default' filepath='include/linux/perf_event.h' line='608' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='count' type-id='7da7300e' visibility='default' filepath='include/linux/perf_event.h' line='606' column='1'/>
+          <var-decl name='count' type-id='7da7300e' visibility='default' filepath='include/linux/perf_event.h' line='609' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1472'>
-          <var-decl name='child_count' type-id='28ee064c' visibility='default' filepath='include/linux/perf_event.h' line='607' column='1'/>
+          <var-decl name='child_count' type-id='28ee064c' visibility='default' filepath='include/linux/perf_event.h' line='610' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='total_time_enabled' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='615' column='1'/>
+          <var-decl name='total_time_enabled' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='618' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1600'>
-          <var-decl name='total_time_running' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='616' column='1'/>
+          <var-decl name='total_time_running' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='619' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1664'>
-          <var-decl name='tstamp' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='617' column='1'/>
+          <var-decl name='tstamp' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='620' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1728'>
-          <var-decl name='shadow_ctx_time' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='627' column='1'/>
+          <var-decl name='shadow_ctx_time' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='630' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1792'>
-          <var-decl name='attr' type-id='e57536d9' visibility='default' filepath='include/linux/perf_event.h' line='629' column='1'/>
+          <var-decl name='attr' type-id='e57536d9' visibility='default' filepath='include/linux/perf_event.h' line='632' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2688'>
-          <var-decl name='header_size' type-id='1dc6a898' visibility='default' filepath='include/linux/perf_event.h' line='630' column='1'/>
+          <var-decl name='header_size' type-id='1dc6a898' visibility='default' filepath='include/linux/perf_event.h' line='633' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2704'>
-          <var-decl name='id_header_size' type-id='1dc6a898' visibility='default' filepath='include/linux/perf_event.h' line='631' column='1'/>
+          <var-decl name='id_header_size' type-id='1dc6a898' visibility='default' filepath='include/linux/perf_event.h' line='634' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2720'>
-          <var-decl name='read_size' type-id='1dc6a898' visibility='default' filepath='include/linux/perf_event.h' line='632' column='1'/>
+          <var-decl name='read_size' type-id='1dc6a898' visibility='default' filepath='include/linux/perf_event.h' line='635' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2752'>
-          <var-decl name='hw' type-id='b594b0c9' visibility='default' filepath='include/linux/perf_event.h' line='633' column='1'/>
+          <var-decl name='hw' type-id='b594b0c9' visibility='default' filepath='include/linux/perf_event.h' line='636' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4288'>
-          <var-decl name='ctx' type-id='b9419dc5' visibility='default' filepath='include/linux/perf_event.h' line='635' column='1'/>
+          <var-decl name='ctx' type-id='b9419dc5' visibility='default' filepath='include/linux/perf_event.h' line='638' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4352'>
-          <var-decl name='refcount' type-id='f22a8abb' visibility='default' filepath='include/linux/perf_event.h' line='636' column='1'/>
+          <var-decl name='refcount' type-id='f22a8abb' visibility='default' filepath='include/linux/perf_event.h' line='639' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4416'>
-          <var-decl name='child_total_time_enabled' type-id='28ee064c' visibility='default' filepath='include/linux/perf_event.h' line='642' column='1'/>
+          <var-decl name='child_total_time_enabled' type-id='28ee064c' visibility='default' filepath='include/linux/perf_event.h' line='645' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4480'>
-          <var-decl name='child_total_time_running' type-id='28ee064c' visibility='default' filepath='include/linux/perf_event.h' line='643' column='1'/>
+          <var-decl name='child_total_time_running' type-id='28ee064c' visibility='default' filepath='include/linux/perf_event.h' line='646' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4544'>
-          <var-decl name='child_mutex' type-id='925167dc' visibility='default' filepath='include/linux/perf_event.h' line='648' column='1'/>
+          <var-decl name='child_mutex' type-id='925167dc' visibility='default' filepath='include/linux/perf_event.h' line='651' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4800'>
-          <var-decl name='child_list' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='649' column='1'/>
+          <var-decl name='child_list' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='652' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4928'>
-          <var-decl name='parent' type-id='2bf16f59' visibility='default' filepath='include/linux/perf_event.h' line='650' column='1'/>
+          <var-decl name='parent' type-id='2bf16f59' visibility='default' filepath='include/linux/perf_event.h' line='653' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4992'>
-          <var-decl name='oncpu' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='652' column='1'/>
+          <var-decl name='oncpu' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='655' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5024'>
-          <var-decl name='cpu' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='653' column='1'/>
+          <var-decl name='cpu' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='656' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5056'>
-          <var-decl name='readable_on_cpus' type-id='90bc6bed' visibility='default' filepath='include/linux/perf_event.h' line='654' column='1'/>
+          <var-decl name='readable_on_cpus' type-id='90bc6bed' visibility='default' filepath='include/linux/perf_event.h' line='657' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5120'>
-          <var-decl name='owner_entry' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='656' column='1'/>
+          <var-decl name='owner_entry' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='659' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5248'>
-          <var-decl name='owner' type-id='f23e2572' visibility='default' filepath='include/linux/perf_event.h' line='657' column='1'/>
+          <var-decl name='owner' type-id='f23e2572' visibility='default' filepath='include/linux/perf_event.h' line='660' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5312'>
-          <var-decl name='mmap_mutex' type-id='925167dc' visibility='default' filepath='include/linux/perf_event.h' line='660' column='1'/>
+          <var-decl name='mmap_mutex' type-id='925167dc' visibility='default' filepath='include/linux/perf_event.h' line='663' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5568'>
-          <var-decl name='mmap_count' type-id='49178f86' visibility='default' filepath='include/linux/perf_event.h' line='661' column='1'/>
+          <var-decl name='mmap_count' type-id='49178f86' visibility='default' filepath='include/linux/perf_event.h' line='664' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5632'>
-          <var-decl name='rb' type-id='8462bc54' visibility='default' filepath='include/linux/perf_event.h' line='663' column='1'/>
+          <var-decl name='rb' type-id='8462bc54' visibility='default' filepath='include/linux/perf_event.h' line='666' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5696'>
-          <var-decl name='rb_entry' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='664' column='1'/>
+          <var-decl name='rb_entry' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='667' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5824'>
-          <var-decl name='rcu_batches' type-id='7359adad' visibility='default' filepath='include/linux/perf_event.h' line='665' column='1'/>
+          <var-decl name='rcu_batches' type-id='7359adad' visibility='default' filepath='include/linux/perf_event.h' line='668' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5888'>
-          <var-decl name='rcu_pending' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='666' column='1'/>
+          <var-decl name='rcu_pending' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='669' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5952'>
-          <var-decl name='waitq' type-id='b5ab048f' visibility='default' filepath='include/linux/perf_event.h' line='669' column='1'/>
+          <var-decl name='waitq' type-id='b5ab048f' visibility='default' filepath='include/linux/perf_event.h' line='672' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6144'>
-          <var-decl name='fasync' type-id='5bb9c75d' visibility='default' filepath='include/linux/perf_event.h' line='670' column='1'/>
+          <var-decl name='fasync' type-id='5bb9c75d' visibility='default' filepath='include/linux/perf_event.h' line='673' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6208'>
-          <var-decl name='pending_wakeup' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='673' column='1'/>
+          <var-decl name='pending_wakeup' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='676' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6240'>
-          <var-decl name='pending_kill' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='674' column='1'/>
+          <var-decl name='pending_kill' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='677' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6272'>
-          <var-decl name='pending_disable' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='675' column='1'/>
+          <var-decl name='pending_disable' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='678' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6336'>
-          <var-decl name='pending' type-id='9281c70f' visibility='default' filepath='include/linux/perf_event.h' line='676' column='1'/>
+          <var-decl name='pending' type-id='9281c70f' visibility='default' filepath='include/linux/perf_event.h' line='679' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6528'>
-          <var-decl name='event_limit' type-id='49178f86' visibility='default' filepath='include/linux/perf_event.h' line='678' column='1'/>
+          <var-decl name='event_limit' type-id='49178f86' visibility='default' filepath='include/linux/perf_event.h' line='681' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6592'>
-          <var-decl name='addr_filters' type-id='54885433' visibility='default' filepath='include/linux/perf_event.h' line='681' column='1'/>
+          <var-decl name='addr_filters' type-id='54885433' visibility='default' filepath='include/linux/perf_event.h' line='684' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6784'>
-          <var-decl name='addr_filter_ranges' type-id='200ffa89' visibility='default' filepath='include/linux/perf_event.h' line='683' column='1'/>
+          <var-decl name='addr_filter_ranges' type-id='200ffa89' visibility='default' filepath='include/linux/perf_event.h' line='686' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6848'>
-          <var-decl name='addr_filters_gen' type-id='7359adad' visibility='default' filepath='include/linux/perf_event.h' line='684' column='1'/>
+          <var-decl name='addr_filters_gen' type-id='7359adad' visibility='default' filepath='include/linux/perf_event.h' line='687' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6912'>
-          <var-decl name='destroy' type-id='aed2baa8' visibility='default' filepath='include/linux/perf_event.h' line='686' column='1'/>
+          <var-decl name='destroy' type-id='aed2baa8' visibility='default' filepath='include/linux/perf_event.h' line='689' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6976'>
-          <var-decl name='callback_head' type-id='e3d8ce29' visibility='default' filepath='include/linux/perf_event.h' line='687' column='1'/>
+          <var-decl name='callback_head' type-id='e3d8ce29' visibility='default' filepath='include/linux/perf_event.h' line='690' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7104'>
-          <var-decl name='ns' type-id='b816e1d0' visibility='default' filepath='include/linux/perf_event.h' line='689' column='1'/>
+          <var-decl name='ns' type-id='b816e1d0' visibility='default' filepath='include/linux/perf_event.h' line='692' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7168'>
-          <var-decl name='id' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='690' column='1'/>
+          <var-decl name='id' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='693' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7232'>
-          <var-decl name='clock' type-id='0e70db3e' visibility='default' filepath='include/linux/perf_event.h' line='692' column='1'/>
+          <var-decl name='clock' type-id='0e70db3e' visibility='default' filepath='include/linux/perf_event.h' line='695' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7296'>
-          <var-decl name='overflow_handler' type-id='20a2e4e6' visibility='default' filepath='include/linux/perf_event.h' line='693' column='1'/>
+          <var-decl name='overflow_handler' type-id='20a2e4e6' visibility='default' filepath='include/linux/perf_event.h' line='696' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7360'>
-          <var-decl name='overflow_handler_context' type-id='eaa32e2f' visibility='default' filepath='include/linux/perf_event.h' line='694' column='1'/>
+          <var-decl name='overflow_handler_context' type-id='eaa32e2f' visibility='default' filepath='include/linux/perf_event.h' line='697' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7424'>
-          <var-decl name='orig_overflow_handler' type-id='20a2e4e6' visibility='default' filepath='include/linux/perf_event.h' line='696' column='1'/>
+          <var-decl name='orig_overflow_handler' type-id='20a2e4e6' visibility='default' filepath='include/linux/perf_event.h' line='699' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7488'>
-          <var-decl name='prog' type-id='bdcee7ae' visibility='default' filepath='include/linux/perf_event.h' line='697' column='1'/>
+          <var-decl name='prog' type-id='bdcee7ae' visibility='default' filepath='include/linux/perf_event.h' line='700' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7552'>
-          <var-decl name='tp_event' type-id='23d6768c' visibility='default' filepath='include/linux/perf_event.h' line='701' column='1'/>
+          <var-decl name='tp_event' type-id='23d6768c' visibility='default' filepath='include/linux/perf_event.h' line='704' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7616'>
-          <var-decl name='filter' type-id='26461068' visibility='default' filepath='include/linux/perf_event.h' line='702' column='1'/>
+          <var-decl name='filter' type-id='26461068' visibility='default' filepath='include/linux/perf_event.h' line='705' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7680'>
-          <var-decl name='security' type-id='eaa32e2f' visibility='default' filepath='include/linux/perf_event.h' line='713' column='1'/>
+          <var-decl name='security' type-id='eaa32e2f' visibility='default' filepath='include/linux/perf_event.h' line='716' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7744'>
-          <var-decl name='sb_list' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='715' column='1'/>
+          <var-decl name='sb_list' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='718' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7872'>
-          <var-decl name='shared' type-id='b50a4934' visibility='default' filepath='include/linux/perf_event.h' line='717' column='1'/>
+          <var-decl name='shared' type-id='b50a4934' visibility='default' filepath='include/linux/perf_event.h' line='720' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7936'>
-          <var-decl name='dormant_event_entry' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='721' column='1'/>
+          <var-decl name='dormant_event_entry' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='724' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='perf_event_context' size-in-bits='2048' is-struct='yes' visibility='default' filepath='include/linux/perf_event.h' line='736' column='1' id='9d67acd5'>
+      <class-decl name='perf_event_context' size-in-bits='2048' is-struct='yes' visibility='default' filepath='include/linux/perf_event.h' line='739' column='1' id='9d67acd5'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='pmu' type-id='0906f5b9' visibility='default' filepath='include/linux/perf_event.h' line='737' column='1'/>
+          <var-decl name='pmu' type-id='0906f5b9' visibility='default' filepath='include/linux/perf_event.h' line='740' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='lock' type-id='f5c90b3f' visibility='default' filepath='include/linux/perf_event.h' line='742' column='1'/>
+          <var-decl name='lock' type-id='f5c90b3f' visibility='default' filepath='include/linux/perf_event.h' line='745' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='mutex' type-id='925167dc' visibility='default' filepath='include/linux/perf_event.h' line='748' column='1'/>
+          <var-decl name='mutex' type-id='925167dc' visibility='default' filepath='include/linux/perf_event.h' line='751' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='active_ctx_list' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='750' column='1'/>
+          <var-decl name='active_ctx_list' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='753' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='pinned_groups' type-id='3643bc2a' visibility='default' filepath='include/linux/perf_event.h' line='751' column='1'/>
+          <var-decl name='pinned_groups' type-id='3643bc2a' visibility='default' filepath='include/linux/perf_event.h' line='754' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='flexible_groups' type-id='3643bc2a' visibility='default' filepath='include/linux/perf_event.h' line='752' column='1'/>
+          <var-decl name='flexible_groups' type-id='3643bc2a' visibility='default' filepath='include/linux/perf_event.h' line='755' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='event_list' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='753' column='1'/>
+          <var-decl name='event_list' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='756' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='pinned_active' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='755' column='1'/>
+          <var-decl name='pinned_active' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='758' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='flexible_active' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='756' column='1'/>
+          <var-decl name='flexible_active' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='759' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='nr_events' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='758' column='1'/>
+          <var-decl name='nr_events' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='761' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1184'>
-          <var-decl name='nr_active' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='759' column='1'/>
+          <var-decl name='nr_active' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='762' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='is_active' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='760' column='1'/>
+          <var-decl name='is_active' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='763' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1248'>
-          <var-decl name='nr_stat' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='761' column='1'/>
+          <var-decl name='nr_stat' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='764' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='nr_freq' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='762' column='1'/>
+          <var-decl name='nr_freq' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='765' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1312'>
-          <var-decl name='rotate_disable' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='763' column='1'/>
+          <var-decl name='rotate_disable' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='766' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='refcount' type-id='49178f86' visibility='default' filepath='include/linux/perf_event.h' line='764' column='1'/>
+          <var-decl name='refcount' type-id='49178f86' visibility='default' filepath='include/linux/perf_event.h' line='767' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='task' type-id='f23e2572' visibility='default' filepath='include/linux/perf_event.h' line='765' column='1'/>
+          <var-decl name='task' type-id='f23e2572' visibility='default' filepath='include/linux/perf_event.h' line='768' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1472'>
-          <var-decl name='time' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='770' column='1'/>
+          <var-decl name='time' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='773' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='timestamp' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='771' column='1'/>
+          <var-decl name='timestamp' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='774' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1600'>
-          <var-decl name='parent_ctx' type-id='b9419dc5' visibility='default' filepath='include/linux/perf_event.h' line='777' column='1'/>
+          <var-decl name='parent_ctx' type-id='b9419dc5' visibility='default' filepath='include/linux/perf_event.h' line='780' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1664'>
-          <var-decl name='parent_gen' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='778' column='1'/>
+          <var-decl name='parent_gen' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='781' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1728'>
-          <var-decl name='generation' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='779' column='1'/>
+          <var-decl name='generation' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='782' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1792'>
-          <var-decl name='pin_count' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='780' column='1'/>
+          <var-decl name='pin_count' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='783' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='task_ctx_data' type-id='eaa32e2f' visibility='default' filepath='include/linux/perf_event.h' line='784' column='1'/>
+          <var-decl name='task_ctx_data' type-id='eaa32e2f' visibility='default' filepath='include/linux/perf_event.h' line='787' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1920'>
-          <var-decl name='callback_head' type-id='e3d8ce29' visibility='default' filepath='include/linux/perf_event.h' line='785' column='1'/>
+          <var-decl name='callback_head' type-id='e3d8ce29' visibility='default' filepath='include/linux/perf_event.h' line='788' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='pid_namespace' size-in-bits='1728' is-struct='yes' visibility='default' filepath='include/linux/pid_namespace.h' line='24' column='1' id='0252e252'>
@@ -8653,21 +8656,21 @@
           <var-decl name='xol_area' type-id='3d15880e' visibility='default' filepath='include/linux/uprobes.h' line='115' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='work_struct' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='103' column='1' id='ef9025d0'>
+      <class-decl name='work_struct' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='104' column='1' id='ef9025d0'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='data' type-id='f22a8abb' visibility='default' filepath='include/linux/workqueue.h' line='104' column='1'/>
+          <var-decl name='data' type-id='f22a8abb' visibility='default' filepath='include/linux/workqueue.h' line='105' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='entry' type-id='72f469ec' visibility='default' filepath='include/linux/workqueue.h' line='105' column='1'/>
+          <var-decl name='entry' type-id='72f469ec' visibility='default' filepath='include/linux/workqueue.h' line='106' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='func' type-id='72666d3f' visibility='default' filepath='include/linux/workqueue.h' line='106' column='1'/>
+          <var-decl name='func' type-id='72666d3f' visibility='default' filepath='include/linux/workqueue.h' line='107' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/workqueue.h' line='110' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/workqueue.h' line='111' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/workqueue.h' line='111' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/workqueue.h' line='112' column='1'/>
         </data-member>
       </class-decl>
       <typedef-decl name='work_func_t' type-id='939280af' filepath='include/linux/workqueue.h' line='22' column='1' id='72666d3f'/>
@@ -9536,24 +9539,24 @@
           <var-decl name='dir' type-id='7c7d6006' visibility='default' filepath='include/linux/sysctl.h' line='161' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='delayed_work' size-in-bits='1088' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='118' column='1' id='5ad6e0ef'>
+      <class-decl name='delayed_work' size-in-bits='1088' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='119' column='1' id='5ad6e0ef'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='work' type-id='ef9025d0' visibility='default' filepath='include/linux/workqueue.h' line='119' column='1'/>
+          <var-decl name='work' type-id='ef9025d0' visibility='default' filepath='include/linux/workqueue.h' line='120' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='timer' type-id='abe41e67' visibility='default' filepath='include/linux/workqueue.h' line='120' column='1'/>
+          <var-decl name='timer' type-id='abe41e67' visibility='default' filepath='include/linux/workqueue.h' line='121' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='wq' type-id='242e3d19' visibility='default' filepath='include/linux/workqueue.h' line='123' column='1'/>
+          <var-decl name='wq' type-id='242e3d19' visibility='default' filepath='include/linux/workqueue.h' line='124' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='cpu' type-id='95e97e5e' visibility='default' filepath='include/linux/workqueue.h' line='124' column='1'/>
+          <var-decl name='cpu' type-id='95e97e5e' visibility='default' filepath='include/linux/workqueue.h' line='125' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/workqueue.h' line='126' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/workqueue.h' line='127' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/workqueue.h' line='127' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/workqueue.h' line='128' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='fdtable' size-in-bits='448' is-struct='yes' visibility='default' filepath='include/linux/fdtable.h' line='26' column='1' id='ff35cfe1'>
@@ -9952,12 +9955,12 @@
           <var-decl name='__reserved_2' type-id='d315442e' visibility='default' filepath='include/uapi/linux/perf_event.h' line='424' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='perf_event_groups' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/linux/perf_event.h' line='726' column='1' id='3643bc2a'>
+      <class-decl name='perf_event_groups' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/linux/perf_event.h' line='729' column='1' id='3643bc2a'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='tree' type-id='dec44472' visibility='default' filepath='include/linux/perf_event.h' line='727' column='1'/>
+          <var-decl name='tree' type-id='dec44472' visibility='default' filepath='include/linux/perf_event.h' line='730' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='index' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='728' column='1'/>
+          <var-decl name='index' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='731' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='queue_limits' size-in-bits='832' is-struct='yes' visibility='default' filepath='include/linux/blkdev.h' line='373' column='1' id='f0966d3d'>
@@ -11891,12 +11894,12 @@
           <var-decl name='hash' type-id='53b70d6c' visibility='default' filepath='include/linux/elevator.h' line='190' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='event_filter' size-in-bits='128' is-struct='yes' visibility='default' filepath='kernel/trace/trace.h' line='1287' column='1' id='5ff1273a'>
+      <class-decl name='event_filter' size-in-bits='128' is-struct='yes' visibility='default' filepath='kernel/trace/trace.h' line='1289' column='1' id='5ff1273a'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='prog' type-id='efd0fdec' visibility='default' filepath='kernel/trace/trace.h' line='1288' column='1'/>
+          <var-decl name='prog' type-id='efd0fdec' visibility='default' filepath='kernel/trace/trace.h' line='1290' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='filter_string' type-id='26a90f95' visibility='default' filepath='kernel/trace/trace.h' line='1289' column='1'/>
+          <var-decl name='filter_string' type-id='26a90f95' visibility='default' filepath='kernel/trace/trace.h' line='1291' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='fasync_struct' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/linux/fs.h' line='1315' column='1' id='70c545cd'>
@@ -12645,176 +12648,176 @@
           <var-decl name='check_period' type-id='36f91979' visibility='default' filepath='include/linux/perf_event.h' line='457' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='proto' size-in-bits='3392' is-struct='yes' visibility='default' filepath='include/net/sock.h' line='1087' column='1' id='7203ee09'>
+      <class-decl name='proto' size-in-bits='3392' is-struct='yes' visibility='default' filepath='include/net/sock.h' line='1095' column='1' id='7203ee09'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='close' type-id='09f3a86b' visibility='default' filepath='include/net/sock.h' line='1088' column='1'/>
+          <var-decl name='close' type-id='09f3a86b' visibility='default' filepath='include/net/sock.h' line='1096' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='pre_connect' type-id='c25ed103' visibility='default' filepath='include/net/sock.h' line='1090' column='1'/>
+          <var-decl name='pre_connect' type-id='c25ed103' visibility='default' filepath='include/net/sock.h' line='1098' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='connect' type-id='c25ed103' visibility='default' filepath='include/net/sock.h' line='1093' column='1'/>
+          <var-decl name='connect' type-id='c25ed103' visibility='default' filepath='include/net/sock.h' line='1101' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='disconnect' type-id='95208a5e' visibility='default' filepath='include/net/sock.h' line='1096' column='1'/>
+          <var-decl name='disconnect' type-id='95208a5e' visibility='default' filepath='include/net/sock.h' line='1104' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='accept' type-id='67adf9a9' visibility='default' filepath='include/net/sock.h' line='1098' column='1'/>
+          <var-decl name='accept' type-id='67adf9a9' visibility='default' filepath='include/net/sock.h' line='1106' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='ioctl' type-id='08113f0a' visibility='default' filepath='include/net/sock.h' line='1101' column='1'/>
+          <var-decl name='ioctl' type-id='08113f0a' visibility='default' filepath='include/net/sock.h' line='1109' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='init' type-id='55530c47' visibility='default' filepath='include/net/sock.h' line='1103' column='1'/>
+          <var-decl name='init' type-id='55530c47' visibility='default' filepath='include/net/sock.h' line='1111' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='destroy' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1104' column='1'/>
+          <var-decl name='destroy' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1112' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='shutdown' type-id='e937debf' visibility='default' filepath='include/net/sock.h' line='1105' column='1'/>
+          <var-decl name='shutdown' type-id='e937debf' visibility='default' filepath='include/net/sock.h' line='1113' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='setsockopt' type-id='bc1bf185' visibility='default' filepath='include/net/sock.h' line='1106' column='1'/>
+          <var-decl name='setsockopt' type-id='bc1bf185' visibility='default' filepath='include/net/sock.h' line='1114' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='getsockopt' type-id='e0fadd76' visibility='default' filepath='include/net/sock.h' line='1109' column='1'/>
+          <var-decl name='getsockopt' type-id='e0fadd76' visibility='default' filepath='include/net/sock.h' line='1117' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='keepalive' type-id='e937debf' visibility='default' filepath='include/net/sock.h' line='1112' column='1'/>
+          <var-decl name='keepalive' type-id='e937debf' visibility='default' filepath='include/net/sock.h' line='1120' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='compat_setsockopt' type-id='bc1bf185' visibility='default' filepath='include/net/sock.h' line='1114' column='1'/>
+          <var-decl name='compat_setsockopt' type-id='bc1bf185' visibility='default' filepath='include/net/sock.h' line='1122' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='compat_getsockopt' type-id='e0fadd76' visibility='default' filepath='include/net/sock.h' line='1118' column='1'/>
+          <var-decl name='compat_getsockopt' type-id='e0fadd76' visibility='default' filepath='include/net/sock.h' line='1126' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='compat_ioctl' type-id='20da830b' visibility='default' filepath='include/net/sock.h' line='1122' column='1'/>
+          <var-decl name='compat_ioctl' type-id='20da830b' visibility='default' filepath='include/net/sock.h' line='1130' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='sendmsg' type-id='1df08751' visibility='default' filepath='include/net/sock.h' line='1125' column='1'/>
+          <var-decl name='sendmsg' type-id='1df08751' visibility='default' filepath='include/net/sock.h' line='1133' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='recvmsg' type-id='74e71fae' visibility='default' filepath='include/net/sock.h' line='1127' column='1'/>
+          <var-decl name='recvmsg' type-id='74e71fae' visibility='default' filepath='include/net/sock.h' line='1135' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='sendpage' type-id='65399e23' visibility='default' filepath='include/net/sock.h' line='1130' column='1'/>
+          <var-decl name='sendpage' type-id='65399e23' visibility='default' filepath='include/net/sock.h' line='1138' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='bind' type-id='c25ed103' visibility='default' filepath='include/net/sock.h' line='1132' column='1'/>
+          <var-decl name='bind' type-id='c25ed103' visibility='default' filepath='include/net/sock.h' line='1140' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='backlog_rcv' type-id='a0f5247f' visibility='default' filepath='include/net/sock.h' line='1135' column='1'/>
+          <var-decl name='backlog_rcv' type-id='a0f5247f' visibility='default' filepath='include/net/sock.h' line='1143' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='release_cb' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1138' column='1'/>
+          <var-decl name='release_cb' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1146' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='hash' type-id='55530c47' visibility='default' filepath='include/net/sock.h' line='1141' column='1'/>
+          <var-decl name='hash' type-id='55530c47' visibility='default' filepath='include/net/sock.h' line='1149' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='unhash' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1142' column='1'/>
+          <var-decl name='unhash' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1150' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1472'>
-          <var-decl name='rehash' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1143' column='1'/>
+          <var-decl name='rehash' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1151' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='get_port' type-id='078de3a3' visibility='default' filepath='include/net/sock.h' line='1144' column='1'/>
+          <var-decl name='get_port' type-id='078de3a3' visibility='default' filepath='include/net/sock.h' line='1152' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1600'>
-          <var-decl name='inuse_idx' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1148' column='1'/>
+          <var-decl name='inuse_idx' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1156' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1664'>
-          <var-decl name='stream_memory_free' type-id='3d4d3aba' visibility='default' filepath='include/net/sock.h' line='1151' column='1'/>
+          <var-decl name='stream_memory_free' type-id='3d4d3aba' visibility='default' filepath='include/net/sock.h' line='1159' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1728'>
-          <var-decl name='stream_memory_read' type-id='3d4d3aba' visibility='default' filepath='include/net/sock.h' line='1152' column='1'/>
+          <var-decl name='stream_memory_read' type-id='3d4d3aba' visibility='default' filepath='include/net/sock.h' line='1160' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1792'>
-          <var-decl name='enter_memory_pressure' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1154' column='1'/>
+          <var-decl name='enter_memory_pressure' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1162' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='leave_memory_pressure' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1155' column='1'/>
+          <var-decl name='leave_memory_pressure' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1163' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1920'>
-          <var-decl name='memory_allocated' type-id='5403cb36' visibility='default' filepath='include/net/sock.h' line='1156' column='1'/>
+          <var-decl name='memory_allocated' type-id='5403cb36' visibility='default' filepath='include/net/sock.h' line='1164' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1984'>
-          <var-decl name='sockets_allocated' type-id='84c6078d' visibility='default' filepath='include/net/sock.h' line='1157' column='1'/>
+          <var-decl name='sockets_allocated' type-id='84c6078d' visibility='default' filepath='include/net/sock.h' line='1165' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='memory_pressure' type-id='1d2c2b85' visibility='default' filepath='include/net/sock.h' line='1164' column='1'/>
+          <var-decl name='memory_pressure' type-id='1d2c2b85' visibility='default' filepath='include/net/sock.h' line='1173' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='sysctl_mem' type-id='3ccc2590' visibility='default' filepath='include/net/sock.h' line='1165' column='1'/>
+          <var-decl name='sysctl_mem' type-id='3ccc2590' visibility='default' filepath='include/net/sock.h' line='1174' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2176'>
-          <var-decl name='sysctl_wmem' type-id='7292109c' visibility='default' filepath='include/net/sock.h' line='1167' column='1'/>
+          <var-decl name='sysctl_wmem' type-id='7292109c' visibility='default' filepath='include/net/sock.h' line='1176' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2240'>
-          <var-decl name='sysctl_rmem' type-id='7292109c' visibility='default' filepath='include/net/sock.h' line='1168' column='1'/>
+          <var-decl name='sysctl_rmem' type-id='7292109c' visibility='default' filepath='include/net/sock.h' line='1177' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2304'>
-          <var-decl name='sysctl_wmem_offset' type-id='19c2251e' visibility='default' filepath='include/net/sock.h' line='1169' column='1'/>
+          <var-decl name='sysctl_wmem_offset' type-id='19c2251e' visibility='default' filepath='include/net/sock.h' line='1178' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2336'>
-          <var-decl name='sysctl_rmem_offset' type-id='19c2251e' visibility='default' filepath='include/net/sock.h' line='1170' column='1'/>
+          <var-decl name='sysctl_rmem_offset' type-id='19c2251e' visibility='default' filepath='include/net/sock.h' line='1179' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2368'>
-          <var-decl name='max_header' type-id='95e97e5e' visibility='default' filepath='include/net/sock.h' line='1172' column='1'/>
+          <var-decl name='max_header' type-id='95e97e5e' visibility='default' filepath='include/net/sock.h' line='1181' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2400'>
-          <var-decl name='no_autobind' type-id='b50a4934' visibility='default' filepath='include/net/sock.h' line='1173' column='1'/>
+          <var-decl name='no_autobind' type-id='b50a4934' visibility='default' filepath='include/net/sock.h' line='1182' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2432'>
-          <var-decl name='slab' type-id='f3b4aca8' visibility='default' filepath='include/net/sock.h' line='1175' column='1'/>
+          <var-decl name='slab' type-id='f3b4aca8' visibility='default' filepath='include/net/sock.h' line='1184' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2496'>
-          <var-decl name='obj_size' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1176' column='1'/>
+          <var-decl name='obj_size' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1185' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2528'>
-          <var-decl name='slab_flags' type-id='f7fe96cb' visibility='default' filepath='include/net/sock.h' line='1177' column='1'/>
+          <var-decl name='slab_flags' type-id='f7fe96cb' visibility='default' filepath='include/net/sock.h' line='1186' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2560'>
-          <var-decl name='useroffset' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1178' column='1'/>
+          <var-decl name='useroffset' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1187' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2592'>
-          <var-decl name='usersize' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1179' column='1'/>
+          <var-decl name='usersize' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1188' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2624'>
-          <var-decl name='orphan_count' type-id='84c6078d' visibility='default' filepath='include/net/sock.h' line='1181' column='1'/>
+          <var-decl name='orphan_count' type-id='84c6078d' visibility='default' filepath='include/net/sock.h' line='1190' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2688'>
-          <var-decl name='rsk_prot' type-id='db994912' visibility='default' filepath='include/net/sock.h' line='1183' column='1'/>
+          <var-decl name='rsk_prot' type-id='db994912' visibility='default' filepath='include/net/sock.h' line='1192' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2752'>
-          <var-decl name='twsk_prot' type-id='d68ad8b5' visibility='default' filepath='include/net/sock.h' line='1184' column='1'/>
+          <var-decl name='twsk_prot' type-id='d68ad8b5' visibility='default' filepath='include/net/sock.h' line='1193' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2816'>
-          <var-decl name='h' type-id='adf5bf47' visibility='default' filepath='include/net/sock.h' line='1191' column='1'/>
+          <var-decl name='h' type-id='adf5bf47' visibility='default' filepath='include/net/sock.h' line='1200' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2880'>
-          <var-decl name='owner' type-id='2730d015' visibility='default' filepath='include/net/sock.h' line='1193' column='1'/>
+          <var-decl name='owner' type-id='2730d015' visibility='default' filepath='include/net/sock.h' line='1202' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2944'>
-          <var-decl name='name' type-id='16dc656a' visibility='default' filepath='include/net/sock.h' line='1195' column='1'/>
+          <var-decl name='name' type-id='16dc656a' visibility='default' filepath='include/net/sock.h' line='1204' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3200'>
-          <var-decl name='node' type-id='72f469ec' visibility='default' filepath='include/net/sock.h' line='1197' column='1'/>
+          <var-decl name='node' type-id='72f469ec' visibility='default' filepath='include/net/sock.h' line='1206' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3328'>
-          <var-decl name='diag_destroy' type-id='95208a5e' visibility='default' filepath='include/net/sock.h' line='1201' column='1'/>
+          <var-decl name='diag_destroy' type-id='95208a5e' visibility='default' filepath='include/net/sock.h' line='1210' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='rcu_work' size-in-bits='576' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='130' column='1' id='7c0b9fdb'>
+      <class-decl name='rcu_work' size-in-bits='576' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='131' column='1' id='7c0b9fdb'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='work' type-id='ef9025d0' visibility='default' filepath='include/linux/workqueue.h' line='131' column='1'/>
+          <var-decl name='work' type-id='ef9025d0' visibility='default' filepath='include/linux/workqueue.h' line='132' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/linux/workqueue.h' line='132' column='1'/>
+          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/linux/workqueue.h' line='133' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='wq' type-id='242e3d19' visibility='default' filepath='include/linux/workqueue.h' line='135' column='1'/>
+          <var-decl name='wq' type-id='242e3d19' visibility='default' filepath='include/linux/workqueue.h' line='136' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='request' size-in-bits='2432' is-struct='yes' visibility='default' filepath='include/linux/blkdev.h' line='159' column='1' id='ceee71ca'>
@@ -15517,10 +15520,10 @@
           <var-decl name='hooks_bridge' type-id='94310593' visibility='default' filepath='include/net/netns/netfilter.h' line='25' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2176'>
-          <var-decl name='defrag_ipv4' type-id='b50a4934' visibility='default' filepath='include/net/netns/netfilter.h' line='30' column='1'/>
+          <var-decl name='defrag_ipv4' type-id='b50a4934' visibility='default' filepath='include/net/netns/netfilter.h' line='27' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2184'>
-          <var-decl name='defrag_ipv6' type-id='b50a4934' visibility='default' filepath='include/net/netns/netfilter.h' line='33' column='1'/>
+          <var-decl name='defrag_ipv6' type-id='b50a4934' visibility='default' filepath='include/net/netns/netfilter.h' line='30' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='netns_nf_frag' size-in-bits='2560' is-struct='yes' visibility='default' filepath='include/net/netns/ipv6.h' line='112' column='1' id='ebd39a5d'>
@@ -16730,18 +16733,18 @@
           <var-decl name='__rcu_head' type-id='e3d8ce29' visibility='default' filepath='include/linux/iocontext.h' line='89' column='1'/>
         </data-member>
       </union-decl>
-      <union-decl name='__anonymous_union__35' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/net/sock.h' line='1186' column='1' id='adf5bf47'>
+      <union-decl name='__anonymous_union__35' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/net/sock.h' line='1195' column='1' id='adf5bf47'>
         <data-member access='public'>
-          <var-decl name='hashinfo' type-id='d7a1e3c2' visibility='default' filepath='include/net/sock.h' line='1187' column='1'/>
+          <var-decl name='hashinfo' type-id='d7a1e3c2' visibility='default' filepath='include/net/sock.h' line='1196' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='udp_table' type-id='115daa23' visibility='default' filepath='include/net/sock.h' line='1188' column='1'/>
+          <var-decl name='udp_table' type-id='115daa23' visibility='default' filepath='include/net/sock.h' line='1197' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='raw_hash' type-id='eb2c56dc' visibility='default' filepath='include/net/sock.h' line='1189' column='1'/>
+          <var-decl name='raw_hash' type-id='eb2c56dc' visibility='default' filepath='include/net/sock.h' line='1198' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='smc_hash' type-id='aa8162a3' visibility='default' filepath='include/net/sock.h' line='1190' column='1'/>
+          <var-decl name='smc_hash' type-id='aa8162a3' visibility='default' filepath='include/net/sock.h' line='1199' column='1'/>
         </data-member>
       </union-decl>
       <union-decl name='__anonymous_union__7' size-in-bits='256' is-anonymous='yes' visibility='default' filepath='include/linux/key.h' line='214' column='1' id='d5d77d48'>
@@ -18082,431 +18085,431 @@
           <var-decl name='pgdat' type-id='c876a7a5' visibility='default' filepath='include/linux/mmzone.h' line='255' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='lwtunnel_state' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/net/lwtunnel.h' line='25' column='1' id='44644afc'>
+      <class-decl name='lwtunnel_state' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/net/lwtunnel.h' line='28' column='1' id='44644afc'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='type' type-id='d315442e' visibility='default' filepath='include/net/lwtunnel.h' line='26' column='1'/>
+          <var-decl name='type' type-id='d315442e' visibility='default' filepath='include/net/lwtunnel.h' line='29' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='flags' type-id='d315442e' visibility='default' filepath='include/net/lwtunnel.h' line='27' column='1'/>
+          <var-decl name='flags' type-id='d315442e' visibility='default' filepath='include/net/lwtunnel.h' line='30' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='headroom' type-id='d315442e' visibility='default' filepath='include/net/lwtunnel.h' line='28' column='1'/>
+          <var-decl name='headroom' type-id='d315442e' visibility='default' filepath='include/net/lwtunnel.h' line='31' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='refcnt' type-id='49178f86' visibility='default' filepath='include/net/lwtunnel.h' line='29' column='1'/>
+          <var-decl name='refcnt' type-id='49178f86' visibility='default' filepath='include/net/lwtunnel.h' line='32' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='orig_output' type-id='0023218e' visibility='default' filepath='include/net/lwtunnel.h' line='30' column='1'/>
+          <var-decl name='orig_output' type-id='0023218e' visibility='default' filepath='include/net/lwtunnel.h' line='33' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='orig_input' type-id='d2e00785' visibility='default' filepath='include/net/lwtunnel.h' line='31' column='1'/>
+          <var-decl name='orig_input' type-id='d2e00785' visibility='default' filepath='include/net/lwtunnel.h' line='34' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/net/lwtunnel.h' line='32' column='1'/>
+          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/net/lwtunnel.h' line='35' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='data' type-id='167619f6' visibility='default' filepath='include/net/lwtunnel.h' line='33' column='1'/>
+          <var-decl name='data' type-id='167619f6' visibility='default' filepath='include/net/lwtunnel.h' line='36' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='net_device' size-in-bits='19456' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='1786' column='1' id='5a9929eb'>
+      <class-decl name='net_device' size-in-bits='19456' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='1788' column='1' id='5a9929eb'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='name' type-id='ac1fa8c0' visibility='default' filepath='include/linux/netdevice.h' line='1787' column='1'/>
+          <var-decl name='name' type-id='ac1fa8c0' visibility='default' filepath='include/linux/netdevice.h' line='1789' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='name_hlist' type-id='03a4a074' visibility='default' filepath='include/linux/netdevice.h' line='1788' column='1'/>
+          <var-decl name='name_hlist' type-id='03a4a074' visibility='default' filepath='include/linux/netdevice.h' line='1790' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ifalias' type-id='d81cf24c' visibility='default' filepath='include/linux/netdevice.h' line='1789' column='1'/>
+          <var-decl name='ifalias' type-id='d81cf24c' visibility='default' filepath='include/linux/netdevice.h' line='1791' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='mem_end' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1794' column='1'/>
+          <var-decl name='mem_end' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1796' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='mem_start' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1795' column='1'/>
+          <var-decl name='mem_start' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1797' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='base_addr' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1796' column='1'/>
+          <var-decl name='base_addr' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1798' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='irq' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1797' column='1'/>
+          <var-decl name='irq' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1799' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='state' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1805' column='1'/>
+          <var-decl name='state' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1807' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='dev_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1807' column='1'/>
+          <var-decl name='dev_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1809' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='napi_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1808' column='1'/>
+          <var-decl name='napi_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1810' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='unreg_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1809' column='1'/>
+          <var-decl name='unreg_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1811' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='close_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1810' column='1'/>
+          <var-decl name='close_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1812' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='ptype_all' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1811' column='1'/>
+          <var-decl name='ptype_all' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1813' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='ptype_specific' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1812' column='1'/>
+          <var-decl name='ptype_specific' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1814' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='adj_list' type-id='19245258' visibility='default' filepath='include/linux/netdevice.h' line='1817' column='1'/>
+          <var-decl name='adj_list' type-id='19245258' visibility='default' filepath='include/linux/netdevice.h' line='1819' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1664'>
-          <var-decl name='features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1819' column='1'/>
+          <var-decl name='features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1821' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1728'>
-          <var-decl name='hw_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1820' column='1'/>
+          <var-decl name='hw_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1822' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1792'>
-          <var-decl name='wanted_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1821' column='1'/>
+          <var-decl name='wanted_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1823' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='vlan_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1822' column='1'/>
+          <var-decl name='vlan_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1824' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1920'>
-          <var-decl name='hw_enc_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1823' column='1'/>
+          <var-decl name='hw_enc_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1825' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1984'>
-          <var-decl name='mpls_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1824' column='1'/>
+          <var-decl name='mpls_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1826' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='gso_partial_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1825' column='1'/>
+          <var-decl name='gso_partial_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1827' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='ifindex' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1827' column='1'/>
+          <var-decl name='ifindex' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1829' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2144'>
-          <var-decl name='group' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1828' column='1'/>
+          <var-decl name='group' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1830' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2176'>
-          <var-decl name='stats' type-id='a3566137' visibility='default' filepath='include/linux/netdevice.h' line='1830' column='1'/>
+          <var-decl name='stats' type-id='a3566137' visibility='default' filepath='include/linux/netdevice.h' line='1832' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3648'>
-          <var-decl name='rx_dropped' type-id='f22a8abb' visibility='default' filepath='include/linux/netdevice.h' line='1832' column='1'/>
+          <var-decl name='rx_dropped' type-id='f22a8abb' visibility='default' filepath='include/linux/netdevice.h' line='1834' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3712'>
-          <var-decl name='tx_dropped' type-id='f22a8abb' visibility='default' filepath='include/linux/netdevice.h' line='1833' column='1'/>
+          <var-decl name='tx_dropped' type-id='f22a8abb' visibility='default' filepath='include/linux/netdevice.h' line='1835' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3776'>
-          <var-decl name='rx_nohandler' type-id='f22a8abb' visibility='default' filepath='include/linux/netdevice.h' line='1834' column='1'/>
+          <var-decl name='rx_nohandler' type-id='f22a8abb' visibility='default' filepath='include/linux/netdevice.h' line='1836' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3840'>
-          <var-decl name='carrier_up_count' type-id='49178f86' visibility='default' filepath='include/linux/netdevice.h' line='1837' column='1'/>
+          <var-decl name='carrier_up_count' type-id='49178f86' visibility='default' filepath='include/linux/netdevice.h' line='1839' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3872'>
-          <var-decl name='carrier_down_count' type-id='49178f86' visibility='default' filepath='include/linux/netdevice.h' line='1838' column='1'/>
+          <var-decl name='carrier_down_count' type-id='49178f86' visibility='default' filepath='include/linux/netdevice.h' line='1840' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3904'>
-          <var-decl name='wireless_handlers' type-id='3e2bb973' visibility='default' filepath='include/linux/netdevice.h' line='1841' column='1'/>
+          <var-decl name='wireless_handlers' type-id='3e2bb973' visibility='default' filepath='include/linux/netdevice.h' line='1843' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3968'>
-          <var-decl name='wireless_data' type-id='e40f7bda' visibility='default' filepath='include/linux/netdevice.h' line='1842' column='1'/>
+          <var-decl name='wireless_data' type-id='e40f7bda' visibility='default' filepath='include/linux/netdevice.h' line='1844' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4032'>
-          <var-decl name='netdev_ops' type-id='a84ec761' visibility='default' filepath='include/linux/netdevice.h' line='1844' column='1'/>
+          <var-decl name='netdev_ops' type-id='a84ec761' visibility='default' filepath='include/linux/netdevice.h' line='1846' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4096'>
-          <var-decl name='ethtool_ops' type-id='bdf901f8' visibility='default' filepath='include/linux/netdevice.h' line='1845' column='1'/>
+          <var-decl name='ethtool_ops' type-id='bdf901f8' visibility='default' filepath='include/linux/netdevice.h' line='1847' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4160'>
-          <var-decl name='ndisc_ops' type-id='a2e418a6' visibility='default' filepath='include/linux/netdevice.h' line='1853' column='1'/>
+          <var-decl name='ndisc_ops' type-id='a2e418a6' visibility='default' filepath='include/linux/netdevice.h' line='1855' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4224'>
-          <var-decl name='header_ops' type-id='2d747e78' visibility='default' filepath='include/linux/netdevice.h' line='1864' column='1'/>
+          <var-decl name='header_ops' type-id='2d747e78' visibility='default' filepath='include/linux/netdevice.h' line='1866' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4288'>
-          <var-decl name='flags' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1866' column='1'/>
+          <var-decl name='flags' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1868' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4320'>
-          <var-decl name='priv_flags' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1867' column='1'/>
+          <var-decl name='priv_flags' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1869' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4352'>
-          <var-decl name='gflags' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1869' column='1'/>
+          <var-decl name='gflags' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1871' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4368'>
-          <var-decl name='padded' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1870' column='1'/>
+          <var-decl name='padded' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1872' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4384'>
-          <var-decl name='operstate' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1872' column='1'/>
+          <var-decl name='operstate' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1874' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4392'>
-          <var-decl name='link_mode' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1873' column='1'/>
+          <var-decl name='link_mode' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1875' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4400'>
-          <var-decl name='if_port' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1875' column='1'/>
+          <var-decl name='if_port' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1877' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4408'>
-          <var-decl name='dma' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1876' column='1'/>
+          <var-decl name='dma' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1878' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4416'>
-          <var-decl name='mtu' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1883' column='1'/>
+          <var-decl name='mtu' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1885' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4448'>
-          <var-decl name='min_mtu' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1884' column='1'/>
+          <var-decl name='min_mtu' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1886' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4480'>
-          <var-decl name='max_mtu' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1885' column='1'/>
+          <var-decl name='max_mtu' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1887' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4512'>
-          <var-decl name='type' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1886' column='1'/>
+          <var-decl name='type' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1888' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4528'>
-          <var-decl name='hard_header_len' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1887' column='1'/>
+          <var-decl name='hard_header_len' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1889' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4544'>
-          <var-decl name='min_header_len' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1888' column='1'/>
+          <var-decl name='min_header_len' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1890' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4560'>
-          <var-decl name='needed_headroom' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1890' column='1'/>
+          <var-decl name='needed_headroom' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1892' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4576'>
-          <var-decl name='needed_tailroom' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1891' column='1'/>
+          <var-decl name='needed_tailroom' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1893' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4592'>
-          <var-decl name='perm_addr' type-id='fc872715' visibility='default' filepath='include/linux/netdevice.h' line='1894' column='1'/>
+          <var-decl name='perm_addr' type-id='fc872715' visibility='default' filepath='include/linux/netdevice.h' line='1896' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4848'>
-          <var-decl name='addr_assign_type' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1895' column='1'/>
+          <var-decl name='addr_assign_type' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1897' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4856'>
-          <var-decl name='addr_len' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1896' column='1'/>
+          <var-decl name='addr_len' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1898' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4864'>
-          <var-decl name='upper_level' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1897' column='1'/>
+          <var-decl name='upper_level' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1899' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4872'>
-          <var-decl name='lower_level' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1898' column='1'/>
+          <var-decl name='lower_level' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1900' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4880'>
-          <var-decl name='neigh_priv_len' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1899' column='1'/>
+          <var-decl name='neigh_priv_len' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1901' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4896'>
-          <var-decl name='dev_id' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1900' column='1'/>
+          <var-decl name='dev_id' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1902' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4912'>
-          <var-decl name='dev_port' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1901' column='1'/>
+          <var-decl name='dev_port' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1903' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4928'>
-          <var-decl name='addr_list_lock' type-id='fb4018a0' visibility='default' filepath='include/linux/netdevice.h' line='1902' column='1'/>
+          <var-decl name='addr_list_lock' type-id='fb4018a0' visibility='default' filepath='include/linux/netdevice.h' line='1904' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4960'>
-          <var-decl name='name_assign_type' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1903' column='1'/>
+          <var-decl name='name_assign_type' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1905' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4968'>
-          <var-decl name='uc_promisc' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='1904' column='1'/>
+          <var-decl name='uc_promisc' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='1906' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4992'>
-          <var-decl name='uc' type-id='44a1ec32' visibility='default' filepath='include/linux/netdevice.h' line='1905' column='1'/>
+          <var-decl name='uc' type-id='44a1ec32' visibility='default' filepath='include/linux/netdevice.h' line='1907' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5184'>
-          <var-decl name='mc' type-id='44a1ec32' visibility='default' filepath='include/linux/netdevice.h' line='1906' column='1'/>
+          <var-decl name='mc' type-id='44a1ec32' visibility='default' filepath='include/linux/netdevice.h' line='1908' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5376'>
-          <var-decl name='dev_addrs' type-id='44a1ec32' visibility='default' filepath='include/linux/netdevice.h' line='1907' column='1'/>
+          <var-decl name='dev_addrs' type-id='44a1ec32' visibility='default' filepath='include/linux/netdevice.h' line='1909' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5568'>
-          <var-decl name='queues_kset' type-id='89b70200' visibility='default' filepath='include/linux/netdevice.h' line='1910' column='1'/>
+          <var-decl name='queues_kset' type-id='89b70200' visibility='default' filepath='include/linux/netdevice.h' line='1912' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5632'>
-          <var-decl name='promiscuity' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1912' column='1'/>
+          <var-decl name='promiscuity' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1914' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5664'>
-          <var-decl name='allmulti' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1913' column='1'/>
+          <var-decl name='allmulti' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1915' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5696'>
-          <var-decl name='tipc_ptr' type-id='eeaf504d' visibility='default' filepath='include/linux/netdevice.h' line='1925' column='1'/>
+          <var-decl name='tipc_ptr' type-id='eeaf504d' visibility='default' filepath='include/linux/netdevice.h' line='1927' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5760'>
-          <var-decl name='ip_ptr' type-id='fc6f14a9' visibility='default' filepath='include/linux/netdevice.h' line='1930' column='1'/>
+          <var-decl name='ip_ptr' type-id='fc6f14a9' visibility='default' filepath='include/linux/netdevice.h' line='1932' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5824'>
-          <var-decl name='ip6_ptr' type-id='f026b16b' visibility='default' filepath='include/linux/netdevice.h' line='1934' column='1'/>
+          <var-decl name='ip6_ptr' type-id='f026b16b' visibility='default' filepath='include/linux/netdevice.h' line='1933' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5888'>
-          <var-decl name='ieee80211_ptr' type-id='63c7e8e1' visibility='default' filepath='include/linux/netdevice.h' line='1938' column='1'/>
+          <var-decl name='ieee80211_ptr' type-id='63c7e8e1' visibility='default' filepath='include/linux/netdevice.h' line='1937' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5952'>
-          <var-decl name='ieee802154_ptr' type-id='165146ad' visibility='default' filepath='include/linux/netdevice.h' line='1939' column='1'/>
+          <var-decl name='ieee802154_ptr' type-id='165146ad' visibility='default' filepath='include/linux/netdevice.h' line='1938' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6016'>
-          <var-decl name='dev_addr' type-id='cf536864' visibility='default' filepath='include/linux/netdevice.h' line='1948' column='1'/>
+          <var-decl name='dev_addr' type-id='cf536864' visibility='default' filepath='include/linux/netdevice.h' line='1947' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6080'>
-          <var-decl name='_rx' type-id='31094274' visibility='default' filepath='include/linux/netdevice.h' line='1950' column='1'/>
+          <var-decl name='_rx' type-id='31094274' visibility='default' filepath='include/linux/netdevice.h' line='1949' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6144'>
-          <var-decl name='num_rx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1951' column='1'/>
+          <var-decl name='num_rx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1950' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6176'>
-          <var-decl name='real_num_rx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1952' column='1'/>
+          <var-decl name='real_num_rx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1951' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6208'>
-          <var-decl name='xdp_prog' type-id='bdcee7ae' visibility='default' filepath='include/linux/netdevice.h' line='1954' column='1'/>
+          <var-decl name='xdp_prog' type-id='bdcee7ae' visibility='default' filepath='include/linux/netdevice.h' line='1953' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6272'>
-          <var-decl name='gro_flush_timeout' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1955' column='1'/>
+          <var-decl name='gro_flush_timeout' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1954' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6336'>
-          <var-decl name='rx_handler' type-id='da1cb816' visibility='default' filepath='include/linux/netdevice.h' line='1956' column='1'/>
+          <var-decl name='rx_handler' type-id='da1cb816' visibility='default' filepath='include/linux/netdevice.h' line='1955' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6400'>
-          <var-decl name='rx_handler_data' type-id='eaa32e2f' visibility='default' filepath='include/linux/netdevice.h' line='1957' column='1'/>
+          <var-decl name='rx_handler_data' type-id='eaa32e2f' visibility='default' filepath='include/linux/netdevice.h' line='1956' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6464'>
-          <var-decl name='miniq_ingress' type-id='b70f37f7' visibility='default' filepath='include/linux/netdevice.h' line='1960' column='1'/>
+          <var-decl name='miniq_ingress' type-id='b70f37f7' visibility='default' filepath='include/linux/netdevice.h' line='1959' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6528'>
-          <var-decl name='ingress_queue' type-id='35b28c4f' visibility='default' filepath='include/linux/netdevice.h' line='1962' column='1'/>
+          <var-decl name='ingress_queue' type-id='35b28c4f' visibility='default' filepath='include/linux/netdevice.h' line='1961' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6592'>
-          <var-decl name='nf_hooks_ingress' type-id='39a43b40' visibility='default' filepath='include/linux/netdevice.h' line='1964' column='1'/>
+          <var-decl name='nf_hooks_ingress' type-id='39a43b40' visibility='default' filepath='include/linux/netdevice.h' line='1963' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6656'>
-          <var-decl name='broadcast' type-id='fc872715' visibility='default' filepath='include/linux/netdevice.h' line='1967' column='1'/>
+          <var-decl name='broadcast' type-id='fc872715' visibility='default' filepath='include/linux/netdevice.h' line='1966' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6912'>
-          <var-decl name='rx_cpu_rmap' type-id='52baee64' visibility='default' filepath='include/linux/netdevice.h' line='1969' column='1'/>
+          <var-decl name='rx_cpu_rmap' type-id='52baee64' visibility='default' filepath='include/linux/netdevice.h' line='1968' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6976'>
-          <var-decl name='index_hlist' type-id='03a4a074' visibility='default' filepath='include/linux/netdevice.h' line='1971' column='1'/>
+          <var-decl name='index_hlist' type-id='03a4a074' visibility='default' filepath='include/linux/netdevice.h' line='1970' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7168'>
-          <var-decl name='_tx' type-id='35b28c4f' visibility='default' filepath='include/linux/netdevice.h' line='1976' column='1'/>
+          <var-decl name='_tx' type-id='35b28c4f' visibility='default' filepath='include/linux/netdevice.h' line='1975' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7232'>
-          <var-decl name='num_tx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1977' column='1'/>
+          <var-decl name='num_tx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1976' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7264'>
-          <var-decl name='real_num_tx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1978' column='1'/>
+          <var-decl name='real_num_tx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1977' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7296'>
-          <var-decl name='qdisc' type-id='ee406209' visibility='default' filepath='include/linux/netdevice.h' line='1979' column='1'/>
+          <var-decl name='qdisc' type-id='ee406209' visibility='default' filepath='include/linux/netdevice.h' line='1978' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7360'>
-          <var-decl name='qdisc_hash' type-id='ccfd385f' visibility='default' filepath='include/linux/netdevice.h' line='1981' column='1'/>
+          <var-decl name='qdisc_hash' type-id='ccfd385f' visibility='default' filepath='include/linux/netdevice.h' line='1980' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8384'>
-          <var-decl name='tx_queue_len' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1983' column='1'/>
+          <var-decl name='tx_queue_len' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1982' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8416'>
-          <var-decl name='tx_global_lock' type-id='fb4018a0' visibility='default' filepath='include/linux/netdevice.h' line='1984' column='1'/>
+          <var-decl name='tx_global_lock' type-id='fb4018a0' visibility='default' filepath='include/linux/netdevice.h' line='1983' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8448'>
-          <var-decl name='watchdog_timeo' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1985' column='1'/>
+          <var-decl name='watchdog_timeo' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1984' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8512'>
-          <var-decl name='xps_cpus_map' type-id='bf237056' visibility='default' filepath='include/linux/netdevice.h' line='1988' column='1'/>
+          <var-decl name='xps_cpus_map' type-id='bf237056' visibility='default' filepath='include/linux/netdevice.h' line='1987' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8576'>
-          <var-decl name='xps_rxqs_map' type-id='bf237056' visibility='default' filepath='include/linux/netdevice.h' line='1989' column='1'/>
+          <var-decl name='xps_rxqs_map' type-id='bf237056' visibility='default' filepath='include/linux/netdevice.h' line='1988' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8640'>
-          <var-decl name='miniq_egress' type-id='b70f37f7' visibility='default' filepath='include/linux/netdevice.h' line='1992' column='1'/>
+          <var-decl name='miniq_egress' type-id='b70f37f7' visibility='default' filepath='include/linux/netdevice.h' line='1991' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8704'>
-          <var-decl name='watchdog_timer' type-id='abe41e67' visibility='default' filepath='include/linux/netdevice.h' line='1996' column='1'/>
+          <var-decl name='watchdog_timer' type-id='abe41e67' visibility='default' filepath='include/linux/netdevice.h' line='1995' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9152'>
-          <var-decl name='pcpu_refcnt' type-id='7292109c' visibility='default' filepath='include/linux/netdevice.h' line='1998' column='1'/>
+          <var-decl name='pcpu_refcnt' type-id='7292109c' visibility='default' filepath='include/linux/netdevice.h' line='1997' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9216'>
-          <var-decl name='todo_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1999' column='1'/>
+          <var-decl name='todo_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1998' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9344'>
-          <var-decl name='link_watch_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='2001' column='1'/>
+          <var-decl name='link_watch_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='2000' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='reg_state' type-id='08f5ca18' visibility='default' filepath='include/linux/netdevice.h' line='2009' column='1'/>
+          <var-decl name='reg_state' type-id='08f5ca18' visibility='default' filepath='include/linux/netdevice.h' line='2008' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9480'>
-          <var-decl name='dismantle' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='2011' column='1'/>
+          <var-decl name='dismantle' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='2010' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='rtnl_link_state' type-id='08f5ca19' visibility='default' filepath='include/linux/netdevice.h' line='2016' column='1'/>
+          <var-decl name='rtnl_link_state' type-id='08f5ca19' visibility='default' filepath='include/linux/netdevice.h' line='2015' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9504'>
-          <var-decl name='needs_free_netdev' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='2018' column='1'/>
+          <var-decl name='needs_free_netdev' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='2017' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9536'>
-          <var-decl name='priv_destructor' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='2019' column='1'/>
+          <var-decl name='priv_destructor' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='2018' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9600'>
-          <var-decl name='nd_net' type-id='c9df1e6c' visibility='default' filepath='include/linux/netdevice.h' line='2025' column='1'/>
+          <var-decl name='nd_net' type-id='c9df1e6c' visibility='default' filepath='include/linux/netdevice.h' line='2024' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9664'>
-          <var-decl name='' type-id='38feef9e' visibility='default' filepath='include/linux/netdevice.h' line='2028' column='1'/>
+          <var-decl name='' type-id='38feef9e' visibility='default' filepath='include/linux/netdevice.h' line='2027' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9728'>
-          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/linux/netdevice.h' line='2043' column='1'/>
+          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/linux/netdevice.h' line='2042' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17344'>
-          <var-decl name='sysfs_groups' type-id='db1b7234' visibility='default' filepath='include/linux/netdevice.h' line='2044' column='1'/>
+          <var-decl name='sysfs_groups' type-id='db1b7234' visibility='default' filepath='include/linux/netdevice.h' line='2043' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17600'>
-          <var-decl name='sysfs_rx_queue_group' type-id='8ff9530e' visibility='default' filepath='include/linux/netdevice.h' line='2045' column='1'/>
+          <var-decl name='sysfs_rx_queue_group' type-id='8ff9530e' visibility='default' filepath='include/linux/netdevice.h' line='2044' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17664'>
-          <var-decl name='rtnl_link_ops' type-id='999c8d90' visibility='default' filepath='include/linux/netdevice.h' line='2047' column='1'/>
+          <var-decl name='rtnl_link_ops' type-id='999c8d90' visibility='default' filepath='include/linux/netdevice.h' line='2046' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17728'>
-          <var-decl name='gso_max_size' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='2051' column='1'/>
+          <var-decl name='gso_max_size' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='2050' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17760'>
-          <var-decl name='gso_max_segs' type-id='1dc6a898' visibility='default' filepath='include/linux/netdevice.h' line='2053' column='1'/>
+          <var-decl name='gso_max_segs' type-id='1dc6a898' visibility='default' filepath='include/linux/netdevice.h' line='2052' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17776'>
-          <var-decl name='num_tc' type-id='9b7e9486' visibility='default' filepath='include/linux/netdevice.h' line='2058' column='1'/>
+          <var-decl name='num_tc' type-id='9b7e9486' visibility='default' filepath='include/linux/netdevice.h' line='2057' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17792'>
-          <var-decl name='tc_to_txq' type-id='b5839634' visibility='default' filepath='include/linux/netdevice.h' line='2059' column='1'/>
+          <var-decl name='tc_to_txq' type-id='b5839634' visibility='default' filepath='include/linux/netdevice.h' line='2058' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18304'>
-          <var-decl name='prio_tc_map' type-id='0d8415b5' visibility='default' filepath='include/linux/netdevice.h' line='2060' column='1'/>
+          <var-decl name='prio_tc_map' type-id='0d8415b5' visibility='default' filepath='include/linux/netdevice.h' line='2059' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18432'>
-          <var-decl name='phydev' type-id='7efbcaaf' visibility='default' filepath='include/linux/netdevice.h' line='2068' column='1'/>
+          <var-decl name='phydev' type-id='7efbcaaf' visibility='default' filepath='include/linux/netdevice.h' line='2067' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18496'>
-          <var-decl name='sfp_bus' type-id='6daf6abd' visibility='default' filepath='include/linux/netdevice.h' line='2069' column='1'/>
+          <var-decl name='sfp_bus' type-id='6daf6abd' visibility='default' filepath='include/linux/netdevice.h' line='2068' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18560'>
-          <var-decl name='qdisc_tx_busylock' type-id='a57283f9' visibility='default' filepath='include/linux/netdevice.h' line='2070' column='1'/>
+          <var-decl name='qdisc_tx_busylock' type-id='a57283f9' visibility='default' filepath='include/linux/netdevice.h' line='2069' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18624'>
-          <var-decl name='qdisc_running_key' type-id='a57283f9' visibility='default' filepath='include/linux/netdevice.h' line='2071' column='1'/>
+          <var-decl name='qdisc_running_key' type-id='a57283f9' visibility='default' filepath='include/linux/netdevice.h' line='2070' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18688'>
-          <var-decl name='proto_down' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='2072' column='1'/>
+          <var-decl name='proto_down' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='2071' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8'>
-          <var-decl name='wol_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='2073' column='1'/>
+          <var-decl name='wol_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='2072' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18752'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2075' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2074' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18816'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2076' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2075' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18880'>
-          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2077' column='1'/>
+          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2076' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18944'>
-          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2078' column='1'/>
+          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2077' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19008'>
-          <var-decl name='android_kabi_reserved5' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2079' column='1'/>
+          <var-decl name='android_kabi_reserved5' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2078' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19072'>
-          <var-decl name='android_kabi_reserved6' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2080' column='1'/>
+          <var-decl name='android_kabi_reserved6' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2079' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19136'>
-          <var-decl name='android_kabi_reserved7' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2081' column='1'/>
+          <var-decl name='android_kabi_reserved7' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2080' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19200'>
-          <var-decl name='android_kabi_reserved8' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2082' column='1'/>
+          <var-decl name='android_kabi_reserved8' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2081' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='net_generic' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/netns/generic.h' line='28' column='1' id='8e5f5512'>
@@ -18655,39 +18658,39 @@
           <var-decl name='sctp' type-id='c91839d0' visibility='default' filepath='include/net/netns/conntrack.h' line='83' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='perf_cpu_context' size-in-bits='3136' is-struct='yes' visibility='default' filepath='include/linux/perf_event.h' line='797' column='1' id='4448fdd3'>
+      <class-decl name='perf_cpu_context' size-in-bits='3136' is-struct='yes' visibility='default' filepath='include/linux/perf_event.h' line='800' column='1' id='4448fdd3'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='ctx' type-id='9d67acd5' visibility='default' filepath='include/linux/perf_event.h' line='798' column='1'/>
+          <var-decl name='ctx' type-id='9d67acd5' visibility='default' filepath='include/linux/perf_event.h' line='801' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='task_ctx' type-id='b9419dc5' visibility='default' filepath='include/linux/perf_event.h' line='799' column='1'/>
+          <var-decl name='task_ctx' type-id='b9419dc5' visibility='default' filepath='include/linux/perf_event.h' line='802' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='active_oncpu' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='800' column='1'/>
+          <var-decl name='active_oncpu' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='803' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2144'>
-          <var-decl name='exclusive' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='801' column='1'/>
+          <var-decl name='exclusive' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='804' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2176'>
-          <var-decl name='hrtimer_lock' type-id='f5c90b3f' visibility='default' filepath='include/linux/perf_event.h' line='803' column='1'/>
+          <var-decl name='hrtimer_lock' type-id='f5c90b3f' visibility='default' filepath='include/linux/perf_event.h' line='806' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2240'>
-          <var-decl name='hrtimer' type-id='b6993efc' visibility='default' filepath='include/linux/perf_event.h' line='804' column='1'/>
+          <var-decl name='hrtimer' type-id='b6993efc' visibility='default' filepath='include/linux/perf_event.h' line='807' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2816'>
-          <var-decl name='hrtimer_interval' type-id='fbc017ef' visibility='default' filepath='include/linux/perf_event.h' line='805' column='1'/>
+          <var-decl name='hrtimer_interval' type-id='fbc017ef' visibility='default' filepath='include/linux/perf_event.h' line='808' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2880'>
-          <var-decl name='hrtimer_active' type-id='f0981eeb' visibility='default' filepath='include/linux/perf_event.h' line='806' column='1'/>
+          <var-decl name='hrtimer_active' type-id='f0981eeb' visibility='default' filepath='include/linux/perf_event.h' line='809' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2944'>
-          <var-decl name='sched_cb_entry' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='813' column='1'/>
+          <var-decl name='sched_cb_entry' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='816' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3072'>
-          <var-decl name='sched_cb_usage' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='814' column='1'/>
+          <var-decl name='sched_cb_usage' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='817' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3104'>
-          <var-decl name='online' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='816' column='1'/>
+          <var-decl name='online' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='819' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='perf_event_mmap_page' size-in-bits='8704' is-struct='yes' visibility='default' filepath='include/uapi/linux/perf_event.h' line='473' column='1' id='a752caf1'>
@@ -21032,18 +21035,18 @@
           <var-decl name='search_restart' type-id='f0981eeb' visibility='default' filepath='include/linux/netfilter/nf_conntrack_common.h' line='19' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='ip_ra_chain' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/ip.h' line='123' column='1' id='4816a146'>
+      <class-decl name='ip_ra_chain' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/ip.h' line='125' column='1' id='4816a146'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='next' type-id='00c4cbac' visibility='default' filepath='include/net/ip.h' line='124' column='1'/>
+          <var-decl name='next' type-id='00c4cbac' visibility='default' filepath='include/net/ip.h' line='126' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='sk' type-id='f772df6d' visibility='default' filepath='include/net/ip.h' line='125' column='1'/>
+          <var-decl name='sk' type-id='f772df6d' visibility='default' filepath='include/net/ip.h' line='127' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='' type-id='4fa91678' visibility='default' filepath='include/net/ip.h' line='126' column='1'/>
+          <var-decl name='' type-id='4fa91678' visibility='default' filepath='include/net/ip.h' line='128' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/net/ip.h' line='130' column='1'/>
+          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/net/ip.h' line='132' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='ipstats_mib' size-in-bits='2368' is-struct='yes' visibility='default' filepath='include/net/snmp.h' line='56' column='1' id='f52a1ce8'>
@@ -21756,21 +21759,21 @@
           <var-decl name='times_prev' type-id='4e00dfcd' visibility='default' filepath='include/linux/psi_types.h' line='77' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='quota_info' size-in-bits='2560' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='527' column='1' id='c26e4ad8'>
+      <class-decl name='quota_info' size-in-bits='2560' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='529' column='1' id='c26e4ad8'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='flags' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='528' column='1'/>
+          <var-decl name='flags' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='530' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='dqio_sem' type-id='f19fdb93' visibility='default' filepath='include/linux/quota.h' line='529' column='1'/>
+          <var-decl name='dqio_sem' type-id='f19fdb93' visibility='default' filepath='include/linux/quota.h' line='531' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='files' type-id='e6ff92fb' visibility='default' filepath='include/linux/quota.h' line='530' column='1'/>
+          <var-decl name='files' type-id='e6ff92fb' visibility='default' filepath='include/linux/quota.h' line='532' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='info' type-id='83ae09a1' visibility='default' filepath='include/linux/quota.h' line='531' column='1'/>
+          <var-decl name='info' type-id='83ae09a1' visibility='default' filepath='include/linux/quota.h' line='533' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2368'>
-          <var-decl name='ops' type-id='59bd9302' visibility='default' filepath='include/linux/quota.h' line='532' column='1'/>
+          <var-decl name='ops' type-id='59bd9302' visibility='default' filepath='include/linux/quota.h' line='534' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='raw_hashinfo' is-struct='yes' visibility='default' is-declaration-only='yes' id='51ee3086'/>
@@ -22007,15 +22010,15 @@
           <var-decl name='function' type-id='ca9b3bbf' visibility='default' filepath='include/linux/interrupt.h' line='629' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='tcp_fastopen_context' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/tcp.h' line='1634' column='1' id='f77d4717'>
+      <class-decl name='tcp_fastopen_context' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/tcp.h' line='1639' column='1' id='f77d4717'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='tfm' type-id='75f72758' visibility='default' filepath='include/net/tcp.h' line='1635' column='1'/>
+          <var-decl name='tfm' type-id='75f72758' visibility='default' filepath='include/net/tcp.h' line='1640' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='key' type-id='9396cabb' visibility='default' filepath='include/net/tcp.h' line='1636' column='1'/>
+          <var-decl name='key' type-id='9396cabb' visibility='default' filepath='include/net/tcp.h' line='1641' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/net/tcp.h' line='1637' column='1'/>
+          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/net/tcp.h' line='1642' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='tcp_mib' size-in-bits='1024' is-struct='yes' visibility='default' filepath='include/net/snmp.h' line='97' column='1' id='e1f906a3'>
@@ -22184,18 +22187,18 @@
           <var-decl name='entry' type-id='72f469ec' visibility='default' filepath='include/linux/wait.h' line='32' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wake_irq' size-in-bits='192' is-struct='yes' visibility='default' filepath='drivers/base/power/power.h' line='30' column='1' id='4657336c'>
+      <class-decl name='wake_irq' size-in-bits='192' is-struct='yes' visibility='default' filepath='drivers/base/power/power.h' line='33' column='1' id='4657336c'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='dev' type-id='fa0b179b' visibility='default' filepath='drivers/base/power/power.h' line='31' column='1'/>
+          <var-decl name='dev' type-id='fa0b179b' visibility='default' filepath='drivers/base/power/power.h' line='34' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='status' type-id='f0981eeb' visibility='default' filepath='drivers/base/power/power.h' line='32' column='1'/>
+          <var-decl name='status' type-id='f0981eeb' visibility='default' filepath='drivers/base/power/power.h' line='35' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='irq' type-id='95e97e5e' visibility='default' filepath='drivers/base/power/power.h' line='33' column='1'/>
+          <var-decl name='irq' type-id='95e97e5e' visibility='default' filepath='drivers/base/power/power.h' line='36' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='name' type-id='80f4b756' visibility='default' filepath='drivers/base/power/power.h' line='34' column='1'/>
+          <var-decl name='name' type-id='80f4b756' visibility='default' filepath='drivers/base/power/power.h' line='37' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='wakeup_source' size-in-bits='1664' is-struct='yes' visibility='default' filepath='include/linux/pm_wakeup.h' line='56' column='1' id='152cd1b0'>
@@ -22304,23 +22307,23 @@
           <var-decl name='last_func' type-id='72666d3f' visibility='default' filepath='kernel/workqueue_internal.h' line='58' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='workqueue_attrs' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='143' column='1' id='2fe6f208'>
+      <class-decl name='workqueue_attrs' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='144' column='1' id='2fe6f208'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='nice' type-id='95e97e5e' visibility='default' filepath='include/linux/workqueue.h' line='147' column='1'/>
+          <var-decl name='nice' type-id='95e97e5e' visibility='default' filepath='include/linux/workqueue.h' line='148' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='cpumask' type-id='b16b461b' visibility='default' filepath='include/linux/workqueue.h' line='152' column='1'/>
+          <var-decl name='cpumask' type-id='b16b461b' visibility='default' filepath='include/linux/workqueue.h' line='153' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='no_numa' type-id='b50a4934' visibility='default' filepath='include/linux/workqueue.h' line='161' column='1'/>
+          <var-decl name='no_numa' type-id='b50a4934' visibility='default' filepath='include/linux/workqueue.h' line='162' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wq_device' size-in-bits='7680' is-struct='yes' visibility='default' filepath='kernel/workqueue.c' line='5203' column='1' id='a88ecfc8'>
+      <class-decl name='wq_device' size-in-bits='7680' is-struct='yes' visibility='default' filepath='kernel/workqueue.c' line='5210' column='1' id='a88ecfc8'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='wq' type-id='242e3d19' visibility='default' filepath='kernel/workqueue.c' line='5204' column='1'/>
+          <var-decl name='wq' type-id='242e3d19' visibility='default' filepath='kernel/workqueue.c' line='5211' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='kernel/workqueue.c' line='5205' column='1'/>
+          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='kernel/workqueue.c' line='5212' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='wq_flusher' size-in-bits='448' is-struct='yes' visibility='default' filepath='kernel/workqueue.c' line='226' column='1' id='c8eb0f4f'>
@@ -22515,12 +22518,12 @@
           <var-decl name='csum_offset' type-id='d315442e' visibility='default' filepath='include/linux/skbuff.h' line='808' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='__anonymous_struct__' size-in-bits='256' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='1814' column='1' id='19245258'>
+      <class-decl name='__anonymous_struct__' size-in-bits='256' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='1816' column='1' id='19245258'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='upper' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1815' column='1'/>
+          <var-decl name='upper' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1817' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='lower' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1816' column='1'/>
+          <var-decl name='lower' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1818' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='__anonymous_struct__4' size-in-bits='768' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/slab.h' line='641' column='1' id='26b3aff0'>
@@ -22688,7 +22691,7 @@
       <pointer-type-def type-id='c21690c0' size-in-bits='64' id='3ce3447a'/>
       <pointer-type-def type-id='7f4a5e53' size-in-bits='64' id='d7c38177'/>
       <pointer-type-def type-id='aaa166ff' size-in-bits='64' id='177a4437'/>
-      <enum-decl name='__anonymous_enum__2' is-anonymous='yes' filepath='include/linux/netdevice.h' line='2003' column='1' id='08f5ca18'>
+      <enum-decl name='__anonymous_enum__2' is-anonymous='yes' filepath='include/linux/netdevice.h' line='2002' column='1' id='08f5ca18'>
         <underlying-type type-id='9cac1fee'/>
         <enumerator name='NETREG_UNINITIALIZED' value='0'/>
         <enumerator name='NETREG_REGISTERED' value='1'/>
@@ -22697,7 +22700,7 @@
         <enumerator name='NETREG_RELEASED' value='4'/>
         <enumerator name='NETREG_DUMMY' value='5'/>
       </enum-decl>
-      <enum-decl name='__anonymous_enum__3' is-anonymous='yes' filepath='include/linux/netdevice.h' line='2013' column='1' id='08f5ca19'>
+      <enum-decl name='__anonymous_enum__3' is-anonymous='yes' filepath='include/linux/netdevice.h' line='2012' column='1' id='08f5ca19'>
         <underlying-type type-id='9cac1fee'/>
         <enumerator name='RTNL_LINK_INITIALIZED' value='0'/>
         <enumerator name='RTNL_LINK_INITIALIZING' value='1'/>
@@ -22875,21 +22878,21 @@
           <var-decl name='bydst' type-id='03a4a074' visibility='default' filepath='include/net/xfrm.h' line='140' column='1'/>
         </data-member>
       </union-decl>
-      <union-decl name='__anonymous_union__36' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='2028' column='1' id='38feef9e'>
+      <union-decl name='__anonymous_union__36' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='2027' column='1' id='38feef9e'>
         <data-member access='public'>
-          <var-decl name='ml_priv' type-id='eaa32e2f' visibility='default' filepath='include/linux/netdevice.h' line='2029' column='1'/>
+          <var-decl name='ml_priv' type-id='eaa32e2f' visibility='default' filepath='include/linux/netdevice.h' line='2028' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='lstats' type-id='a42934eb' visibility='default' filepath='include/linux/netdevice.h' line='2030' column='1'/>
+          <var-decl name='lstats' type-id='a42934eb' visibility='default' filepath='include/linux/netdevice.h' line='2029' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='tstats' type-id='90cd86e5' visibility='default' filepath='include/linux/netdevice.h' line='2031' column='1'/>
+          <var-decl name='tstats' type-id='90cd86e5' visibility='default' filepath='include/linux/netdevice.h' line='2030' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='dstats' type-id='f59f5033' visibility='default' filepath='include/linux/netdevice.h' line='2032' column='1'/>
+          <var-decl name='dstats' type-id='f59f5033' visibility='default' filepath='include/linux/netdevice.h' line='2031' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='vstats' type-id='1200d79d' visibility='default' filepath='include/linux/netdevice.h' line='2033' column='1'/>
+          <var-decl name='vstats' type-id='1200d79d' visibility='default' filepath='include/linux/netdevice.h' line='2032' column='1'/>
         </data-member>
       </union-decl>
       <union-decl name='__anonymous_union__24' size-in-bits='384' is-anonymous='yes' visibility='default' filepath='include/linux/bpf.h' line='298' column='1' id='b597c0fa'>
@@ -23165,7 +23168,23 @@
           <var-decl name='jited_len' type-id='19c2251e' visibility='default' filepath='include/linux/bpf.h' line='272' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cpu_rmap' is-struct='yes' visibility='default' is-declaration-only='yes' id='e09a048e'/>
+      <class-decl name='cpu_rmap' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/linux/cpu_rmap.h' line='27' column='1' id='e09a048e'>
+        <data-member access='public' layout-offset-in-bits='0'>
+          <var-decl name='refcount' type-id='400fb07b' visibility='default' filepath='include/linux/cpu_rmap.h' line='28' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='32'>
+          <var-decl name='size' type-id='1dc6a898' visibility='default' filepath='include/linux/cpu_rmap.h' line='29' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='48'>
+          <var-decl name='used' type-id='1dc6a898' visibility='default' filepath='include/linux/cpu_rmap.h' line='29' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='64'>
+          <var-decl name='obj' type-id='63e171df' visibility='default' filepath='include/linux/cpu_rmap.h' line='30' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='128'>
+          <var-decl name='near' type-id='f443352a' visibility='default' filepath='include/linux/cpu_rmap.h' line='34' column='1'/>
+        </data-member>
+      </class-decl>
       <class-decl name='ctl_table_poll' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/sysctl.h' line='95' column='1' id='d39c42ab'>
         <data-member access='public' layout-offset-in-bits='0'>
           <var-decl name='event' type-id='49178f86' visibility='default' filepath='include/linux/sysctl.h' line='96' column='1'/>
@@ -23174,12 +23193,12 @@
           <var-decl name='wait' type-id='b5ab048f' visibility='default' filepath='include/linux/sysctl.h' line='97' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='dev_ifalias' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='946' column='1' id='ddd212e6'>
+      <class-decl name='dev_ifalias' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='949' column='1' id='ddd212e6'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='rcuhead' type-id='e3d8ce29' visibility='default' filepath='include/linux/netdevice.h' line='947' column='1'/>
+          <var-decl name='rcuhead' type-id='e3d8ce29' visibility='default' filepath='include/linux/netdevice.h' line='950' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='ifalias' type-id='e84913bd' visibility='default' filepath='include/linux/netdevice.h' line='948' column='1'/>
+          <var-decl name='ifalias' type-id='e84913bd' visibility='default' filepath='include/linux/netdevice.h' line='951' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='disk_events' size-in-bits='1792' is-struct='yes' visibility='default' filepath='block/genhd.c' line='1595' column='1' id='ec1aac50'>
@@ -23871,41 +23890,41 @@
           <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='616' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='netdev_rx_queue' size-in-bits='2048' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='723' column='1' id='f12ac4ae'>
+      <class-decl name='netdev_rx_queue' size-in-bits='2048' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='726' column='1' id='f12ac4ae'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='rps_map' type-id='f30dbff5' visibility='default' filepath='include/linux/netdevice.h' line='725' column='1'/>
+          <var-decl name='rps_map' type-id='f30dbff5' visibility='default' filepath='include/linux/netdevice.h' line='728' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='rps_flow_table' type-id='deff2378' visibility='default' filepath='include/linux/netdevice.h' line='726' column='1'/>
+          <var-decl name='rps_flow_table' type-id='deff2378' visibility='default' filepath='include/linux/netdevice.h' line='729' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='kobj' type-id='b6ab8849' visibility='default' filepath='include/linux/netdevice.h' line='728' column='1'/>
+          <var-decl name='kobj' type-id='b6ab8849' visibility='default' filepath='include/linux/netdevice.h' line='731' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='dev' type-id='68a2d05b' visibility='default' filepath='include/linux/netdevice.h' line='729' column='1'/>
+          <var-decl name='dev' type-id='68a2d05b' visibility='default' filepath='include/linux/netdevice.h' line='732' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='xdp_rxq' type-id='eb0d6f26' visibility='default' filepath='include/linux/netdevice.h' line='730' column='1'/>
+          <var-decl name='xdp_rxq' type-id='eb0d6f26' visibility='default' filepath='include/linux/netdevice.h' line='733' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='732' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='735' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1600'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='733' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='736' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1664'>
-          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='734' column='1'/>
+          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='737' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1728'>
-          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='735' column='1'/>
+          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='738' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='netdev_tc_txq' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='782' column='1' id='f1e1eb79'>
+      <class-decl name='netdev_tc_txq' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='785' column='1' id='f1e1eb79'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='count' type-id='1dc6a898' visibility='default' filepath='include/linux/netdevice.h' line='783' column='1'/>
+          <var-decl name='count' type-id='1dc6a898' visibility='default' filepath='include/linux/netdevice.h' line='786' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='offset' type-id='1dc6a898' visibility='default' filepath='include/linux/netdevice.h' line='784' column='1'/>
+          <var-decl name='offset' type-id='1dc6a898' visibility='default' filepath='include/linux/netdevice.h' line='787' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='nf_hook_entries' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/linux/netfilter.h' line='85' column='1' id='85c08b52'>
@@ -24368,60 +24387,60 @@
           <var-decl name='data' type-id='7359adad' visibility='default' filepath='include/linux/interrupt.h' line='548' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='tcp_congestion_ops' size-in-bits='1216' is-struct='yes' visibility='default' filepath='include/net/tcp.h' line='1018' column='1' id='54718f09'>
+      <class-decl name='tcp_congestion_ops' size-in-bits='1216' is-struct='yes' visibility='default' filepath='include/net/tcp.h' line='1023' column='1' id='54718f09'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/net/tcp.h' line='1019' column='1'/>
+          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/net/tcp.h' line='1024' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='key' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1020' column='1'/>
+          <var-decl name='key' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1025' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1021' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1026' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='init' type-id='841969d0' visibility='default' filepath='include/net/tcp.h' line='1024' column='1'/>
+          <var-decl name='init' type-id='841969d0' visibility='default' filepath='include/net/tcp.h' line='1029' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='release' type-id='841969d0' visibility='default' filepath='include/net/tcp.h' line='1026' column='1'/>
+          <var-decl name='release' type-id='841969d0' visibility='default' filepath='include/net/tcp.h' line='1031' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='ssthresh' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1029' column='1'/>
+          <var-decl name='ssthresh' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1034' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='cong_avoid' type-id='ece3af1e' visibility='default' filepath='include/net/tcp.h' line='1031' column='1'/>
+          <var-decl name='cong_avoid' type-id='ece3af1e' visibility='default' filepath='include/net/tcp.h' line='1036' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='set_state' type-id='f5feb7a4' visibility='default' filepath='include/net/tcp.h' line='1033' column='1'/>
+          <var-decl name='set_state' type-id='f5feb7a4' visibility='default' filepath='include/net/tcp.h' line='1038' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='cwnd_event' type-id='bfacbc7a' visibility='default' filepath='include/net/tcp.h' line='1035' column='1'/>
+          <var-decl name='cwnd_event' type-id='bfacbc7a' visibility='default' filepath='include/net/tcp.h' line='1040' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='in_ack_event' type-id='815f64bf' visibility='default' filepath='include/net/tcp.h' line='1037' column='1'/>
+          <var-decl name='in_ack_event' type-id='815f64bf' visibility='default' filepath='include/net/tcp.h' line='1042' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='undo_cwnd' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1039' column='1'/>
+          <var-decl name='undo_cwnd' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1044' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='pkts_acked' type-id='bffb5883' visibility='default' filepath='include/net/tcp.h' line='1041' column='1'/>
+          <var-decl name='pkts_acked' type-id='bffb5883' visibility='default' filepath='include/net/tcp.h' line='1046' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='min_tso_segs' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1043' column='1'/>
+          <var-decl name='min_tso_segs' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1048' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='sndbuf_expand' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1045' column='1'/>
+          <var-decl name='sndbuf_expand' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1050' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='cong_control' type-id='636d3a20' visibility='default' filepath='include/net/tcp.h' line='1049' column='1'/>
+          <var-decl name='cong_control' type-id='636d3a20' visibility='default' filepath='include/net/tcp.h' line='1054' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='get_info' type-id='14ca5c08' visibility='default' filepath='include/net/tcp.h' line='1051' column='1'/>
+          <var-decl name='get_info' type-id='14ca5c08' visibility='default' filepath='include/net/tcp.h' line='1056' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='name' type-id='ac1fa8c0' visibility='default' filepath='include/net/tcp.h' line='1054' column='1'/>
+          <var-decl name='name' type-id='ac1fa8c0' visibility='default' filepath='include/net/tcp.h' line='1059' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='owner' type-id='2730d015' visibility='default' filepath='include/net/tcp.h' line='1055' column='1'/>
+          <var-decl name='owner' type-id='2730d015' visibility='default' filepath='include/net/tcp.h' line='1060' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='timer_rand_state' is-struct='yes' visibility='default' is-declaration-only='yes' id='f308a7ce'/>
@@ -24512,120 +24531,120 @@
         </data-member>
       </class-decl>
       <class-decl name='unicode_map' is-struct='yes' visibility='default' is-declaration-only='yes' id='a24978a1'/>
-      <class-decl name='wireless_dev' size-in-bits='3008' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='4500' column='1' id='3ce3a3e9'>
+      <class-decl name='wireless_dev' size-in-bits='3008' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='4503' column='1' id='3ce3a3e9'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='wiphy' type-id='666fb412' visibility='default' filepath='include/net/cfg80211.h' line='4501' column='1'/>
+          <var-decl name='wiphy' type-id='666fb412' visibility='default' filepath='include/net/cfg80211.h' line='4504' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='iftype' type-id='86505f90' visibility='default' filepath='include/net/cfg80211.h' line='4502' column='1'/>
+          <var-decl name='iftype' type-id='86505f90' visibility='default' filepath='include/net/cfg80211.h' line='4505' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4505' column='1'/>
+          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4508' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='netdev' type-id='68a2d05b' visibility='default' filepath='include/net/cfg80211.h' line='4506' column='1'/>
+          <var-decl name='netdev' type-id='68a2d05b' visibility='default' filepath='include/net/cfg80211.h' line='4509' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='identifier' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4508' column='1'/>
+          <var-decl name='identifier' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4511' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='mgmt_registrations' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4510' column='1'/>
+          <var-decl name='mgmt_registrations' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4513' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='mgmt_registrations_lock' type-id='fb4018a0' visibility='default' filepath='include/net/cfg80211.h' line='4511' column='1'/>
+          <var-decl name='mgmt_registrations_lock' type-id='fb4018a0' visibility='default' filepath='include/net/cfg80211.h' line='4514' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='mtx' type-id='925167dc' visibility='default' filepath='include/net/cfg80211.h' line='4513' column='1'/>
+          <var-decl name='mtx' type-id='925167dc' visibility='default' filepath='include/net/cfg80211.h' line='4516' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='use_4addr' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4515' column='1'/>
+          <var-decl name='use_4addr' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4518' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='840'>
-          <var-decl name='is_running' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4515' column='1'/>
+          <var-decl name='is_running' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4518' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='848'>
-          <var-decl name='address' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4517' column='1'/>
+          <var-decl name='address' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4520' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='ssid' type-id='e3dc4fdb' visibility='default' filepath='include/net/cfg80211.h' line='4520' column='1'/>
+          <var-decl name='ssid' type-id='e3dc4fdb' visibility='default' filepath='include/net/cfg80211.h' line='4523' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='ssid_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4521' column='1'/>
+          <var-decl name='ssid_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4524' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1160'>
-          <var-decl name='mesh_id_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4521' column='1'/>
+          <var-decl name='mesh_id_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4524' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1168'>
-          <var-decl name='mesh_id_up_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4521' column='1'/>
+          <var-decl name='mesh_id_up_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4524' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='conn' type-id='6dbc8e18' visibility='default' filepath='include/net/cfg80211.h' line='4522' column='1'/>
+          <var-decl name='conn' type-id='6dbc8e18' visibility='default' filepath='include/net/cfg80211.h' line='4525' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='connect_keys' type-id='561a36db' visibility='default' filepath='include/net/cfg80211.h' line='4523' column='1'/>
+          <var-decl name='connect_keys' type-id='561a36db' visibility='default' filepath='include/net/cfg80211.h' line='4526' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='conn_bss_type' type-id='cb952348' visibility='default' filepath='include/net/cfg80211.h' line='4524' column='1'/>
+          <var-decl name='conn_bss_type' type-id='cb952348' visibility='default' filepath='include/net/cfg80211.h' line='4527' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1376'>
-          <var-decl name='conn_owner_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4525' column='1'/>
+          <var-decl name='conn_owner_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4528' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='disconnect_wk' type-id='ef9025d0' visibility='default' filepath='include/net/cfg80211.h' line='4527' column='1'/>
+          <var-decl name='disconnect_wk' type-id='ef9025d0' visibility='default' filepath='include/net/cfg80211.h' line='4530' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1792'>
-          <var-decl name='disconnect_bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4528' column='1'/>
+          <var-decl name='disconnect_bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4531' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='event_list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4530' column='1'/>
+          <var-decl name='event_list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4533' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1984'>
-          <var-decl name='event_lock' type-id='fb4018a0' visibility='default' filepath='include/net/cfg80211.h' line='4531' column='1'/>
+          <var-decl name='event_lock' type-id='fb4018a0' visibility='default' filepath='include/net/cfg80211.h' line='4534' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='current_bss' type-id='1819dec8' visibility='default' filepath='include/net/cfg80211.h' line='4533' column='1'/>
+          <var-decl name='current_bss' type-id='1819dec8' visibility='default' filepath='include/net/cfg80211.h' line='4536' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='preset_chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='4534' column='1'/>
+          <var-decl name='preset_chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='4537' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2368'>
-          <var-decl name='chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='4535' column='1'/>
+          <var-decl name='chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='4538' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2624'>
-          <var-decl name='ibss_fixed' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4537' column='1'/>
+          <var-decl name='ibss_fixed' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4540' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2632'>
-          <var-decl name='ibss_dfs_possible' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4538' column='1'/>
+          <var-decl name='ibss_dfs_possible' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4541' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2640'>
-          <var-decl name='ps' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4540' column='1'/>
+          <var-decl name='ps' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4543' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2656'>
-          <var-decl name='ps_timeout' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4541' column='1'/>
+          <var-decl name='ps_timeout' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4544' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2688'>
-          <var-decl name='beacon_interval' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4543' column='1'/>
+          <var-decl name='beacon_interval' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4546' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2720'>
-          <var-decl name='ap_unexpected_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4545' column='1'/>
+          <var-decl name='ap_unexpected_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4548' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2752'>
-          <var-decl name='owner_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4547' column='1'/>
+          <var-decl name='owner_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4550' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2784'>
-          <var-decl name='nl_owner_dead' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4548' column='1'/>
+          <var-decl name='nl_owner_dead' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4551' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2792'>
-          <var-decl name='cac_started' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4550' column='1'/>
+          <var-decl name='cac_started' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4553' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2816'>
-          <var-decl name='cac_start_time' type-id='7359adad' visibility='default' filepath='include/net/cfg80211.h' line='4551' column='1'/>
+          <var-decl name='cac_start_time' type-id='7359adad' visibility='default' filepath='include/net/cfg80211.h' line='4554' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2880'>
-          <var-decl name='cac_time_ms' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='4552' column='1'/>
+          <var-decl name='cac_time_ms' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='4555' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2944'>
-          <var-decl name='cqm_config' type-id='ee527710' visibility='default' filepath='include/net/cfg80211.h' line='4569' column='1'/>
+          <var-decl name='cqm_config' type-id='ee527710' visibility='default' filepath='include/net/cfg80211.h' line='4572' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='wpan_dev' is-struct='yes' visibility='default' is-declaration-only='yes' id='8ae2fb1d'/>
@@ -24737,12 +24756,12 @@
           <var-decl name='bmp' type-id='d5016f6f' visibility='default' filepath='include/uapi/linux/xfrm.h' line='99' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='xps_dev_maps' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='766' column='1' id='4edc4180'>
+      <class-decl name='xps_dev_maps' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='769' column='1' id='4edc4180'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/linux/netdevice.h' line='767' column='1'/>
+          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/linux/netdevice.h' line='770' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='attr_map' type-id='a0955e2b' visibility='default' filepath='include/linux/netdevice.h' line='768' column='1'/>
+          <var-decl name='attr_map' type-id='a0955e2b' visibility='default' filepath='include/linux/netdevice.h' line='771' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='__anonymous_struct__' size-in-bits='64' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/uapi/linux/perf_event.h' line='519' column='1' id='7179013d'>
@@ -25056,12 +25075,12 @@
           <var-decl name='' type-id='2a125a28' visibility='default' filepath='include/linux/dcache.h' line='154' column='1'/>
         </data-member>
       </union-decl>
-      <union-decl name='__anonymous_union__33' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/net/ip.h' line='126' column='1' id='4fa91678'>
+      <union-decl name='__anonymous_union__33' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/net/ip.h' line='128' column='1' id='4fa91678'>
         <data-member access='public'>
-          <var-decl name='destructor' type-id='841969d0' visibility='default' filepath='include/net/ip.h' line='127' column='1'/>
+          <var-decl name='destructor' type-id='841969d0' visibility='default' filepath='include/net/ip.h' line='129' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='saved_sk' type-id='f772df6d' visibility='default' filepath='include/net/ip.h' line='128' column='1'/>
+          <var-decl name='saved_sk' type-id='f772df6d' visibility='default' filepath='include/net/ip.h' line='130' column='1'/>
         </data-member>
       </union-decl>
       <pointer-type-def type-id='02138eb3' size-in-bits='64' id='3a0c781f'/>
@@ -25125,6 +25144,9 @@
         <subrange length='6' type-id='7ff19f0f' id='52fa524b'/>
       </array-type-def>
       <pointer-type-def type-id='68a72cd7' size-in-bits='64' id='b6316a7f'/>
+      <array-type-def dimensions='1' type-id='bb08c7e1' size-in-bits='infinite' id='f443352a'>
+        <subrange length='infinite' type-id='7ff19f0f' id='031f2035'/>
+      </array-type-def>
       <pointer-type-def type-id='708c2394' size-in-bits='64' id='282b7312'/>
       <pointer-type-def type-id='0ad68707' size-in-bits='64' id='b6a33eaf'/>
       <pointer-type-def type-id='0ef5c7e0' size-in-bits='64' id='b1253746'/>
@@ -25245,21 +25267,21 @@
           <var-decl name='buckets' type-id='bde3078a' visibility='default' filepath='include/linux/rhashtable.h' line='75' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_chan_def' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='568' column='1' id='e07d69c8'>
+      <class-decl name='cfg80211_chan_def' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='571' column='1' id='e07d69c8'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='chan' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='569' column='1'/>
+          <var-decl name='chan' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='572' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='width' type-id='e043cccc' visibility='default' filepath='include/net/cfg80211.h' line='570' column='1'/>
+          <var-decl name='width' type-id='e043cccc' visibility='default' filepath='include/net/cfg80211.h' line='573' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='center_freq1' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='571' column='1'/>
+          <var-decl name='center_freq1' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='574' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='center_freq2' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='572' column='1'/>
+          <var-decl name='center_freq2' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='575' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='edmg' type-id='d87e6929' visibility='default' filepath='include/net/cfg80211.h' line='573' column='1'/>
+          <var-decl name='edmg' type-id='d87e6929' visibility='default' filepath='include/net/cfg80211.h' line='576' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='crypto_cipher' size-in-bits='1024' is-struct='yes' visibility='default' filepath='include/linux/crypto.h' line='619' column='1' id='5e09ca8a'>
@@ -25366,45 +25388,45 @@
           <var-decl name='slack_hold_time' type-id='f0981eeb' visibility='default' filepath='include/linux/dynamic_queue_limits.h' line='62' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='dquot_operations' size-in-bits='832' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='325' column='1' id='0584e65d'>
+      <class-decl name='dquot_operations' size-in-bits='832' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='327' column='1' id='0584e65d'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='write_dquot' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='326' column='1'/>
+          <var-decl name='write_dquot' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='328' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='alloc_dquot' type-id='324070f9' visibility='default' filepath='include/linux/quota.h' line='327' column='1'/>
+          <var-decl name='alloc_dquot' type-id='324070f9' visibility='default' filepath='include/linux/quota.h' line='329' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='destroy_dquot' type-id='dbc22931' visibility='default' filepath='include/linux/quota.h' line='328' column='1'/>
+          <var-decl name='destroy_dquot' type-id='dbc22931' visibility='default' filepath='include/linux/quota.h' line='330' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='acquire_dquot' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='329' column='1'/>
+          <var-decl name='acquire_dquot' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='331' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='release_dquot' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='330' column='1'/>
+          <var-decl name='release_dquot' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='332' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='mark_dirty' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='331' column='1'/>
+          <var-decl name='mark_dirty' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='333' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='write_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='332' column='1'/>
+          <var-decl name='write_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='334' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='get_reserved_space' type-id='15543b10' visibility='default' filepath='include/linux/quota.h' line='335' column='1'/>
+          <var-decl name='get_reserved_space' type-id='15543b10' visibility='default' filepath='include/linux/quota.h' line='337' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='get_projid' type-id='c23b3cbc' visibility='default' filepath='include/linux/quota.h' line='336' column='1'/>
+          <var-decl name='get_projid' type-id='c23b3cbc' visibility='default' filepath='include/linux/quota.h' line='338' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='get_inode_usage' type-id='6b7539fb' visibility='default' filepath='include/linux/quota.h' line='338' column='1'/>
+          <var-decl name='get_inode_usage' type-id='6b7539fb' visibility='default' filepath='include/linux/quota.h' line='340' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='get_next_id' type-id='70b08f83' visibility='default' filepath='include/linux/quota.h' line='340' column='1'/>
+          <var-decl name='get_next_id' type-id='70b08f83' visibility='default' filepath='include/linux/quota.h' line='342' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='342' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='344' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='343' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='345' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='dst_metrics' size-in-bits='576' is-struct='yes' visibility='default' filepath='include/net/dst.h' line='93' column='1' id='e51de182'>
@@ -26101,222 +26123,222 @@
           <var-decl name='prefix_rcv_add_addr' type-id='1cebc84d' visibility='default' filepath='include/net/ndisc.h' line='214' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='net_device_ops' size-in-bits='4608' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='1255' column='1' id='ba44c7d8'>
+      <class-decl name='net_device_ops' size-in-bits='4608' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='1258' column='1' id='ba44c7d8'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='ndo_init' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1256' column='1'/>
+          <var-decl name='ndo_init' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1259' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='ndo_uninit' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='1257' column='1'/>
+          <var-decl name='ndo_uninit' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='1260' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='ndo_open' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1258' column='1'/>
+          <var-decl name='ndo_open' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1261' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='ndo_stop' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1259' column='1'/>
+          <var-decl name='ndo_stop' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1262' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ndo_start_xmit' type-id='bd3f3f93' visibility='default' filepath='include/linux/netdevice.h' line='1260' column='1'/>
+          <var-decl name='ndo_start_xmit' type-id='bd3f3f93' visibility='default' filepath='include/linux/netdevice.h' line='1263' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='ndo_features_check' type-id='7a0ed254' visibility='default' filepath='include/linux/netdevice.h' line='1262' column='1'/>
+          <var-decl name='ndo_features_check' type-id='7a0ed254' visibility='default' filepath='include/linux/netdevice.h' line='1265' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='ndo_select_queue' type-id='e9b83e5c' visibility='default' filepath='include/linux/netdevice.h' line='1265' column='1'/>
+          <var-decl name='ndo_select_queue' type-id='e9b83e5c' visibility='default' filepath='include/linux/netdevice.h' line='1268' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='ndo_change_rx_flags' type-id='c7c94ce1' visibility='default' filepath='include/linux/netdevice.h' line='1269' column='1'/>
+          <var-decl name='ndo_change_rx_flags' type-id='c7c94ce1' visibility='default' filepath='include/linux/netdevice.h' line='1272' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='ndo_set_rx_mode' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='1271' column='1'/>
+          <var-decl name='ndo_set_rx_mode' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='1274' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='ndo_set_mac_address' type-id='f4dd5cc5' visibility='default' filepath='include/linux/netdevice.h' line='1272' column='1'/>
+          <var-decl name='ndo_set_mac_address' type-id='f4dd5cc5' visibility='default' filepath='include/linux/netdevice.h' line='1275' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='ndo_validate_addr' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1274' column='1'/>
+          <var-decl name='ndo_validate_addr' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1277' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='ndo_do_ioctl' type-id='cc325be7' visibility='default' filepath='include/linux/netdevice.h' line='1275' column='1'/>
+          <var-decl name='ndo_do_ioctl' type-id='cc325be7' visibility='default' filepath='include/linux/netdevice.h' line='1278' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='ndo_set_config' type-id='bd2d1eba' visibility='default' filepath='include/linux/netdevice.h' line='1277' column='1'/>
+          <var-decl name='ndo_set_config' type-id='bd2d1eba' visibility='default' filepath='include/linux/netdevice.h' line='1280' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='ndo_change_mtu' type-id='d6762aa0' visibility='default' filepath='include/linux/netdevice.h' line='1279' column='1'/>
+          <var-decl name='ndo_change_mtu' type-id='d6762aa0' visibility='default' filepath='include/linux/netdevice.h' line='1282' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='ndo_neigh_setup' type-id='5c9f2a92' visibility='default' filepath='include/linux/netdevice.h' line='1281' column='1'/>
+          <var-decl name='ndo_neigh_setup' type-id='5c9f2a92' visibility='default' filepath='include/linux/netdevice.h' line='1284' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='ndo_tx_timeout' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='1283' column='1'/>
+          <var-decl name='ndo_tx_timeout' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='1286' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='ndo_get_stats64' type-id='cb4c6db1' visibility='default' filepath='include/linux/netdevice.h' line='1285' column='1'/>
+          <var-decl name='ndo_get_stats64' type-id='cb4c6db1' visibility='default' filepath='include/linux/netdevice.h' line='1288' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='ndo_has_offload_stats' type-id='e95fd96b' visibility='default' filepath='include/linux/netdevice.h' line='1287' column='1'/>
+          <var-decl name='ndo_has_offload_stats' type-id='e95fd96b' visibility='default' filepath='include/linux/netdevice.h' line='1290' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='ndo_get_offload_stats' type-id='f98694f9' visibility='default' filepath='include/linux/netdevice.h' line='1288' column='1'/>
+          <var-decl name='ndo_get_offload_stats' type-id='f98694f9' visibility='default' filepath='include/linux/netdevice.h' line='1291' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='ndo_get_stats' type-id='3217f9ba' visibility='default' filepath='include/linux/netdevice.h' line='1291' column='1'/>
+          <var-decl name='ndo_get_stats' type-id='3217f9ba' visibility='default' filepath='include/linux/netdevice.h' line='1294' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='ndo_vlan_rx_add_vid' type-id='4fcb4c39' visibility='default' filepath='include/linux/netdevice.h' line='1293' column='1'/>
+          <var-decl name='ndo_vlan_rx_add_vid' type-id='4fcb4c39' visibility='default' filepath='include/linux/netdevice.h' line='1296' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='ndo_vlan_rx_kill_vid' type-id='4fcb4c39' visibility='default' filepath='include/linux/netdevice.h' line='1295' column='1'/>
+          <var-decl name='ndo_vlan_rx_kill_vid' type-id='4fcb4c39' visibility='default' filepath='include/linux/netdevice.h' line='1298' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='ndo_set_vf_mac' type-id='bae60bcf' visibility='default' filepath='include/linux/netdevice.h' line='1303' column='1'/>
+          <var-decl name='ndo_set_vf_mac' type-id='bae60bcf' visibility='default' filepath='include/linux/netdevice.h' line='1306' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1472'>
-          <var-decl name='ndo_set_vf_vlan' type-id='699131d0' visibility='default' filepath='include/linux/netdevice.h' line='1305' column='1'/>
+          <var-decl name='ndo_set_vf_vlan' type-id='699131d0' visibility='default' filepath='include/linux/netdevice.h' line='1308' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='ndo_set_vf_rate' type-id='7cd466e6' visibility='default' filepath='include/linux/netdevice.h' line='1308' column='1'/>
+          <var-decl name='ndo_set_vf_rate' type-id='7cd466e6' visibility='default' filepath='include/linux/netdevice.h' line='1311' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1600'>
-          <var-decl name='ndo_set_vf_spoofchk' type-id='0c16aca1' visibility='default' filepath='include/linux/netdevice.h' line='1311' column='1'/>
+          <var-decl name='ndo_set_vf_spoofchk' type-id='0c16aca1' visibility='default' filepath='include/linux/netdevice.h' line='1314' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1664'>
-          <var-decl name='ndo_set_vf_trust' type-id='0c16aca1' visibility='default' filepath='include/linux/netdevice.h' line='1313' column='1'/>
+          <var-decl name='ndo_set_vf_trust' type-id='0c16aca1' visibility='default' filepath='include/linux/netdevice.h' line='1316' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1728'>
-          <var-decl name='ndo_get_vf_config' type-id='d22f8cbe' visibility='default' filepath='include/linux/netdevice.h' line='1315' column='1'/>
+          <var-decl name='ndo_get_vf_config' type-id='d22f8cbe' visibility='default' filepath='include/linux/netdevice.h' line='1318' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1792'>
-          <var-decl name='ndo_set_vf_link_state' type-id='b54cfa0f' visibility='default' filepath='include/linux/netdevice.h' line='1318' column='1'/>
+          <var-decl name='ndo_set_vf_link_state' type-id='b54cfa0f' visibility='default' filepath='include/linux/netdevice.h' line='1321' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='ndo_get_vf_stats' type-id='eee971fd' visibility='default' filepath='include/linux/netdevice.h' line='1320' column='1'/>
+          <var-decl name='ndo_get_vf_stats' type-id='eee971fd' visibility='default' filepath='include/linux/netdevice.h' line='1323' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1920'>
-          <var-decl name='ndo_set_vf_port' type-id='af60ef81' visibility='default' filepath='include/linux/netdevice.h' line='1324' column='1'/>
+          <var-decl name='ndo_set_vf_port' type-id='af60ef81' visibility='default' filepath='include/linux/netdevice.h' line='1327' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1984'>
-          <var-decl name='ndo_get_vf_port' type-id='be55abd8' visibility='default' filepath='include/linux/netdevice.h' line='1327' column='1'/>
+          <var-decl name='ndo_get_vf_port' type-id='be55abd8' visibility='default' filepath='include/linux/netdevice.h' line='1330' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='ndo_set_vf_guid' type-id='0617ad2b' visibility='default' filepath='include/linux/netdevice.h' line='1329' column='1'/>
+          <var-decl name='ndo_set_vf_guid' type-id='0617ad2b' visibility='default' filepath='include/linux/netdevice.h' line='1332' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='ndo_set_vf_rss_query_en' type-id='0c16aca1' visibility='default' filepath='include/linux/netdevice.h' line='1332' column='1'/>
+          <var-decl name='ndo_set_vf_rss_query_en' type-id='0c16aca1' visibility='default' filepath='include/linux/netdevice.h' line='1335' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2176'>
-          <var-decl name='ndo_setup_tc' type-id='06b83346' visibility='default' filepath='include/linux/netdevice.h' line='1335' column='1'/>
+          <var-decl name='ndo_setup_tc' type-id='06b83346' visibility='default' filepath='include/linux/netdevice.h' line='1338' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2240'>
-          <var-decl name='ndo_rx_flow_steer' type-id='47498e6c' visibility='default' filepath='include/linux/netdevice.h' line='1363' column='1'/>
+          <var-decl name='ndo_rx_flow_steer' type-id='47498e6c' visibility='default' filepath='include/linux/netdevice.h' line='1366' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2304'>
-          <var-decl name='ndo_add_slave' type-id='031fe454' visibility='default' filepath='include/linux/netdevice.h' line='1368' column='1'/>
+          <var-decl name='ndo_add_slave' type-id='031fe454' visibility='default' filepath='include/linux/netdevice.h' line='1371' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2368'>
-          <var-decl name='ndo_del_slave' type-id='ed3019e9' visibility='default' filepath='include/linux/netdevice.h' line='1371' column='1'/>
+          <var-decl name='ndo_del_slave' type-id='ed3019e9' visibility='default' filepath='include/linux/netdevice.h' line='1374' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2432'>
-          <var-decl name='ndo_fix_features' type-id='4a028f44' visibility='default' filepath='include/linux/netdevice.h' line='1373' column='1'/>
+          <var-decl name='ndo_fix_features' type-id='4a028f44' visibility='default' filepath='include/linux/netdevice.h' line='1376' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2496'>
-          <var-decl name='ndo_set_features' type-id='10dae4c5' visibility='default' filepath='include/linux/netdevice.h' line='1375' column='1'/>
+          <var-decl name='ndo_set_features' type-id='10dae4c5' visibility='default' filepath='include/linux/netdevice.h' line='1378' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2560'>
-          <var-decl name='ndo_neigh_construct' type-id='92446276' visibility='default' filepath='include/linux/netdevice.h' line='1377' column='1'/>
+          <var-decl name='ndo_neigh_construct' type-id='92446276' visibility='default' filepath='include/linux/netdevice.h' line='1380' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2624'>
-          <var-decl name='ndo_neigh_destroy' type-id='11e89fb9' visibility='default' filepath='include/linux/netdevice.h' line='1379' column='1'/>
+          <var-decl name='ndo_neigh_destroy' type-id='11e89fb9' visibility='default' filepath='include/linux/netdevice.h' line='1382' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2688'>
-          <var-decl name='ndo_fdb_add' type-id='c0fb2f11' visibility='default' filepath='include/linux/netdevice.h' line='1382' column='1'/>
+          <var-decl name='ndo_fdb_add' type-id='c0fb2f11' visibility='default' filepath='include/linux/netdevice.h' line='1385' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2752'>
-          <var-decl name='ndo_fdb_del' type-id='e6032f80' visibility='default' filepath='include/linux/netdevice.h' line='1388' column='1'/>
+          <var-decl name='ndo_fdb_del' type-id='e6032f80' visibility='default' filepath='include/linux/netdevice.h' line='1391' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2816'>
-          <var-decl name='ndo_fdb_dump' type-id='147cd5a7' visibility='default' filepath='include/linux/netdevice.h' line='1393' column='1'/>
+          <var-decl name='ndo_fdb_dump' type-id='147cd5a7' visibility='default' filepath='include/linux/netdevice.h' line='1396' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2880'>
-          <var-decl name='ndo_bridge_setlink' type-id='1223555b' visibility='default' filepath='include/linux/netdevice.h' line='1399' column='1'/>
+          <var-decl name='ndo_bridge_setlink' type-id='1223555b' visibility='default' filepath='include/linux/netdevice.h' line='1402' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2944'>
-          <var-decl name='ndo_bridge_getlink' type-id='e78e01a9' visibility='default' filepath='include/linux/netdevice.h' line='1402' column='1'/>
+          <var-decl name='ndo_bridge_getlink' type-id='e78e01a9' visibility='default' filepath='include/linux/netdevice.h' line='1405' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3008'>
-          <var-decl name='ndo_bridge_dellink' type-id='1223555b' visibility='default' filepath='include/linux/netdevice.h' line='1407' column='1'/>
+          <var-decl name='ndo_bridge_dellink' type-id='1223555b' visibility='default' filepath='include/linux/netdevice.h' line='1410' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3072'>
-          <var-decl name='ndo_change_carrier' type-id='e36088ec' visibility='default' filepath='include/linux/netdevice.h' line='1410' column='1'/>
+          <var-decl name='ndo_change_carrier' type-id='e36088ec' visibility='default' filepath='include/linux/netdevice.h' line='1413' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3136'>
-          <var-decl name='ndo_get_phys_port_id' type-id='98252144' visibility='default' filepath='include/linux/netdevice.h' line='1412' column='1'/>
+          <var-decl name='ndo_get_phys_port_id' type-id='98252144' visibility='default' filepath='include/linux/netdevice.h' line='1415' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3200'>
-          <var-decl name='ndo_get_phys_port_name' type-id='5139dd84' visibility='default' filepath='include/linux/netdevice.h' line='1414' column='1'/>
+          <var-decl name='ndo_get_phys_port_name' type-id='5139dd84' visibility='default' filepath='include/linux/netdevice.h' line='1417' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3264'>
-          <var-decl name='ndo_udp_tunnel_add' type-id='a43821b9' visibility='default' filepath='include/linux/netdevice.h' line='1416' column='1'/>
+          <var-decl name='ndo_udp_tunnel_add' type-id='a43821b9' visibility='default' filepath='include/linux/netdevice.h' line='1419' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3328'>
-          <var-decl name='ndo_udp_tunnel_del' type-id='a43821b9' visibility='default' filepath='include/linux/netdevice.h' line='1418' column='1'/>
+          <var-decl name='ndo_udp_tunnel_del' type-id='a43821b9' visibility='default' filepath='include/linux/netdevice.h' line='1421' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3392'>
-          <var-decl name='ndo_dfwd_add_station' type-id='e2d7f258' visibility='default' filepath='include/linux/netdevice.h' line='1420' column='1'/>
+          <var-decl name='ndo_dfwd_add_station' type-id='e2d7f258' visibility='default' filepath='include/linux/netdevice.h' line='1423' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3456'>
-          <var-decl name='ndo_dfwd_del_station' type-id='5ac7baf4' visibility='default' filepath='include/linux/netdevice.h' line='1422' column='1'/>
+          <var-decl name='ndo_dfwd_del_station' type-id='5ac7baf4' visibility='default' filepath='include/linux/netdevice.h' line='1425' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3520'>
-          <var-decl name='ndo_get_lock_subclass' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1425' column='1'/>
+          <var-decl name='ndo_get_lock_subclass' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1428' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3584'>
-          <var-decl name='ndo_set_tx_maxrate' type-id='c1e0b02f' visibility='default' filepath='include/linux/netdevice.h' line='1426' column='1'/>
+          <var-decl name='ndo_set_tx_maxrate' type-id='c1e0b02f' visibility='default' filepath='include/linux/netdevice.h' line='1429' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3648'>
-          <var-decl name='ndo_get_iflink' type-id='4753b592' visibility='default' filepath='include/linux/netdevice.h' line='1429' column='1'/>
+          <var-decl name='ndo_get_iflink' type-id='4753b592' visibility='default' filepath='include/linux/netdevice.h' line='1432' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3712'>
-          <var-decl name='ndo_change_proto_down' type-id='e36088ec' visibility='default' filepath='include/linux/netdevice.h' line='1430' column='1'/>
+          <var-decl name='ndo_change_proto_down' type-id='e36088ec' visibility='default' filepath='include/linux/netdevice.h' line='1433' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3776'>
-          <var-decl name='ndo_fill_metadata_dst' type-id='2cc5a575' visibility='default' filepath='include/linux/netdevice.h' line='1432' column='1'/>
+          <var-decl name='ndo_fill_metadata_dst' type-id='2cc5a575' visibility='default' filepath='include/linux/netdevice.h' line='1435' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3840'>
-          <var-decl name='ndo_set_rx_headroom' type-id='c7c94ce1' visibility='default' filepath='include/linux/netdevice.h' line='1434' column='1'/>
+          <var-decl name='ndo_set_rx_headroom' type-id='c7c94ce1' visibility='default' filepath='include/linux/netdevice.h' line='1437' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3904'>
-          <var-decl name='ndo_bpf' type-id='49f84764' visibility='default' filepath='include/linux/netdevice.h' line='1436' column='1'/>
+          <var-decl name='ndo_bpf' type-id='49f84764' visibility='default' filepath='include/linux/netdevice.h' line='1439' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3968'>
-          <var-decl name='ndo_xdp_xmit' type-id='0c7d25ff' visibility='default' filepath='include/linux/netdevice.h' line='1438' column='1'/>
+          <var-decl name='ndo_xdp_xmit' type-id='0c7d25ff' visibility='default' filepath='include/linux/netdevice.h' line='1441' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4032'>
-          <var-decl name='ndo_xsk_async_xmit' type-id='0f8df030' visibility='default' filepath='include/linux/netdevice.h' line='1441' column='1'/>
+          <var-decl name='ndo_xsk_async_xmit' type-id='0f8df030' visibility='default' filepath='include/linux/netdevice.h' line='1444' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4096'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1444' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1447' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4160'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1445' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1448' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4224'>
-          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1446' column='1'/>
+          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1449' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4288'>
-          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1447' column='1'/>
+          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1450' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4352'>
-          <var-decl name='android_kabi_reserved5' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1448' column='1'/>
+          <var-decl name='android_kabi_reserved5' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1451' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4416'>
-          <var-decl name='android_kabi_reserved6' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1449' column='1'/>
+          <var-decl name='android_kabi_reserved6' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1452' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4480'>
-          <var-decl name='android_kabi_reserved7' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1450' column='1'/>
+          <var-decl name='android_kabi_reserved7' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1453' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4544'>
-          <var-decl name='android_kabi_reserved8' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1451' column='1'/>
+          <var-decl name='android_kabi_reserved8' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1454' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='nf_logger' is-struct='yes' visibility='default' is-declaration-only='yes' id='01c546da'/>
@@ -26357,21 +26379,21 @@
         </data-member>
       </class-decl>
       <class-decl name='pcpu_lstats' is-struct='yes' visibility='default' is-declaration-only='yes' id='b71b307b'/>
-      <class-decl name='pcpu_sw_netstats' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='2423' column='1' id='101eeec5'>
+      <class-decl name='pcpu_sw_netstats' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='2422' column='1' id='101eeec5'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='rx_packets' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2424' column='1'/>
+          <var-decl name='rx_packets' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2423' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='rx_bytes' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2425' column='1'/>
+          <var-decl name='rx_bytes' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2424' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='tx_packets' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2426' column='1'/>
+          <var-decl name='tx_packets' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2425' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='tx_bytes' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2427' column='1'/>
+          <var-decl name='tx_bytes' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2426' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='syncp' type-id='e4d85780' visibility='default' filepath='include/linux/netdevice.h' line='2428' column='1'/>
+          <var-decl name='syncp' type-id='e4d85780' visibility='default' filepath='include/linux/netdevice.h' line='2427' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='pcpu_vstats' size-in-bits='128' is-struct='yes' visibility='default' filepath='drivers/net/veth.c' line='39' column='1' id='f21ec7ed'>
@@ -26437,45 +26459,45 @@
           <var-decl name='lock' type-id='fb4018a0' visibility='default' filepath='include/net/sch_generic.h' line='54' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='quotactl_ops' size-in-bits='832' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='434' column='1' id='8ce4ff83'>
+      <class-decl name='quotactl_ops' size-in-bits='832' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='436' column='1' id='8ce4ff83'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='quota_on' type-id='de6b64d0' visibility='default' filepath='include/linux/quota.h' line='435' column='1'/>
+          <var-decl name='quota_on' type-id='de6b64d0' visibility='default' filepath='include/linux/quota.h' line='437' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='quota_off' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='436' column='1'/>
+          <var-decl name='quota_off' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='438' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='quota_enable' type-id='7aa5a21e' visibility='default' filepath='include/linux/quota.h' line='437' column='1'/>
+          <var-decl name='quota_enable' type-id='7aa5a21e' visibility='default' filepath='include/linux/quota.h' line='439' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='quota_disable' type-id='7aa5a21e' visibility='default' filepath='include/linux/quota.h' line='438' column='1'/>
+          <var-decl name='quota_disable' type-id='7aa5a21e' visibility='default' filepath='include/linux/quota.h' line='440' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='quota_sync' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='439' column='1'/>
+          <var-decl name='quota_sync' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='441' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='set_info' type-id='4e326e06' visibility='default' filepath='include/linux/quota.h' line='440' column='1'/>
+          <var-decl name='set_info' type-id='4e326e06' visibility='default' filepath='include/linux/quota.h' line='442' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='get_dqblk' type-id='9e27a8d4' visibility='default' filepath='include/linux/quota.h' line='441' column='1'/>
+          <var-decl name='get_dqblk' type-id='9e27a8d4' visibility='default' filepath='include/linux/quota.h' line='443' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='get_nextdqblk' type-id='483e8c3a' visibility='default' filepath='include/linux/quota.h' line='442' column='1'/>
+          <var-decl name='get_nextdqblk' type-id='483e8c3a' visibility='default' filepath='include/linux/quota.h' line='444' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='set_dqblk' type-id='9e27a8d4' visibility='default' filepath='include/linux/quota.h' line='444' column='1'/>
+          <var-decl name='set_dqblk' type-id='9e27a8d4' visibility='default' filepath='include/linux/quota.h' line='446' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='get_state' type-id='eb638046' visibility='default' filepath='include/linux/quota.h' line='445' column='1'/>
+          <var-decl name='get_state' type-id='eb638046' visibility='default' filepath='include/linux/quota.h' line='447' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='rm_xquota' type-id='7aa5a21e' visibility='default' filepath='include/linux/quota.h' line='446' column='1'/>
+          <var-decl name='rm_xquota' type-id='7aa5a21e' visibility='default' filepath='include/linux/quota.h' line='448' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='448' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='450' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='449' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='451' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='rt6_exception_bucket' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/net/ip6_fib.h' line='110' column='1' id='db281924'>
@@ -26764,12 +26786,12 @@
           <var-decl name='lock' type-id='fb4018a0' visibility='default' filepath='include/net/udp.h' line='64' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='uncached_list' size-in-bits='192' is-struct='yes' visibility='default' filepath='net/ipv4/route.c' line='1518' column='1' id='6b1203e5'>
+      <class-decl name='uncached_list' size-in-bits='192' is-struct='yes' visibility='default' filepath='net/ipv4/route.c' line='1520' column='1' id='6b1203e5'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='lock' type-id='fb4018a0' visibility='default' filepath='net/ipv4/route.c' line='1519' column='1'/>
+          <var-decl name='lock' type-id='fb4018a0' visibility='default' filepath='net/ipv4/route.c' line='1521' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='head' type-id='72f469ec' visibility='default' filepath='net/ipv4/route.c' line='1520' column='1'/>
+          <var-decl name='head' type-id='72f469ec' visibility='default' filepath='net/ipv4/route.c' line='1522' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='worker_pool' size-in-bits='7168' is-struct='yes' visibility='default' filepath='kernel/workqueue.c' line='147' column='1' id='19ea21fe'>
@@ -27875,237 +27897,237 @@
           <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/net/sch_generic.h' line='326' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wiphy' size-in-bits='11264' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='4154' column='1' id='68523a94'>
+      <class-decl name='wiphy' size-in-bits='11264' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='4157' column='1' id='68523a94'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='perm_addr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4158' column='1'/>
+          <var-decl name='perm_addr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4161' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='48'>
-          <var-decl name='addr_mask' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4159' column='1'/>
+          <var-decl name='addr_mask' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4162' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='addresses' type-id='01b378ab' visibility='default' filepath='include/net/cfg80211.h' line='4161' column='1'/>
+          <var-decl name='addresses' type-id='01b378ab' visibility='default' filepath='include/net/cfg80211.h' line='4164' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='mgmt_stypes' type-id='0cda9080' visibility='default' filepath='include/net/cfg80211.h' line='4163' column='1'/>
+          <var-decl name='mgmt_stypes' type-id='0cda9080' visibility='default' filepath='include/net/cfg80211.h' line='4166' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='iface_combinations' type-id='fa32a449' visibility='default' filepath='include/net/cfg80211.h' line='4165' column='1'/>
+          <var-decl name='iface_combinations' type-id='fa32a449' visibility='default' filepath='include/net/cfg80211.h' line='4168' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='n_iface_combinations' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4166' column='1'/>
+          <var-decl name='n_iface_combinations' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4169' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='352'>
-          <var-decl name='software_iftypes' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4167' column='1'/>
+          <var-decl name='software_iftypes' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4170' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='368'>
-          <var-decl name='n_addresses' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4169' column='1'/>
+          <var-decl name='n_addresses' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4172' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='interface_modes' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4172' column='1'/>
+          <var-decl name='interface_modes' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4175' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='400'>
-          <var-decl name='max_acl_mac_addrs' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4174' column='1'/>
+          <var-decl name='max_acl_mac_addrs' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4177' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='416'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4176' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4179' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='regulatory_flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4176' column='1'/>
+          <var-decl name='regulatory_flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4179' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='480'>
-          <var-decl name='features' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4176' column='1'/>
+          <var-decl name='features' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4179' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='ext_features' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4177' column='1'/>
+          <var-decl name='ext_features' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4180' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='ap_sme_capa' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4179' column='1'/>
+          <var-decl name='ap_sme_capa' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4182' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='608'>
-          <var-decl name='signal_type' type-id='b8524648' visibility='default' filepath='include/net/cfg80211.h' line='4181' column='1'/>
+          <var-decl name='signal_type' type-id='b8524648' visibility='default' filepath='include/net/cfg80211.h' line='4184' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='bss_priv_size' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4183' column='1'/>
+          <var-decl name='bss_priv_size' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4186' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='672'>
-          <var-decl name='max_scan_ssids' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4184' column='1'/>
+          <var-decl name='max_scan_ssids' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4187' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='680'>
-          <var-decl name='max_sched_scan_reqs' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4185' column='1'/>
+          <var-decl name='max_sched_scan_reqs' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4188' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='688'>
-          <var-decl name='max_sched_scan_ssids' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4186' column='1'/>
+          <var-decl name='max_sched_scan_ssids' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4189' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='696'>
-          <var-decl name='max_match_sets' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4187' column='1'/>
+          <var-decl name='max_match_sets' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4190' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='max_scan_ie_len' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4188' column='1'/>
+          <var-decl name='max_scan_ie_len' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4191' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='720'>
-          <var-decl name='max_sched_scan_ie_len' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4189' column='1'/>
+          <var-decl name='max_sched_scan_ie_len' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4192' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='736'>
-          <var-decl name='max_sched_scan_plans' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4190' column='1'/>
+          <var-decl name='max_sched_scan_plans' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4193' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='max_sched_scan_plan_interval' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4191' column='1'/>
+          <var-decl name='max_sched_scan_plan_interval' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4194' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='800'>
-          <var-decl name='max_sched_scan_plan_iterations' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4192' column='1'/>
+          <var-decl name='max_sched_scan_plan_iterations' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4195' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='n_cipher_suites' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4194' column='1'/>
+          <var-decl name='n_cipher_suites' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4197' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='cipher_suites' type-id='aded214c' visibility='default' filepath='include/net/cfg80211.h' line='4195' column='1'/>
+          <var-decl name='cipher_suites' type-id='aded214c' visibility='default' filepath='include/net/cfg80211.h' line='4198' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='iftype_akm_suites' type-id='6196d741' visibility='default' filepath='include/net/cfg80211.h' line='4197' column='1'/>
+          <var-decl name='iftype_akm_suites' type-id='6196d741' visibility='default' filepath='include/net/cfg80211.h' line='4200' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='num_iftype_akm_suites' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='4198' column='1'/>
+          <var-decl name='num_iftype_akm_suites' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='4201' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1056'>
-          <var-decl name='retry_short' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4200' column='1'/>
+          <var-decl name='retry_short' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4203' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1064'>
-          <var-decl name='retry_long' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4201' column='1'/>
+          <var-decl name='retry_long' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4204' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='frag_threshold' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4202' column='1'/>
+          <var-decl name='frag_threshold' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4205' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1120'>
-          <var-decl name='rts_threshold' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4203' column='1'/>
+          <var-decl name='rts_threshold' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4206' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='coverage_class' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4204' column='1'/>
+          <var-decl name='coverage_class' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4207' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1160'>
-          <var-decl name='fw_version' type-id='16dc656a' visibility='default' filepath='include/net/cfg80211.h' line='4206' column='1'/>
+          <var-decl name='fw_version' type-id='16dc656a' visibility='default' filepath='include/net/cfg80211.h' line='4209' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1440'>
-          <var-decl name='hw_version' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4207' column='1'/>
+          <var-decl name='hw_version' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4210' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1472'>
-          <var-decl name='wowlan' type-id='78a34b70' visibility='default' filepath='include/net/cfg80211.h' line='4210' column='1'/>
+          <var-decl name='wowlan' type-id='78a34b70' visibility='default' filepath='include/net/cfg80211.h' line='4213' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='wowlan_config' type-id='9d025b00' visibility='default' filepath='include/net/cfg80211.h' line='4211' column='1'/>
+          <var-decl name='wowlan_config' type-id='9d025b00' visibility='default' filepath='include/net/cfg80211.h' line='4214' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1600'>
-          <var-decl name='max_remain_on_channel_duration' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4214' column='1'/>
+          <var-decl name='max_remain_on_channel_duration' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4217' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1616'>
-          <var-decl name='max_num_pmkids' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4216' column='1'/>
+          <var-decl name='max_num_pmkids' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4219' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1632'>
-          <var-decl name='available_antennas_tx' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4218' column='1'/>
+          <var-decl name='available_antennas_tx' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4221' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1664'>
-          <var-decl name='available_antennas_rx' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4219' column='1'/>
+          <var-decl name='available_antennas_rx' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4222' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1696'>
-          <var-decl name='probe_resp_offload' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4226' column='1'/>
+          <var-decl name='probe_resp_offload' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4229' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1728'>
-          <var-decl name='extended_capabilities' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='4228' column='1'/>
+          <var-decl name='extended_capabilities' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='4231' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1792'>
-          <var-decl name='extended_capabilities_mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='4228' column='1'/>
+          <var-decl name='extended_capabilities_mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='4231' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='extended_capabilities_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4229' column='1'/>
+          <var-decl name='extended_capabilities_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4232' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1920'>
-          <var-decl name='iftype_ext_capab' type-id='3ca25343' visibility='default' filepath='include/net/cfg80211.h' line='4231' column='1'/>
+          <var-decl name='iftype_ext_capab' type-id='3ca25343' visibility='default' filepath='include/net/cfg80211.h' line='4234' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1984'>
-          <var-decl name='num_iftype_ext_capab' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='4232' column='1'/>
+          <var-decl name='num_iftype_ext_capab' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='4235' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='privid' type-id='eaa32e2f' visibility='default' filepath='include/net/cfg80211.h' line='4239' column='1'/>
+          <var-decl name='privid' type-id='eaa32e2f' visibility='default' filepath='include/net/cfg80211.h' line='4242' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='bands' type-id='640b99c7' visibility='default' filepath='include/net/cfg80211.h' line='4241' column='1'/>
+          <var-decl name='bands' type-id='640b99c7' visibility='default' filepath='include/net/cfg80211.h' line='4244' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2304'>
-          <var-decl name='reg_notifier' type-id='39ee8359' visibility='default' filepath='include/net/cfg80211.h' line='4244' column='1'/>
+          <var-decl name='reg_notifier' type-id='39ee8359' visibility='default' filepath='include/net/cfg80211.h' line='4247' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2368'>
-          <var-decl name='regd' type-id='4e819401' visibility='default' filepath='include/net/cfg80211.h' line='4249' column='1'/>
+          <var-decl name='regd' type-id='4e819401' visibility='default' filepath='include/net/cfg80211.h' line='4252' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2432'>
-          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/net/cfg80211.h' line='4253' column='1'/>
+          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/net/cfg80211.h' line='4256' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10048'>
-          <var-decl name='registered' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4256' column='1'/>
+          <var-decl name='registered' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4259' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10112'>
-          <var-decl name='debugfsdir' type-id='27675065' visibility='default' filepath='include/net/cfg80211.h' line='4259' column='1'/>
+          <var-decl name='debugfsdir' type-id='27675065' visibility='default' filepath='include/net/cfg80211.h' line='4262' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10176'>
-          <var-decl name='ht_capa_mod_mask' type-id='81f1a1a8' visibility='default' filepath='include/net/cfg80211.h' line='4261' column='1'/>
+          <var-decl name='ht_capa_mod_mask' type-id='81f1a1a8' visibility='default' filepath='include/net/cfg80211.h' line='4264' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10240'>
-          <var-decl name='vht_capa_mod_mask' type-id='fffb07a4' visibility='default' filepath='include/net/cfg80211.h' line='4262' column='1'/>
+          <var-decl name='vht_capa_mod_mask' type-id='fffb07a4' visibility='default' filepath='include/net/cfg80211.h' line='4265' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10304'>
-          <var-decl name='wdev_list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4264' column='1'/>
+          <var-decl name='wdev_list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4267' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10432'>
-          <var-decl name='_net' type-id='c9df1e6c' visibility='default' filepath='include/net/cfg80211.h' line='4267' column='1'/>
+          <var-decl name='_net' type-id='c9df1e6c' visibility='default' filepath='include/net/cfg80211.h' line='4270' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10496'>
-          <var-decl name='coalesce' type-id='9ef499bf' visibility='default' filepath='include/net/cfg80211.h' line='4273' column='1'/>
+          <var-decl name='coalesce' type-id='9ef499bf' visibility='default' filepath='include/net/cfg80211.h' line='4276' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10560'>
-          <var-decl name='vendor_commands' type-id='41e3f782' visibility='default' filepath='include/net/cfg80211.h' line='4275' column='1'/>
+          <var-decl name='vendor_commands' type-id='41e3f782' visibility='default' filepath='include/net/cfg80211.h' line='4278' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10624'>
-          <var-decl name='vendor_events' type-id='b188cc4f' visibility='default' filepath='include/net/cfg80211.h' line='4276' column='1'/>
+          <var-decl name='vendor_events' type-id='b188cc4f' visibility='default' filepath='include/net/cfg80211.h' line='4279' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10688'>
-          <var-decl name='n_vendor_commands' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4277' column='1'/>
+          <var-decl name='n_vendor_commands' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4280' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10720'>
-          <var-decl name='n_vendor_events' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4277' column='1'/>
+          <var-decl name='n_vendor_events' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4280' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10752'>
-          <var-decl name='max_ap_assoc_sta' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4279' column='1'/>
+          <var-decl name='max_ap_assoc_sta' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4282' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10768'>
-          <var-decl name='max_num_csa_counters' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4281' column='1'/>
+          <var-decl name='max_num_csa_counters' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4284' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10776'>
-          <var-decl name='max_adj_channel_rssi_comp' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4282' column='1'/>
+          <var-decl name='max_adj_channel_rssi_comp' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4285' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10784'>
-          <var-decl name='bss_select_support' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4284' column='1'/>
+          <var-decl name='bss_select_support' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4287' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10816'>
-          <var-decl name='cookie_counter' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='4286' column='1'/>
+          <var-decl name='cookie_counter' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='4289' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10880'>
-          <var-decl name='nan_supported_bands' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4288' column='1'/>
+          <var-decl name='nan_supported_bands' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4291' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10912'>
-          <var-decl name='txq_limit' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4290' column='1'/>
+          <var-decl name='txq_limit' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4293' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10944'>
-          <var-decl name='txq_memory_limit' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4291' column='1'/>
+          <var-decl name='txq_memory_limit' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4294' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10976'>
-          <var-decl name='txq_quantum' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4292' column='1'/>
+          <var-decl name='txq_quantum' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4295' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='support_mbssid' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4294' column='1'/>
+          <var-decl name='support_mbssid' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4297' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1'>
-          <var-decl name='support_only_he_mbssid' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4295' column='1'/>
+          <var-decl name='support_only_he_mbssid' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4298' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='11264'>
-          <var-decl name='priv' type-id='e84913bd' visibility='default' filepath='include/net/cfg80211.h' line='4297' column='1'/>
+          <var-decl name='priv' type-id='e84913bd' visibility='default' filepath='include/net/cfg80211.h' line='4300' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='xattr_handler' size-in-bits='448' is-struct='yes' visibility='default' filepath='include/linux/xattr.h' line='28' column='1' id='2d3dd5e3'>
@@ -28309,6 +28331,14 @@
           <var-decl name='hi' type-id='3f1a6b60' visibility='default' filepath='include/net/xfrm.h' line='1074' column='1'/>
         </data-member>
       </class-decl>
+      <class-decl name='__anonymous_struct__2' size-in-bits='32' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/cpu_rmap.h' line='31' column='1' id='bb08c7e1'>
+        <data-member access='public' layout-offset-in-bits='0'>
+          <var-decl name='index' type-id='1dc6a898' visibility='default' filepath='include/linux/cpu_rmap.h' line='32' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='16'>
+          <var-decl name='dist' type-id='1dc6a898' visibility='default' filepath='include/linux/cpu_rmap.h' line='33' column='1'/>
+        </data-member>
+      </class-decl>
       <qualified-type-def type-id='47692c1a' const='yes' id='2212bd2d'/>
       <qualified-type-def type-id='90cdb889' const='yes' id='4e65adfa'/>
       <qualified-type-def type-id='1cf1b931' const='yes' id='f4f74d50'/>
@@ -28803,158 +28833,158 @@
           <var-decl name='insn_hook' type-id='ae2f55a8' visibility='default' filepath='include/linux/bpf.h' line='260' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_bss' size-in-bits='768' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2088' column='1' id='5f145050'>
+      <class-decl name='cfg80211_bss' size-in-bits='768' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2091' column='1' id='5f145050'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='channel' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2089' column='1'/>
+          <var-decl name='channel' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2092' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='scan_width' type-id='95d46034' visibility='default' filepath='include/net/cfg80211.h' line='2090' column='1'/>
+          <var-decl name='scan_width' type-id='95d46034' visibility='default' filepath='include/net/cfg80211.h' line='2093' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='ies' type-id='f344e815' visibility='default' filepath='include/net/cfg80211.h' line='2092' column='1'/>
+          <var-decl name='ies' type-id='f344e815' visibility='default' filepath='include/net/cfg80211.h' line='2095' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='beacon_ies' type-id='f344e815' visibility='default' filepath='include/net/cfg80211.h' line='2093' column='1'/>
+          <var-decl name='beacon_ies' type-id='f344e815' visibility='default' filepath='include/net/cfg80211.h' line='2096' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='proberesp_ies' type-id='f344e815' visibility='default' filepath='include/net/cfg80211.h' line='2094' column='1'/>
+          <var-decl name='proberesp_ies' type-id='f344e815' visibility='default' filepath='include/net/cfg80211.h' line='2097' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='hidden_beacon_bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='2096' column='1'/>
+          <var-decl name='hidden_beacon_bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='2099' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='transmitted_bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='2097' column='1'/>
+          <var-decl name='transmitted_bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='2100' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='nontrans_list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='2098' column='1'/>
+          <var-decl name='nontrans_list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='2101' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='signal' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='2100' column='1'/>
+          <var-decl name='signal' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='2103' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='608'>
-          <var-decl name='beacon_interval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2102' column='1'/>
+          <var-decl name='beacon_interval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2105' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='624'>
-          <var-decl name='capability' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2103' column='1'/>
+          <var-decl name='capability' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2106' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2105' column='1'/>
+          <var-decl name='bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2108' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='688'>
-          <var-decl name='chains' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2106' column='1'/>
+          <var-decl name='chains' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2109' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='696'>
-          <var-decl name='chain_signal' type-id='da004b74' visibility='default' filepath='include/net/cfg80211.h' line='2107' column='1'/>
+          <var-decl name='chain_signal' type-id='da004b74' visibility='default' filepath='include/net/cfg80211.h' line='2110' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='728'>
-          <var-decl name='bssid_index' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2109' column='1'/>
+          <var-decl name='bssid_index' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2112' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='736'>
-          <var-decl name='max_bssid_indicator' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2110' column='1'/>
+          <var-decl name='max_bssid_indicator' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2113' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='priv' type-id='29c3368c' visibility='default' filepath='include/net/cfg80211.h' line='2112' column='1'/>
+          <var-decl name='priv' type-id='29c3368c' visibility='default' filepath='include/net/cfg80211.h' line='2115' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_connect_params' size-in-bits='2816' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2400' column='1' id='1291defd'>
+      <class-decl name='cfg80211_connect_params' size-in-bits='2816' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2403' column='1' id='1291defd'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='channel' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2401' column='1'/>
+          <var-decl name='channel' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2404' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='channel_hint' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2402' column='1'/>
+          <var-decl name='channel_hint' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2405' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2403' column='1'/>
+          <var-decl name='bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2406' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='bssid_hint' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2404' column='1'/>
+          <var-decl name='bssid_hint' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2407' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2405' column='1'/>
+          <var-decl name='ssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2408' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='ssid_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2406' column='1'/>
+          <var-decl name='ssid_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2409' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='auth_type' type-id='f7dadf06' visibility='default' filepath='include/net/cfg80211.h' line='2407' column='1'/>
+          <var-decl name='auth_type' type-id='f7dadf06' visibility='default' filepath='include/net/cfg80211.h' line='2410' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2408' column='1'/>
+          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2411' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2409' column='1'/>
+          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2412' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='privacy' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2410' column='1'/>
+          <var-decl name='privacy' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2413' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='608'>
-          <var-decl name='mfp' type-id='dfb2486c' visibility='default' filepath='include/net/cfg80211.h' line='2411' column='1'/>
+          <var-decl name='mfp' type-id='dfb2486c' visibility='default' filepath='include/net/cfg80211.h' line='2414' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='crypto' type-id='f81bbd3b' visibility='default' filepath='include/net/cfg80211.h' line='2412' column='1'/>
+          <var-decl name='crypto' type-id='f81bbd3b' visibility='default' filepath='include/net/cfg80211.h' line='2415' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='key' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2413' column='1'/>
+          <var-decl name='key' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2416' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='key_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2414' column='1'/>
+          <var-decl name='key_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2417' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1352'>
-          <var-decl name='key_idx' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2414' column='1'/>
+          <var-decl name='key_idx' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2417' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1376'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2415' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2418' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='bg_scan_period' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2416' column='1'/>
+          <var-decl name='bg_scan_period' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2419' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1440'>
-          <var-decl name='ht_capa' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2417' column='1'/>
+          <var-decl name='ht_capa' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2420' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1648'>
-          <var-decl name='ht_capa_mask' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2418' column='1'/>
+          <var-decl name='ht_capa_mask' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2421' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='vht_capa' type-id='2eec6999' visibility='default' filepath='include/net/cfg80211.h' line='2419' column='1'/>
+          <var-decl name='vht_capa' type-id='2eec6999' visibility='default' filepath='include/net/cfg80211.h' line='2422' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1952'>
-          <var-decl name='vht_capa_mask' type-id='2eec6999' visibility='default' filepath='include/net/cfg80211.h' line='2420' column='1'/>
+          <var-decl name='vht_capa_mask' type-id='2eec6999' visibility='default' filepath='include/net/cfg80211.h' line='2423' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='pbss' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2421' column='1'/>
+          <var-decl name='pbss' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2424' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2080'>
-          <var-decl name='bss_select' type-id='d24a933d' visibility='default' filepath='include/net/cfg80211.h' line='2422' column='1'/>
+          <var-decl name='bss_select' type-id='d24a933d' visibility='default' filepath='include/net/cfg80211.h' line='2425' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2176'>
-          <var-decl name='prev_bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2423' column='1'/>
+          <var-decl name='prev_bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2426' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2240'>
-          <var-decl name='fils_erp_username' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2424' column='1'/>
+          <var-decl name='fils_erp_username' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2427' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2304'>
-          <var-decl name='fils_erp_username_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2425' column='1'/>
+          <var-decl name='fils_erp_username_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2428' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2368'>
-          <var-decl name='fils_erp_realm' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2426' column='1'/>
+          <var-decl name='fils_erp_realm' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2429' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2432'>
-          <var-decl name='fils_erp_realm_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2427' column='1'/>
+          <var-decl name='fils_erp_realm_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2430' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2496'>
-          <var-decl name='fils_erp_next_seq_num' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2428' column='1'/>
+          <var-decl name='fils_erp_next_seq_num' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2431' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2560'>
-          <var-decl name='fils_erp_rrk' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2429' column='1'/>
+          <var-decl name='fils_erp_rrk' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2432' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2624'>
-          <var-decl name='fils_erp_rrk_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2430' column='1'/>
+          <var-decl name='fils_erp_rrk_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2433' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2688'>
-          <var-decl name='want_1x' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2431' column='1'/>
+          <var-decl name='want_1x' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2434' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2720'>
-          <var-decl name='edmg' type-id='d87e6929' visibility='default' filepath='include/net/cfg80211.h' line='2432' column='1'/>
+          <var-decl name='edmg' type-id='d87e6929' visibility='default' filepath='include/net/cfg80211.h' line='2435' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='crypto_ahash' size-in-bits='2048' is-struct='yes' visibility='default' filepath='include/crypto/hash.h' line='200' column='1' id='8eb3840c'>
@@ -29231,50 +29261,50 @@
           <var-decl name='flags' type-id='a7832498' visibility='default' filepath='include/linux/pm_qos.h' line='72' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='quota_format_ops' size-in-bits='640' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='310' column='1' id='87cad984'>
+      <class-decl name='quota_format_ops' size-in-bits='640' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='312' column='1' id='87cad984'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='check_quota_file' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='311' column='1'/>
+          <var-decl name='check_quota_file' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='313' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='read_file_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='312' column='1'/>
+          <var-decl name='read_file_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='314' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='write_file_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='313' column='1'/>
+          <var-decl name='write_file_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='315' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='free_file_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='314' column='1'/>
+          <var-decl name='free_file_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='316' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='read_dqblk' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='315' column='1'/>
+          <var-decl name='read_dqblk' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='317' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='commit_dqblk' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='316' column='1'/>
+          <var-decl name='commit_dqblk' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='318' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='release_dqblk' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='317' column='1'/>
+          <var-decl name='release_dqblk' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='319' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='get_next_id' type-id='70b08f83' visibility='default' filepath='include/linux/quota.h' line='318' column='1'/>
+          <var-decl name='get_next_id' type-id='70b08f83' visibility='default' filepath='include/linux/quota.h' line='320' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='320' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='322' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='321' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='323' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='quota_format_type' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='452' column='1' id='c2be49b0'>
+      <class-decl name='quota_format_type' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='454' column='1' id='c2be49b0'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='qf_fmt_id' type-id='95e97e5e' visibility='default' filepath='include/linux/quota.h' line='453' column='1'/>
+          <var-decl name='qf_fmt_id' type-id='95e97e5e' visibility='default' filepath='include/linux/quota.h' line='455' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='qf_ops' type-id='bd561d05' visibility='default' filepath='include/linux/quota.h' line='454' column='1'/>
+          <var-decl name='qf_ops' type-id='bd561d05' visibility='default' filepath='include/linux/quota.h' line='456' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='qf_owner' type-id='2730d015' visibility='default' filepath='include/linux/quota.h' line='455' column='1'/>
+          <var-decl name='qf_owner' type-id='2730d015' visibility='default' filepath='include/linux/quota.h' line='457' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='qf_next' type-id='eb9a3ab6' visibility='default' filepath='include/linux/quota.h' line='456' column='1'/>
+          <var-decl name='qf_next' type-id='eb9a3ab6' visibility='default' filepath='include/linux/quota.h' line='458' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='tc_sizespec' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/uapi/linux/pkt_sched.h' line='101' column='1' id='c7a2cf9f'>
@@ -29303,18 +29333,18 @@
           <var-decl name='tsize' type-id='f0981eeb' visibility='default' filepath='include/uapi/linux/pkt_sched.h' line='109' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='xps_map' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='753' column='1' id='279bdcdf'>
+      <class-decl name='xps_map' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='756' column='1' id='279bdcdf'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='len' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='754' column='1'/>
+          <var-decl name='len' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='757' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='alloc_len' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='755' column='1'/>
+          <var-decl name='alloc_len' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='758' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/linux/netdevice.h' line='756' column='1'/>
+          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/linux/netdevice.h' line='759' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='queues' type-id='0f300383' visibility='default' filepath='include/linux/netdevice.h' line='757' column='1'/>
+          <var-decl name='queues' type-id='0f300383' visibility='default' filepath='include/linux/netdevice.h' line='760' column='1'/>
         </data-member>
       </class-decl>
       <pointer-type-def type-id='269d8092' size-in-bits='64' id='81f1a1a8'/>
@@ -29354,7 +29384,7 @@
         <enumerator name='CFG80211_CONN_ABANDON' value='10'/>
         <enumerator name='CFG80211_CONN_CONNECTED' value='11'/>
       </enum-decl>
-      <enum-decl name='cfg80211_signal_type' filepath='include/net/cfg80211.h' line='2004' column='1' id='b8524648'>
+      <enum-decl name='cfg80211_signal_type' filepath='include/net/cfg80211.h' line='2007' column='1' id='b8524648'>
         <underlying-type type-id='9cac1fee'/>
         <enumerator name='CFG80211_SIGNAL_TYPE_NONE' value='0'/>
         <enumerator name='CFG80211_SIGNAL_TYPE_MBM' value='1'/>
@@ -29485,88 +29515,88 @@
       <array-type-def dimensions='1' type-id='a84c031d' size-in-bits='488' id='1de7616e'>
         <subrange length='61' type-id='7ff19f0f' id='b51728a6'/>
       </array-type-def>
-      <class-decl name='cfg80211_bss_selection' size-in-bits='96' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2329' column='1' id='d24a933d'>
+      <class-decl name='cfg80211_bss_selection' size-in-bits='96' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2332' column='1' id='d24a933d'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='behaviour' type-id='10fd9108' visibility='default' filepath='include/net/cfg80211.h' line='2330' column='1'/>
+          <var-decl name='behaviour' type-id='10fd9108' visibility='default' filepath='include/net/cfg80211.h' line='2333' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='param' type-id='0532d6f6' visibility='default' filepath='include/net/cfg80211.h' line='2334' column='1'/>
+          <var-decl name='param' type-id='0532d6f6' visibility='default' filepath='include/net/cfg80211.h' line='2337' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_crypto_settings' size-in-bits='640' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='821' column='1' id='f81bbd3b'>
+      <class-decl name='cfg80211_crypto_settings' size-in-bits='640' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='824' column='1' id='f81bbd3b'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='wpa_versions' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='822' column='1'/>
+          <var-decl name='wpa_versions' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='825' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='cipher_group' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='823' column='1'/>
+          <var-decl name='cipher_group' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='826' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='n_ciphers_pairwise' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='824' column='1'/>
+          <var-decl name='n_ciphers_pairwise' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='827' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='ciphers_pairwise' type-id='586ea944' visibility='default' filepath='include/net/cfg80211.h' line='825' column='1'/>
+          <var-decl name='ciphers_pairwise' type-id='586ea944' visibility='default' filepath='include/net/cfg80211.h' line='828' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='n_akm_suites' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='826' column='1'/>
+          <var-decl name='n_akm_suites' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='829' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='288'>
-          <var-decl name='akm_suites' type-id='1872161b' visibility='default' filepath='include/net/cfg80211.h' line='827' column='1'/>
+          <var-decl name='akm_suites' type-id='1872161b' visibility='default' filepath='include/net/cfg80211.h' line='830' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='352'>
-          <var-decl name='control_port' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='828' column='1'/>
+          <var-decl name='control_port' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='831' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='368'>
-          <var-decl name='control_port_ethertype' type-id='84a5c3d4' visibility='default' filepath='include/net/cfg80211.h' line='829' column='1'/>
+          <var-decl name='control_port_ethertype' type-id='84a5c3d4' visibility='default' filepath='include/net/cfg80211.h' line='832' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='control_port_no_encrypt' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='830' column='1'/>
+          <var-decl name='control_port_no_encrypt' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='833' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='392'>
-          <var-decl name='control_port_over_nl80211' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='831' column='1'/>
+          <var-decl name='control_port_over_nl80211' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='834' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='wep_keys' type-id='706d79ff' visibility='default' filepath='include/net/cfg80211.h' line='832' column='1'/>
+          <var-decl name='wep_keys' type-id='706d79ff' visibility='default' filepath='include/net/cfg80211.h' line='835' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='wep_tx_key' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='833' column='1'/>
+          <var-decl name='wep_tx_key' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='836' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='psk' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='834' column='1'/>
+          <var-decl name='psk' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='837' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_wowlan' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2575' column='1' id='80126e32'>
+      <class-decl name='cfg80211_wowlan' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2578' column='1' id='80126e32'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='any' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2576' column='1'/>
+          <var-decl name='any' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2579' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8'>
-          <var-decl name='disconnect' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2576' column='1'/>
+          <var-decl name='disconnect' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2579' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='magic_pkt' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2576' column='1'/>
+          <var-decl name='magic_pkt' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2579' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='24'>
-          <var-decl name='gtk_rekey_failure' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2576' column='1'/>
+          <var-decl name='gtk_rekey_failure' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2579' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='eap_identity_req' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2577' column='1'/>
+          <var-decl name='eap_identity_req' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2580' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='40'>
-          <var-decl name='four_way_handshake' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2577' column='1'/>
+          <var-decl name='four_way_handshake' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2580' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='48'>
-          <var-decl name='rfkill_release' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2578' column='1'/>
+          <var-decl name='rfkill_release' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2581' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='patterns' type-id='1ed3660c' visibility='default' filepath='include/net/cfg80211.h' line='2579' column='1'/>
+          <var-decl name='patterns' type-id='1ed3660c' visibility='default' filepath='include/net/cfg80211.h' line='2582' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='tcp' type-id='e0c1c1b8' visibility='default' filepath='include/net/cfg80211.h' line='2580' column='1'/>
+          <var-decl name='tcp' type-id='e0c1c1b8' visibility='default' filepath='include/net/cfg80211.h' line='2583' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='n_patterns' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2581' column='1'/>
+          <var-decl name='n_patterns' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2584' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='nd_config' type-id='9e4995c7' visibility='default' filepath='include/net/cfg80211.h' line='2582' column='1'/>
+          <var-decl name='nd_config' type-id='9e4995c7' visibility='default' filepath='include/net/cfg80211.h' line='2585' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='free_area' size-in-bits='832' is-struct='yes' visibility='default' filepath='include/linux/mmzone.h' line='99' column='1' id='39ec6fe5'>
@@ -29659,26 +29689,26 @@
           <var-decl name='name' type-id='ac1fa8c0' visibility='default' filepath='include/uapi/linux/wireless.h' line='1067' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='key_params' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='548' column='1' id='45947737'>
+      <class-decl name='key_params' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='551' column='1' id='45947737'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='key' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='549' column='1'/>
+          <var-decl name='key' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='552' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='seq' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='550' column='1'/>
+          <var-decl name='seq' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='553' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='key_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='551' column='1'/>
+          <var-decl name='key_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='554' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='seq_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='552' column='1'/>
+          <var-decl name='seq_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='555' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='cipher' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='553' column='1'/>
+          <var-decl name='cipher' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='556' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='mac_address' size-in-bits='48' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='870' column='1' id='6d8d26fb'>
+      <class-decl name='mac_address' size-in-bits='48' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='873' column='1' id='6d8d26fb'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='addr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='871' column='1'/>
+          <var-decl name='addr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='874' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='neigh_table' size-in-bits='4224' is-struct='yes' visibility='default' filepath='include/net/neighbour.h' line='192' column='1' id='aebe1cff'>
@@ -29991,30 +30021,30 @@
           <var-decl name='pin_ranges' type-id='72f469ec' visibility='default' filepath='drivers/gpio/gpiolib.h' line='72' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='ieee80211_iface_combination' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3735' column='1' id='1179f27e'>
+      <class-decl name='ieee80211_iface_combination' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3738' column='1' id='1179f27e'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='limits' type-id='2fde6795' visibility='default' filepath='include/net/cfg80211.h' line='3740' column='1'/>
+          <var-decl name='limits' type-id='2fde6795' visibility='default' filepath='include/net/cfg80211.h' line='3743' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='num_different_channels' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3746' column='1'/>
+          <var-decl name='num_different_channels' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3749' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='max_interfaces' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3752' column='1'/>
+          <var-decl name='max_interfaces' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3755' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='112'>
-          <var-decl name='n_limits' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3758' column='1'/>
+          <var-decl name='n_limits' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3761' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='120'>
-          <var-decl name='beacon_int_infra_match' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='3765' column='1'/>
+          <var-decl name='beacon_int_infra_match' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='3768' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='radar_detect_widths' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3771' column='1'/>
+          <var-decl name='radar_detect_widths' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3774' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='136'>
-          <var-decl name='radar_detect_regions' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3777' column='1'/>
+          <var-decl name='radar_detect_regions' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3780' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='beacon_int_min_gcd' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3790' column='1'/>
+          <var-decl name='beacon_int_min_gcd' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3793' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='ieee80211_mcs_info' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/linux/ieee80211.h' line='1276' column='1' id='835fe4c6'>
@@ -30080,12 +30110,12 @@
           <var-decl name='iftype_data' type-id='e76a43c4' visibility='default' filepath='include/net/cfg80211.h' line='413' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='ieee80211_txrx_stypes' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3793' column='1' id='21301fc9'>
+      <class-decl name='ieee80211_txrx_stypes' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3796' column='1' id='21301fc9'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='tx' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3794' column='1'/>
+          <var-decl name='tx' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3797' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='rx' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3794' column='1'/>
+          <var-decl name='rx' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3797' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='ieee80211_vht_mcs_info' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/linux/ieee80211.h' line='1480' column='1' id='830056b5'>
@@ -30194,86 +30224,86 @@
           <var-decl name='owner' type-id='2730d015' visibility='default' filepath='include/net/sch_generic.h' line='307' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wiphy_coalesce_support' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3869' column='1' id='7124a2a6'>
+      <class-decl name='wiphy_coalesce_support' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3872' column='1' id='7124a2a6'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='n_rules' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3870' column='1'/>
+          <var-decl name='n_rules' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3873' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='max_delay' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3871' column='1'/>
+          <var-decl name='max_delay' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3874' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='n_patterns' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3872' column='1'/>
+          <var-decl name='n_patterns' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3875' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='pattern_max_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3873' column='1'/>
+          <var-decl name='pattern_max_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3876' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='pattern_min_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3874' column='1'/>
+          <var-decl name='pattern_min_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3877' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='max_pkt_offset' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3875' column='1'/>
+          <var-decl name='max_pkt_offset' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3878' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wiphy_iftype_akm_suites' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3971' column='1' id='c86a8a16'>
+      <class-decl name='wiphy_iftype_akm_suites' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3974' column='1' id='c86a8a16'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='iftypes_mask' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3972' column='1'/>
+          <var-decl name='iftypes_mask' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3975' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='akm_suites' type-id='aded214c' visibility='default' filepath='include/net/cfg80211.h' line='3973' column='1'/>
+          <var-decl name='akm_suites' type-id='aded214c' visibility='default' filepath='include/net/cfg80211.h' line='3976' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='n_akm_suites' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3974' column='1'/>
+          <var-decl name='n_akm_suites' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3977' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wiphy_iftype_ext_capab' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3955' column='1' id='378a6c5a'>
+      <class-decl name='wiphy_iftype_ext_capab' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3958' column='1' id='378a6c5a'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='iftype' type-id='86505f90' visibility='default' filepath='include/net/cfg80211.h' line='3956' column='1'/>
+          <var-decl name='iftype' type-id='86505f90' visibility='default' filepath='include/net/cfg80211.h' line='3959' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='extended_capabilities' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='3957' column='1'/>
+          <var-decl name='extended_capabilities' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='3960' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='extended_capabilities_mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='3958' column='1'/>
+          <var-decl name='extended_capabilities_mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='3961' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='extended_capabilities_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3959' column='1'/>
+          <var-decl name='extended_capabilities_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3962' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wiphy_vendor_command' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3934' column='1' id='fc206ed1'>
+      <class-decl name='wiphy_vendor_command' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3937' column='1' id='fc206ed1'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='info' type-id='e223f110' visibility='default' filepath='include/net/cfg80211.h' line='3935' column='1'/>
+          <var-decl name='info' type-id='e223f110' visibility='default' filepath='include/net/cfg80211.h' line='3938' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3936' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3939' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='doit' type-id='a9032da3' visibility='default' filepath='include/net/cfg80211.h' line='3937' column='1'/>
+          <var-decl name='doit' type-id='a9032da3' visibility='default' filepath='include/net/cfg80211.h' line='3940' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='dumpit' type-id='dcf81beb' visibility='default' filepath='include/net/cfg80211.h' line='3939' column='1'/>
+          <var-decl name='dumpit' type-id='dcf81beb' visibility='default' filepath='include/net/cfg80211.h' line='3942' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wiphy_wowlan_support' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3849' column='1' id='5bbd300b'>
+      <class-decl name='wiphy_wowlan_support' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3852' column='1' id='5bbd300b'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3850' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3853' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='n_patterns' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3851' column='1'/>
+          <var-decl name='n_patterns' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3854' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='pattern_max_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3852' column='1'/>
+          <var-decl name='pattern_max_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3855' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='pattern_min_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3853' column='1'/>
+          <var-decl name='pattern_min_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3856' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='max_pkt_offset' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3854' column='1'/>
+          <var-decl name='max_pkt_offset' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3857' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='max_nd_match_sets' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3855' column='1'/>
+          <var-decl name='max_nd_match_sets' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3858' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='tcp' type-id='b3ebc0a8' visibility='default' filepath='include/net/cfg80211.h' line='3856' column='1'/>
+          <var-decl name='tcp' type-id='b3ebc0a8' visibility='default' filepath='include/net/cfg80211.h' line='3859' column='1'/>
         </data-member>
       </class-decl>
       <qualified-type-def type-id='d9ceb659' const='yes' id='170bab5e'/>
@@ -30308,12 +30338,12 @@
       <array-type-def dimensions='1' type-id='19c2251e' size-in-bits='64' id='1872161b'>
         <subrange length='2' type-id='7ff19f0f' id='52efc4ef'/>
       </array-type-def>
-      <union-decl name='__anonymous_union__3' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/net/cfg80211.h' line='2331' column='1' id='0532d6f6'>
+      <union-decl name='__anonymous_union__3' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/net/cfg80211.h' line='2334' column='1' id='0532d6f6'>
         <data-member access='public'>
-          <var-decl name='band_pref' type-id='3eaa0294' visibility='default' filepath='include/net/cfg80211.h' line='2332' column='1'/>
+          <var-decl name='band_pref' type-id='3eaa0294' visibility='default' filepath='include/net/cfg80211.h' line='2335' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='adjust' type-id='5da08e25' visibility='default' filepath='include/net/cfg80211.h' line='2333' column='1'/>
+          <var-decl name='adjust' type-id='5da08e25' visibility='default' filepath='include/net/cfg80211.h' line='2336' column='1'/>
         </data-member>
       </union-decl>
       <pointer-type-def type-id='d66ae2ca' size-in-bits='64' id='5c4c6144'/>
@@ -30362,176 +30392,176 @@
           <var-decl name='dump_stats' type-id='6313cef0' visibility='default' filepath='include/net/sch_generic.h' line='209' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_bss_ies' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2049' column='1' id='7eedb398'>
+      <class-decl name='cfg80211_bss_ies' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2052' column='1' id='7eedb398'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='tsf' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='2050' column='1'/>
+          <var-decl name='tsf' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='2053' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='callback_head' type-id='e3d8ce29' visibility='default' filepath='include/net/cfg80211.h' line='2051' column='1'/>
+          <var-decl name='callback_head' type-id='e3d8ce29' visibility='default' filepath='include/net/cfg80211.h' line='2054' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2052' column='1'/>
+          <var-decl name='len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2055' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='224'>
-          <var-decl name='from_beacon' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2053' column='1'/>
+          <var-decl name='from_beacon' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2056' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='232'>
-          <var-decl name='data' type-id='29c3368c' visibility='default' filepath='include/net/cfg80211.h' line='2054' column='1'/>
+          <var-decl name='data' type-id='29c3368c' visibility='default' filepath='include/net/cfg80211.h' line='2057' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_bss_select_adjust' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1905' column='1' id='5da08e25'>
+      <class-decl name='cfg80211_bss_select_adjust' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1908' column='1' id='5da08e25'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='band' type-id='3eaa0294' visibility='default' filepath='include/net/cfg80211.h' line='1906' column='1'/>
+          <var-decl name='band' type-id='3eaa0294' visibility='default' filepath='include/net/cfg80211.h' line='1909' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='delta' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1907' column='1'/>
+          <var-decl name='delta' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1910' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_pkt_pattern' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2516' column='1' id='76959226'>
+      <class-decl name='cfg80211_pkt_pattern' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2519' column='1' id='76959226'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2517' column='1'/>
+          <var-decl name='mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2520' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='pattern' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2517' column='1'/>
+          <var-decl name='pattern' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2520' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='pattern_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2518' column='1'/>
+          <var-decl name='pattern_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2521' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='pkt_offset' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2519' column='1'/>
+          <var-decl name='pkt_offset' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2522' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_sched_scan_request' size-in-bits='1536' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1960' column='1' id='12a2e88f'>
+      <class-decl name='cfg80211_sched_scan_request' size-in-bits='1536' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1963' column='1' id='12a2e88f'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='reqid' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1961' column='1'/>
+          <var-decl name='reqid' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1964' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='ssids' type-id='a1fa7fb7' visibility='default' filepath='include/net/cfg80211.h' line='1962' column='1'/>
+          <var-decl name='ssids' type-id='a1fa7fb7' visibility='default' filepath='include/net/cfg80211.h' line='1965' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='n_ssids' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1963' column='1'/>
+          <var-decl name='n_ssids' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1966' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='n_channels' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1964' column='1'/>
+          <var-decl name='n_channels' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1967' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='scan_width' type-id='95d46034' visibility='default' filepath='include/net/cfg80211.h' line='1965' column='1'/>
+          <var-decl name='scan_width' type-id='95d46034' visibility='default' filepath='include/net/cfg80211.h' line='1968' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1966' column='1'/>
+          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1969' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='1967' column='1'/>
+          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='1970' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1968' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1971' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='match_sets' type-id='ea00c914' visibility='default' filepath='include/net/cfg80211.h' line='1969' column='1'/>
+          <var-decl name='match_sets' type-id='ea00c914' visibility='default' filepath='include/net/cfg80211.h' line='1972' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='n_match_sets' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1970' column='1'/>
+          <var-decl name='n_match_sets' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1973' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='544'>
-          <var-decl name='min_rssi_thold' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='1971' column='1'/>
+          <var-decl name='min_rssi_thold' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='1974' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='delay' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1972' column='1'/>
+          <var-decl name='delay' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1975' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='scan_plans' type-id='302e9391' visibility='default' filepath='include/net/cfg80211.h' line='1973' column='1'/>
+          <var-decl name='scan_plans' type-id='302e9391' visibility='default' filepath='include/net/cfg80211.h' line='1976' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='n_scan_plans' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1974' column='1'/>
+          <var-decl name='n_scan_plans' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1977' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='736'>
-          <var-decl name='mac_addr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1976' column='1'/>
+          <var-decl name='mac_addr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1979' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='784'>
-          <var-decl name='mac_addr_mask' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1977' column='1'/>
+          <var-decl name='mac_addr_mask' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1980' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='relative_rssi_set' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1979' column='1'/>
+          <var-decl name='relative_rssi_set' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1982' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='840'>
-          <var-decl name='relative_rssi' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1980' column='1'/>
+          <var-decl name='relative_rssi' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1983' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='864'>
-          <var-decl name='rssi_adjust' type-id='5da08e25' visibility='default' filepath='include/net/cfg80211.h' line='1981' column='1'/>
+          <var-decl name='rssi_adjust' type-id='5da08e25' visibility='default' filepath='include/net/cfg80211.h' line='1984' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='wiphy' type-id='666fb412' visibility='default' filepath='include/net/cfg80211.h' line='1984' column='1'/>
+          <var-decl name='wiphy' type-id='666fb412' visibility='default' filepath='include/net/cfg80211.h' line='1987' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='dev' type-id='68a2d05b' visibility='default' filepath='include/net/cfg80211.h' line='1985' column='1'/>
+          <var-decl name='dev' type-id='68a2d05b' visibility='default' filepath='include/net/cfg80211.h' line='1988' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='scan_start' type-id='7359adad' visibility='default' filepath='include/net/cfg80211.h' line='1986' column='1'/>
+          <var-decl name='scan_start' type-id='7359adad' visibility='default' filepath='include/net/cfg80211.h' line='1989' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='report_results' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1987' column='1'/>
+          <var-decl name='report_results' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1990' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='callback_head' type-id='e3d8ce29' visibility='default' filepath='include/net/cfg80211.h' line='1988' column='1'/>
+          <var-decl name='callback_head' type-id='e3d8ce29' visibility='default' filepath='include/net/cfg80211.h' line='1991' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='owner_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1989' column='1'/>
+          <var-decl name='owner_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1992' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1376'>
-          <var-decl name='nl_owner_dead' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1990' column='1'/>
+          <var-decl name='nl_owner_dead' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1993' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='1991' column='1'/>
+          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='1994' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='channels' type-id='14cad687' visibility='default' filepath='include/net/cfg80211.h' line='1994' column='1'/>
+          <var-decl name='channels' type-id='14cad687' visibility='default' filepath='include/net/cfg80211.h' line='1997' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_wowlan_tcp' size-in-bits='768' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2541' column='1' id='1752769a'>
+      <class-decl name='cfg80211_wowlan_tcp' size-in-bits='768' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2544' column='1' id='1752769a'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='sock' type-id='13103032' visibility='default' filepath='include/net/cfg80211.h' line='2542' column='1'/>
+          <var-decl name='sock' type-id='13103032' visibility='default' filepath='include/net/cfg80211.h' line='2545' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='src' type-id='78a133c2' visibility='default' filepath='include/net/cfg80211.h' line='2543' column='1'/>
+          <var-decl name='src' type-id='78a133c2' visibility='default' filepath='include/net/cfg80211.h' line='2546' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='dst' type-id='78a133c2' visibility='default' filepath='include/net/cfg80211.h' line='2543' column='1'/>
+          <var-decl name='dst' type-id='78a133c2' visibility='default' filepath='include/net/cfg80211.h' line='2546' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='src_port' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2544' column='1'/>
+          <var-decl name='src_port' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2547' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='144'>
-          <var-decl name='dst_port' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2544' column='1'/>
+          <var-decl name='dst_port' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2547' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='dst_mac' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2545' column='1'/>
+          <var-decl name='dst_mac' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2548' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='224'>
-          <var-decl name='payload_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2546' column='1'/>
+          <var-decl name='payload_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2549' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='payload' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2547' column='1'/>
+          <var-decl name='payload' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2550' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='payload_seq' type-id='d5a1b375' visibility='default' filepath='include/net/cfg80211.h' line='2548' column='1'/>
+          <var-decl name='payload_seq' type-id='d5a1b375' visibility='default' filepath='include/net/cfg80211.h' line='2551' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='416'>
-          <var-decl name='data_interval' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2549' column='1'/>
+          <var-decl name='data_interval' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2552' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='wake_len' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2550' column='1'/>
+          <var-decl name='wake_len' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2553' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='wake_data' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2551' column='1'/>
+          <var-decl name='wake_data' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2554' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='wake_mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2551' column='1'/>
+          <var-decl name='wake_mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2554' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='tokens_size' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2552' column='1'/>
+          <var-decl name='tokens_size' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2555' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='672'>
-          <var-decl name='payload_tok' type-id='2868c21b' visibility='default' filepath='include/net/cfg80211.h' line='2554' column='1'/>
+          <var-decl name='payload_tok' type-id='2868c21b' visibility='default' filepath='include/net/cfg80211.h' line='2557' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='ieee80211_sta_ht_cap' size-in-bits='176' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='267' column='1' id='a041735c'>
@@ -31011,31 +31041,31 @@
       <pointer-type-def type-id='9e497d29' size-in-bits='64' id='9438aa05'/>
       <pointer-type-def type-id='e7c67bff' size-in-bits='64' id='19c5fc2b'/>
       <pointer-type-def type-id='da4d9050' size-in-bits='64' id='8937f3c2'/>
-      <class-decl name='cfg80211_match_set' size-in-bits='352' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1879' column='1' id='7430554e'>
+      <class-decl name='cfg80211_match_set' size-in-bits='352' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1882' column='1' id='7430554e'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='ssid' type-id='0c960fcf' visibility='default' filepath='include/net/cfg80211.h' line='1880' column='1'/>
+          <var-decl name='ssid' type-id='0c960fcf' visibility='default' filepath='include/net/cfg80211.h' line='1883' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='264'>
-          <var-decl name='bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1881' column='1'/>
+          <var-decl name='bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1884' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='rssi_thold' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='1882' column='1'/>
+          <var-decl name='rssi_thold' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='1885' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_sched_scan_plan' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1894' column='1' id='391881a9'>
+      <class-decl name='cfg80211_sched_scan_plan' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1897' column='1' id='391881a9'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='interval' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1895' column='1'/>
+          <var-decl name='interval' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1898' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='iterations' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1896' column='1'/>
+          <var-decl name='iterations' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1899' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_ssid' size-in-bits='264' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1780' column='1' id='0c960fcf'>
+      <class-decl name='cfg80211_ssid' size-in-bits='264' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1783' column='1' id='0c960fcf'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='ssid' type-id='e3dc4fdb' visibility='default' filepath='include/net/cfg80211.h' line='1781' column='1'/>
+          <var-decl name='ssid' type-id='e3dc4fdb' visibility='default' filepath='include/net/cfg80211.h' line='1784' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ssid_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1782' column='1'/>
+          <var-decl name='ssid_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1785' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='gpio_irq_chip' size-in-bits='1024' is-struct='yes' visibility='default' filepath='include/linux/gpio/driver.h' line='27' column='1' id='31045126'>
@@ -31105,12 +31135,12 @@
           <var-decl name='max_bandwidth_khz' type-id='19c2251e' visibility='default' filepath='include/net/regulatory.h' line='184' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='ieee80211_iface_limit' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3671' column='1' id='e47a5a92'>
+      <class-decl name='ieee80211_iface_limit' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3674' column='1' id='e47a5a92'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='max' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3672' column='1'/>
+          <var-decl name='max' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3675' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='types' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3673' column='1'/>
+          <var-decl name='types' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3676' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='ieee80211_power_rule' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/net/regulatory.h' line='187' column='1' id='736b3d64'>
@@ -31137,21 +31167,21 @@
           <var-decl name='ap' type-id='00286dfe' visibility='default' filepath='include/net/regulatory.h' line='214' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wiphy_wowlan_tcp_support' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3826' column='1' id='557bca33'>
+      <class-decl name='wiphy_wowlan_tcp_support' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3829' column='1' id='557bca33'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='tok' type-id='6a8cbf59' visibility='default' filepath='include/net/cfg80211.h' line='3827' column='1'/>
+          <var-decl name='tok' type-id='6a8cbf59' visibility='default' filepath='include/net/cfg80211.h' line='3830' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='data_payload_max' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3828' column='1'/>
+          <var-decl name='data_payload_max' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3831' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='data_interval_max' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3829' column='1'/>
+          <var-decl name='data_interval_max' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3832' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='wake_payload_max' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3830' column='1'/>
+          <var-decl name='wake_payload_max' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3833' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='seq' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='3831' column='1'/>
+          <var-decl name='seq' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='3834' column='1'/>
         </data-member>
       </class-decl>
       <pointer-type-def type-id='b99c00c9' size-in-bits='64' id='13956559'/>
@@ -31510,11 +31540,11 @@
     </abi-instr>
     <abi-instr address-size='64' path='arch/arm64/kernel/ptrace.c' language='LANG_C89'>
       <pointer-type-def type-id='e57536d9' size-in-bits='64' id='20862e61'/>
-      <function-decl name='perf_event_release_kernel' mangled-name='perf_event_release_kernel' filepath='include/linux/perf_event.h' line='906' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='perf_event_release_kernel'>
+      <function-decl name='perf_event_release_kernel' mangled-name='perf_event_release_kernel' filepath='include/linux/perf_event.h' line='909' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='perf_event_release_kernel'>
         <parameter type-id='2bf16f59'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='perf_event_create_kernel_counter' mangled-name='perf_event_create_kernel_counter' filepath='include/linux/perf_event.h' line='908' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='perf_event_create_kernel_counter'>
+      <function-decl name='perf_event_create_kernel_counter' mangled-name='perf_event_create_kernel_counter' filepath='include/linux/perf_event.h' line='911' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='perf_event_create_kernel_counter'>
         <parameter type-id='20862e61'/>
         <parameter type-id='95e97e5e'/>
         <parameter type-id='f23e2572'/>
@@ -32445,313 +32475,313 @@
       </function-decl>
     </abi-instr>
     <abi-instr address-size='64' path='block/blk-mq-pci.c' language='LANG_C89'>
-      <function-decl name='pci_irq_get_affinity' mangled-name='pci_irq_get_affinity' filepath='include/linux/pci.h' line='1406' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_irq_get_affinity'>
+      <function-decl name='pci_irq_get_affinity' mangled-name='pci_irq_get_affinity' filepath='include/linux/pci.h' line='1407' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_irq_get_affinity'>
         <parameter type-id='85196e3f'/>
         <parameter type-id='95e97e5e'/>
         <return type-id='5f8a1ac4'/>
       </function-decl>
       <pointer-type-def type-id='6b2a4486' size-in-bits='64' id='5f8a1ac4'/>
       <pointer-type-def type-id='5c93f9a7' size-in-bits='64' id='85196e3f'/>
-      <class-decl name='pci_dev' size-in-bits='20224' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='289' column='1' id='5c93f9a7'>
+      <class-decl name='pci_dev' size-in-bits='20224' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='290' column='1' id='5c93f9a7'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='bus_list' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='290' column='1'/>
+          <var-decl name='bus_list' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='291' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='bus' type-id='d1feb554' visibility='default' filepath='include/linux/pci.h' line='291' column='1'/>
+          <var-decl name='bus' type-id='d1feb554' visibility='default' filepath='include/linux/pci.h' line='292' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='subordinate' type-id='d1feb554' visibility='default' filepath='include/linux/pci.h' line='292' column='1'/>
+          <var-decl name='subordinate' type-id='d1feb554' visibility='default' filepath='include/linux/pci.h' line='293' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='sysdata' type-id='eaa32e2f' visibility='default' filepath='include/linux/pci.h' line='294' column='1'/>
+          <var-decl name='sysdata' type-id='eaa32e2f' visibility='default' filepath='include/linux/pci.h' line='295' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='procent' type-id='d077e928' visibility='default' filepath='include/linux/pci.h' line='295' column='1'/>
+          <var-decl name='procent' type-id='d077e928' visibility='default' filepath='include/linux/pci.h' line='296' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='slot' type-id='4f146b8a' visibility='default' filepath='include/linux/pci.h' line='296' column='1'/>
+          <var-decl name='slot' type-id='4f146b8a' visibility='default' filepath='include/linux/pci.h' line='297' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='devfn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='298' column='1'/>
+          <var-decl name='devfn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='299' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='480'>
-          <var-decl name='vendor' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='299' column='1'/>
+          <var-decl name='vendor' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='300' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='496'>
-          <var-decl name='device' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='300' column='1'/>
+          <var-decl name='device' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='301' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='subsystem_vendor' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='301' column='1'/>
+          <var-decl name='subsystem_vendor' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='302' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='528'>
-          <var-decl name='subsystem_device' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='302' column='1'/>
+          <var-decl name='subsystem_device' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='303' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='544'>
-          <var-decl name='class' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='303' column='1'/>
+          <var-decl name='class' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='304' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='revision' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='304' column='1'/>
+          <var-decl name='revision' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='305' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='584'>
-          <var-decl name='hdr_type' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='305' column='1'/>
+          <var-decl name='hdr_type' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='306' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='592'>
-          <var-decl name='pcie_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='310' column='1'/>
+          <var-decl name='pcie_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='311' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='600'>
-          <var-decl name='msi_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='311' column='1'/>
+          <var-decl name='msi_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='312' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='608'>
-          <var-decl name='msix_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='312' column='1'/>
+          <var-decl name='msix_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='313' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='pcie_mpss' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='313' column='1'/>
+          <var-decl name='pcie_mpss' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='314' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='624'>
-          <var-decl name='rom_base_reg' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='314' column='1'/>
+          <var-decl name='rom_base_reg' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='315' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='632'>
-          <var-decl name='pin' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='315' column='1'/>
+          <var-decl name='pin' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='316' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='pcie_flags_reg' type-id='1dc6a898' visibility='default' filepath='include/linux/pci.h' line='316' column='1'/>
+          <var-decl name='pcie_flags_reg' type-id='1dc6a898' visibility='default' filepath='include/linux/pci.h' line='317' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='dma_alias_mask' type-id='1d2c2b85' visibility='default' filepath='include/linux/pci.h' line='317' column='1'/>
+          <var-decl name='dma_alias_mask' type-id='1d2c2b85' visibility='default' filepath='include/linux/pci.h' line='318' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='driver' type-id='85b59624' visibility='default' filepath='include/linux/pci.h' line='319' column='1'/>
+          <var-decl name='driver' type-id='85b59624' visibility='default' filepath='include/linux/pci.h' line='320' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='dma_mask' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='320' column='1'/>
+          <var-decl name='dma_mask' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='321' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='dma_parms' type-id='37251e77' visibility='default' filepath='include/linux/pci.h' line='326' column='1'/>
+          <var-decl name='dma_parms' type-id='37251e77' visibility='default' filepath='include/linux/pci.h' line='327' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='current_state' type-id='49c32219' visibility='default' filepath='include/linux/pci.h' line='328' column='1'/>
+          <var-decl name='current_state' type-id='49c32219' visibility='default' filepath='include/linux/pci.h' line='329' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1056'>
-          <var-decl name='pm_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='331' column='1'/>
+          <var-decl name='pm_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='332' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8'>
-          <var-decl name='pme_support' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='332' column='1'/>
+          <var-decl name='pme_support' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='333' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='13'>
-          <var-decl name='pme_poll' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='334' column='1'/>
+          <var-decl name='pme_poll' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='335' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='14'>
-          <var-decl name='d1_support' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='335' column='1'/>
+          <var-decl name='d1_support' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='336' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='15'>
-          <var-decl name='d2_support' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='336' column='1'/>
+          <var-decl name='d2_support' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='337' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='no_d1d2' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='337' column='1'/>
+          <var-decl name='no_d1d2' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='338' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17'>
-          <var-decl name='no_d3cold' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='338' column='1'/>
+          <var-decl name='no_d3cold' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='339' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18'>
-          <var-decl name='no_d3hot' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='339' column='1'/>
+          <var-decl name='no_d3hot' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='340' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19'>
-          <var-decl name='bridge_d3' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='340' column='1'/>
+          <var-decl name='bridge_d3' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='341' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='20'>
-          <var-decl name='d3cold_allowed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='341' column='1'/>
+          <var-decl name='d3cold_allowed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='342' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='21'>
-          <var-decl name='mmio_always_on' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='342' column='1'/>
+          <var-decl name='mmio_always_on' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='343' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='22'>
-          <var-decl name='wakeup_prepared' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='344' column='1'/>
+          <var-decl name='wakeup_prepared' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='345' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='23'>
-          <var-decl name='runtime_d3cold' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='345' column='1'/>
+          <var-decl name='runtime_d3cold' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='346' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='24'>
-          <var-decl name='ignore_hotplug' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='349' column='1'/>
+          <var-decl name='ignore_hotplug' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='350' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='25'>
-          <var-decl name='hotplug_user_indicators' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='350' column='1'/>
+          <var-decl name='hotplug_user_indicators' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='351' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='26'>
-          <var-decl name='clear_retrain_link' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='353' column='1'/>
+          <var-decl name='clear_retrain_link' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='354' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='d3_delay' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='355' column='1'/>
+          <var-decl name='d3_delay' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='356' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1120'>
-          <var-decl name='d3cold_delay' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='356' column='1'/>
+          <var-decl name='d3cold_delay' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='357' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='eetlp_prefix_path' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='363' column='1'/>
+          <var-decl name='eetlp_prefix_path' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='364' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1184'>
-          <var-decl name='error_state' type-id='7d5a17ad' visibility='default' filepath='include/linux/pci.h' line='365' column='1'/>
+          <var-decl name='error_state' type-id='7d5a17ad' visibility='default' filepath='include/linux/pci.h' line='366' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/linux/pci.h' line='366' column='1'/>
+          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/linux/pci.h' line='367' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8832'>
-          <var-decl name='cfg_size' type-id='95e97e5e' visibility='default' filepath='include/linux/pci.h' line='368' column='1'/>
+          <var-decl name='cfg_size' type-id='95e97e5e' visibility='default' filepath='include/linux/pci.h' line='369' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8864'>
-          <var-decl name='irq' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='374' column='1'/>
+          <var-decl name='irq' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='375' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8896'>
-          <var-decl name='resource' type-id='221adaf7' visibility='default' filepath='include/linux/pci.h' line='375' column='1'/>
+          <var-decl name='resource' type-id='221adaf7' visibility='default' filepath='include/linux/pci.h' line='376' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17344'>
-          <var-decl name='match_driver' type-id='b50a4934' visibility='default' filepath='include/linux/pci.h' line='377' column='1'/>
+          <var-decl name='match_driver' type-id='b50a4934' visibility='default' filepath='include/linux/pci.h' line='378' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8'>
-          <var-decl name='transparent' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='379' column='1'/>
+          <var-decl name='transparent' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='380' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9'>
-          <var-decl name='multifunction' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='380' column='1'/>
+          <var-decl name='multifunction' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='381' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10'>
-          <var-decl name='is_busmaster' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='382' column='1'/>
+          <var-decl name='is_busmaster' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='383' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='11'>
-          <var-decl name='no_msi' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='383' column='1'/>
+          <var-decl name='no_msi' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='384' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='12'>
-          <var-decl name='no_64bit_msi' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='384' column='1'/>
+          <var-decl name='no_64bit_msi' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='385' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='13'>
-          <var-decl name='block_cfg_access' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='385' column='1'/>
+          <var-decl name='block_cfg_access' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='386' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='14'>
-          <var-decl name='broken_parity_status' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='386' column='1'/>
+          <var-decl name='broken_parity_status' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='387' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='15'>
-          <var-decl name='irq_reroute_variant' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='387' column='1'/>
+          <var-decl name='irq_reroute_variant' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='388' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17'>
-          <var-decl name='msi_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='388' column='1'/>
+          <var-decl name='msi_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='389' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18'>
-          <var-decl name='msix_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='389' column='1'/>
+          <var-decl name='msix_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='390' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19'>
-          <var-decl name='ari_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='390' column='1'/>
+          <var-decl name='ari_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='391' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='20'>
-          <var-decl name='ats_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='391' column='1'/>
+          <var-decl name='ats_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='392' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='21'>
-          <var-decl name='pasid_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='392' column='1'/>
+          <var-decl name='pasid_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='393' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='22'>
-          <var-decl name='pri_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='393' column='1'/>
+          <var-decl name='pri_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='394' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='23'>
-          <var-decl name='is_managed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='394' column='1'/>
+          <var-decl name='is_managed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='395' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='24'>
-          <var-decl name='needs_freset' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='395' column='1'/>
+          <var-decl name='needs_freset' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='396' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='25'>
-          <var-decl name='state_saved' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='396' column='1'/>
+          <var-decl name='state_saved' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='397' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='26'>
-          <var-decl name='is_physfn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='397' column='1'/>
+          <var-decl name='is_physfn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='398' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='27'>
-          <var-decl name='is_virtfn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='398' column='1'/>
+          <var-decl name='is_virtfn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='399' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='28'>
-          <var-decl name='reset_fn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='399' column='1'/>
+          <var-decl name='reset_fn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='400' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='29'>
-          <var-decl name='is_hotplug_bridge' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='400' column='1'/>
+          <var-decl name='is_hotplug_bridge' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='401' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='30'>
-          <var-decl name='shpc_managed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='401' column='1'/>
+          <var-decl name='shpc_managed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='402' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='31'>
-          <var-decl name='is_thunderbolt' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='402' column='1'/>
+          <var-decl name='is_thunderbolt' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='403' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='__aer_firmware_first_valid' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='403' column='1'/>
+          <var-decl name='__aer_firmware_first_valid' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='404' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1'>
-          <var-decl name='__aer_firmware_first' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='404' column='1'/>
+          <var-decl name='__aer_firmware_first' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='405' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2'>
-          <var-decl name='broken_intx_masking' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='405' column='1'/>
+          <var-decl name='broken_intx_masking' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='406' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3'>
-          <var-decl name='io_window_1k' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='406' column='1'/>
+          <var-decl name='io_window_1k' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='407' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4'>
-          <var-decl name='irq_managed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='407' column='1'/>
+          <var-decl name='irq_managed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='408' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5'>
-          <var-decl name='has_secondary_link' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='408' column='1'/>
+          <var-decl name='has_secondary_link' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='409' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6'>
-          <var-decl name='non_compliant_bars' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='409' column='1'/>
+          <var-decl name='non_compliant_bars' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='410' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7'>
-          <var-decl name='is_probed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='410' column='1'/>
+          <var-decl name='is_probed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='411' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17392'>
-          <var-decl name='dev_flags' type-id='0f4efb07' visibility='default' filepath='include/linux/pci.h' line='411' column='1'/>
+          <var-decl name='dev_flags' type-id='0f4efb07' visibility='default' filepath='include/linux/pci.h' line='412' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17408'>
-          <var-decl name='enable_cnt' type-id='49178f86' visibility='default' filepath='include/linux/pci.h' line='412' column='1'/>
+          <var-decl name='enable_cnt' type-id='49178f86' visibility='default' filepath='include/linux/pci.h' line='413' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17440'>
-          <var-decl name='saved_config_space' type-id='02fdec64' visibility='default' filepath='include/linux/pci.h' line='414' column='1'/>
+          <var-decl name='saved_config_space' type-id='02fdec64' visibility='default' filepath='include/linux/pci.h' line='415' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17984'>
-          <var-decl name='saved_cap_space' type-id='e151255a' visibility='default' filepath='include/linux/pci.h' line='415' column='1'/>
+          <var-decl name='saved_cap_space' type-id='e151255a' visibility='default' filepath='include/linux/pci.h' line='416' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18048'>
-          <var-decl name='rom_attr' type-id='c0e2acc9' visibility='default' filepath='include/linux/pci.h' line='416' column='1'/>
+          <var-decl name='rom_attr' type-id='c0e2acc9' visibility='default' filepath='include/linux/pci.h' line='417' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18112'>
-          <var-decl name='rom_attr_enabled' type-id='95e97e5e' visibility='default' filepath='include/linux/pci.h' line='417' column='1'/>
+          <var-decl name='rom_attr_enabled' type-id='95e97e5e' visibility='default' filepath='include/linux/pci.h' line='418' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18176'>
-          <var-decl name='res_attr' type-id='2cc49b73' visibility='default' filepath='include/linux/pci.h' line='418' column='1'/>
+          <var-decl name='res_attr' type-id='2cc49b73' visibility='default' filepath='include/linux/pci.h' line='419' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18880'>
-          <var-decl name='res_attr_wc' type-id='2cc49b73' visibility='default' filepath='include/linux/pci.h' line='419' column='1'/>
+          <var-decl name='res_attr_wc' type-id='2cc49b73' visibility='default' filepath='include/linux/pci.h' line='420' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19584'>
-          <var-decl name='msi_irq_groups' type-id='c97de1ac' visibility='default' filepath='include/linux/pci.h' line='430' column='1'/>
+          <var-decl name='msi_irq_groups' type-id='c97de1ac' visibility='default' filepath='include/linux/pci.h' line='431' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19648'>
-          <var-decl name='vpd' type-id='0b72939c' visibility='default' filepath='include/linux/pci.h' line='432' column='1'/>
+          <var-decl name='vpd' type-id='0b72939c' visibility='default' filepath='include/linux/pci.h' line='433' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19712'>
-          <var-decl name='rom' type-id='2522883d' visibility='default' filepath='include/linux/pci.h' line='448' column='1'/>
+          <var-decl name='rom' type-id='2522883d' visibility='default' filepath='include/linux/pci.h' line='449' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19776'>
-          <var-decl name='romlen' type-id='b59d7dce' visibility='default' filepath='include/linux/pci.h' line='449' column='1'/>
+          <var-decl name='romlen' type-id='b59d7dce' visibility='default' filepath='include/linux/pci.h' line='450' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19840'>
-          <var-decl name='driver_override' type-id='26a90f95' visibility='default' filepath='include/linux/pci.h' line='450' column='1'/>
+          <var-decl name='driver_override' type-id='26a90f95' visibility='default' filepath='include/linux/pci.h' line='451' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19904'>
-          <var-decl name='priv_flags' type-id='7359adad' visibility='default' filepath='include/linux/pci.h' line='452' column='1'/>
+          <var-decl name='priv_flags' type-id='7359adad' visibility='default' filepath='include/linux/pci.h' line='453' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19968'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='454' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='455' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='20032'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='455' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='456' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='20096'>
-          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='456' column='1'/>
+          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='457' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='20160'>
-          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='457' column='1'/>
+          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='458' column='1'/>
         </data-member>
       </class-decl>
       <qualified-type-def type-id='1354385d' const='yes' id='6b2a4486'/>
@@ -32771,155 +32801,155 @@
       <array-type-def dimensions='1' type-id='19c2251e' size-in-bits='512' id='02fdec64'>
         <subrange length='16' type-id='7ff19f0f' id='848d0938'/>
       </array-type-def>
-      <class-decl name='pci_bus' size-in-bits='10688' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='554' column='1' id='7e8e008e'>
+      <class-decl name='pci_bus' size-in-bits='10688' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='555' column='1' id='7e8e008e'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='node' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='555' column='1'/>
+          <var-decl name='node' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='556' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='parent' type-id='d1feb554' visibility='default' filepath='include/linux/pci.h' line='556' column='1'/>
+          <var-decl name='parent' type-id='d1feb554' visibility='default' filepath='include/linux/pci.h' line='557' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='children' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='557' column='1'/>
+          <var-decl name='children' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='558' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='devices' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='558' column='1'/>
+          <var-decl name='devices' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='559' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='self' type-id='85196e3f' visibility='default' filepath='include/linux/pci.h' line='559' column='1'/>
+          <var-decl name='self' type-id='85196e3f' visibility='default' filepath='include/linux/pci.h' line='560' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='slots' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='560' column='1'/>
+          <var-decl name='slots' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='561' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='resource' type-id='774e8b2d' visibility='default' filepath='include/linux/pci.h' line='562' column='1'/>
+          <var-decl name='resource' type-id='774e8b2d' visibility='default' filepath='include/linux/pci.h' line='563' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='resources' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='563' column='1'/>
+          <var-decl name='resources' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='564' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='busn_res' type-id='5218160d' visibility='default' filepath='include/linux/pci.h' line='564' column='1'/>
+          <var-decl name='busn_res' type-id='5218160d' visibility='default' filepath='include/linux/pci.h' line='565' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1792'>
-          <var-decl name='ops' type-id='2058826a' visibility='default' filepath='include/linux/pci.h' line='566' column='1'/>
+          <var-decl name='ops' type-id='2058826a' visibility='default' filepath='include/linux/pci.h' line='567' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='msi' type-id='b9526cc1' visibility='default' filepath='include/linux/pci.h' line='567' column='1'/>
+          <var-decl name='msi' type-id='b9526cc1' visibility='default' filepath='include/linux/pci.h' line='568' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1920'>
-          <var-decl name='sysdata' type-id='eaa32e2f' visibility='default' filepath='include/linux/pci.h' line='568' column='1'/>
+          <var-decl name='sysdata' type-id='eaa32e2f' visibility='default' filepath='include/linux/pci.h' line='569' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1984'>
-          <var-decl name='procdir' type-id='d077e928' visibility='default' filepath='include/linux/pci.h' line='569' column='1'/>
+          <var-decl name='procdir' type-id='d077e928' visibility='default' filepath='include/linux/pci.h' line='570' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='number' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='571' column='1'/>
+          <var-decl name='number' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='572' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2056'>
-          <var-decl name='primary' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='572' column='1'/>
+          <var-decl name='primary' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='573' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2064'>
-          <var-decl name='max_bus_speed' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='573' column='1'/>
+          <var-decl name='max_bus_speed' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='574' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2072'>
-          <var-decl name='cur_bus_speed' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='574' column='1'/>
+          <var-decl name='cur_bus_speed' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='575' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2080'>
-          <var-decl name='domain_nr' type-id='95e97e5e' visibility='default' filepath='include/linux/pci.h' line='576' column='1'/>
+          <var-decl name='domain_nr' type-id='95e97e5e' visibility='default' filepath='include/linux/pci.h' line='577' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='name' type-id='36d7f119' visibility='default' filepath='include/linux/pci.h' line='579' column='1'/>
+          <var-decl name='name' type-id='36d7f119' visibility='default' filepath='include/linux/pci.h' line='580' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2496'>
-          <var-decl name='bridge_ctl' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='581' column='1'/>
+          <var-decl name='bridge_ctl' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='582' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2512'>
-          <var-decl name='bus_flags' type-id='757fc982' visibility='default' filepath='include/linux/pci.h' line='582' column='1'/>
+          <var-decl name='bus_flags' type-id='757fc982' visibility='default' filepath='include/linux/pci.h' line='583' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2560'>
-          <var-decl name='bridge' type-id='fa0b179b' visibility='default' filepath='include/linux/pci.h' line='583' column='1'/>
+          <var-decl name='bridge' type-id='fa0b179b' visibility='default' filepath='include/linux/pci.h' line='584' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2624'>
-          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/linux/pci.h' line='584' column='1'/>
+          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/linux/pci.h' line='585' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10240'>
-          <var-decl name='legacy_io' type-id='c0e2acc9' visibility='default' filepath='include/linux/pci.h' line='585' column='1'/>
+          <var-decl name='legacy_io' type-id='c0e2acc9' visibility='default' filepath='include/linux/pci.h' line='586' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10304'>
-          <var-decl name='legacy_mem' type-id='c0e2acc9' visibility='default' filepath='include/linux/pci.h' line='586' column='1'/>
+          <var-decl name='legacy_mem' type-id='c0e2acc9' visibility='default' filepath='include/linux/pci.h' line='587' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='is_added' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='587' column='1'/>
+          <var-decl name='is_added' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='588' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10432'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='589' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='590' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10496'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='590' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='591' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10560'>
-          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='591' column='1'/>
+          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='592' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10624'>
-          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='592' column='1'/>
+          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='593' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='pci_driver' size-in-bits='2688' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='768' column='1' id='314e713e'>
+      <class-decl name='pci_driver' size-in-bits='2688' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='769' column='1' id='314e713e'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='node' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='769' column='1'/>
+          <var-decl name='node' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='770' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='name' type-id='80f4b756' visibility='default' filepath='include/linux/pci.h' line='770' column='1'/>
+          <var-decl name='name' type-id='80f4b756' visibility='default' filepath='include/linux/pci.h' line='771' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='id_table' type-id='92fc8aa5' visibility='default' filepath='include/linux/pci.h' line='771' column='1'/>
+          <var-decl name='id_table' type-id='92fc8aa5' visibility='default' filepath='include/linux/pci.h' line='772' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='probe' type-id='6cc3a8b3' visibility='default' filepath='include/linux/pci.h' line='772' column='1'/>
+          <var-decl name='probe' type-id='6cc3a8b3' visibility='default' filepath='include/linux/pci.h' line='773' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='remove' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='773' column='1'/>
+          <var-decl name='remove' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='774' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='suspend' type-id='831f84c2' visibility='default' filepath='include/linux/pci.h' line='774' column='1'/>
+          <var-decl name='suspend' type-id='831f84c2' visibility='default' filepath='include/linux/pci.h' line='775' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='suspend_late' type-id='831f84c2' visibility='default' filepath='include/linux/pci.h' line='775' column='1'/>
+          <var-decl name='suspend_late' type-id='831f84c2' visibility='default' filepath='include/linux/pci.h' line='776' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='resume_early' type-id='40672f7b' visibility='default' filepath='include/linux/pci.h' line='776' column='1'/>
+          <var-decl name='resume_early' type-id='40672f7b' visibility='default' filepath='include/linux/pci.h' line='777' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='resume' type-id='40672f7b' visibility='default' filepath='include/linux/pci.h' line='777' column='1'/>
+          <var-decl name='resume' type-id='40672f7b' visibility='default' filepath='include/linux/pci.h' line='778' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='shutdown' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='778' column='1'/>
+          <var-decl name='shutdown' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='779' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='sriov_configure' type-id='ab05e282' visibility='default' filepath='include/linux/pci.h' line='779' column='1'/>
+          <var-decl name='sriov_configure' type-id='ab05e282' visibility='default' filepath='include/linux/pci.h' line='780' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='err_handler' type-id='2da88de7' visibility='default' filepath='include/linux/pci.h' line='780' column='1'/>
+          <var-decl name='err_handler' type-id='2da88de7' visibility='default' filepath='include/linux/pci.h' line='781' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='groups' type-id='c97de1ac' visibility='default' filepath='include/linux/pci.h' line='781' column='1'/>
+          <var-decl name='groups' type-id='c97de1ac' visibility='default' filepath='include/linux/pci.h' line='782' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='driver' type-id='fe007c02' visibility='default' filepath='include/linux/pci.h' line='782' column='1'/>
+          <var-decl name='driver' type-id='fe007c02' visibility='default' filepath='include/linux/pci.h' line='783' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2240'>
-          <var-decl name='dynids' type-id='022719b7' visibility='default' filepath='include/linux/pci.h' line='783' column='1'/>
+          <var-decl name='dynids' type-id='022719b7' visibility='default' filepath='include/linux/pci.h' line='784' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2432'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='785' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='786' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2496'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='786' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='787' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2560'>
-          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='787' column='1'/>
+          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='788' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2624'>
-          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='788' column='1'/>
+          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='789' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='pci_slot' size-in-bits='1088' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='57' column='1' id='cce0f0cc'>
@@ -32940,12 +32970,12 @@
         </data-member>
       </class-decl>
       <class-decl name='pci_vpd' is-struct='yes' visibility='default' is-declaration-only='yes' id='059a2256'/>
-      <class-decl name='pci_dynids' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='711' column='1' id='022719b7'>
+      <class-decl name='pci_dynids' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='712' column='1' id='022719b7'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='lock' type-id='fb4018a0' visibility='default' filepath='include/linux/pci.h' line='712' column='1'/>
+          <var-decl name='lock' type-id='fb4018a0' visibility='default' filepath='include/linux/pci.h' line='713' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='713' column='1'/>
+          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='714' column='1'/>
         </data-member>
       </class-decl>
       <pointer-type-def type-id='b947c5cd' size-in-bits='64' id='92fc8aa5'/>
@@ -33002,21 +33032,21 @@
           <var-decl name='teardown_irq' type-id='694b6f36' visibility='default' filepath='include/linux/msi.h' line='199' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='pci_ops' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='683' column='1' id='fc2007cc'>
+      <class-decl name='pci_ops' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='684' column='1' id='fc2007cc'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='add_bus' type-id='4a1c3304' visibility='default' filepath='include/linux/pci.h' line='684' column='1'/>
+          <var-decl name='add_bus' type-id='4a1c3304' visibility='default' filepath='include/linux/pci.h' line='685' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='remove_bus' type-id='7df445b9' visibility='default' filepath='include/linux/pci.h' line='685' column='1'/>
+          <var-decl name='remove_bus' type-id='7df445b9' visibility='default' filepath='include/linux/pci.h' line='686' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='map_bus' type-id='d479d76a' visibility='default' filepath='include/linux/pci.h' line='686' column='1'/>
+          <var-decl name='map_bus' type-id='d479d76a' visibility='default' filepath='include/linux/pci.h' line='687' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='read' type-id='ffde3570' visibility='default' filepath='include/linux/pci.h' line='687' column='1'/>
+          <var-decl name='read' type-id='ffde3570' visibility='default' filepath='include/linux/pci.h' line='688' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='write' type-id='934d23eb' visibility='default' filepath='include/linux/pci.h' line='688' column='1'/>
+          <var-decl name='write' type-id='934d23eb' visibility='default' filepath='include/linux/pci.h' line='689' column='1'/>
         </data-member>
       </class-decl>
       <qualified-type-def type-id='6cb59de2' const='yes' id='b947c5cd'/>
@@ -33044,24 +33074,24 @@
           <var-decl name='driver_data' type-id='0791d6c8' visibility='default' filepath='include/linux/mod_devicetable.h' line='23' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='pci_error_handlers' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='747' column='1' id='709bf5ba'>
+      <class-decl name='pci_error_handlers' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='748' column='1' id='709bf5ba'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='error_detected' type-id='abc80f30' visibility='default' filepath='include/linux/pci.h' line='749' column='1'/>
+          <var-decl name='error_detected' type-id='abc80f30' visibility='default' filepath='include/linux/pci.h' line='750' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='mmio_enabled' type-id='80b73a7b' visibility='default' filepath='include/linux/pci.h' line='753' column='1'/>
+          <var-decl name='mmio_enabled' type-id='80b73a7b' visibility='default' filepath='include/linux/pci.h' line='754' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='slot_reset' type-id='80b73a7b' visibility='default' filepath='include/linux/pci.h' line='756' column='1'/>
+          <var-decl name='slot_reset' type-id='80b73a7b' visibility='default' filepath='include/linux/pci.h' line='757' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='reset_prepare' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='759' column='1'/>
+          <var-decl name='reset_prepare' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='760' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='reset_done' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='760' column='1'/>
+          <var-decl name='reset_done' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='761' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='resume' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='763' column='1'/>
+          <var-decl name='resume' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='764' column='1'/>
         </data-member>
       </class-decl>
       <pointer-type-def type-id='df8b174a' size-in-bits='64' id='c14deb08'/>
@@ -33566,7 +33596,7 @@
         <parameter type-id='08c8d0fa'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='cancel_work_sync' mangled-name='cancel_work_sync' filepath='include/linux/workqueue.h' line='486' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='cancel_work_sync'>
+      <function-decl name='cancel_work_sync' mangled-name='cancel_work_sync' filepath='include/linux/workqueue.h' line='487' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='cancel_work_sync'>
         <parameter type-id='83c1bde6'/>
         <return type-id='c894953d'/>
       </function-decl>
@@ -34303,7 +34333,23 @@
           <var-decl name='buckets' type-id='bde3078a' visibility='default' filepath='include/linux/rhashtable.h' line='75' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cpu_rmap' is-struct='yes' visibility='default' is-declaration-only='yes' id='e09a048e'/>
+      <class-decl name='cpu_rmap' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/linux/cpu_rmap.h' line='27' column='1' id='e09a048e'>
+        <data-member access='public' layout-offset-in-bits='0'>
+          <var-decl name='refcount' type-id='400fb07b' visibility='default' filepath='include/linux/cpu_rmap.h' line='28' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='32'>
+          <var-decl name='size' type-id='1dc6a898' visibility='default' filepath='include/linux/cpu_rmap.h' line='29' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='48'>
+          <var-decl name='used' type-id='1dc6a898' visibility='default' filepath='include/linux/cpu_rmap.h' line='29' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='64'>
+          <var-decl name='obj' type-id='63e171df' visibility='default' filepath='include/linux/cpu_rmap.h' line='30' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='128'>
+          <var-decl name='near' type-id='f443352a' visibility='default' filepath='include/linux/cpu_rmap.h' line='34' column='1'/>
+        </data-member>
+      </class-decl>
       <class-decl name='dst_entry' size-in-bits='896' is-struct='yes' visibility='default' filepath='include/net/dst.h' line='35' column='1' id='772a4ddf'>
         <data-member access='public' layout-offset-in-bits='0'>
           <var-decl name='dev' type-id='68a2d05b' visibility='default' filepath='include/net/dst.h' line='36' column='1'/>
@@ -34790,18 +34836,18 @@
           <var-decl name='total' type-id='95e97e5e' visibility='default' filepath='include/net/inetpeer.h' line='64' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='ip_ra_chain' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/ip.h' line='123' column='1' id='4816a146'>
+      <class-decl name='ip_ra_chain' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/ip.h' line='125' column='1' id='4816a146'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='next' type-id='00c4cbac' visibility='default' filepath='include/net/ip.h' line='124' column='1'/>
+          <var-decl name='next' type-id='00c4cbac' visibility='default' filepath='include/net/ip.h' line='126' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='sk' type-id='f772df6d' visibility='default' filepath='include/net/ip.h' line='125' column='1'/>
+          <var-decl name='sk' type-id='f772df6d' visibility='default' filepath='include/net/ip.h' line='127' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='' type-id='4fa91678' visibility='default' filepath='include/net/ip.h' line='126' column='1'/>
+          <var-decl name='' type-id='4fa91678' visibility='default' filepath='include/net/ip.h' line='128' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/net/ip.h' line='130' column='1'/>
+          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/net/ip.h' line='132' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='ipc_namespace' is-struct='yes' visibility='default' is-declaration-only='yes' id='dd74f3ed'/>
@@ -35499,71 +35545,71 @@
         </data-member>
       </class-decl>
       <class-decl name='sfp_bus' is-struct='yes' visibility='default' is-declaration-only='yes' id='cc52ca8d'/>
-      <class-decl name='tcp_congestion_ops' size-in-bits='1216' is-struct='yes' visibility='default' filepath='include/net/tcp.h' line='1018' column='1' id='54718f09'>
+      <class-decl name='tcp_congestion_ops' size-in-bits='1216' is-struct='yes' visibility='default' filepath='include/net/tcp.h' line='1023' column='1' id='54718f09'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/net/tcp.h' line='1019' column='1'/>
+          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/net/tcp.h' line='1024' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='key' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1020' column='1'/>
+          <var-decl name='key' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1025' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1021' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1026' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='init' type-id='841969d0' visibility='default' filepath='include/net/tcp.h' line='1024' column='1'/>
+          <var-decl name='init' type-id='841969d0' visibility='default' filepath='include/net/tcp.h' line='1029' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='release' type-id='841969d0' visibility='default' filepath='include/net/tcp.h' line='1026' column='1'/>
+          <var-decl name='release' type-id='841969d0' visibility='default' filepath='include/net/tcp.h' line='1031' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='ssthresh' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1029' column='1'/>
+          <var-decl name='ssthresh' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1034' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='cong_avoid' type-id='ece3af1e' visibility='default' filepath='include/net/tcp.h' line='1031' column='1'/>
+          <var-decl name='cong_avoid' type-id='ece3af1e' visibility='default' filepath='include/net/tcp.h' line='1036' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='set_state' type-id='f5feb7a4' visibility='default' filepath='include/net/tcp.h' line='1033' column='1'/>
+          <var-decl name='set_state' type-id='f5feb7a4' visibility='default' filepath='include/net/tcp.h' line='1038' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='cwnd_event' type-id='bfacbc7a' visibility='default' filepath='include/net/tcp.h' line='1035' column='1'/>
+          <var-decl name='cwnd_event' type-id='bfacbc7a' visibility='default' filepath='include/net/tcp.h' line='1040' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='in_ack_event' type-id='815f64bf' visibility='default' filepath='include/net/tcp.h' line='1037' column='1'/>
+          <var-decl name='in_ack_event' type-id='815f64bf' visibility='default' filepath='include/net/tcp.h' line='1042' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='undo_cwnd' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1039' column='1'/>
+          <var-decl name='undo_cwnd' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1044' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='pkts_acked' type-id='bffb5883' visibility='default' filepath='include/net/tcp.h' line='1041' column='1'/>
+          <var-decl name='pkts_acked' type-id='bffb5883' visibility='default' filepath='include/net/tcp.h' line='1046' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='min_tso_segs' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1043' column='1'/>
+          <var-decl name='min_tso_segs' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1048' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='sndbuf_expand' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1045' column='1'/>
+          <var-decl name='sndbuf_expand' type-id='8af06487' visibility='default' filepath='include/net/tcp.h' line='1050' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='cong_control' type-id='636d3a20' visibility='default' filepath='include/net/tcp.h' line='1049' column='1'/>
+          <var-decl name='cong_control' type-id='636d3a20' visibility='default' filepath='include/net/tcp.h' line='1054' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='get_info' type-id='14ca5c08' visibility='default' filepath='include/net/tcp.h' line='1051' column='1'/>
+          <var-decl name='get_info' type-id='14ca5c08' visibility='default' filepath='include/net/tcp.h' line='1056' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='name' type-id='ac1fa8c0' visibility='default' filepath='include/net/tcp.h' line='1054' column='1'/>
+          <var-decl name='name' type-id='ac1fa8c0' visibility='default' filepath='include/net/tcp.h' line='1059' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='owner' type-id='2730d015' visibility='default' filepath='include/net/tcp.h' line='1055' column='1'/>
+          <var-decl name='owner' type-id='2730d015' visibility='default' filepath='include/net/tcp.h' line='1060' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='tcp_fastopen_context' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/tcp.h' line='1634' column='1' id='f77d4717'>
+      <class-decl name='tcp_fastopen_context' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/tcp.h' line='1639' column='1' id='f77d4717'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='tfm' type-id='75f72758' visibility='default' filepath='include/net/tcp.h' line='1635' column='1'/>
+          <var-decl name='tfm' type-id='75f72758' visibility='default' filepath='include/net/tcp.h' line='1640' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='key' type-id='9396cabb' visibility='default' filepath='include/net/tcp.h' line='1636' column='1'/>
+          <var-decl name='key' type-id='9396cabb' visibility='default' filepath='include/net/tcp.h' line='1641' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/net/tcp.h' line='1637' column='1'/>
+          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/net/tcp.h' line='1642' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='tipc_bearer' is-struct='yes' visibility='default' is-declaration-only='yes' id='10ec1ded'/>
@@ -35730,120 +35776,120 @@
           <var-decl name='ns' type-id='99f367f2' visibility='default' filepath='include/linux/utsname.h' line='29' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wireless_dev' size-in-bits='3008' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='4500' column='1' id='3ce3a3e9'>
+      <class-decl name='wireless_dev' size-in-bits='3008' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='4503' column='1' id='3ce3a3e9'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='wiphy' type-id='666fb412' visibility='default' filepath='include/net/cfg80211.h' line='4501' column='1'/>
+          <var-decl name='wiphy' type-id='666fb412' visibility='default' filepath='include/net/cfg80211.h' line='4504' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='iftype' type-id='86505f90' visibility='default' filepath='include/net/cfg80211.h' line='4502' column='1'/>
+          <var-decl name='iftype' type-id='86505f90' visibility='default' filepath='include/net/cfg80211.h' line='4505' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4505' column='1'/>
+          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4508' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='netdev' type-id='68a2d05b' visibility='default' filepath='include/net/cfg80211.h' line='4506' column='1'/>
+          <var-decl name='netdev' type-id='68a2d05b' visibility='default' filepath='include/net/cfg80211.h' line='4509' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='identifier' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4508' column='1'/>
+          <var-decl name='identifier' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4511' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='mgmt_registrations' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4510' column='1'/>
+          <var-decl name='mgmt_registrations' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4513' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='mgmt_registrations_lock' type-id='fb4018a0' visibility='default' filepath='include/net/cfg80211.h' line='4511' column='1'/>
+          <var-decl name='mgmt_registrations_lock' type-id='fb4018a0' visibility='default' filepath='include/net/cfg80211.h' line='4514' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='mtx' type-id='925167dc' visibility='default' filepath='include/net/cfg80211.h' line='4513' column='1'/>
+          <var-decl name='mtx' type-id='925167dc' visibility='default' filepath='include/net/cfg80211.h' line='4516' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='use_4addr' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4515' column='1'/>
+          <var-decl name='use_4addr' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4518' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='840'>
-          <var-decl name='is_running' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4515' column='1'/>
+          <var-decl name='is_running' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4518' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='848'>
-          <var-decl name='address' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4517' column='1'/>
+          <var-decl name='address' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4520' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='ssid' type-id='e3dc4fdb' visibility='default' filepath='include/net/cfg80211.h' line='4520' column='1'/>
+          <var-decl name='ssid' type-id='e3dc4fdb' visibility='default' filepath='include/net/cfg80211.h' line='4523' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='ssid_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4521' column='1'/>
+          <var-decl name='ssid_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4524' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1160'>
-          <var-decl name='mesh_id_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4521' column='1'/>
+          <var-decl name='mesh_id_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4524' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1168'>
-          <var-decl name='mesh_id_up_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4521' column='1'/>
+          <var-decl name='mesh_id_up_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4524' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='conn' type-id='6dbc8e18' visibility='default' filepath='include/net/cfg80211.h' line='4522' column='1'/>
+          <var-decl name='conn' type-id='6dbc8e18' visibility='default' filepath='include/net/cfg80211.h' line='4525' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='connect_keys' type-id='561a36db' visibility='default' filepath='include/net/cfg80211.h' line='4523' column='1'/>
+          <var-decl name='connect_keys' type-id='561a36db' visibility='default' filepath='include/net/cfg80211.h' line='4526' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='conn_bss_type' type-id='cb952348' visibility='default' filepath='include/net/cfg80211.h' line='4524' column='1'/>
+          <var-decl name='conn_bss_type' type-id='cb952348' visibility='default' filepath='include/net/cfg80211.h' line='4527' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1376'>
-          <var-decl name='conn_owner_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4525' column='1'/>
+          <var-decl name='conn_owner_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4528' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='disconnect_wk' type-id='ef9025d0' visibility='default' filepath='include/net/cfg80211.h' line='4527' column='1'/>
+          <var-decl name='disconnect_wk' type-id='ef9025d0' visibility='default' filepath='include/net/cfg80211.h' line='4530' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1792'>
-          <var-decl name='disconnect_bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4528' column='1'/>
+          <var-decl name='disconnect_bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4531' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='event_list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4530' column='1'/>
+          <var-decl name='event_list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4533' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1984'>
-          <var-decl name='event_lock' type-id='fb4018a0' visibility='default' filepath='include/net/cfg80211.h' line='4531' column='1'/>
+          <var-decl name='event_lock' type-id='fb4018a0' visibility='default' filepath='include/net/cfg80211.h' line='4534' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='current_bss' type-id='1819dec8' visibility='default' filepath='include/net/cfg80211.h' line='4533' column='1'/>
+          <var-decl name='current_bss' type-id='1819dec8' visibility='default' filepath='include/net/cfg80211.h' line='4536' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='preset_chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='4534' column='1'/>
+          <var-decl name='preset_chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='4537' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2368'>
-          <var-decl name='chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='4535' column='1'/>
+          <var-decl name='chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='4538' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2624'>
-          <var-decl name='ibss_fixed' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4537' column='1'/>
+          <var-decl name='ibss_fixed' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4540' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2632'>
-          <var-decl name='ibss_dfs_possible' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4538' column='1'/>
+          <var-decl name='ibss_dfs_possible' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4541' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2640'>
-          <var-decl name='ps' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4540' column='1'/>
+          <var-decl name='ps' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4543' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2656'>
-          <var-decl name='ps_timeout' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4541' column='1'/>
+          <var-decl name='ps_timeout' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4544' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2688'>
-          <var-decl name='beacon_interval' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4543' column='1'/>
+          <var-decl name='beacon_interval' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4546' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2720'>
-          <var-decl name='ap_unexpected_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4545' column='1'/>
+          <var-decl name='ap_unexpected_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4548' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2752'>
-          <var-decl name='owner_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4547' column='1'/>
+          <var-decl name='owner_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4550' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2784'>
-          <var-decl name='nl_owner_dead' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4548' column='1'/>
+          <var-decl name='nl_owner_dead' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4551' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2792'>
-          <var-decl name='cac_started' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4550' column='1'/>
+          <var-decl name='cac_started' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4553' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2816'>
-          <var-decl name='cac_start_time' type-id='7359adad' visibility='default' filepath='include/net/cfg80211.h' line='4551' column='1'/>
+          <var-decl name='cac_start_time' type-id='7359adad' visibility='default' filepath='include/net/cfg80211.h' line='4554' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2880'>
-          <var-decl name='cac_time_ms' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='4552' column='1'/>
+          <var-decl name='cac_time_ms' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='4555' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2944'>
-          <var-decl name='cqm_config' type-id='ee527710' visibility='default' filepath='include/net/cfg80211.h' line='4569' column='1'/>
+          <var-decl name='cqm_config' type-id='ee527710' visibility='default' filepath='include/net/cfg80211.h' line='4572' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='wpan_dev' is-struct='yes' visibility='default' is-declaration-only='yes' id='8ae2fb1d'/>
@@ -36116,421 +36162,421 @@
           <var-decl name='fnhe_genid' type-id='49178f86' visibility='default' filepath='include/net/net_namespace.h' line='161' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='net_device' size-in-bits='19456' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='1786' column='1' id='5a9929eb'>
+      <class-decl name='net_device' size-in-bits='19456' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='1788' column='1' id='5a9929eb'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='name' type-id='ac1fa8c0' visibility='default' filepath='include/linux/netdevice.h' line='1787' column='1'/>
+          <var-decl name='name' type-id='ac1fa8c0' visibility='default' filepath='include/linux/netdevice.h' line='1789' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='name_hlist' type-id='03a4a074' visibility='default' filepath='include/linux/netdevice.h' line='1788' column='1'/>
+          <var-decl name='name_hlist' type-id='03a4a074' visibility='default' filepath='include/linux/netdevice.h' line='1790' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ifalias' type-id='d81cf24c' visibility='default' filepath='include/linux/netdevice.h' line='1789' column='1'/>
+          <var-decl name='ifalias' type-id='d81cf24c' visibility='default' filepath='include/linux/netdevice.h' line='1791' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='mem_end' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1794' column='1'/>
+          <var-decl name='mem_end' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1796' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='mem_start' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1795' column='1'/>
+          <var-decl name='mem_start' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1797' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='base_addr' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1796' column='1'/>
+          <var-decl name='base_addr' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1798' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='irq' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1797' column='1'/>
+          <var-decl name='irq' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1799' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='state' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1805' column='1'/>
+          <var-decl name='state' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1807' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='dev_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1807' column='1'/>
+          <var-decl name='dev_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1809' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='napi_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1808' column='1'/>
+          <var-decl name='napi_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1810' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='unreg_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1809' column='1'/>
+          <var-decl name='unreg_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1811' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='close_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1810' column='1'/>
+          <var-decl name='close_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1812' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='ptype_all' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1811' column='1'/>
+          <var-decl name='ptype_all' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1813' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='ptype_specific' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1812' column='1'/>
+          <var-decl name='ptype_specific' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1814' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='adj_list' type-id='19245258' visibility='default' filepath='include/linux/netdevice.h' line='1817' column='1'/>
+          <var-decl name='adj_list' type-id='19245258' visibility='default' filepath='include/linux/netdevice.h' line='1819' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1664'>
-          <var-decl name='features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1819' column='1'/>
+          <var-decl name='features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1821' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1728'>
-          <var-decl name='hw_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1820' column='1'/>
+          <var-decl name='hw_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1822' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1792'>
-          <var-decl name='wanted_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1821' column='1'/>
+          <var-decl name='wanted_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1823' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='vlan_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1822' column='1'/>
+          <var-decl name='vlan_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1824' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1920'>
-          <var-decl name='hw_enc_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1823' column='1'/>
+          <var-decl name='hw_enc_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1825' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1984'>
-          <var-decl name='mpls_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1824' column='1'/>
+          <var-decl name='mpls_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1826' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='gso_partial_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1825' column='1'/>
+          <var-decl name='gso_partial_features' type-id='f9f4b16f' visibility='default' filepath='include/linux/netdevice.h' line='1827' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='ifindex' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1827' column='1'/>
+          <var-decl name='ifindex' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1829' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2144'>
-          <var-decl name='group' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1828' column='1'/>
+          <var-decl name='group' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1830' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2176'>
-          <var-decl name='stats' type-id='a3566137' visibility='default' filepath='include/linux/netdevice.h' line='1830' column='1'/>
+          <var-decl name='stats' type-id='a3566137' visibility='default' filepath='include/linux/netdevice.h' line='1832' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3648'>
-          <var-decl name='rx_dropped' type-id='f22a8abb' visibility='default' filepath='include/linux/netdevice.h' line='1832' column='1'/>
+          <var-decl name='rx_dropped' type-id='f22a8abb' visibility='default' filepath='include/linux/netdevice.h' line='1834' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3712'>
-          <var-decl name='tx_dropped' type-id='f22a8abb' visibility='default' filepath='include/linux/netdevice.h' line='1833' column='1'/>
+          <var-decl name='tx_dropped' type-id='f22a8abb' visibility='default' filepath='include/linux/netdevice.h' line='1835' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3776'>
-          <var-decl name='rx_nohandler' type-id='f22a8abb' visibility='default' filepath='include/linux/netdevice.h' line='1834' column='1'/>
+          <var-decl name='rx_nohandler' type-id='f22a8abb' visibility='default' filepath='include/linux/netdevice.h' line='1836' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3840'>
-          <var-decl name='carrier_up_count' type-id='49178f86' visibility='default' filepath='include/linux/netdevice.h' line='1837' column='1'/>
+          <var-decl name='carrier_up_count' type-id='49178f86' visibility='default' filepath='include/linux/netdevice.h' line='1839' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3872'>
-          <var-decl name='carrier_down_count' type-id='49178f86' visibility='default' filepath='include/linux/netdevice.h' line='1838' column='1'/>
+          <var-decl name='carrier_down_count' type-id='49178f86' visibility='default' filepath='include/linux/netdevice.h' line='1840' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3904'>
-          <var-decl name='wireless_handlers' type-id='3e2bb973' visibility='default' filepath='include/linux/netdevice.h' line='1841' column='1'/>
+          <var-decl name='wireless_handlers' type-id='3e2bb973' visibility='default' filepath='include/linux/netdevice.h' line='1843' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3968'>
-          <var-decl name='wireless_data' type-id='e40f7bda' visibility='default' filepath='include/linux/netdevice.h' line='1842' column='1'/>
+          <var-decl name='wireless_data' type-id='e40f7bda' visibility='default' filepath='include/linux/netdevice.h' line='1844' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4032'>
-          <var-decl name='netdev_ops' type-id='a84ec761' visibility='default' filepath='include/linux/netdevice.h' line='1844' column='1'/>
+          <var-decl name='netdev_ops' type-id='a84ec761' visibility='default' filepath='include/linux/netdevice.h' line='1846' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4096'>
-          <var-decl name='ethtool_ops' type-id='bdf901f8' visibility='default' filepath='include/linux/netdevice.h' line='1845' column='1'/>
+          <var-decl name='ethtool_ops' type-id='bdf901f8' visibility='default' filepath='include/linux/netdevice.h' line='1847' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4160'>
-          <var-decl name='ndisc_ops' type-id='a2e418a6' visibility='default' filepath='include/linux/netdevice.h' line='1853' column='1'/>
+          <var-decl name='ndisc_ops' type-id='a2e418a6' visibility='default' filepath='include/linux/netdevice.h' line='1855' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4224'>
-          <var-decl name='header_ops' type-id='2d747e78' visibility='default' filepath='include/linux/netdevice.h' line='1864' column='1'/>
+          <var-decl name='header_ops' type-id='2d747e78' visibility='default' filepath='include/linux/netdevice.h' line='1866' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4288'>
-          <var-decl name='flags' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1866' column='1'/>
+          <var-decl name='flags' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1868' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4320'>
-          <var-decl name='priv_flags' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1867' column='1'/>
+          <var-decl name='priv_flags' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1869' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4352'>
-          <var-decl name='gflags' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1869' column='1'/>
+          <var-decl name='gflags' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1871' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4368'>
-          <var-decl name='padded' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1870' column='1'/>
+          <var-decl name='padded' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1872' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4384'>
-          <var-decl name='operstate' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1872' column='1'/>
+          <var-decl name='operstate' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1874' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4392'>
-          <var-decl name='link_mode' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1873' column='1'/>
+          <var-decl name='link_mode' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1875' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4400'>
-          <var-decl name='if_port' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1875' column='1'/>
+          <var-decl name='if_port' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1877' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4408'>
-          <var-decl name='dma' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1876' column='1'/>
+          <var-decl name='dma' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1878' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4416'>
-          <var-decl name='mtu' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1883' column='1'/>
+          <var-decl name='mtu' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1885' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4448'>
-          <var-decl name='min_mtu' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1884' column='1'/>
+          <var-decl name='min_mtu' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1886' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4480'>
-          <var-decl name='max_mtu' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1885' column='1'/>
+          <var-decl name='max_mtu' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1887' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4512'>
-          <var-decl name='type' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1886' column='1'/>
+          <var-decl name='type' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1888' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4528'>
-          <var-decl name='hard_header_len' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1887' column='1'/>
+          <var-decl name='hard_header_len' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1889' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4544'>
-          <var-decl name='min_header_len' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1888' column='1'/>
+          <var-decl name='min_header_len' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1890' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4560'>
-          <var-decl name='needed_headroom' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1890' column='1'/>
+          <var-decl name='needed_headroom' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1892' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4576'>
-          <var-decl name='needed_tailroom' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1891' column='1'/>
+          <var-decl name='needed_tailroom' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1893' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4592'>
-          <var-decl name='perm_addr' type-id='fc872715' visibility='default' filepath='include/linux/netdevice.h' line='1894' column='1'/>
+          <var-decl name='perm_addr' type-id='fc872715' visibility='default' filepath='include/linux/netdevice.h' line='1896' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4848'>
-          <var-decl name='addr_assign_type' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1895' column='1'/>
+          <var-decl name='addr_assign_type' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1897' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4856'>
-          <var-decl name='addr_len' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1896' column='1'/>
+          <var-decl name='addr_len' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1898' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4864'>
-          <var-decl name='upper_level' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1897' column='1'/>
+          <var-decl name='upper_level' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1899' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4872'>
-          <var-decl name='lower_level' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1898' column='1'/>
+          <var-decl name='lower_level' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1900' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4880'>
-          <var-decl name='neigh_priv_len' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1899' column='1'/>
+          <var-decl name='neigh_priv_len' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1901' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4896'>
-          <var-decl name='dev_id' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1900' column='1'/>
+          <var-decl name='dev_id' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1902' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4912'>
-          <var-decl name='dev_port' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1901' column='1'/>
+          <var-decl name='dev_port' type-id='8efea9e5' visibility='default' filepath='include/linux/netdevice.h' line='1903' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4928'>
-          <var-decl name='addr_list_lock' type-id='fb4018a0' visibility='default' filepath='include/linux/netdevice.h' line='1902' column='1'/>
+          <var-decl name='addr_list_lock' type-id='fb4018a0' visibility='default' filepath='include/linux/netdevice.h' line='1904' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4960'>
-          <var-decl name='name_assign_type' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1903' column='1'/>
+          <var-decl name='name_assign_type' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='1905' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4968'>
-          <var-decl name='uc_promisc' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='1904' column='1'/>
+          <var-decl name='uc_promisc' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='1906' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4992'>
-          <var-decl name='uc' type-id='44a1ec32' visibility='default' filepath='include/linux/netdevice.h' line='1905' column='1'/>
+          <var-decl name='uc' type-id='44a1ec32' visibility='default' filepath='include/linux/netdevice.h' line='1907' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5184'>
-          <var-decl name='mc' type-id='44a1ec32' visibility='default' filepath='include/linux/netdevice.h' line='1906' column='1'/>
+          <var-decl name='mc' type-id='44a1ec32' visibility='default' filepath='include/linux/netdevice.h' line='1908' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5376'>
-          <var-decl name='dev_addrs' type-id='44a1ec32' visibility='default' filepath='include/linux/netdevice.h' line='1907' column='1'/>
+          <var-decl name='dev_addrs' type-id='44a1ec32' visibility='default' filepath='include/linux/netdevice.h' line='1909' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5568'>
-          <var-decl name='queues_kset' type-id='89b70200' visibility='default' filepath='include/linux/netdevice.h' line='1910' column='1'/>
+          <var-decl name='queues_kset' type-id='89b70200' visibility='default' filepath='include/linux/netdevice.h' line='1912' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5632'>
-          <var-decl name='promiscuity' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1912' column='1'/>
+          <var-decl name='promiscuity' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1914' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5664'>
-          <var-decl name='allmulti' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1913' column='1'/>
+          <var-decl name='allmulti' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1915' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5696'>
-          <var-decl name='tipc_ptr' type-id='eeaf504d' visibility='default' filepath='include/linux/netdevice.h' line='1925' column='1'/>
+          <var-decl name='tipc_ptr' type-id='eeaf504d' visibility='default' filepath='include/linux/netdevice.h' line='1927' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5760'>
-          <var-decl name='ip_ptr' type-id='fc6f14a9' visibility='default' filepath='include/linux/netdevice.h' line='1930' column='1'/>
+          <var-decl name='ip_ptr' type-id='fc6f14a9' visibility='default' filepath='include/linux/netdevice.h' line='1932' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5824'>
-          <var-decl name='ip6_ptr' type-id='f026b16b' visibility='default' filepath='include/linux/netdevice.h' line='1934' column='1'/>
+          <var-decl name='ip6_ptr' type-id='f026b16b' visibility='default' filepath='include/linux/netdevice.h' line='1933' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5888'>
-          <var-decl name='ieee80211_ptr' type-id='63c7e8e1' visibility='default' filepath='include/linux/netdevice.h' line='1938' column='1'/>
+          <var-decl name='ieee80211_ptr' type-id='63c7e8e1' visibility='default' filepath='include/linux/netdevice.h' line='1937' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5952'>
-          <var-decl name='ieee802154_ptr' type-id='165146ad' visibility='default' filepath='include/linux/netdevice.h' line='1939' column='1'/>
+          <var-decl name='ieee802154_ptr' type-id='165146ad' visibility='default' filepath='include/linux/netdevice.h' line='1938' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6016'>
-          <var-decl name='dev_addr' type-id='cf536864' visibility='default' filepath='include/linux/netdevice.h' line='1948' column='1'/>
+          <var-decl name='dev_addr' type-id='cf536864' visibility='default' filepath='include/linux/netdevice.h' line='1947' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6080'>
-          <var-decl name='_rx' type-id='31094274' visibility='default' filepath='include/linux/netdevice.h' line='1950' column='1'/>
+          <var-decl name='_rx' type-id='31094274' visibility='default' filepath='include/linux/netdevice.h' line='1949' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6144'>
-          <var-decl name='num_rx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1951' column='1'/>
+          <var-decl name='num_rx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1950' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6176'>
-          <var-decl name='real_num_rx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1952' column='1'/>
+          <var-decl name='real_num_rx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1951' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6208'>
-          <var-decl name='xdp_prog' type-id='bdcee7ae' visibility='default' filepath='include/linux/netdevice.h' line='1954' column='1'/>
+          <var-decl name='xdp_prog' type-id='bdcee7ae' visibility='default' filepath='include/linux/netdevice.h' line='1953' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6272'>
-          <var-decl name='gro_flush_timeout' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1955' column='1'/>
+          <var-decl name='gro_flush_timeout' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='1954' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6336'>
-          <var-decl name='rx_handler' type-id='da1cb816' visibility='default' filepath='include/linux/netdevice.h' line='1956' column='1'/>
+          <var-decl name='rx_handler' type-id='da1cb816' visibility='default' filepath='include/linux/netdevice.h' line='1955' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6400'>
-          <var-decl name='rx_handler_data' type-id='eaa32e2f' visibility='default' filepath='include/linux/netdevice.h' line='1957' column='1'/>
+          <var-decl name='rx_handler_data' type-id='eaa32e2f' visibility='default' filepath='include/linux/netdevice.h' line='1956' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6464'>
-          <var-decl name='miniq_ingress' type-id='b70f37f7' visibility='default' filepath='include/linux/netdevice.h' line='1960' column='1'/>
+          <var-decl name='miniq_ingress' type-id='b70f37f7' visibility='default' filepath='include/linux/netdevice.h' line='1959' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6528'>
-          <var-decl name='ingress_queue' type-id='35b28c4f' visibility='default' filepath='include/linux/netdevice.h' line='1962' column='1'/>
+          <var-decl name='ingress_queue' type-id='35b28c4f' visibility='default' filepath='include/linux/netdevice.h' line='1961' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6592'>
-          <var-decl name='nf_hooks_ingress' type-id='39a43b40' visibility='default' filepath='include/linux/netdevice.h' line='1964' column='1'/>
+          <var-decl name='nf_hooks_ingress' type-id='39a43b40' visibility='default' filepath='include/linux/netdevice.h' line='1963' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6656'>
-          <var-decl name='broadcast' type-id='fc872715' visibility='default' filepath='include/linux/netdevice.h' line='1967' column='1'/>
+          <var-decl name='broadcast' type-id='fc872715' visibility='default' filepath='include/linux/netdevice.h' line='1966' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6912'>
-          <var-decl name='rx_cpu_rmap' type-id='52baee64' visibility='default' filepath='include/linux/netdevice.h' line='1969' column='1'/>
+          <var-decl name='rx_cpu_rmap' type-id='52baee64' visibility='default' filepath='include/linux/netdevice.h' line='1968' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6976'>
-          <var-decl name='index_hlist' type-id='03a4a074' visibility='default' filepath='include/linux/netdevice.h' line='1971' column='1'/>
+          <var-decl name='index_hlist' type-id='03a4a074' visibility='default' filepath='include/linux/netdevice.h' line='1970' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7168'>
-          <var-decl name='_tx' type-id='35b28c4f' visibility='default' filepath='include/linux/netdevice.h' line='1976' column='1'/>
+          <var-decl name='_tx' type-id='35b28c4f' visibility='default' filepath='include/linux/netdevice.h' line='1975' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7232'>
-          <var-decl name='num_tx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1977' column='1'/>
+          <var-decl name='num_tx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1976' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7264'>
-          <var-decl name='real_num_tx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1978' column='1'/>
+          <var-decl name='real_num_tx_queues' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1977' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7296'>
-          <var-decl name='qdisc' type-id='ee406209' visibility='default' filepath='include/linux/netdevice.h' line='1979' column='1'/>
+          <var-decl name='qdisc' type-id='ee406209' visibility='default' filepath='include/linux/netdevice.h' line='1978' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7360'>
-          <var-decl name='qdisc_hash' type-id='ccfd385f' visibility='default' filepath='include/linux/netdevice.h' line='1981' column='1'/>
+          <var-decl name='qdisc_hash' type-id='ccfd385f' visibility='default' filepath='include/linux/netdevice.h' line='1980' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8384'>
-          <var-decl name='tx_queue_len' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1983' column='1'/>
+          <var-decl name='tx_queue_len' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='1982' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8416'>
-          <var-decl name='tx_global_lock' type-id='fb4018a0' visibility='default' filepath='include/linux/netdevice.h' line='1984' column='1'/>
+          <var-decl name='tx_global_lock' type-id='fb4018a0' visibility='default' filepath='include/linux/netdevice.h' line='1983' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8448'>
-          <var-decl name='watchdog_timeo' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1985' column='1'/>
+          <var-decl name='watchdog_timeo' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='1984' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8512'>
-          <var-decl name='xps_cpus_map' type-id='bf237056' visibility='default' filepath='include/linux/netdevice.h' line='1988' column='1'/>
+          <var-decl name='xps_cpus_map' type-id='bf237056' visibility='default' filepath='include/linux/netdevice.h' line='1987' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8576'>
-          <var-decl name='xps_rxqs_map' type-id='bf237056' visibility='default' filepath='include/linux/netdevice.h' line='1989' column='1'/>
+          <var-decl name='xps_rxqs_map' type-id='bf237056' visibility='default' filepath='include/linux/netdevice.h' line='1988' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8640'>
-          <var-decl name='miniq_egress' type-id='b70f37f7' visibility='default' filepath='include/linux/netdevice.h' line='1992' column='1'/>
+          <var-decl name='miniq_egress' type-id='b70f37f7' visibility='default' filepath='include/linux/netdevice.h' line='1991' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8704'>
-          <var-decl name='watchdog_timer' type-id='abe41e67' visibility='default' filepath='include/linux/netdevice.h' line='1996' column='1'/>
+          <var-decl name='watchdog_timer' type-id='abe41e67' visibility='default' filepath='include/linux/netdevice.h' line='1995' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9152'>
-          <var-decl name='pcpu_refcnt' type-id='7292109c' visibility='default' filepath='include/linux/netdevice.h' line='1998' column='1'/>
+          <var-decl name='pcpu_refcnt' type-id='7292109c' visibility='default' filepath='include/linux/netdevice.h' line='1997' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9216'>
-          <var-decl name='todo_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1999' column='1'/>
+          <var-decl name='todo_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1998' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9344'>
-          <var-decl name='link_watch_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='2001' column='1'/>
+          <var-decl name='link_watch_list' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='2000' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='reg_state' type-id='08f5ca18' visibility='default' filepath='include/linux/netdevice.h' line='2009' column='1'/>
+          <var-decl name='reg_state' type-id='08f5ca18' visibility='default' filepath='include/linux/netdevice.h' line='2008' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9480'>
-          <var-decl name='dismantle' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='2011' column='1'/>
+          <var-decl name='dismantle' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='2010' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='rtnl_link_state' type-id='08f5ca19' visibility='default' filepath='include/linux/netdevice.h' line='2016' column='1'/>
+          <var-decl name='rtnl_link_state' type-id='08f5ca19' visibility='default' filepath='include/linux/netdevice.h' line='2015' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9504'>
-          <var-decl name='needs_free_netdev' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='2018' column='1'/>
+          <var-decl name='needs_free_netdev' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='2017' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9536'>
-          <var-decl name='priv_destructor' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='2019' column='1'/>
+          <var-decl name='priv_destructor' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='2018' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9600'>
-          <var-decl name='nd_net' type-id='c9df1e6c' visibility='default' filepath='include/linux/netdevice.h' line='2025' column='1'/>
+          <var-decl name='nd_net' type-id='c9df1e6c' visibility='default' filepath='include/linux/netdevice.h' line='2024' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9664'>
-          <var-decl name='' type-id='38feef9e' visibility='default' filepath='include/linux/netdevice.h' line='2028' column='1'/>
+          <var-decl name='' type-id='38feef9e' visibility='default' filepath='include/linux/netdevice.h' line='2027' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9728'>
-          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/linux/netdevice.h' line='2043' column='1'/>
+          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/linux/netdevice.h' line='2042' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17344'>
-          <var-decl name='sysfs_groups' type-id='db1b7234' visibility='default' filepath='include/linux/netdevice.h' line='2044' column='1'/>
+          <var-decl name='sysfs_groups' type-id='db1b7234' visibility='default' filepath='include/linux/netdevice.h' line='2043' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17600'>
-          <var-decl name='sysfs_rx_queue_group' type-id='8ff9530e' visibility='default' filepath='include/linux/netdevice.h' line='2045' column='1'/>
+          <var-decl name='sysfs_rx_queue_group' type-id='8ff9530e' visibility='default' filepath='include/linux/netdevice.h' line='2044' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17664'>
-          <var-decl name='rtnl_link_ops' type-id='999c8d90' visibility='default' filepath='include/linux/netdevice.h' line='2047' column='1'/>
+          <var-decl name='rtnl_link_ops' type-id='999c8d90' visibility='default' filepath='include/linux/netdevice.h' line='2046' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17728'>
-          <var-decl name='gso_max_size' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='2051' column='1'/>
+          <var-decl name='gso_max_size' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='2050' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17760'>
-          <var-decl name='gso_max_segs' type-id='1dc6a898' visibility='default' filepath='include/linux/netdevice.h' line='2053' column='1'/>
+          <var-decl name='gso_max_segs' type-id='1dc6a898' visibility='default' filepath='include/linux/netdevice.h' line='2052' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17776'>
-          <var-decl name='num_tc' type-id='9b7e9486' visibility='default' filepath='include/linux/netdevice.h' line='2058' column='1'/>
+          <var-decl name='num_tc' type-id='9b7e9486' visibility='default' filepath='include/linux/netdevice.h' line='2057' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17792'>
-          <var-decl name='tc_to_txq' type-id='b5839634' visibility='default' filepath='include/linux/netdevice.h' line='2059' column='1'/>
+          <var-decl name='tc_to_txq' type-id='b5839634' visibility='default' filepath='include/linux/netdevice.h' line='2058' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18304'>
-          <var-decl name='prio_tc_map' type-id='0d8415b5' visibility='default' filepath='include/linux/netdevice.h' line='2060' column='1'/>
+          <var-decl name='prio_tc_map' type-id='0d8415b5' visibility='default' filepath='include/linux/netdevice.h' line='2059' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18432'>
-          <var-decl name='phydev' type-id='7efbcaaf' visibility='default' filepath='include/linux/netdevice.h' line='2068' column='1'/>
+          <var-decl name='phydev' type-id='7efbcaaf' visibility='default' filepath='include/linux/netdevice.h' line='2067' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18496'>
-          <var-decl name='sfp_bus' type-id='6daf6abd' visibility='default' filepath='include/linux/netdevice.h' line='2069' column='1'/>
+          <var-decl name='sfp_bus' type-id='6daf6abd' visibility='default' filepath='include/linux/netdevice.h' line='2068' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18560'>
-          <var-decl name='qdisc_tx_busylock' type-id='a57283f9' visibility='default' filepath='include/linux/netdevice.h' line='2070' column='1'/>
+          <var-decl name='qdisc_tx_busylock' type-id='a57283f9' visibility='default' filepath='include/linux/netdevice.h' line='2069' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18624'>
-          <var-decl name='qdisc_running_key' type-id='a57283f9' visibility='default' filepath='include/linux/netdevice.h' line='2071' column='1'/>
+          <var-decl name='qdisc_running_key' type-id='a57283f9' visibility='default' filepath='include/linux/netdevice.h' line='2070' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18688'>
-          <var-decl name='proto_down' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='2072' column='1'/>
+          <var-decl name='proto_down' type-id='b50a4934' visibility='default' filepath='include/linux/netdevice.h' line='2071' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8'>
-          <var-decl name='wol_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='2073' column='1'/>
+          <var-decl name='wol_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='2072' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18752'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2075' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2074' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18816'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2076' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2075' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18880'>
-          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2077' column='1'/>
+          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2076' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18944'>
-          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2078' column='1'/>
+          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2077' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19008'>
-          <var-decl name='android_kabi_reserved5' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2079' column='1'/>
+          <var-decl name='android_kabi_reserved5' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2078' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19072'>
-          <var-decl name='android_kabi_reserved6' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2080' column='1'/>
+          <var-decl name='android_kabi_reserved6' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2079' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19136'>
-          <var-decl name='android_kabi_reserved7' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2081' column='1'/>
+          <var-decl name='android_kabi_reserved7' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2080' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19200'>
-          <var-decl name='android_kabi_reserved8' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2082' column='1'/>
+          <var-decl name='android_kabi_reserved8' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2081' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='dev_ifalias' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='946' column='1' id='ddd212e6'>
+      <class-decl name='dev_ifalias' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='949' column='1' id='ddd212e6'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='rcuhead' type-id='e3d8ce29' visibility='default' filepath='include/linux/netdevice.h' line='947' column='1'/>
+          <var-decl name='rcuhead' type-id='e3d8ce29' visibility='default' filepath='include/linux/netdevice.h' line='950' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='ifalias' type-id='e84913bd' visibility='default' filepath='include/linux/netdevice.h' line='948' column='1'/>
+          <var-decl name='ifalias' type-id='e84913bd' visibility='default' filepath='include/linux/netdevice.h' line='951' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='__anonymous_struct__' size-in-bits='256' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='1814' column='1' id='19245258'>
+      <class-decl name='__anonymous_struct__' size-in-bits='256' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='1816' column='1' id='19245258'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='upper' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1815' column='1'/>
+          <var-decl name='upper' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1817' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='lower' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1816' column='1'/>
+          <var-decl name='lower' type-id='72f469ec' visibility='default' filepath='include/linux/netdevice.h' line='1818' column='1'/>
         </data-member>
       </class-decl>
       <typedef-decl name='netdev_features_t' type-id='91ce1af9' filepath='include/linux/netdev_features.h' line='17' column='1' id='f9f4b16f'/>
@@ -36605,222 +36651,222 @@
           <var-decl name='tx_compressed' type-id='7359adad' visibility='default' filepath='include/linux/netdevice.h' line='189' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='net_device_ops' size-in-bits='4608' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='1255' column='1' id='ba44c7d8'>
+      <class-decl name='net_device_ops' size-in-bits='4608' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='1258' column='1' id='ba44c7d8'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='ndo_init' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1256' column='1'/>
+          <var-decl name='ndo_init' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1259' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='ndo_uninit' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='1257' column='1'/>
+          <var-decl name='ndo_uninit' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='1260' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='ndo_open' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1258' column='1'/>
+          <var-decl name='ndo_open' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1261' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='ndo_stop' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1259' column='1'/>
+          <var-decl name='ndo_stop' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1262' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ndo_start_xmit' type-id='bd3f3f93' visibility='default' filepath='include/linux/netdevice.h' line='1260' column='1'/>
+          <var-decl name='ndo_start_xmit' type-id='bd3f3f93' visibility='default' filepath='include/linux/netdevice.h' line='1263' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='ndo_features_check' type-id='7a0ed254' visibility='default' filepath='include/linux/netdevice.h' line='1262' column='1'/>
+          <var-decl name='ndo_features_check' type-id='7a0ed254' visibility='default' filepath='include/linux/netdevice.h' line='1265' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='ndo_select_queue' type-id='e9b83e5c' visibility='default' filepath='include/linux/netdevice.h' line='1265' column='1'/>
+          <var-decl name='ndo_select_queue' type-id='e9b83e5c' visibility='default' filepath='include/linux/netdevice.h' line='1268' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='ndo_change_rx_flags' type-id='c7c94ce1' visibility='default' filepath='include/linux/netdevice.h' line='1269' column='1'/>
+          <var-decl name='ndo_change_rx_flags' type-id='c7c94ce1' visibility='default' filepath='include/linux/netdevice.h' line='1272' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='ndo_set_rx_mode' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='1271' column='1'/>
+          <var-decl name='ndo_set_rx_mode' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='1274' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='ndo_set_mac_address' type-id='f4dd5cc5' visibility='default' filepath='include/linux/netdevice.h' line='1272' column='1'/>
+          <var-decl name='ndo_set_mac_address' type-id='f4dd5cc5' visibility='default' filepath='include/linux/netdevice.h' line='1275' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='ndo_validate_addr' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1274' column='1'/>
+          <var-decl name='ndo_validate_addr' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1277' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='ndo_do_ioctl' type-id='cc325be7' visibility='default' filepath='include/linux/netdevice.h' line='1275' column='1'/>
+          <var-decl name='ndo_do_ioctl' type-id='cc325be7' visibility='default' filepath='include/linux/netdevice.h' line='1278' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='ndo_set_config' type-id='bd2d1eba' visibility='default' filepath='include/linux/netdevice.h' line='1277' column='1'/>
+          <var-decl name='ndo_set_config' type-id='bd2d1eba' visibility='default' filepath='include/linux/netdevice.h' line='1280' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='ndo_change_mtu' type-id='d6762aa0' visibility='default' filepath='include/linux/netdevice.h' line='1279' column='1'/>
+          <var-decl name='ndo_change_mtu' type-id='d6762aa0' visibility='default' filepath='include/linux/netdevice.h' line='1282' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='ndo_neigh_setup' type-id='5c9f2a92' visibility='default' filepath='include/linux/netdevice.h' line='1281' column='1'/>
+          <var-decl name='ndo_neigh_setup' type-id='5c9f2a92' visibility='default' filepath='include/linux/netdevice.h' line='1284' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='ndo_tx_timeout' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='1283' column='1'/>
+          <var-decl name='ndo_tx_timeout' type-id='548eee3a' visibility='default' filepath='include/linux/netdevice.h' line='1286' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='ndo_get_stats64' type-id='cb4c6db1' visibility='default' filepath='include/linux/netdevice.h' line='1285' column='1'/>
+          <var-decl name='ndo_get_stats64' type-id='cb4c6db1' visibility='default' filepath='include/linux/netdevice.h' line='1288' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='ndo_has_offload_stats' type-id='e95fd96b' visibility='default' filepath='include/linux/netdevice.h' line='1287' column='1'/>
+          <var-decl name='ndo_has_offload_stats' type-id='e95fd96b' visibility='default' filepath='include/linux/netdevice.h' line='1290' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='ndo_get_offload_stats' type-id='f98694f9' visibility='default' filepath='include/linux/netdevice.h' line='1288' column='1'/>
+          <var-decl name='ndo_get_offload_stats' type-id='f98694f9' visibility='default' filepath='include/linux/netdevice.h' line='1291' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='ndo_get_stats' type-id='3217f9ba' visibility='default' filepath='include/linux/netdevice.h' line='1291' column='1'/>
+          <var-decl name='ndo_get_stats' type-id='3217f9ba' visibility='default' filepath='include/linux/netdevice.h' line='1294' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='ndo_vlan_rx_add_vid' type-id='4fcb4c39' visibility='default' filepath='include/linux/netdevice.h' line='1293' column='1'/>
+          <var-decl name='ndo_vlan_rx_add_vid' type-id='4fcb4c39' visibility='default' filepath='include/linux/netdevice.h' line='1296' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='ndo_vlan_rx_kill_vid' type-id='4fcb4c39' visibility='default' filepath='include/linux/netdevice.h' line='1295' column='1'/>
+          <var-decl name='ndo_vlan_rx_kill_vid' type-id='4fcb4c39' visibility='default' filepath='include/linux/netdevice.h' line='1298' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='ndo_set_vf_mac' type-id='bae60bcf' visibility='default' filepath='include/linux/netdevice.h' line='1303' column='1'/>
+          <var-decl name='ndo_set_vf_mac' type-id='bae60bcf' visibility='default' filepath='include/linux/netdevice.h' line='1306' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1472'>
-          <var-decl name='ndo_set_vf_vlan' type-id='699131d0' visibility='default' filepath='include/linux/netdevice.h' line='1305' column='1'/>
+          <var-decl name='ndo_set_vf_vlan' type-id='699131d0' visibility='default' filepath='include/linux/netdevice.h' line='1308' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='ndo_set_vf_rate' type-id='7cd466e6' visibility='default' filepath='include/linux/netdevice.h' line='1308' column='1'/>
+          <var-decl name='ndo_set_vf_rate' type-id='7cd466e6' visibility='default' filepath='include/linux/netdevice.h' line='1311' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1600'>
-          <var-decl name='ndo_set_vf_spoofchk' type-id='0c16aca1' visibility='default' filepath='include/linux/netdevice.h' line='1311' column='1'/>
+          <var-decl name='ndo_set_vf_spoofchk' type-id='0c16aca1' visibility='default' filepath='include/linux/netdevice.h' line='1314' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1664'>
-          <var-decl name='ndo_set_vf_trust' type-id='0c16aca1' visibility='default' filepath='include/linux/netdevice.h' line='1313' column='1'/>
+          <var-decl name='ndo_set_vf_trust' type-id='0c16aca1' visibility='default' filepath='include/linux/netdevice.h' line='1316' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1728'>
-          <var-decl name='ndo_get_vf_config' type-id='d22f8cbe' visibility='default' filepath='include/linux/netdevice.h' line='1315' column='1'/>
+          <var-decl name='ndo_get_vf_config' type-id='d22f8cbe' visibility='default' filepath='include/linux/netdevice.h' line='1318' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1792'>
-          <var-decl name='ndo_set_vf_link_state' type-id='b54cfa0f' visibility='default' filepath='include/linux/netdevice.h' line='1318' column='1'/>
+          <var-decl name='ndo_set_vf_link_state' type-id='b54cfa0f' visibility='default' filepath='include/linux/netdevice.h' line='1321' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='ndo_get_vf_stats' type-id='eee971fd' visibility='default' filepath='include/linux/netdevice.h' line='1320' column='1'/>
+          <var-decl name='ndo_get_vf_stats' type-id='eee971fd' visibility='default' filepath='include/linux/netdevice.h' line='1323' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1920'>
-          <var-decl name='ndo_set_vf_port' type-id='af60ef81' visibility='default' filepath='include/linux/netdevice.h' line='1324' column='1'/>
+          <var-decl name='ndo_set_vf_port' type-id='af60ef81' visibility='default' filepath='include/linux/netdevice.h' line='1327' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1984'>
-          <var-decl name='ndo_get_vf_port' type-id='be55abd8' visibility='default' filepath='include/linux/netdevice.h' line='1327' column='1'/>
+          <var-decl name='ndo_get_vf_port' type-id='be55abd8' visibility='default' filepath='include/linux/netdevice.h' line='1330' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='ndo_set_vf_guid' type-id='0617ad2b' visibility='default' filepath='include/linux/netdevice.h' line='1329' column='1'/>
+          <var-decl name='ndo_set_vf_guid' type-id='0617ad2b' visibility='default' filepath='include/linux/netdevice.h' line='1332' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='ndo_set_vf_rss_query_en' type-id='0c16aca1' visibility='default' filepath='include/linux/netdevice.h' line='1332' column='1'/>
+          <var-decl name='ndo_set_vf_rss_query_en' type-id='0c16aca1' visibility='default' filepath='include/linux/netdevice.h' line='1335' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2176'>
-          <var-decl name='ndo_setup_tc' type-id='06b83346' visibility='default' filepath='include/linux/netdevice.h' line='1335' column='1'/>
+          <var-decl name='ndo_setup_tc' type-id='06b83346' visibility='default' filepath='include/linux/netdevice.h' line='1338' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2240'>
-          <var-decl name='ndo_rx_flow_steer' type-id='47498e6c' visibility='default' filepath='include/linux/netdevice.h' line='1363' column='1'/>
+          <var-decl name='ndo_rx_flow_steer' type-id='47498e6c' visibility='default' filepath='include/linux/netdevice.h' line='1366' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2304'>
-          <var-decl name='ndo_add_slave' type-id='031fe454' visibility='default' filepath='include/linux/netdevice.h' line='1368' column='1'/>
+          <var-decl name='ndo_add_slave' type-id='031fe454' visibility='default' filepath='include/linux/netdevice.h' line='1371' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2368'>
-          <var-decl name='ndo_del_slave' type-id='ed3019e9' visibility='default' filepath='include/linux/netdevice.h' line='1371' column='1'/>
+          <var-decl name='ndo_del_slave' type-id='ed3019e9' visibility='default' filepath='include/linux/netdevice.h' line='1374' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2432'>
-          <var-decl name='ndo_fix_features' type-id='4a028f44' visibility='default' filepath='include/linux/netdevice.h' line='1373' column='1'/>
+          <var-decl name='ndo_fix_features' type-id='4a028f44' visibility='default' filepath='include/linux/netdevice.h' line='1376' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2496'>
-          <var-decl name='ndo_set_features' type-id='10dae4c5' visibility='default' filepath='include/linux/netdevice.h' line='1375' column='1'/>
+          <var-decl name='ndo_set_features' type-id='10dae4c5' visibility='default' filepath='include/linux/netdevice.h' line='1378' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2560'>
-          <var-decl name='ndo_neigh_construct' type-id='92446276' visibility='default' filepath='include/linux/netdevice.h' line='1377' column='1'/>
+          <var-decl name='ndo_neigh_construct' type-id='92446276' visibility='default' filepath='include/linux/netdevice.h' line='1380' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2624'>
-          <var-decl name='ndo_neigh_destroy' type-id='11e89fb9' visibility='default' filepath='include/linux/netdevice.h' line='1379' column='1'/>
+          <var-decl name='ndo_neigh_destroy' type-id='11e89fb9' visibility='default' filepath='include/linux/netdevice.h' line='1382' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2688'>
-          <var-decl name='ndo_fdb_add' type-id='c0fb2f11' visibility='default' filepath='include/linux/netdevice.h' line='1382' column='1'/>
+          <var-decl name='ndo_fdb_add' type-id='c0fb2f11' visibility='default' filepath='include/linux/netdevice.h' line='1385' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2752'>
-          <var-decl name='ndo_fdb_del' type-id='e6032f80' visibility='default' filepath='include/linux/netdevice.h' line='1388' column='1'/>
+          <var-decl name='ndo_fdb_del' type-id='e6032f80' visibility='default' filepath='include/linux/netdevice.h' line='1391' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2816'>
-          <var-decl name='ndo_fdb_dump' type-id='147cd5a7' visibility='default' filepath='include/linux/netdevice.h' line='1393' column='1'/>
+          <var-decl name='ndo_fdb_dump' type-id='147cd5a7' visibility='default' filepath='include/linux/netdevice.h' line='1396' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2880'>
-          <var-decl name='ndo_bridge_setlink' type-id='1223555b' visibility='default' filepath='include/linux/netdevice.h' line='1399' column='1'/>
+          <var-decl name='ndo_bridge_setlink' type-id='1223555b' visibility='default' filepath='include/linux/netdevice.h' line='1402' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2944'>
-          <var-decl name='ndo_bridge_getlink' type-id='e78e01a9' visibility='default' filepath='include/linux/netdevice.h' line='1402' column='1'/>
+          <var-decl name='ndo_bridge_getlink' type-id='e78e01a9' visibility='default' filepath='include/linux/netdevice.h' line='1405' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3008'>
-          <var-decl name='ndo_bridge_dellink' type-id='1223555b' visibility='default' filepath='include/linux/netdevice.h' line='1407' column='1'/>
+          <var-decl name='ndo_bridge_dellink' type-id='1223555b' visibility='default' filepath='include/linux/netdevice.h' line='1410' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3072'>
-          <var-decl name='ndo_change_carrier' type-id='e36088ec' visibility='default' filepath='include/linux/netdevice.h' line='1410' column='1'/>
+          <var-decl name='ndo_change_carrier' type-id='e36088ec' visibility='default' filepath='include/linux/netdevice.h' line='1413' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3136'>
-          <var-decl name='ndo_get_phys_port_id' type-id='98252144' visibility='default' filepath='include/linux/netdevice.h' line='1412' column='1'/>
+          <var-decl name='ndo_get_phys_port_id' type-id='98252144' visibility='default' filepath='include/linux/netdevice.h' line='1415' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3200'>
-          <var-decl name='ndo_get_phys_port_name' type-id='5139dd84' visibility='default' filepath='include/linux/netdevice.h' line='1414' column='1'/>
+          <var-decl name='ndo_get_phys_port_name' type-id='5139dd84' visibility='default' filepath='include/linux/netdevice.h' line='1417' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3264'>
-          <var-decl name='ndo_udp_tunnel_add' type-id='a43821b9' visibility='default' filepath='include/linux/netdevice.h' line='1416' column='1'/>
+          <var-decl name='ndo_udp_tunnel_add' type-id='a43821b9' visibility='default' filepath='include/linux/netdevice.h' line='1419' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3328'>
-          <var-decl name='ndo_udp_tunnel_del' type-id='a43821b9' visibility='default' filepath='include/linux/netdevice.h' line='1418' column='1'/>
+          <var-decl name='ndo_udp_tunnel_del' type-id='a43821b9' visibility='default' filepath='include/linux/netdevice.h' line='1421' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3392'>
-          <var-decl name='ndo_dfwd_add_station' type-id='e2d7f258' visibility='default' filepath='include/linux/netdevice.h' line='1420' column='1'/>
+          <var-decl name='ndo_dfwd_add_station' type-id='e2d7f258' visibility='default' filepath='include/linux/netdevice.h' line='1423' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3456'>
-          <var-decl name='ndo_dfwd_del_station' type-id='5ac7baf4' visibility='default' filepath='include/linux/netdevice.h' line='1422' column='1'/>
+          <var-decl name='ndo_dfwd_del_station' type-id='5ac7baf4' visibility='default' filepath='include/linux/netdevice.h' line='1425' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3520'>
-          <var-decl name='ndo_get_lock_subclass' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1425' column='1'/>
+          <var-decl name='ndo_get_lock_subclass' type-id='2555df59' visibility='default' filepath='include/linux/netdevice.h' line='1428' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3584'>
-          <var-decl name='ndo_set_tx_maxrate' type-id='c1e0b02f' visibility='default' filepath='include/linux/netdevice.h' line='1426' column='1'/>
+          <var-decl name='ndo_set_tx_maxrate' type-id='c1e0b02f' visibility='default' filepath='include/linux/netdevice.h' line='1429' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3648'>
-          <var-decl name='ndo_get_iflink' type-id='4753b592' visibility='default' filepath='include/linux/netdevice.h' line='1429' column='1'/>
+          <var-decl name='ndo_get_iflink' type-id='4753b592' visibility='default' filepath='include/linux/netdevice.h' line='1432' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3712'>
-          <var-decl name='ndo_change_proto_down' type-id='e36088ec' visibility='default' filepath='include/linux/netdevice.h' line='1430' column='1'/>
+          <var-decl name='ndo_change_proto_down' type-id='e36088ec' visibility='default' filepath='include/linux/netdevice.h' line='1433' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3776'>
-          <var-decl name='ndo_fill_metadata_dst' type-id='2cc5a575' visibility='default' filepath='include/linux/netdevice.h' line='1432' column='1'/>
+          <var-decl name='ndo_fill_metadata_dst' type-id='2cc5a575' visibility='default' filepath='include/linux/netdevice.h' line='1435' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3840'>
-          <var-decl name='ndo_set_rx_headroom' type-id='c7c94ce1' visibility='default' filepath='include/linux/netdevice.h' line='1434' column='1'/>
+          <var-decl name='ndo_set_rx_headroom' type-id='c7c94ce1' visibility='default' filepath='include/linux/netdevice.h' line='1437' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3904'>
-          <var-decl name='ndo_bpf' type-id='49f84764' visibility='default' filepath='include/linux/netdevice.h' line='1436' column='1'/>
+          <var-decl name='ndo_bpf' type-id='49f84764' visibility='default' filepath='include/linux/netdevice.h' line='1439' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3968'>
-          <var-decl name='ndo_xdp_xmit' type-id='0c7d25ff' visibility='default' filepath='include/linux/netdevice.h' line='1438' column='1'/>
+          <var-decl name='ndo_xdp_xmit' type-id='0c7d25ff' visibility='default' filepath='include/linux/netdevice.h' line='1441' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4032'>
-          <var-decl name='ndo_xsk_async_xmit' type-id='0f8df030' visibility='default' filepath='include/linux/netdevice.h' line='1441' column='1'/>
+          <var-decl name='ndo_xsk_async_xmit' type-id='0f8df030' visibility='default' filepath='include/linux/netdevice.h' line='1444' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4096'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1444' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1447' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4160'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1445' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1448' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4224'>
-          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1446' column='1'/>
+          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1449' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4288'>
-          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1447' column='1'/>
+          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1450' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4352'>
-          <var-decl name='android_kabi_reserved5' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1448' column='1'/>
+          <var-decl name='android_kabi_reserved5' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1451' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4416'>
-          <var-decl name='android_kabi_reserved6' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1449' column='1'/>
+          <var-decl name='android_kabi_reserved6' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1452' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4480'>
-          <var-decl name='android_kabi_reserved7' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1450' column='1'/>
+          <var-decl name='android_kabi_reserved7' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1453' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4544'>
-          <var-decl name='android_kabi_reserved8' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1451' column='1'/>
+          <var-decl name='android_kabi_reserved8' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='1454' column='1'/>
         </data-member>
       </class-decl>
       <typedef-decl name='netdev_tx_t' type-id='e246a80b' filepath='include/linux/netdevice.h' line='117' column='1' id='6849a88c'/>
@@ -37225,7 +37271,7 @@
         </data-member>
       </union-decl>
       <typedef-decl name='sk_buff_data_t' type-id='f0981eeb' filepath='include/linux/skbuff.h' line='584' column='1' id='5c1abc34'/>
-      <typedef-decl name='select_queue_fallback_t' type-id='de36db77' filepath='include/linux/netdevice.h' line='821' column='1' id='68494f84'/>
+      <typedef-decl name='select_queue_fallback_t' type-id='de36db77' filepath='include/linux/netdevice.h' line='824' column='1' id='68494f84'/>
       <class-decl name='ifreq' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/uapi/linux/if.h' line='231' column='1' id='c1a75286'>
         <data-member access='public' layout-offset-in-bits='0'>
           <var-decl name='ifr_ifrn' type-id='96ef15db' visibility='default' filepath='include/uapi/linux/if.h' line='236' column='1'/>
@@ -37571,7 +37617,7 @@
           <var-decl name='nla_type' type-id='d315442e' visibility='default' filepath='include/uapi/linux/netlink.h' line='212' column='1'/>
         </data-member>
       </class-decl>
-      <enum-decl name='tc_setup_type' filepath='include/linux/netdevice.h' line='825' column='1' id='b3e12f1c'>
+      <enum-decl name='tc_setup_type' filepath='include/linux/netdevice.h' line='828' column='1' id='b3e12f1c'>
         <underlying-type type-id='9cac1fee'/>
         <enumerator name='TC_SETUP_QDISC_MQPRIO' value='0'/>
         <enumerator name='TC_SETUP_CLSU32' value='1'/>
@@ -37674,23 +37720,23 @@
           <var-decl name='nlmsg_pid' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/netlink.h' line='49' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='netdev_phys_item_id' size-in-bits='264' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='809' column='1' id='14a30316'>
+      <class-decl name='netdev_phys_item_id' size-in-bits='264' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='812' column='1' id='14a30316'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='id' type-id='fc872715' visibility='default' filepath='include/linux/netdevice.h' line='810' column='1'/>
+          <var-decl name='id' type-id='fc872715' visibility='default' filepath='include/linux/netdevice.h' line='813' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='id_len' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='811' column='1'/>
+          <var-decl name='id_len' type-id='002ac4a6' visibility='default' filepath='include/linux/netdevice.h' line='814' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='netdev_bpf' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='868' column='1' id='0360a184'>
+      <class-decl name='netdev_bpf' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='871' column='1' id='0360a184'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='command' type-id='fa64b30d' visibility='default' filepath='include/linux/netdevice.h' line='869' column='1'/>
+          <var-decl name='command' type-id='fa64b30d' visibility='default' filepath='include/linux/netdevice.h' line='872' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='' type-id='aa66a4ab' visibility='default' filepath='include/linux/netdevice.h' line='870' column='1'/>
+          <var-decl name='' type-id='aa66a4ab' visibility='default' filepath='include/linux/netdevice.h' line='873' column='1'/>
         </data-member>
       </class-decl>
-      <enum-decl name='bpf_netdev_command' filepath='include/linux/netdevice.h' line='842' column='1' id='fa64b30d'>
+      <enum-decl name='bpf_netdev_command' filepath='include/linux/netdevice.h' line='845' column='1' id='fa64b30d'>
         <underlying-type type-id='9cac1fee'/>
         <enumerator name='XDP_SETUP_PROG' value='0'/>
         <enumerator name='XDP_SETUP_PROG_HW' value='1'/>
@@ -37704,69 +37750,69 @@
         <enumerator name='XDP_QUERY_XSK_UMEM' value='9'/>
         <enumerator name='XDP_SETUP_XSK_UMEM' value='10'/>
       </enum-decl>
-      <union-decl name='__anonymous_union__14' size-in-bits='192' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='870' column='1' id='aa66a4ab'>
+      <union-decl name='__anonymous_union__14' size-in-bits='192' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='873' column='1' id='aa66a4ab'>
         <data-member access='public'>
-          <var-decl name='' type-id='33bba89f' visibility='default' filepath='include/linux/netdevice.h' line='872' column='1'/>
+          <var-decl name='' type-id='33bba89f' visibility='default' filepath='include/linux/netdevice.h' line='875' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='' type-id='0ed9a4e9' visibility='default' filepath='include/linux/netdevice.h' line='878' column='1'/>
+          <var-decl name='' type-id='0ed9a4e9' visibility='default' filepath='include/linux/netdevice.h' line='881' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='verifier' type-id='346c06af' visibility='default' filepath='include/linux/netdevice.h' line='887' column='1'/>
+          <var-decl name='verifier' type-id='346c06af' visibility='default' filepath='include/linux/netdevice.h' line='890' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='offload' type-id='099cc829' visibility='default' filepath='include/linux/netdevice.h' line='891' column='1'/>
+          <var-decl name='offload' type-id='099cc829' visibility='default' filepath='include/linux/netdevice.h' line='894' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='' type-id='f7a2361f' visibility='default' filepath='include/linux/netdevice.h' line='893' column='1'/>
+          <var-decl name='' type-id='f7a2361f' visibility='default' filepath='include/linux/netdevice.h' line='896' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='xsk' type-id='40a847cb' visibility='default' filepath='include/linux/netdevice.h' line='900' column='1'/>
+          <var-decl name='xsk' type-id='40a847cb' visibility='default' filepath='include/linux/netdevice.h' line='903' column='1'/>
         </data-member>
       </union-decl>
-      <class-decl name='__anonymous_struct__11' size-in-bits='192' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='872' column='1' id='33bba89f'>
+      <class-decl name='__anonymous_struct__11' size-in-bits='192' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='875' column='1' id='33bba89f'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/linux/netdevice.h' line='873' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/linux/netdevice.h' line='876' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='prog' type-id='bdcee7ae' visibility='default' filepath='include/linux/netdevice.h' line='874' column='1'/>
+          <var-decl name='prog' type-id='bdcee7ae' visibility='default' filepath='include/linux/netdevice.h' line='877' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='extack' type-id='5799dc94' visibility='default' filepath='include/linux/netdevice.h' line='875' column='1'/>
+          <var-decl name='extack' type-id='5799dc94' visibility='default' filepath='include/linux/netdevice.h' line='878' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='__anonymous_struct__12' size-in-bits='64' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='878' column='1' id='0ed9a4e9'>
+      <class-decl name='__anonymous_struct__12' size-in-bits='64' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='881' column='1' id='0ed9a4e9'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='prog_id' type-id='19c2251e' visibility='default' filepath='include/linux/netdevice.h' line='879' column='1'/>
+          <var-decl name='prog_id' type-id='19c2251e' visibility='default' filepath='include/linux/netdevice.h' line='882' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='prog_flags' type-id='19c2251e' visibility='default' filepath='include/linux/netdevice.h' line='881' column='1'/>
+          <var-decl name='prog_flags' type-id='19c2251e' visibility='default' filepath='include/linux/netdevice.h' line='884' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='__anonymous_struct__13' size-in-bits='128' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='884' column='1' id='346c06af'>
+      <class-decl name='__anonymous_struct__13' size-in-bits='128' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='887' column='1' id='346c06af'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='prog' type-id='bdcee7ae' visibility='default' filepath='include/linux/netdevice.h' line='885' column='1'/>
+          <var-decl name='prog' type-id='bdcee7ae' visibility='default' filepath='include/linux/netdevice.h' line='888' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='ops' type-id='1b4ef70e' visibility='default' filepath='include/linux/netdevice.h' line='886' column='1'/>
+          <var-decl name='ops' type-id='1b4ef70e' visibility='default' filepath='include/linux/netdevice.h' line='889' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='__anonymous_struct__14' size-in-bits='64' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='889' column='1' id='099cc829'>
+      <class-decl name='__anonymous_struct__14' size-in-bits='64' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='892' column='1' id='099cc829'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='prog' type-id='bdcee7ae' visibility='default' filepath='include/linux/netdevice.h' line='890' column='1'/>
+          <var-decl name='prog' type-id='bdcee7ae' visibility='default' filepath='include/linux/netdevice.h' line='893' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='__anonymous_struct__15' size-in-bits='64' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='893' column='1' id='f7a2361f'>
+      <class-decl name='__anonymous_struct__15' size-in-bits='64' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='896' column='1' id='f7a2361f'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='offmap' type-id='366d2695' visibility='default' filepath='include/linux/netdevice.h' line='894' column='1'/>
+          <var-decl name='offmap' type-id='366d2695' visibility='default' filepath='include/linux/netdevice.h' line='897' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='__anonymous_struct__16' size-in-bits='128' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='897' column='1' id='40a847cb'>
+      <class-decl name='__anonymous_struct__16' size-in-bits='128' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='900' column='1' id='40a847cb'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='umem' type-id='577ede06' visibility='default' filepath='include/linux/netdevice.h' line='898' column='1'/>
+          <var-decl name='umem' type-id='577ede06' visibility='default' filepath='include/linux/netdevice.h' line='901' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='queue_id' type-id='1dc6a898' visibility='default' filepath='include/linux/netdevice.h' line='899' column='1'/>
+          <var-decl name='queue_id' type-id='1dc6a898' visibility='default' filepath='include/linux/netdevice.h' line='902' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='xdp_frame' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/xdp.h' line='75' column='1' id='21f83f61'>
@@ -38760,33 +38806,33 @@
           <var-decl name='count' type-id='95e97e5e' visibility='default' filepath='include/linux/netdevice.h' line='224' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='netdev_rx_queue' size-in-bits='2048' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='723' column='1' id='f12ac4ae'>
+      <class-decl name='netdev_rx_queue' size-in-bits='2048' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='726' column='1' id='f12ac4ae'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='rps_map' type-id='f30dbff5' visibility='default' filepath='include/linux/netdevice.h' line='725' column='1'/>
+          <var-decl name='rps_map' type-id='f30dbff5' visibility='default' filepath='include/linux/netdevice.h' line='728' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='rps_flow_table' type-id='deff2378' visibility='default' filepath='include/linux/netdevice.h' line='726' column='1'/>
+          <var-decl name='rps_flow_table' type-id='deff2378' visibility='default' filepath='include/linux/netdevice.h' line='729' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='kobj' type-id='b6ab8849' visibility='default' filepath='include/linux/netdevice.h' line='728' column='1'/>
+          <var-decl name='kobj' type-id='b6ab8849' visibility='default' filepath='include/linux/netdevice.h' line='731' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='dev' type-id='68a2d05b' visibility='default' filepath='include/linux/netdevice.h' line='729' column='1'/>
+          <var-decl name='dev' type-id='68a2d05b' visibility='default' filepath='include/linux/netdevice.h' line='732' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='xdp_rxq' type-id='eb0d6f26' visibility='default' filepath='include/linux/netdevice.h' line='730' column='1'/>
+          <var-decl name='xdp_rxq' type-id='eb0d6f26' visibility='default' filepath='include/linux/netdevice.h' line='733' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='732' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='735' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1600'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='733' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='736' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1664'>
-          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='734' column='1'/>
+          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='737' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1728'>
-          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='735' column='1'/>
+          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='738' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='rps_map' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='649' column='1' id='6f8d5f55'>
@@ -38936,29 +38982,29 @@
           <var-decl name='slack_hold_time' type-id='f0981eeb' visibility='default' filepath='include/linux/dynamic_queue_limits.h' line='62' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='xps_dev_maps' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='766' column='1' id='4edc4180'>
+      <class-decl name='xps_dev_maps' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='769' column='1' id='4edc4180'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/linux/netdevice.h' line='767' column='1'/>
+          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/linux/netdevice.h' line='770' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='attr_map' type-id='a0955e2b' visibility='default' filepath='include/linux/netdevice.h' line='768' column='1'/>
+          <var-decl name='attr_map' type-id='a0955e2b' visibility='default' filepath='include/linux/netdevice.h' line='771' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='xps_map' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='753' column='1' id='279bdcdf'>
+      <class-decl name='xps_map' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='756' column='1' id='279bdcdf'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='len' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='754' column='1'/>
+          <var-decl name='len' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='757' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='alloc_len' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='755' column='1'/>
+          <var-decl name='alloc_len' type-id='f0981eeb' visibility='default' filepath='include/linux/netdevice.h' line='758' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/linux/netdevice.h' line='756' column='1'/>
+          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/linux/netdevice.h' line='759' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='queues' type-id='0f300383' visibility='default' filepath='include/linux/netdevice.h' line='757' column='1'/>
+          <var-decl name='queues' type-id='0f300383' visibility='default' filepath='include/linux/netdevice.h' line='760' column='1'/>
         </data-member>
       </class-decl>
-      <enum-decl name='__anonymous_enum__1' is-anonymous='yes' filepath='include/linux/netdevice.h' line='2003' column='1' id='08f5ca18'>
+      <enum-decl name='__anonymous_enum__1' is-anonymous='yes' filepath='include/linux/netdevice.h' line='2002' column='1' id='08f5ca18'>
         <underlying-type type-id='9cac1fee'/>
         <enumerator name='NETREG_UNINITIALIZED' value='0'/>
         <enumerator name='NETREG_REGISTERED' value='1'/>
@@ -38967,7 +39013,7 @@
         <enumerator name='NETREG_RELEASED' value='4'/>
         <enumerator name='NETREG_DUMMY' value='5'/>
       </enum-decl>
-      <enum-decl name='__anonymous_enum__2' is-anonymous='yes' filepath='include/linux/netdevice.h' line='2013' column='1' id='08f5ca19'>
+      <enum-decl name='__anonymous_enum__2' is-anonymous='yes' filepath='include/linux/netdevice.h' line='2012' column='1' id='08f5ca19'>
         <underlying-type type-id='9cac1fee'/>
         <enumerator name='RTNL_LINK_INITIALIZED' value='0'/>
         <enumerator name='RTNL_LINK_INITIALIZING' value='1'/>
@@ -38978,48 +39024,48 @@
           <var-decl name='net' type-id='a2bff676' visibility='default' filepath='include/net/net_namespace.h' line='291' column='1'/>
         </data-member>
       </class-decl>
-      <union-decl name='__anonymous_union__16' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='2028' column='1' id='38feef9e'>
+      <union-decl name='__anonymous_union__16' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/linux/netdevice.h' line='2027' column='1' id='38feef9e'>
         <data-member access='public'>
-          <var-decl name='ml_priv' type-id='eaa32e2f' visibility='default' filepath='include/linux/netdevice.h' line='2029' column='1'/>
+          <var-decl name='ml_priv' type-id='eaa32e2f' visibility='default' filepath='include/linux/netdevice.h' line='2028' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='lstats' type-id='a42934eb' visibility='default' filepath='include/linux/netdevice.h' line='2030' column='1'/>
+          <var-decl name='lstats' type-id='a42934eb' visibility='default' filepath='include/linux/netdevice.h' line='2029' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='tstats' type-id='90cd86e5' visibility='default' filepath='include/linux/netdevice.h' line='2031' column='1'/>
+          <var-decl name='tstats' type-id='90cd86e5' visibility='default' filepath='include/linux/netdevice.h' line='2030' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='dstats' type-id='f59f5033' visibility='default' filepath='include/linux/netdevice.h' line='2032' column='1'/>
+          <var-decl name='dstats' type-id='f59f5033' visibility='default' filepath='include/linux/netdevice.h' line='2031' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='vstats' type-id='1200d79d' visibility='default' filepath='include/linux/netdevice.h' line='2033' column='1'/>
+          <var-decl name='vstats' type-id='1200d79d' visibility='default' filepath='include/linux/netdevice.h' line='2032' column='1'/>
         </data-member>
       </union-decl>
-      <class-decl name='pcpu_sw_netstats' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='2423' column='1' id='101eeec5'>
+      <class-decl name='pcpu_sw_netstats' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='2422' column='1' id='101eeec5'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='rx_packets' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2424' column='1'/>
+          <var-decl name='rx_packets' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2423' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='rx_bytes' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2425' column='1'/>
+          <var-decl name='rx_bytes' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2424' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='tx_packets' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2426' column='1'/>
+          <var-decl name='tx_packets' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2425' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='tx_bytes' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2427' column='1'/>
+          <var-decl name='tx_bytes' type-id='91ce1af9' visibility='default' filepath='include/linux/netdevice.h' line='2426' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='syncp' type-id='e4d85780' visibility='default' filepath='include/linux/netdevice.h' line='2428' column='1'/>
+          <var-decl name='syncp' type-id='e4d85780' visibility='default' filepath='include/linux/netdevice.h' line='2427' column='1'/>
         </data-member>
       </class-decl>
       <typedef-decl name='s16' type-id='b55def60' filepath='include/asm-generic/int-ll64.h' line='18' column='1' id='9b7e9486'/>
       <typedef-decl name='__s16' type-id='a2185560' filepath='include/uapi/asm-generic/int-ll64.h' line='23' column='1' id='b55def60'/>
-      <class-decl name='netdev_tc_txq' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='782' column='1' id='f1e1eb79'>
+      <class-decl name='netdev_tc_txq' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='785' column='1' id='f1e1eb79'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='count' type-id='1dc6a898' visibility='default' filepath='include/linux/netdevice.h' line='783' column='1'/>
+          <var-decl name='count' type-id='1dc6a898' visibility='default' filepath='include/linux/netdevice.h' line='786' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='offset' type-id='1dc6a898' visibility='default' filepath='include/linux/netdevice.h' line='784' column='1'/>
+          <var-decl name='offset' type-id='1dc6a898' visibility='default' filepath='include/linux/netdevice.h' line='787' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='netns_core' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/netns/core.h' line='8' column='1' id='7436aa2b'>
@@ -40204,10 +40250,10 @@
           <var-decl name='hooks_bridge' type-id='94310593' visibility='default' filepath='include/net/netns/netfilter.h' line='25' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2176'>
-          <var-decl name='defrag_ipv4' type-id='b50a4934' visibility='default' filepath='include/net/netns/netfilter.h' line='30' column='1'/>
+          <var-decl name='defrag_ipv4' type-id='b50a4934' visibility='default' filepath='include/net/netns/netfilter.h' line='27' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2184'>
-          <var-decl name='defrag_ipv6' type-id='b50a4934' visibility='default' filepath='include/net/netns/netfilter.h' line='33' column='1'/>
+          <var-decl name='defrag_ipv6' type-id='b50a4934' visibility='default' filepath='include/net/netns/netfilter.h' line='30' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='netns_xt' size-in-bits='1920' is-struct='yes' visibility='default' filepath='include/net/netns/x_tables.h' line='10' column='1' id='288fe7b8'>
@@ -44750,42 +44796,42 @@
         <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='127' column='1'/>
         <return type-id='7359adad'/>
       </function-decl>
-      <function-decl name='__pm_runtime_idle' mangled-name='__pm_runtime_idle' filepath='drivers/base/power/runtime.c' line='973' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__pm_runtime_idle'>
-        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='973' column='1'/>
-        <parameter type-id='95e97e5e' name='rpmflags' filepath='drivers/base/power/runtime.c' line='973' column='1'/>
+      <function-decl name='__pm_runtime_idle' mangled-name='__pm_runtime_idle' filepath='drivers/base/power/runtime.c' line='975' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__pm_runtime_idle'>
+        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='975' column='1'/>
+        <parameter type-id='95e97e5e' name='rpmflags' filepath='drivers/base/power/runtime.c' line='975' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='__pm_runtime_suspend' mangled-name='__pm_runtime_suspend' filepath='drivers/base/power/runtime.c' line='1005' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__pm_runtime_suspend'>
-        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='1005' column='1'/>
-        <parameter type-id='95e97e5e' name='rpmflags' filepath='drivers/base/power/runtime.c' line='1005' column='1'/>
+      <function-decl name='__pm_runtime_suspend' mangled-name='__pm_runtime_suspend' filepath='drivers/base/power/runtime.c' line='1007' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__pm_runtime_suspend'>
+        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='1007' column='1'/>
+        <parameter type-id='95e97e5e' name='rpmflags' filepath='drivers/base/power/runtime.c' line='1007' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='__pm_runtime_resume' mangled-name='__pm_runtime_resume' filepath='drivers/base/power/runtime.c' line='1036' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__pm_runtime_resume'>
-        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='1036' column='1'/>
-        <parameter type-id='95e97e5e' name='rpmflags' filepath='drivers/base/power/runtime.c' line='1036' column='1'/>
+      <function-decl name='__pm_runtime_resume' mangled-name='__pm_runtime_resume' filepath='drivers/base/power/runtime.c' line='1038' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__pm_runtime_resume'>
+        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='1038' column='1'/>
+        <parameter type-id='95e97e5e' name='rpmflags' filepath='drivers/base/power/runtime.c' line='1038' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='__pm_runtime_set_status' mangled-name='__pm_runtime_set_status' filepath='drivers/base/power/runtime.c' line='1096' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__pm_runtime_set_status'>
-        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='1096' column='1'/>
-        <parameter type-id='f0981eeb' name='status' filepath='drivers/base/power/runtime.c' line='1096' column='1'/>
+      <function-decl name='__pm_runtime_set_status' mangled-name='__pm_runtime_set_status' filepath='drivers/base/power/runtime.c' line='1098' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__pm_runtime_set_status'>
+        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='1098' column='1'/>
+        <parameter type-id='f0981eeb' name='status' filepath='drivers/base/power/runtime.c' line='1098' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='__pm_runtime_disable' mangled-name='__pm_runtime_disable' filepath='drivers/base/power/runtime.c' line='1253' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__pm_runtime_disable'>
-        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='1253' column='1'/>
-        <parameter type-id='b50a4934' name='check_resume' filepath='drivers/base/power/runtime.c' line='1253' column='1'/>
+      <function-decl name='__pm_runtime_disable' mangled-name='__pm_runtime_disable' filepath='drivers/base/power/runtime.c' line='1255' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__pm_runtime_disable'>
+        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='1255' column='1'/>
+        <parameter type-id='b50a4934' name='check_resume' filepath='drivers/base/power/runtime.c' line='1255' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='__pm_runtime_use_autosuspend' mangled-name='__pm_runtime_use_autosuspend' filepath='drivers/base/power/runtime.c' line='1464' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__pm_runtime_use_autosuspend'>
-        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='1464' column='1'/>
-        <parameter type-id='b50a4934' name='use' filepath='drivers/base/power/runtime.c' line='1464' column='1'/>
+      <function-decl name='__pm_runtime_use_autosuspend' mangled-name='__pm_runtime_use_autosuspend' filepath='drivers/base/power/runtime.c' line='1466' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__pm_runtime_use_autosuspend'>
+        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='1466' column='1'/>
+        <parameter type-id='b50a4934' name='use' filepath='drivers/base/power/runtime.c' line='1466' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='pm_runtime_force_suspend' mangled-name='pm_runtime_force_suspend' filepath='drivers/base/power/runtime.c' line='1658' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pm_runtime_force_suspend'>
-        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='1658' column='1'/>
+      <function-decl name='pm_runtime_force_suspend' mangled-name='pm_runtime_force_suspend' filepath='drivers/base/power/runtime.c' line='1660' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pm_runtime_force_suspend'>
+        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='1660' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='pm_runtime_force_resume' mangled-name='pm_runtime_force_resume' filepath='drivers/base/power/runtime.c' line='1704' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pm_runtime_force_resume'>
-        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='1704' column='1'/>
+      <function-decl name='pm_runtime_force_resume' mangled-name='pm_runtime_force_resume' filepath='drivers/base/power/runtime.c' line='1706' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pm_runtime_force_resume'>
+        <parameter type-id='fa0b179b' name='dev' filepath='drivers/base/power/runtime.c' line='1706' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
     </abi-instr>
@@ -46531,10 +46577,10 @@
         <parameter type-id='80f4b756' name='lock_name' filepath='drivers/base/regmap/regmap.c' line='662' column='1'/>
         <return type-id='29af9a71'/>
       </function-decl>
-      <function-decl name='regmap_register_patch' mangled-name='regmap_register_patch' filepath='drivers/base/regmap/regmap.c' line='2929' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_register_patch'>
-        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='2929' column='1'/>
-        <parameter type-id='0472a368' name='regs' filepath='drivers/base/regmap/regmap.c' line='2929' column='1'/>
-        <parameter type-id='95e97e5e' name='num_regs' filepath='drivers/base/regmap/regmap.c' line='2930' column='1'/>
+      <function-decl name='regmap_register_patch' mangled-name='regmap_register_patch' filepath='drivers/base/regmap/regmap.c' line='2931' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_register_patch'>
+        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='2931' column='1'/>
+        <parameter type-id='0472a368' name='regs' filepath='drivers/base/regmap/regmap.c' line='2931' column='1'/>
+        <parameter type-id='95e97e5e' name='num_regs' filepath='drivers/base/regmap/regmap.c' line='2932' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
       <function-decl name='hwspin_lock_request_specific' mangled-name='hwspin_lock_request_specific' filepath='include/linux/hwspinlock.h' line='61' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='hwspin_lock_request_specific'>
@@ -46560,69 +46606,69 @@
         <parameter type-id='d7d5e052' name='reg_field' filepath='drivers/base/regmap/regmap.c' line='1201' column='1'/>
         <return type-id='476eb32c'/>
       </function-decl>
-      <function-decl name='regmap_raw_write' mangled-name='regmap_raw_write' filepath='drivers/base/regmap/regmap.c' line='1875' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_raw_write'>
-        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='1875' column='1'/>
-        <parameter type-id='f0981eeb' name='reg' filepath='drivers/base/regmap/regmap.c' line='1875' column='1'/>
-        <parameter type-id='eaa32e2f' name='val' filepath='drivers/base/regmap/regmap.c' line='1876' column='1'/>
-        <parameter type-id='b59d7dce' name='val_len' filepath='drivers/base/regmap/regmap.c' line='1876' column='1'/>
+      <function-decl name='regmap_raw_write' mangled-name='regmap_raw_write' filepath='drivers/base/regmap/regmap.c' line='1877' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_raw_write'>
+        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='1877' column='1'/>
+        <parameter type-id='f0981eeb' name='reg' filepath='drivers/base/regmap/regmap.c' line='1877' column='1'/>
+        <parameter type-id='eaa32e2f' name='val' filepath='drivers/base/regmap/regmap.c' line='1878' column='1'/>
+        <parameter type-id='b59d7dce' name='val_len' filepath='drivers/base/regmap/regmap.c' line='1878' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='regmap_field_update_bits_base' mangled-name='regmap_field_update_bits_base' filepath='drivers/base/regmap/regmap.c' line='1912' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_field_update_bits_base'>
-        <parameter type-id='476eb32c' name='field' filepath='drivers/base/regmap/regmap.c' line='1912' column='1'/>
-        <parameter type-id='f0981eeb' name='mask' filepath='drivers/base/regmap/regmap.c' line='1913' column='1'/>
-        <parameter type-id='f0981eeb' name='val' filepath='drivers/base/regmap/regmap.c' line='1913' column='1'/>
-        <parameter type-id='d8e6b335' name='change' filepath='drivers/base/regmap/regmap.c' line='1914' column='1'/>
-        <parameter type-id='b50a4934' name='async' filepath='drivers/base/regmap/regmap.c' line='1914' column='1'/>
-        <parameter type-id='b50a4934' name='force' filepath='drivers/base/regmap/regmap.c' line='1914' column='1'/>
+      <function-decl name='regmap_field_update_bits_base' mangled-name='regmap_field_update_bits_base' filepath='drivers/base/regmap/regmap.c' line='1914' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_field_update_bits_base'>
+        <parameter type-id='476eb32c' name='field' filepath='drivers/base/regmap/regmap.c' line='1914' column='1'/>
+        <parameter type-id='f0981eeb' name='mask' filepath='drivers/base/regmap/regmap.c' line='1915' column='1'/>
+        <parameter type-id='f0981eeb' name='val' filepath='drivers/base/regmap/regmap.c' line='1915' column='1'/>
+        <parameter type-id='d8e6b335' name='change' filepath='drivers/base/regmap/regmap.c' line='1916' column='1'/>
+        <parameter type-id='b50a4934' name='async' filepath='drivers/base/regmap/regmap.c' line='1916' column='1'/>
+        <parameter type-id='b50a4934' name='force' filepath='drivers/base/regmap/regmap.c' line='1916' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='regmap_bulk_write' mangled-name='regmap_bulk_write' filepath='drivers/base/regmap/regmap.c' line='1969' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_bulk_write'>
-        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='1969' column='1'/>
-        <parameter type-id='f0981eeb' name='reg' filepath='drivers/base/regmap/regmap.c' line='1969' column='1'/>
-        <parameter type-id='eaa32e2f' name='val' filepath='drivers/base/regmap/regmap.c' line='1969' column='1'/>
-        <parameter type-id='b59d7dce' name='val_count' filepath='drivers/base/regmap/regmap.c' line='1970' column='1'/>
+      <function-decl name='regmap_bulk_write' mangled-name='regmap_bulk_write' filepath='drivers/base/regmap/regmap.c' line='1971' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_bulk_write'>
+        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='1971' column='1'/>
+        <parameter type-id='f0981eeb' name='reg' filepath='drivers/base/regmap/regmap.c' line='1971' column='1'/>
+        <parameter type-id='eaa32e2f' name='val' filepath='drivers/base/regmap/regmap.c' line='1971' column='1'/>
+        <parameter type-id='b59d7dce' name='val_count' filepath='drivers/base/regmap/regmap.c' line='1972' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='regmap_multi_reg_write' mangled-name='regmap_multi_reg_write' filepath='drivers/base/regmap/regmap.c' line='2268' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_multi_reg_write'>
-        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='2268' column='1'/>
-        <parameter type-id='0472a368' name='regs' filepath='drivers/base/regmap/regmap.c' line='2268' column='1'/>
-        <parameter type-id='95e97e5e' name='num_regs' filepath='drivers/base/regmap/regmap.c' line='2269' column='1'/>
+      <function-decl name='regmap_multi_reg_write' mangled-name='regmap_multi_reg_write' filepath='drivers/base/regmap/regmap.c' line='2270' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_multi_reg_write'>
+        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='2270' column='1'/>
+        <parameter type-id='0472a368' name='regs' filepath='drivers/base/regmap/regmap.c' line='2270' column='1'/>
+        <parameter type-id='95e97e5e' name='num_regs' filepath='drivers/base/regmap/regmap.c' line='2271' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='regmap_multi_reg_write_bypassed' mangled-name='regmap_multi_reg_write_bypassed' filepath='drivers/base/regmap/regmap.c' line='2301' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_multi_reg_write_bypassed'>
-        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='2301' column='1'/>
-        <parameter type-id='0472a368' name='regs' filepath='drivers/base/regmap/regmap.c' line='2302' column='1'/>
-        <parameter type-id='95e97e5e' name='num_regs' filepath='drivers/base/regmap/regmap.c' line='2303' column='1'/>
+      <function-decl name='regmap_multi_reg_write_bypassed' mangled-name='regmap_multi_reg_write_bypassed' filepath='drivers/base/regmap/regmap.c' line='2303' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_multi_reg_write_bypassed'>
+        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='2303' column='1'/>
+        <parameter type-id='0472a368' name='regs' filepath='drivers/base/regmap/regmap.c' line='2304' column='1'/>
+        <parameter type-id='95e97e5e' name='num_regs' filepath='drivers/base/regmap/regmap.c' line='2305' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='regmap_raw_write_async' mangled-name='regmap_raw_write_async' filepath='drivers/base/regmap/regmap.c' line='2345' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_raw_write_async'>
-        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='2345' column='1'/>
-        <parameter type-id='f0981eeb' name='reg' filepath='drivers/base/regmap/regmap.c' line='2345' column='1'/>
-        <parameter type-id='eaa32e2f' name='val' filepath='drivers/base/regmap/regmap.c' line='2346' column='1'/>
-        <parameter type-id='b59d7dce' name='val_len' filepath='drivers/base/regmap/regmap.c' line='2346' column='1'/>
+      <function-decl name='regmap_raw_write_async' mangled-name='regmap_raw_write_async' filepath='drivers/base/regmap/regmap.c' line='2347' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_raw_write_async'>
+        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='2347' column='1'/>
+        <parameter type-id='f0981eeb' name='reg' filepath='drivers/base/regmap/regmap.c' line='2347' column='1'/>
+        <parameter type-id='eaa32e2f' name='val' filepath='drivers/base/regmap/regmap.c' line='2348' column='1'/>
+        <parameter type-id='b59d7dce' name='val_len' filepath='drivers/base/regmap/regmap.c' line='2348' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='regmap_raw_read' mangled-name='regmap_raw_read' filepath='drivers/base/regmap/regmap.c' line='2500' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_raw_read'>
-        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='2500' column='1'/>
-        <parameter type-id='f0981eeb' name='reg' filepath='drivers/base/regmap/regmap.c' line='2500' column='1'/>
-        <parameter type-id='eaa32e2f' name='val' filepath='drivers/base/regmap/regmap.c' line='2500' column='1'/>
-        <parameter type-id='b59d7dce' name='val_len' filepath='drivers/base/regmap/regmap.c' line='2501' column='1'/>
+      <function-decl name='regmap_raw_read' mangled-name='regmap_raw_read' filepath='drivers/base/regmap/regmap.c' line='2502' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_raw_read'>
+        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='2502' column='1'/>
+        <parameter type-id='f0981eeb' name='reg' filepath='drivers/base/regmap/regmap.c' line='2502' column='1'/>
+        <parameter type-id='eaa32e2f' name='val' filepath='drivers/base/regmap/regmap.c' line='2502' column='1'/>
+        <parameter type-id='b59d7dce' name='val_len' filepath='drivers/base/regmap/regmap.c' line='2503' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='regmap_field_read' mangled-name='regmap_field_read' filepath='drivers/base/regmap/regmap.c' line='2647' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_field_read'>
-        <parameter type-id='476eb32c' name='field' filepath='drivers/base/regmap/regmap.c' line='2647' column='1'/>
-        <parameter type-id='807869d3' name='val' filepath='drivers/base/regmap/regmap.c' line='2647' column='1'/>
+      <function-decl name='regmap_field_read' mangled-name='regmap_field_read' filepath='drivers/base/regmap/regmap.c' line='2649' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_field_read'>
+        <parameter type-id='476eb32c' name='field' filepath='drivers/base/regmap/regmap.c' line='2649' column='1'/>
+        <parameter type-id='807869d3' name='val' filepath='drivers/base/regmap/regmap.c' line='2649' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='regmap_bulk_read' mangled-name='regmap_bulk_read' filepath='drivers/base/regmap/regmap.c' line='2707' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_bulk_read'>
-        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='2707' column='1'/>
-        <parameter type-id='f0981eeb' name='reg' filepath='drivers/base/regmap/regmap.c' line='2707' column='1'/>
-        <parameter type-id='eaa32e2f' name='val' filepath='drivers/base/regmap/regmap.c' line='2707' column='1'/>
-        <parameter type-id='b59d7dce' name='val_count' filepath='drivers/base/regmap/regmap.c' line='2708' column='1'/>
+      <function-decl name='regmap_bulk_read' mangled-name='regmap_bulk_read' filepath='drivers/base/regmap/regmap.c' line='2709' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_bulk_read'>
+        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='2709' column='1'/>
+        <parameter type-id='f0981eeb' name='reg' filepath='drivers/base/regmap/regmap.c' line='2709' column='1'/>
+        <parameter type-id='eaa32e2f' name='val' filepath='drivers/base/regmap/regmap.c' line='2709' column='1'/>
+        <parameter type-id='b59d7dce' name='val_count' filepath='drivers/base/regmap/regmap.c' line='2710' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='regmap_async_complete' mangled-name='regmap_async_complete' filepath='drivers/base/regmap/regmap.c' line='2888' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_async_complete'>
-        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='2888' column='1'/>
+      <function-decl name='regmap_async_complete' mangled-name='regmap_async_complete' filepath='drivers/base/regmap/regmap.c' line='2890' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='regmap_async_complete'>
+        <parameter type-id='29af9a71' name='map' filepath='drivers/base/regmap/regmap.c' line='2890' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
       <pointer-type-def type-id='b50a4934' size-in-bits='64' id='d8e6b335'/>
@@ -47012,24 +47058,24 @@
         </data-member>
       </class-decl>
       <pointer-type-def type-id='830e3b1b' size-in-bits='64' id='7d0bc0eb'/>
-      <function-decl name='devm_clk_get' mangled-name='devm_clk_get' filepath='include/linux/clk.h' line='349' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devm_clk_get'>
+      <function-decl name='devm_clk_get' mangled-name='devm_clk_get' filepath='include/linux/clk.h' line='389' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devm_clk_get'>
         <parameter type-id='fa0b179b'/>
         <parameter type-id='80f4b756'/>
         <return type-id='7d0bc0eb'/>
       </function-decl>
-      <function-decl name='clk_prepare' mangled-name='clk_prepare' filepath='include/linux/clk.h' line='235' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_prepare'>
+      <function-decl name='clk_prepare' mangled-name='clk_prepare' filepath='include/linux/clk.h' line='275' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_prepare'>
         <parameter type-id='7d0bc0eb'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='clk_enable' mangled-name='clk_enable' filepath='include/linux/clk.h' line='410' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_enable'>
+      <function-decl name='clk_enable' mangled-name='clk_enable' filepath='include/linux/clk.h' line='418' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_enable'>
         <parameter type-id='7d0bc0eb'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='clk_unprepare' mangled-name='clk_unprepare' filepath='include/linux/clk.h' line='262' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_unprepare'>
+      <function-decl name='clk_unprepare' mangled-name='clk_unprepare' filepath='include/linux/clk.h' line='302' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_unprepare'>
         <parameter type-id='7d0bc0eb'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='clk_disable' mangled-name='clk_disable' filepath='include/linux/clk.h' line='438' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_disable'>
+      <function-decl name='clk_disable' mangled-name='clk_disable' filepath='include/linux/clk.h' line='446' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_disable'>
         <parameter type-id='7d0bc0eb'/>
         <return type-id='48b5725f'/>
       </function-decl>
@@ -47193,13 +47239,13 @@
         <parameter type-id='2942e355' name='clks' filepath='drivers/clk/clk-devres.c' line='50' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='clk_bulk_get' mangled-name='clk_bulk_get' filepath='include/linux/clk.h' line='313' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_bulk_get'>
+      <function-decl name='clk_bulk_get' mangled-name='clk_bulk_get' filepath='include/linux/clk.h' line='353' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_bulk_get'>
         <parameter type-id='fa0b179b'/>
         <parameter type-id='95e97e5e'/>
         <parameter type-id='2942e355'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='clk_bulk_put' mangled-name='clk_bulk_put' filepath='include/linux/clk.h' line='488' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_bulk_put'>
+      <function-decl name='clk_bulk_put' mangled-name='clk_bulk_put' filepath='include/linux/clk.h' line='496' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_bulk_put'>
         <parameter type-id='95e97e5e'/>
         <parameter type-id='2942e355'/>
         <return type-id='48b5725f'/>
@@ -48970,12 +49016,12 @@
       <pointer-type-def type-id='7fd43619' size-in-bits='64' id='ff2d9ea5'/>
     </abi-instr>
     <abi-instr address-size='64' path='drivers/cpufreq/scpi-cpufreq.c' language='LANG_C89'>
-      <function-decl name='clk_get' mangled-name='clk_get' filepath='include/linux/clk.h' line='291' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_get'>
+      <function-decl name='clk_get' mangled-name='clk_get' filepath='include/linux/clk.h' line='331' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_get'>
         <parameter type-id='fa0b179b'/>
         <parameter type-id='80f4b756'/>
         <return type-id='7d0bc0eb'/>
       </function-decl>
-      <function-decl name='clk_put' mangled-name='clk_put' filepath='include/linux/clk.h' line='475' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_put'>
+      <function-decl name='clk_put' mangled-name='clk_put' filepath='include/linux/clk.h' line='483' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_put'>
         <parameter type-id='7d0bc0eb'/>
         <return type-id='48b5725f'/>
       </function-decl>
@@ -49345,30 +49391,30 @@
       <pointer-type-def type-id='1eb56b1e' size-in-bits='64' id='8b97c2dc'/>
     </abi-instr>
     <abi-instr address-size='64' path='drivers/devfreq/devfreq.c' language='LANG_C89'>
-      <function-decl name='devfreq_add_device' mangled-name='devfreq_add_device' filepath='drivers/devfreq/devfreq.c' line='595' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devfreq_add_device'>
-        <parameter type-id='fa0b179b' name='dev' filepath='drivers/devfreq/devfreq.c' line='595' column='1'/>
-        <parameter type-id='cba10b6e' name='profile' filepath='drivers/devfreq/devfreq.c' line='596' column='1'/>
-        <parameter type-id='80f4b756' name='governor_name' filepath='drivers/devfreq/devfreq.c' line='597' column='1'/>
-        <parameter type-id='eaa32e2f' name='data' filepath='drivers/devfreq/devfreq.c' line='598' column='1'/>
+      <function-decl name='devfreq_add_device' mangled-name='devfreq_add_device' filepath='drivers/devfreq/devfreq.c' line='596' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devfreq_add_device'>
+        <parameter type-id='fa0b179b' name='dev' filepath='drivers/devfreq/devfreq.c' line='596' column='1'/>
+        <parameter type-id='cba10b6e' name='profile' filepath='drivers/devfreq/devfreq.c' line='597' column='1'/>
+        <parameter type-id='80f4b756' name='governor_name' filepath='drivers/devfreq/devfreq.c' line='598' column='1'/>
+        <parameter type-id='eaa32e2f' name='data' filepath='drivers/devfreq/devfreq.c' line='599' column='1'/>
         <return type-id='f66fa7f4'/>
       </function-decl>
-      <function-decl name='devfreq_remove_device' mangled-name='devfreq_remove_device' filepath='drivers/devfreq/devfreq.c' line='727' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devfreq_remove_device'>
-        <parameter type-id='f66fa7f4' name='devfreq' filepath='drivers/devfreq/devfreq.c' line='727' column='1'/>
+      <function-decl name='devfreq_remove_device' mangled-name='devfreq_remove_device' filepath='drivers/devfreq/devfreq.c' line='728' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devfreq_remove_device'>
+        <parameter type-id='f66fa7f4' name='devfreq' filepath='drivers/devfreq/devfreq.c' line='728' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='devm_devfreq_add_device' mangled-name='devm_devfreq_add_device' filepath='drivers/devfreq/devfreq.c' line='768' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devm_devfreq_add_device'>
-        <parameter type-id='fa0b179b' name='dev' filepath='drivers/devfreq/devfreq.c' line='768' column='1'/>
-        <parameter type-id='cba10b6e' name='profile' filepath='drivers/devfreq/devfreq.c' line='769' column='1'/>
-        <parameter type-id='80f4b756' name='governor_name' filepath='drivers/devfreq/devfreq.c' line='770' column='1'/>
-        <parameter type-id='eaa32e2f' name='data' filepath='drivers/devfreq/devfreq.c' line='771' column='1'/>
+      <function-decl name='devm_devfreq_add_device' mangled-name='devm_devfreq_add_device' filepath='drivers/devfreq/devfreq.c' line='769' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devm_devfreq_add_device'>
+        <parameter type-id='fa0b179b' name='dev' filepath='drivers/devfreq/devfreq.c' line='769' column='1'/>
+        <parameter type-id='cba10b6e' name='profile' filepath='drivers/devfreq/devfreq.c' line='770' column='1'/>
+        <parameter type-id='80f4b756' name='governor_name' filepath='drivers/devfreq/devfreq.c' line='771' column='1'/>
+        <parameter type-id='eaa32e2f' name='data' filepath='drivers/devfreq/devfreq.c' line='772' column='1'/>
         <return type-id='f66fa7f4'/>
       </function-decl>
-      <function-decl name='devfreq_suspend_device' mangled-name='devfreq_suspend_device' filepath='drivers/devfreq/devfreq.c' line='857' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devfreq_suspend_device'>
-        <parameter type-id='f66fa7f4' name='devfreq' filepath='drivers/devfreq/devfreq.c' line='857' column='1'/>
+      <function-decl name='devfreq_suspend_device' mangled-name='devfreq_suspend_device' filepath='drivers/devfreq/devfreq.c' line='858' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devfreq_suspend_device'>
+        <parameter type-id='f66fa7f4' name='devfreq' filepath='drivers/devfreq/devfreq.c' line='858' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='devfreq_resume_device' mangled-name='devfreq_resume_device' filepath='drivers/devfreq/devfreq.c' line='887' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devfreq_resume_device'>
-        <parameter type-id='f66fa7f4' name='devfreq' filepath='drivers/devfreq/devfreq.c' line='887' column='1'/>
+      <function-decl name='devfreq_resume_device' mangled-name='devfreq_resume_device' filepath='drivers/devfreq/devfreq.c' line='888' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devfreq_resume_device'>
+        <parameter type-id='f66fa7f4' name='devfreq' filepath='drivers/devfreq/devfreq.c' line='888' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
       <pointer-type-def type-id='f80c018e' size-in-bits='64' id='f66fa7f4'/>
@@ -50661,48 +50707,48 @@
       </class-decl>
       <pointer-type-def type-id='103b4c26' size-in-bits='64' id='e07a8e4c'/>
       <pointer-type-def type-id='96e74f5f' size-in-bits='64' id='dc20ab67'/>
-      <class-decl name='extcon_cable' size-in-bits='1664' is-struct='yes' visibility='default' filepath='drivers/extcon/extcon.c' line='208' column='1' id='103b4c26'>
+      <class-decl name='extcon_cable' size-in-bits='1664' is-struct='yes' visibility='default' filepath='drivers/extcon/extcon.c' line='216' column='1' id='103b4c26'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='edev' type-id='c0d6fada' visibility='default' filepath='drivers/extcon/extcon.c' line='209' column='1'/>
+          <var-decl name='edev' type-id='c0d6fada' visibility='default' filepath='drivers/extcon/extcon.c' line='217' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='cable_index' type-id='95e97e5e' visibility='default' filepath='drivers/extcon/extcon.c' line='210' column='1'/>
+          <var-decl name='cable_index' type-id='95e97e5e' visibility='default' filepath='drivers/extcon/extcon.c' line='218' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='attr_g' type-id='e4af473b' visibility='default' filepath='drivers/extcon/extcon.c' line='212' column='1'/>
+          <var-decl name='attr_g' type-id='e4af473b' visibility='default' filepath='drivers/extcon/extcon.c' line='220' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='attr_name' type-id='dbf3947c' visibility='default' filepath='drivers/extcon/extcon.c' line='213' column='1'/>
+          <var-decl name='attr_name' type-id='dbf3947c' visibility='default' filepath='drivers/extcon/extcon.c' line='221' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='attr_state' type-id='dbf3947c' visibility='default' filepath='drivers/extcon/extcon.c' line='214' column='1'/>
+          <var-decl name='attr_state' type-id='dbf3947c' visibility='default' filepath='drivers/extcon/extcon.c' line='222' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='attrs' type-id='ff62a050' visibility='default' filepath='drivers/extcon/extcon.c' line='216' column='1'/>
+          <var-decl name='attrs' type-id='ff62a050' visibility='default' filepath='drivers/extcon/extcon.c' line='224' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='usb_propval' type-id='476b9520' visibility='default' filepath='drivers/extcon/extcon.c' line='218' column='1'/>
+          <var-decl name='usb_propval' type-id='476b9520' visibility='default' filepath='drivers/extcon/extcon.c' line='226' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='chg_propval' type-id='0b5e6ab9' visibility='default' filepath='drivers/extcon/extcon.c' line='219' column='1'/>
+          <var-decl name='chg_propval' type-id='0b5e6ab9' visibility='default' filepath='drivers/extcon/extcon.c' line='227' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1312'>
-          <var-decl name='jack_propval' type-id='0b5e6ab9' visibility='default' filepath='drivers/extcon/extcon.c' line='220' column='1'/>
+          <var-decl name='jack_propval' type-id='0b5e6ab9' visibility='default' filepath='drivers/extcon/extcon.c' line='228' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='disp_propval' type-id='0b5c2c22' visibility='default' filepath='drivers/extcon/extcon.c' line='221' column='1'/>
+          <var-decl name='disp_propval' type-id='0b5c2c22' visibility='default' filepath='drivers/extcon/extcon.c' line='229' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='usb_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='223' column='1'/>
+          <var-decl name='usb_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='231' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1472'>
-          <var-decl name='chg_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='224' column='1'/>
+          <var-decl name='chg_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='232' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='jack_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='225' column='1'/>
+          <var-decl name='jack_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='233' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1600'>
-          <var-decl name='disp_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='226' column='1'/>
+          <var-decl name='disp_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='234' column='1'/>
         </data-member>
       </class-decl>
       <array-type-def dimensions='1' type-id='0b001c1f' size-in-bits='192' id='ff62a050'>
@@ -50736,48 +50782,48 @@
       <array-type-def dimensions='1' type-id='282b2805' size-in-bits='128' id='476b9520'>
         <subrange length='4' type-id='7ff19f0f' id='16fe7105'/>
       </array-type-def>
-      <class-decl name='extcon_cable' size-in-bits='1664' is-struct='yes' visibility='default' filepath='drivers/extcon/extcon.c' line='208' column='1' id='103b4c26'>
+      <class-decl name='extcon_cable' size-in-bits='1664' is-struct='yes' visibility='default' filepath='drivers/extcon/extcon.c' line='216' column='1' id='103b4c26'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='edev' type-id='c0d6fada' visibility='default' filepath='drivers/extcon/extcon.c' line='209' column='1'/>
+          <var-decl name='edev' type-id='c0d6fada' visibility='default' filepath='drivers/extcon/extcon.c' line='217' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='cable_index' type-id='95e97e5e' visibility='default' filepath='drivers/extcon/extcon.c' line='210' column='1'/>
+          <var-decl name='cable_index' type-id='95e97e5e' visibility='default' filepath='drivers/extcon/extcon.c' line='218' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='attr_g' type-id='e4af473b' visibility='default' filepath='drivers/extcon/extcon.c' line='212' column='1'/>
+          <var-decl name='attr_g' type-id='e4af473b' visibility='default' filepath='drivers/extcon/extcon.c' line='220' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='attr_name' type-id='dbf3947c' visibility='default' filepath='drivers/extcon/extcon.c' line='213' column='1'/>
+          <var-decl name='attr_name' type-id='dbf3947c' visibility='default' filepath='drivers/extcon/extcon.c' line='221' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='attr_state' type-id='dbf3947c' visibility='default' filepath='drivers/extcon/extcon.c' line='214' column='1'/>
+          <var-decl name='attr_state' type-id='dbf3947c' visibility='default' filepath='drivers/extcon/extcon.c' line='222' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='attrs' type-id='ff62a050' visibility='default' filepath='drivers/extcon/extcon.c' line='216' column='1'/>
+          <var-decl name='attrs' type-id='ff62a050' visibility='default' filepath='drivers/extcon/extcon.c' line='224' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='usb_propval' type-id='476b9520' visibility='default' filepath='drivers/extcon/extcon.c' line='218' column='1'/>
+          <var-decl name='usb_propval' type-id='476b9520' visibility='default' filepath='drivers/extcon/extcon.c' line='226' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='chg_propval' type-id='0b5e6ab9' visibility='default' filepath='drivers/extcon/extcon.c' line='219' column='1'/>
+          <var-decl name='chg_propval' type-id='0b5e6ab9' visibility='default' filepath='drivers/extcon/extcon.c' line='227' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1312'>
-          <var-decl name='jack_propval' type-id='0b5e6ab9' visibility='default' filepath='drivers/extcon/extcon.c' line='220' column='1'/>
+          <var-decl name='jack_propval' type-id='0b5e6ab9' visibility='default' filepath='drivers/extcon/extcon.c' line='228' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='disp_propval' type-id='0b5c2c22' visibility='default' filepath='drivers/extcon/extcon.c' line='221' column='1'/>
+          <var-decl name='disp_propval' type-id='0b5c2c22' visibility='default' filepath='drivers/extcon/extcon.c' line='229' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='usb_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='223' column='1'/>
+          <var-decl name='usb_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='231' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1472'>
-          <var-decl name='chg_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='224' column='1'/>
+          <var-decl name='chg_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='232' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='jack_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='225' column='1'/>
+          <var-decl name='jack_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='233' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1600'>
-          <var-decl name='disp_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='226' column='1'/>
+          <var-decl name='disp_bits' type-id='f066dd3c' visibility='default' filepath='drivers/extcon/extcon.c' line='234' column='1'/>
         </data-member>
       </class-decl>
       <union-decl name='extcon_property_value' size-in-bits='32' visibility='default' filepath='include/linux/extcon.h' line='175' column='1' id='282b2805'>
@@ -50787,56 +50833,56 @@
       </union-decl>
       <pointer-type-def type-id='103b4c26' size-in-bits='64' id='e07a8e4c'/>
       <pointer-type-def type-id='282b2805' size-in-bits='64' id='50842338'/>
-      <function-decl name='extcon_set_state_sync' mangled-name='extcon_set_state_sync' filepath='drivers/extcon/extcon.c' line='600' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_set_state_sync'>
-        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='600' column='1'/>
-        <parameter type-id='f0981eeb' name='id' filepath='drivers/extcon/extcon.c' line='600' column='1'/>
-        <parameter type-id='b50a4934' name='state' filepath='drivers/extcon/extcon.c' line='600' column='1'/>
+      <function-decl name='extcon_set_state_sync' mangled-name='extcon_set_state_sync' filepath='drivers/extcon/extcon.c' line='608' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_set_state_sync'>
+        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='608' column='1'/>
+        <parameter type-id='f0981eeb' name='id' filepath='drivers/extcon/extcon.c' line='608' column='1'/>
+        <parameter type-id='b50a4934' name='state' filepath='drivers/extcon/extcon.c' line='608' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='extcon_get_property' mangled-name='extcon_get_property' filepath='drivers/extcon/extcon.c' line='638' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_get_property'>
-        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='638' column='1'/>
-        <parameter type-id='f0981eeb' name='id' filepath='drivers/extcon/extcon.c' line='638' column='1'/>
-        <parameter type-id='f0981eeb' name='prop' filepath='drivers/extcon/extcon.c' line='639' column='1'/>
-        <parameter type-id='50842338' name='prop_val' filepath='drivers/extcon/extcon.c' line='640' column='1'/>
+      <function-decl name='extcon_get_property' mangled-name='extcon_get_property' filepath='drivers/extcon/extcon.c' line='646' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_get_property'>
+        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='646' column='1'/>
+        <parameter type-id='f0981eeb' name='id' filepath='drivers/extcon/extcon.c' line='646' column='1'/>
+        <parameter type-id='f0981eeb' name='prop' filepath='drivers/extcon/extcon.c' line='647' column='1'/>
+        <parameter type-id='50842338' name='prop_val' filepath='drivers/extcon/extcon.c' line='648' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='extcon_set_property' mangled-name='extcon_set_property' filepath='drivers/extcon/extcon.c' line='717' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_set_property'>
-        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='717' column='1'/>
-        <parameter type-id='f0981eeb' name='id' filepath='drivers/extcon/extcon.c' line='717' column='1'/>
-        <parameter type-id='f0981eeb' name='prop' filepath='drivers/extcon/extcon.c' line='718' column='1'/>
-        <parameter type-id='282b2805' name='prop_val' filepath='drivers/extcon/extcon.c' line='719' column='1'/>
+      <function-decl name='extcon_set_property' mangled-name='extcon_set_property' filepath='drivers/extcon/extcon.c' line='725' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_set_property'>
+        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='725' column='1'/>
+        <parameter type-id='f0981eeb' name='id' filepath='drivers/extcon/extcon.c' line='725' column='1'/>
+        <parameter type-id='f0981eeb' name='prop' filepath='drivers/extcon/extcon.c' line='726' column='1'/>
+        <parameter type-id='282b2805' name='prop_val' filepath='drivers/extcon/extcon.c' line='727' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='extcon_set_property_capability' mangled-name='extcon_set_property_capability' filepath='drivers/extcon/extcon.c' line='839' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_set_property_capability'>
-        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='839' column='1'/>
-        <parameter type-id='f0981eeb' name='id' filepath='drivers/extcon/extcon.c' line='839' column='1'/>
-        <parameter type-id='f0981eeb' name='prop' filepath='drivers/extcon/extcon.c' line='840' column='1'/>
+      <function-decl name='extcon_set_property_capability' mangled-name='extcon_set_property_capability' filepath='drivers/extcon/extcon.c' line='847' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_set_property_capability'>
+        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='847' column='1'/>
+        <parameter type-id='f0981eeb' name='id' filepath='drivers/extcon/extcon.c' line='847' column='1'/>
+        <parameter type-id='f0981eeb' name='prop' filepath='drivers/extcon/extcon.c' line='848' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='extcon_register_notifier' mangled-name='extcon_register_notifier' filepath='drivers/extcon/extcon.c' line='922' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_register_notifier'>
-        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='922' column='1'/>
-        <parameter type-id='f0981eeb' name='id' filepath='drivers/extcon/extcon.c' line='922' column='1'/>
-        <parameter type-id='d504f73d' name='nb' filepath='drivers/extcon/extcon.c' line='923' column='1'/>
+      <function-decl name='extcon_register_notifier' mangled-name='extcon_register_notifier' filepath='drivers/extcon/extcon.c' line='930' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_register_notifier'>
+        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='930' column='1'/>
+        <parameter type-id='f0981eeb' name='id' filepath='drivers/extcon/extcon.c' line='930' column='1'/>
+        <parameter type-id='d504f73d' name='nb' filepath='drivers/extcon/extcon.c' line='931' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='extcon_register_blocking_notifier' mangled-name='extcon_register_blocking_notifier' filepath='drivers/extcon/extcon.c' line='943' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_register_blocking_notifier'>
-        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='943' column='1'/>
-        <parameter type-id='f0981eeb' name='id' filepath='drivers/extcon/extcon.c' line='943' column='1'/>
-        <parameter type-id='d504f73d' name='nb' filepath='drivers/extcon/extcon.c' line='944' column='1'/>
+      <function-decl name='extcon_register_blocking_notifier' mangled-name='extcon_register_blocking_notifier' filepath='drivers/extcon/extcon.c' line='951' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_register_blocking_notifier'>
+        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='951' column='1'/>
+        <parameter type-id='f0981eeb' name='id' filepath='drivers/extcon/extcon.c' line='951' column='1'/>
+        <parameter type-id='d504f73d' name='nb' filepath='drivers/extcon/extcon.c' line='952' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='extcon_unregister_notifier' mangled-name='extcon_unregister_notifier' filepath='drivers/extcon/extcon.c' line='983' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_unregister_notifier'>
-        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='983' column='1'/>
-        <parameter type-id='f0981eeb' name='id' filepath='drivers/extcon/extcon.c' line='983' column='1'/>
-        <parameter type-id='d504f73d' name='nb' filepath='drivers/extcon/extcon.c' line='984' column='1'/>
+      <function-decl name='extcon_unregister_notifier' mangled-name='extcon_unregister_notifier' filepath='drivers/extcon/extcon.c' line='991' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_unregister_notifier'>
+        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='991' column='1'/>
+        <parameter type-id='f0981eeb' name='id' filepath='drivers/extcon/extcon.c' line='991' column='1'/>
+        <parameter type-id='d504f73d' name='nb' filepath='drivers/extcon/extcon.c' line='992' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='extcon_find_edev_by_node' mangled-name='extcon_find_edev_by_node' filepath='drivers/extcon/extcon.c' line='1413' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_find_edev_by_node'>
-        <parameter type-id='9a537bbe' name='node' filepath='drivers/extcon/extcon.c' line='1413' column='1'/>
+      <function-decl name='extcon_find_edev_by_node' mangled-name='extcon_find_edev_by_node' filepath='drivers/extcon/extcon.c' line='1421' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_find_edev_by_node'>
+        <parameter type-id='9a537bbe' name='node' filepath='drivers/extcon/extcon.c' line='1421' column='1'/>
         <return type-id='c0d6fada'/>
       </function-decl>
-      <function-decl name='extcon_get_edev_name' mangled-name='extcon_get_edev_name' filepath='drivers/extcon/extcon.c' line='1482' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_get_edev_name'>
-        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='1482' column='1'/>
+      <function-decl name='extcon_get_edev_name' mangled-name='extcon_get_edev_name' filepath='drivers/extcon/extcon.c' line='1490' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='extcon_get_edev_name'>
+        <parameter type-id='c0d6fada' name='edev' filepath='drivers/extcon/extcon.c' line='1490' column='1'/>
         <return type-id='80f4b756'/>
       </function-decl>
     </abi-instr>
@@ -56334,22 +56380,22 @@
         <parameter type-id='e3dd029e' name='state' filepath='drivers/gpu/drm/drm_atomic.c' line='76' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='drm_atomic_state_default_clear' mangled-name='drm_atomic_state_default_clear' filepath='drivers/gpu/drm/drm_atomic.c' line='141' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='drm_atomic_state_default_clear'>
-        <parameter type-id='e3dd029e' name='state' filepath='drivers/gpu/drm/drm_atomic.c' line='141' column='1'/>
+      <function-decl name='drm_atomic_state_default_clear' mangled-name='drm_atomic_state_default_clear' filepath='drivers/gpu/drm/drm_atomic.c' line='147' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='drm_atomic_state_default_clear'>
+        <parameter type-id='e3dd029e' name='state' filepath='drivers/gpu/drm/drm_atomic.c' line='147' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='drm_atomic_state_clear' mangled-name='drm_atomic_state_clear' filepath='drivers/gpu/drm/drm_atomic.c' line='231' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='drm_atomic_state_clear'>
-        <parameter type-id='e3dd029e' name='state' filepath='drivers/gpu/drm/drm_atomic.c' line='231' column='1'/>
+      <function-decl name='drm_atomic_state_clear' mangled-name='drm_atomic_state_clear' filepath='drivers/gpu/drm/drm_atomic.c' line='237' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='drm_atomic_state_clear'>
+        <parameter type-id='e3dd029e' name='state' filepath='drivers/gpu/drm/drm_atomic.c' line='237' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='__drm_atomic_state_free' mangled-name='__drm_atomic_state_free' filepath='drivers/gpu/drm/drm_atomic.c' line='250' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__drm_atomic_state_free'>
-        <parameter type-id='aa29ecab' name='ref' filepath='drivers/gpu/drm/drm_atomic.c' line='250' column='1'/>
+      <function-decl name='__drm_atomic_state_free' mangled-name='__drm_atomic_state_free' filepath='drivers/gpu/drm/drm_atomic.c' line='256' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__drm_atomic_state_free'>
+        <parameter type-id='aa29ecab' name='ref' filepath='drivers/gpu/drm/drm_atomic.c' line='256' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='drm_atomic_private_obj_init' mangled-name='drm_atomic_private_obj_init' filepath='drivers/gpu/drm/drm_atomic.c' line='1176' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='drm_atomic_private_obj_init'>
-        <parameter type-id='11c98e9a' name='obj' filepath='drivers/gpu/drm/drm_atomic.c' line='1176' column='1'/>
-        <parameter type-id='4ea020ae' name='state' filepath='drivers/gpu/drm/drm_atomic.c' line='1177' column='1'/>
-        <parameter type-id='515fa1af' name='funcs' filepath='drivers/gpu/drm/drm_atomic.c' line='1178' column='1'/>
+      <function-decl name='drm_atomic_private_obj_init' mangled-name='drm_atomic_private_obj_init' filepath='drivers/gpu/drm/drm_atomic.c' line='1185' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='drm_atomic_private_obj_init'>
+        <parameter type-id='11c98e9a' name='obj' filepath='drivers/gpu/drm/drm_atomic.c' line='1185' column='1'/>
+        <parameter type-id='4ea020ae' name='state' filepath='drivers/gpu/drm/drm_atomic.c' line='1186' column='1'/>
+        <parameter type-id='515fa1af' name='funcs' filepath='drivers/gpu/drm/drm_atomic.c' line='1187' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
       <function-decl name='sync_file_get_fence' mangled-name='sync_file_get_fence' filepath='include/linux/sync_file.h' line='59' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sync_file_get_fence'>
@@ -62642,9 +62688,9 @@
         <parameter type-id='c91d1bf1' name='edid' filepath='drivers/gpu/drm/drm_edid.c' line='1488' column='1'/>
         <return type-id='b50a4934'/>
       </function-decl>
-      <function-decl name='drm_add_edid_modes' mangled-name='drm_add_edid_modes' filepath='drivers/gpu/drm/drm_edid.c' line='5094' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='drm_add_edid_modes'>
-        <parameter type-id='4db02c58' name='connector' filepath='drivers/gpu/drm/drm_edid.c' line='5094' column='1'/>
-        <parameter type-id='c91d1bf1' name='edid' filepath='drivers/gpu/drm/drm_edid.c' line='5094' column='1'/>
+      <function-decl name='drm_add_edid_modes' mangled-name='drm_add_edid_modes' filepath='drivers/gpu/drm/drm_edid.c' line='5096' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='drm_add_edid_modes'>
+        <parameter type-id='4db02c58' name='connector' filepath='drivers/gpu/drm/drm_edid.c' line='5096' column='1'/>
+        <parameter type-id='c91d1bf1' name='edid' filepath='drivers/gpu/drm/drm_edid.c' line='5096' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
       <function-decl name='drm_do_get_edid' mangled-name='drm_do_get_edid' filepath='drivers/gpu/drm/drm_edid.c' line='1660' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='drm_do_get_edid'>
@@ -62653,14 +62699,14 @@
         <parameter type-id='eaa32e2f' name='data' filepath='drivers/gpu/drm/drm_edid.c' line='1663' column='1'/>
         <return type-id='c91d1bf1'/>
       </function-decl>
-      <function-decl name='drm_detect_hdmi_monitor' mangled-name='drm_detect_hdmi_monitor' filepath='drivers/gpu/drm/drm_edid.c' line='4576' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='drm_detect_hdmi_monitor'>
-        <parameter type-id='c91d1bf1' name='edid' filepath='drivers/gpu/drm/drm_edid.c' line='4576' column='1'/>
+      <function-decl name='drm_detect_hdmi_monitor' mangled-name='drm_detect_hdmi_monitor' filepath='drivers/gpu/drm/drm_edid.c' line='4578' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='drm_detect_hdmi_monitor'>
+        <parameter type-id='c91d1bf1' name='edid' filepath='drivers/gpu/drm/drm_edid.c' line='4578' column='1'/>
         <return type-id='b50a4934'/>
       </function-decl>
-      <function-decl name='drm_set_preferred_mode' mangled-name='drm_set_preferred_mode' filepath='drivers/gpu/drm/drm_edid.c' line='5219' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='drm_set_preferred_mode'>
-        <parameter type-id='4db02c58' name='connector' filepath='drivers/gpu/drm/drm_edid.c' line='5219' column='1'/>
-        <parameter type-id='95e97e5e' name='hpref' filepath='drivers/gpu/drm/drm_edid.c' line='5220' column='1'/>
-        <parameter type-id='95e97e5e' name='vpref' filepath='drivers/gpu/drm/drm_edid.c' line='5220' column='1'/>
+      <function-decl name='drm_set_preferred_mode' mangled-name='drm_set_preferred_mode' filepath='drivers/gpu/drm/drm_edid.c' line='5221' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='drm_set_preferred_mode'>
+        <parameter type-id='4db02c58' name='connector' filepath='drivers/gpu/drm/drm_edid.c' line='5221' column='1'/>
+        <parameter type-id='95e97e5e' name='hpref' filepath='drivers/gpu/drm/drm_edid.c' line='5222' column='1'/>
+        <parameter type-id='95e97e5e' name='vpref' filepath='drivers/gpu/drm/drm_edid.c' line='5222' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
       <function-type size-in-bits='64' id='c3fc04e5'>
@@ -66304,6 +66350,15 @@
         <subrange length='2' type-id='7ff19f0f' id='52efc4ef'/>
       </array-type-def>
     </abi-instr>
+    <abi-instr address-size='64' path='drivers/hid/hid-multitouch.c' language='LANG_C89'>
+      <function-decl name='devm_kasprintf' mangled-name='devm_kasprintf' filepath='include/linux/device.h' line='708' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devm_kasprintf'>
+        <parameter type-id='fa0b179b'/>
+        <parameter type-id='f0981eeb'/>
+        <parameter type-id='80f4b756'/>
+        <parameter is-variadic='yes'/>
+        <return type-id='26a90f95'/>
+      </function-decl>
+    </abi-instr>
     <abi-instr address-size='64' path='drivers/hid/hid-nintendo.c' language='LANG_C89'>
       <class-decl name='semaphore' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/semaphore.h' line='16' column='1' id='011244e5'>
         <data-member access='public' layout-offset-in-bits='0'>
@@ -66774,20 +66829,13 @@
         <parameter type-id='bd1c8eb6'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='devm_kasprintf' mangled-name='devm_kasprintf' filepath='include/linux/device.h' line='708' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devm_kasprintf'>
-        <parameter type-id='fa0b179b'/>
-        <parameter type-id='f0981eeb'/>
-        <parameter type-id='80f4b756'/>
-        <parameter is-variadic='yes'/>
-        <return type-id='26a90f95'/>
-      </function-decl>
-      <function-decl name='devm_power_supply_register' mangled-name='devm_power_supply_register' filepath='include/linux/power_supply.h' line='687' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devm_power_supply_register'>
+      <function-decl name='devm_power_supply_register' mangled-name='devm_power_supply_register' filepath='include/linux/power_supply.h' line='688' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='devm_power_supply_register'>
         <parameter type-id='fa0b179b'/>
         <parameter type-id='cb9cd99f'/>
         <parameter type-id='048b3ad6'/>
         <return type-id='c0c93c9e'/>
       </function-decl>
-      <function-decl name='power_supply_get_drvdata' mangled-name='power_supply_get_drvdata' filepath='include/linux/power_supply.h' line='699' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='power_supply_get_drvdata'>
+      <function-decl name='power_supply_get_drvdata' mangled-name='power_supply_get_drvdata' filepath='include/linux/power_supply.h' line='700' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='power_supply_get_drvdata'>
         <parameter type-id='c0c93c9e'/>
         <return type-id='eaa32e2f'/>
       </function-decl>
@@ -68892,7 +68940,7 @@
         <parameter type-id='3a47d82b'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='flush_work' mangled-name='flush_work' filepath='include/linux/workqueue.h' line='485' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='flush_work'>
+      <function-decl name='flush_work' mangled-name='flush_work' filepath='include/linux/workqueue.h' line='486' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='flush_work'>
         <parameter type-id='83c1bde6'/>
         <return type-id='c894953d'/>
       </function-decl>
@@ -69919,7 +69967,7 @@
         <parameter type-id='fa0b179b'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='mod_delayed_work_on' mangled-name='mod_delayed_work_on' filepath='include/linux/workqueue.h' line='474' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='mod_delayed_work_on'>
+      <function-decl name='mod_delayed_work_on' mangled-name='mod_delayed_work_on' filepath='include/linux/workqueue.h' line='475' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='mod_delayed_work_on'>
         <parameter type-id='95e97e5e'/>
         <parameter type-id='242e3d19'/>
         <parameter type-id='1a7ee447'/>
@@ -70568,415 +70616,415 @@
           <var-decl name='msi_index' type-id='1dc6a898' visibility='default' filepath='include/linux/msi.h' line='47' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='pci_dev' size-in-bits='20224' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='289' column='1' id='5c93f9a7'>
+      <class-decl name='pci_dev' size-in-bits='20224' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='290' column='1' id='5c93f9a7'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='bus_list' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='290' column='1'/>
+          <var-decl name='bus_list' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='291' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='bus' type-id='d1feb554' visibility='default' filepath='include/linux/pci.h' line='291' column='1'/>
+          <var-decl name='bus' type-id='d1feb554' visibility='default' filepath='include/linux/pci.h' line='292' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='subordinate' type-id='d1feb554' visibility='default' filepath='include/linux/pci.h' line='292' column='1'/>
+          <var-decl name='subordinate' type-id='d1feb554' visibility='default' filepath='include/linux/pci.h' line='293' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='sysdata' type-id='eaa32e2f' visibility='default' filepath='include/linux/pci.h' line='294' column='1'/>
+          <var-decl name='sysdata' type-id='eaa32e2f' visibility='default' filepath='include/linux/pci.h' line='295' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='procent' type-id='d077e928' visibility='default' filepath='include/linux/pci.h' line='295' column='1'/>
+          <var-decl name='procent' type-id='d077e928' visibility='default' filepath='include/linux/pci.h' line='296' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='slot' type-id='4f146b8a' visibility='default' filepath='include/linux/pci.h' line='296' column='1'/>
+          <var-decl name='slot' type-id='4f146b8a' visibility='default' filepath='include/linux/pci.h' line='297' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='devfn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='298' column='1'/>
+          <var-decl name='devfn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='299' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='480'>
-          <var-decl name='vendor' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='299' column='1'/>
+          <var-decl name='vendor' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='300' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='496'>
-          <var-decl name='device' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='300' column='1'/>
+          <var-decl name='device' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='301' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='subsystem_vendor' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='301' column='1'/>
+          <var-decl name='subsystem_vendor' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='302' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='528'>
-          <var-decl name='subsystem_device' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='302' column='1'/>
+          <var-decl name='subsystem_device' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='303' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='544'>
-          <var-decl name='class' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='303' column='1'/>
+          <var-decl name='class' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='304' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='revision' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='304' column='1'/>
+          <var-decl name='revision' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='305' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='584'>
-          <var-decl name='hdr_type' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='305' column='1'/>
+          <var-decl name='hdr_type' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='306' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='592'>
-          <var-decl name='pcie_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='310' column='1'/>
+          <var-decl name='pcie_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='311' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='600'>
-          <var-decl name='msi_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='311' column='1'/>
+          <var-decl name='msi_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='312' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='608'>
-          <var-decl name='msix_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='312' column='1'/>
+          <var-decl name='msix_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='313' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='pcie_mpss' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='313' column='1'/>
+          <var-decl name='pcie_mpss' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='314' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='624'>
-          <var-decl name='rom_base_reg' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='314' column='1'/>
+          <var-decl name='rom_base_reg' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='315' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='632'>
-          <var-decl name='pin' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='315' column='1'/>
+          <var-decl name='pin' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='316' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='pcie_flags_reg' type-id='1dc6a898' visibility='default' filepath='include/linux/pci.h' line='316' column='1'/>
+          <var-decl name='pcie_flags_reg' type-id='1dc6a898' visibility='default' filepath='include/linux/pci.h' line='317' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='dma_alias_mask' type-id='1d2c2b85' visibility='default' filepath='include/linux/pci.h' line='317' column='1'/>
+          <var-decl name='dma_alias_mask' type-id='1d2c2b85' visibility='default' filepath='include/linux/pci.h' line='318' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='driver' type-id='85b59624' visibility='default' filepath='include/linux/pci.h' line='319' column='1'/>
+          <var-decl name='driver' type-id='85b59624' visibility='default' filepath='include/linux/pci.h' line='320' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='dma_mask' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='320' column='1'/>
+          <var-decl name='dma_mask' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='321' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='dma_parms' type-id='37251e77' visibility='default' filepath='include/linux/pci.h' line='326' column='1'/>
+          <var-decl name='dma_parms' type-id='37251e77' visibility='default' filepath='include/linux/pci.h' line='327' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='current_state' type-id='49c32219' visibility='default' filepath='include/linux/pci.h' line='328' column='1'/>
+          <var-decl name='current_state' type-id='49c32219' visibility='default' filepath='include/linux/pci.h' line='329' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1056'>
-          <var-decl name='pm_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='331' column='1'/>
+          <var-decl name='pm_cap' type-id='f9b06939' visibility='default' filepath='include/linux/pci.h' line='332' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8'>
-          <var-decl name='pme_support' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='332' column='1'/>
+          <var-decl name='pme_support' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='333' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='13'>
-          <var-decl name='pme_poll' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='334' column='1'/>
+          <var-decl name='pme_poll' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='335' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='14'>
-          <var-decl name='d1_support' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='335' column='1'/>
+          <var-decl name='d1_support' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='336' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='15'>
-          <var-decl name='d2_support' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='336' column='1'/>
+          <var-decl name='d2_support' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='337' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='no_d1d2' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='337' column='1'/>
+          <var-decl name='no_d1d2' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='338' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17'>
-          <var-decl name='no_d3cold' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='338' column='1'/>
+          <var-decl name='no_d3cold' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='339' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18'>
-          <var-decl name='no_d3hot' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='339' column='1'/>
+          <var-decl name='no_d3hot' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='340' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19'>
-          <var-decl name='bridge_d3' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='340' column='1'/>
+          <var-decl name='bridge_d3' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='341' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='20'>
-          <var-decl name='d3cold_allowed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='341' column='1'/>
+          <var-decl name='d3cold_allowed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='342' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='21'>
-          <var-decl name='mmio_always_on' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='342' column='1'/>
+          <var-decl name='mmio_always_on' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='343' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='22'>
-          <var-decl name='wakeup_prepared' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='344' column='1'/>
+          <var-decl name='wakeup_prepared' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='345' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='23'>
-          <var-decl name='runtime_d3cold' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='345' column='1'/>
+          <var-decl name='runtime_d3cold' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='346' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='24'>
-          <var-decl name='ignore_hotplug' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='349' column='1'/>
+          <var-decl name='ignore_hotplug' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='350' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='25'>
-          <var-decl name='hotplug_user_indicators' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='350' column='1'/>
+          <var-decl name='hotplug_user_indicators' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='351' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='26'>
-          <var-decl name='clear_retrain_link' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='353' column='1'/>
+          <var-decl name='clear_retrain_link' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='354' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='d3_delay' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='355' column='1'/>
+          <var-decl name='d3_delay' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='356' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1120'>
-          <var-decl name='d3cold_delay' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='356' column='1'/>
+          <var-decl name='d3cold_delay' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='357' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='eetlp_prefix_path' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='363' column='1'/>
+          <var-decl name='eetlp_prefix_path' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='364' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1184'>
-          <var-decl name='error_state' type-id='7d5a17ad' visibility='default' filepath='include/linux/pci.h' line='365' column='1'/>
+          <var-decl name='error_state' type-id='7d5a17ad' visibility='default' filepath='include/linux/pci.h' line='366' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/linux/pci.h' line='366' column='1'/>
+          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/linux/pci.h' line='367' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8832'>
-          <var-decl name='cfg_size' type-id='95e97e5e' visibility='default' filepath='include/linux/pci.h' line='368' column='1'/>
+          <var-decl name='cfg_size' type-id='95e97e5e' visibility='default' filepath='include/linux/pci.h' line='369' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8864'>
-          <var-decl name='irq' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='374' column='1'/>
+          <var-decl name='irq' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='375' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8896'>
-          <var-decl name='resource' type-id='221adaf7' visibility='default' filepath='include/linux/pci.h' line='375' column='1'/>
+          <var-decl name='resource' type-id='221adaf7' visibility='default' filepath='include/linux/pci.h' line='376' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17344'>
-          <var-decl name='match_driver' type-id='b50a4934' visibility='default' filepath='include/linux/pci.h' line='377' column='1'/>
+          <var-decl name='match_driver' type-id='b50a4934' visibility='default' filepath='include/linux/pci.h' line='378' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8'>
-          <var-decl name='transparent' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='379' column='1'/>
+          <var-decl name='transparent' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='380' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='9'>
-          <var-decl name='multifunction' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='380' column='1'/>
+          <var-decl name='multifunction' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='381' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10'>
-          <var-decl name='is_busmaster' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='382' column='1'/>
+          <var-decl name='is_busmaster' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='383' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='11'>
-          <var-decl name='no_msi' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='383' column='1'/>
+          <var-decl name='no_msi' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='384' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='12'>
-          <var-decl name='no_64bit_msi' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='384' column='1'/>
+          <var-decl name='no_64bit_msi' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='385' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='13'>
-          <var-decl name='block_cfg_access' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='385' column='1'/>
+          <var-decl name='block_cfg_access' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='386' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='14'>
-          <var-decl name='broken_parity_status' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='386' column='1'/>
+          <var-decl name='broken_parity_status' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='387' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='15'>
-          <var-decl name='irq_reroute_variant' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='387' column='1'/>
+          <var-decl name='irq_reroute_variant' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='388' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17'>
-          <var-decl name='msi_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='388' column='1'/>
+          <var-decl name='msi_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='389' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18'>
-          <var-decl name='msix_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='389' column='1'/>
+          <var-decl name='msix_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='390' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19'>
-          <var-decl name='ari_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='390' column='1'/>
+          <var-decl name='ari_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='391' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='20'>
-          <var-decl name='ats_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='391' column='1'/>
+          <var-decl name='ats_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='392' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='21'>
-          <var-decl name='pasid_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='392' column='1'/>
+          <var-decl name='pasid_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='393' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='22'>
-          <var-decl name='pri_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='393' column='1'/>
+          <var-decl name='pri_enabled' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='394' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='23'>
-          <var-decl name='is_managed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='394' column='1'/>
+          <var-decl name='is_managed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='395' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='24'>
-          <var-decl name='needs_freset' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='395' column='1'/>
+          <var-decl name='needs_freset' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='396' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='25'>
-          <var-decl name='state_saved' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='396' column='1'/>
+          <var-decl name='state_saved' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='397' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='26'>
-          <var-decl name='is_physfn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='397' column='1'/>
+          <var-decl name='is_physfn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='398' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='27'>
-          <var-decl name='is_virtfn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='398' column='1'/>
+          <var-decl name='is_virtfn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='399' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='28'>
-          <var-decl name='reset_fn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='399' column='1'/>
+          <var-decl name='reset_fn' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='400' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='29'>
-          <var-decl name='is_hotplug_bridge' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='400' column='1'/>
+          <var-decl name='is_hotplug_bridge' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='401' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='30'>
-          <var-decl name='shpc_managed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='401' column='1'/>
+          <var-decl name='shpc_managed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='402' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='31'>
-          <var-decl name='is_thunderbolt' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='402' column='1'/>
+          <var-decl name='is_thunderbolt' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='403' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='__aer_firmware_first_valid' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='403' column='1'/>
+          <var-decl name='__aer_firmware_first_valid' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='404' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1'>
-          <var-decl name='__aer_firmware_first' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='404' column='1'/>
+          <var-decl name='__aer_firmware_first' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='405' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2'>
-          <var-decl name='broken_intx_masking' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='405' column='1'/>
+          <var-decl name='broken_intx_masking' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='406' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3'>
-          <var-decl name='io_window_1k' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='406' column='1'/>
+          <var-decl name='io_window_1k' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='407' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4'>
-          <var-decl name='irq_managed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='407' column='1'/>
+          <var-decl name='irq_managed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='408' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5'>
-          <var-decl name='has_secondary_link' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='408' column='1'/>
+          <var-decl name='has_secondary_link' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='409' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6'>
-          <var-decl name='non_compliant_bars' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='409' column='1'/>
+          <var-decl name='non_compliant_bars' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='410' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='7'>
-          <var-decl name='is_probed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='410' column='1'/>
+          <var-decl name='is_probed' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='411' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17392'>
-          <var-decl name='dev_flags' type-id='0f4efb07' visibility='default' filepath='include/linux/pci.h' line='411' column='1'/>
+          <var-decl name='dev_flags' type-id='0f4efb07' visibility='default' filepath='include/linux/pci.h' line='412' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17408'>
-          <var-decl name='enable_cnt' type-id='49178f86' visibility='default' filepath='include/linux/pci.h' line='412' column='1'/>
+          <var-decl name='enable_cnt' type-id='49178f86' visibility='default' filepath='include/linux/pci.h' line='413' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17440'>
-          <var-decl name='saved_config_space' type-id='02fdec64' visibility='default' filepath='include/linux/pci.h' line='414' column='1'/>
+          <var-decl name='saved_config_space' type-id='02fdec64' visibility='default' filepath='include/linux/pci.h' line='415' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='17984'>
-          <var-decl name='saved_cap_space' type-id='e151255a' visibility='default' filepath='include/linux/pci.h' line='415' column='1'/>
+          <var-decl name='saved_cap_space' type-id='e151255a' visibility='default' filepath='include/linux/pci.h' line='416' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18048'>
-          <var-decl name='rom_attr' type-id='c0e2acc9' visibility='default' filepath='include/linux/pci.h' line='416' column='1'/>
+          <var-decl name='rom_attr' type-id='c0e2acc9' visibility='default' filepath='include/linux/pci.h' line='417' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18112'>
-          <var-decl name='rom_attr_enabled' type-id='95e97e5e' visibility='default' filepath='include/linux/pci.h' line='417' column='1'/>
+          <var-decl name='rom_attr_enabled' type-id='95e97e5e' visibility='default' filepath='include/linux/pci.h' line='418' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18176'>
-          <var-decl name='res_attr' type-id='2cc49b73' visibility='default' filepath='include/linux/pci.h' line='418' column='1'/>
+          <var-decl name='res_attr' type-id='2cc49b73' visibility='default' filepath='include/linux/pci.h' line='419' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='18880'>
-          <var-decl name='res_attr_wc' type-id='2cc49b73' visibility='default' filepath='include/linux/pci.h' line='419' column='1'/>
+          <var-decl name='res_attr_wc' type-id='2cc49b73' visibility='default' filepath='include/linux/pci.h' line='420' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19584'>
-          <var-decl name='msi_irq_groups' type-id='c97de1ac' visibility='default' filepath='include/linux/pci.h' line='430' column='1'/>
+          <var-decl name='msi_irq_groups' type-id='c97de1ac' visibility='default' filepath='include/linux/pci.h' line='431' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19648'>
-          <var-decl name='vpd' type-id='0b72939c' visibility='default' filepath='include/linux/pci.h' line='432' column='1'/>
+          <var-decl name='vpd' type-id='0b72939c' visibility='default' filepath='include/linux/pci.h' line='433' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19712'>
-          <var-decl name='rom' type-id='2522883d' visibility='default' filepath='include/linux/pci.h' line='448' column='1'/>
+          <var-decl name='rom' type-id='2522883d' visibility='default' filepath='include/linux/pci.h' line='449' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19776'>
-          <var-decl name='romlen' type-id='b59d7dce' visibility='default' filepath='include/linux/pci.h' line='449' column='1'/>
+          <var-decl name='romlen' type-id='b59d7dce' visibility='default' filepath='include/linux/pci.h' line='450' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19840'>
-          <var-decl name='driver_override' type-id='26a90f95' visibility='default' filepath='include/linux/pci.h' line='450' column='1'/>
+          <var-decl name='driver_override' type-id='26a90f95' visibility='default' filepath='include/linux/pci.h' line='451' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19904'>
-          <var-decl name='priv_flags' type-id='7359adad' visibility='default' filepath='include/linux/pci.h' line='452' column='1'/>
+          <var-decl name='priv_flags' type-id='7359adad' visibility='default' filepath='include/linux/pci.h' line='453' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='19968'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='454' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='455' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='20032'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='455' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='456' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='20096'>
-          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='456' column='1'/>
+          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='457' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='20160'>
-          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='457' column='1'/>
+          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='458' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='pci_bus' size-in-bits='10688' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='554' column='1' id='7e8e008e'>
+      <class-decl name='pci_bus' size-in-bits='10688' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='555' column='1' id='7e8e008e'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='node' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='555' column='1'/>
+          <var-decl name='node' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='556' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='parent' type-id='d1feb554' visibility='default' filepath='include/linux/pci.h' line='556' column='1'/>
+          <var-decl name='parent' type-id='d1feb554' visibility='default' filepath='include/linux/pci.h' line='557' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='children' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='557' column='1'/>
+          <var-decl name='children' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='558' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='devices' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='558' column='1'/>
+          <var-decl name='devices' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='559' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='self' type-id='85196e3f' visibility='default' filepath='include/linux/pci.h' line='559' column='1'/>
+          <var-decl name='self' type-id='85196e3f' visibility='default' filepath='include/linux/pci.h' line='560' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='slots' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='560' column='1'/>
+          <var-decl name='slots' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='561' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='resource' type-id='774e8b2d' visibility='default' filepath='include/linux/pci.h' line='562' column='1'/>
+          <var-decl name='resource' type-id='774e8b2d' visibility='default' filepath='include/linux/pci.h' line='563' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='resources' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='563' column='1'/>
+          <var-decl name='resources' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='564' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='busn_res' type-id='5218160d' visibility='default' filepath='include/linux/pci.h' line='564' column='1'/>
+          <var-decl name='busn_res' type-id='5218160d' visibility='default' filepath='include/linux/pci.h' line='565' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1792'>
-          <var-decl name='ops' type-id='2058826a' visibility='default' filepath='include/linux/pci.h' line='566' column='1'/>
+          <var-decl name='ops' type-id='2058826a' visibility='default' filepath='include/linux/pci.h' line='567' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='msi' type-id='b9526cc1' visibility='default' filepath='include/linux/pci.h' line='567' column='1'/>
+          <var-decl name='msi' type-id='b9526cc1' visibility='default' filepath='include/linux/pci.h' line='568' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1920'>
-          <var-decl name='sysdata' type-id='eaa32e2f' visibility='default' filepath='include/linux/pci.h' line='568' column='1'/>
+          <var-decl name='sysdata' type-id='eaa32e2f' visibility='default' filepath='include/linux/pci.h' line='569' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1984'>
-          <var-decl name='procdir' type-id='d077e928' visibility='default' filepath='include/linux/pci.h' line='569' column='1'/>
+          <var-decl name='procdir' type-id='d077e928' visibility='default' filepath='include/linux/pci.h' line='570' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='number' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='571' column='1'/>
+          <var-decl name='number' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='572' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2056'>
-          <var-decl name='primary' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='572' column='1'/>
+          <var-decl name='primary' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='573' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2064'>
-          <var-decl name='max_bus_speed' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='573' column='1'/>
+          <var-decl name='max_bus_speed' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='574' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2072'>
-          <var-decl name='cur_bus_speed' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='574' column='1'/>
+          <var-decl name='cur_bus_speed' type-id='002ac4a6' visibility='default' filepath='include/linux/pci.h' line='575' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2080'>
-          <var-decl name='domain_nr' type-id='95e97e5e' visibility='default' filepath='include/linux/pci.h' line='576' column='1'/>
+          <var-decl name='domain_nr' type-id='95e97e5e' visibility='default' filepath='include/linux/pci.h' line='577' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='name' type-id='36d7f119' visibility='default' filepath='include/linux/pci.h' line='579' column='1'/>
+          <var-decl name='name' type-id='36d7f119' visibility='default' filepath='include/linux/pci.h' line='580' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2496'>
-          <var-decl name='bridge_ctl' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='581' column='1'/>
+          <var-decl name='bridge_ctl' type-id='8efea9e5' visibility='default' filepath='include/linux/pci.h' line='582' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2512'>
-          <var-decl name='bus_flags' type-id='757fc982' visibility='default' filepath='include/linux/pci.h' line='582' column='1'/>
+          <var-decl name='bus_flags' type-id='757fc982' visibility='default' filepath='include/linux/pci.h' line='583' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2560'>
-          <var-decl name='bridge' type-id='fa0b179b' visibility='default' filepath='include/linux/pci.h' line='583' column='1'/>
+          <var-decl name='bridge' type-id='fa0b179b' visibility='default' filepath='include/linux/pci.h' line='584' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2624'>
-          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/linux/pci.h' line='584' column='1'/>
+          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/linux/pci.h' line='585' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10240'>
-          <var-decl name='legacy_io' type-id='c0e2acc9' visibility='default' filepath='include/linux/pci.h' line='585' column='1'/>
+          <var-decl name='legacy_io' type-id='c0e2acc9' visibility='default' filepath='include/linux/pci.h' line='586' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10304'>
-          <var-decl name='legacy_mem' type-id='c0e2acc9' visibility='default' filepath='include/linux/pci.h' line='586' column='1'/>
+          <var-decl name='legacy_mem' type-id='c0e2acc9' visibility='default' filepath='include/linux/pci.h' line='587' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='is_added' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='587' column='1'/>
+          <var-decl name='is_added' type-id='f0981eeb' visibility='default' filepath='include/linux/pci.h' line='588' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10432'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='589' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='590' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10496'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='590' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='591' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10560'>
-          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='591' column='1'/>
+          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='592' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10624'>
-          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='592' column='1'/>
+          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='593' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='pci_ops' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='683' column='1' id='fc2007cc'>
+      <class-decl name='pci_ops' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='684' column='1' id='fc2007cc'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='add_bus' type-id='4a1c3304' visibility='default' filepath='include/linux/pci.h' line='684' column='1'/>
+          <var-decl name='add_bus' type-id='4a1c3304' visibility='default' filepath='include/linux/pci.h' line='685' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='remove_bus' type-id='7df445b9' visibility='default' filepath='include/linux/pci.h' line='685' column='1'/>
+          <var-decl name='remove_bus' type-id='7df445b9' visibility='default' filepath='include/linux/pci.h' line='686' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='map_bus' type-id='d479d76a' visibility='default' filepath='include/linux/pci.h' line='686' column='1'/>
+          <var-decl name='map_bus' type-id='d479d76a' visibility='default' filepath='include/linux/pci.h' line='687' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='read' type-id='ffde3570' visibility='default' filepath='include/linux/pci.h' line='687' column='1'/>
+          <var-decl name='read' type-id='ffde3570' visibility='default' filepath='include/linux/pci.h' line='688' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='write' type-id='934d23eb' visibility='default' filepath='include/linux/pci.h' line='688' column='1'/>
+          <var-decl name='write' type-id='934d23eb' visibility='default' filepath='include/linux/pci.h' line='689' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='msi_controller' size-in-bits='512' is-struct='yes' visibility='default' filepath='include/linux/msi.h' line='189' column='1' id='1f8bced9'>
@@ -71020,63 +71068,63 @@
           <var-decl name='kobj' type-id='b6ab8849' visibility='default' filepath='include/linux/pci.h' line='62' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='pci_driver' size-in-bits='2688' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='768' column='1' id='314e713e'>
+      <class-decl name='pci_driver' size-in-bits='2688' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='769' column='1' id='314e713e'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='node' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='769' column='1'/>
+          <var-decl name='node' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='770' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='name' type-id='80f4b756' visibility='default' filepath='include/linux/pci.h' line='770' column='1'/>
+          <var-decl name='name' type-id='80f4b756' visibility='default' filepath='include/linux/pci.h' line='771' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='id_table' type-id='92fc8aa5' visibility='default' filepath='include/linux/pci.h' line='771' column='1'/>
+          <var-decl name='id_table' type-id='92fc8aa5' visibility='default' filepath='include/linux/pci.h' line='772' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='probe' type-id='6cc3a8b3' visibility='default' filepath='include/linux/pci.h' line='772' column='1'/>
+          <var-decl name='probe' type-id='6cc3a8b3' visibility='default' filepath='include/linux/pci.h' line='773' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='remove' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='773' column='1'/>
+          <var-decl name='remove' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='774' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='suspend' type-id='831f84c2' visibility='default' filepath='include/linux/pci.h' line='774' column='1'/>
+          <var-decl name='suspend' type-id='831f84c2' visibility='default' filepath='include/linux/pci.h' line='775' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='suspend_late' type-id='831f84c2' visibility='default' filepath='include/linux/pci.h' line='775' column='1'/>
+          <var-decl name='suspend_late' type-id='831f84c2' visibility='default' filepath='include/linux/pci.h' line='776' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='resume_early' type-id='40672f7b' visibility='default' filepath='include/linux/pci.h' line='776' column='1'/>
+          <var-decl name='resume_early' type-id='40672f7b' visibility='default' filepath='include/linux/pci.h' line='777' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='resume' type-id='40672f7b' visibility='default' filepath='include/linux/pci.h' line='777' column='1'/>
+          <var-decl name='resume' type-id='40672f7b' visibility='default' filepath='include/linux/pci.h' line='778' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='shutdown' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='778' column='1'/>
+          <var-decl name='shutdown' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='779' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='sriov_configure' type-id='ab05e282' visibility='default' filepath='include/linux/pci.h' line='779' column='1'/>
+          <var-decl name='sriov_configure' type-id='ab05e282' visibility='default' filepath='include/linux/pci.h' line='780' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='err_handler' type-id='2da88de7' visibility='default' filepath='include/linux/pci.h' line='780' column='1'/>
+          <var-decl name='err_handler' type-id='2da88de7' visibility='default' filepath='include/linux/pci.h' line='781' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='groups' type-id='c97de1ac' visibility='default' filepath='include/linux/pci.h' line='781' column='1'/>
+          <var-decl name='groups' type-id='c97de1ac' visibility='default' filepath='include/linux/pci.h' line='782' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='driver' type-id='fe007c02' visibility='default' filepath='include/linux/pci.h' line='782' column='1'/>
+          <var-decl name='driver' type-id='fe007c02' visibility='default' filepath='include/linux/pci.h' line='783' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2240'>
-          <var-decl name='dynids' type-id='022719b7' visibility='default' filepath='include/linux/pci.h' line='783' column='1'/>
+          <var-decl name='dynids' type-id='022719b7' visibility='default' filepath='include/linux/pci.h' line='784' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2432'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='785' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='786' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2496'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='786' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='787' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2560'>
-          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='787' column='1'/>
+          <var-decl name='android_kabi_reserved3' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='788' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2624'>
-          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='788' column='1'/>
+          <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/pci.h' line='789' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='pci_device_id' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/mod_devicetable.h' line='19' column='1' id='6cb59de2'>
@@ -71102,39 +71150,39 @@
           <var-decl name='driver_data' type-id='0791d6c8' visibility='default' filepath='include/linux/mod_devicetable.h' line='23' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='pci_error_handlers' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='747' column='1' id='709bf5ba'>
+      <class-decl name='pci_error_handlers' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='748' column='1' id='709bf5ba'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='error_detected' type-id='abc80f30' visibility='default' filepath='include/linux/pci.h' line='749' column='1'/>
+          <var-decl name='error_detected' type-id='abc80f30' visibility='default' filepath='include/linux/pci.h' line='750' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='mmio_enabled' type-id='80b73a7b' visibility='default' filepath='include/linux/pci.h' line='753' column='1'/>
+          <var-decl name='mmio_enabled' type-id='80b73a7b' visibility='default' filepath='include/linux/pci.h' line='754' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='slot_reset' type-id='80b73a7b' visibility='default' filepath='include/linux/pci.h' line='756' column='1'/>
+          <var-decl name='slot_reset' type-id='80b73a7b' visibility='default' filepath='include/linux/pci.h' line='757' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='reset_prepare' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='759' column='1'/>
+          <var-decl name='reset_prepare' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='760' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='reset_done' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='760' column='1'/>
+          <var-decl name='reset_done' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='761' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='resume' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='763' column='1'/>
+          <var-decl name='resume' type-id='01d543be' visibility='default' filepath='include/linux/pci.h' line='764' column='1'/>
         </data-member>
       </class-decl>
-      <typedef-decl name='pci_ers_result_t' type-id='f0981eeb' filepath='include/linux/pci.h' line='724' column='1' id='453a795e'/>
+      <typedef-decl name='pci_ers_result_t' type-id='f0981eeb' filepath='include/linux/pci.h' line='725' column='1' id='453a795e'/>
       <enum-decl name='pci_channel_state' filepath='include/linux/pci.h' line='161' column='1' id='c36cf4da'>
         <underlying-type type-id='9cac1fee'/>
         <enumerator name='pci_channel_io_normal' value='1'/>
         <enumerator name='pci_channel_io_frozen' value='2'/>
         <enumerator name='pci_channel_io_perm_failure' value='3'/>
       </enum-decl>
-      <class-decl name='pci_dynids' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='711' column='1' id='022719b7'>
+      <class-decl name='pci_dynids' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/pci.h' line='712' column='1' id='022719b7'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='lock' type-id='fb4018a0' visibility='default' filepath='include/linux/pci.h' line='712' column='1'/>
+          <var-decl name='lock' type-id='fb4018a0' visibility='default' filepath='include/linux/pci.h' line='713' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='713' column='1'/>
+          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/linux/pci.h' line='714' column='1'/>
         </data-member>
       </class-decl>
       <typedef-decl name='pci_power_t' type-id='95e97e5e' filepath='include/linux/pci.h' line='131' column='1' id='49c32219'/>
@@ -71177,7 +71225,7 @@
         <parameter type-id='1c475548'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='pci_for_each_dma_alias' mangled-name='pci_for_each_dma_alias' filepath='include/linux/pci.h' line='2290' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_for_each_dma_alias'>
+      <function-decl name='pci_for_each_dma_alias' mangled-name='pci_for_each_dma_alias' filepath='include/linux/pci.h' line='2292' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_for_each_dma_alias'>
         <parameter type-id='85196e3f'/>
         <parameter type-id='ef9f46e3'/>
         <parameter type-id='eaa32e2f'/>
@@ -72671,7 +72719,7 @@
         <parameter type-id='f23e2572'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='destroy_workqueue' mangled-name='destroy_workqueue' filepath='include/linux/workqueue.h' line='462' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='destroy_workqueue'>
+      <function-decl name='destroy_workqueue' mangled-name='destroy_workqueue' filepath='include/linux/workqueue.h' line='463' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='destroy_workqueue'>
         <parameter type-id='242e3d19'/>
         <return type-id='48b5725f'/>
       </function-decl>
@@ -80076,7 +80124,7 @@
         <parameter type-id='959ab461'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='ether_setup' mangled-name='ether_setup' filepath='include/linux/netdevice.h' line='4093' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='ether_setup'>
+      <function-decl name='ether_setup' mangled-name='ether_setup' filepath='include/linux/netdevice.h' line='4092' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='ether_setup'>
         <parameter type-id='68a2d05b'/>
         <return type-id='48b5725f'/>
       </function-decl>
@@ -80089,11 +80137,11 @@
         <parameter type-id='0fbf3cfd'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='netif_carrier_on' mangled-name='netif_carrier_on' filepath='include/linux/netdevice.h' line='3770' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_carrier_on'>
+      <function-decl name='netif_carrier_on' mangled-name='netif_carrier_on' filepath='include/linux/netdevice.h' line='3769' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_carrier_on'>
         <parameter type-id='68a2d05b'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='netif_carrier_off' mangled-name='netif_carrier_off' filepath='include/linux/netdevice.h' line='3772' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_carrier_off'>
+      <function-decl name='netif_carrier_off' mangled-name='netif_carrier_off' filepath='include/linux/netdevice.h' line='3771' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_carrier_off'>
         <parameter type-id='68a2d05b'/>
         <return type-id='48b5725f'/>
       </function-decl>
@@ -80103,7 +80151,7 @@
       <function-decl name='rtnl_unlock' mangled-name='rtnl_unlock' filepath='include/linux/rtnetlink.h' line='34' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='rtnl_unlock'>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='alloc_netdev_mqs' mangled-name='alloc_netdev_mqs' filepath='include/linux/netdevice.h' line='4096' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='alloc_netdev_mqs'>
+      <function-decl name='alloc_netdev_mqs' mangled-name='alloc_netdev_mqs' filepath='include/linux/netdevice.h' line='4095' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='alloc_netdev_mqs'>
         <parameter type-id='95e97e5e'/>
         <parameter type-id='80f4b756'/>
         <parameter type-id='002ac4a6'/>
@@ -80112,11 +80160,11 @@
         <parameter type-id='f0981eeb'/>
         <return type-id='68a2d05b'/>
       </function-decl>
-      <function-decl name='register_netdevice' mangled-name='register_netdevice' filepath='include/linux/netdevice.h' line='2664' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='register_netdevice'>
+      <function-decl name='register_netdevice' mangled-name='register_netdevice' filepath='include/linux/netdevice.h' line='2663' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='register_netdevice'>
         <parameter type-id='68a2d05b'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='free_netdev' mangled-name='free_netdev' filepath='include/linux/netdevice.h' line='2673' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='free_netdev'>
+      <function-decl name='free_netdev' mangled-name='free_netdev' filepath='include/linux/netdevice.h' line='2672' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='free_netdev'>
         <parameter type-id='68a2d05b'/>
         <return type-id='48b5725f'/>
       </function-decl>
@@ -80321,11 +80369,11 @@
       <pointer-type-def type-id='d9fc42c3' size-in-bits='64' id='96b07343'/>
       <pointer-type-def type-id='6aebc4a7' size-in-bits='64' id='c8f5869f'/>
       <pointer-type-def type-id='e61c85d0' size-in-bits='64' id='03c386c6'/>
-      <function-decl name='proto_unregister' mangled-name='proto_unregister' filepath='include/net/sock.h' line='1205' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='proto_unregister'>
+      <function-decl name='proto_unregister' mangled-name='proto_unregister' filepath='include/net/sock.h' line='1214' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='proto_unregister'>
         <parameter type-id='d2524501'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='dst_release' mangled-name='dst_release' filepath='include/net/dst.h' line='263' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='dst_release'>
+      <function-decl name='dst_release' mangled-name='dst_release' filepath='include/net/dst.h' line='257' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='dst_release'>
         <parameter type-id='141b6427'/>
         <return type-id='48b5725f'/>
       </function-decl>
@@ -80333,12 +80381,12 @@
         <parameter type-id='96b07343'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='proto_register' mangled-name='proto_register' filepath='include/net/sock.h' line='1204' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='proto_register'>
+      <function-decl name='proto_register' mangled-name='proto_register' filepath='include/net/sock.h' line='1213' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='proto_register'>
         <parameter type-id='d2524501'/>
         <parameter type-id='95e97e5e'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sk_alloc' mangled-name='sk_alloc' filepath='include/net/sock.h' line='1600' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sk_alloc'>
+      <function-decl name='sk_alloc' mangled-name='sk_alloc' filepath='include/net/sock.h' line='1615' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sk_alloc'>
         <parameter type-id='a2bff676'/>
         <parameter type-id='95e97e5e'/>
         <parameter type-id='f0981eeb'/>
@@ -80346,12 +80394,12 @@
         <parameter type-id='95e97e5e'/>
         <return type-id='f772df6d'/>
       </function-decl>
-      <function-decl name='sock_init_data' mangled-name='sock_init_data' filepath='include/net/sock.h' line='1700' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_init_data'>
+      <function-decl name='sock_init_data' mangled-name='sock_init_data' filepath='include/net/sock.h' line='1715' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_init_data'>
         <parameter type-id='13103032'/>
         <parameter type-id='f772df6d'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='sock_queue_rcv_skb' mangled-name='sock_queue_rcv_skb' filepath='include/net/sock.h' line='2178' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_queue_rcv_skb'>
+      <function-decl name='sock_queue_rcv_skb' mangled-name='sock_queue_rcv_skb' filepath='include/net/sock.h' line='2194' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_queue_rcv_skb'>
         <parameter type-id='f772df6d'/>
         <parameter type-id='0fbf3cfd'/>
         <return type-id='95e97e5e'/>
@@ -80365,7 +80413,7 @@
         <parameter type-id='03c386c6'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='lock_sock_nested' mangled-name='lock_sock_nested' filepath='include/net/sock.h' line='1526' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='lock_sock_nested'>
+      <function-decl name='lock_sock_nested' mangled-name='lock_sock_nested' filepath='include/net/sock.h' line='1541' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='lock_sock_nested'>
         <parameter type-id='f772df6d'/>
         <parameter type-id='95e97e5e'/>
         <return type-id='48b5725f'/>
@@ -80381,11 +80429,11 @@
         <parameter type-id='8567d8b0'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='release_sock' mangled-name='release_sock' filepath='include/net/sock.h' line='1534' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='release_sock'>
+      <function-decl name='release_sock' mangled-name='release_sock' filepath='include/net/sock.h' line='1549' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='release_sock'>
         <parameter type-id='f772df6d'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='sk_free' mangled-name='sk_free' filepath='include/net/sock.h' line='1602' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sk_free'>
+      <function-decl name='sk_free' mangled-name='sk_free' filepath='include/net/sock.h' line='1617' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sk_free'>
         <parameter type-id='f772df6d'/>
         <return type-id='48b5725f'/>
       </function-decl>
@@ -80401,12 +80449,12 @@
         <parameter type-id='78e7cf52'/>
         <return type-id='c8f5869f'/>
       </function-decl>
-      <function-decl name='sk_setup_caps' mangled-name='sk_setup_caps' filepath='include/net/sock.h' line='1969' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sk_setup_caps'>
+      <function-decl name='sk_setup_caps' mangled-name='sk_setup_caps' filepath='include/net/sock.h' line='1985' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sk_setup_caps'>
         <parameter type-id='f772df6d'/>
         <parameter type-id='141b6427'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='skb_set_owner_w' mangled-name='skb_set_owner_w' filepath='include/net/sock.h' line='2136' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='skb_set_owner_w'>
+      <function-decl name='skb_set_owner_w' mangled-name='skb_set_owner_w' filepath='include/net/sock.h' line='2152' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='skb_set_owner_w'>
         <parameter type-id='0fbf3cfd'/>
         <parameter type-id='f772df6d'/>
         <return type-id='48b5725f'/>
@@ -80535,21 +80583,21 @@
         <parameter type-id='8efea9e5'/>
         <return type-id='c894953d'/>
       </function-decl>
-      <function-decl name='netif_receive_skb' mangled-name='netif_receive_skb' filepath='include/linux/netdevice.h' line='3623' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_receive_skb'>
+      <function-decl name='netif_receive_skb' mangled-name='netif_receive_skb' filepath='include/linux/netdevice.h' line='3622' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_receive_skb'>
         <parameter type-id='0fbf3cfd'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='netif_set_real_num_tx_queues' mangled-name='netif_set_real_num_tx_queues' filepath='include/linux/netdevice.h' line='3538' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_set_real_num_tx_queues'>
+      <function-decl name='netif_set_real_num_tx_queues' mangled-name='netif_set_real_num_tx_queues' filepath='include/linux/netdevice.h' line='3537' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_set_real_num_tx_queues'>
         <parameter type-id='68a2d05b'/>
         <parameter type-id='f0981eeb'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='netif_set_real_num_rx_queues' mangled-name='netif_set_real_num_rx_queues' filepath='include/linux/netdevice.h' line='3541' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_set_real_num_rx_queues'>
+      <function-decl name='netif_set_real_num_rx_queues' mangled-name='netif_set_real_num_rx_queues' filepath='include/linux/netdevice.h' line='3540' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_set_real_num_rx_queues'>
         <parameter type-id='68a2d05b'/>
         <parameter type-id='f0981eeb'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='netif_tx_stop_all_queues' mangled-name='netif_tx_stop_all_queues' filepath='include/linux/netdevice.h' line='3161' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_tx_stop_all_queues'>
+      <function-decl name='netif_tx_stop_all_queues' mangled-name='netif_tx_stop_all_queues' filepath='include/linux/netdevice.h' line='3160' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_tx_stop_all_queues'>
         <parameter type-id='68a2d05b'/>
         <return type-id='48b5725f'/>
       </function-decl>
@@ -80570,38 +80618,38 @@
         <parameter type-id='f0981eeb'/>
         <return type-id='68a2d05b'/>
       </function-decl>
-      <function-decl name='queue_delayed_work_on' mangled-name='queue_delayed_work_on' filepath='include/linux/workqueue.h' line='472' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='queue_delayed_work_on'>
+      <function-decl name='queue_delayed_work_on' mangled-name='queue_delayed_work_on' filepath='include/linux/workqueue.h' line='473' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='queue_delayed_work_on'>
         <parameter type-id='95e97e5e'/>
         <parameter type-id='242e3d19'/>
         <parameter type-id='1a7ee447'/>
         <parameter type-id='7359adad'/>
         <return type-id='c894953d'/>
       </function-decl>
-      <function-decl name='register_netdev' mangled-name='register_netdev' filepath='include/linux/netdevice.h' line='4110' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='register_netdev'>
+      <function-decl name='register_netdev' mangled-name='register_netdev' filepath='include/linux/netdevice.h' line='4109' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='register_netdev'>
         <parameter type-id='68a2d05b'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='netdev_err' mangled-name='netdev_err' filepath='include/linux/netdevice.h' line='4709' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_err'>
+      <function-decl name='netdev_err' mangled-name='netdev_err' filepath='include/linux/netdevice.h' line='4726' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_err'>
         <parameter type-id='2ce52478'/>
         <parameter type-id='80f4b756'/>
         <parameter is-variadic='yes'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='netdev_info' mangled-name='netdev_info' filepath='include/linux/netdevice.h' line='4715' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_info'>
+      <function-decl name='netdev_info' mangled-name='netdev_info' filepath='include/linux/netdevice.h' line='4732' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_info'>
         <parameter type-id='2ce52478'/>
         <parameter type-id='80f4b756'/>
         <parameter is-variadic='yes'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='unregister_netdev' mangled-name='unregister_netdev' filepath='include/linux/netdevice.h' line='4111' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='unregister_netdev'>
+      <function-decl name='unregister_netdev' mangled-name='unregister_netdev' filepath='include/linux/netdevice.h' line='4110' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='unregister_netdev'>
         <parameter type-id='68a2d05b'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='cancel_delayed_work_sync' mangled-name='cancel_delayed_work_sync' filepath='include/linux/workqueue.h' line='490' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='cancel_delayed_work_sync'>
+      <function-decl name='cancel_delayed_work_sync' mangled-name='cancel_delayed_work_sync' filepath='include/linux/workqueue.h' line='491' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='cancel_delayed_work_sync'>
         <parameter type-id='1a7ee447'/>
         <return type-id='c894953d'/>
       </function-decl>
-      <function-decl name='netif_device_detach' mangled-name='netif_device_detach' filepath='include/linux/netdevice.h' line='3839' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_device_detach'>
+      <function-decl name='netif_device_detach' mangled-name='netif_device_detach' filepath='include/linux/netdevice.h' line='3838' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_device_detach'>
         <parameter type-id='68a2d05b'/>
         <return type-id='48b5725f'/>
       </function-decl>
@@ -80611,22 +80659,22 @@
         <parameter type-id='f0981eeb'/>
         <return type-id='eaa32e2f'/>
       </function-decl>
-      <function-decl name='work_busy' mangled-name='work_busy' filepath='include/linux/workqueue.h' line='499' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='work_busy'>
+      <function-decl name='work_busy' mangled-name='work_busy' filepath='include/linux/workqueue.h' line='500' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='work_busy'>
         <parameter type-id='83c1bde6'/>
         <return type-id='f0981eeb'/>
       </function-decl>
-      <function-decl name='netif_device_attach' mangled-name='netif_device_attach' filepath='include/linux/netdevice.h' line='3841' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_device_attach'>
+      <function-decl name='netif_device_attach' mangled-name='netif_device_attach' filepath='include/linux/netdevice.h' line='3840' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_device_attach'>
         <parameter type-id='68a2d05b'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='netif_tx_wake_queue' mangled-name='netif_tx_wake_queue' filepath='include/linux/netdevice.h' line='3120' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_tx_wake_queue'>
+      <function-decl name='netif_tx_wake_queue' mangled-name='netif_tx_wake_queue' filepath='include/linux/netdevice.h' line='3119' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_tx_wake_queue'>
         <parameter type-id='35b28c4f'/>
         <return type-id='48b5725f'/>
       </function-decl>
       <function-decl name='net_ratelimit' mangled-name='net_ratelimit' filepath='include/linux/net.h' line='252' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='net_ratelimit'>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='netdev_warn' mangled-name='netdev_warn' filepath='include/linux/netdevice.h' line='4711' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_warn'>
+      <function-decl name='netdev_warn' mangled-name='netdev_warn' filepath='include/linux/netdevice.h' line='4728' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_warn'>
         <parameter type-id='2ce52478'/>
         <parameter type-id='80f4b756'/>
         <parameter is-variadic='yes'/>
@@ -80651,7 +80699,7 @@
         <parameter type-id='f0981eeb'/>
         <return type-id='8efea9e5'/>
       </function-decl>
-      <function-decl name='netif_schedule_queue' mangled-name='netif_schedule_queue' filepath='include/linux/netdevice.h' line='3084' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_schedule_queue'>
+      <function-decl name='netif_schedule_queue' mangled-name='netif_schedule_queue' filepath='include/linux/netdevice.h' line='3083' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_schedule_queue'>
         <parameter type-id='35b28c4f'/>
         <return type-id='48b5725f'/>
       </function-decl>
@@ -80739,12 +80787,12 @@
           <var-decl name='log' type-id='f0981eeb' visibility='default' filepath='include/net/udp.h' line='79' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='uncached_list' size-in-bits='192' is-struct='yes' visibility='default' filepath='net/ipv4/route.c' line='1518' column='1' id='6b1203e5'>
+      <class-decl name='uncached_list' size-in-bits='192' is-struct='yes' visibility='default' filepath='net/ipv4/route.c' line='1520' column='1' id='6b1203e5'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='lock' type-id='fb4018a0' visibility='default' filepath='net/ipv4/route.c' line='1519' column='1'/>
+          <var-decl name='lock' type-id='fb4018a0' visibility='default' filepath='net/ipv4/route.c' line='1521' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='head' type-id='72f469ec' visibility='default' filepath='net/ipv4/route.c' line='1520' column='1'/>
+          <var-decl name='head' type-id='72f469ec' visibility='default' filepath='net/ipv4/route.c' line='1522' column='1'/>
         </data-member>
       </class-decl>
       <array-type-def dimensions='1' type-id='4e812b7a' size-in-bits='16384' id='bb890663'>
@@ -81041,165 +81089,165 @@
           <var-decl name='skc_portaddr_node' type-id='03a4a074' visibility='default' filepath='include/net/sock.h' line='186' column='1'/>
         </data-member>
       </union-decl>
-      <class-decl name='proto' size-in-bits='3392' is-struct='yes' visibility='default' filepath='include/net/sock.h' line='1087' column='1' id='7203ee09'>
+      <class-decl name='proto' size-in-bits='3392' is-struct='yes' visibility='default' filepath='include/net/sock.h' line='1095' column='1' id='7203ee09'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='close' type-id='09f3a86b' visibility='default' filepath='include/net/sock.h' line='1088' column='1'/>
+          <var-decl name='close' type-id='09f3a86b' visibility='default' filepath='include/net/sock.h' line='1096' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='pre_connect' type-id='c25ed103' visibility='default' filepath='include/net/sock.h' line='1090' column='1'/>
+          <var-decl name='pre_connect' type-id='c25ed103' visibility='default' filepath='include/net/sock.h' line='1098' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='connect' type-id='c25ed103' visibility='default' filepath='include/net/sock.h' line='1093' column='1'/>
+          <var-decl name='connect' type-id='c25ed103' visibility='default' filepath='include/net/sock.h' line='1101' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='disconnect' type-id='95208a5e' visibility='default' filepath='include/net/sock.h' line='1096' column='1'/>
+          <var-decl name='disconnect' type-id='95208a5e' visibility='default' filepath='include/net/sock.h' line='1104' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='accept' type-id='67adf9a9' visibility='default' filepath='include/net/sock.h' line='1098' column='1'/>
+          <var-decl name='accept' type-id='67adf9a9' visibility='default' filepath='include/net/sock.h' line='1106' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='ioctl' type-id='08113f0a' visibility='default' filepath='include/net/sock.h' line='1101' column='1'/>
+          <var-decl name='ioctl' type-id='08113f0a' visibility='default' filepath='include/net/sock.h' line='1109' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='init' type-id='55530c47' visibility='default' filepath='include/net/sock.h' line='1103' column='1'/>
+          <var-decl name='init' type-id='55530c47' visibility='default' filepath='include/net/sock.h' line='1111' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='destroy' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1104' column='1'/>
+          <var-decl name='destroy' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1112' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='shutdown' type-id='e937debf' visibility='default' filepath='include/net/sock.h' line='1105' column='1'/>
+          <var-decl name='shutdown' type-id='e937debf' visibility='default' filepath='include/net/sock.h' line='1113' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='setsockopt' type-id='bc1bf185' visibility='default' filepath='include/net/sock.h' line='1106' column='1'/>
+          <var-decl name='setsockopt' type-id='bc1bf185' visibility='default' filepath='include/net/sock.h' line='1114' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='getsockopt' type-id='e0fadd76' visibility='default' filepath='include/net/sock.h' line='1109' column='1'/>
+          <var-decl name='getsockopt' type-id='e0fadd76' visibility='default' filepath='include/net/sock.h' line='1117' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='keepalive' type-id='e937debf' visibility='default' filepath='include/net/sock.h' line='1112' column='1'/>
+          <var-decl name='keepalive' type-id='e937debf' visibility='default' filepath='include/net/sock.h' line='1120' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='compat_setsockopt' type-id='bc1bf185' visibility='default' filepath='include/net/sock.h' line='1114' column='1'/>
+          <var-decl name='compat_setsockopt' type-id='bc1bf185' visibility='default' filepath='include/net/sock.h' line='1122' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='compat_getsockopt' type-id='e0fadd76' visibility='default' filepath='include/net/sock.h' line='1118' column='1'/>
+          <var-decl name='compat_getsockopt' type-id='e0fadd76' visibility='default' filepath='include/net/sock.h' line='1126' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='compat_ioctl' type-id='20da830b' visibility='default' filepath='include/net/sock.h' line='1122' column='1'/>
+          <var-decl name='compat_ioctl' type-id='20da830b' visibility='default' filepath='include/net/sock.h' line='1130' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='sendmsg' type-id='1df08751' visibility='default' filepath='include/net/sock.h' line='1125' column='1'/>
+          <var-decl name='sendmsg' type-id='1df08751' visibility='default' filepath='include/net/sock.h' line='1133' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='recvmsg' type-id='74e71fae' visibility='default' filepath='include/net/sock.h' line='1127' column='1'/>
+          <var-decl name='recvmsg' type-id='74e71fae' visibility='default' filepath='include/net/sock.h' line='1135' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='sendpage' type-id='65399e23' visibility='default' filepath='include/net/sock.h' line='1130' column='1'/>
+          <var-decl name='sendpage' type-id='65399e23' visibility='default' filepath='include/net/sock.h' line='1138' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='bind' type-id='c25ed103' visibility='default' filepath='include/net/sock.h' line='1132' column='1'/>
+          <var-decl name='bind' type-id='c25ed103' visibility='default' filepath='include/net/sock.h' line='1140' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='backlog_rcv' type-id='a0f5247f' visibility='default' filepath='include/net/sock.h' line='1135' column='1'/>
+          <var-decl name='backlog_rcv' type-id='a0f5247f' visibility='default' filepath='include/net/sock.h' line='1143' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='release_cb' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1138' column='1'/>
+          <var-decl name='release_cb' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1146' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='hash' type-id='55530c47' visibility='default' filepath='include/net/sock.h' line='1141' column='1'/>
+          <var-decl name='hash' type-id='55530c47' visibility='default' filepath='include/net/sock.h' line='1149' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='unhash' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1142' column='1'/>
+          <var-decl name='unhash' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1150' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1472'>
-          <var-decl name='rehash' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1143' column='1'/>
+          <var-decl name='rehash' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1151' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='get_port' type-id='078de3a3' visibility='default' filepath='include/net/sock.h' line='1144' column='1'/>
+          <var-decl name='get_port' type-id='078de3a3' visibility='default' filepath='include/net/sock.h' line='1152' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1600'>
-          <var-decl name='inuse_idx' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1148' column='1'/>
+          <var-decl name='inuse_idx' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1156' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1664'>
-          <var-decl name='stream_memory_free' type-id='3d4d3aba' visibility='default' filepath='include/net/sock.h' line='1151' column='1'/>
+          <var-decl name='stream_memory_free' type-id='3d4d3aba' visibility='default' filepath='include/net/sock.h' line='1159' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1728'>
-          <var-decl name='stream_memory_read' type-id='3d4d3aba' visibility='default' filepath='include/net/sock.h' line='1152' column='1'/>
+          <var-decl name='stream_memory_read' type-id='3d4d3aba' visibility='default' filepath='include/net/sock.h' line='1160' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1792'>
-          <var-decl name='enter_memory_pressure' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1154' column='1'/>
+          <var-decl name='enter_memory_pressure' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1162' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='leave_memory_pressure' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1155' column='1'/>
+          <var-decl name='leave_memory_pressure' type-id='841969d0' visibility='default' filepath='include/net/sock.h' line='1163' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1920'>
-          <var-decl name='memory_allocated' type-id='5403cb36' visibility='default' filepath='include/net/sock.h' line='1156' column='1'/>
+          <var-decl name='memory_allocated' type-id='5403cb36' visibility='default' filepath='include/net/sock.h' line='1164' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1984'>
-          <var-decl name='sockets_allocated' type-id='84c6078d' visibility='default' filepath='include/net/sock.h' line='1157' column='1'/>
+          <var-decl name='sockets_allocated' type-id='84c6078d' visibility='default' filepath='include/net/sock.h' line='1165' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='memory_pressure' type-id='1d2c2b85' visibility='default' filepath='include/net/sock.h' line='1164' column='1'/>
+          <var-decl name='memory_pressure' type-id='1d2c2b85' visibility='default' filepath='include/net/sock.h' line='1173' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='sysctl_mem' type-id='3ccc2590' visibility='default' filepath='include/net/sock.h' line='1165' column='1'/>
+          <var-decl name='sysctl_mem' type-id='3ccc2590' visibility='default' filepath='include/net/sock.h' line='1174' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2176'>
-          <var-decl name='sysctl_wmem' type-id='7292109c' visibility='default' filepath='include/net/sock.h' line='1167' column='1'/>
+          <var-decl name='sysctl_wmem' type-id='7292109c' visibility='default' filepath='include/net/sock.h' line='1176' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2240'>
-          <var-decl name='sysctl_rmem' type-id='7292109c' visibility='default' filepath='include/net/sock.h' line='1168' column='1'/>
+          <var-decl name='sysctl_rmem' type-id='7292109c' visibility='default' filepath='include/net/sock.h' line='1177' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2304'>
-          <var-decl name='sysctl_wmem_offset' type-id='19c2251e' visibility='default' filepath='include/net/sock.h' line='1169' column='1'/>
+          <var-decl name='sysctl_wmem_offset' type-id='19c2251e' visibility='default' filepath='include/net/sock.h' line='1178' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2336'>
-          <var-decl name='sysctl_rmem_offset' type-id='19c2251e' visibility='default' filepath='include/net/sock.h' line='1170' column='1'/>
+          <var-decl name='sysctl_rmem_offset' type-id='19c2251e' visibility='default' filepath='include/net/sock.h' line='1179' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2368'>
-          <var-decl name='max_header' type-id='95e97e5e' visibility='default' filepath='include/net/sock.h' line='1172' column='1'/>
+          <var-decl name='max_header' type-id='95e97e5e' visibility='default' filepath='include/net/sock.h' line='1181' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2400'>
-          <var-decl name='no_autobind' type-id='b50a4934' visibility='default' filepath='include/net/sock.h' line='1173' column='1'/>
+          <var-decl name='no_autobind' type-id='b50a4934' visibility='default' filepath='include/net/sock.h' line='1182' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2432'>
-          <var-decl name='slab' type-id='f3b4aca8' visibility='default' filepath='include/net/sock.h' line='1175' column='1'/>
+          <var-decl name='slab' type-id='f3b4aca8' visibility='default' filepath='include/net/sock.h' line='1184' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2496'>
-          <var-decl name='obj_size' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1176' column='1'/>
+          <var-decl name='obj_size' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1185' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2528'>
-          <var-decl name='slab_flags' type-id='f7fe96cb' visibility='default' filepath='include/net/sock.h' line='1177' column='1'/>
+          <var-decl name='slab_flags' type-id='f7fe96cb' visibility='default' filepath='include/net/sock.h' line='1186' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2560'>
-          <var-decl name='useroffset' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1178' column='1'/>
+          <var-decl name='useroffset' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1187' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2592'>
-          <var-decl name='usersize' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1179' column='1'/>
+          <var-decl name='usersize' type-id='f0981eeb' visibility='default' filepath='include/net/sock.h' line='1188' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2624'>
-          <var-decl name='orphan_count' type-id='84c6078d' visibility='default' filepath='include/net/sock.h' line='1181' column='1'/>
+          <var-decl name='orphan_count' type-id='84c6078d' visibility='default' filepath='include/net/sock.h' line='1190' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2688'>
-          <var-decl name='rsk_prot' type-id='db994912' visibility='default' filepath='include/net/sock.h' line='1183' column='1'/>
+          <var-decl name='rsk_prot' type-id='db994912' visibility='default' filepath='include/net/sock.h' line='1192' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2752'>
-          <var-decl name='twsk_prot' type-id='d68ad8b5' visibility='default' filepath='include/net/sock.h' line='1184' column='1'/>
+          <var-decl name='twsk_prot' type-id='d68ad8b5' visibility='default' filepath='include/net/sock.h' line='1193' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2816'>
-          <var-decl name='h' type-id='adf5bf47' visibility='default' filepath='include/net/sock.h' line='1191' column='1'/>
+          <var-decl name='h' type-id='adf5bf47' visibility='default' filepath='include/net/sock.h' line='1200' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2880'>
-          <var-decl name='owner' type-id='2730d015' visibility='default' filepath='include/net/sock.h' line='1193' column='1'/>
+          <var-decl name='owner' type-id='2730d015' visibility='default' filepath='include/net/sock.h' line='1202' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2944'>
-          <var-decl name='name' type-id='16dc656a' visibility='default' filepath='include/net/sock.h' line='1195' column='1'/>
+          <var-decl name='name' type-id='16dc656a' visibility='default' filepath='include/net/sock.h' line='1204' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3200'>
-          <var-decl name='node' type-id='72f469ec' visibility='default' filepath='include/net/sock.h' line='1197' column='1'/>
+          <var-decl name='node' type-id='72f469ec' visibility='default' filepath='include/net/sock.h' line='1206' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3328'>
-          <var-decl name='diag_destroy' type-id='95208a5e' visibility='default' filepath='include/net/sock.h' line='1201' column='1'/>
+          <var-decl name='diag_destroy' type-id='95208a5e' visibility='default' filepath='include/net/sock.h' line='1210' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='msghdr' size-in-bits='704' is-struct='yes' visibility='default' filepath='include/linux/socket.h' line='48' column='1' id='ab94745c'>
@@ -82180,18 +82228,18 @@
           <var-decl name='twsk_destructor' type-id='841969d0' visibility='default' filepath='include/net/timewait_sock.h' line='24' column='1'/>
         </data-member>
       </class-decl>
-      <union-decl name='__anonymous_union__17' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/net/sock.h' line='1186' column='1' id='adf5bf47'>
+      <union-decl name='__anonymous_union__17' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/net/sock.h' line='1195' column='1' id='adf5bf47'>
         <data-member access='public'>
-          <var-decl name='hashinfo' type-id='d7a1e3c2' visibility='default' filepath='include/net/sock.h' line='1187' column='1'/>
+          <var-decl name='hashinfo' type-id='d7a1e3c2' visibility='default' filepath='include/net/sock.h' line='1196' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='udp_table' type-id='115daa23' visibility='default' filepath='include/net/sock.h' line='1188' column='1'/>
+          <var-decl name='udp_table' type-id='115daa23' visibility='default' filepath='include/net/sock.h' line='1197' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='raw_hash' type-id='eb2c56dc' visibility='default' filepath='include/net/sock.h' line='1189' column='1'/>
+          <var-decl name='raw_hash' type-id='eb2c56dc' visibility='default' filepath='include/net/sock.h' line='1198' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='smc_hash' type-id='aa8162a3' visibility='default' filepath='include/net/sock.h' line='1190' column='1'/>
+          <var-decl name='smc_hash' type-id='aa8162a3' visibility='default' filepath='include/net/sock.h' line='1199' column='1'/>
         </data-member>
       </union-decl>
       <class-decl name='smc_hashinfo' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/net/smc.h' line='16' column='1' id='adb1d973'>
@@ -83027,30 +83075,30 @@
           <var-decl name='timeout' type-id='7359adad' visibility='default' filepath='include/net/xfrm.h' line='570' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='lwtunnel_state' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/net/lwtunnel.h' line='25' column='1' id='44644afc'>
+      <class-decl name='lwtunnel_state' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/net/lwtunnel.h' line='28' column='1' id='44644afc'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='type' type-id='d315442e' visibility='default' filepath='include/net/lwtunnel.h' line='26' column='1'/>
+          <var-decl name='type' type-id='d315442e' visibility='default' filepath='include/net/lwtunnel.h' line='29' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='flags' type-id='d315442e' visibility='default' filepath='include/net/lwtunnel.h' line='27' column='1'/>
+          <var-decl name='flags' type-id='d315442e' visibility='default' filepath='include/net/lwtunnel.h' line='30' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='headroom' type-id='d315442e' visibility='default' filepath='include/net/lwtunnel.h' line='28' column='1'/>
+          <var-decl name='headroom' type-id='d315442e' visibility='default' filepath='include/net/lwtunnel.h' line='31' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='refcnt' type-id='49178f86' visibility='default' filepath='include/net/lwtunnel.h' line='29' column='1'/>
+          <var-decl name='refcnt' type-id='49178f86' visibility='default' filepath='include/net/lwtunnel.h' line='32' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='orig_output' type-id='0023218e' visibility='default' filepath='include/net/lwtunnel.h' line='30' column='1'/>
+          <var-decl name='orig_output' type-id='0023218e' visibility='default' filepath='include/net/lwtunnel.h' line='33' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='orig_input' type-id='d2e00785' visibility='default' filepath='include/net/lwtunnel.h' line='31' column='1'/>
+          <var-decl name='orig_input' type-id='d2e00785' visibility='default' filepath='include/net/lwtunnel.h' line='34' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/net/lwtunnel.h' line='32' column='1'/>
+          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/net/lwtunnel.h' line='35' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='data' type-id='167619f6' visibility='default' filepath='include/net/lwtunnel.h' line='33' column='1'/>
+          <var-decl name='data' type-id='167619f6' visibility='default' filepath='include/net/lwtunnel.h' line='36' column='1'/>
         </data-member>
       </class-decl>
       <union-decl name='__anonymous_union__27' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/net/sock.h' line='414' column='1' id='fc714247'>
@@ -83259,12 +83307,12 @@
           <var-decl name='' type-id='2a125a28' visibility='default' filepath='include/net/sock.h' line='523' column='1'/>
         </data-member>
       </union-decl>
-      <union-decl name='__anonymous_union__33' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/net/ip.h' line='126' column='1' id='4fa91678'>
+      <union-decl name='__anonymous_union__33' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/net/ip.h' line='128' column='1' id='4fa91678'>
         <data-member access='public'>
-          <var-decl name='destructor' type-id='841969d0' visibility='default' filepath='include/net/ip.h' line='127' column='1'/>
+          <var-decl name='destructor' type-id='841969d0' visibility='default' filepath='include/net/ip.h' line='129' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='saved_sk' type-id='f772df6d' visibility='default' filepath='include/net/ip.h' line='128' column='1'/>
+          <var-decl name='saved_sk' type-id='f772df6d' visibility='default' filepath='include/net/ip.h' line='130' column='1'/>
         </data-member>
       </union-decl>
       <class-decl name='fib_rule' size-in-bits='1216' is-struct='yes' visibility='default' filepath='include/net/fib_rules.h' line='19' column='1' id='94b5478d'>
@@ -84514,12 +84562,12 @@
         <parameter type-id='7359adad'/>
         <return type-id='7359adad'/>
       </function-decl>
-      <function-decl name='unregister_netdevice_queue' mangled-name='unregister_netdevice_queue' filepath='include/linux/netdevice.h' line='2665' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='unregister_netdevice_queue'>
+      <function-decl name='unregister_netdevice_queue' mangled-name='unregister_netdevice_queue' filepath='include/linux/netdevice.h' line='2664' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='unregister_netdevice_queue'>
         <parameter type-id='68a2d05b'/>
         <parameter type-id='e84b031a'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='netif_rx' mangled-name='netif_rx' filepath='include/linux/netdevice.h' line='3621' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_rx'>
+      <function-decl name='netif_rx' mangled-name='netif_rx' filepath='include/linux/netdevice.h' line='3620' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_rx'>
         <parameter type-id='0fbf3cfd'/>
         <return type-id='95e97e5e'/>
       </function-decl>
@@ -84551,7 +84599,7 @@
         <parameter type-id='eaa32e2f'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='netif_napi_add' mangled-name='netif_napi_add' filepath='include/linux/netdevice.h' line='2252' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_napi_add'>
+      <function-decl name='netif_napi_add' mangled-name='netif_napi_add' filepath='include/linux/netdevice.h' line='2251' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_napi_add'>
         <parameter type-id='68a2d05b'/>
         <parameter type-id='c50361c5'/>
         <parameter type-id='f07d90b4'/>
@@ -84574,10 +84622,10 @@
         <parameter type-id='c50361c5'/>
         <return type-id='c894953d'/>
       </function-decl>
-      <function-decl name='synchronize_net' mangled-name='synchronize_net' filepath='include/linux/netdevice.h' line='2675' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='synchronize_net'>
+      <function-decl name='synchronize_net' mangled-name='synchronize_net' filepath='include/linux/netdevice.h' line='2674' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='synchronize_net'>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='netif_napi_del' mangled-name='netif_napi_del' filepath='include/linux/netdevice.h' line='2281' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_napi_del'>
+      <function-decl name='netif_napi_del' mangled-name='netif_napi_del' filepath='include/linux/netdevice.h' line='2280' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_napi_del'>
         <parameter type-id='c50361c5'/>
         <return type-id='48b5725f'/>
       </function-decl>
@@ -84586,7 +84634,7 @@
         <parameter type-id='95e97e5e'/>
         <return type-id='c894953d'/>
       </function-decl>
-      <function-decl name='napi_gro_receive' mangled-name='napi_gro_receive' filepath='include/linux/netdevice.h' line='3626' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='napi_gro_receive'>
+      <function-decl name='napi_gro_receive' mangled-name='napi_gro_receive' filepath='include/linux/netdevice.h' line='3625' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='napi_gro_receive'>
         <parameter type-id='c50361c5'/>
         <parameter type-id='0fbf3cfd'/>
         <return type-id='3facc5aa'/>
@@ -85443,7 +85491,7 @@
         <parameter type-id='63d7819b'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='dev_get_by_name' mangled-name='dev_get_by_name' filepath='include/linux/netdevice.h' line='2646' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='dev_get_by_name'>
+      <function-decl name='dev_get_by_name' mangled-name='dev_get_by_name' filepath='include/linux/netdevice.h' line='2645' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='dev_get_by_name'>
         <parameter type-id='a2bff676'/>
         <parameter type-id='80f4b756'/>
         <return type-id='68a2d05b'/>
@@ -86857,7 +86905,7 @@
         <parameter type-id='807869d3'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='clk_set_rate' mangled-name='clk_set_rate' filepath='include/linux/clk.h' line='538' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_set_rate'>
+      <function-decl name='clk_set_rate' mangled-name='clk_set_rate' filepath='include/linux/clk.h' line='546' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_set_rate'>
         <parameter type-id='7d0bc0eb'/>
         <parameter type-id='7359adad'/>
         <return type-id='95e97e5e'/>
@@ -86885,7 +86933,7 @@
       </function-decl>
     </abi-instr>
     <abi-instr address-size='64' path='drivers/pci/irq.c' language='LANG_C89'>
-      <function-decl name='pci_irq_vector' mangled-name='pci_irq_vector' filepath='include/linux/pci.h' line='1405' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_irq_vector'>
+      <function-decl name='pci_irq_vector' mangled-name='pci_irq_vector' filepath='include/linux/pci.h' line='1406' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_irq_vector'>
         <parameter type-id='85196e3f'/>
         <parameter type-id='f0981eeb'/>
         <return type-id='95e97e5e'/>
@@ -86964,8 +87012,8 @@
         <parameter type-id='95e97e5e' name='cap' filepath='drivers/pci/pci.c' line='393' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='pci_device_is_present' mangled-name='pci_device_is_present' filepath='drivers/pci/pci.c' line='5815' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_device_is_present'>
-        <parameter type-id='85196e3f' name='pdev' filepath='drivers/pci/pci.c' line='5815' column='1'/>
+      <function-decl name='pci_device_is_present' mangled-name='pci_device_is_present' filepath='drivers/pci/pci.c' line='5817' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_device_is_present'>
+        <parameter type-id='85196e3f' name='pdev' filepath='drivers/pci/pci.c' line='5817' column='1'/>
         <return type-id='b50a4934'/>
       </function-decl>
       <function-decl name='pci_enable_device' mangled-name='pci_enable_device' filepath='drivers/pci/pci.c' line='1656' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_enable_device'>
@@ -87082,12 +87130,12 @@
         <parameter type-id='92d15ae9'/>
         <return type-id='fa0b179b'/>
       </function-decl>
-      <function-decl name='pci_find_capability' mangled-name='pci_find_capability' filepath='include/linux/pci.h' line='987' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_find_capability'>
+      <function-decl name='pci_find_capability' mangled-name='pci_find_capability' filepath='include/linux/pci.h' line='988' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_find_capability'>
         <parameter type-id='85196e3f'/>
         <parameter type-id='95e97e5e'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='pci_find_ext_capability' mangled-name='pci_find_ext_capability' filepath='include/linux/pci.h' line='989' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_find_ext_capability'>
+      <function-decl name='pci_find_ext_capability' mangled-name='pci_find_ext_capability' filepath='include/linux/pci.h' line='990' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_find_ext_capability'>
         <parameter type-id='85196e3f'/>
         <parameter type-id='95e97e5e'/>
         <return type-id='95e97e5e'/>
@@ -88171,32 +88219,32 @@
       </function-decl>
     </abi-instr>
     <abi-instr address-size='64' path='drivers/power/supply/power_supply_core.c' language='LANG_C89'>
-      <function-decl name='power_supply_get_by_name' mangled-name='power_supply_get_by_name' filepath='drivers/power/supply/power_supply_core.c' line='454' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='power_supply_get_by_name'>
-        <parameter type-id='80f4b756' name='name' filepath='drivers/power/supply/power_supply_core.c' line='454' column='1'/>
+      <function-decl name='power_supply_get_by_name' mangled-name='power_supply_get_by_name' filepath='drivers/power/supply/power_supply_core.c' line='461' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='power_supply_get_by_name'>
+        <parameter type-id='80f4b756' name='name' filepath='drivers/power/supply/power_supply_core.c' line='461' column='1'/>
         <return type-id='c0c93c9e'/>
       </function-decl>
-      <function-decl name='power_supply_put' mangled-name='power_supply_put' filepath='drivers/power/supply/power_supply_core.c' line='476' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='power_supply_put'>
-        <parameter type-id='c0c93c9e' name='psy' filepath='drivers/power/supply/power_supply_core.c' line='476' column='1'/>
+      <function-decl name='power_supply_put' mangled-name='power_supply_put' filepath='drivers/power/supply/power_supply_core.c' line='483' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='power_supply_put'>
+        <parameter type-id='c0c93c9e' name='psy' filepath='drivers/power/supply/power_supply_core.c' line='483' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='power_supply_get_property' mangled-name='power_supply_get_property' filepath='drivers/power/supply/power_supply_core.c' line='624' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='power_supply_get_property'>
-        <parameter type-id='c0c93c9e' name='psy' filepath='drivers/power/supply/power_supply_core.c' line='624' column='1'/>
-        <parameter type-id='5f78aa17' name='psp' filepath='drivers/power/supply/power_supply_core.c' line='625' column='1'/>
-        <parameter type-id='2e53d20f' name='val' filepath='drivers/power/supply/power_supply_core.c' line='626' column='1'/>
+      <function-decl name='power_supply_get_property' mangled-name='power_supply_get_property' filepath='drivers/power/supply/power_supply_core.c' line='631' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='power_supply_get_property'>
+        <parameter type-id='c0c93c9e' name='psy' filepath='drivers/power/supply/power_supply_core.c' line='631' column='1'/>
+        <parameter type-id='5f78aa17' name='psp' filepath='drivers/power/supply/power_supply_core.c' line='632' column='1'/>
+        <parameter type-id='2e53d20f' name='val' filepath='drivers/power/supply/power_supply_core.c' line='633' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='power_supply_set_property' mangled-name='power_supply_set_property' filepath='drivers/power/supply/power_supply_core.c' line='638' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='power_supply_set_property'>
-        <parameter type-id='c0c93c9e' name='psy' filepath='drivers/power/supply/power_supply_core.c' line='638' column='1'/>
-        <parameter type-id='5f78aa17' name='psp' filepath='drivers/power/supply/power_supply_core.c' line='639' column='1'/>
-        <parameter type-id='f3abafd4' name='val' filepath='drivers/power/supply/power_supply_core.c' line='640' column='1'/>
+      <function-decl name='power_supply_set_property' mangled-name='power_supply_set_property' filepath='drivers/power/supply/power_supply_core.c' line='645' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='power_supply_set_property'>
+        <parameter type-id='c0c93c9e' name='psy' filepath='drivers/power/supply/power_supply_core.c' line='645' column='1'/>
+        <parameter type-id='5f78aa17' name='psp' filepath='drivers/power/supply/power_supply_core.c' line='646' column='1'/>
+        <parameter type-id='f3abafd4' name='val' filepath='drivers/power/supply/power_supply_core.c' line='647' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='power_supply_reg_notifier' mangled-name='power_supply_reg_notifier' filepath='drivers/power/supply/power_supply_core.c' line='683' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='power_supply_reg_notifier'>
-        <parameter type-id='d504f73d' name='nb' filepath='drivers/power/supply/power_supply_core.c' line='683' column='1'/>
+      <function-decl name='power_supply_reg_notifier' mangled-name='power_supply_reg_notifier' filepath='drivers/power/supply/power_supply_core.c' line='690' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='power_supply_reg_notifier'>
+        <parameter type-id='d504f73d' name='nb' filepath='drivers/power/supply/power_supply_core.c' line='690' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='power_supply_unreg_notifier' mangled-name='power_supply_unreg_notifier' filepath='drivers/power/supply/power_supply_core.c' line='689' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='power_supply_unreg_notifier'>
-        <parameter type-id='d504f73d' name='nb' filepath='drivers/power/supply/power_supply_core.c' line='689' column='1'/>
+      <function-decl name='power_supply_unreg_notifier' mangled-name='power_supply_unreg_notifier' filepath='drivers/power/supply/power_supply_core.c' line='696' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='power_supply_unreg_notifier'>
+        <parameter type-id='d504f73d' name='nb' filepath='drivers/power/supply/power_supply_core.c' line='696' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
       <function-decl name='thermal_cooling_device_unregister' mangled-name='thermal_cooling_device_unregister' filepath='include/linux/thermal.h' line='528' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='thermal_cooling_device_unregister'>
@@ -91003,9 +91051,9 @@
           <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/scsi/scsi_device.h' line='240' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='execute_work' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='174' column='1' id='53f7ea88'>
+      <class-decl name='execute_work' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='175' column='1' id='53f7ea88'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='work' type-id='ef9025d0' visibility='default' filepath='include/linux/workqueue.h' line='175' column='1'/>
+          <var-decl name='work' type-id='ef9025d0' visibility='default' filepath='include/linux/workqueue.h' line='176' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='scsi_device_state' filepath='include/scsi/scsi_device.h' line='37' column='1' id='7e4b2e83'>
@@ -91176,17 +91224,17 @@
         <parameter type-id='0b8718c0'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='scsi_block_requests' mangled-name='scsi_block_requests' filepath='drivers/scsi/scsi_lib.c' line='2442' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='scsi_block_requests'>
-        <parameter type-id='a970a64c' name='shost' filepath='drivers/scsi/scsi_lib.c' line='2442' column='1'/>
+      <function-decl name='scsi_block_requests' mangled-name='scsi_block_requests' filepath='drivers/scsi/scsi_lib.c' line='2444' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='scsi_block_requests'>
+        <parameter type-id='a970a64c' name='shost' filepath='drivers/scsi/scsi_lib.c' line='2444' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='scsi_unblock_requests' mangled-name='scsi_unblock_requests' filepath='drivers/scsi/scsi_lib.c' line='2468' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='scsi_unblock_requests'>
-        <parameter type-id='a970a64c' name='shost' filepath='drivers/scsi/scsi_lib.c' line='2468' column='1'/>
+      <function-decl name='scsi_unblock_requests' mangled-name='scsi_unblock_requests' filepath='drivers/scsi/scsi_lib.c' line='2470' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='scsi_unblock_requests'>
+        <parameter type-id='a970a64c' name='shost' filepath='drivers/scsi/scsi_lib.c' line='2470' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='scsi_set_cmd_timeout_override' mangled-name='scsi_set_cmd_timeout_override' filepath='drivers/scsi/scsi_lib.c' line='2495' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='scsi_set_cmd_timeout_override'>
-        <parameter type-id='eb572b74' name='sdev' filepath='drivers/scsi/scsi_lib.c' line='2495' column='1'/>
-        <parameter type-id='f0981eeb' name='timeout' filepath='drivers/scsi/scsi_lib.c' line='2496' column='1'/>
+      <function-decl name='scsi_set_cmd_timeout_override' mangled-name='scsi_set_cmd_timeout_override' filepath='drivers/scsi/scsi_lib.c' line='2497' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='scsi_set_cmd_timeout_override'>
+        <parameter type-id='eb572b74' name='sdev' filepath='drivers/scsi/scsi_lib.c' line='2497' column='1'/>
+        <parameter type-id='f0981eeb' name='timeout' filepath='drivers/scsi/scsi_lib.c' line='2498' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
       <class-decl name='scsi_sense_hdr' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/scsi/scsi_common.h' line='50' column='1' id='d6746ce3'>
@@ -92505,9 +92553,9 @@
         </data-member>
       </class-decl>
       <typedef-decl name='blist_flags_t' type-id='d3130597' filepath='include/scsi/scsi_device.h' line='19' column='1' id='ec838379'/>
-      <class-decl name='execute_work' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='174' column='1' id='53f7ea88'>
+      <class-decl name='execute_work' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='175' column='1' id='53f7ea88'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='work' type-id='ef9025d0' visibility='default' filepath='include/linux/workqueue.h' line='175' column='1'/>
+          <var-decl name='work' type-id='ef9025d0' visibility='default' filepath='include/linux/workqueue.h' line='176' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='scsi_device_state' filepath='include/scsi/scsi_device.h' line='37' column='1' id='7e4b2e83'>
@@ -94215,7 +94263,7 @@
         <parameter type-id='fa0b179b'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='clk_get_rate' mangled-name='clk_get_rate' filepath='include/linux/clk.h' line='463' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_get_rate'>
+      <function-decl name='clk_get_rate' mangled-name='clk_get_rate' filepath='include/linux/clk.h' line='471' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='clk_get_rate'>
         <parameter type-id='7d0bc0eb'/>
         <return type-id='7359adad'/>
       </function-decl>
@@ -104054,7 +104102,7 @@
       <pointer-type-def type-id='73956807' size-in-bits='64' id='2e0bb6d4'/>
       <pointer-type-def type-id='3e02e52d' size-in-bits='64' id='997bd29d'/>
       <pointer-type-def type-id='7607667c' size-in-bits='64' id='644da7aa'/>
-      <function-decl name='pci_unregister_driver' mangled-name='pci_unregister_driver' filepath='include/linux/pci.h' line='1307' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_unregister_driver'>
+      <function-decl name='pci_unregister_driver' mangled-name='pci_unregister_driver' filepath='include/linux/pci.h' line='1308' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_unregister_driver'>
         <parameter type-id='85b59624'/>
         <return type-id='48b5725f'/>
       </function-decl>
@@ -104098,7 +104146,7 @@
         <parameter type-id='c894953d'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='pci_read_config_byte' mangled-name='pci_read_config_byte' filepath='include/linux/pci.h' line='1030' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_read_config_byte'>
+      <function-decl name='pci_read_config_byte' mangled-name='pci_read_config_byte' filepath='include/linux/pci.h' line='1031' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_read_config_byte'>
         <parameter type-id='947f31e6'/>
         <parameter type-id='95e97e5e'/>
         <parameter type-id='cf536864'/>
@@ -106422,56 +106470,56 @@
       </function-decl>
     </abi-instr>
     <abi-instr address-size='64' path='fs/namei.c' language='LANG_C89'>
-      <function-decl name='user_path_at_empty' mangled-name='user_path_at_empty' filepath='fs/namei.c' line='2690' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='user_path_at_empty'>
-        <parameter type-id='95e97e5e' name='dfd' filepath='fs/namei.c' line='2690' column='1'/>
-        <parameter type-id='80f4b756' name='name' filepath='fs/namei.c' line='2690' column='1'/>
-        <parameter type-id='f0981eeb' name='flags' filepath='fs/namei.c' line='2690' column='1'/>
-        <parameter type-id='bcfe6314' name='path' filepath='fs/namei.c' line='2691' column='1'/>
-        <parameter type-id='7292109c' name='empty' filepath='fs/namei.c' line='2691' column='1'/>
+      <function-decl name='user_path_at_empty' mangled-name='user_path_at_empty' filepath='fs/namei.c' line='2710' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='user_path_at_empty'>
+        <parameter type-id='95e97e5e' name='dfd' filepath='fs/namei.c' line='2710' column='1'/>
+        <parameter type-id='80f4b756' name='name' filepath='fs/namei.c' line='2710' column='1'/>
+        <parameter type-id='f0981eeb' name='flags' filepath='fs/namei.c' line='2710' column='1'/>
+        <parameter type-id='bcfe6314' name='path' filepath='fs/namei.c' line='2711' column='1'/>
+        <parameter type-id='7292109c' name='empty' filepath='fs/namei.c' line='2711' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='vfs_create' mangled-name='vfs_create' filepath='fs/namei.c' line='2983' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='vfs_create'>
-        <parameter type-id='7e666abe' name='dir' filepath='fs/namei.c' line='2983' column='1'/>
-        <parameter type-id='27675065' name='dentry' filepath='fs/namei.c' line='2983' column='1'/>
-        <parameter type-id='2594b00f' name='mode' filepath='fs/namei.c' line='2983' column='1'/>
-        <parameter type-id='b50a4934' name='want_excl' filepath='fs/namei.c' line='2984' column='1'/>
+      <function-decl name='vfs_create' mangled-name='vfs_create' filepath='fs/namei.c' line='3003' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='vfs_create'>
+        <parameter type-id='7e666abe' name='dir' filepath='fs/namei.c' line='3003' column='1'/>
+        <parameter type-id='27675065' name='dentry' filepath='fs/namei.c' line='3003' column='1'/>
+        <parameter type-id='2594b00f' name='mode' filepath='fs/namei.c' line='3003' column='1'/>
+        <parameter type-id='b50a4934' name='want_excl' filepath='fs/namei.c' line='3004' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='vfs_mkdir' mangled-name='vfs_mkdir' filepath='fs/namei.c' line='3886' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='vfs_mkdir'>
-        <parameter type-id='7e666abe' name='dir' filepath='fs/namei.c' line='3886' column='1'/>
-        <parameter type-id='27675065' name='dentry' filepath='fs/namei.c' line='3886' column='1'/>
-        <parameter type-id='2594b00f' name='mode' filepath='fs/namei.c' line='3886' column='1'/>
+      <function-decl name='vfs_mkdir' mangled-name='vfs_mkdir' filepath='fs/namei.c' line='3906' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='vfs_mkdir'>
+        <parameter type-id='7e666abe' name='dir' filepath='fs/namei.c' line='3906' column='1'/>
+        <parameter type-id='27675065' name='dentry' filepath='fs/namei.c' line='3906' column='1'/>
+        <parameter type-id='2594b00f' name='mode' filepath='fs/namei.c' line='3906' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='vfs_rmdir' mangled-name='vfs_rmdir' filepath='fs/namei.c' line='3947' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='vfs_rmdir'>
-        <parameter type-id='7e666abe' name='dir' filepath='fs/namei.c' line='3947' column='1'/>
-        <parameter type-id='27675065' name='dentry' filepath='fs/namei.c' line='3947' column='1'/>
+      <function-decl name='vfs_rmdir' mangled-name='vfs_rmdir' filepath='fs/namei.c' line='3967' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='vfs_rmdir'>
+        <parameter type-id='7e666abe' name='dir' filepath='fs/namei.c' line='3967' column='1'/>
+        <parameter type-id='27675065' name='dentry' filepath='fs/namei.c' line='3967' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
       <function-decl name='d_delete' mangled-name='d_delete' filepath='include/linux/dcache.h' line='241' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='d_delete'>
         <parameter type-id='27675065'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='vfs_unlink' mangled-name='vfs_unlink' filepath='fs/namei.c' line='4068' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='vfs_unlink'>
-        <parameter type-id='7e666abe' name='dir' filepath='fs/namei.c' line='4068' column='1'/>
-        <parameter type-id='27675065' name='dentry' filepath='fs/namei.c' line='4068' column='1'/>
-        <parameter type-id='8f39c6fc' name='delegated_inode' filepath='fs/namei.c' line='4068' column='1'/>
+      <function-decl name='vfs_unlink' mangled-name='vfs_unlink' filepath='fs/namei.c' line='4088' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='vfs_unlink'>
+        <parameter type-id='7e666abe' name='dir' filepath='fs/namei.c' line='4088' column='1'/>
+        <parameter type-id='27675065' name='dentry' filepath='fs/namei.c' line='4088' column='1'/>
+        <parameter type-id='8f39c6fc' name='delegated_inode' filepath='fs/namei.c' line='4088' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='vfs_link' mangled-name='vfs_link' filepath='fs/namei.c' line='4283' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='vfs_link'>
-        <parameter type-id='27675065' name='old_dentry' filepath='fs/namei.c' line='4283' column='1'/>
-        <parameter type-id='7e666abe' name='dir' filepath='fs/namei.c' line='4283' column='1'/>
-        <parameter type-id='27675065' name='new_dentry' filepath='fs/namei.c' line='4283' column='1'/>
-        <parameter type-id='8f39c6fc' name='delegated_inode' filepath='fs/namei.c' line='4283' column='1'/>
+      <function-decl name='vfs_link' mangled-name='vfs_link' filepath='fs/namei.c' line='4303' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='vfs_link'>
+        <parameter type-id='27675065' name='old_dentry' filepath='fs/namei.c' line='4303' column='1'/>
+        <parameter type-id='7e666abe' name='dir' filepath='fs/namei.c' line='4303' column='1'/>
+        <parameter type-id='27675065' name='new_dentry' filepath='fs/namei.c' line='4303' column='1'/>
+        <parameter type-id='8f39c6fc' name='delegated_inode' filepath='fs/namei.c' line='4303' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='vfs_rename' mangled-name='vfs_rename' filepath='fs/namei.c' line='4479' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='vfs_rename'>
-        <parameter type-id='7e666abe' name='old_dir' filepath='fs/namei.c' line='4479' column='1'/>
-        <parameter type-id='27675065' name='old_dentry' filepath='fs/namei.c' line='4479' column='1'/>
-        <parameter type-id='7e666abe' name='new_dir' filepath='fs/namei.c' line='4480' column='1'/>
-        <parameter type-id='27675065' name='new_dentry' filepath='fs/namei.c' line='4480' column='1'/>
-        <parameter type-id='8f39c6fc' name='delegated_inode' filepath='fs/namei.c' line='4481' column='1'/>
-        <parameter type-id='f0981eeb' name='flags' filepath='fs/namei.c' line='4481' column='1'/>
+      <function-decl name='vfs_rename' mangled-name='vfs_rename' filepath='fs/namei.c' line='4499' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='vfs_rename'>
+        <parameter type-id='7e666abe' name='old_dir' filepath='fs/namei.c' line='4499' column='1'/>
+        <parameter type-id='27675065' name='old_dentry' filepath='fs/namei.c' line='4499' column='1'/>
+        <parameter type-id='7e666abe' name='new_dir' filepath='fs/namei.c' line='4500' column='1'/>
+        <parameter type-id='27675065' name='new_dentry' filepath='fs/namei.c' line='4500' column='1'/>
+        <parameter type-id='8f39c6fc' name='delegated_inode' filepath='fs/namei.c' line='4501' column='1'/>
+        <parameter type-id='f0981eeb' name='flags' filepath='fs/namei.c' line='4501' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
       <pointer-type-def type-id='7e666abe' size-in-bits='64' id='8f39c6fc'/>
@@ -106573,7 +106621,7 @@
           <var-decl name='' type-id='0394b7eb' visibility='default' filepath='include/linux/exportfs.h' line='114' column='1'/>
         </data-member>
       </class-decl>
-      <union-decl name='__anonymous_union__16' size-in-bits='160' is-anonymous='yes' visibility='default' filepath='include/linux/exportfs.h' line='114' column='1' id='0394b7eb'>
+      <union-decl name='__anonymous_union__1' size-in-bits='160' is-anonymous='yes' visibility='default' filepath='include/linux/exportfs.h' line='114' column='1' id='0394b7eb'>
         <data-member access='public'>
           <var-decl name='i32' type-id='273ef6eb' visibility='default' filepath='include/linux/exportfs.h' line='120' column='1'/>
         </data-member>
@@ -106584,7 +106632,7 @@
           <var-decl name='raw' type-id='d5016f6f' visibility='default' filepath='include/linux/exportfs.h' line='129' column='1'/>
         </data-member>
       </union-decl>
-      <class-decl name='__anonymous_struct__6' size-in-bits='128' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/exportfs.h' line='115' column='1' id='273ef6eb'>
+      <class-decl name='__anonymous_struct__1' size-in-bits='128' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/exportfs.h' line='115' column='1' id='273ef6eb'>
         <data-member access='public' layout-offset-in-bits='0'>
           <var-decl name='ino' type-id='19c2251e' visibility='default' filepath='include/linux/exportfs.h' line='116' column='1'/>
         </data-member>
@@ -106598,7 +106646,7 @@
           <var-decl name='parent_gen' type-id='19c2251e' visibility='default' filepath='include/linux/exportfs.h' line='119' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='__anonymous_struct__7' size-in-bits='160' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/exportfs.h' line='121' column='1' id='2d08566e'>
+      <class-decl name='__anonymous_struct__2' size-in-bits='160' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/exportfs.h' line='121' column='1' id='2d08566e'>
         <data-member access='public' layout-offset-in-bits='0'>
           <var-decl name='block' type-id='19c2251e' visibility='default' filepath='include/linux/exportfs.h' line='122' column='1'/>
         </data-member>
@@ -106659,12 +106707,12 @@
         <parameter type-id='a77efac3'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='lock_rename' mangled-name='lock_rename' filepath='include/linux/namei.h' line='92' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='lock_rename'>
+      <function-decl name='lock_rename' mangled-name='lock_rename' filepath='include/linux/namei.h' line='93' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='lock_rename'>
         <parameter type-id='27675065'/>
         <parameter type-id='27675065'/>
         <return type-id='27675065'/>
       </function-decl>
-      <function-decl name='unlock_rename' mangled-name='unlock_rename' filepath='include/linux/namei.h' line='93' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='unlock_rename'>
+      <function-decl name='unlock_rename' mangled-name='unlock_rename' filepath='include/linux/namei.h' line='94' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='unlock_rename'>
         <parameter type-id='27675065'/>
         <parameter type-id='27675065'/>
         <return type-id='48b5725f'/>
@@ -107848,24 +107896,24 @@
       <array-type-def dimensions='1' type-id='a84c031d' size-in-bits='520' id='5ddd38d2'>
         <subrange length='65' type-id='7ff19f0f' id='b50e2e4a'/>
       </array-type-def>
-      <class-decl name='trace_subsystem_dir' size-in-bits='384' is-struct='yes' visibility='default' filepath='kernel/trace/trace.h' line='1299' column='1' id='10143522'>
+      <class-decl name='trace_subsystem_dir' size-in-bits='384' is-struct='yes' visibility='default' filepath='kernel/trace/trace.h' line='1301' column='1' id='10143522'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='kernel/trace/trace.h' line='1300' column='1'/>
+          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='kernel/trace/trace.h' line='1302' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='subsystem' type-id='841939f3' visibility='default' filepath='kernel/trace/trace.h' line='1301' column='1'/>
+          <var-decl name='subsystem' type-id='841939f3' visibility='default' filepath='kernel/trace/trace.h' line='1303' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='tr' type-id='898c1076' visibility='default' filepath='kernel/trace/trace.h' line='1302' column='1'/>
+          <var-decl name='tr' type-id='898c1076' visibility='default' filepath='kernel/trace/trace.h' line='1304' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='entry' type-id='27675065' visibility='default' filepath='kernel/trace/trace.h' line='1303' column='1'/>
+          <var-decl name='entry' type-id='27675065' visibility='default' filepath='kernel/trace/trace.h' line='1305' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='ref_count' type-id='95e97e5e' visibility='default' filepath='kernel/trace/trace.h' line='1304' column='1'/>
+          <var-decl name='ref_count' type-id='95e97e5e' visibility='default' filepath='kernel/trace/trace.h' line='1306' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='352'>
-          <var-decl name='nr_events' type-id='95e97e5e' visibility='default' filepath='kernel/trace/trace.h' line='1305' column='1'/>
+          <var-decl name='nr_events' type-id='95e97e5e' visibility='default' filepath='kernel/trace/trace.h' line='1307' column='1'/>
         </data-member>
       </class-decl>
       <array-type-def dimensions='1' type-id='19c2251e' size-in-bits='infinite' id='c165e8b9'>
@@ -107986,7 +108034,7 @@
       <pointer-type-def type-id='10143522' size-in-bits='64' id='f4f46ed0'/>
       <pointer-type-def type-id='61062930' size-in-bits='64' id='6fa26802'/>
       <pointer-type-def type-id='107219ed' size-in-bits='64' id='277e3361'/>
-      <var-decl name='system_state' type-id='2ead22b4' mangled-name='system_state' visibility='default' filepath='init/main.c' line='119' column='1' elf-symbol-id='system_state'/>
+      <var-decl name='system_state' type-id='2ead22b4' mangled-name='system_state' visibility='default' filepath='init/main.c' line='117' column='1' elf-symbol-id='system_state'/>
       <function-decl name='event_triggers_call' mangled-name='event_triggers_call' filepath='include/linux/trace_events.h' line='434' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='event_triggers_call'>
         <parameter type-id='3d4ca6d2'/>
         <parameter type-id='eaa32e2f'/>
@@ -108007,13 +108055,13 @@
         <parameter type-id='9f548f9a'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='perf_trace_buf_alloc' mangled-name='perf_trace_buf_alloc' filepath='include/linux/trace_events.h' line='590' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='perf_trace_buf_alloc'>
+      <function-decl name='perf_trace_buf_alloc' mangled-name='perf_trace_buf_alloc' filepath='include/linux/trace_events.h' line='591' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='perf_trace_buf_alloc'>
         <parameter type-id='95e97e5e'/>
         <parameter type-id='a89ff5a9'/>
         <parameter type-id='7292109c'/>
         <return type-id='eaa32e2f'/>
       </function-decl>
-      <function-decl name='perf_trace_run_bpf_submit' mangled-name='perf_trace_run_bpf_submit' filepath='include/linux/trace_events.h' line='619' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='perf_trace_run_bpf_submit'>
+      <function-decl name='perf_trace_run_bpf_submit' mangled-name='perf_trace_run_bpf_submit' filepath='include/linux/trace_events.h' line='620' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='perf_trace_run_bpf_submit'>
         <parameter type-id='eaa32e2f'/>
         <parameter type-id='95e97e5e'/>
         <parameter type-id='95e97e5e'/>
@@ -108034,12 +108082,12 @@
         <parameter type-id='95e97e5e'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='bpf_trace_run1' mangled-name='bpf_trace_run1' filepath='include/linux/trace_events.h' line='592' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='bpf_trace_run1'>
+      <function-decl name='bpf_trace_run1' mangled-name='bpf_trace_run1' filepath='include/linux/trace_events.h' line='593' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='bpf_trace_run1'>
         <parameter type-id='bdcee7ae'/>
         <parameter type-id='3a47d82b'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='bpf_trace_run2' mangled-name='bpf_trace_run2' filepath='include/linux/trace_events.h' line='593' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='bpf_trace_run2'>
+      <function-decl name='bpf_trace_run2' mangled-name='bpf_trace_run2' filepath='include/linux/trace_events.h' line='594' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='bpf_trace_run2'>
         <parameter type-id='bdcee7ae'/>
         <parameter type-id='3a47d82b'/>
         <parameter type-id='3a47d82b'/>
@@ -108050,7 +108098,7 @@
         <parameter type-id='7292109c'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='find_last_bit' mangled-name='find_last_bit' filepath='include/linux/bitops.h' line='284' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='find_last_bit'>
+      <function-decl name='find_last_bit' mangled-name='find_last_bit' filepath='include/linux/bitops.h' line='285' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='find_last_bit'>
         <parameter type-id='f9b37274'/>
         <parameter type-id='7359adad'/>
         <return type-id='7359adad'/>
@@ -108119,18 +108167,18 @@
       <pointer-type-def type-id='e27b4e90' size-in-bits='64' id='898c1076'/>
       <pointer-type-def type-id='78b26ac9' size-in-bits='64' id='fb7d87a1'/>
       <pointer-type-def type-id='60588bb1' size-in-bits='64' id='18881289'/>
-      <class-decl name='event_subsystem' size-in-bits='320' is-struct='yes' visibility='default' filepath='kernel/trace/trace.h' line='1292' column='1' id='ba400603'>
+      <class-decl name='event_subsystem' size-in-bits='320' is-struct='yes' visibility='default' filepath='kernel/trace/trace.h' line='1294' column='1' id='ba400603'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='kernel/trace/trace.h' line='1293' column='1'/>
+          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='kernel/trace/trace.h' line='1295' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='name' type-id='80f4b756' visibility='default' filepath='kernel/trace/trace.h' line='1294' column='1'/>
+          <var-decl name='name' type-id='80f4b756' visibility='default' filepath='kernel/trace/trace.h' line='1296' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='filter' type-id='26461068' visibility='default' filepath='kernel/trace/trace.h' line='1295' column='1'/>
+          <var-decl name='filter' type-id='26461068' visibility='default' filepath='kernel/trace/trace.h' line='1297' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ref_count' type-id='95e97e5e' visibility='default' filepath='kernel/trace/trace.h' line='1296' column='1'/>
+          <var-decl name='ref_count' type-id='95e97e5e' visibility='default' filepath='kernel/trace/trace.h' line='1298' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='seq_buf' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/seq_buf.h' line='19' column='1' id='857188d6'>
@@ -109250,7 +109298,7 @@
       <var-decl name='__cpu_online_mask' type-id='1354385d' mangled-name='__cpu_online_mask' visibility='default' filepath='kernel/cpu.c' line='2356' column='1' elf-symbol-id='__cpu_online_mask'/>
       <var-decl name='__cpu_present_mask' type-id='1354385d' mangled-name='__cpu_present_mask' visibility='default' filepath='kernel/cpu.c' line='2359' column='1' elf-symbol-id='__cpu_present_mask'/>
       <var-decl name='__cpu_isolated_mask' type-id='1354385d' mangled-name='__cpu_isolated_mask' visibility='default' filepath='kernel/cpu.c' line='2365' column='1' elf-symbol-id='__cpu_isolated_mask'/>
-      <function-decl name='bpf_trace_run4' mangled-name='bpf_trace_run4' filepath='include/linux/trace_events.h' line='596' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='bpf_trace_run4'>
+      <function-decl name='bpf_trace_run4' mangled-name='bpf_trace_run4' filepath='include/linux/trace_events.h' line='597' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='bpf_trace_run4'>
         <parameter type-id='bdcee7ae'/>
         <parameter type-id='3a47d82b'/>
         <parameter type-id='3a47d82b'/>
@@ -109258,7 +109306,7 @@
         <parameter type-id='3a47d82b'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='bpf_trace_run5' mangled-name='bpf_trace_run5' filepath='include/linux/trace_events.h' line='598' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='bpf_trace_run5'>
+      <function-decl name='bpf_trace_run5' mangled-name='bpf_trace_run5' filepath='include/linux/trace_events.h' line='599' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='bpf_trace_run5'>
         <parameter type-id='bdcee7ae'/>
         <parameter type-id='3a47d82b'/>
         <parameter type-id='3a47d82b'/>
@@ -109511,20 +109559,20 @@
         </data-member>
       </class-decl>
       <pointer-type-def type-id='a752caf1' size-in-bits='64' id='4b860c99'/>
-      <function-decl name='perf_pmu_register' mangled-name='perf_pmu_register' filepath='kernel/events/core.c' line='9713' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='perf_pmu_register'>
-        <parameter type-id='0906f5b9' name='pmu' filepath='kernel/events/core.c' line='9713' column='1'/>
-        <parameter type-id='80f4b756' name='name' filepath='kernel/events/core.c' line='9713' column='1'/>
-        <parameter type-id='95e97e5e' name='type' filepath='kernel/events/core.c' line='9713' column='1'/>
+      <function-decl name='perf_pmu_register' mangled-name='perf_pmu_register' filepath='kernel/events/core.c' line='9743' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='perf_pmu_register'>
+        <parameter type-id='0906f5b9' name='pmu' filepath='kernel/events/core.c' line='9743' column='1'/>
+        <parameter type-id='80f4b756' name='name' filepath='kernel/events/core.c' line='9743' column='1'/>
+        <parameter type-id='95e97e5e' name='type' filepath='kernel/events/core.c' line='9743' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='perf_event_enable' mangled-name='perf_event_enable' filepath='kernel/events/core.c' line='2729' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='perf_event_enable'>
-        <parameter type-id='2bf16f59' name='event' filepath='kernel/events/core.c' line='2729' column='1'/>
+      <function-decl name='perf_event_enable' mangled-name='perf_event_enable' filepath='kernel/events/core.c' line='2736' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='perf_event_enable'>
+        <parameter type-id='2bf16f59' name='event' filepath='kernel/events/core.c' line='2736' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='perf_event_read_value' mangled-name='perf_event_read_value' filepath='kernel/events/core.c' line='4717' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='perf_event_read_value'>
-        <parameter type-id='2bf16f59' name='event' filepath='kernel/events/core.c' line='4717' column='1'/>
-        <parameter type-id='3df9fd28' name='enabled' filepath='kernel/events/core.c' line='4717' column='1'/>
-        <parameter type-id='3df9fd28' name='running' filepath='kernel/events/core.c' line='4717' column='1'/>
+      <function-decl name='perf_event_read_value' mangled-name='perf_event_read_value' filepath='kernel/events/core.c' line='4724' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='perf_event_read_value'>
+        <parameter type-id='2bf16f59' name='event' filepath='kernel/events/core.c' line='4724' column='1'/>
+        <parameter type-id='3df9fd28' name='enabled' filepath='kernel/events/core.c' line='4724' column='1'/>
+        <parameter type-id='3df9fd28' name='running' filepath='kernel/events/core.c' line='4724' column='1'/>
         <return type-id='91ce1af9'/>
       </function-decl>
       <function-decl name='bus_register' mangled-name='bus_register' filepath='include/linux/device.h' line='162' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='bus_register'>
@@ -110255,12 +110303,12 @@
         <parameter type-id='2730d015' name='module' filepath='kernel/module.c' line='1110' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='module_layout' mangled-name='module_layout' filepath='kernel/module.c' line='4491' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='module_layout'>
-        <parameter type-id='2730d015' name='mod' filepath='kernel/module.c' line='4491' column='1'/>
-        <parameter type-id='3a498c74' name='ver' filepath='kernel/module.c' line='4492' column='1'/>
-        <parameter type-id='a7c6e908' name='kp' filepath='kernel/module.c' line='4493' column='1'/>
-        <parameter type-id='eefd7061' name='ks' filepath='kernel/module.c' line='4494' column='1'/>
-        <parameter type-id='e525e121' name='tp' filepath='kernel/module.c' line='4495' column='1'/>
+      <function-decl name='module_layout' mangled-name='module_layout' filepath='kernel/module.c' line='4502' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='module_layout'>
+        <parameter type-id='2730d015' name='mod' filepath='kernel/module.c' line='4502' column='1'/>
+        <parameter type-id='3a498c74' name='ver' filepath='kernel/module.c' line='4503' column='1'/>
+        <parameter type-id='a7c6e908' name='kp' filepath='kernel/module.c' line='4504' column='1'/>
+        <parameter type-id='eefd7061' name='ks' filepath='kernel/module.c' line='4505' column='1'/>
+        <parameter type-id='e525e121' name='tp' filepath='kernel/module.c' line='4506' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
       <function-decl name='sysfs_remove_link' mangled-name='sysfs_remove_link' filepath='include/linux/sysfs.h' line='258' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sysfs_remove_link'>
@@ -110488,7 +110536,7 @@
       </function-decl>
     </abi-instr>
     <abi-instr address-size='64' path='kernel/power/poweroff.c' language='LANG_C89'>
-      <function-decl name='queue_work_on' mangled-name='queue_work_on' filepath='include/linux/workqueue.h' line='470' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='queue_work_on'>
+      <function-decl name='queue_work_on' mangled-name='queue_work_on' filepath='include/linux/workqueue.h' line='471' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='queue_work_on'>
         <parameter type-id='95e97e5e'/>
         <parameter type-id='242e3d19'/>
         <parameter type-id='83c1bde6'/>
@@ -111676,7 +111724,7 @@
       <pointer-type-def type-id='24bb49a8' size-in-bits='64' id='54777a92'/>
       <pointer-type-def type-id='ca7f7878' size-in-bits='64' id='9d640202'/>
       <var-decl name='kstat' type-id='153750ef' mangled-name='kstat' visibility='default' filepath='kernel/sched/core.c' line='3678' column='1' elf-symbol-id='kstat'/>
-      <function-decl name='bpf_trace_run7' mangled-name='bpf_trace_run7' filepath='include/linux/trace_events.h' line='602' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='bpf_trace_run7'>
+      <function-decl name='bpf_trace_run7' mangled-name='bpf_trace_run7' filepath='include/linux/trace_events.h' line='603' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='bpf_trace_run7'>
         <parameter type-id='bdcee7ae'/>
         <parameter type-id='3a47d82b'/>
         <parameter type-id='3a47d82b'/>
@@ -112540,12 +112588,12 @@
           <var-decl name='driver' type-id='00c7b870' visibility='default' filepath='drivers/base/base.h' line='52' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='event_filter' size-in-bits='128' is-struct='yes' visibility='default' filepath='kernel/trace/trace.h' line='1287' column='1' id='5ff1273a'>
+      <class-decl name='event_filter' size-in-bits='128' is-struct='yes' visibility='default' filepath='kernel/trace/trace.h' line='1289' column='1' id='5ff1273a'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='prog' type-id='efd0fdec' visibility='default' filepath='kernel/trace/trace.h' line='1288' column='1'/>
+          <var-decl name='prog' type-id='efd0fdec' visibility='default' filepath='kernel/trace/trace.h' line='1290' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='filter_string' type-id='26a90f95' visibility='default' filepath='kernel/trace/trace.h' line='1289' column='1'/>
+          <var-decl name='filter_string' type-id='26a90f95' visibility='default' filepath='kernel/trace/trace.h' line='1291' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='eventfd_ctx' is-struct='yes' visibility='default' is-declaration-only='yes' id='77dc8383'/>
@@ -113352,18 +113400,18 @@
           <var-decl name='data' type-id='eaa32e2f' visibility='default' filepath='include/linux/mount.h' line='76' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wake_irq' size-in-bits='192' is-struct='yes' visibility='default' filepath='drivers/base/power/power.h' line='30' column='1' id='4657336c'>
+      <class-decl name='wake_irq' size-in-bits='192' is-struct='yes' visibility='default' filepath='drivers/base/power/power.h' line='33' column='1' id='4657336c'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='dev' type-id='fa0b179b' visibility='default' filepath='drivers/base/power/power.h' line='31' column='1'/>
+          <var-decl name='dev' type-id='fa0b179b' visibility='default' filepath='drivers/base/power/power.h' line='34' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='status' type-id='f0981eeb' visibility='default' filepath='drivers/base/power/power.h' line='32' column='1'/>
+          <var-decl name='status' type-id='f0981eeb' visibility='default' filepath='drivers/base/power/power.h' line='35' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='irq' type-id='95e97e5e' visibility='default' filepath='drivers/base/power/power.h' line='33' column='1'/>
+          <var-decl name='irq' type-id='95e97e5e' visibility='default' filepath='drivers/base/power/power.h' line='36' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='name' type-id='80f4b756' visibility='default' filepath='drivers/base/power/power.h' line='34' column='1'/>
+          <var-decl name='name' type-id='80f4b756' visibility='default' filepath='drivers/base/power/power.h' line='37' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='workqueue_struct' size-in-bits='2560' is-struct='yes' visibility='default' filepath='kernel/workqueue.c' line='238' column='1' id='a5159c01'>
@@ -114969,7 +115017,6 @@
         </data-member>
       </class-decl>
       <typedef-decl name='key_serial_t' type-id='3ff5601b' filepath='include/linux/key.h' line='33' column='1' id='c84025ab'/>
-      <typedef-decl name='int32_t' type-id='a7832498' filepath='include/linux/types.h' line='103' column='1' id='3ff5601b'/>
       <union-decl name='key_payload' size-in-bits='256' visibility='default' filepath='include/linux/key.h' line='94' column='1' id='2888d74a'>
         <data-member access='public'>
           <var-decl name='rcu_data0' type-id='eaa32e2f' visibility='default' filepath='include/linux/key.h' line='95' column='1'/>
@@ -114978,6 +115025,7 @@
           <var-decl name='data' type-id='209ef23f' visibility='default' filepath='include/linux/key.h' line='96' column='1'/>
         </data-member>
       </union-decl>
+      <typedef-decl name='int32_t' type-id='a7832498' filepath='include/linux/types.h' line='103' column='1' id='3ff5601b'/>
       <union-decl name='__anonymous_union__3' size-in-bits='192' is-anonymous='yes' visibility='default' filepath='include/linux/key.h' line='158' column='1' id='1a65b0a7'>
         <data-member access='public'>
           <var-decl name='graveyard_link' type-id='72f469ec' visibility='default' filepath='include/linux/key.h' line='159' column='1'/>
@@ -115802,24 +115850,24 @@
         <enumerator name='WB_REASON_FORKER_THREAD' value='7'/>
         <enumerator name='WB_REASON_MAX' value='8'/>
       </enum-decl>
-      <class-decl name='delayed_work' size-in-bits='1088' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='118' column='1' id='5ad6e0ef'>
+      <class-decl name='delayed_work' size-in-bits='1088' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='119' column='1' id='5ad6e0ef'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='work' type-id='ef9025d0' visibility='default' filepath='include/linux/workqueue.h' line='119' column='1'/>
+          <var-decl name='work' type-id='ef9025d0' visibility='default' filepath='include/linux/workqueue.h' line='120' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='timer' type-id='abe41e67' visibility='default' filepath='include/linux/workqueue.h' line='120' column='1'/>
+          <var-decl name='timer' type-id='abe41e67' visibility='default' filepath='include/linux/workqueue.h' line='121' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='wq' type-id='242e3d19' visibility='default' filepath='include/linux/workqueue.h' line='123' column='1'/>
+          <var-decl name='wq' type-id='242e3d19' visibility='default' filepath='include/linux/workqueue.h' line='124' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='cpu' type-id='95e97e5e' visibility='default' filepath='include/linux/workqueue.h' line='124' column='1'/>
+          <var-decl name='cpu' type-id='95e97e5e' visibility='default' filepath='include/linux/workqueue.h' line='125' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/workqueue.h' line='126' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/workqueue.h' line='127' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/workqueue.h' line='127' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/workqueue.h' line='128' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='percpu_ref' size-in-bits='448' is-struct='yes' visibility='default' filepath='include/linux/percpu-refcount.h' line='88' column='1' id='818799b4'>
@@ -116392,15 +116440,15 @@
         </data-member>
       </class-decl>
       <typedef-decl name='poll_queue_proc' type-id='4aecccbd' filepath='include/linux/poll.h' line='37' column='1' id='650104ba'/>
-      <class-decl name='rcu_work' size-in-bits='576' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='130' column='1' id='7c0b9fdb'>
+      <class-decl name='rcu_work' size-in-bits='576' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='131' column='1' id='7c0b9fdb'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='work' type-id='ef9025d0' visibility='default' filepath='include/linux/workqueue.h' line='131' column='1'/>
+          <var-decl name='work' type-id='ef9025d0' visibility='default' filepath='include/linux/workqueue.h' line='132' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/linux/workqueue.h' line='132' column='1'/>
+          <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='include/linux/workqueue.h' line='133' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='wq' type-id='242e3d19' visibility='default' filepath='include/linux/workqueue.h' line='135' column='1'/>
+          <var-decl name='wq' type-id='242e3d19' visibility='default' filepath='include/linux/workqueue.h' line='136' column='1'/>
         </data-member>
       </class-decl>
       <union-decl name='__anonymous_union__13' size-in-bits='384' is-anonymous='yes' visibility='default' filepath='include/linux/backing-dev-defs.h' line='160' column='1' id='93944b10'>
@@ -119497,47 +119545,47 @@
           <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/device.h' line='458' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='perf_cpu_context' size-in-bits='3136' is-struct='yes' visibility='default' filepath='include/linux/perf_event.h' line='797' column='1' id='4448fdd3'>
+      <class-decl name='perf_cpu_context' size-in-bits='3136' is-struct='yes' visibility='default' filepath='include/linux/perf_event.h' line='800' column='1' id='4448fdd3'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='ctx' type-id='9d67acd5' visibility='default' filepath='include/linux/perf_event.h' line='798' column='1'/>
+          <var-decl name='ctx' type-id='9d67acd5' visibility='default' filepath='include/linux/perf_event.h' line='801' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='task_ctx' type-id='b9419dc5' visibility='default' filepath='include/linux/perf_event.h' line='799' column='1'/>
+          <var-decl name='task_ctx' type-id='b9419dc5' visibility='default' filepath='include/linux/perf_event.h' line='802' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='active_oncpu' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='800' column='1'/>
+          <var-decl name='active_oncpu' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='803' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2144'>
-          <var-decl name='exclusive' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='801' column='1'/>
+          <var-decl name='exclusive' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='804' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2176'>
-          <var-decl name='hrtimer_lock' type-id='f5c90b3f' visibility='default' filepath='include/linux/perf_event.h' line='803' column='1'/>
+          <var-decl name='hrtimer_lock' type-id='f5c90b3f' visibility='default' filepath='include/linux/perf_event.h' line='806' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2240'>
-          <var-decl name='hrtimer' type-id='b6993efc' visibility='default' filepath='include/linux/perf_event.h' line='804' column='1'/>
+          <var-decl name='hrtimer' type-id='b6993efc' visibility='default' filepath='include/linux/perf_event.h' line='807' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2816'>
-          <var-decl name='hrtimer_interval' type-id='fbc017ef' visibility='default' filepath='include/linux/perf_event.h' line='805' column='1'/>
+          <var-decl name='hrtimer_interval' type-id='fbc017ef' visibility='default' filepath='include/linux/perf_event.h' line='808' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2880'>
-          <var-decl name='hrtimer_active' type-id='f0981eeb' visibility='default' filepath='include/linux/perf_event.h' line='806' column='1'/>
+          <var-decl name='hrtimer_active' type-id='f0981eeb' visibility='default' filepath='include/linux/perf_event.h' line='809' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2944'>
-          <var-decl name='sched_cb_entry' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='813' column='1'/>
+          <var-decl name='sched_cb_entry' type-id='72f469ec' visibility='default' filepath='include/linux/perf_event.h' line='816' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3072'>
-          <var-decl name='sched_cb_usage' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='814' column='1'/>
+          <var-decl name='sched_cb_usage' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='817' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3104'>
-          <var-decl name='online' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='816' column='1'/>
+          <var-decl name='online' type-id='95e97e5e' visibility='default' filepath='include/linux/perf_event.h' line='819' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='perf_event_groups' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/linux/perf_event.h' line='726' column='1' id='3643bc2a'>
+      <class-decl name='perf_event_groups' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/linux/perf_event.h' line='729' column='1' id='3643bc2a'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='tree' type-id='dec44472' visibility='default' filepath='include/linux/perf_event.h' line='727' column='1'/>
+          <var-decl name='tree' type-id='dec44472' visibility='default' filepath='include/linux/perf_event.h' line='730' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='index' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='728' column='1'/>
+          <var-decl name='index' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='731' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='perf_event_state' filepath='include/linux/perf_event.h' line='508' column='1' id='31fdb95a'>
@@ -119958,66 +120006,66 @@
         </data-member>
       </class-decl>
       <typedef-decl name='perf_overflow_handler_t' type-id='a8564695' filepath='include/linux/perf_event.h' line='521' column='1' id='20a2e4e6'/>
-      <class-decl name='perf_sample_data' size-in-bits='4096' is-struct='yes' visibility='default' filepath='include/linux/perf_event.h' line='921' column='1' id='2b3d4ba2'>
+      <class-decl name='perf_sample_data' size-in-bits='4096' is-struct='yes' visibility='default' filepath='include/linux/perf_event.h' line='924' column='1' id='2b3d4ba2'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='addr' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='926' column='1'/>
+          <var-decl name='addr' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='929' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='raw' type-id='f4a67529' visibility='default' filepath='include/linux/perf_event.h' line='927' column='1'/>
+          <var-decl name='raw' type-id='f4a67529' visibility='default' filepath='include/linux/perf_event.h' line='930' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='br_stack' type-id='070ae8d2' visibility='default' filepath='include/linux/perf_event.h' line='928' column='1'/>
+          <var-decl name='br_stack' type-id='070ae8d2' visibility='default' filepath='include/linux/perf_event.h' line='931' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='period' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='929' column='1'/>
+          <var-decl name='period' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='932' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='weight' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='930' column='1'/>
+          <var-decl name='weight' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='933' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='txn' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='931' column='1'/>
+          <var-decl name='txn' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='934' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='data_src' type-id='2be3cc53' visibility='default' filepath='include/linux/perf_event.h' line='932' column='1'/>
+          <var-decl name='data_src' type-id='2be3cc53' visibility='default' filepath='include/linux/perf_event.h' line='935' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='type' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='938' column='1'/>
+          <var-decl name='type' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='941' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='ip' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='939' column='1'/>
+          <var-decl name='ip' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='942' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='tid_entry' type-id='0e48f9a5' visibility='default' filepath='include/linux/perf_event.h' line='943' column='1'/>
+          <var-decl name='tid_entry' type-id='0e48f9a5' visibility='default' filepath='include/linux/perf_event.h' line='946' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='time' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='944' column='1'/>
+          <var-decl name='time' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='947' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='id' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='945' column='1'/>
+          <var-decl name='id' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='948' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='stream_id' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='946' column='1'/>
+          <var-decl name='stream_id' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='949' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='cpu_entry' type-id='3851c7bb' visibility='default' filepath='include/linux/perf_event.h' line='950' column='1'/>
+          <var-decl name='cpu_entry' type-id='3851c7bb' visibility='default' filepath='include/linux/perf_event.h' line='953' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='callchain' type-id='cd3a82e3' visibility='default' filepath='include/linux/perf_event.h' line='951' column='1'/>
+          <var-decl name='callchain' type-id='cd3a82e3' visibility='default' filepath='include/linux/perf_event.h' line='954' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='regs_user' type-id='85b37ab4' visibility='default' filepath='include/linux/perf_event.h' line='957' column='1'/>
+          <var-decl name='regs_user' type-id='85b37ab4' visibility='default' filepath='include/linux/perf_event.h' line='960' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='regs_user_copy' type-id='0d029111' visibility='default' filepath='include/linux/perf_event.h' line='958' column='1'/>
+          <var-decl name='regs_user_copy' type-id='0d029111' visibility='default' filepath='include/linux/perf_event.h' line='961' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3648'>
-          <var-decl name='regs_intr' type-id='85b37ab4' visibility='default' filepath='include/linux/perf_event.h' line='960' column='1'/>
+          <var-decl name='regs_intr' type-id='85b37ab4' visibility='default' filepath='include/linux/perf_event.h' line='963' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3776'>
-          <var-decl name='stack_user_size' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='961' column='1'/>
+          <var-decl name='stack_user_size' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='964' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3840'>
-          <var-decl name='phys_addr' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='963' column='1'/>
+          <var-decl name='phys_addr' type-id='91ce1af9' visibility='default' filepath='include/linux/perf_event.h' line='966' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='perf_raw_record' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/perf_event.h' line='87' column='1' id='40ea9ac1'>
@@ -120125,20 +120173,20 @@
           <var-decl name='mem_rsvd' type-id='d3130597' visibility='default' filepath='include/uapi/linux/perf_event.h' line='1009' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='__anonymous_struct__29' size-in-bits='64' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/perf_event.h' line='940' column='1' id='0e48f9a5'>
+      <class-decl name='__anonymous_struct__29' size-in-bits='64' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/perf_event.h' line='943' column='1' id='0e48f9a5'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='pid' type-id='19c2251e' visibility='default' filepath='include/linux/perf_event.h' line='941' column='1'/>
+          <var-decl name='pid' type-id='19c2251e' visibility='default' filepath='include/linux/perf_event.h' line='944' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='tid' type-id='19c2251e' visibility='default' filepath='include/linux/perf_event.h' line='942' column='1'/>
+          <var-decl name='tid' type-id='19c2251e' visibility='default' filepath='include/linux/perf_event.h' line='945' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='__anonymous_struct__30' size-in-bits='64' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/perf_event.h' line='947' column='1' id='3851c7bb'>
+      <class-decl name='__anonymous_struct__30' size-in-bits='64' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/perf_event.h' line='950' column='1' id='3851c7bb'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='cpu' type-id='19c2251e' visibility='default' filepath='include/linux/perf_event.h' line='948' column='1'/>
+          <var-decl name='cpu' type-id='19c2251e' visibility='default' filepath='include/linux/perf_event.h' line='951' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='reserved' type-id='19c2251e' visibility='default' filepath='include/linux/perf_event.h' line='949' column='1'/>
+          <var-decl name='reserved' type-id='19c2251e' visibility='default' filepath='include/linux/perf_event.h' line='952' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='perf_callchain_entry' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/linux/perf_event.h' line='61' column='1' id='16650a93'>
@@ -120261,42 +120309,42 @@
           <var-decl name='android_kabi_reserved4' type-id='91ce1af9' visibility='default' filepath='include/linux/fs.h' line='1965' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='dquot' size-in-bits='1664' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='294' column='1' id='691a06da'>
+      <class-decl name='dquot' size-in-bits='1664' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='296' column='1' id='691a06da'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='dq_hash' type-id='03a4a074' visibility='default' filepath='include/linux/quota.h' line='295' column='1'/>
+          <var-decl name='dq_hash' type-id='03a4a074' visibility='default' filepath='include/linux/quota.h' line='297' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='dq_inuse' type-id='72f469ec' visibility='default' filepath='include/linux/quota.h' line='296' column='1'/>
+          <var-decl name='dq_inuse' type-id='72f469ec' visibility='default' filepath='include/linux/quota.h' line='298' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='dq_free' type-id='72f469ec' visibility='default' filepath='include/linux/quota.h' line='297' column='1'/>
+          <var-decl name='dq_free' type-id='72f469ec' visibility='default' filepath='include/linux/quota.h' line='299' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='dq_dirty' type-id='72f469ec' visibility='default' filepath='include/linux/quota.h' line='298' column='1'/>
+          <var-decl name='dq_dirty' type-id='72f469ec' visibility='default' filepath='include/linux/quota.h' line='300' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='dq_lock' type-id='925167dc' visibility='default' filepath='include/linux/quota.h' line='299' column='1'/>
+          <var-decl name='dq_lock' type-id='925167dc' visibility='default' filepath='include/linux/quota.h' line='301' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='dq_dqb_lock' type-id='fb4018a0' visibility='default' filepath='include/linux/quota.h' line='300' column='1'/>
+          <var-decl name='dq_dqb_lock' type-id='fb4018a0' visibility='default' filepath='include/linux/quota.h' line='302' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='800'>
-          <var-decl name='dq_count' type-id='49178f86' visibility='default' filepath='include/linux/quota.h' line='301' column='1'/>
+          <var-decl name='dq_count' type-id='49178f86' visibility='default' filepath='include/linux/quota.h' line='303' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='dq_sb' type-id='42c8f564' visibility='default' filepath='include/linux/quota.h' line='302' column='1'/>
+          <var-decl name='dq_sb' type-id='42c8f564' visibility='default' filepath='include/linux/quota.h' line='304' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='dq_id' type-id='72028e1c' visibility='default' filepath='include/linux/quota.h' line='303' column='1'/>
+          <var-decl name='dq_id' type-id='72028e1c' visibility='default' filepath='include/linux/quota.h' line='305' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='dq_off' type-id='69bf7bee' visibility='default' filepath='include/linux/quota.h' line='304' column='1'/>
+          <var-decl name='dq_off' type-id='69bf7bee' visibility='default' filepath='include/linux/quota.h' line='306' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='dq_flags' type-id='7359adad' visibility='default' filepath='include/linux/quota.h' line='305' column='1'/>
+          <var-decl name='dq_flags' type-id='7359adad' visibility='default' filepath='include/linux/quota.h' line='307' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='dq_dqb' type-id='bd17a943' visibility='default' filepath='include/linux/quota.h' line='306' column='1'/>
+          <var-decl name='dq_dqb' type-id='bd17a943' visibility='default' filepath='include/linux/quota.h' line='308' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='kqid' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='68' column='1' id='72028e1c'>
@@ -120378,202 +120426,202 @@
           <var-decl name='memcg' type-id='223696fb' visibility='default' filepath='include/linux/shrinker.h' line='33' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='dquot_operations' size-in-bits='832' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='325' column='1' id='0584e65d'>
+      <class-decl name='dquot_operations' size-in-bits='832' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='327' column='1' id='0584e65d'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='write_dquot' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='326' column='1'/>
+          <var-decl name='write_dquot' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='328' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='alloc_dquot' type-id='324070f9' visibility='default' filepath='include/linux/quota.h' line='327' column='1'/>
+          <var-decl name='alloc_dquot' type-id='324070f9' visibility='default' filepath='include/linux/quota.h' line='329' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='destroy_dquot' type-id='dbc22931' visibility='default' filepath='include/linux/quota.h' line='328' column='1'/>
+          <var-decl name='destroy_dquot' type-id='dbc22931' visibility='default' filepath='include/linux/quota.h' line='330' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='acquire_dquot' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='329' column='1'/>
+          <var-decl name='acquire_dquot' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='331' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='release_dquot' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='330' column='1'/>
+          <var-decl name='release_dquot' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='332' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='mark_dirty' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='331' column='1'/>
+          <var-decl name='mark_dirty' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='333' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='write_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='332' column='1'/>
+          <var-decl name='write_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='334' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='get_reserved_space' type-id='15543b10' visibility='default' filepath='include/linux/quota.h' line='335' column='1'/>
+          <var-decl name='get_reserved_space' type-id='15543b10' visibility='default' filepath='include/linux/quota.h' line='337' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='get_projid' type-id='c23b3cbc' visibility='default' filepath='include/linux/quota.h' line='336' column='1'/>
+          <var-decl name='get_projid' type-id='c23b3cbc' visibility='default' filepath='include/linux/quota.h' line='338' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='get_inode_usage' type-id='6b7539fb' visibility='default' filepath='include/linux/quota.h' line='338' column='1'/>
+          <var-decl name='get_inode_usage' type-id='6b7539fb' visibility='default' filepath='include/linux/quota.h' line='340' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='get_next_id' type-id='70b08f83' visibility='default' filepath='include/linux/quota.h' line='340' column='1'/>
+          <var-decl name='get_next_id' type-id='70b08f83' visibility='default' filepath='include/linux/quota.h' line='342' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='342' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='344' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='343' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='345' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='quotactl_ops' size-in-bits='832' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='434' column='1' id='8ce4ff83'>
+      <class-decl name='quotactl_ops' size-in-bits='832' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='436' column='1' id='8ce4ff83'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='quota_on' type-id='de6b64d0' visibility='default' filepath='include/linux/quota.h' line='435' column='1'/>
+          <var-decl name='quota_on' type-id='de6b64d0' visibility='default' filepath='include/linux/quota.h' line='437' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='quota_off' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='436' column='1'/>
+          <var-decl name='quota_off' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='438' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='quota_enable' type-id='7aa5a21e' visibility='default' filepath='include/linux/quota.h' line='437' column='1'/>
+          <var-decl name='quota_enable' type-id='7aa5a21e' visibility='default' filepath='include/linux/quota.h' line='439' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='quota_disable' type-id='7aa5a21e' visibility='default' filepath='include/linux/quota.h' line='438' column='1'/>
+          <var-decl name='quota_disable' type-id='7aa5a21e' visibility='default' filepath='include/linux/quota.h' line='440' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='quota_sync' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='439' column='1'/>
+          <var-decl name='quota_sync' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='441' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='set_info' type-id='4e326e06' visibility='default' filepath='include/linux/quota.h' line='440' column='1'/>
+          <var-decl name='set_info' type-id='4e326e06' visibility='default' filepath='include/linux/quota.h' line='442' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='get_dqblk' type-id='9e27a8d4' visibility='default' filepath='include/linux/quota.h' line='441' column='1'/>
+          <var-decl name='get_dqblk' type-id='9e27a8d4' visibility='default' filepath='include/linux/quota.h' line='443' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='get_nextdqblk' type-id='483e8c3a' visibility='default' filepath='include/linux/quota.h' line='442' column='1'/>
+          <var-decl name='get_nextdqblk' type-id='483e8c3a' visibility='default' filepath='include/linux/quota.h' line='444' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='set_dqblk' type-id='9e27a8d4' visibility='default' filepath='include/linux/quota.h' line='444' column='1'/>
+          <var-decl name='set_dqblk' type-id='9e27a8d4' visibility='default' filepath='include/linux/quota.h' line='446' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='get_state' type-id='eb638046' visibility='default' filepath='include/linux/quota.h' line='445' column='1'/>
+          <var-decl name='get_state' type-id='eb638046' visibility='default' filepath='include/linux/quota.h' line='447' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='rm_xquota' type-id='7aa5a21e' visibility='default' filepath='include/linux/quota.h' line='446' column='1'/>
+          <var-decl name='rm_xquota' type-id='7aa5a21e' visibility='default' filepath='include/linux/quota.h' line='448' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='448' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='450' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='449' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='451' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='qc_info' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='421' column='1' id='9dbdc7de'>
+      <class-decl name='qc_info' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='423' column='1' id='9dbdc7de'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='i_fieldmask' type-id='95e97e5e' visibility='default' filepath='include/linux/quota.h' line='422' column='1'/>
+          <var-decl name='i_fieldmask' type-id='95e97e5e' visibility='default' filepath='include/linux/quota.h' line='424' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='i_flags' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='423' column='1'/>
+          <var-decl name='i_flags' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='425' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='i_spc_timelimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='424' column='1'/>
+          <var-decl name='i_spc_timelimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='426' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='i_ino_timelimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='426' column='1'/>
+          <var-decl name='i_ino_timelimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='428' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='i_rt_spc_timelimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='427' column='1'/>
+          <var-decl name='i_rt_spc_timelimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='429' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='i_spc_warnlimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='428' column='1'/>
+          <var-decl name='i_spc_warnlimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='430' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='i_ino_warnlimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='429' column='1'/>
+          <var-decl name='i_ino_warnlimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='431' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='224'>
-          <var-decl name='i_rt_spc_warnlimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='430' column='1'/>
+          <var-decl name='i_rt_spc_warnlimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='432' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='qc_dqblk' size-in-bits='960' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='349' column='1' id='aef83a98'>
+      <class-decl name='qc_dqblk' size-in-bits='960' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='351' column='1' id='aef83a98'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='d_fieldmask' type-id='95e97e5e' visibility='default' filepath='include/linux/quota.h' line='350' column='1'/>
+          <var-decl name='d_fieldmask' type-id='95e97e5e' visibility='default' filepath='include/linux/quota.h' line='352' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='d_spc_hardlimit' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='351' column='1'/>
+          <var-decl name='d_spc_hardlimit' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='353' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='d_spc_softlimit' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='352' column='1'/>
+          <var-decl name='d_spc_softlimit' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='354' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='d_ino_hardlimit' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='353' column='1'/>
+          <var-decl name='d_ino_hardlimit' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='355' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='d_ino_softlimit' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='354' column='1'/>
+          <var-decl name='d_ino_softlimit' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='356' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='d_space' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='355' column='1'/>
+          <var-decl name='d_space' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='357' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='d_ino_count' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='356' column='1'/>
+          <var-decl name='d_ino_count' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='358' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='d_ino_timer' type-id='9b7c55ef' visibility='default' filepath='include/linux/quota.h' line='357' column='1'/>
+          <var-decl name='d_ino_timer' type-id='9b7c55ef' visibility='default' filepath='include/linux/quota.h' line='359' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='d_spc_timer' type-id='9b7c55ef' visibility='default' filepath='include/linux/quota.h' line='359' column='1'/>
+          <var-decl name='d_spc_timer' type-id='9b7c55ef' visibility='default' filepath='include/linux/quota.h' line='361' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='d_ino_warns' type-id='95e97e5e' visibility='default' filepath='include/linux/quota.h' line='360' column='1'/>
+          <var-decl name='d_ino_warns' type-id='95e97e5e' visibility='default' filepath='include/linux/quota.h' line='362' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='608'>
-          <var-decl name='d_spc_warns' type-id='95e97e5e' visibility='default' filepath='include/linux/quota.h' line='361' column='1'/>
+          <var-decl name='d_spc_warns' type-id='95e97e5e' visibility='default' filepath='include/linux/quota.h' line='363' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='d_rt_spc_hardlimit' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='362' column='1'/>
+          <var-decl name='d_rt_spc_hardlimit' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='364' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='d_rt_spc_softlimit' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='363' column='1'/>
+          <var-decl name='d_rt_spc_softlimit' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='365' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='d_rt_space' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='364' column='1'/>
+          <var-decl name='d_rt_space' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='366' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='d_rt_spc_timer' type-id='9b7c55ef' visibility='default' filepath='include/linux/quota.h' line='365' column='1'/>
+          <var-decl name='d_rt_spc_timer' type-id='9b7c55ef' visibility='default' filepath='include/linux/quota.h' line='367' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='d_rt_spc_warns' type-id='95e97e5e' visibility='default' filepath='include/linux/quota.h' line='366' column='1'/>
+          <var-decl name='d_rt_spc_warns' type-id='95e97e5e' visibility='default' filepath='include/linux/quota.h' line='368' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='qc_state' size-in-bits='1408' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='415' column='1' id='f6be3c23'>
+      <class-decl name='qc_state' size-in-bits='1408' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='417' column='1' id='f6be3c23'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='s_incoredqs' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='416' column='1'/>
+          <var-decl name='s_incoredqs' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='418' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='s_state' type-id='55d1e02d' visibility='default' filepath='include/linux/quota.h' line='417' column='1'/>
+          <var-decl name='s_state' type-id='55d1e02d' visibility='default' filepath='include/linux/quota.h' line='419' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='qc_type_state' size-in-bits='448' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='401' column='1' id='e878d564'>
+      <class-decl name='qc_type_state' size-in-bits='448' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='403' column='1' id='e878d564'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='flags' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='402' column='1'/>
+          <var-decl name='flags' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='404' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='spc_timelimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='403' column='1'/>
+          <var-decl name='spc_timelimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='405' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='ino_timelimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='405' column='1'/>
+          <var-decl name='ino_timelimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='407' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='rt_spc_timelimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='406' column='1'/>
+          <var-decl name='rt_spc_timelimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='408' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='spc_warnlimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='407' column='1'/>
+          <var-decl name='spc_warnlimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='409' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='ino_warnlimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='408' column='1'/>
+          <var-decl name='ino_warnlimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='410' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='rt_spc_warnlimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='409' column='1'/>
+          <var-decl name='rt_spc_warnlimit' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='411' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ino' type-id='3a47d82b' visibility='default' filepath='include/linux/quota.h' line='410' column='1'/>
+          <var-decl name='ino' type-id='3a47d82b' visibility='default' filepath='include/linux/quota.h' line='412' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='blocks' type-id='17345459' visibility='default' filepath='include/linux/quota.h' line='411' column='1'/>
+          <var-decl name='blocks' type-id='17345459' visibility='default' filepath='include/linux/quota.h' line='413' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='nextents' type-id='17345459' visibility='default' filepath='include/linux/quota.h' line='412' column='1'/>
+          <var-decl name='nextents' type-id='17345459' visibility='default' filepath='include/linux/quota.h' line='414' column='1'/>
         </data-member>
       </class-decl>
       <typedef-decl name='blkcnt_t' type-id='7359adad' filepath='include/linux/types.h' line='135' column='1' id='17345459'/>
@@ -120582,21 +120630,21 @@
           <var-decl name='first' type-id='d09d4bab' visibility='default' filepath='include/linux/list_bl.h' line='35' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='quota_info' size-in-bits='2560' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='527' column='1' id='c26e4ad8'>
+      <class-decl name='quota_info' size-in-bits='2560' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='529' column='1' id='c26e4ad8'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='flags' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='528' column='1'/>
+          <var-decl name='flags' type-id='f0981eeb' visibility='default' filepath='include/linux/quota.h' line='530' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='dqio_sem' type-id='f19fdb93' visibility='default' filepath='include/linux/quota.h' line='529' column='1'/>
+          <var-decl name='dqio_sem' type-id='f19fdb93' visibility='default' filepath='include/linux/quota.h' line='531' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='files' type-id='e6ff92fb' visibility='default' filepath='include/linux/quota.h' line='530' column='1'/>
+          <var-decl name='files' type-id='e6ff92fb' visibility='default' filepath='include/linux/quota.h' line='532' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='info' type-id='83ae09a1' visibility='default' filepath='include/linux/quota.h' line='531' column='1'/>
+          <var-decl name='info' type-id='83ae09a1' visibility='default' filepath='include/linux/quota.h' line='533' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2368'>
-          <var-decl name='ops' type-id='59bd9302' visibility='default' filepath='include/linux/quota.h' line='532' column='1'/>
+          <var-decl name='ops' type-id='59bd9302' visibility='default' filepath='include/linux/quota.h' line='534' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='mem_dqinfo' size-in-bits='576' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='222' column='1' id='b0690d78'>
@@ -120628,50 +120676,50 @@
           <var-decl name='dqi_priv' type-id='eaa32e2f' visibility='default' filepath='include/linux/quota.h' line='232' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='quota_format_type' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='452' column='1' id='c2be49b0'>
+      <class-decl name='quota_format_type' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='454' column='1' id='c2be49b0'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='qf_fmt_id' type-id='95e97e5e' visibility='default' filepath='include/linux/quota.h' line='453' column='1'/>
+          <var-decl name='qf_fmt_id' type-id='95e97e5e' visibility='default' filepath='include/linux/quota.h' line='455' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='qf_ops' type-id='bd561d05' visibility='default' filepath='include/linux/quota.h' line='454' column='1'/>
+          <var-decl name='qf_ops' type-id='bd561d05' visibility='default' filepath='include/linux/quota.h' line='456' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='qf_owner' type-id='2730d015' visibility='default' filepath='include/linux/quota.h' line='455' column='1'/>
+          <var-decl name='qf_owner' type-id='2730d015' visibility='default' filepath='include/linux/quota.h' line='457' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='qf_next' type-id='eb9a3ab6' visibility='default' filepath='include/linux/quota.h' line='456' column='1'/>
+          <var-decl name='qf_next' type-id='eb9a3ab6' visibility='default' filepath='include/linux/quota.h' line='458' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='quota_format_ops' size-in-bits='640' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='310' column='1' id='87cad984'>
+      <class-decl name='quota_format_ops' size-in-bits='640' is-struct='yes' visibility='default' filepath='include/linux/quota.h' line='312' column='1' id='87cad984'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='check_quota_file' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='311' column='1'/>
+          <var-decl name='check_quota_file' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='313' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='read_file_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='312' column='1'/>
+          <var-decl name='read_file_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='314' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='write_file_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='313' column='1'/>
+          <var-decl name='write_file_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='315' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='free_file_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='314' column='1'/>
+          <var-decl name='free_file_info' type-id='dcab5203' visibility='default' filepath='include/linux/quota.h' line='316' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='read_dqblk' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='315' column='1'/>
+          <var-decl name='read_dqblk' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='317' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='commit_dqblk' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='316' column='1'/>
+          <var-decl name='commit_dqblk' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='318' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='release_dqblk' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='317' column='1'/>
+          <var-decl name='release_dqblk' type-id='24c1e1dc' visibility='default' filepath='include/linux/quota.h' line='319' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='get_next_id' type-id='70b08f83' visibility='default' filepath='include/linux/quota.h' line='318' column='1'/>
+          <var-decl name='get_next_id' type-id='70b08f83' visibility='default' filepath='include/linux/quota.h' line='320' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='320' column='1'/>
+          <var-decl name='android_kabi_reserved1' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='322' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='321' column='1'/>
+          <var-decl name='android_kabi_reserved2' type-id='91ce1af9' visibility='default' filepath='include/linux/quota.h' line='323' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='sb_writers' size-in-bits='3520' is-struct='yes' visibility='default' filepath='include/linux/fs.h' line='1407' column='1' id='fb476a2b'>
@@ -123534,7 +123582,7 @@
       <qualified-type-def type-id='69f06cc6' const='yes' id='99fda9f5'/>
       <pointer-type-def type-id='99fda9f5' size-in-bits='64' id='49526a0d'/>
       <var-decl name='irq_stat' type-id='715fcff2' mangled-name='irq_stat' visibility='default' filepath='kernel/softirq.c' line='52' column='1' elf-symbol-id='irq_stat'/>
-      <function-decl name='bpf_trace_run3' mangled-name='bpf_trace_run3' filepath='include/linux/trace_events.h' line='594' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='bpf_trace_run3'>
+      <function-decl name='bpf_trace_run3' mangled-name='bpf_trace_run3' filepath='include/linux/trace_events.h' line='595' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='bpf_trace_run3'>
         <parameter type-id='bdcee7ae'/>
         <parameter type-id='3a47d82b'/>
         <parameter type-id='3a47d82b'/>
@@ -124349,18 +124397,18 @@
           <var-decl name='entry' type-id='27675065' visibility='default' filepath='kernel/trace/trace.h' line='392' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='event_subsystem' size-in-bits='320' is-struct='yes' visibility='default' filepath='kernel/trace/trace.h' line='1292' column='1' id='ba400603'>
+      <class-decl name='event_subsystem' size-in-bits='320' is-struct='yes' visibility='default' filepath='kernel/trace/trace.h' line='1294' column='1' id='ba400603'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='kernel/trace/trace.h' line='1293' column='1'/>
+          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='kernel/trace/trace.h' line='1295' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='name' type-id='80f4b756' visibility='default' filepath='kernel/trace/trace.h' line='1294' column='1'/>
+          <var-decl name='name' type-id='80f4b756' visibility='default' filepath='kernel/trace/trace.h' line='1296' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='filter' type-id='26461068' visibility='default' filepath='kernel/trace/trace.h' line='1295' column='1'/>
+          <var-decl name='filter' type-id='26461068' visibility='default' filepath='kernel/trace/trace.h' line='1297' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ref_count' type-id='95e97e5e' visibility='default' filepath='kernel/trace/trace.h' line='1296' column='1'/>
+          <var-decl name='ref_count' type-id='95e97e5e' visibility='default' filepath='kernel/trace/trace.h' line='1298' column='1'/>
         </data-member>
       </class-decl>
       <pointer-type-def type-id='94dd3300' size-in-bits='64' id='cfbdf512'/>
@@ -124663,23 +124711,23 @@
           <var-decl name='rcu' type-id='e3d8ce29' visibility='default' filepath='kernel/workqueue.c' line='190' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='workqueue_attrs' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='143' column='1' id='2fe6f208'>
+      <class-decl name='workqueue_attrs' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/workqueue.h' line='144' column='1' id='2fe6f208'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='nice' type-id='95e97e5e' visibility='default' filepath='include/linux/workqueue.h' line='147' column='1'/>
+          <var-decl name='nice' type-id='95e97e5e' visibility='default' filepath='include/linux/workqueue.h' line='148' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='cpumask' type-id='b16b461b' visibility='default' filepath='include/linux/workqueue.h' line='152' column='1'/>
+          <var-decl name='cpumask' type-id='b16b461b' visibility='default' filepath='include/linux/workqueue.h' line='153' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='no_numa' type-id='b50a4934' visibility='default' filepath='include/linux/workqueue.h' line='161' column='1'/>
+          <var-decl name='no_numa' type-id='b50a4934' visibility='default' filepath='include/linux/workqueue.h' line='162' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wq_device' size-in-bits='7680' is-struct='yes' visibility='default' filepath='kernel/workqueue.c' line='5203' column='1' id='a88ecfc8'>
+      <class-decl name='wq_device' size-in-bits='7680' is-struct='yes' visibility='default' filepath='kernel/workqueue.c' line='5210' column='1' id='a88ecfc8'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='wq' type-id='242e3d19' visibility='default' filepath='kernel/workqueue.c' line='5204' column='1'/>
+          <var-decl name='wq' type-id='242e3d19' visibility='default' filepath='kernel/workqueue.c' line='5211' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='kernel/workqueue.c' line='5205' column='1'/>
+          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='kernel/workqueue.c' line='5212' column='1'/>
         </data-member>
       </class-decl>
       <pointer-type-def type-id='b0355154' size-in-bits='64' id='a7a31b92'/>
@@ -124688,12 +124736,12 @@
       <pointer-type-def type-id='2fe6f208' size-in-bits='64' id='cfd15e7e'/>
       <pointer-type-def type-id='a88ecfc8' size-in-bits='64' id='5cebc26e'/>
       <pointer-type-def type-id='c8eb0f4f' size-in-bits='64' id='ec037527'/>
-      <function-decl name='__alloc_workqueue_key' mangled-name='__alloc_workqueue_key' filepath='kernel/workqueue.c' line='4092' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__alloc_workqueue_key'>
-        <parameter type-id='80f4b756' name='fmt' filepath='kernel/workqueue.c' line='4092' column='1'/>
-        <parameter type-id='f0981eeb' name='flags' filepath='kernel/workqueue.c' line='4093' column='1'/>
-        <parameter type-id='95e97e5e' name='max_active' filepath='kernel/workqueue.c' line='4094' column='1'/>
-        <parameter type-id='a57283f9' name='key' filepath='kernel/workqueue.c' line='4095' column='1'/>
-        <parameter type-id='80f4b756' name='lock_name' filepath='kernel/workqueue.c' line='4096' column='1'/>
+      <function-decl name='__alloc_workqueue_key' mangled-name='__alloc_workqueue_key' filepath='kernel/workqueue.c' line='4095' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__alloc_workqueue_key'>
+        <parameter type-id='80f4b756' name='fmt' filepath='kernel/workqueue.c' line='4095' column='1'/>
+        <parameter type-id='f0981eeb' name='flags' filepath='kernel/workqueue.c' line='4096' column='1'/>
+        <parameter type-id='95e97e5e' name='max_active' filepath='kernel/workqueue.c' line='4097' column='1'/>
+        <parameter type-id='a57283f9' name='key' filepath='kernel/workqueue.c' line='4098' column='1'/>
+        <parameter type-id='80f4b756' name='lock_name' filepath='kernel/workqueue.c' line='4099' column='1'/>
         <parameter is-variadic='yes'/>
         <return type-id='242e3d19'/>
       </function-decl>
@@ -124702,16 +124750,16 @@
       <var-decl name='system_long_wq' type-id='242e3d19' mangled-name='system_long_wq' visibility='default' filepath='kernel/workqueue.c' line='343' column='1' elf-symbol-id='system_long_wq'/>
       <var-decl name='system_unbound_wq' type-id='242e3d19' mangled-name='system_unbound_wq' visibility='default' filepath='kernel/workqueue.c' line='345' column='1' elf-symbol-id='system_unbound_wq'/>
       <var-decl name='system_freezable_wq' type-id='242e3d19' mangled-name='system_freezable_wq' visibility='default' filepath='kernel/workqueue.c' line='347' column='1' elf-symbol-id='system_freezable_wq'/>
-      <function-decl name='delayed_work_timer_fn' mangled-name='delayed_work_timer_fn' filepath='kernel/workqueue.c' line='1518' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='delayed_work_timer_fn'>
-        <parameter type-id='9248e67f' name='t' filepath='kernel/workqueue.c' line='1518' column='1'/>
+      <function-decl name='delayed_work_timer_fn' mangled-name='delayed_work_timer_fn' filepath='kernel/workqueue.c' line='1521' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='delayed_work_timer_fn'>
+        <parameter type-id='9248e67f' name='t' filepath='kernel/workqueue.c' line='1521' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='flush_workqueue' mangled-name='flush_workqueue' filepath='kernel/workqueue.c' line='2674' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='flush_workqueue'>
-        <parameter type-id='242e3d19' name='wq' filepath='kernel/workqueue.c' line='2674' column='1'/>
+      <function-decl name='flush_workqueue' mangled-name='flush_workqueue' filepath='kernel/workqueue.c' line='2677' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='flush_workqueue'>
+        <parameter type-id='242e3d19' name='wq' filepath='kernel/workqueue.c' line='2677' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='drain_workqueue' mangled-name='drain_workqueue' filepath='kernel/workqueue.c' line='2836' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='drain_workqueue'>
-        <parameter type-id='242e3d19' name='wq' filepath='kernel/workqueue.c' line='2836' column='1'/>
+      <function-decl name='drain_workqueue' mangled-name='drain_workqueue' filepath='kernel/workqueue.c' line='2839' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='drain_workqueue'>
+        <parameter type-id='242e3d19' name='wq' filepath='kernel/workqueue.c' line='2839' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
       <function-decl name='prepare_to_wait_exclusive' mangled-name='prepare_to_wait_exclusive' filepath='include/linux/wait.h' line='1138' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='prepare_to_wait_exclusive'>
@@ -124720,12 +124768,12 @@
         <parameter type-id='95e97e5e'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='flush_delayed_work' mangled-name='flush_delayed_work' filepath='kernel/workqueue.c' line='3088' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='flush_delayed_work'>
-        <parameter type-id='1a7ee447' name='dwork' filepath='kernel/workqueue.c' line='3088' column='1'/>
+      <function-decl name='flush_delayed_work' mangled-name='flush_delayed_work' filepath='kernel/workqueue.c' line='3091' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='flush_delayed_work'>
+        <parameter type-id='1a7ee447' name='dwork' filepath='kernel/workqueue.c' line='3091' column='1'/>
         <return type-id='b50a4934'/>
       </function-decl>
-      <function-decl name='cancel_delayed_work' mangled-name='cancel_delayed_work' filepath='kernel/workqueue.c' line='3151' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='cancel_delayed_work'>
-        <parameter type-id='1a7ee447' name='dwork' filepath='kernel/workqueue.c' line='3151' column='1'/>
+      <function-decl name='cancel_delayed_work' mangled-name='cancel_delayed_work' filepath='kernel/workqueue.c' line='3154' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='cancel_delayed_work'>
+        <parameter type-id='1a7ee447' name='dwork' filepath='kernel/workqueue.c' line='3154' column='1'/>
         <return type-id='b50a4934'/>
       </function-decl>
       <function-decl name='device_unregister' mangled-name='device_unregister' filepath='include/linux/device.h' line='1301' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='device_unregister'>
@@ -124842,12 +124890,12 @@
         <parameter type-id='eaa32e2f' name='addr' filepath='lib/devres.c' line='128' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='pci_release_region' mangled-name='pci_release_region' filepath='include/linux/pci.h' line='1239' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_release_region'>
+      <function-decl name='pci_release_region' mangled-name='pci_release_region' filepath='include/linux/pci.h' line='1240' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_release_region'>
         <parameter type-id='85196e3f'/>
         <parameter type-id='95e97e5e'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='pci_release_selected_regions' mangled-name='pci_release_selected_regions' filepath='include/linux/pci.h' line='1242' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_release_selected_regions'>
+      <function-decl name='pci_release_selected_regions' mangled-name='pci_release_selected_regions' filepath='include/linux/pci.h' line='1243' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='pci_release_selected_regions'>
         <parameter type-id='85196e3f'/>
         <parameter type-id='95e97e5e'/>
         <return type-id='48b5725f'/>
@@ -127173,7 +127221,7 @@
       </function-type>
     </abi-instr>
     <abi-instr address-size='64' path='net/bridge/br.c' language='LANG_C89'>
-      <function-decl name='call_netdevice_notifiers' mangled-name='call_netdevice_notifiers' filepath='include/linux/netdevice.h' line='2575' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='call_netdevice_notifiers'>
+      <function-decl name='call_netdevice_notifiers' mangled-name='call_netdevice_notifiers' filepath='include/linux/netdevice.h' line='2574' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='call_netdevice_notifiers'>
         <parameter type-id='7359adad'/>
         <parameter type-id='68a2d05b'/>
         <return type-id='95e97e5e'/>
@@ -127193,6 +127241,217 @@
       </function-decl>
     </abi-instr>
     <abi-instr address-size='64' path='net/core/dev.c' language='LANG_C89'>
+      <array-type-def dimensions='1' type-id='bb08c7e1' size-in-bits='infinite' id='f443352a'>
+        <subrange length='infinite' type-id='7ff19f0f' id='031f2035'/>
+      </array-type-def>
+      <class-decl name='libipw_device' is-struct='yes' visibility='default' is-declaration-only='yes' id='9c91a761'/>
+      <array-type-def dimensions='1' type-id='aa80c027' size-in-bits='256' id='c73a16a3'>
+        <subrange length='8' type-id='7ff19f0f' id='56e0c0b1'/>
+      </array-type-def>
+      <array-type-def dimensions='1' type-id='b151a3a8' size-in-bits='64' id='4a744ea1'>
+        <subrange length='8' type-id='7ff19f0f' id='56e0c0b1'/>
+      </array-type-def>
+      <array-type-def dimensions='2' type-id='b151a3a8' size-in-bits='384' id='2d507faf'>
+        <subrange length='8' type-id='7ff19f0f' id='56e0c0b1'/>
+        <subrange length='6' type-id='7ff19f0f' id='52fa524b'/>
+      </array-type-def>
+      <typedef-decl name='iw_handler' type-id='2c8ff697' filepath='include/net/iw_handler.h' line='315' column='1' id='bcc5cab3'/>
+      <class-decl name='iw_request_info' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/net/iw_handler.h' line='304' column='1' id='e90b3b44'>
+        <data-member access='public' layout-offset-in-bits='0'>
+          <var-decl name='cmd' type-id='d315442e' visibility='default' filepath='include/net/iw_handler.h' line='305' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='16'>
+          <var-decl name='flags' type-id='d315442e' visibility='default' filepath='include/net/iw_handler.h' line='306' column='1'/>
+        </data-member>
+      </class-decl>
+      <class-decl name='iw_point' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='691' column='1' id='db4e746c'>
+        <data-member access='public' layout-offset-in-bits='0'>
+          <var-decl name='pointer' type-id='eaa32e2f' visibility='default' filepath='include/uapi/linux/wireless.h' line='692' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='64'>
+          <var-decl name='length' type-id='d315442e' visibility='default' filepath='include/uapi/linux/wireless.h' line='693' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='80'>
+          <var-decl name='flags' type-id='d315442e' visibility='default' filepath='include/uapi/linux/wireless.h' line='694' column='1'/>
+        </data-member>
+      </class-decl>
+      <class-decl name='iw_param' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='680' column='1' id='b024252b'>
+        <data-member access='public' layout-offset-in-bits='0'>
+          <var-decl name='value' type-id='3158a266' visibility='default' filepath='include/uapi/linux/wireless.h' line='681' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='32'>
+          <var-decl name='fixed' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='682' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='40'>
+          <var-decl name='disabled' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='683' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='48'>
+          <var-decl name='flags' type-id='d315442e' visibility='default' filepath='include/uapi/linux/wireless.h' line='684' column='1'/>
+        </data-member>
+      </class-decl>
+      <class-decl name='iw_freq' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='706' column='1' id='bc1ac22c'>
+        <data-member access='public' layout-offset-in-bits='0'>
+          <var-decl name='m' type-id='3158a266' visibility='default' filepath='include/uapi/linux/wireless.h' line='707' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='32'>
+          <var-decl name='e' type-id='b55def60' visibility='default' filepath='include/uapi/linux/wireless.h' line='708' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='48'>
+          <var-decl name='i' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='709' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='56'>
+          <var-decl name='flags' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='710' column='1'/>
+        </data-member>
+      </class-decl>
+      <class-decl name='iw_quality' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='716' column='1' id='aa80c027'>
+        <data-member access='public' layout-offset-in-bits='0'>
+          <var-decl name='qual' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='717' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='8'>
+          <var-decl name='level' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='719' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='16'>
+          <var-decl name='noise' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='720' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='24'>
+          <var-decl name='updated' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='721' column='1'/>
+        </data-member>
+      </class-decl>
+      <class-decl name='iw_priv_args' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='1063' column='1' id='0c842ad9'>
+        <data-member access='public' layout-offset-in-bits='0'>
+          <var-decl name='cmd' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='1064' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='32'>
+          <var-decl name='set_args' type-id='d315442e' visibility='default' filepath='include/uapi/linux/wireless.h' line='1065' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='48'>
+          <var-decl name='get_args' type-id='d315442e' visibility='default' filepath='include/uapi/linux/wireless.h' line='1066' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='64'>
+          <var-decl name='name' type-id='ac1fa8c0' visibility='default' filepath='include/uapi/linux/wireless.h' line='1067' column='1'/>
+        </data-member>
+      </class-decl>
+      <class-decl name='iw_statistics' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='881' column='1' id='1c8cc2fd'>
+        <data-member access='public' layout-offset-in-bits='0'>
+          <var-decl name='status' type-id='d315442e' visibility='default' filepath='include/uapi/linux/wireless.h' line='882' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='16'>
+          <var-decl name='qual' type-id='aa80c027' visibility='default' filepath='include/uapi/linux/wireless.h' line='885' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='64'>
+          <var-decl name='discard' type-id='832938ed' visibility='default' filepath='include/uapi/linux/wireless.h' line='887' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='224'>
+          <var-decl name='miss' type-id='6a2a3473' visibility='default' filepath='include/uapi/linux/wireless.h' line='888' column='1'/>
+        </data-member>
+      </class-decl>
+      <class-decl name='iw_discarded' size-in-bits='160' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='731' column='1' id='832938ed'>
+        <data-member access='public' layout-offset-in-bits='0'>
+          <var-decl name='nwid' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='732' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='32'>
+          <var-decl name='code' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='733' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='64'>
+          <var-decl name='fragment' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='734' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='96'>
+          <var-decl name='retries' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='735' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='128'>
+          <var-decl name='misc' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='736' column='1'/>
+        </data-member>
+      </class-decl>
+      <class-decl name='iw_missed' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='743' column='1' id='6a2a3473'>
+        <data-member access='public' layout-offset-in-bits='0'>
+          <var-decl name='beacon' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='744' column='1'/>
+        </data-member>
+      </class-decl>
+      <class-decl name='iw_spy_data' size-in-bits='800' is-struct='yes' visibility='default' filepath='include/net/iw_handler.h' line='396' column='1' id='f8292115'>
+        <data-member access='public' layout-offset-in-bits='0'>
+          <var-decl name='spy_number' type-id='95e97e5e' visibility='default' filepath='include/net/iw_handler.h' line='398' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='32'>
+          <var-decl name='spy_address' type-id='2d507faf' visibility='default' filepath='include/net/iw_handler.h' line='399' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='416'>
+          <var-decl name='spy_stat' type-id='c73a16a3' visibility='default' filepath='include/net/iw_handler.h' line='400' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='672'>
+          <var-decl name='spy_thr_low' type-id='aa80c027' visibility='default' filepath='include/net/iw_handler.h' line='402' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='704'>
+          <var-decl name='spy_thr_high' type-id='aa80c027' visibility='default' filepath='include/net/iw_handler.h' line='403' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='736'>
+          <var-decl name='spy_thr_under' type-id='4a744ea1' visibility='default' filepath='include/net/iw_handler.h' line='404' column='1'/>
+        </data-member>
+      </class-decl>
+      <typedef-decl name='u_char' type-id='002ac4a6' filepath='include/linux/types.h' line='84' column='1' id='b151a3a8'/>
+      <union-decl name='iwreq_data' size-in-bits='128' visibility='default' filepath='include/uapi/linux/wireless.h' line='902' column='1' id='ed626d0d'>
+        <data-member access='public'>
+          <var-decl name='name' type-id='ac1fa8c0' visibility='default' filepath='include/uapi/linux/wireless.h' line='904' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='essid' type-id='db4e746c' visibility='default' filepath='include/uapi/linux/wireless.h' line='908' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='nwid' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='909' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='freq' type-id='bc1ac22c' visibility='default' filepath='include/uapi/linux/wireless.h' line='910' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='sens' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='914' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='bitrate' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='915' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='txpower' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='916' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='rts' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='917' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='frag' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='918' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='mode' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='919' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='retry' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='920' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='encoding' type-id='db4e746c' visibility='default' filepath='include/uapi/linux/wireless.h' line='922' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='power' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='923' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='qual' type-id='aa80c027' visibility='default' filepath='include/uapi/linux/wireless.h' line='924' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='ap_addr' type-id='5221b18a' visibility='default' filepath='include/uapi/linux/wireless.h' line='926' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='addr' type-id='5221b18a' visibility='default' filepath='include/uapi/linux/wireless.h' line='927' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='param' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='929' column='1'/>
+        </data-member>
+        <data-member access='public'>
+          <var-decl name='data' type-id='db4e746c' visibility='default' filepath='include/uapi/linux/wireless.h' line='930' column='1'/>
+        </data-member>
+      </union-decl>
+      <class-decl name='__anonymous_struct__2' size-in-bits='32' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/linux/cpu_rmap.h' line='31' column='1' id='bb08c7e1'>
+        <data-member access='public' layout-offset-in-bits='0'>
+          <var-decl name='index' type-id='1dc6a898' visibility='default' filepath='include/linux/cpu_rmap.h' line='32' column='1'/>
+        </data-member>
+        <data-member access='public' layout-offset-in-bits='16'>
+          <var-decl name='dist' type-id='1dc6a898' visibility='default' filepath='include/linux/cpu_rmap.h' line='33' column='1'/>
+        </data-member>
+      </class-decl>
       <class-decl name='rps_sock_flow_table' size-in-bits='512' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='689' column='1' id='512813dd'>
         <data-member access='public' layout-offset-in-bits='0'>
           <var-decl name='mask' type-id='19c2251e' visibility='default' filepath='include/linux/netdevice.h' line='690' column='1'/>
@@ -127201,24 +127460,35 @@
           <var-decl name='ents' type-id='c165e8b9' visibility='default' filepath='include/linux/netdevice.h' line='692' column='1'/>
         </data-member>
       </class-decl>
-      <enum-decl name='skb_free_reason' filepath='include/linux/netdevice.h' line='3572' column='1' id='1f17c6b4'>
+      <enum-decl name='skb_free_reason' filepath='include/linux/netdevice.h' line='3571' column='1' id='1f17c6b4'>
         <underlying-type type-id='9cac1fee'/>
         <enumerator name='SKB_REASON_CONSUMED' value='0'/>
         <enumerator name='SKB_REASON_DROPPED' value='1'/>
       </enum-decl>
+      <qualified-type-def type-id='bcc5cab3' const='yes' id='208298e3'/>
+      <pointer-type-def type-id='208298e3' size-in-bits='64' id='f696846b'/>
+      <qualified-type-def type-id='0c842ad9' const='yes' id='afa36b70'/>
+      <pointer-type-def type-id='afa36b70' size-in-bits='64' id='d841feae'/>
+      <pointer-type-def type-id='97488913' size-in-bits='64' id='2c8ff697'/>
+      <pointer-type-def type-id='e90b3b44' size-in-bits='64' id='4780e252'/>
+      <pointer-type-def type-id='f8292115' size-in-bits='64' id='96efb615'/>
+      <pointer-type-def type-id='1c8cc2fd' size-in-bits='64' id='003642fd'/>
+      <pointer-type-def type-id='cfdbff8a' size-in-bits='64' id='55e2a83c'/>
+      <pointer-type-def type-id='ed626d0d' size-in-bits='64' id='00e2a7ce'/>
+      <pointer-type-def type-id='9c91a761' size-in-bits='64' id='29244949'/>
       <pointer-type-def type-id='512813dd' size-in-bits='64' id='2293f1dd'/>
-      <function-decl name='netdev_rx_handler_unregister' mangled-name='netdev_rx_handler_unregister' filepath='net/core/dev.c' line='4735' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_rx_handler_unregister'>
-        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='4735' column='1'/>
+      <function-decl name='netdev_rx_handler_unregister' mangled-name='netdev_rx_handler_unregister' filepath='net/core/dev.c' line='4737' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_rx_handler_unregister'>
+        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='4737' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='netdev_upper_dev_unlink' mangled-name='netdev_upper_dev_unlink' filepath='net/core/dev.c' line='7283' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_upper_dev_unlink'>
-        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='7283' column='1'/>
-        <parameter type-id='68a2d05b' name='upper_dev' filepath='net/core/dev.c' line='7284' column='1'/>
+      <function-decl name='netdev_upper_dev_unlink' mangled-name='netdev_upper_dev_unlink' filepath='net/core/dev.c' line='7285' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_upper_dev_unlink'>
+        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='7285' column='1'/>
+        <parameter type-id='68a2d05b' name='upper_dev' filepath='net/core/dev.c' line='7286' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='netdev_lower_state_changed' mangled-name='netdev_lower_state_changed' filepath='net/core/dev.c' line='7454' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_lower_state_changed'>
-        <parameter type-id='68a2d05b' name='lower_dev' filepath='net/core/dev.c' line='7454' column='1'/>
-        <parameter type-id='eaa32e2f' name='lower_state_info' filepath='net/core/dev.c' line='7455' column='1'/>
+      <function-decl name='netdev_lower_state_changed' mangled-name='netdev_lower_state_changed' filepath='net/core/dev.c' line='7456' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_lower_state_changed'>
+        <parameter type-id='68a2d05b' name='lower_dev' filepath='net/core/dev.c' line='7456' column='1'/>
+        <parameter type-id='eaa32e2f' name='lower_state_info' filepath='net/core/dev.c' line='7457' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
       <var-decl name='rps_sock_flow_table' type-id='2293f1dd' mangled-name='rps_sock_flow_table' visibility='default' filepath='net/core/dev.c' line='3963' column='1' elf-symbol-id='rps_sock_flow_table'/>
@@ -127269,62 +127539,62 @@
         <parameter type-id='f9f4b16f' name='features' filepath='net/core/dev.c' line='3179' column='1'/>
         <return type-id='f9f4b16f'/>
       </function-decl>
-      <function-decl name='netif_rx_ni' mangled-name='netif_rx_ni' filepath='net/core/dev.c' line='4533' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_rx_ni'>
-        <parameter type-id='0fbf3cfd' name='skb' filepath='net/core/dev.c' line='4533' column='1'/>
+      <function-decl name='netif_rx_ni' mangled-name='netif_rx_ni' filepath='net/core/dev.c' line='4535' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_rx_ni'>
+        <parameter type-id='0fbf3cfd' name='skb' filepath='net/core/dev.c' line='4535' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
       <function-decl name='dev_queue_xmit' mangled-name='dev_queue_xmit' filepath='net/core/dev.c' line='3882' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='dev_queue_xmit'>
         <parameter type-id='0fbf3cfd' name='skb' filepath='net/core/dev.c' line='3882' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='netdev_rx_handler_register' mangled-name='netdev_rx_handler_register' filepath='net/core/dev.c' line='4709' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_rx_handler_register'>
-        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='4709' column='1'/>
-        <parameter type-id='da1cb816' name='rx_handler' filepath='net/core/dev.c' line='4710' column='1'/>
-        <parameter type-id='eaa32e2f' name='rx_handler_data' filepath='net/core/dev.c' line='4711' column='1'/>
+      <function-decl name='netdev_rx_handler_register' mangled-name='netdev_rx_handler_register' filepath='net/core/dev.c' line='4711' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_rx_handler_register'>
+        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='4711' column='1'/>
+        <parameter type-id='da1cb816' name='rx_handler' filepath='net/core/dev.c' line='4712' column='1'/>
+        <parameter type-id='eaa32e2f' name='rx_handler_data' filepath='net/core/dev.c' line='4713' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='napi_gro_flush' mangled-name='napi_gro_flush' filepath='net/core/dev.c' line='5358' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='napi_gro_flush'>
-        <parameter type-id='c50361c5' name='napi' filepath='net/core/dev.c' line='5358' column='1'/>
-        <parameter type-id='b50a4934' name='flush_old' filepath='net/core/dev.c' line='5358' column='1'/>
+      <function-decl name='napi_gro_flush' mangled-name='napi_gro_flush' filepath='net/core/dev.c' line='5360' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='napi_gro_flush'>
+        <parameter type-id='c50361c5' name='napi' filepath='net/core/dev.c' line='5360' column='1'/>
+        <parameter type-id='b50a4934' name='flush_old' filepath='net/core/dev.c' line='5360' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='__napi_schedule' mangled-name='__napi_schedule' filepath='net/core/dev.c' line='5904' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__napi_schedule'>
-        <parameter type-id='c50361c5' name='n' filepath='net/core/dev.c' line='5904' column='1'/>
+      <function-decl name='__napi_schedule' mangled-name='__napi_schedule' filepath='net/core/dev.c' line='5906' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__napi_schedule'>
+        <parameter type-id='c50361c5' name='n' filepath='net/core/dev.c' line='5906' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='get_current_napi_context' mangled-name='get_current_napi_context' filepath='net/core/dev.c' line='6280' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='get_current_napi_context'>
+      <function-decl name='get_current_napi_context' mangled-name='get_current_napi_context' filepath='net/core/dev.c' line='6282' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='get_current_napi_context'>
         <return type-id='c50361c5'/>
       </function-decl>
-      <function-decl name='netdev_upper_dev_link' mangled-name='netdev_upper_dev_link' filepath='net/core/dev.c' line='7242' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_upper_dev_link'>
-        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='7242' column='1'/>
-        <parameter type-id='68a2d05b' name='upper_dev' filepath='net/core/dev.c' line='7243' column='1'/>
-        <parameter type-id='5799dc94' name='extack' filepath='net/core/dev.c' line='7244' column='1'/>
+      <function-decl name='netdev_upper_dev_link' mangled-name='netdev_upper_dev_link' filepath='net/core/dev.c' line='7244' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_upper_dev_link'>
+        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='7244' column='1'/>
+        <parameter type-id='68a2d05b' name='upper_dev' filepath='net/core/dev.c' line='7245' column='1'/>
+        <parameter type-id='5799dc94' name='extack' filepath='net/core/dev.c' line='7246' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='netdev_master_upper_dev_link' mangled-name='netdev_master_upper_dev_link' filepath='net/core/dev.c' line='7265' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_master_upper_dev_link'>
-        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='7265' column='1'/>
-        <parameter type-id='68a2d05b' name='upper_dev' filepath='net/core/dev.c' line='7266' column='1'/>
-        <parameter type-id='eaa32e2f' name='upper_priv' filepath='net/core/dev.c' line='7267' column='1'/>
-        <parameter type-id='eaa32e2f' name='upper_info' filepath='net/core/dev.c' line='7267' column='1'/>
-        <parameter type-id='5799dc94' name='extack' filepath='net/core/dev.c' line='7268' column='1'/>
+      <function-decl name='netdev_master_upper_dev_link' mangled-name='netdev_master_upper_dev_link' filepath='net/core/dev.c' line='7267' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_master_upper_dev_link'>
+        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='7267' column='1'/>
+        <parameter type-id='68a2d05b' name='upper_dev' filepath='net/core/dev.c' line='7268' column='1'/>
+        <parameter type-id='eaa32e2f' name='upper_priv' filepath='net/core/dev.c' line='7269' column='1'/>
+        <parameter type-id='eaa32e2f' name='upper_info' filepath='net/core/dev.c' line='7269' column='1'/>
+        <parameter type-id='5799dc94' name='extack' filepath='net/core/dev.c' line='7270' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='dev_set_mtu' mangled-name='dev_set_mtu' filepath='net/core/dev.c' line='7864' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='dev_set_mtu'>
-        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='7864' column='1'/>
-        <parameter type-id='95e97e5e' name='new_mtu' filepath='net/core/dev.c' line='7864' column='1'/>
+      <function-decl name='dev_set_mtu' mangled-name='dev_set_mtu' filepath='net/core/dev.c' line='7866' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='dev_set_mtu'>
+        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='7866' column='1'/>
+        <parameter type-id='95e97e5e' name='new_mtu' filepath='net/core/dev.c' line='7866' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='netdev_change_features' mangled-name='netdev_change_features' filepath='net/core/dev.c' line='8517' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_change_features'>
-        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='8517' column='1'/>
+      <function-decl name='netdev_change_features' mangled-name='netdev_change_features' filepath='net/core/dev.c' line='8519' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netdev_change_features'>
+        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='8519' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='netif_stacked_transfer_operstate' mangled-name='netif_stacked_transfer_operstate' filepath='net/core/dev.c' line='8533' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_stacked_transfer_operstate'>
-        <parameter type-id='2ce52478' name='rootdev' filepath='net/core/dev.c' line='8533' column='1'/>
-        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='8534' column='1'/>
+      <function-decl name='netif_stacked_transfer_operstate' mangled-name='netif_stacked_transfer_operstate' filepath='net/core/dev.c' line='8535' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='netif_stacked_transfer_operstate'>
+        <parameter type-id='2ce52478' name='rootdev' filepath='net/core/dev.c' line='8535' column='1'/>
+        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='8536' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='init_dummy_netdev' mangled-name='init_dummy_netdev' filepath='net/core/dev.c' line='8836' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='init_dummy_netdev'>
-        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='8836' column='1'/>
+      <function-decl name='init_dummy_netdev' mangled-name='init_dummy_netdev' filepath='net/core/dev.c' line='8838' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='init_dummy_netdev'>
+        <parameter type-id='68a2d05b' name='dev' filepath='net/core/dev.c' line='8838' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
       <function-decl name='dev_get_stats' mangled-name='dev_get_stats' filepath='net/core/dev.c' line='9084' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='dev_get_stats'>
@@ -127338,6 +127608,17 @@
         <parameter type-id='f9f4b16f' name='mask' filepath='net/core/dev.c' line='9581' column='1'/>
         <return type-id='f9f4b16f'/>
       </function-decl>
+      <function-type size-in-bits='64' id='97488913'>
+        <parameter type-id='68a2d05b'/>
+        <parameter type-id='4780e252'/>
+        <parameter type-id='00e2a7ce'/>
+        <parameter type-id='26a90f95'/>
+        <return type-id='95e97e5e'/>
+      </function-type>
+      <function-type size-in-bits='64' id='cfdbff8a'>
+        <parameter type-id='68a2d05b'/>
+        <return type-id='003642fd'/>
+      </function-type>
     </abi-instr>
     <abi-instr address-size='64' path='net/core/dev_addr_lists.c' language='LANG_C89'>
       <function-decl name='dev_uc_sync_multiple' mangled-name='dev_uc_sync_multiple' filepath='net/core/dev_addr_lists.c' line='567' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='dev_uc_sync_multiple'>
@@ -127978,8 +128259,8 @@
         <parameter type-id='b50a4934' name='free_on_error' filepath='net/core/skbuff.c' line='1637' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='skb_condense' mangled-name='skb_condense' filepath='net/core/skbuff.c' line='5636' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='skb_condense'>
-        <parameter type-id='0fbf3cfd' name='skb' filepath='net/core/skbuff.c' line='5636' column='1'/>
+      <function-decl name='skb_condense' mangled-name='skb_condense' filepath='net/core/skbuff.c' line='5642' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='skb_condense'>
+        <parameter type-id='0fbf3cfd' name='skb' filepath='net/core/skbuff.c' line='5642' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
       <function-decl name='__skb_checksum' mangled-name='__skb_checksum' filepath='net/core/skbuff.c' line='2495' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__skb_checksum'>
@@ -128025,11 +128306,11 @@
     </abi-instr>
     <abi-instr address-size='64' path='net/core/sock.c' language='LANG_C89'>
       <pointer-type-def type-id='2a693ac3' size-in-bits='64' id='896f1b83'/>
-      <function-decl name='net_enable_timestamp' mangled-name='net_enable_timestamp' filepath='include/linux/netdevice.h' line='4394' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='net_enable_timestamp'>
+      <function-decl name='net_enable_timestamp' mangled-name='net_enable_timestamp' filepath='include/linux/netdevice.h' line='4411' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='net_enable_timestamp'>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='sock_wfree' mangled-name='sock_wfree' filepath='net/core/sock.c' line='1824' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_wfree'>
-        <parameter type-id='0fbf3cfd' name='skb' filepath='net/core/sock.c' line='1824' column='1'/>
+      <function-decl name='sock_wfree' mangled-name='sock_wfree' filepath='net/core/sock.c' line='1825' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_wfree'>
+        <parameter type-id='0fbf3cfd' name='skb' filepath='net/core/sock.c' line='1825' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
       <function-decl name='alloc_skb_with_frags' mangled-name='alloc_skb_with_frags' filepath='include/linux/skbuff.h' line='998' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='alloc_skb_with_frags'>
@@ -128040,124 +128321,124 @@
         <parameter type-id='f0981eeb'/>
         <return type-id='0fbf3cfd'/>
       </function-decl>
-      <function-decl name='sock_alloc_send_skb' mangled-name='sock_alloc_send_skb' filepath='net/core/sock.c' line='2122' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_alloc_send_skb'>
-        <parameter type-id='f772df6d' name='sk' filepath='net/core/sock.c' line='2122' column='1'/>
-        <parameter type-id='7359adad' name='size' filepath='net/core/sock.c' line='2122' column='1'/>
-        <parameter type-id='95e97e5e' name='noblock' filepath='net/core/sock.c' line='2123' column='1'/>
-        <parameter type-id='7292109c' name='errcode' filepath='net/core/sock.c' line='2123' column='1'/>
+      <function-decl name='sock_alloc_send_skb' mangled-name='sock_alloc_send_skb' filepath='net/core/sock.c' line='2134' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_alloc_send_skb'>
+        <parameter type-id='f772df6d' name='sk' filepath='net/core/sock.c' line='2134' column='1'/>
+        <parameter type-id='7359adad' name='size' filepath='net/core/sock.c' line='2134' column='1'/>
+        <parameter type-id='95e97e5e' name='noblock' filepath='net/core/sock.c' line='2135' column='1'/>
+        <parameter type-id='7292109c' name='errcode' filepath='net/core/sock.c' line='2135' column='1'/>
         <return type-id='0fbf3cfd'/>
       </function-decl>
-      <function-decl name='__sk_mem_schedule' mangled-name='__sk_mem_schedule' filepath='net/core/sock.c' line='2504' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__sk_mem_schedule'>
-        <parameter type-id='f772df6d' name='sk' filepath='net/core/sock.c' line='2504' column='1'/>
-        <parameter type-id='95e97e5e' name='size' filepath='net/core/sock.c' line='2504' column='1'/>
-        <parameter type-id='95e97e5e' name='kind' filepath='net/core/sock.c' line='2504' column='1'/>
+      <function-decl name='__sk_mem_schedule' mangled-name='__sk_mem_schedule' filepath='net/core/sock.c' line='2516' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__sk_mem_schedule'>
+        <parameter type-id='f772df6d' name='sk' filepath='net/core/sock.c' line='2516' column='1'/>
+        <parameter type-id='95e97e5e' name='size' filepath='net/core/sock.c' line='2516' column='1'/>
+        <parameter type-id='95e97e5e' name='kind' filepath='net/core/sock.c' line='2516' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='__sk_mem_reclaim' mangled-name='__sk_mem_reclaim' filepath='net/core/sock.c' line='2541' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__sk_mem_reclaim'>
-        <parameter type-id='f772df6d' name='sk' filepath='net/core/sock.c' line='2541' column='1'/>
-        <parameter type-id='95e97e5e' name='amount' filepath='net/core/sock.c' line='2541' column='1'/>
+      <function-decl name='__sk_mem_reclaim' mangled-name='__sk_mem_reclaim' filepath='net/core/sock.c' line='2553' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__sk_mem_reclaim'>
+        <parameter type-id='f772df6d' name='sk' filepath='net/core/sock.c' line='2553' column='1'/>
+        <parameter type-id='95e97e5e' name='amount' filepath='net/core/sock.c' line='2553' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='sock_no_socketpair' mangled-name='sock_no_socketpair' filepath='net/core/sock.c' line='2576' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_socketpair'>
-        <parameter type-id='13103032' name='sock1' filepath='net/core/sock.c' line='2576' column='1'/>
-        <parameter type-id='13103032' name='sock2' filepath='net/core/sock.c' line='2576' column='1'/>
+      <function-decl name='sock_no_socketpair' mangled-name='sock_no_socketpair' filepath='net/core/sock.c' line='2588' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_socketpair'>
+        <parameter type-id='13103032' name='sock1' filepath='net/core/sock.c' line='2588' column='1'/>
+        <parameter type-id='13103032' name='sock2' filepath='net/core/sock.c' line='2588' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sock_no_accept' mangled-name='sock_no_accept' filepath='net/core/sock.c' line='2582' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_accept'>
-        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='2582' column='1'/>
-        <parameter type-id='13103032' name='newsock' filepath='net/core/sock.c' line='2582' column='1'/>
-        <parameter type-id='95e97e5e' name='flags' filepath='net/core/sock.c' line='2582' column='1'/>
-        <parameter type-id='b50a4934' name='kern' filepath='net/core/sock.c' line='2583' column='1'/>
+      <function-decl name='sock_no_accept' mangled-name='sock_no_accept' filepath='net/core/sock.c' line='2594' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_accept'>
+        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='2594' column='1'/>
+        <parameter type-id='13103032' name='newsock' filepath='net/core/sock.c' line='2594' column='1'/>
+        <parameter type-id='95e97e5e' name='flags' filepath='net/core/sock.c' line='2594' column='1'/>
+        <parameter type-id='b50a4934' name='kern' filepath='net/core/sock.c' line='2595' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sock_no_ioctl' mangled-name='sock_no_ioctl' filepath='net/core/sock.c' line='2596' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_ioctl'>
-        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='2596' column='1'/>
-        <parameter type-id='f0981eeb' name='cmd' filepath='net/core/sock.c' line='2596' column='1'/>
-        <parameter type-id='7359adad' name='arg' filepath='net/core/sock.c' line='2596' column='1'/>
+      <function-decl name='sock_no_ioctl' mangled-name='sock_no_ioctl' filepath='net/core/sock.c' line='2608' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_ioctl'>
+        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='2608' column='1'/>
+        <parameter type-id='f0981eeb' name='cmd' filepath='net/core/sock.c' line='2608' column='1'/>
+        <parameter type-id='7359adad' name='arg' filepath='net/core/sock.c' line='2608' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sock_no_listen' mangled-name='sock_no_listen' filepath='net/core/sock.c' line='2602' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_listen'>
-        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='2602' column='1'/>
-        <parameter type-id='95e97e5e' name='backlog' filepath='net/core/sock.c' line='2602' column='1'/>
+      <function-decl name='sock_no_listen' mangled-name='sock_no_listen' filepath='net/core/sock.c' line='2614' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_listen'>
+        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='2614' column='1'/>
+        <parameter type-id='95e97e5e' name='backlog' filepath='net/core/sock.c' line='2614' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sock_no_shutdown' mangled-name='sock_no_shutdown' filepath='net/core/sock.c' line='2608' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_shutdown'>
-        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='2608' column='1'/>
-        <parameter type-id='95e97e5e' name='how' filepath='net/core/sock.c' line='2608' column='1'/>
+      <function-decl name='sock_no_shutdown' mangled-name='sock_no_shutdown' filepath='net/core/sock.c' line='2620' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_shutdown'>
+        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='2620' column='1'/>
+        <parameter type-id='95e97e5e' name='how' filepath='net/core/sock.c' line='2620' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sock_no_setsockopt' mangled-name='sock_no_setsockopt' filepath='net/core/sock.c' line='2614' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_setsockopt'>
-        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='2614' column='1'/>
-        <parameter type-id='95e97e5e' name='level' filepath='net/core/sock.c' line='2614' column='1'/>
-        <parameter type-id='95e97e5e' name='optname' filepath='net/core/sock.c' line='2614' column='1'/>
-        <parameter type-id='26a90f95' name='optval' filepath='net/core/sock.c' line='2615' column='1'/>
-        <parameter type-id='f0981eeb' name='optlen' filepath='net/core/sock.c' line='2615' column='1'/>
+      <function-decl name='sock_no_setsockopt' mangled-name='sock_no_setsockopt' filepath='net/core/sock.c' line='2626' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_setsockopt'>
+        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='2626' column='1'/>
+        <parameter type-id='95e97e5e' name='level' filepath='net/core/sock.c' line='2626' column='1'/>
+        <parameter type-id='95e97e5e' name='optname' filepath='net/core/sock.c' line='2626' column='1'/>
+        <parameter type-id='26a90f95' name='optval' filepath='net/core/sock.c' line='2627' column='1'/>
+        <parameter type-id='f0981eeb' name='optlen' filepath='net/core/sock.c' line='2627' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sock_no_getsockopt' mangled-name='sock_no_getsockopt' filepath='net/core/sock.c' line='2621' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_getsockopt'>
-        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='2621' column='1'/>
-        <parameter type-id='95e97e5e' name='level' filepath='net/core/sock.c' line='2621' column='1'/>
-        <parameter type-id='95e97e5e' name='optname' filepath='net/core/sock.c' line='2621' column='1'/>
-        <parameter type-id='26a90f95' name='optval' filepath='net/core/sock.c' line='2622' column='1'/>
-        <parameter type-id='7292109c' name='optlen' filepath='net/core/sock.c' line='2622' column='1'/>
+      <function-decl name='sock_no_getsockopt' mangled-name='sock_no_getsockopt' filepath='net/core/sock.c' line='2633' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_getsockopt'>
+        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='2633' column='1'/>
+        <parameter type-id='95e97e5e' name='level' filepath='net/core/sock.c' line='2633' column='1'/>
+        <parameter type-id='95e97e5e' name='optname' filepath='net/core/sock.c' line='2633' column='1'/>
+        <parameter type-id='26a90f95' name='optval' filepath='net/core/sock.c' line='2634' column='1'/>
+        <parameter type-id='7292109c' name='optlen' filepath='net/core/sock.c' line='2634' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sock_no_mmap' mangled-name='sock_no_mmap' filepath='net/core/sock.c' line='2647' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_mmap'>
-        <parameter type-id='77e79a4b' name='file' filepath='net/core/sock.c' line='2647' column='1'/>
-        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='2647' column='1'/>
-        <parameter type-id='2ae08426' name='vma' filepath='net/core/sock.c' line='2647' column='1'/>
+      <function-decl name='sock_no_mmap' mangled-name='sock_no_mmap' filepath='net/core/sock.c' line='2659' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_mmap'>
+        <parameter type-id='77e79a4b' name='file' filepath='net/core/sock.c' line='2659' column='1'/>
+        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='2659' column='1'/>
+        <parameter type-id='2ae08426' name='vma' filepath='net/core/sock.c' line='2659' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sock_get_timestamp' mangled-name='sock_get_timestamp' filepath='net/core/sock.c' line='2949' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_get_timestamp'>
-        <parameter type-id='f772df6d' name='sk' filepath='net/core/sock.c' line='2949' column='1'/>
-        <parameter type-id='896f1b83' name='userstamp' filepath='net/core/sock.c' line='2949' column='1'/>
+      <function-decl name='sock_get_timestamp' mangled-name='sock_get_timestamp' filepath='net/core/sock.c' line='2961' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_get_timestamp'>
+        <parameter type-id='f772df6d' name='sk' filepath='net/core/sock.c' line='2961' column='1'/>
+        <parameter type-id='896f1b83' name='userstamp' filepath='net/core/sock.c' line='2961' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sock_common_getsockopt' mangled-name='sock_common_getsockopt' filepath='net/core/sock.c' line='3043' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_common_getsockopt'>
-        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='3043' column='1'/>
-        <parameter type-id='95e97e5e' name='level' filepath='net/core/sock.c' line='3043' column='1'/>
-        <parameter type-id='95e97e5e' name='optname' filepath='net/core/sock.c' line='3043' column='1'/>
-        <parameter type-id='26a90f95' name='optval' filepath='net/core/sock.c' line='3044' column='1'/>
-        <parameter type-id='7292109c' name='optlen' filepath='net/core/sock.c' line='3044' column='1'/>
+      <function-decl name='sock_common_getsockopt' mangled-name='sock_common_getsockopt' filepath='net/core/sock.c' line='3055' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_common_getsockopt'>
+        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='3055' column='1'/>
+        <parameter type-id='95e97e5e' name='level' filepath='net/core/sock.c' line='3055' column='1'/>
+        <parameter type-id='95e97e5e' name='optname' filepath='net/core/sock.c' line='3055' column='1'/>
+        <parameter type-id='26a90f95' name='optval' filepath='net/core/sock.c' line='3056' column='1'/>
+        <parameter type-id='7292109c' name='optlen' filepath='net/core/sock.c' line='3056' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='compat_sock_common_getsockopt' mangled-name='compat_sock_common_getsockopt' filepath='net/core/sock.c' line='3053' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='compat_sock_common_getsockopt'>
-        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='3053' column='1'/>
-        <parameter type-id='95e97e5e' name='level' filepath='net/core/sock.c' line='3053' column='1'/>
-        <parameter type-id='95e97e5e' name='optname' filepath='net/core/sock.c' line='3053' column='1'/>
-        <parameter type-id='26a90f95' name='optval' filepath='net/core/sock.c' line='3054' column='1'/>
-        <parameter type-id='7292109c' name='optlen' filepath='net/core/sock.c' line='3054' column='1'/>
+      <function-decl name='compat_sock_common_getsockopt' mangled-name='compat_sock_common_getsockopt' filepath='net/core/sock.c' line='3065' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='compat_sock_common_getsockopt'>
+        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='3065' column='1'/>
+        <parameter type-id='95e97e5e' name='level' filepath='net/core/sock.c' line='3065' column='1'/>
+        <parameter type-id='95e97e5e' name='optname' filepath='net/core/sock.c' line='3065' column='1'/>
+        <parameter type-id='26a90f95' name='optval' filepath='net/core/sock.c' line='3066' column='1'/>
+        <parameter type-id='7292109c' name='optlen' filepath='net/core/sock.c' line='3066' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sock_common_setsockopt' mangled-name='sock_common_setsockopt' filepath='net/core/sock.c' line='3084' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_common_setsockopt'>
-        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='3084' column='1'/>
-        <parameter type-id='95e97e5e' name='level' filepath='net/core/sock.c' line='3084' column='1'/>
-        <parameter type-id='95e97e5e' name='optname' filepath='net/core/sock.c' line='3084' column='1'/>
-        <parameter type-id='26a90f95' name='optval' filepath='net/core/sock.c' line='3085' column='1'/>
-        <parameter type-id='f0981eeb' name='optlen' filepath='net/core/sock.c' line='3085' column='1'/>
+      <function-decl name='sock_common_setsockopt' mangled-name='sock_common_setsockopt' filepath='net/core/sock.c' line='3096' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_common_setsockopt'>
+        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='3096' column='1'/>
+        <parameter type-id='95e97e5e' name='level' filepath='net/core/sock.c' line='3096' column='1'/>
+        <parameter type-id='95e97e5e' name='optname' filepath='net/core/sock.c' line='3096' column='1'/>
+        <parameter type-id='26a90f95' name='optval' filepath='net/core/sock.c' line='3097' column='1'/>
+        <parameter type-id='f0981eeb' name='optlen' filepath='net/core/sock.c' line='3097' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='compat_sock_common_setsockopt' mangled-name='compat_sock_common_setsockopt' filepath='net/core/sock.c' line='3094' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='compat_sock_common_setsockopt'>
-        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='3094' column='1'/>
-        <parameter type-id='95e97e5e' name='level' filepath='net/core/sock.c' line='3094' column='1'/>
-        <parameter type-id='95e97e5e' name='optname' filepath='net/core/sock.c' line='3094' column='1'/>
-        <parameter type-id='26a90f95' name='optval' filepath='net/core/sock.c' line='3095' column='1'/>
-        <parameter type-id='f0981eeb' name='optlen' filepath='net/core/sock.c' line='3095' column='1'/>
+      <function-decl name='compat_sock_common_setsockopt' mangled-name='compat_sock_common_setsockopt' filepath='net/core/sock.c' line='3106' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='compat_sock_common_setsockopt'>
+        <parameter type-id='13103032' name='sock' filepath='net/core/sock.c' line='3106' column='1'/>
+        <parameter type-id='95e97e5e' name='level' filepath='net/core/sock.c' line='3106' column='1'/>
+        <parameter type-id='95e97e5e' name='optname' filepath='net/core/sock.c' line='3106' column='1'/>
+        <parameter type-id='26a90f95' name='optval' filepath='net/core/sock.c' line='3107' column='1'/>
+        <parameter type-id='f0981eeb' name='optlen' filepath='net/core/sock.c' line='3107' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sk_common_release' mangled-name='sk_common_release' filepath='net/core/sock.c' line='3107' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sk_common_release'>
-        <parameter type-id='f772df6d' name='sk' filepath='net/core/sock.c' line='3107' column='1'/>
+      <function-decl name='sk_common_release' mangled-name='sk_common_release' filepath='net/core/sock.c' line='3119' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sk_common_release'>
+        <parameter type-id='f772df6d' name='sk' filepath='net/core/sock.c' line='3119' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='sock_prot_inuse_add' mangled-name='sock_prot_inuse_add' filepath='net/core/sock.c' line='3167' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_prot_inuse_add'>
-        <parameter type-id='a2bff676' name='net' filepath='net/core/sock.c' line='3167' column='1'/>
-        <parameter type-id='d2524501' name='prot' filepath='net/core/sock.c' line='3167' column='1'/>
-        <parameter type-id='95e97e5e' name='val' filepath='net/core/sock.c' line='3167' column='1'/>
+      <function-decl name='sock_prot_inuse_add' mangled-name='sock_prot_inuse_add' filepath='net/core/sock.c' line='3179' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_prot_inuse_add'>
+        <parameter type-id='a2bff676' name='net' filepath='net/core/sock.c' line='3179' column='1'/>
+        <parameter type-id='d2524501' name='prot' filepath='net/core/sock.c' line='3179' column='1'/>
+        <parameter type-id='95e97e5e' name='val' filepath='net/core/sock.c' line='3179' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='sk_busy_loop_end' mangled-name='sk_busy_loop_end' filepath='net/core/sock.c' line='3526' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sk_busy_loop_end'>
-        <parameter type-id='eaa32e2f' name='p' filepath='net/core/sock.c' line='3526' column='1'/>
-        <parameter type-id='7359adad' name='start_time' filepath='net/core/sock.c' line='3526' column='1'/>
+      <function-decl name='sk_busy_loop_end' mangled-name='sk_busy_loop_end' filepath='net/core/sock.c' line='3538' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sk_busy_loop_end'>
+        <parameter type-id='eaa32e2f' name='p' filepath='net/core/sock.c' line='3538' column='1'/>
+        <parameter type-id='7359adad' name='start_time' filepath='net/core/sock.c' line='3538' column='1'/>
         <return type-id='b50a4934'/>
       </function-decl>
     </abi-instr>
@@ -128287,15 +128568,15 @@
           <var-decl name='flags' type-id='f0981eeb' visibility='default' filepath='include/net/protocol.h' line='74' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='offload_callbacks' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='2407' column='1' id='cbdbefb1'>
+      <class-decl name='offload_callbacks' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/linux/netdevice.h' line='2406' column='1' id='cbdbefb1'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='gso_segment' type-id='c256a724' visibility='default' filepath='include/linux/netdevice.h' line='2408' column='1'/>
+          <var-decl name='gso_segment' type-id='c256a724' visibility='default' filepath='include/linux/netdevice.h' line='2407' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='gro_receive' type-id='54aa9dbd' visibility='default' filepath='include/linux/netdevice.h' line='2410' column='1'/>
+          <var-decl name='gro_receive' type-id='54aa9dbd' visibility='default' filepath='include/linux/netdevice.h' line='2409' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='gro_complete' type-id='0aeca82c' visibility='default' filepath='include/linux/netdevice.h' line='2412' column='1'/>
+          <var-decl name='gro_complete' type-id='0aeca82c' visibility='default' filepath='include/linux/netdevice.h' line='2411' column='1'/>
         </data-member>
       </class-decl>
       <qualified-type-def type-id='6785038a' const='yes' id='dfc5bf71'/>
@@ -128483,36 +128764,36 @@
       </function-decl>
     </abi-instr>
     <abi-instr address-size='64' path='net/ipv4/ip_sockglue.c' language='LANG_C89'>
-      <function-decl name='ip_setsockopt' mangled-name='ip_setsockopt' filepath='net/ipv4/ip_sockglue.c' line='1238' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='ip_setsockopt'>
-        <parameter type-id='f772df6d' name='sk' filepath='net/ipv4/ip_sockglue.c' line='1238' column='1'/>
-        <parameter type-id='95e97e5e' name='level' filepath='net/ipv4/ip_sockglue.c' line='1238' column='1'/>
-        <parameter type-id='95e97e5e' name='optname' filepath='net/ipv4/ip_sockglue.c' line='1239' column='1'/>
-        <parameter type-id='26a90f95' name='optval' filepath='net/ipv4/ip_sockglue.c' line='1239' column='1'/>
-        <parameter type-id='f0981eeb' name='optlen' filepath='net/ipv4/ip_sockglue.c' line='1239' column='1'/>
+      <function-decl name='ip_setsockopt' mangled-name='ip_setsockopt' filepath='net/ipv4/ip_sockglue.c' line='1245' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='ip_setsockopt'>
+        <parameter type-id='f772df6d' name='sk' filepath='net/ipv4/ip_sockglue.c' line='1245' column='1'/>
+        <parameter type-id='95e97e5e' name='level' filepath='net/ipv4/ip_sockglue.c' line='1245' column='1'/>
+        <parameter type-id='95e97e5e' name='optname' filepath='net/ipv4/ip_sockglue.c' line='1246' column='1'/>
+        <parameter type-id='26a90f95' name='optval' filepath='net/ipv4/ip_sockglue.c' line='1246' column='1'/>
+        <parameter type-id='f0981eeb' name='optlen' filepath='net/ipv4/ip_sockglue.c' line='1246' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='compat_ip_setsockopt' mangled-name='compat_ip_setsockopt' filepath='net/ipv4/ip_sockglue.c' line='1265' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='compat_ip_setsockopt'>
-        <parameter type-id='f772df6d' name='sk' filepath='net/ipv4/ip_sockglue.c' line='1265' column='1'/>
-        <parameter type-id='95e97e5e' name='level' filepath='net/ipv4/ip_sockglue.c' line='1265' column='1'/>
-        <parameter type-id='95e97e5e' name='optname' filepath='net/ipv4/ip_sockglue.c' line='1265' column='1'/>
-        <parameter type-id='26a90f95' name='optval' filepath='net/ipv4/ip_sockglue.c' line='1266' column='1'/>
-        <parameter type-id='f0981eeb' name='optlen' filepath='net/ipv4/ip_sockglue.c' line='1266' column='1'/>
+      <function-decl name='compat_ip_setsockopt' mangled-name='compat_ip_setsockopt' filepath='net/ipv4/ip_sockglue.c' line='1272' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='compat_ip_setsockopt'>
+        <parameter type-id='f772df6d' name='sk' filepath='net/ipv4/ip_sockglue.c' line='1272' column='1'/>
+        <parameter type-id='95e97e5e' name='level' filepath='net/ipv4/ip_sockglue.c' line='1272' column='1'/>
+        <parameter type-id='95e97e5e' name='optname' filepath='net/ipv4/ip_sockglue.c' line='1272' column='1'/>
+        <parameter type-id='26a90f95' name='optval' filepath='net/ipv4/ip_sockglue.c' line='1273' column='1'/>
+        <parameter type-id='f0981eeb' name='optlen' filepath='net/ipv4/ip_sockglue.c' line='1273' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='ip_getsockopt' mangled-name='ip_getsockopt' filepath='net/ipv4/ip_sockglue.c' line='1554' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='ip_getsockopt'>
-        <parameter type-id='f772df6d' name='sk' filepath='net/ipv4/ip_sockglue.c' line='1554' column='1'/>
-        <parameter type-id='95e97e5e' name='level' filepath='net/ipv4/ip_sockglue.c' line='1554' column='1'/>
-        <parameter type-id='95e97e5e' name='optname' filepath='net/ipv4/ip_sockglue.c' line='1555' column='1'/>
-        <parameter type-id='26a90f95' name='optval' filepath='net/ipv4/ip_sockglue.c' line='1555' column='1'/>
-        <parameter type-id='7292109c' name='optlen' filepath='net/ipv4/ip_sockglue.c' line='1555' column='1'/>
+      <function-decl name='ip_getsockopt' mangled-name='ip_getsockopt' filepath='net/ipv4/ip_sockglue.c' line='1564' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='ip_getsockopt'>
+        <parameter type-id='f772df6d' name='sk' filepath='net/ipv4/ip_sockglue.c' line='1564' column='1'/>
+        <parameter type-id='95e97e5e' name='level' filepath='net/ipv4/ip_sockglue.c' line='1564' column='1'/>
+        <parameter type-id='95e97e5e' name='optname' filepath='net/ipv4/ip_sockglue.c' line='1565' column='1'/>
+        <parameter type-id='26a90f95' name='optval' filepath='net/ipv4/ip_sockglue.c' line='1565' column='1'/>
+        <parameter type-id='7292109c' name='optlen' filepath='net/ipv4/ip_sockglue.c' line='1565' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='compat_ip_getsockopt' mangled-name='compat_ip_getsockopt' filepath='net/ipv4/ip_sockglue.c' line='1585' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='compat_ip_getsockopt'>
-        <parameter type-id='f772df6d' name='sk' filepath='net/ipv4/ip_sockglue.c' line='1585' column='1'/>
-        <parameter type-id='95e97e5e' name='level' filepath='net/ipv4/ip_sockglue.c' line='1585' column='1'/>
-        <parameter type-id='95e97e5e' name='optname' filepath='net/ipv4/ip_sockglue.c' line='1585' column='1'/>
-        <parameter type-id='26a90f95' name='optval' filepath='net/ipv4/ip_sockglue.c' line='1586' column='1'/>
-        <parameter type-id='7292109c' name='optlen' filepath='net/ipv4/ip_sockglue.c' line='1586' column='1'/>
+      <function-decl name='compat_ip_getsockopt' mangled-name='compat_ip_getsockopt' filepath='net/ipv4/ip_sockglue.c' line='1595' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='compat_ip_getsockopt'>
+        <parameter type-id='f772df6d' name='sk' filepath='net/ipv4/ip_sockglue.c' line='1595' column='1'/>
+        <parameter type-id='95e97e5e' name='level' filepath='net/ipv4/ip_sockglue.c' line='1595' column='1'/>
+        <parameter type-id='95e97e5e' name='optname' filepath='net/ipv4/ip_sockglue.c' line='1595' column='1'/>
+        <parameter type-id='26a90f95' name='optval' filepath='net/ipv4/ip_sockglue.c' line='1596' column='1'/>
+        <parameter type-id='7292109c' name='optlen' filepath='net/ipv4/ip_sockglue.c' line='1596' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
     </abi-instr>
@@ -128710,7 +128991,7 @@
           <var-decl name='next_rcu' type-id='26479c18' visibility='default' filepath='include/linux/igmp.h' line='83' column='1'/>
         </data-member>
       </union-decl>
-      <enum-decl name='tcp_ca_event' filepath='include/net/tcp.h' line='956' column='1' id='5f51e977'>
+      <enum-decl name='tcp_ca_event' filepath='include/net/tcp.h' line='961' column='1' id='5f51e977'>
         <underlying-type type-id='9cac1fee'/>
         <enumerator name='CA_EVENT_TX_START' value='0'/>
         <enumerator name='CA_EVENT_CWND_RESTART' value='1'/>
@@ -128719,56 +129000,56 @@
         <enumerator name='CA_EVENT_ECN_NO_CE' value='4'/>
         <enumerator name='CA_EVENT_ECN_IS_CE' value='5'/>
       </enum-decl>
-      <class-decl name='ack_sample' size-in-bits='96' is-struct='yes' visibility='default' filepath='include/net/tcp.h' line='988' column='1' id='cd7d3c9d'>
+      <class-decl name='ack_sample' size-in-bits='96' is-struct='yes' visibility='default' filepath='include/net/tcp.h' line='993' column='1' id='cd7d3c9d'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='pkts_acked' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='989' column='1'/>
+          <var-decl name='pkts_acked' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='994' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='rtt_us' type-id='a7832498' visibility='default' filepath='include/net/tcp.h' line='990' column='1'/>
+          <var-decl name='rtt_us' type-id='a7832498' visibility='default' filepath='include/net/tcp.h' line='995' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='in_flight' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='991' column='1'/>
+          <var-decl name='in_flight' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='996' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='rate_sample' size-in-bits='448' is-struct='yes' visibility='default' filepath='include/net/tcp.h' line='1002' column='1' id='a084c932'>
+      <class-decl name='rate_sample' size-in-bits='448' is-struct='yes' visibility='default' filepath='include/net/tcp.h' line='1007' column='1' id='a084c932'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='prior_mstamp' type-id='91ce1af9' visibility='default' filepath='include/net/tcp.h' line='1003' column='1'/>
+          <var-decl name='prior_mstamp' type-id='91ce1af9' visibility='default' filepath='include/net/tcp.h' line='1008' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='prior_delivered' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1004' column='1'/>
+          <var-decl name='prior_delivered' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1009' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='delivered' type-id='a7832498' visibility='default' filepath='include/net/tcp.h' line='1005' column='1'/>
+          <var-decl name='delivered' type-id='a7832498' visibility='default' filepath='include/net/tcp.h' line='1010' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='interval_us' type-id='bd54fe1a' visibility='default' filepath='include/net/tcp.h' line='1006' column='1'/>
+          <var-decl name='interval_us' type-id='bd54fe1a' visibility='default' filepath='include/net/tcp.h' line='1011' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='snd_interval_us' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1007' column='1'/>
+          <var-decl name='snd_interval_us' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1012' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='224'>
-          <var-decl name='rcv_interval_us' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1008' column='1'/>
+          <var-decl name='rcv_interval_us' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1013' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='rtt_us' type-id='bd54fe1a' visibility='default' filepath='include/net/tcp.h' line='1009' column='1'/>
+          <var-decl name='rtt_us' type-id='bd54fe1a' visibility='default' filepath='include/net/tcp.h' line='1014' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='losses' type-id='95e97e5e' visibility='default' filepath='include/net/tcp.h' line='1010' column='1'/>
+          <var-decl name='losses' type-id='95e97e5e' visibility='default' filepath='include/net/tcp.h' line='1015' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='352'>
-          <var-decl name='acked_sacked' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1011' column='1'/>
+          <var-decl name='acked_sacked' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1016' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='prior_in_flight' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1012' column='1'/>
+          <var-decl name='prior_in_flight' type-id='19c2251e' visibility='default' filepath='include/net/tcp.h' line='1017' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='416'>
-          <var-decl name='is_app_limited' type-id='b50a4934' visibility='default' filepath='include/net/tcp.h' line='1013' column='1'/>
+          <var-decl name='is_app_limited' type-id='b50a4934' visibility='default' filepath='include/net/tcp.h' line='1018' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='424'>
-          <var-decl name='is_retrans' type-id='b50a4934' visibility='default' filepath='include/net/tcp.h' line='1014' column='1'/>
+          <var-decl name='is_retrans' type-id='b50a4934' visibility='default' filepath='include/net/tcp.h' line='1019' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='432'>
-          <var-decl name='is_ack_delayed' type-id='b50a4934' visibility='default' filepath='include/net/tcp.h' line='1015' column='1'/>
+          <var-decl name='is_ack_delayed' type-id='b50a4934' visibility='default' filepath='include/net/tcp.h' line='1020' column='1'/>
         </data-member>
       </class-decl>
       <qualified-type-def type-id='cd7d3c9d' const='yes' id='67a1c23c'/>
@@ -128815,7 +129096,7 @@
         <parameter type-id='8b97c2dc'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='inet_get_local_port_range' mangled-name='inet_get_local_port_range' filepath='include/net/ip.h' line='302' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='inet_get_local_port_range'>
+      <function-decl name='inet_get_local_port_range' mangled-name='inet_get_local_port_range' filepath='include/net/ip.h' line='304' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='inet_get_local_port_range'>
         <parameter type-id='a2bff676'/>
         <parameter type-id='7292109c'/>
         <parameter type-id='7292109c'/>
@@ -129094,15 +129375,15 @@
       </function-decl>
     </abi-instr>
     <abi-instr address-size='64' path='net/ipv6/addrconf.c' language='LANG_C89'>
-      <function-decl name='in6_dev_finish_destroy' mangled-name='in6_dev_finish_destroy' filepath='include/net/addrconf.h' line='396' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='in6_dev_finish_destroy'>
+      <function-decl name='in6_dev_finish_destroy' mangled-name='in6_dev_finish_destroy' filepath='include/net/addrconf.h' line='412' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='in6_dev_finish_destroy'>
         <parameter type-id='f026b16b'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='ipv6_chk_addr' mangled-name='ipv6_chk_addr' filepath='net/ipv6/addrconf.c' line='1851' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='ipv6_chk_addr'>
-        <parameter type-id='a2bff676' name='net' filepath='net/ipv6/addrconf.c' line='1851' column='1'/>
-        <parameter type-id='fea9c20b' name='addr' filepath='net/ipv6/addrconf.c' line='1851' column='1'/>
-        <parameter type-id='2ce52478' name='dev' filepath='net/ipv6/addrconf.c' line='1852' column='1'/>
-        <parameter type-id='95e97e5e' name='strict' filepath='net/ipv6/addrconf.c' line='1852' column='1'/>
+      <function-decl name='ipv6_chk_addr' mangled-name='ipv6_chk_addr' filepath='net/ipv6/addrconf.c' line='1850' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='ipv6_chk_addr'>
+        <parameter type-id='a2bff676' name='net' filepath='net/ipv6/addrconf.c' line='1850' column='1'/>
+        <parameter type-id='fea9c20b' name='addr' filepath='net/ipv6/addrconf.c' line='1850' column='1'/>
+        <parameter type-id='2ce52478' name='dev' filepath='net/ipv6/addrconf.c' line='1851' column='1'/>
+        <parameter type-id='95e97e5e' name='strict' filepath='net/ipv6/addrconf.c' line='1851' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
     </abi-instr>
@@ -129211,13 +129492,13 @@
         <parameter type-id='a976bab6' name='p' filepath='net/ipv6/af_inet6.c' line='712' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='fl6_update_dst' mangled-name='fl6_update_dst' filepath='include/net/ipv6.h' line='1009' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='fl6_update_dst'>
+      <function-decl name='fl6_update_dst' mangled-name='fl6_update_dst' filepath='include/net/ipv6.h' line='1005' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='fl6_update_dst'>
         <parameter type-id='a99cde64'/>
         <parameter type-id='b5a73d82'/>
         <parameter type-id='ed512028'/>
         <return type-id='ed512028'/>
       </function-decl>
-      <function-decl name='ip6_dst_lookup_flow' mangled-name='ip6_dst_lookup_flow' filepath='include/net/ipv6.h' line='962' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='ip6_dst_lookup_flow'>
+      <function-decl name='ip6_dst_lookup_flow' mangled-name='ip6_dst_lookup_flow' filepath='include/net/ipv6.h' line='958' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='ip6_dst_lookup_flow'>
         <parameter type-id='a2bff676'/>
         <parameter type-id='78e7cf52'/>
         <parameter type-id='a99cde64'/>
@@ -129244,7 +129525,7 @@
       </function-decl>
     </abi-instr>
     <abi-instr address-size='64' path='net/ipv6/ip6_vti.c' language='LANG_C89'>
-      <function-decl name='unregister_netdevice_many' mangled-name='unregister_netdevice_many' filepath='include/linux/netdevice.h' line='2666' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='unregister_netdevice_many'>
+      <function-decl name='unregister_netdevice_many' mangled-name='unregister_netdevice_many' filepath='include/linux/netdevice.h' line='2665' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='unregister_netdevice_many'>
         <parameter type-id='e84b031a'/>
         <return type-id='48b5725f'/>
       </function-decl>
@@ -129446,7 +129727,7 @@
         <parameter type-id='95e97e5e'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='sock_i_ino' mangled-name='sock_i_ino' filepath='include/net/sock.h' line='1839' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_i_ino'>
+      <function-decl name='sock_i_ino' mangled-name='sock_i_ino' filepath='include/net/sock.h' line='1855' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_i_ino'>
         <parameter type-id='f772df6d'/>
         <return type-id='7359adad'/>
       </function-decl>
@@ -129698,7 +129979,7 @@
       <pointer-type-def type-id='6ddd203f' size-in-bits='64' id='9b92b29b'/>
       <pointer-type-def type-id='63e171df' size-in-bits='64' id='30e664af'/>
       <pointer-type-def type-id='68a72cd7' size-in-bits='64' id='b6316a7f'/>
-      <function-decl name='unregister_netdevice_notifier' mangled-name='unregister_netdevice_notifier' filepath='include/linux/netdevice.h' line='2524' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='unregister_netdevice_notifier'>
+      <function-decl name='unregister_netdevice_notifier' mangled-name='unregister_netdevice_notifier' filepath='include/linux/netdevice.h' line='2523' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='unregister_netdevice_notifier'>
         <parameter type-id='d504f73d'/>
         <return type-id='95e97e5e'/>
       </function-decl>
@@ -129734,7 +130015,7 @@
         <parameter type-id='d6907f4c'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='register_netdevice_notifier' mangled-name='register_netdevice_notifier' filepath='include/linux/netdevice.h' line='2523' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='register_netdevice_notifier'>
+      <function-decl name='register_netdevice_notifier' mangled-name='register_netdevice_notifier' filepath='include/linux/netdevice.h' line='2522' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='register_netdevice_notifier'>
         <parameter type-id='d504f73d'/>
         <return type-id='95e97e5e'/>
       </function-decl>
@@ -130042,7 +130323,7 @@
         <parameter type-id='eaa32e2f'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='sock_i_uid' mangled-name='sock_i_uid' filepath='include/net/sock.h' line='1838' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_i_uid'>
+      <function-decl name='sock_i_uid' mangled-name='sock_i_uid' filepath='include/net/sock.h' line='1853' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_i_uid'>
         <parameter type-id='f772df6d'/>
         <return type-id='e8b29774'/>
       </function-decl>
@@ -130075,7 +130356,7 @@
       </function-decl>
     </abi-instr>
     <abi-instr address-size='64' path='net/netfilter/xt_TCPMSS.c' language='LANG_C89'>
-      <function-decl name='ipv6_skip_exthdr' mangled-name='ipv6_skip_exthdr' filepath='include/net/ipv6.h' line='992' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='ipv6_skip_exthdr'>
+      <function-decl name='ipv6_skip_exthdr' mangled-name='ipv6_skip_exthdr' filepath='include/net/ipv6.h' line='988' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='ipv6_skip_exthdr'>
         <parameter type-id='11f4a000'/>
         <parameter type-id='95e97e5e'/>
         <parameter type-id='cf536864'/>
@@ -130442,27 +130723,27 @@
       <pointer-type-def type-id='21ec1a55' size-in-bits='64' id='6984e365'/>
       <pointer-type-def type-id='f7a1d399' size-in-bits='64' id='8438f281'/>
       <pointer-type-def type-id='64a9bab2' size-in-bits='64' id='bfc146e4'/>
-      <function-decl name='__netlink_kernel_create' mangled-name='__netlink_kernel_create' filepath='net/netlink/af_netlink.c' line='2013' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__netlink_kernel_create'>
-        <parameter type-id='a2bff676' name='net' filepath='net/netlink/af_netlink.c' line='2013' column='1'/>
-        <parameter type-id='95e97e5e' name='unit' filepath='net/netlink/af_netlink.c' line='2013' column='1'/>
-        <parameter type-id='2730d015' name='module' filepath='net/netlink/af_netlink.c' line='2013' column='1'/>
-        <parameter type-id='8438f281' name='cfg' filepath='net/netlink/af_netlink.c' line='2014' column='1'/>
+      <function-decl name='__netlink_kernel_create' mangled-name='__netlink_kernel_create' filepath='net/netlink/af_netlink.c' line='2014' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__netlink_kernel_create'>
+        <parameter type-id='a2bff676' name='net' filepath='net/netlink/af_netlink.c' line='2014' column='1'/>
+        <parameter type-id='95e97e5e' name='unit' filepath='net/netlink/af_netlink.c' line='2014' column='1'/>
+        <parameter type-id='2730d015' name='module' filepath='net/netlink/af_netlink.c' line='2014' column='1'/>
+        <parameter type-id='8438f281' name='cfg' filepath='net/netlink/af_netlink.c' line='2015' column='1'/>
         <return type-id='f772df6d'/>
       </function-decl>
-      <function-decl name='__nlmsg_put' mangled-name='__nlmsg_put' filepath='net/netlink/af_netlink.c' line='2153' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__nlmsg_put'>
-        <parameter type-id='0fbf3cfd' name='skb' filepath='net/netlink/af_netlink.c' line='2153' column='1'/>
-        <parameter type-id='19c2251e' name='portid' filepath='net/netlink/af_netlink.c' line='2153' column='1'/>
-        <parameter type-id='19c2251e' name='seq' filepath='net/netlink/af_netlink.c' line='2153' column='1'/>
-        <parameter type-id='95e97e5e' name='type' filepath='net/netlink/af_netlink.c' line='2153' column='1'/>
-        <parameter type-id='95e97e5e' name='len' filepath='net/netlink/af_netlink.c' line='2153' column='1'/>
-        <parameter type-id='95e97e5e' name='flags' filepath='net/netlink/af_netlink.c' line='2153' column='1'/>
+      <function-decl name='__nlmsg_put' mangled-name='__nlmsg_put' filepath='net/netlink/af_netlink.c' line='2154' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__nlmsg_put'>
+        <parameter type-id='0fbf3cfd' name='skb' filepath='net/netlink/af_netlink.c' line='2154' column='1'/>
+        <parameter type-id='19c2251e' name='portid' filepath='net/netlink/af_netlink.c' line='2154' column='1'/>
+        <parameter type-id='19c2251e' name='seq' filepath='net/netlink/af_netlink.c' line='2154' column='1'/>
+        <parameter type-id='95e97e5e' name='type' filepath='net/netlink/af_netlink.c' line='2154' column='1'/>
+        <parameter type-id='95e97e5e' name='len' filepath='net/netlink/af_netlink.c' line='2154' column='1'/>
+        <parameter type-id='95e97e5e' name='flags' filepath='net/netlink/af_netlink.c' line='2154' column='1'/>
         <return type-id='c2074578'/>
       </function-decl>
-      <function-decl name='__netlink_dump_start' mangled-name='__netlink_dump_start' filepath='net/netlink/af_netlink.c' line='2282' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__netlink_dump_start'>
-        <parameter type-id='f772df6d' name='ssk' filepath='net/netlink/af_netlink.c' line='2282' column='1'/>
-        <parameter type-id='0fbf3cfd' name='skb' filepath='net/netlink/af_netlink.c' line='2282' column='1'/>
-        <parameter type-id='390fbe8f' name='nlh' filepath='net/netlink/af_netlink.c' line='2283' column='1'/>
-        <parameter type-id='6984e365' name='control' filepath='net/netlink/af_netlink.c' line='2284' column='1'/>
+      <function-decl name='__netlink_dump_start' mangled-name='__netlink_dump_start' filepath='net/netlink/af_netlink.c' line='2283' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__netlink_dump_start'>
+        <parameter type-id='f772df6d' name='ssk' filepath='net/netlink/af_netlink.c' line='2283' column='1'/>
+        <parameter type-id='0fbf3cfd' name='skb' filepath='net/netlink/af_netlink.c' line='2283' column='1'/>
+        <parameter type-id='390fbe8f' name='nlh' filepath='net/netlink/af_netlink.c' line='2284' column='1'/>
+        <parameter type-id='6984e365' name='control' filepath='net/netlink/af_netlink.c' line='2285' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
       <function-type size-in-bits='64' id='64a9bab2'>
@@ -130561,22 +130842,22 @@
     <abi-instr address-size='64' path='net/socket.c' language='LANG_C89'>
       <pointer-type-def type-id='cd5915d8' size-in-bits='64' id='9c68341e'/>
       <pointer-type-def type-id='13103032' size-in-bits='64' id='1a7bb5c8'/>
-      <function-decl name='sock_alloc_file' mangled-name='sock_alloc_file' filepath='net/socket.c' line='399' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_alloc_file'>
-        <parameter type-id='13103032' name='sock' filepath='net/socket.c' line='399' column='1'/>
-        <parameter type-id='95e97e5e' name='flags' filepath='net/socket.c' line='399' column='1'/>
-        <parameter type-id='80f4b756' name='dname' filepath='net/socket.c' line='399' column='1'/>
+      <function-decl name='sock_alloc_file' mangled-name='sock_alloc_file' filepath='net/socket.c' line='407' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_alloc_file'>
+        <parameter type-id='13103032' name='sock' filepath='net/socket.c' line='407' column='1'/>
+        <parameter type-id='95e97e5e' name='flags' filepath='net/socket.c' line='407' column='1'/>
+        <parameter type-id='80f4b756' name='dname' filepath='net/socket.c' line='407' column='1'/>
         <return type-id='77e79a4b'/>
       </function-decl>
-      <function-decl name='sock_release' mangled-name='sock_release' filepath='net/socket.c' line='617' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_release'>
-        <parameter type-id='13103032' name='sock' filepath='net/socket.c' line='617' column='1'/>
+      <function-decl name='sock_release' mangled-name='sock_release' filepath='net/socket.c' line='625' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_release'>
+        <parameter type-id='13103032' name='sock' filepath='net/socket.c' line='625' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='kernel_sendmsg' mangled-name='kernel_sendmsg' filepath='net/socket.c' line='677' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='kernel_sendmsg'>
-        <parameter type-id='13103032' name='sock' filepath='net/socket.c' line='677' column='1'/>
-        <parameter type-id='6b9b777a' name='msg' filepath='net/socket.c' line='677' column='1'/>
-        <parameter type-id='9c68341e' name='vec' filepath='net/socket.c' line='678' column='1'/>
-        <parameter type-id='b59d7dce' name='num' filepath='net/socket.c' line='678' column='1'/>
-        <parameter type-id='b59d7dce' name='size' filepath='net/socket.c' line='678' column='1'/>
+      <function-decl name='kernel_sendmsg' mangled-name='kernel_sendmsg' filepath='net/socket.c' line='704' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='kernel_sendmsg'>
+        <parameter type-id='13103032' name='sock' filepath='net/socket.c' line='704' column='1'/>
+        <parameter type-id='6b9b777a' name='msg' filepath='net/socket.c' line='704' column='1'/>
+        <parameter type-id='9c68341e' name='vec' filepath='net/socket.c' line='705' column='1'/>
+        <parameter type-id='b59d7dce' name='num' filepath='net/socket.c' line='705' column='1'/>
+        <parameter type-id='b59d7dce' name='size' filepath='net/socket.c' line='705' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
       <function-decl name='put_cmsg' mangled-name='put_cmsg' filepath='include/linux/socket.h' line='349' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='put_cmsg'>
@@ -130587,69 +130868,69 @@
         <parameter type-id='eaa32e2f'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='__sock_recv_ts_and_drops' mangled-name='__sock_recv_ts_and_drops' filepath='net/socket.c' line='838' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__sock_recv_ts_and_drops'>
-        <parameter type-id='6b9b777a' name='msg' filepath='net/socket.c' line='838' column='1'/>
-        <parameter type-id='f772df6d' name='sk' filepath='net/socket.c' line='838' column='1'/>
-        <parameter type-id='0fbf3cfd' name='skb' filepath='net/socket.c' line='839' column='1'/>
+      <function-decl name='__sock_recv_ts_and_drops' mangled-name='__sock_recv_ts_and_drops' filepath='net/socket.c' line='865' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__sock_recv_ts_and_drops'>
+        <parameter type-id='6b9b777a' name='msg' filepath='net/socket.c' line='865' column='1'/>
+        <parameter type-id='f772df6d' name='sk' filepath='net/socket.c' line='865' column='1'/>
+        <parameter type-id='0fbf3cfd' name='skb' filepath='net/socket.c' line='866' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='kernel_recvmsg' mangled-name='kernel_recvmsg' filepath='net/socket.c' line='886' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='kernel_recvmsg'>
-        <parameter type-id='13103032' name='sock' filepath='net/socket.c' line='886' column='1'/>
-        <parameter type-id='6b9b777a' name='msg' filepath='net/socket.c' line='886' column='1'/>
-        <parameter type-id='9c68341e' name='vec' filepath='net/socket.c' line='887' column='1'/>
-        <parameter type-id='b59d7dce' name='num' filepath='net/socket.c' line='887' column='1'/>
-        <parameter type-id='b59d7dce' name='size' filepath='net/socket.c' line='887' column='1'/>
-        <parameter type-id='95e97e5e' name='flags' filepath='net/socket.c' line='887' column='1'/>
+      <function-decl name='kernel_recvmsg' mangled-name='kernel_recvmsg' filepath='net/socket.c' line='915' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='kernel_recvmsg'>
+        <parameter type-id='13103032' name='sock' filepath='net/socket.c' line='915' column='1'/>
+        <parameter type-id='6b9b777a' name='msg' filepath='net/socket.c' line='915' column='1'/>
+        <parameter type-id='9c68341e' name='vec' filepath='net/socket.c' line='916' column='1'/>
+        <parameter type-id='b59d7dce' name='num' filepath='net/socket.c' line='916' column='1'/>
+        <parameter type-id='b59d7dce' name='size' filepath='net/socket.c' line='916' column='1'/>
+        <parameter type-id='95e97e5e' name='flags' filepath='net/socket.c' line='916' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sock_wake_async' mangled-name='sock_wake_async' filepath='net/socket.c' line='1253' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_wake_async'>
-        <parameter type-id='99f34ac1' name='wq' filepath='net/socket.c' line='1253' column='1'/>
-        <parameter type-id='95e97e5e' name='how' filepath='net/socket.c' line='1253' column='1'/>
-        <parameter type-id='95e97e5e' name='band' filepath='net/socket.c' line='1253' column='1'/>
+      <function-decl name='sock_wake_async' mangled-name='sock_wake_async' filepath='net/socket.c' line='1282' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_wake_async'>
+        <parameter type-id='99f34ac1' name='wq' filepath='net/socket.c' line='1282' column='1'/>
+        <parameter type-id='95e97e5e' name='how' filepath='net/socket.c' line='1282' column='1'/>
+        <parameter type-id='95e97e5e' name='band' filepath='net/socket.c' line='1282' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sock_create' mangled-name='sock_create' filepath='net/socket.c' line='1414' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_create'>
-        <parameter type-id='95e97e5e' name='family' filepath='net/socket.c' line='1414' column='1'/>
-        <parameter type-id='95e97e5e' name='type' filepath='net/socket.c' line='1414' column='1'/>
-        <parameter type-id='95e97e5e' name='protocol' filepath='net/socket.c' line='1414' column='1'/>
-        <parameter type-id='1a7bb5c8' name='res' filepath='net/socket.c' line='1414' column='1'/>
+      <function-decl name='sock_create' mangled-name='sock_create' filepath='net/socket.c' line='1443' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_create'>
+        <parameter type-id='95e97e5e' name='family' filepath='net/socket.c' line='1443' column='1'/>
+        <parameter type-id='95e97e5e' name='type' filepath='net/socket.c' line='1443' column='1'/>
+        <parameter type-id='95e97e5e' name='protocol' filepath='net/socket.c' line='1443' column='1'/>
+        <parameter type-id='1a7bb5c8' name='res' filepath='net/socket.c' line='1443' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sock_create_kern' mangled-name='sock_create_kern' filepath='net/socket.c' line='1432' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_create_kern'>
-        <parameter type-id='a2bff676' name='net' filepath='net/socket.c' line='1432' column='1'/>
-        <parameter type-id='95e97e5e' name='family' filepath='net/socket.c' line='1432' column='1'/>
-        <parameter type-id='95e97e5e' name='type' filepath='net/socket.c' line='1432' column='1'/>
-        <parameter type-id='95e97e5e' name='protocol' filepath='net/socket.c' line='1432' column='1'/>
-        <parameter type-id='1a7bb5c8' name='res' filepath='net/socket.c' line='1432' column='1'/>
+      <function-decl name='sock_create_kern' mangled-name='sock_create_kern' filepath='net/socket.c' line='1461' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_create_kern'>
+        <parameter type-id='a2bff676' name='net' filepath='net/socket.c' line='1461' column='1'/>
+        <parameter type-id='95e97e5e' name='family' filepath='net/socket.c' line='1461' column='1'/>
+        <parameter type-id='95e97e5e' name='type' filepath='net/socket.c' line='1461' column='1'/>
+        <parameter type-id='95e97e5e' name='protocol' filepath='net/socket.c' line='1461' column='1'/>
+        <parameter type-id='1a7bb5c8' name='res' filepath='net/socket.c' line='1461' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sock_kmalloc' mangled-name='sock_kmalloc' filepath='include/net/sock.h' line='1632' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_kmalloc'>
+      <function-decl name='sock_kmalloc' mangled-name='sock_kmalloc' filepath='include/net/sock.h' line='1647' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_kmalloc'>
         <parameter type-id='f772df6d'/>
         <parameter type-id='95e97e5e'/>
         <parameter type-id='f0981eeb'/>
         <return type-id='eaa32e2f'/>
       </function-decl>
-      <function-decl name='kernel_connect' mangled-name='kernel_connect' filepath='net/socket.c' line='3468' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='kernel_connect'>
-        <parameter type-id='13103032' name='sock' filepath='net/socket.c' line='3468' column='1'/>
-        <parameter type-id='5c0abad8' name='addr' filepath='net/socket.c' line='3468' column='1'/>
-        <parameter type-id='95e97e5e' name='addrlen' filepath='net/socket.c' line='3468' column='1'/>
-        <parameter type-id='95e97e5e' name='flags' filepath='net/socket.c' line='3469' column='1'/>
+      <function-decl name='kernel_connect' mangled-name='kernel_connect' filepath='net/socket.c' line='3501' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='kernel_connect'>
+        <parameter type-id='13103032' name='sock' filepath='net/socket.c' line='3501' column='1'/>
+        <parameter type-id='5c0abad8' name='addr' filepath='net/socket.c' line='3501' column='1'/>
+        <parameter type-id='95e97e5e' name='addrlen' filepath='net/socket.c' line='3501' column='1'/>
+        <parameter type-id='95e97e5e' name='flags' filepath='net/socket.c' line='3502' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='kernel_getsockname' mangled-name='kernel_getsockname' filepath='net/socket.c' line='3484' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='kernel_getsockname'>
-        <parameter type-id='13103032' name='sock' filepath='net/socket.c' line='3484' column='1'/>
-        <parameter type-id='5c0abad8' name='addr' filepath='net/socket.c' line='3484' column='1'/>
+      <function-decl name='kernel_getsockname' mangled-name='kernel_getsockname' filepath='net/socket.c' line='3521' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='kernel_getsockname'>
+        <parameter type-id='13103032' name='sock' filepath='net/socket.c' line='3521' column='1'/>
+        <parameter type-id='5c0abad8' name='addr' filepath='net/socket.c' line='3521' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='kernel_setsockopt' mangled-name='kernel_setsockopt' filepath='net/socket.c' line='3550' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='kernel_setsockopt'>
-        <parameter type-id='13103032' name='sock' filepath='net/socket.c' line='3550' column='1'/>
-        <parameter type-id='95e97e5e' name='level' filepath='net/socket.c' line='3550' column='1'/>
-        <parameter type-id='95e97e5e' name='optname' filepath='net/socket.c' line='3550' column='1'/>
-        <parameter type-id='26a90f95' name='optval' filepath='net/socket.c' line='3551' column='1'/>
-        <parameter type-id='f0981eeb' name='optlen' filepath='net/socket.c' line='3551' column='1'/>
+      <function-decl name='kernel_setsockopt' mangled-name='kernel_setsockopt' filepath='net/socket.c' line='3587' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='kernel_setsockopt'>
+        <parameter type-id='13103032' name='sock' filepath='net/socket.c' line='3587' column='1'/>
+        <parameter type-id='95e97e5e' name='level' filepath='net/socket.c' line='3587' column='1'/>
+        <parameter type-id='95e97e5e' name='optname' filepath='net/socket.c' line='3587' column='1'/>
+        <parameter type-id='26a90f95' name='optval' filepath='net/socket.c' line='3588' column='1'/>
+        <parameter type-id='f0981eeb' name='optlen' filepath='net/socket.c' line='3588' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='sock_no_sendpage' mangled-name='sock_no_sendpage' filepath='include/net/sock.h' line='1673' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_sendpage'>
+      <function-decl name='sock_no_sendpage' mangled-name='sock_no_sendpage' filepath='include/net/sock.h' line='1688' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='sock_no_sendpage'>
         <parameter type-id='13103032'/>
         <parameter type-id='02f11ed4'/>
         <parameter type-id='95e97e5e'/>
@@ -130740,7 +131021,6 @@
           <var-decl name='prev_bssid_valid' type-id='b50a4934' visibility='default' filepath='net/wireless/sme.c' line='51' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='libipw_device' is-struct='yes' visibility='default' is-declaration-only='yes' id='9c91a761'/>
       <array-type-def dimensions='1' type-id='ec00acfb' size-in-bits='infinite' id='14cad687'>
         <subrange length='infinite' type-id='7ff19f0f' id='031f2035'/>
       </array-type-def>
@@ -130753,9 +131033,6 @@
       <array-type-def dimensions='1' type-id='86d70780' size-in-bits='256' id='00286dfe'>
         <subrange length='4' type-id='7ff19f0f' id='16fe7105'/>
       </array-type-def>
-      <array-type-def dimensions='1' type-id='aa80c027' size-in-bits='256' id='c73a16a3'>
-        <subrange length='8' type-id='7ff19f0f' id='56e0c0b1'/>
-      </array-type-def>
       <array-type-def dimensions='1' type-id='45947737' size-in-bits='1024' id='248874df'>
         <subrange length='4' type-id='7ff19f0f' id='16fe7105'/>
       </array-type-def>
@@ -130796,348 +131073,341 @@
       <array-type-def dimensions='1' type-id='f9b06939' size-in-bits='72' id='cef57087'>
         <subrange length='9' type-id='7ff19f0f' id='12e4273c'/>
       </array-type-def>
-      <array-type-def dimensions='1' type-id='b151a3a8' size-in-bits='64' id='4a744ea1'>
-        <subrange length='8' type-id='7ff19f0f' id='56e0c0b1'/>
-      </array-type-def>
-      <array-type-def dimensions='2' type-id='b151a3a8' size-in-bits='384' id='2d507faf'>
-        <subrange length='8' type-id='7ff19f0f' id='56e0c0b1'/>
-        <subrange length='6' type-id='7ff19f0f' id='52fa524b'/>
-      </array-type-def>
-      <class-decl name='wiphy' size-in-bits='11264' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='4154' column='1' id='68523a94'>
+      <class-decl name='wiphy' size-in-bits='11264' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='4157' column='1' id='68523a94'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='perm_addr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4158' column='1'/>
+          <var-decl name='perm_addr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4161' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='48'>
-          <var-decl name='addr_mask' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4159' column='1'/>
+          <var-decl name='addr_mask' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4162' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='addresses' type-id='01b378ab' visibility='default' filepath='include/net/cfg80211.h' line='4161' column='1'/>
+          <var-decl name='addresses' type-id='01b378ab' visibility='default' filepath='include/net/cfg80211.h' line='4164' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='mgmt_stypes' type-id='0cda9080' visibility='default' filepath='include/net/cfg80211.h' line='4163' column='1'/>
+          <var-decl name='mgmt_stypes' type-id='0cda9080' visibility='default' filepath='include/net/cfg80211.h' line='4166' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='iface_combinations' type-id='fa32a449' visibility='default' filepath='include/net/cfg80211.h' line='4165' column='1'/>
+          <var-decl name='iface_combinations' type-id='fa32a449' visibility='default' filepath='include/net/cfg80211.h' line='4168' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='n_iface_combinations' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4166' column='1'/>
+          <var-decl name='n_iface_combinations' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4169' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='352'>
-          <var-decl name='software_iftypes' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4167' column='1'/>
+          <var-decl name='software_iftypes' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4170' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='368'>
-          <var-decl name='n_addresses' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4169' column='1'/>
+          <var-decl name='n_addresses' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4172' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='interface_modes' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4172' column='1'/>
+          <var-decl name='interface_modes' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4175' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='400'>
-          <var-decl name='max_acl_mac_addrs' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4174' column='1'/>
+          <var-decl name='max_acl_mac_addrs' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4177' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='416'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4176' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4179' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='regulatory_flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4176' column='1'/>
+          <var-decl name='regulatory_flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4179' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='480'>
-          <var-decl name='features' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4176' column='1'/>
+          <var-decl name='features' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4179' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='ext_features' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4177' column='1'/>
+          <var-decl name='ext_features' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='4180' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='ap_sme_capa' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4179' column='1'/>
+          <var-decl name='ap_sme_capa' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4182' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='608'>
-          <var-decl name='signal_type' type-id='b8524648' visibility='default' filepath='include/net/cfg80211.h' line='4181' column='1'/>
+          <var-decl name='signal_type' type-id='b8524648' visibility='default' filepath='include/net/cfg80211.h' line='4184' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='bss_priv_size' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4183' column='1'/>
+          <var-decl name='bss_priv_size' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4186' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='672'>
-          <var-decl name='max_scan_ssids' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4184' column='1'/>
+          <var-decl name='max_scan_ssids' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4187' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='680'>
-          <var-decl name='max_sched_scan_reqs' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4185' column='1'/>
+          <var-decl name='max_sched_scan_reqs' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4188' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='688'>
-          <var-decl name='max_sched_scan_ssids' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4186' column='1'/>
+          <var-decl name='max_sched_scan_ssids' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4189' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='696'>
-          <var-decl name='max_match_sets' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4187' column='1'/>
+          <var-decl name='max_match_sets' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4190' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='max_scan_ie_len' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4188' column='1'/>
+          <var-decl name='max_scan_ie_len' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4191' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='720'>
-          <var-decl name='max_sched_scan_ie_len' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4189' column='1'/>
+          <var-decl name='max_sched_scan_ie_len' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4192' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='736'>
-          <var-decl name='max_sched_scan_plans' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4190' column='1'/>
+          <var-decl name='max_sched_scan_plans' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4193' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='max_sched_scan_plan_interval' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4191' column='1'/>
+          <var-decl name='max_sched_scan_plan_interval' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4194' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='800'>
-          <var-decl name='max_sched_scan_plan_iterations' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4192' column='1'/>
+          <var-decl name='max_sched_scan_plan_iterations' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4195' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='n_cipher_suites' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4194' column='1'/>
+          <var-decl name='n_cipher_suites' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4197' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='cipher_suites' type-id='aded214c' visibility='default' filepath='include/net/cfg80211.h' line='4195' column='1'/>
+          <var-decl name='cipher_suites' type-id='aded214c' visibility='default' filepath='include/net/cfg80211.h' line='4198' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='iftype_akm_suites' type-id='6196d741' visibility='default' filepath='include/net/cfg80211.h' line='4197' column='1'/>
+          <var-decl name='iftype_akm_suites' type-id='6196d741' visibility='default' filepath='include/net/cfg80211.h' line='4200' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='num_iftype_akm_suites' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='4198' column='1'/>
+          <var-decl name='num_iftype_akm_suites' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='4201' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1056'>
-          <var-decl name='retry_short' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4200' column='1'/>
+          <var-decl name='retry_short' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4203' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1064'>
-          <var-decl name='retry_long' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4201' column='1'/>
+          <var-decl name='retry_long' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4204' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='frag_threshold' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4202' column='1'/>
+          <var-decl name='frag_threshold' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4205' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1120'>
-          <var-decl name='rts_threshold' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4203' column='1'/>
+          <var-decl name='rts_threshold' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4206' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='coverage_class' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4204' column='1'/>
+          <var-decl name='coverage_class' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4207' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1160'>
-          <var-decl name='fw_version' type-id='16dc656a' visibility='default' filepath='include/net/cfg80211.h' line='4206' column='1'/>
+          <var-decl name='fw_version' type-id='16dc656a' visibility='default' filepath='include/net/cfg80211.h' line='4209' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1440'>
-          <var-decl name='hw_version' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4207' column='1'/>
+          <var-decl name='hw_version' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4210' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1472'>
-          <var-decl name='wowlan' type-id='78a34b70' visibility='default' filepath='include/net/cfg80211.h' line='4210' column='1'/>
+          <var-decl name='wowlan' type-id='78a34b70' visibility='default' filepath='include/net/cfg80211.h' line='4213' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='wowlan_config' type-id='9d025b00' visibility='default' filepath='include/net/cfg80211.h' line='4211' column='1'/>
+          <var-decl name='wowlan_config' type-id='9d025b00' visibility='default' filepath='include/net/cfg80211.h' line='4214' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1600'>
-          <var-decl name='max_remain_on_channel_duration' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4214' column='1'/>
+          <var-decl name='max_remain_on_channel_duration' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4217' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1616'>
-          <var-decl name='max_num_pmkids' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4216' column='1'/>
+          <var-decl name='max_num_pmkids' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4219' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1632'>
-          <var-decl name='available_antennas_tx' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4218' column='1'/>
+          <var-decl name='available_antennas_tx' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4221' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1664'>
-          <var-decl name='available_antennas_rx' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4219' column='1'/>
+          <var-decl name='available_antennas_rx' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4222' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1696'>
-          <var-decl name='probe_resp_offload' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4226' column='1'/>
+          <var-decl name='probe_resp_offload' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4229' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1728'>
-          <var-decl name='extended_capabilities' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='4228' column='1'/>
+          <var-decl name='extended_capabilities' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='4231' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1792'>
-          <var-decl name='extended_capabilities_mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='4228' column='1'/>
+          <var-decl name='extended_capabilities_mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='4231' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='extended_capabilities_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4229' column='1'/>
+          <var-decl name='extended_capabilities_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4232' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1920'>
-          <var-decl name='iftype_ext_capab' type-id='3ca25343' visibility='default' filepath='include/net/cfg80211.h' line='4231' column='1'/>
+          <var-decl name='iftype_ext_capab' type-id='3ca25343' visibility='default' filepath='include/net/cfg80211.h' line='4234' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1984'>
-          <var-decl name='num_iftype_ext_capab' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='4232' column='1'/>
+          <var-decl name='num_iftype_ext_capab' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='4235' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='privid' type-id='eaa32e2f' visibility='default' filepath='include/net/cfg80211.h' line='4239' column='1'/>
+          <var-decl name='privid' type-id='eaa32e2f' visibility='default' filepath='include/net/cfg80211.h' line='4242' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='bands' type-id='640b99c7' visibility='default' filepath='include/net/cfg80211.h' line='4241' column='1'/>
+          <var-decl name='bands' type-id='640b99c7' visibility='default' filepath='include/net/cfg80211.h' line='4244' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2304'>
-          <var-decl name='reg_notifier' type-id='39ee8359' visibility='default' filepath='include/net/cfg80211.h' line='4244' column='1'/>
+          <var-decl name='reg_notifier' type-id='39ee8359' visibility='default' filepath='include/net/cfg80211.h' line='4247' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2368'>
-          <var-decl name='regd' type-id='4e819401' visibility='default' filepath='include/net/cfg80211.h' line='4249' column='1'/>
+          <var-decl name='regd' type-id='4e819401' visibility='default' filepath='include/net/cfg80211.h' line='4252' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2432'>
-          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/net/cfg80211.h' line='4253' column='1'/>
+          <var-decl name='dev' type-id='66e487eb' visibility='default' filepath='include/net/cfg80211.h' line='4256' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10048'>
-          <var-decl name='registered' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4256' column='1'/>
+          <var-decl name='registered' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='4259' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10112'>
-          <var-decl name='debugfsdir' type-id='27675065' visibility='default' filepath='include/net/cfg80211.h' line='4259' column='1'/>
+          <var-decl name='debugfsdir' type-id='27675065' visibility='default' filepath='include/net/cfg80211.h' line='4262' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10176'>
-          <var-decl name='ht_capa_mod_mask' type-id='81f1a1a8' visibility='default' filepath='include/net/cfg80211.h' line='4261' column='1'/>
+          <var-decl name='ht_capa_mod_mask' type-id='81f1a1a8' visibility='default' filepath='include/net/cfg80211.h' line='4264' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10240'>
-          <var-decl name='vht_capa_mod_mask' type-id='fffb07a4' visibility='default' filepath='include/net/cfg80211.h' line='4262' column='1'/>
+          <var-decl name='vht_capa_mod_mask' type-id='fffb07a4' visibility='default' filepath='include/net/cfg80211.h' line='4265' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10304'>
-          <var-decl name='wdev_list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4264' column='1'/>
+          <var-decl name='wdev_list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='4267' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10432'>
-          <var-decl name='_net' type-id='c9df1e6c' visibility='default' filepath='include/net/cfg80211.h' line='4267' column='1'/>
+          <var-decl name='_net' type-id='c9df1e6c' visibility='default' filepath='include/net/cfg80211.h' line='4270' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10496'>
-          <var-decl name='coalesce' type-id='9ef499bf' visibility='default' filepath='include/net/cfg80211.h' line='4273' column='1'/>
+          <var-decl name='coalesce' type-id='9ef499bf' visibility='default' filepath='include/net/cfg80211.h' line='4276' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10560'>
-          <var-decl name='vendor_commands' type-id='41e3f782' visibility='default' filepath='include/net/cfg80211.h' line='4275' column='1'/>
+          <var-decl name='vendor_commands' type-id='41e3f782' visibility='default' filepath='include/net/cfg80211.h' line='4278' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10624'>
-          <var-decl name='vendor_events' type-id='b188cc4f' visibility='default' filepath='include/net/cfg80211.h' line='4276' column='1'/>
+          <var-decl name='vendor_events' type-id='b188cc4f' visibility='default' filepath='include/net/cfg80211.h' line='4279' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10688'>
-          <var-decl name='n_vendor_commands' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4277' column='1'/>
+          <var-decl name='n_vendor_commands' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4280' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10720'>
-          <var-decl name='n_vendor_events' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4277' column='1'/>
+          <var-decl name='n_vendor_events' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='4280' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10752'>
-          <var-decl name='max_ap_assoc_sta' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4279' column='1'/>
+          <var-decl name='max_ap_assoc_sta' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='4282' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10768'>
-          <var-decl name='max_num_csa_counters' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4281' column='1'/>
+          <var-decl name='max_num_csa_counters' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4284' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10776'>
-          <var-decl name='max_adj_channel_rssi_comp' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4282' column='1'/>
+          <var-decl name='max_adj_channel_rssi_comp' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4285' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10784'>
-          <var-decl name='bss_select_support' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4284' column='1'/>
+          <var-decl name='bss_select_support' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4287' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10816'>
-          <var-decl name='cookie_counter' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='4286' column='1'/>
+          <var-decl name='cookie_counter' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='4289' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10880'>
-          <var-decl name='nan_supported_bands' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4288' column='1'/>
+          <var-decl name='nan_supported_bands' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4291' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10912'>
-          <var-decl name='txq_limit' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4290' column='1'/>
+          <var-decl name='txq_limit' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4293' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10944'>
-          <var-decl name='txq_memory_limit' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4291' column='1'/>
+          <var-decl name='txq_memory_limit' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4294' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='10976'>
-          <var-decl name='txq_quantum' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4292' column='1'/>
+          <var-decl name='txq_quantum' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='4295' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='support_mbssid' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4294' column='1'/>
+          <var-decl name='support_mbssid' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4297' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1'>
-          <var-decl name='support_only_he_mbssid' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4295' column='1'/>
+          <var-decl name='support_only_he_mbssid' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='4298' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='11264'>
-          <var-decl name='priv' type-id='e84913bd' visibility='default' filepath='include/net/cfg80211.h' line='4297' column='1'/>
+          <var-decl name='priv' type-id='e84913bd' visibility='default' filepath='include/net/cfg80211.h' line='4300' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='mac_address' size-in-bits='48' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='870' column='1' id='6d8d26fb'>
+      <class-decl name='mac_address' size-in-bits='48' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='873' column='1' id='6d8d26fb'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='addr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='871' column='1'/>
+          <var-decl name='addr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='874' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='ieee80211_txrx_stypes' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3793' column='1' id='21301fc9'>
+      <class-decl name='ieee80211_txrx_stypes' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3796' column='1' id='21301fc9'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='tx' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3794' column='1'/>
+          <var-decl name='tx' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3797' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='rx' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3794' column='1'/>
+          <var-decl name='rx' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3797' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='ieee80211_iface_combination' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3735' column='1' id='1179f27e'>
+      <class-decl name='ieee80211_iface_combination' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3738' column='1' id='1179f27e'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='limits' type-id='2fde6795' visibility='default' filepath='include/net/cfg80211.h' line='3740' column='1'/>
+          <var-decl name='limits' type-id='2fde6795' visibility='default' filepath='include/net/cfg80211.h' line='3743' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='num_different_channels' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3746' column='1'/>
+          <var-decl name='num_different_channels' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3749' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='max_interfaces' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3752' column='1'/>
+          <var-decl name='max_interfaces' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3755' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='112'>
-          <var-decl name='n_limits' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3758' column='1'/>
+          <var-decl name='n_limits' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3761' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='120'>
-          <var-decl name='beacon_int_infra_match' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='3765' column='1'/>
+          <var-decl name='beacon_int_infra_match' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='3768' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='radar_detect_widths' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3771' column='1'/>
+          <var-decl name='radar_detect_widths' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3774' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='136'>
-          <var-decl name='radar_detect_regions' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3777' column='1'/>
+          <var-decl name='radar_detect_regions' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3780' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='beacon_int_min_gcd' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3790' column='1'/>
+          <var-decl name='beacon_int_min_gcd' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3793' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='ieee80211_iface_limit' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3671' column='1' id='e47a5a92'>
+      <class-decl name='ieee80211_iface_limit' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3674' column='1' id='e47a5a92'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='max' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3672' column='1'/>
+          <var-decl name='max' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3675' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='types' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3673' column='1'/>
+          <var-decl name='types' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3676' column='1'/>
         </data-member>
       </class-decl>
-      <enum-decl name='cfg80211_signal_type' filepath='include/net/cfg80211.h' line='2004' column='1' id='b8524648'>
+      <enum-decl name='cfg80211_signal_type' filepath='include/net/cfg80211.h' line='2007' column='1' id='b8524648'>
         <underlying-type type-id='9cac1fee'/>
         <enumerator name='CFG80211_SIGNAL_TYPE_NONE' value='0'/>
         <enumerator name='CFG80211_SIGNAL_TYPE_MBM' value='1'/>
         <enumerator name='CFG80211_SIGNAL_TYPE_UNSPEC' value='2'/>
       </enum-decl>
-      <class-decl name='wiphy_iftype_akm_suites' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3971' column='1' id='c86a8a16'>
+      <class-decl name='wiphy_iftype_akm_suites' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3974' column='1' id='c86a8a16'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='iftypes_mask' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3972' column='1'/>
+          <var-decl name='iftypes_mask' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='3975' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='akm_suites' type-id='aded214c' visibility='default' filepath='include/net/cfg80211.h' line='3973' column='1'/>
+          <var-decl name='akm_suites' type-id='aded214c' visibility='default' filepath='include/net/cfg80211.h' line='3976' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='n_akm_suites' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3974' column='1'/>
+          <var-decl name='n_akm_suites' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3977' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wiphy_wowlan_support' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3849' column='1' id='5bbd300b'>
+      <class-decl name='wiphy_wowlan_support' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3852' column='1' id='5bbd300b'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3850' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3853' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='n_patterns' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3851' column='1'/>
+          <var-decl name='n_patterns' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3854' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='pattern_max_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3852' column='1'/>
+          <var-decl name='pattern_max_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3855' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='pattern_min_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3853' column='1'/>
+          <var-decl name='pattern_min_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3856' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='max_pkt_offset' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3854' column='1'/>
+          <var-decl name='max_pkt_offset' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3857' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='max_nd_match_sets' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3855' column='1'/>
+          <var-decl name='max_nd_match_sets' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3858' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='tcp' type-id='b3ebc0a8' visibility='default' filepath='include/net/cfg80211.h' line='3856' column='1'/>
+          <var-decl name='tcp' type-id='b3ebc0a8' visibility='default' filepath='include/net/cfg80211.h' line='3859' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wiphy_wowlan_tcp_support' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3826' column='1' id='557bca33'>
+      <class-decl name='wiphy_wowlan_tcp_support' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3829' column='1' id='557bca33'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='tok' type-id='6a8cbf59' visibility='default' filepath='include/net/cfg80211.h' line='3827' column='1'/>
+          <var-decl name='tok' type-id='6a8cbf59' visibility='default' filepath='include/net/cfg80211.h' line='3830' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='data_payload_max' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3828' column='1'/>
+          <var-decl name='data_payload_max' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3831' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='data_interval_max' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3829' column='1'/>
+          <var-decl name='data_interval_max' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3832' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='wake_payload_max' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3830' column='1'/>
+          <var-decl name='wake_payload_max' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3833' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='seq' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='3831' column='1'/>
+          <var-decl name='seq' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='3834' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='nl80211_wowlan_tcp_data_token_feature' size-in-bits='96' is-struct='yes' visibility='default' filepath='include/uapi/linux/nl80211.h' line='4831' column='1' id='0dd56ffa'>
@@ -131151,100 +131421,100 @@
           <var-decl name='bufsize' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/nl80211.h' line='4832' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_wowlan' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2575' column='1' id='80126e32'>
+      <class-decl name='cfg80211_wowlan' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2578' column='1' id='80126e32'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='any' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2576' column='1'/>
+          <var-decl name='any' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2579' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8'>
-          <var-decl name='disconnect' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2576' column='1'/>
+          <var-decl name='disconnect' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2579' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='magic_pkt' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2576' column='1'/>
+          <var-decl name='magic_pkt' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2579' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='24'>
-          <var-decl name='gtk_rekey_failure' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2576' column='1'/>
+          <var-decl name='gtk_rekey_failure' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2579' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='eap_identity_req' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2577' column='1'/>
+          <var-decl name='eap_identity_req' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2580' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='40'>
-          <var-decl name='four_way_handshake' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2577' column='1'/>
+          <var-decl name='four_way_handshake' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2580' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='48'>
-          <var-decl name='rfkill_release' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2578' column='1'/>
+          <var-decl name='rfkill_release' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2581' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='patterns' type-id='1ed3660c' visibility='default' filepath='include/net/cfg80211.h' line='2579' column='1'/>
+          <var-decl name='patterns' type-id='1ed3660c' visibility='default' filepath='include/net/cfg80211.h' line='2582' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='tcp' type-id='e0c1c1b8' visibility='default' filepath='include/net/cfg80211.h' line='2580' column='1'/>
+          <var-decl name='tcp' type-id='e0c1c1b8' visibility='default' filepath='include/net/cfg80211.h' line='2583' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='n_patterns' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2581' column='1'/>
+          <var-decl name='n_patterns' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2584' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='nd_config' type-id='9e4995c7' visibility='default' filepath='include/net/cfg80211.h' line='2582' column='1'/>
+          <var-decl name='nd_config' type-id='9e4995c7' visibility='default' filepath='include/net/cfg80211.h' line='2585' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_pkt_pattern' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2516' column='1' id='76959226'>
+      <class-decl name='cfg80211_pkt_pattern' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2519' column='1' id='76959226'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2517' column='1'/>
+          <var-decl name='mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2520' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='pattern' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2517' column='1'/>
+          <var-decl name='pattern' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2520' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='pattern_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2518' column='1'/>
+          <var-decl name='pattern_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2521' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='pkt_offset' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2519' column='1'/>
+          <var-decl name='pkt_offset' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2522' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_wowlan_tcp' size-in-bits='768' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2541' column='1' id='1752769a'>
+      <class-decl name='cfg80211_wowlan_tcp' size-in-bits='768' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2544' column='1' id='1752769a'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='sock' type-id='13103032' visibility='default' filepath='include/net/cfg80211.h' line='2542' column='1'/>
+          <var-decl name='sock' type-id='13103032' visibility='default' filepath='include/net/cfg80211.h' line='2545' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='src' type-id='78a133c2' visibility='default' filepath='include/net/cfg80211.h' line='2543' column='1'/>
+          <var-decl name='src' type-id='78a133c2' visibility='default' filepath='include/net/cfg80211.h' line='2546' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='dst' type-id='78a133c2' visibility='default' filepath='include/net/cfg80211.h' line='2543' column='1'/>
+          <var-decl name='dst' type-id='78a133c2' visibility='default' filepath='include/net/cfg80211.h' line='2546' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='src_port' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2544' column='1'/>
+          <var-decl name='src_port' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2547' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='144'>
-          <var-decl name='dst_port' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2544' column='1'/>
+          <var-decl name='dst_port' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2547' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='dst_mac' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2545' column='1'/>
+          <var-decl name='dst_mac' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2548' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='224'>
-          <var-decl name='payload_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2546' column='1'/>
+          <var-decl name='payload_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2549' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='payload' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2547' column='1'/>
+          <var-decl name='payload' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2550' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='payload_seq' type-id='d5a1b375' visibility='default' filepath='include/net/cfg80211.h' line='2548' column='1'/>
+          <var-decl name='payload_seq' type-id='d5a1b375' visibility='default' filepath='include/net/cfg80211.h' line='2551' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='416'>
-          <var-decl name='data_interval' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2549' column='1'/>
+          <var-decl name='data_interval' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2552' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='wake_len' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2550' column='1'/>
+          <var-decl name='wake_len' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2553' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='wake_data' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2551' column='1'/>
+          <var-decl name='wake_data' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2554' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='wake_mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2551' column='1'/>
+          <var-decl name='wake_mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2554' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='tokens_size' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2552' column='1'/>
+          <var-decl name='tokens_size' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2555' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='672'>
-          <var-decl name='payload_tok' type-id='2868c21b' visibility='default' filepath='include/net/cfg80211.h' line='2554' column='1'/>
+          <var-decl name='payload_tok' type-id='2868c21b' visibility='default' filepath='include/net/cfg80211.h' line='2557' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='nl80211_wowlan_tcp_data_seq' size-in-bits='96' is-struct='yes' visibility='default' filepath='include/uapi/linux/nl80211.h' line='4809' column='1' id='d5a1b375'>
@@ -131269,98 +131539,98 @@
           <var-decl name='token_stream' type-id='167619f6' visibility='default' filepath='include/uapi/linux/nl80211.h' line='4822' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_sched_scan_request' size-in-bits='1536' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1960' column='1' id='12a2e88f'>
+      <class-decl name='cfg80211_sched_scan_request' size-in-bits='1536' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1963' column='1' id='12a2e88f'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='reqid' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1961' column='1'/>
+          <var-decl name='reqid' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1964' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='ssids' type-id='a1fa7fb7' visibility='default' filepath='include/net/cfg80211.h' line='1962' column='1'/>
+          <var-decl name='ssids' type-id='a1fa7fb7' visibility='default' filepath='include/net/cfg80211.h' line='1965' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='n_ssids' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1963' column='1'/>
+          <var-decl name='n_ssids' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1966' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='n_channels' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1964' column='1'/>
+          <var-decl name='n_channels' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1967' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='scan_width' type-id='95d46034' visibility='default' filepath='include/net/cfg80211.h' line='1965' column='1'/>
+          <var-decl name='scan_width' type-id='95d46034' visibility='default' filepath='include/net/cfg80211.h' line='1968' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1966' column='1'/>
+          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1969' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='1967' column='1'/>
+          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='1970' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1968' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1971' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='match_sets' type-id='ea00c914' visibility='default' filepath='include/net/cfg80211.h' line='1969' column='1'/>
+          <var-decl name='match_sets' type-id='ea00c914' visibility='default' filepath='include/net/cfg80211.h' line='1972' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='n_match_sets' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1970' column='1'/>
+          <var-decl name='n_match_sets' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1973' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='544'>
-          <var-decl name='min_rssi_thold' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='1971' column='1'/>
+          <var-decl name='min_rssi_thold' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='1974' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='delay' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1972' column='1'/>
+          <var-decl name='delay' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1975' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='scan_plans' type-id='302e9391' visibility='default' filepath='include/net/cfg80211.h' line='1973' column='1'/>
+          <var-decl name='scan_plans' type-id='302e9391' visibility='default' filepath='include/net/cfg80211.h' line='1976' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='n_scan_plans' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1974' column='1'/>
+          <var-decl name='n_scan_plans' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1977' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='736'>
-          <var-decl name='mac_addr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1976' column='1'/>
+          <var-decl name='mac_addr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1979' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='784'>
-          <var-decl name='mac_addr_mask' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1977' column='1'/>
+          <var-decl name='mac_addr_mask' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1980' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='relative_rssi_set' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1979' column='1'/>
+          <var-decl name='relative_rssi_set' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1982' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='840'>
-          <var-decl name='relative_rssi' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1980' column='1'/>
+          <var-decl name='relative_rssi' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1983' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='864'>
-          <var-decl name='rssi_adjust' type-id='5da08e25' visibility='default' filepath='include/net/cfg80211.h' line='1981' column='1'/>
+          <var-decl name='rssi_adjust' type-id='5da08e25' visibility='default' filepath='include/net/cfg80211.h' line='1984' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='wiphy' type-id='666fb412' visibility='default' filepath='include/net/cfg80211.h' line='1984' column='1'/>
+          <var-decl name='wiphy' type-id='666fb412' visibility='default' filepath='include/net/cfg80211.h' line='1987' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='dev' type-id='68a2d05b' visibility='default' filepath='include/net/cfg80211.h' line='1985' column='1'/>
+          <var-decl name='dev' type-id='68a2d05b' visibility='default' filepath='include/net/cfg80211.h' line='1988' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='scan_start' type-id='7359adad' visibility='default' filepath='include/net/cfg80211.h' line='1986' column='1'/>
+          <var-decl name='scan_start' type-id='7359adad' visibility='default' filepath='include/net/cfg80211.h' line='1989' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='report_results' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1987' column='1'/>
+          <var-decl name='report_results' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1990' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='callback_head' type-id='e3d8ce29' visibility='default' filepath='include/net/cfg80211.h' line='1988' column='1'/>
+          <var-decl name='callback_head' type-id='e3d8ce29' visibility='default' filepath='include/net/cfg80211.h' line='1991' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='owner_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1989' column='1'/>
+          <var-decl name='owner_nlportid' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1992' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1376'>
-          <var-decl name='nl_owner_dead' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1990' column='1'/>
+          <var-decl name='nl_owner_dead' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1993' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='1991' column='1'/>
+          <var-decl name='list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='1994' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='channels' type-id='14cad687' visibility='default' filepath='include/net/cfg80211.h' line='1994' column='1'/>
+          <var-decl name='channels' type-id='14cad687' visibility='default' filepath='include/net/cfg80211.h' line='1997' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_ssid' size-in-bits='264' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1780' column='1' id='0c960fcf'>
+      <class-decl name='cfg80211_ssid' size-in-bits='264' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1783' column='1' id='0c960fcf'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='ssid' type-id='e3dc4fdb' visibility='default' filepath='include/net/cfg80211.h' line='1781' column='1'/>
+          <var-decl name='ssid' type-id='e3dc4fdb' visibility='default' filepath='include/net/cfg80211.h' line='1784' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ssid_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1782' column='1'/>
+          <var-decl name='ssid_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1785' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_bss_scan_width' filepath='include/uapi/linux/nl80211.h' line='4224' column='1' id='95d46034'>
@@ -131369,31 +131639,31 @@
         <enumerator name='NL80211_BSS_CHAN_WIDTH_10' value='1'/>
         <enumerator name='NL80211_BSS_CHAN_WIDTH_5' value='2'/>
       </enum-decl>
-      <class-decl name='cfg80211_match_set' size-in-bits='352' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1879' column='1' id='7430554e'>
+      <class-decl name='cfg80211_match_set' size-in-bits='352' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1882' column='1' id='7430554e'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='ssid' type-id='0c960fcf' visibility='default' filepath='include/net/cfg80211.h' line='1880' column='1'/>
+          <var-decl name='ssid' type-id='0c960fcf' visibility='default' filepath='include/net/cfg80211.h' line='1883' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='264'>
-          <var-decl name='bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1881' column='1'/>
+          <var-decl name='bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1884' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='rssi_thold' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='1882' column='1'/>
+          <var-decl name='rssi_thold' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='1885' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_sched_scan_plan' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1894' column='1' id='391881a9'>
+      <class-decl name='cfg80211_sched_scan_plan' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1897' column='1' id='391881a9'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='interval' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1895' column='1'/>
+          <var-decl name='interval' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1898' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='iterations' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1896' column='1'/>
+          <var-decl name='iterations' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1899' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_bss_select_adjust' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1905' column='1' id='5da08e25'>
+      <class-decl name='cfg80211_bss_select_adjust' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1908' column='1' id='5da08e25'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='band' type-id='3eaa0294' visibility='default' filepath='include/net/cfg80211.h' line='1906' column='1'/>
+          <var-decl name='band' type-id='3eaa0294' visibility='default' filepath='include/net/cfg80211.h' line='1909' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='delta' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1907' column='1'/>
+          <var-decl name='delta' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1910' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_band' filepath='include/uapi/linux/nl80211.h' line='4505' column='1' id='3eaa0294'>
@@ -131403,195 +131673,6 @@
         <enumerator name='NL80211_BAND_60GHZ' value='2'/>
         <enumerator name='NUM_NL80211_BANDS' value='3'/>
       </enum-decl>
-      <union-decl name='iwreq_data' size-in-bits='128' visibility='default' filepath='include/uapi/linux/wireless.h' line='902' column='1' id='ed626d0d'>
-        <data-member access='public'>
-          <var-decl name='name' type-id='ac1fa8c0' visibility='default' filepath='include/uapi/linux/wireless.h' line='904' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='essid' type-id='db4e746c' visibility='default' filepath='include/uapi/linux/wireless.h' line='908' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='nwid' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='909' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='freq' type-id='bc1ac22c' visibility='default' filepath='include/uapi/linux/wireless.h' line='910' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='sens' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='914' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='bitrate' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='915' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='txpower' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='916' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='rts' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='917' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='frag' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='918' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='mode' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='919' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='retry' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='920' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='encoding' type-id='db4e746c' visibility='default' filepath='include/uapi/linux/wireless.h' line='922' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='power' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='923' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='qual' type-id='aa80c027' visibility='default' filepath='include/uapi/linux/wireless.h' line='924' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='ap_addr' type-id='5221b18a' visibility='default' filepath='include/uapi/linux/wireless.h' line='926' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='addr' type-id='5221b18a' visibility='default' filepath='include/uapi/linux/wireless.h' line='927' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='param' type-id='b024252b' visibility='default' filepath='include/uapi/linux/wireless.h' line='929' column='1'/>
-        </data-member>
-        <data-member access='public'>
-          <var-decl name='data' type-id='db4e746c' visibility='default' filepath='include/uapi/linux/wireless.h' line='930' column='1'/>
-        </data-member>
-      </union-decl>
-      <typedef-decl name='iw_handler' type-id='2c8ff697' filepath='include/net/iw_handler.h' line='315' column='1' id='bcc5cab3'/>
-      <class-decl name='iw_request_info' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/net/iw_handler.h' line='304' column='1' id='e90b3b44'>
-        <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='cmd' type-id='d315442e' visibility='default' filepath='include/net/iw_handler.h' line='305' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='flags' type-id='d315442e' visibility='default' filepath='include/net/iw_handler.h' line='306' column='1'/>
-        </data-member>
-      </class-decl>
-      <class-decl name='iw_point' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='691' column='1' id='db4e746c'>
-        <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='pointer' type-id='eaa32e2f' visibility='default' filepath='include/uapi/linux/wireless.h' line='692' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='length' type-id='d315442e' visibility='default' filepath='include/uapi/linux/wireless.h' line='693' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='80'>
-          <var-decl name='flags' type-id='d315442e' visibility='default' filepath='include/uapi/linux/wireless.h' line='694' column='1'/>
-        </data-member>
-      </class-decl>
-      <class-decl name='iw_param' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='680' column='1' id='b024252b'>
-        <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='value' type-id='3158a266' visibility='default' filepath='include/uapi/linux/wireless.h' line='681' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='fixed' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='682' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='40'>
-          <var-decl name='disabled' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='683' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='48'>
-          <var-decl name='flags' type-id='d315442e' visibility='default' filepath='include/uapi/linux/wireless.h' line='684' column='1'/>
-        </data-member>
-      </class-decl>
-      <class-decl name='iw_freq' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='706' column='1' id='bc1ac22c'>
-        <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='m' type-id='3158a266' visibility='default' filepath='include/uapi/linux/wireless.h' line='707' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='e' type-id='b55def60' visibility='default' filepath='include/uapi/linux/wireless.h' line='708' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='48'>
-          <var-decl name='i' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='709' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='56'>
-          <var-decl name='flags' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='710' column='1'/>
-        </data-member>
-      </class-decl>
-      <class-decl name='iw_quality' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='716' column='1' id='aa80c027'>
-        <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='qual' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='717' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='8'>
-          <var-decl name='level' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='719' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='noise' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='720' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='24'>
-          <var-decl name='updated' type-id='8f048e17' visibility='default' filepath='include/uapi/linux/wireless.h' line='721' column='1'/>
-        </data-member>
-      </class-decl>
-      <class-decl name='iw_priv_args' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='1063' column='1' id='0c842ad9'>
-        <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='cmd' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='1064' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='set_args' type-id='d315442e' visibility='default' filepath='include/uapi/linux/wireless.h' line='1065' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='48'>
-          <var-decl name='get_args' type-id='d315442e' visibility='default' filepath='include/uapi/linux/wireless.h' line='1066' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='name' type-id='ac1fa8c0' visibility='default' filepath='include/uapi/linux/wireless.h' line='1067' column='1'/>
-        </data-member>
-      </class-decl>
-      <class-decl name='iw_statistics' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='881' column='1' id='1c8cc2fd'>
-        <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='status' type-id='d315442e' visibility='default' filepath='include/uapi/linux/wireless.h' line='882' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='qual' type-id='aa80c027' visibility='default' filepath='include/uapi/linux/wireless.h' line='885' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='discard' type-id='832938ed' visibility='default' filepath='include/uapi/linux/wireless.h' line='887' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='224'>
-          <var-decl name='miss' type-id='6a2a3473' visibility='default' filepath='include/uapi/linux/wireless.h' line='888' column='1'/>
-        </data-member>
-      </class-decl>
-      <class-decl name='iw_discarded' size-in-bits='160' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='731' column='1' id='832938ed'>
-        <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='nwid' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='732' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='code' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='733' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='fragment' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='734' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='retries' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='735' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='misc' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='736' column='1'/>
-        </data-member>
-      </class-decl>
-      <class-decl name='iw_missed' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/uapi/linux/wireless.h' line='743' column='1' id='6a2a3473'>
-        <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='beacon' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/wireless.h' line='744' column='1'/>
-        </data-member>
-      </class-decl>
-      <class-decl name='iw_spy_data' size-in-bits='800' is-struct='yes' visibility='default' filepath='include/net/iw_handler.h' line='396' column='1' id='f8292115'>
-        <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='spy_number' type-id='95e97e5e' visibility='default' filepath='include/net/iw_handler.h' line='398' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='spy_address' type-id='2d507faf' visibility='default' filepath='include/net/iw_handler.h' line='399' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='416'>
-          <var-decl name='spy_stat' type-id='c73a16a3' visibility='default' filepath='include/net/iw_handler.h' line='400' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='672'>
-          <var-decl name='spy_thr_low' type-id='aa80c027' visibility='default' filepath='include/net/iw_handler.h' line='402' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='spy_thr_high' type-id='aa80c027' visibility='default' filepath='include/net/iw_handler.h' line='403' column='1'/>
-        </data-member>
-        <data-member access='public' layout-offset-in-bits='736'>
-          <var-decl name='spy_thr_under' type-id='4a744ea1' visibility='default' filepath='include/net/iw_handler.h' line='404' column='1'/>
-        </data-member>
-      </class-decl>
-      <typedef-decl name='u_char' type-id='002ac4a6' filepath='include/linux/types.h' line='84' column='1' id='b151a3a8'/>
       <enum-decl name='nl80211_iftype' filepath='include/uapi/linux/nl80211.h' line='2912' column='1' id='86505f90'>
         <underlying-type type-id='9cac1fee'/>
         <enumerator name='NL80211_IFTYPE_UNSPECIFIED' value='0'/>
@@ -131621,21 +131702,21 @@
           <var-decl name='def' type-id='95e97e5e' visibility='default' filepath='net/wireless/core.h' line='261' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='key_params' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='548' column='1' id='45947737'>
+      <class-decl name='key_params' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='551' column='1' id='45947737'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='key' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='549' column='1'/>
+          <var-decl name='key' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='552' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='seq' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='550' column='1'/>
+          <var-decl name='seq' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='553' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='key_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='551' column='1'/>
+          <var-decl name='key_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='554' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='seq_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='552' column='1'/>
+          <var-decl name='seq_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='555' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='cipher' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='553' column='1'/>
+          <var-decl name='cipher' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='556' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='ieee80211_bss_type' filepath='include/net/cfg80211.h' line='211' column='1' id='cb952348'>
@@ -131678,57 +131759,57 @@
           <var-decl name='pub' type-id='5f145050' visibility='default' filepath='net/wireless/core.h' line='163' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_bss' size-in-bits='768' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2088' column='1' id='5f145050'>
+      <class-decl name='cfg80211_bss' size-in-bits='768' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2091' column='1' id='5f145050'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='channel' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2089' column='1'/>
+          <var-decl name='channel' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2092' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='scan_width' type-id='95d46034' visibility='default' filepath='include/net/cfg80211.h' line='2090' column='1'/>
+          <var-decl name='scan_width' type-id='95d46034' visibility='default' filepath='include/net/cfg80211.h' line='2093' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='ies' type-id='f344e815' visibility='default' filepath='include/net/cfg80211.h' line='2092' column='1'/>
+          <var-decl name='ies' type-id='f344e815' visibility='default' filepath='include/net/cfg80211.h' line='2095' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='beacon_ies' type-id='f344e815' visibility='default' filepath='include/net/cfg80211.h' line='2093' column='1'/>
+          <var-decl name='beacon_ies' type-id='f344e815' visibility='default' filepath='include/net/cfg80211.h' line='2096' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='proberesp_ies' type-id='f344e815' visibility='default' filepath='include/net/cfg80211.h' line='2094' column='1'/>
+          <var-decl name='proberesp_ies' type-id='f344e815' visibility='default' filepath='include/net/cfg80211.h' line='2097' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='hidden_beacon_bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='2096' column='1'/>
+          <var-decl name='hidden_beacon_bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='2099' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='transmitted_bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='2097' column='1'/>
+          <var-decl name='transmitted_bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='2100' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='nontrans_list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='2098' column='1'/>
+          <var-decl name='nontrans_list' type-id='72f469ec' visibility='default' filepath='include/net/cfg80211.h' line='2101' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='signal' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='2100' column='1'/>
+          <var-decl name='signal' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='2103' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='608'>
-          <var-decl name='beacon_interval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2102' column='1'/>
+          <var-decl name='beacon_interval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2105' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='624'>
-          <var-decl name='capability' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2103' column='1'/>
+          <var-decl name='capability' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2106' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2105' column='1'/>
+          <var-decl name='bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2108' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='688'>
-          <var-decl name='chains' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2106' column='1'/>
+          <var-decl name='chains' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2109' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='696'>
-          <var-decl name='chain_signal' type-id='da004b74' visibility='default' filepath='include/net/cfg80211.h' line='2107' column='1'/>
+          <var-decl name='chain_signal' type-id='da004b74' visibility='default' filepath='include/net/cfg80211.h' line='2110' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='728'>
-          <var-decl name='bssid_index' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2109' column='1'/>
+          <var-decl name='bssid_index' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2112' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='736'>
-          <var-decl name='max_bssid_indicator' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2110' column='1'/>
+          <var-decl name='max_bssid_indicator' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2113' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='priv' type-id='29c3368c' visibility='default' filepath='include/net/cfg80211.h' line='2112' column='1'/>
+          <var-decl name='priv' type-id='29c3368c' visibility='default' filepath='include/net/cfg80211.h' line='2115' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='ieee80211_channel' size-in-bits='512' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='153' column='1' id='839b249b'>
@@ -131781,38 +131862,38 @@
         <enumerator name='NL80211_DFS_UNAVAILABLE' value='1'/>
         <enumerator name='NL80211_DFS_AVAILABLE' value='2'/>
       </enum-decl>
-      <class-decl name='cfg80211_bss_ies' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2049' column='1' id='7eedb398'>
+      <class-decl name='cfg80211_bss_ies' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2052' column='1' id='7eedb398'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='tsf' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='2050' column='1'/>
+          <var-decl name='tsf' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='2053' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='callback_head' type-id='e3d8ce29' visibility='default' filepath='include/net/cfg80211.h' line='2051' column='1'/>
+          <var-decl name='callback_head' type-id='e3d8ce29' visibility='default' filepath='include/net/cfg80211.h' line='2054' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2052' column='1'/>
+          <var-decl name='len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2055' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='224'>
-          <var-decl name='from_beacon' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2053' column='1'/>
+          <var-decl name='from_beacon' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2056' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='232'>
-          <var-decl name='data' type-id='29c3368c' visibility='default' filepath='include/net/cfg80211.h' line='2054' column='1'/>
+          <var-decl name='data' type-id='29c3368c' visibility='default' filepath='include/net/cfg80211.h' line='2057' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_chan_def' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='568' column='1' id='e07d69c8'>
+      <class-decl name='cfg80211_chan_def' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='571' column='1' id='e07d69c8'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='chan' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='569' column='1'/>
+          <var-decl name='chan' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='572' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='width' type-id='e043cccc' visibility='default' filepath='include/net/cfg80211.h' line='570' column='1'/>
+          <var-decl name='width' type-id='e043cccc' visibility='default' filepath='include/net/cfg80211.h' line='573' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='center_freq1' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='571' column='1'/>
+          <var-decl name='center_freq1' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='574' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='center_freq2' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='572' column='1'/>
+          <var-decl name='center_freq2' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='575' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='edmg' type-id='d87e6929' visibility='default' filepath='include/net/cfg80211.h' line='573' column='1'/>
+          <var-decl name='edmg' type-id='d87e6929' visibility='default' filepath='include/net/cfg80211.h' line='576' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_chan_width' filepath='include/uapi/linux/nl80211.h' line='4204' column='1' id='e043cccc'>
@@ -131863,18 +131944,18 @@
           <var-decl name='rssi_thresholds' type-id='a4bfb48f' visibility='default' filepath='net/wireless/core.h' line='279' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wiphy_iftype_ext_capab' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3955' column='1' id='378a6c5a'>
+      <class-decl name='wiphy_iftype_ext_capab' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3958' column='1' id='378a6c5a'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='iftype' type-id='86505f90' visibility='default' filepath='include/net/cfg80211.h' line='3956' column='1'/>
+          <var-decl name='iftype' type-id='86505f90' visibility='default' filepath='include/net/cfg80211.h' line='3959' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='extended_capabilities' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='3957' column='1'/>
+          <var-decl name='extended_capabilities' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='3960' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='extended_capabilities_mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='3958' column='1'/>
+          <var-decl name='extended_capabilities_mask' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='3961' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='extended_capabilities_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3959' column='1'/>
+          <var-decl name='extended_capabilities_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='3962' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='ieee80211_supported_band' size-in-bits='704' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='403' column='1' id='f7e1259c'>
@@ -132193,38 +132274,38 @@
           <var-decl name='supp_mcs' type-id='830056b5' visibility='default' filepath='include/linux/ieee80211.h' line='1518' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wiphy_coalesce_support' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3869' column='1' id='7124a2a6'>
+      <class-decl name='wiphy_coalesce_support' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3872' column='1' id='7124a2a6'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='n_rules' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3870' column='1'/>
+          <var-decl name='n_rules' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3873' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='max_delay' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3871' column='1'/>
+          <var-decl name='max_delay' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3874' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='n_patterns' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3872' column='1'/>
+          <var-decl name='n_patterns' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3875' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='pattern_max_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3873' column='1'/>
+          <var-decl name='pattern_max_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3876' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='pattern_min_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3874' column='1'/>
+          <var-decl name='pattern_min_len' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3877' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='max_pkt_offset' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3875' column='1'/>
+          <var-decl name='max_pkt_offset' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='3878' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='wiphy_vendor_command' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3934' column='1' id='fc206ed1'>
+      <class-decl name='wiphy_vendor_command' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3937' column='1' id='fc206ed1'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='info' type-id='e223f110' visibility='default' filepath='include/net/cfg80211.h' line='3935' column='1'/>
+          <var-decl name='info' type-id='e223f110' visibility='default' filepath='include/net/cfg80211.h' line='3938' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3936' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='3939' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='doit' type-id='a9032da3' visibility='default' filepath='include/net/cfg80211.h' line='3937' column='1'/>
+          <var-decl name='doit' type-id='a9032da3' visibility='default' filepath='include/net/cfg80211.h' line='3940' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='dumpit' type-id='dcf81beb' visibility='default' filepath='include/net/cfg80211.h' line='3939' column='1'/>
+          <var-decl name='dumpit' type-id='dcf81beb' visibility='default' filepath='include/net/cfg80211.h' line='3942' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='nl80211_vendor_cmd_info' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/uapi/linux/nl80211.h' line='5743' column='1' id='e223f110'>
@@ -132235,453 +132316,453 @@
           <var-decl name='subcmd' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/nl80211.h' line='5745' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_ops' size-in-bits='6912' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3281' column='1' id='8035b730'>
+      <class-decl name='cfg80211_ops' size-in-bits='6912' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='3284' column='1' id='8035b730'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='suspend' type-id='48b6113f' visibility='default' filepath='include/net/cfg80211.h' line='3282' column='1'/>
+          <var-decl name='suspend' type-id='48b6113f' visibility='default' filepath='include/net/cfg80211.h' line='3285' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='resume' type-id='518c633a' visibility='default' filepath='include/net/cfg80211.h' line='3283' column='1'/>
+          <var-decl name='resume' type-id='518c633a' visibility='default' filepath='include/net/cfg80211.h' line='3286' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='set_wakeup' type-id='dea9803a' visibility='default' filepath='include/net/cfg80211.h' line='3284' column='1'/>
+          <var-decl name='set_wakeup' type-id='dea9803a' visibility='default' filepath='include/net/cfg80211.h' line='3287' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='add_virtual_intf' type-id='d0299fd8' visibility='default' filepath='include/net/cfg80211.h' line='3286' column='1'/>
+          <var-decl name='add_virtual_intf' type-id='d0299fd8' visibility='default' filepath='include/net/cfg80211.h' line='3289' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='del_virtual_intf' type-id='242a426a' visibility='default' filepath='include/net/cfg80211.h' line='3291' column='1'/>
+          <var-decl name='del_virtual_intf' type-id='242a426a' visibility='default' filepath='include/net/cfg80211.h' line='3294' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='change_virtual_intf' type-id='9e135c1b' visibility='default' filepath='include/net/cfg80211.h' line='3293' column='1'/>
+          <var-decl name='change_virtual_intf' type-id='9e135c1b' visibility='default' filepath='include/net/cfg80211.h' line='3296' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='add_key' type-id='ad666b67' visibility='default' filepath='include/net/cfg80211.h' line='3298' column='1'/>
+          <var-decl name='add_key' type-id='ad666b67' visibility='default' filepath='include/net/cfg80211.h' line='3301' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='get_key' type-id='a9103ada' visibility='default' filepath='include/net/cfg80211.h' line='3301' column='1'/>
+          <var-decl name='get_key' type-id='a9103ada' visibility='default' filepath='include/net/cfg80211.h' line='3304' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='del_key' type-id='5bb4e7cf' visibility='default' filepath='include/net/cfg80211.h' line='3305' column='1'/>
+          <var-decl name='del_key' type-id='5bb4e7cf' visibility='default' filepath='include/net/cfg80211.h' line='3308' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='set_default_key' type-id='3e5d8250' visibility='default' filepath='include/net/cfg80211.h' line='3307' column='1'/>
+          <var-decl name='set_default_key' type-id='3e5d8250' visibility='default' filepath='include/net/cfg80211.h' line='3310' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='set_default_mgmt_key' type-id='a1fc1aec' visibility='default' filepath='include/net/cfg80211.h' line='3310' column='1'/>
+          <var-decl name='set_default_mgmt_key' type-id='a1fc1aec' visibility='default' filepath='include/net/cfg80211.h' line='3313' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='set_default_beacon_key' type-id='a1fc1aec' visibility='default' filepath='include/net/cfg80211.h' line='3313' column='1'/>
+          <var-decl name='set_default_beacon_key' type-id='a1fc1aec' visibility='default' filepath='include/net/cfg80211.h' line='3316' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='start_ap' type-id='c64be45e' visibility='default' filepath='include/net/cfg80211.h' line='3317' column='1'/>
+          <var-decl name='start_ap' type-id='c64be45e' visibility='default' filepath='include/net/cfg80211.h' line='3320' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='change_beacon' type-id='2ae5992c' visibility='default' filepath='include/net/cfg80211.h' line='3319' column='1'/>
+          <var-decl name='change_beacon' type-id='2ae5992c' visibility='default' filepath='include/net/cfg80211.h' line='3322' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='stop_ap' type-id='85316748' visibility='default' filepath='include/net/cfg80211.h' line='3321' column='1'/>
+          <var-decl name='stop_ap' type-id='85316748' visibility='default' filepath='include/net/cfg80211.h' line='3324' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='add_station' type-id='cf6c6fcb' visibility='default' filepath='include/net/cfg80211.h' line='3324' column='1'/>
+          <var-decl name='add_station' type-id='cf6c6fcb' visibility='default' filepath='include/net/cfg80211.h' line='3327' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='del_station' type-id='ce1d0c65' visibility='default' filepath='include/net/cfg80211.h' line='3327' column='1'/>
+          <var-decl name='del_station' type-id='ce1d0c65' visibility='default' filepath='include/net/cfg80211.h' line='3330' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='change_station' type-id='cf6c6fcb' visibility='default' filepath='include/net/cfg80211.h' line='3329' column='1'/>
+          <var-decl name='change_station' type-id='cf6c6fcb' visibility='default' filepath='include/net/cfg80211.h' line='3332' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='get_station' type-id='8ae117f3' visibility='default' filepath='include/net/cfg80211.h' line='3332' column='1'/>
+          <var-decl name='get_station' type-id='8ae117f3' visibility='default' filepath='include/net/cfg80211.h' line='3335' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='dump_station' type-id='ecbadb29' visibility='default' filepath='include/net/cfg80211.h' line='3334' column='1'/>
+          <var-decl name='dump_station' type-id='ecbadb29' visibility='default' filepath='include/net/cfg80211.h' line='3337' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='add_mpath' type-id='117ab738' visibility='default' filepath='include/net/cfg80211.h' line='3337' column='1'/>
+          <var-decl name='add_mpath' type-id='117ab738' visibility='default' filepath='include/net/cfg80211.h' line='3340' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='del_mpath' type-id='e8733840' visibility='default' filepath='include/net/cfg80211.h' line='3339' column='1'/>
+          <var-decl name='del_mpath' type-id='e8733840' visibility='default' filepath='include/net/cfg80211.h' line='3342' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='change_mpath' type-id='117ab738' visibility='default' filepath='include/net/cfg80211.h' line='3341' column='1'/>
+          <var-decl name='change_mpath' type-id='117ab738' visibility='default' filepath='include/net/cfg80211.h' line='3344' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1472'>
-          <var-decl name='get_mpath' type-id='b916eba5' visibility='default' filepath='include/net/cfg80211.h' line='3343' column='1'/>
+          <var-decl name='get_mpath' type-id='b916eba5' visibility='default' filepath='include/net/cfg80211.h' line='3346' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='dump_mpath' type-id='add0c1a4' visibility='default' filepath='include/net/cfg80211.h' line='3345' column='1'/>
+          <var-decl name='dump_mpath' type-id='add0c1a4' visibility='default' filepath='include/net/cfg80211.h' line='3348' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1600'>
-          <var-decl name='get_mpp' type-id='b916eba5' visibility='default' filepath='include/net/cfg80211.h' line='3348' column='1'/>
+          <var-decl name='get_mpp' type-id='b916eba5' visibility='default' filepath='include/net/cfg80211.h' line='3351' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1664'>
-          <var-decl name='dump_mpp' type-id='add0c1a4' visibility='default' filepath='include/net/cfg80211.h' line='3350' column='1'/>
+          <var-decl name='dump_mpp' type-id='add0c1a4' visibility='default' filepath='include/net/cfg80211.h' line='3353' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1728'>
-          <var-decl name='get_mesh_config' type-id='f1dac4d6' visibility='default' filepath='include/net/cfg80211.h' line='3353' column='1'/>
+          <var-decl name='get_mesh_config' type-id='f1dac4d6' visibility='default' filepath='include/net/cfg80211.h' line='3356' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1792'>
-          <var-decl name='update_mesh_config' type-id='39979680' visibility='default' filepath='include/net/cfg80211.h' line='3356' column='1'/>
+          <var-decl name='update_mesh_config' type-id='39979680' visibility='default' filepath='include/net/cfg80211.h' line='3359' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='join_mesh' type-id='840c4ecb' visibility='default' filepath='include/net/cfg80211.h' line='3359' column='1'/>
+          <var-decl name='join_mesh' type-id='840c4ecb' visibility='default' filepath='include/net/cfg80211.h' line='3362' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1920'>
-          <var-decl name='leave_mesh' type-id='85316748' visibility='default' filepath='include/net/cfg80211.h' line='3362' column='1'/>
+          <var-decl name='leave_mesh' type-id='85316748' visibility='default' filepath='include/net/cfg80211.h' line='3365' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1984'>
-          <var-decl name='join_ocb' type-id='8afbb034' visibility='default' filepath='include/net/cfg80211.h' line='3364' column='1'/>
+          <var-decl name='join_ocb' type-id='8afbb034' visibility='default' filepath='include/net/cfg80211.h' line='3367' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='leave_ocb' type-id='85316748' visibility='default' filepath='include/net/cfg80211.h' line='3366' column='1'/>
+          <var-decl name='leave_ocb' type-id='85316748' visibility='default' filepath='include/net/cfg80211.h' line='3369' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='change_bss' type-id='b7589fb3' visibility='default' filepath='include/net/cfg80211.h' line='3368' column='1'/>
+          <var-decl name='change_bss' type-id='b7589fb3' visibility='default' filepath='include/net/cfg80211.h' line='3371' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2176'>
-          <var-decl name='set_txq_params' type-id='626eee7d' visibility='default' filepath='include/net/cfg80211.h' line='3371' column='1'/>
+          <var-decl name='set_txq_params' type-id='626eee7d' visibility='default' filepath='include/net/cfg80211.h' line='3374' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2240'>
-          <var-decl name='libertas_set_mesh_channel' type-id='1ad767ce' visibility='default' filepath='include/net/cfg80211.h' line='3374' column='1'/>
+          <var-decl name='libertas_set_mesh_channel' type-id='1ad767ce' visibility='default' filepath='include/net/cfg80211.h' line='3377' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2304'>
-          <var-decl name='set_monitor_channel' type-id='40a250d9' visibility='default' filepath='include/net/cfg80211.h' line='3378' column='1'/>
+          <var-decl name='set_monitor_channel' type-id='40a250d9' visibility='default' filepath='include/net/cfg80211.h' line='3381' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2368'>
-          <var-decl name='scan' type-id='f6d3f940' visibility='default' filepath='include/net/cfg80211.h' line='3381' column='1'/>
+          <var-decl name='scan' type-id='f6d3f940' visibility='default' filepath='include/net/cfg80211.h' line='3384' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2432'>
-          <var-decl name='abort_scan' type-id='c62f28a1' visibility='default' filepath='include/net/cfg80211.h' line='3383' column='1'/>
+          <var-decl name='abort_scan' type-id='c62f28a1' visibility='default' filepath='include/net/cfg80211.h' line='3386' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2496'>
-          <var-decl name='auth' type-id='7bc524a3' visibility='default' filepath='include/net/cfg80211.h' line='3385' column='1'/>
+          <var-decl name='auth' type-id='7bc524a3' visibility='default' filepath='include/net/cfg80211.h' line='3388' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2560'>
-          <var-decl name='assoc' type-id='683d81d8' visibility='default' filepath='include/net/cfg80211.h' line='3387' column='1'/>
+          <var-decl name='assoc' type-id='683d81d8' visibility='default' filepath='include/net/cfg80211.h' line='3390' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2624'>
-          <var-decl name='deauth' type-id='cdbc24fe' visibility='default' filepath='include/net/cfg80211.h' line='3389' column='1'/>
+          <var-decl name='deauth' type-id='cdbc24fe' visibility='default' filepath='include/net/cfg80211.h' line='3392' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2688'>
-          <var-decl name='disassoc' type-id='6430463c' visibility='default' filepath='include/net/cfg80211.h' line='3391' column='1'/>
+          <var-decl name='disassoc' type-id='6430463c' visibility='default' filepath='include/net/cfg80211.h' line='3394' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2752'>
-          <var-decl name='connect' type-id='b074b5d4' visibility='default' filepath='include/net/cfg80211.h' line='3394' column='1'/>
+          <var-decl name='connect' type-id='b074b5d4' visibility='default' filepath='include/net/cfg80211.h' line='3397' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2816'>
-          <var-decl name='update_connect_params' type-id='bcf952e3' visibility='default' filepath='include/net/cfg80211.h' line='3396' column='1'/>
+          <var-decl name='update_connect_params' type-id='bcf952e3' visibility='default' filepath='include/net/cfg80211.h' line='3399' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2880'>
-          <var-decl name='disconnect' type-id='bb2acc29' visibility='default' filepath='include/net/cfg80211.h' line='3400' column='1'/>
+          <var-decl name='disconnect' type-id='bb2acc29' visibility='default' filepath='include/net/cfg80211.h' line='3403' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2944'>
-          <var-decl name='join_ibss' type-id='ead2af37' visibility='default' filepath='include/net/cfg80211.h' line='3403' column='1'/>
+          <var-decl name='join_ibss' type-id='ead2af37' visibility='default' filepath='include/net/cfg80211.h' line='3406' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3008'>
-          <var-decl name='leave_ibss' type-id='85316748' visibility='default' filepath='include/net/cfg80211.h' line='3405' column='1'/>
+          <var-decl name='leave_ibss' type-id='85316748' visibility='default' filepath='include/net/cfg80211.h' line='3408' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3072'>
-          <var-decl name='set_mcast_rate' type-id='c5fb4eb9' visibility='default' filepath='include/net/cfg80211.h' line='3407' column='1'/>
+          <var-decl name='set_mcast_rate' type-id='c5fb4eb9' visibility='default' filepath='include/net/cfg80211.h' line='3410' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3136'>
-          <var-decl name='set_wiphy_params' type-id='bba0f341' visibility='default' filepath='include/net/cfg80211.h' line='3410' column='1'/>
+          <var-decl name='set_wiphy_params' type-id='bba0f341' visibility='default' filepath='include/net/cfg80211.h' line='3413' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3200'>
-          <var-decl name='set_tx_power' type-id='fffcbb90' visibility='default' filepath='include/net/cfg80211.h' line='3412' column='1'/>
+          <var-decl name='set_tx_power' type-id='fffcbb90' visibility='default' filepath='include/net/cfg80211.h' line='3415' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3264'>
-          <var-decl name='get_tx_power' type-id='030fbe7b' visibility='default' filepath='include/net/cfg80211.h' line='3414' column='1'/>
+          <var-decl name='get_tx_power' type-id='030fbe7b' visibility='default' filepath='include/net/cfg80211.h' line='3417' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3328'>
-          <var-decl name='set_wds_peer' type-id='e8733840' visibility='default' filepath='include/net/cfg80211.h' line='3417' column='1'/>
+          <var-decl name='set_wds_peer' type-id='e8733840' visibility='default' filepath='include/net/cfg80211.h' line='3420' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3392'>
-          <var-decl name='rfkill_poll' type-id='03a67bbf' visibility='default' filepath='include/net/cfg80211.h' line='3420' column='1'/>
+          <var-decl name='rfkill_poll' type-id='03a67bbf' visibility='default' filepath='include/net/cfg80211.h' line='3423' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3456'>
-          <var-decl name='testmode_cmd' type-id='a9032da3' visibility='default' filepath='include/net/cfg80211.h' line='3422' column='1'/>
+          <var-decl name='testmode_cmd' type-id='a9032da3' visibility='default' filepath='include/net/cfg80211.h' line='3425' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3520'>
-          <var-decl name='testmode_dump' type-id='b92cb0da' visibility='default' filepath='include/net/cfg80211.h' line='3424' column='1'/>
+          <var-decl name='testmode_dump' type-id='b92cb0da' visibility='default' filepath='include/net/cfg80211.h' line='3427' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3584'>
-          <var-decl name='set_bitrate_mask' type-id='95464a70' visibility='default' filepath='include/net/cfg80211.h' line='3428' column='1'/>
+          <var-decl name='set_bitrate_mask' type-id='95464a70' visibility='default' filepath='include/net/cfg80211.h' line='3431' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3648'>
-          <var-decl name='dump_survey' type-id='95a1c330' visibility='default' filepath='include/net/cfg80211.h' line='3433' column='1'/>
+          <var-decl name='dump_survey' type-id='95a1c330' visibility='default' filepath='include/net/cfg80211.h' line='3436' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3712'>
-          <var-decl name='set_pmksa' type-id='e227fe73' visibility='default' filepath='include/net/cfg80211.h' line='3436' column='1'/>
+          <var-decl name='set_pmksa' type-id='e227fe73' visibility='default' filepath='include/net/cfg80211.h' line='3439' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3776'>
-          <var-decl name='del_pmksa' type-id='e227fe73' visibility='default' filepath='include/net/cfg80211.h' line='3438' column='1'/>
+          <var-decl name='del_pmksa' type-id='e227fe73' visibility='default' filepath='include/net/cfg80211.h' line='3441' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3840'>
-          <var-decl name='flush_pmksa' type-id='85316748' visibility='default' filepath='include/net/cfg80211.h' line='3440' column='1'/>
+          <var-decl name='flush_pmksa' type-id='85316748' visibility='default' filepath='include/net/cfg80211.h' line='3443' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3904'>
-          <var-decl name='remain_on_channel' type-id='e4776627' visibility='default' filepath='include/net/cfg80211.h' line='3442' column='1'/>
+          <var-decl name='remain_on_channel' type-id='e4776627' visibility='default' filepath='include/net/cfg80211.h' line='3445' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3968'>
-          <var-decl name='cancel_remain_on_channel' type-id='6a7c3ba2' visibility='default' filepath='include/net/cfg80211.h' line='3447' column='1'/>
+          <var-decl name='cancel_remain_on_channel' type-id='6a7c3ba2' visibility='default' filepath='include/net/cfg80211.h' line='3450' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4032'>
-          <var-decl name='mgmt_tx' type-id='654eb68b' visibility='default' filepath='include/net/cfg80211.h' line='3451' column='1'/>
+          <var-decl name='mgmt_tx' type-id='654eb68b' visibility='default' filepath='include/net/cfg80211.h' line='3454' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4096'>
-          <var-decl name='mgmt_tx_cancel_wait' type-id='6a7c3ba2' visibility='default' filepath='include/net/cfg80211.h' line='3454' column='1'/>
+          <var-decl name='mgmt_tx_cancel_wait' type-id='6a7c3ba2' visibility='default' filepath='include/net/cfg80211.h' line='3457' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4160'>
-          <var-decl name='set_power_mgmt' type-id='00ca7240' visibility='default' filepath='include/net/cfg80211.h' line='3458' column='1'/>
+          <var-decl name='set_power_mgmt' type-id='00ca7240' visibility='default' filepath='include/net/cfg80211.h' line='3461' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4224'>
-          <var-decl name='set_cqm_rssi_config' type-id='d170fd68' visibility='default' filepath='include/net/cfg80211.h' line='3461' column='1'/>
+          <var-decl name='set_cqm_rssi_config' type-id='d170fd68' visibility='default' filepath='include/net/cfg80211.h' line='3464' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4288'>
-          <var-decl name='set_cqm_rssi_range_config' type-id='841c4b1a' visibility='default' filepath='include/net/cfg80211.h' line='3465' column='1'/>
+          <var-decl name='set_cqm_rssi_range_config' type-id='841c4b1a' visibility='default' filepath='include/net/cfg80211.h' line='3468' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4352'>
-          <var-decl name='set_cqm_txe_config' type-id='e279af7d' visibility='default' filepath='include/net/cfg80211.h' line='3469' column='1'/>
+          <var-decl name='set_cqm_txe_config' type-id='e279af7d' visibility='default' filepath='include/net/cfg80211.h' line='3472' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4416'>
-          <var-decl name='mgmt_frame_register' type-id='585d0267' visibility='default' filepath='include/net/cfg80211.h' line='3473' column='1'/>
+          <var-decl name='mgmt_frame_register' type-id='585d0267' visibility='default' filepath='include/net/cfg80211.h' line='3476' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4480'>
-          <var-decl name='set_antenna' type-id='5e89e128' visibility='default' filepath='include/net/cfg80211.h' line='3477' column='1'/>
+          <var-decl name='set_antenna' type-id='5e89e128' visibility='default' filepath='include/net/cfg80211.h' line='3480' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4544'>
-          <var-decl name='get_antenna' type-id='22c1973a' visibility='default' filepath='include/net/cfg80211.h' line='3478' column='1'/>
+          <var-decl name='get_antenna' type-id='22c1973a' visibility='default' filepath='include/net/cfg80211.h' line='3481' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4608'>
-          <var-decl name='sched_scan_start' type-id='672436e6' visibility='default' filepath='include/net/cfg80211.h' line='3480' column='1'/>
+          <var-decl name='sched_scan_start' type-id='672436e6' visibility='default' filepath='include/net/cfg80211.h' line='3483' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4672'>
-          <var-decl name='sched_scan_stop' type-id='f7f7a1c4' visibility='default' filepath='include/net/cfg80211.h' line='3483' column='1'/>
+          <var-decl name='sched_scan_stop' type-id='f7f7a1c4' visibility='default' filepath='include/net/cfg80211.h' line='3486' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4736'>
-          <var-decl name='set_rekey_data' type-id='f76a2553' visibility='default' filepath='include/net/cfg80211.h' line='3486' column='1'/>
+          <var-decl name='set_rekey_data' type-id='f76a2553' visibility='default' filepath='include/net/cfg80211.h' line='3489' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4800'>
-          <var-decl name='tdls_mgmt' type-id='d6ca98e4' visibility='default' filepath='include/net/cfg80211.h' line='3489' column='1'/>
+          <var-decl name='tdls_mgmt' type-id='d6ca98e4' visibility='default' filepath='include/net/cfg80211.h' line='3492' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4864'>
-          <var-decl name='tdls_oper' type-id='7f8a52ed' visibility='default' filepath='include/net/cfg80211.h' line='3493' column='1'/>
+          <var-decl name='tdls_oper' type-id='7f8a52ed' visibility='default' filepath='include/net/cfg80211.h' line='3496' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4928'>
-          <var-decl name='probe_client' type-id='3c511dc5' visibility='default' filepath='include/net/cfg80211.h' line='3496' column='1'/>
+          <var-decl name='probe_client' type-id='3c511dc5' visibility='default' filepath='include/net/cfg80211.h' line='3499' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='4992'>
-          <var-decl name='set_noack_map' type-id='bb2acc29' visibility='default' filepath='include/net/cfg80211.h' line='3499' column='1'/>
+          <var-decl name='set_noack_map' type-id='bb2acc29' visibility='default' filepath='include/net/cfg80211.h' line='3502' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5056'>
-          <var-decl name='get_channel' type-id='68dd3d29' visibility='default' filepath='include/net/cfg80211.h' line='3503' column='1'/>
+          <var-decl name='get_channel' type-id='68dd3d29' visibility='default' filepath='include/net/cfg80211.h' line='3506' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5120'>
-          <var-decl name='start_p2p_device' type-id='242a426a' visibility='default' filepath='include/net/cfg80211.h' line='3507' column='1'/>
+          <var-decl name='start_p2p_device' type-id='242a426a' visibility='default' filepath='include/net/cfg80211.h' line='3510' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5184'>
-          <var-decl name='stop_p2p_device' type-id='c62f28a1' visibility='default' filepath='include/net/cfg80211.h' line='3509' column='1'/>
+          <var-decl name='stop_p2p_device' type-id='c62f28a1' visibility='default' filepath='include/net/cfg80211.h' line='3512' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5248'>
-          <var-decl name='set_mac_acl' type-id='79cba4ed' visibility='default' filepath='include/net/cfg80211.h' line='3512' column='1'/>
+          <var-decl name='set_mac_acl' type-id='79cba4ed' visibility='default' filepath='include/net/cfg80211.h' line='3515' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5312'>
-          <var-decl name='start_radar_detection' type-id='ded841a6' visibility='default' filepath='include/net/cfg80211.h' line='3515' column='1'/>
+          <var-decl name='start_radar_detection' type-id='ded841a6' visibility='default' filepath='include/net/cfg80211.h' line='3518' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5376'>
-          <var-decl name='end_cac' type-id='df4195e7' visibility='default' filepath='include/net/cfg80211.h' line='3519' column='1'/>
+          <var-decl name='end_cac' type-id='df4195e7' visibility='default' filepath='include/net/cfg80211.h' line='3522' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5440'>
-          <var-decl name='update_ft_ies' type-id='1ca6081e' visibility='default' filepath='include/net/cfg80211.h' line='3521' column='1'/>
+          <var-decl name='update_ft_ies' type-id='1ca6081e' visibility='default' filepath='include/net/cfg80211.h' line='3524' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5504'>
-          <var-decl name='crit_proto_start' type-id='8e9877b2' visibility='default' filepath='include/net/cfg80211.h' line='3523' column='1'/>
+          <var-decl name='crit_proto_start' type-id='8e9877b2' visibility='default' filepath='include/net/cfg80211.h' line='3526' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5568'>
-          <var-decl name='crit_proto_stop' type-id='c62f28a1' visibility='default' filepath='include/net/cfg80211.h' line='3527' column='1'/>
+          <var-decl name='crit_proto_stop' type-id='c62f28a1' visibility='default' filepath='include/net/cfg80211.h' line='3530' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5632'>
-          <var-decl name='set_coalesce' type-id='ee39fcb4' visibility='default' filepath='include/net/cfg80211.h' line='3529' column='1'/>
+          <var-decl name='set_coalesce' type-id='ee39fcb4' visibility='default' filepath='include/net/cfg80211.h' line='3532' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5696'>
-          <var-decl name='channel_switch' type-id='314252f6' visibility='default' filepath='include/net/cfg80211.h' line='3532' column='1'/>
+          <var-decl name='channel_switch' type-id='314252f6' visibility='default' filepath='include/net/cfg80211.h' line='3535' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5760'>
-          <var-decl name='set_qos_map' type-id='ef4b69cb' visibility='default' filepath='include/net/cfg80211.h' line='3536' column='1'/>
+          <var-decl name='set_qos_map' type-id='ef4b69cb' visibility='default' filepath='include/net/cfg80211.h' line='3539' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5824'>
-          <var-decl name='set_ap_chanwidth' type-id='ca02ba37' visibility='default' filepath='include/net/cfg80211.h' line='3540' column='1'/>
+          <var-decl name='set_ap_chanwidth' type-id='ca02ba37' visibility='default' filepath='include/net/cfg80211.h' line='3543' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5888'>
-          <var-decl name='add_tx_ts' type-id='83206c41' visibility='default' filepath='include/net/cfg80211.h' line='3543' column='1'/>
+          <var-decl name='add_tx_ts' type-id='83206c41' visibility='default' filepath='include/net/cfg80211.h' line='3546' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='5952'>
-          <var-decl name='del_tx_ts' type-id='99da26e4' visibility='default' filepath='include/net/cfg80211.h' line='3546' column='1'/>
+          <var-decl name='del_tx_ts' type-id='99da26e4' visibility='default' filepath='include/net/cfg80211.h' line='3549' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6016'>
-          <var-decl name='tdls_channel_switch' type-id='5228b15b' visibility='default' filepath='include/net/cfg80211.h' line='3549' column='1'/>
+          <var-decl name='tdls_channel_switch' type-id='5228b15b' visibility='default' filepath='include/net/cfg80211.h' line='3552' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6080'>
-          <var-decl name='tdls_cancel_channel_switch' type-id='6bc8bd61' visibility='default' filepath='include/net/cfg80211.h' line='3553' column='1'/>
+          <var-decl name='tdls_cancel_channel_switch' type-id='6bc8bd61' visibility='default' filepath='include/net/cfg80211.h' line='3556' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6144'>
-          <var-decl name='start_nan' type-id='e0e35961' visibility='default' filepath='include/net/cfg80211.h' line='3556' column='1'/>
+          <var-decl name='start_nan' type-id='e0e35961' visibility='default' filepath='include/net/cfg80211.h' line='3559' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6208'>
-          <var-decl name='stop_nan' type-id='c62f28a1' visibility='default' filepath='include/net/cfg80211.h' line='3558' column='1'/>
+          <var-decl name='stop_nan' type-id='c62f28a1' visibility='default' filepath='include/net/cfg80211.h' line='3561' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6272'>
-          <var-decl name='add_nan_func' type-id='e045e355' visibility='default' filepath='include/net/cfg80211.h' line='3559' column='1'/>
+          <var-decl name='add_nan_func' type-id='e045e355' visibility='default' filepath='include/net/cfg80211.h' line='3562' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6336'>
-          <var-decl name='del_nan_func' type-id='8baf5297' visibility='default' filepath='include/net/cfg80211.h' line='3561' column='1'/>
+          <var-decl name='del_nan_func' type-id='8baf5297' visibility='default' filepath='include/net/cfg80211.h' line='3564' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6400'>
-          <var-decl name='nan_change_conf' type-id='f61682c8' visibility='default' filepath='include/net/cfg80211.h' line='3563' column='1'/>
+          <var-decl name='nan_change_conf' type-id='f61682c8' visibility='default' filepath='include/net/cfg80211.h' line='3566' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6464'>
-          <var-decl name='set_multicast_to_unicast' type-id='5c035afd' visibility='default' filepath='include/net/cfg80211.h' line='3568' column='1'/>
+          <var-decl name='set_multicast_to_unicast' type-id='5c035afd' visibility='default' filepath='include/net/cfg80211.h' line='3571' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6528'>
-          <var-decl name='get_txq_stats' type-id='7e6add04' visibility='default' filepath='include/net/cfg80211.h' line='3572' column='1'/>
+          <var-decl name='get_txq_stats' type-id='7e6add04' visibility='default' filepath='include/net/cfg80211.h' line='3575' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6592'>
-          <var-decl name='set_pmk' type-id='6d8f49c3' visibility='default' filepath='include/net/cfg80211.h' line='3576' column='1'/>
+          <var-decl name='set_pmk' type-id='6d8f49c3' visibility='default' filepath='include/net/cfg80211.h' line='3579' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6656'>
-          <var-decl name='del_pmk' type-id='e8733840' visibility='default' filepath='include/net/cfg80211.h' line='3578' column='1'/>
+          <var-decl name='del_pmk' type-id='e8733840' visibility='default' filepath='include/net/cfg80211.h' line='3581' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6720'>
-          <var-decl name='external_auth' type-id='9b201d8c' visibility='default' filepath='include/net/cfg80211.h' line='3580' column='1'/>
+          <var-decl name='external_auth' type-id='9b201d8c' visibility='default' filepath='include/net/cfg80211.h' line='3583' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6784'>
-          <var-decl name='tx_control_port' type-id='f08a54cd' visibility='default' filepath='include/net/cfg80211.h' line='3583' column='1'/>
+          <var-decl name='tx_control_port' type-id='f08a54cd' visibility='default' filepath='include/net/cfg80211.h' line='3586' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='6848'>
-          <var-decl name='update_owe_info' type-id='3f98a2ff' visibility='default' filepath='include/net/cfg80211.h' line='3588' column='1'/>
+          <var-decl name='update_owe_info' type-id='3f98a2ff' visibility='default' filepath='include/net/cfg80211.h' line='3591' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='vif_params' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='527' column='1' id='d1abd80d'>
+      <class-decl name='vif_params' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='530' column='1' id='d1abd80d'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='528' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='531' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='use_4addr' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='529' column='1'/>
+          <var-decl name='use_4addr' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='532' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='macaddr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='530' column='1'/>
+          <var-decl name='macaddr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='533' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='vht_mumimo_groups' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='531' column='1'/>
+          <var-decl name='vht_mumimo_groups' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='534' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='vht_mumimo_follow_addr' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='532' column='1'/>
+          <var-decl name='vht_mumimo_follow_addr' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='535' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_ap_settings' size-in-bits='3264' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='944' column='1' id='7f421823'>
+      <class-decl name='cfg80211_ap_settings' size-in-bits='3264' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='947' column='1' id='7f421823'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='945' column='1'/>
+          <var-decl name='chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='948' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='beacon' type-id='e61c5935' visibility='default' filepath='include/net/cfg80211.h' line='947' column='1'/>
+          <var-decl name='beacon' type-id='e61c5935' visibility='default' filepath='include/net/cfg80211.h' line='950' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='beacon_interval' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='949' column='1'/>
+          <var-decl name='beacon_interval' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='952' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1056'>
-          <var-decl name='dtim_period' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='949' column='1'/>
+          <var-decl name='dtim_period' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='952' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='ssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='950' column='1'/>
+          <var-decl name='ssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='953' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='ssid_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='951' column='1'/>
+          <var-decl name='ssid_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='954' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='hidden_ssid' type-id='fba6f1ff' visibility='default' filepath='include/net/cfg80211.h' line='952' column='1'/>
+          <var-decl name='hidden_ssid' type-id='fba6f1ff' visibility='default' filepath='include/net/cfg80211.h' line='955' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='crypto' type-id='f81bbd3b' visibility='default' filepath='include/net/cfg80211.h' line='953' column='1'/>
+          <var-decl name='crypto' type-id='f81bbd3b' visibility='default' filepath='include/net/cfg80211.h' line='956' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1920'>
-          <var-decl name='privacy' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='954' column='1'/>
+          <var-decl name='privacy' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='957' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1952'>
-          <var-decl name='auth_type' type-id='f7dadf06' visibility='default' filepath='include/net/cfg80211.h' line='955' column='1'/>
+          <var-decl name='auth_type' type-id='f7dadf06' visibility='default' filepath='include/net/cfg80211.h' line='958' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1984'>
-          <var-decl name='smps_mode' type-id='7f4af420' visibility='default' filepath='include/net/cfg80211.h' line='956' column='1'/>
+          <var-decl name='smps_mode' type-id='7f4af420' visibility='default' filepath='include/net/cfg80211.h' line='959' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2016'>
-          <var-decl name='inactivity_timeout' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='957' column='1'/>
+          <var-decl name='inactivity_timeout' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='960' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='p2p_ctwindow' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='958' column='1'/>
+          <var-decl name='p2p_ctwindow' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='961' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2056'>
-          <var-decl name='p2p_opp_ps' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='959' column='1'/>
+          <var-decl name='p2p_opp_ps' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='962' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2112'>
-          <var-decl name='acl' type-id='bfda7a08' visibility='default' filepath='include/net/cfg80211.h' line='960' column='1'/>
+          <var-decl name='acl' type-id='bfda7a08' visibility='default' filepath='include/net/cfg80211.h' line='963' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2176'>
-          <var-decl name='pbss' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='961' column='1'/>
+          <var-decl name='pbss' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='964' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2208'>
-          <var-decl name='beacon_rate' type-id='febb0cbe' visibility='default' filepath='include/net/cfg80211.h' line='962' column='1'/>
+          <var-decl name='beacon_rate' type-id='febb0cbe' visibility='default' filepath='include/net/cfg80211.h' line='965' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3072'>
-          <var-decl name='ht_cap' type-id='81f1a1a8' visibility='default' filepath='include/net/cfg80211.h' line='964' column='1'/>
+          <var-decl name='ht_cap' type-id='81f1a1a8' visibility='default' filepath='include/net/cfg80211.h' line='967' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3136'>
-          <var-decl name='vht_cap' type-id='fffb07a4' visibility='default' filepath='include/net/cfg80211.h' line='965' column='1'/>
+          <var-decl name='vht_cap' type-id='fffb07a4' visibility='default' filepath='include/net/cfg80211.h' line='968' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3200'>
-          <var-decl name='ht_required' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='966' column='1'/>
+          <var-decl name='ht_required' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='969' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3208'>
-          <var-decl name='vht_required' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='966' column='1'/>
+          <var-decl name='vht_required' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='969' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='3232'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='967' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='970' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_beacon_data' size-in-bits='768' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='856' column='1' id='e61c5935'>
+      <class-decl name='cfg80211_beacon_data' size-in-bits='768' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='859' column='1' id='e61c5935'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='head' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='857' column='1'/>
+          <var-decl name='head' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='860' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='tail' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='857' column='1'/>
+          <var-decl name='tail' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='860' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='beacon_ies' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='858' column='1'/>
+          <var-decl name='beacon_ies' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='861' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='proberesp_ies' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='859' column='1'/>
+          <var-decl name='proberesp_ies' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='862' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='assocresp_ies' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='860' column='1'/>
+          <var-decl name='assocresp_ies' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='863' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='probe_resp' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='861' column='1'/>
+          <var-decl name='probe_resp' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='864' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='head_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='863' column='1'/>
+          <var-decl name='head_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='866' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='tail_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='863' column='1'/>
+          <var-decl name='tail_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='866' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='beacon_ies_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='864' column='1'/>
+          <var-decl name='beacon_ies_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='867' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='proberesp_ies_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='865' column='1'/>
+          <var-decl name='proberesp_ies_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='868' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='assocresp_ies_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='866' column='1'/>
+          <var-decl name='assocresp_ies_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='869' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='probe_resp_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='867' column='1'/>
+          <var-decl name='probe_resp_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='870' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_hidden_ssid' filepath='include/uapi/linux/nl80211.h' line='5102' column='1' id='fba6f1ff'>
@@ -132690,45 +132771,45 @@
         <enumerator name='NL80211_HIDDEN_SSID_ZERO_LEN' value='1'/>
         <enumerator name='NL80211_HIDDEN_SSID_ZERO_CONTENTS' value='2'/>
       </enum-decl>
-      <class-decl name='cfg80211_crypto_settings' size-in-bits='640' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='821' column='1' id='f81bbd3b'>
+      <class-decl name='cfg80211_crypto_settings' size-in-bits='640' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='824' column='1' id='f81bbd3b'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='wpa_versions' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='822' column='1'/>
+          <var-decl name='wpa_versions' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='825' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='cipher_group' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='823' column='1'/>
+          <var-decl name='cipher_group' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='826' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='n_ciphers_pairwise' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='824' column='1'/>
+          <var-decl name='n_ciphers_pairwise' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='827' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='ciphers_pairwise' type-id='586ea944' visibility='default' filepath='include/net/cfg80211.h' line='825' column='1'/>
+          <var-decl name='ciphers_pairwise' type-id='586ea944' visibility='default' filepath='include/net/cfg80211.h' line='828' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='n_akm_suites' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='826' column='1'/>
+          <var-decl name='n_akm_suites' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='829' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='288'>
-          <var-decl name='akm_suites' type-id='1872161b' visibility='default' filepath='include/net/cfg80211.h' line='827' column='1'/>
+          <var-decl name='akm_suites' type-id='1872161b' visibility='default' filepath='include/net/cfg80211.h' line='830' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='352'>
-          <var-decl name='control_port' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='828' column='1'/>
+          <var-decl name='control_port' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='831' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='368'>
-          <var-decl name='control_port_ethertype' type-id='84a5c3d4' visibility='default' filepath='include/net/cfg80211.h' line='829' column='1'/>
+          <var-decl name='control_port_ethertype' type-id='84a5c3d4' visibility='default' filepath='include/net/cfg80211.h' line='832' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='control_port_no_encrypt' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='830' column='1'/>
+          <var-decl name='control_port_no_encrypt' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='833' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='392'>
-          <var-decl name='control_port_over_nl80211' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='831' column='1'/>
+          <var-decl name='control_port_over_nl80211' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='834' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='wep_keys' type-id='706d79ff' visibility='default' filepath='include/net/cfg80211.h' line='832' column='1'/>
+          <var-decl name='wep_keys' type-id='706d79ff' visibility='default' filepath='include/net/cfg80211.h' line='835' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='wep_tx_key' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='833' column='1'/>
+          <var-decl name='wep_tx_key' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='836' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='psk' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='834' column='1'/>
+          <var-decl name='psk' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='837' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_auth_type' filepath='include/uapi/linux/nl80211.h' line='4344' column='1' id='f7dadf06'>
@@ -132753,15 +132834,15 @@
         <enumerator name='__NL80211_SMPS_AFTER_LAST' value='3'/>
         <enumerator name='NL80211_SMPS_MAX' value='2'/>
       </enum-decl>
-      <class-decl name='cfg80211_acl_data' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='882' column='1' id='88cc1885'>
+      <class-decl name='cfg80211_acl_data' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='885' column='1' id='88cc1885'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='acl_policy' type-id='79c93734' visibility='default' filepath='include/net/cfg80211.h' line='883' column='1'/>
+          <var-decl name='acl_policy' type-id='79c93734' visibility='default' filepath='include/net/cfg80211.h' line='886' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='n_acl_entries' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='884' column='1'/>
+          <var-decl name='n_acl_entries' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='887' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='mac_addrs' type-id='a099b86f' visibility='default' filepath='include/net/cfg80211.h' line='887' column='1'/>
+          <var-decl name='mac_addrs' type-id='a099b86f' visibility='default' filepath='include/net/cfg80211.h' line='890' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_acl_policy' filepath='include/uapi/linux/nl80211.h' line='5608' column='1' id='79c93734'>
@@ -132769,23 +132850,23 @@
         <enumerator name='NL80211_ACL_POLICY_ACCEPT_UNLESS_LISTED' value='0'/>
         <enumerator name='NL80211_ACL_POLICY_DENY_UNLESS_LISTED' value='1'/>
       </enum-decl>
-      <class-decl name='cfg80211_bitrate_mask' size-in-bits='864' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='893' column='1' id='febb0cbe'>
+      <class-decl name='cfg80211_bitrate_mask' size-in-bits='864' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='896' column='1' id='febb0cbe'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='control' type-id='b7bcaa67' visibility='default' filepath='include/net/cfg80211.h' line='899' column='1'/>
+          <var-decl name='control' type-id='b7bcaa67' visibility='default' filepath='include/net/cfg80211.h' line='902' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='__anonymous_struct__1' size-in-bits='288' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/net/cfg80211.h' line='894' column='1' id='5b11c736'>
+      <class-decl name='__anonymous_struct__1' size-in-bits='288' is-struct='yes' is-anonymous='yes' visibility='default' filepath='include/net/cfg80211.h' line='897' column='1' id='5b11c736'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='legacy' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='895' column='1'/>
+          <var-decl name='legacy' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='898' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='ht_mcs' type-id='097504df' visibility='default' filepath='include/net/cfg80211.h' line='896' column='1'/>
+          <var-decl name='ht_mcs' type-id='097504df' visibility='default' filepath='include/net/cfg80211.h' line='899' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='112'>
-          <var-decl name='vht_mcs' type-id='c24d1a13' visibility='default' filepath='include/net/cfg80211.h' line='897' column='1'/>
+          <var-decl name='vht_mcs' type-id='c24d1a13' visibility='default' filepath='include/net/cfg80211.h' line='900' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='gi' type-id='4170ee5e' visibility='default' filepath='include/net/cfg80211.h' line='898' column='1'/>
+          <var-decl name='gi' type-id='4170ee5e' visibility='default' filepath='include/net/cfg80211.h' line='901' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_txrate_gi' filepath='include/uapi/linux/nl80211.h' line='4491' column='1' id='4170ee5e'>
@@ -132794,90 +132875,90 @@
         <enumerator name='NL80211_TXRATE_FORCE_SGI' value='1'/>
         <enumerator name='NL80211_TXRATE_FORCE_LGI' value='2'/>
       </enum-decl>
-      <class-decl name='station_parameters' size-in-bits='1088' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1082' column='1' id='9367a320'>
+      <class-decl name='station_parameters' size-in-bits='1088' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1085' column='1' id='9367a320'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='supported_rates' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1083' column='1'/>
+          <var-decl name='supported_rates' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1086' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='vlan' type-id='68a2d05b' visibility='default' filepath='include/net/cfg80211.h' line='1084' column='1'/>
+          <var-decl name='vlan' type-id='68a2d05b' visibility='default' filepath='include/net/cfg80211.h' line='1087' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='sta_flags_mask' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1085' column='1'/>
+          <var-decl name='sta_flags_mask' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1088' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='sta_flags_set' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1085' column='1'/>
+          <var-decl name='sta_flags_set' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1088' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='sta_modify_mask' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1086' column='1'/>
+          <var-decl name='sta_modify_mask' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1089' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='224'>
-          <var-decl name='listen_interval' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1087' column='1'/>
+          <var-decl name='listen_interval' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1090' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='aid' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1088' column='1'/>
+          <var-decl name='aid' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1091' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='272'>
-          <var-decl name='peer_aid' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1089' column='1'/>
+          <var-decl name='peer_aid' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1092' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='288'>
-          <var-decl name='supported_rates_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1090' column='1'/>
+          <var-decl name='supported_rates_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1093' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='296'>
-          <var-decl name='plink_action' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1091' column='1'/>
+          <var-decl name='plink_action' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1094' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='304'>
-          <var-decl name='plink_state' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1092' column='1'/>
+          <var-decl name='plink_state' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1095' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='ht_capa' type-id='81f1a1a8' visibility='default' filepath='include/net/cfg80211.h' line='1093' column='1'/>
+          <var-decl name='ht_capa' type-id='81f1a1a8' visibility='default' filepath='include/net/cfg80211.h' line='1096' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='vht_capa' type-id='fffb07a4' visibility='default' filepath='include/net/cfg80211.h' line='1094' column='1'/>
+          <var-decl name='vht_capa' type-id='fffb07a4' visibility='default' filepath='include/net/cfg80211.h' line='1097' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='uapsd_queues' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1095' column='1'/>
+          <var-decl name='uapsd_queues' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1098' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='456'>
-          <var-decl name='max_sp' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1096' column='1'/>
+          <var-decl name='max_sp' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1099' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='480'>
-          <var-decl name='local_pm' type-id='8fbf0816' visibility='default' filepath='include/net/cfg80211.h' line='1097' column='1'/>
+          <var-decl name='local_pm' type-id='8fbf0816' visibility='default' filepath='include/net/cfg80211.h' line='1100' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='capability' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1098' column='1'/>
+          <var-decl name='capability' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1101' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='ext_capab' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1099' column='1'/>
+          <var-decl name='ext_capab' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1102' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='ext_capab_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1100' column='1'/>
+          <var-decl name='ext_capab_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1103' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='supported_channels' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1101' column='1'/>
+          <var-decl name='supported_channels' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1104' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='supported_channels_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1102' column='1'/>
+          <var-decl name='supported_channels_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1105' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='supported_oper_classes' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1103' column='1'/>
+          <var-decl name='supported_oper_classes' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1106' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='supported_oper_classes_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1104' column='1'/>
+          <var-decl name='supported_oper_classes_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1107' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='904'>
-          <var-decl name='opmode_notif' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1105' column='1'/>
+          <var-decl name='opmode_notif' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1108' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='912'>
-          <var-decl name='opmode_notif_used' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1106' column='1'/>
+          <var-decl name='opmode_notif_used' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1109' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='928'>
-          <var-decl name='support_p2p_ps' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1107' column='1'/>
+          <var-decl name='support_p2p_ps' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1110' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='he_capa' type-id='0bf1fd35' visibility='default' filepath='include/net/cfg80211.h' line='1108' column='1'/>
+          <var-decl name='he_capa' type-id='0bf1fd35' visibility='default' filepath='include/net/cfg80211.h' line='1111' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='he_capa_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1109' column='1'/>
+          <var-decl name='he_capa_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1112' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_mesh_power_mode' filepath='include/uapi/linux/nl80211.h' line='3908' column='1' id='8fbf0816'>
@@ -132889,174 +132970,174 @@
         <enumerator name='__NL80211_MESH_POWER_AFTER_LAST' value='4'/>
         <enumerator name='NL80211_MESH_POWER_MAX' value='3'/>
       </enum-decl>
-      <class-decl name='station_del_parameters' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1122' column='1' id='d8d4804a'>
+      <class-decl name='station_del_parameters' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1125' column='1' id='d8d4804a'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='mac' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1123' column='1'/>
+          <var-decl name='mac' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1126' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='subtype' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1124' column='1'/>
+          <var-decl name='subtype' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1127' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='80'>
-          <var-decl name='reason_code' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1125' column='1'/>
+          <var-decl name='reason_code' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1128' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='station_info' size-in-bits='1600' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1392' column='1' id='214ce930'>
+      <class-decl name='station_info' size-in-bits='1600' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1395' column='1' id='214ce930'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='filled' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1393' column='1'/>
+          <var-decl name='filled' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1396' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='connected_time' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1394' column='1'/>
+          <var-decl name='connected_time' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1397' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='inactive_time' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1395' column='1'/>
+          <var-decl name='inactive_time' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1398' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='rx_bytes' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1396' column='1'/>
+          <var-decl name='rx_bytes' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1399' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='tx_bytes' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1397' column='1'/>
+          <var-decl name='tx_bytes' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1400' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='llid' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1398' column='1'/>
+          <var-decl name='llid' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1401' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='272'>
-          <var-decl name='plid' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1399' column='1'/>
+          <var-decl name='plid' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1402' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='288'>
-          <var-decl name='plink_state' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1400' column='1'/>
+          <var-decl name='plink_state' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1403' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='296'>
-          <var-decl name='signal' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1401' column='1'/>
+          <var-decl name='signal' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1404' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='304'>
-          <var-decl name='signal_avg' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1402' column='1'/>
+          <var-decl name='signal_avg' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1405' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='312'>
-          <var-decl name='chains' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1404' column='1'/>
+          <var-decl name='chains' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1407' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='chain_signal' type-id='da004b74' visibility='default' filepath='include/net/cfg80211.h' line='1405' column='1'/>
+          <var-decl name='chain_signal' type-id='da004b74' visibility='default' filepath='include/net/cfg80211.h' line='1408' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='352'>
-          <var-decl name='chain_signal_avg' type-id='da004b74' visibility='default' filepath='include/net/cfg80211.h' line='1406' column='1'/>
+          <var-decl name='chain_signal_avg' type-id='da004b74' visibility='default' filepath='include/net/cfg80211.h' line='1409' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='txrate' type-id='5ece574c' visibility='default' filepath='include/net/cfg80211.h' line='1408' column='1'/>
+          <var-decl name='txrate' type-id='5ece574c' visibility='default' filepath='include/net/cfg80211.h' line='1411' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='464'>
-          <var-decl name='rxrate' type-id='5ece574c' visibility='default' filepath='include/net/cfg80211.h' line='1409' column='1'/>
+          <var-decl name='rxrate' type-id='5ece574c' visibility='default' filepath='include/net/cfg80211.h' line='1412' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='544'>
-          <var-decl name='rx_packets' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1410' column='1'/>
+          <var-decl name='rx_packets' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1413' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='tx_packets' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1411' column='1'/>
+          <var-decl name='tx_packets' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1414' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='608'>
-          <var-decl name='tx_retries' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1412' column='1'/>
+          <var-decl name='tx_retries' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1415' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='tx_failed' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1413' column='1'/>
+          <var-decl name='tx_failed' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1416' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='672'>
-          <var-decl name='rx_dropped_misc' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1414' column='1'/>
+          <var-decl name='rx_dropped_misc' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1417' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='bss_param' type-id='ca45acc3' visibility='default' filepath='include/net/cfg80211.h' line='1415' column='1'/>
+          <var-decl name='bss_param' type-id='ca45acc3' visibility='default' filepath='include/net/cfg80211.h' line='1418' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='736'>
-          <var-decl name='sta_flags' type-id='8d118865' visibility='default' filepath='include/net/cfg80211.h' line='1416' column='1'/>
+          <var-decl name='sta_flags' type-id='8d118865' visibility='default' filepath='include/net/cfg80211.h' line='1419' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='800'>
-          <var-decl name='generation' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1418' column='1'/>
+          <var-decl name='generation' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1421' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='assoc_req_ies' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1420' column='1'/>
+          <var-decl name='assoc_req_ies' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1423' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='assoc_req_ies_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='1421' column='1'/>
+          <var-decl name='assoc_req_ies_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='1424' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='beacon_loss_count' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1423' column='1'/>
+          <var-decl name='beacon_loss_count' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1426' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='t_offset' type-id='9b7c55ef' visibility='default' filepath='include/net/cfg80211.h' line='1424' column='1'/>
+          <var-decl name='t_offset' type-id='9b7c55ef' visibility='default' filepath='include/net/cfg80211.h' line='1427' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='local_pm' type-id='8fbf0816' visibility='default' filepath='include/net/cfg80211.h' line='1425' column='1'/>
+          <var-decl name='local_pm' type-id='8fbf0816' visibility='default' filepath='include/net/cfg80211.h' line='1428' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1120'>
-          <var-decl name='peer_pm' type-id='8fbf0816' visibility='default' filepath='include/net/cfg80211.h' line='1426' column='1'/>
+          <var-decl name='peer_pm' type-id='8fbf0816' visibility='default' filepath='include/net/cfg80211.h' line='1429' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='nonpeer_pm' type-id='8fbf0816' visibility='default' filepath='include/net/cfg80211.h' line='1427' column='1'/>
+          <var-decl name='nonpeer_pm' type-id='8fbf0816' visibility='default' filepath='include/net/cfg80211.h' line='1430' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1184'>
-          <var-decl name='expected_throughput' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1429' column='1'/>
+          <var-decl name='expected_throughput' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1432' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='rx_beacon' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1431' column='1'/>
+          <var-decl name='rx_beacon' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1434' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='rx_duration' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1432' column='1'/>
+          <var-decl name='rx_duration' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1435' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='rx_beacon_signal_avg' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1433' column='1'/>
+          <var-decl name='rx_beacon_signal_avg' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1436' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='pertid' type-id='718fbcad' visibility='default' filepath='include/net/cfg80211.h' line='1434' column='1'/>
+          <var-decl name='pertid' type-id='718fbcad' visibility='default' filepath='include/net/cfg80211.h' line='1437' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1472'>
-          <var-decl name='ack_signal' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1435' column='1'/>
+          <var-decl name='ack_signal' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1438' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1480'>
-          <var-decl name='avg_ack_signal' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1436' column='1'/>
+          <var-decl name='avg_ack_signal' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1439' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1504'>
-          <var-decl name='rx_mpdu_count' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1438' column='1'/>
+          <var-decl name='rx_mpdu_count' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1441' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1536'>
-          <var-decl name='fcs_err_count' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1439' column='1'/>
+          <var-decl name='fcs_err_count' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1442' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='rate_info' size-in-bits='80' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1235' column='1' id='5ece574c'>
+      <class-decl name='rate_info' size-in-bits='80' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1238' column='1' id='5ece574c'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='flags' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1236' column='1'/>
+          <var-decl name='flags' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1239' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8'>
-          <var-decl name='mcs' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1237' column='1'/>
+          <var-decl name='mcs' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1240' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='legacy' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1238' column='1'/>
+          <var-decl name='legacy' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1241' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='nss' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1239' column='1'/>
+          <var-decl name='nss' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1242' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='40'>
-          <var-decl name='bw' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1240' column='1'/>
+          <var-decl name='bw' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1243' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='48'>
-          <var-decl name='he_gi' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1241' column='1'/>
+          <var-decl name='he_gi' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1244' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='56'>
-          <var-decl name='he_dcm' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1242' column='1'/>
+          <var-decl name='he_dcm' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1245' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='he_ru_alloc' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1243' column='1'/>
+          <var-decl name='he_ru_alloc' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1246' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='72'>
-          <var-decl name='n_bonded_ch' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1244' column='1'/>
+          <var-decl name='n_bonded_ch' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1247' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='sta_bss_parameters' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1272' column='1' id='ca45acc3'>
+      <class-decl name='sta_bss_parameters' size-in-bits='32' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1275' column='1' id='ca45acc3'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='flags' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1273' column='1'/>
+          <var-decl name='flags' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1276' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8'>
-          <var-decl name='dtim_period' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1274' column='1'/>
+          <var-decl name='dtim_period' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1277' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='beacon_interval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1275' column='1'/>
+          <var-decl name='beacon_interval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1278' column='1'/>
         </data-member>
       </class-decl>
       <class-decl name='nl80211_sta_flag_update' size-in-bits='64' is-struct='yes' visibility='default' filepath='include/uapi/linux/nl80211.h' line='2994' column='1' id='8d118865'>
@@ -133067,287 +133148,287 @@
           <var-decl name='set' type-id='3f1a6b60' visibility='default' filepath='include/uapi/linux/nl80211.h' line='2996' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_tid_stats' size-in-bits='704' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1320' column='1' id='af09339d'>
+      <class-decl name='cfg80211_tid_stats' size-in-bits='704' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1323' column='1' id='af09339d'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='filled' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1321' column='1'/>
+          <var-decl name='filled' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1324' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='rx_msdu' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1322' column='1'/>
+          <var-decl name='rx_msdu' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1325' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='tx_msdu' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1323' column='1'/>
+          <var-decl name='tx_msdu' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1326' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='tx_msdu_retries' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1324' column='1'/>
+          <var-decl name='tx_msdu_retries' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1327' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='tx_msdu_failed' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1325' column='1'/>
+          <var-decl name='tx_msdu_failed' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1328' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='txq_stats' type-id='14305947' visibility='default' filepath='include/net/cfg80211.h' line='1326' column='1'/>
+          <var-decl name='txq_stats' type-id='14305947' visibility='default' filepath='include/net/cfg80211.h' line='1329' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_txq_stats' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1294' column='1' id='14305947'>
+      <class-decl name='cfg80211_txq_stats' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1297' column='1' id='14305947'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='filled' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1295' column='1'/>
+          <var-decl name='filled' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1298' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='backlog_bytes' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1296' column='1'/>
+          <var-decl name='backlog_bytes' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1299' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='backlog_packets' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1297' column='1'/>
+          <var-decl name='backlog_packets' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1300' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='flows' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1298' column='1'/>
+          <var-decl name='flows' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1301' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='drops' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1299' column='1'/>
+          <var-decl name='drops' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1302' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='ecn_marks' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1300' column='1'/>
+          <var-decl name='ecn_marks' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1303' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='overlimit' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1301' column='1'/>
+          <var-decl name='overlimit' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1304' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='224'>
-          <var-decl name='overmemory' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1302' column='1'/>
+          <var-decl name='overmemory' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1305' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='collisions' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1303' column='1'/>
+          <var-decl name='collisions' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1306' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='288'>
-          <var-decl name='tx_bytes' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1304' column='1'/>
+          <var-decl name='tx_bytes' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1307' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='tx_packets' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1305' column='1'/>
+          <var-decl name='tx_packets' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1308' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='352'>
-          <var-decl name='max_flows' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1306' column='1'/>
+          <var-decl name='max_flows' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1309' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='mpath_info' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1530' column='1' id='1cac2bf4'>
+      <class-decl name='mpath_info' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1533' column='1' id='1cac2bf4'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='filled' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1531' column='1'/>
+          <var-decl name='filled' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1534' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='frame_qlen' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1532' column='1'/>
+          <var-decl name='frame_qlen' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1535' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='sn' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1533' column='1'/>
+          <var-decl name='sn' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1536' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='metric' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1534' column='1'/>
+          <var-decl name='metric' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1537' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='exptime' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1535' column='1'/>
+          <var-decl name='exptime' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1538' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='discovery_timeout' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1536' column='1'/>
+          <var-decl name='discovery_timeout' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1539' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='discovery_retries' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1537' column='1'/>
+          <var-decl name='discovery_retries' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1540' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='200'>
-          <var-decl name='flags' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1538' column='1'/>
+          <var-decl name='flags' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1541' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='224'>
-          <var-decl name='generation' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1540' column='1'/>
+          <var-decl name='generation' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1543' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='mesh_config' size-in-bits='576' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1644' column='1' id='50718ec3'>
+      <class-decl name='mesh_config' size-in-bits='576' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1647' column='1' id='50718ec3'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='dot11MeshRetryTimeout' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1645' column='1'/>
+          <var-decl name='dot11MeshRetryTimeout' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1648' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='16'>
-          <var-decl name='dot11MeshConfirmTimeout' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1646' column='1'/>
+          <var-decl name='dot11MeshConfirmTimeout' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1649' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='dot11MeshHoldingTimeout' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1647' column='1'/>
+          <var-decl name='dot11MeshHoldingTimeout' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1650' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='48'>
-          <var-decl name='dot11MeshMaxPeerLinks' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1648' column='1'/>
+          <var-decl name='dot11MeshMaxPeerLinks' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1651' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='dot11MeshMaxRetries' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1649' column='1'/>
+          <var-decl name='dot11MeshMaxRetries' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1652' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='72'>
-          <var-decl name='dot11MeshTTL' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1650' column='1'/>
+          <var-decl name='dot11MeshTTL' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1653' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='80'>
-          <var-decl name='element_ttl' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1651' column='1'/>
+          <var-decl name='element_ttl' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1654' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='88'>
-          <var-decl name='auto_open_plinks' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1652' column='1'/>
+          <var-decl name='auto_open_plinks' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1655' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='dot11MeshNbrOffsetMaxNeighbor' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1653' column='1'/>
+          <var-decl name='dot11MeshNbrOffsetMaxNeighbor' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1656' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='dot11MeshHWMPmaxPREQretries' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1654' column='1'/>
+          <var-decl name='dot11MeshHWMPmaxPREQretries' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1657' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='160'>
-          <var-decl name='path_refresh_time' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1655' column='1'/>
+          <var-decl name='path_refresh_time' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1658' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='min_discovery_timeout' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1656' column='1'/>
+          <var-decl name='min_discovery_timeout' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1659' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='224'>
-          <var-decl name='dot11MeshHWMPactivePathTimeout' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1657' column='1'/>
+          <var-decl name='dot11MeshHWMPactivePathTimeout' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1660' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='dot11MeshHWMPpreqMinInterval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1658' column='1'/>
+          <var-decl name='dot11MeshHWMPpreqMinInterval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1661' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='272'>
-          <var-decl name='dot11MeshHWMPperrMinInterval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1659' column='1'/>
+          <var-decl name='dot11MeshHWMPperrMinInterval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1662' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='288'>
-          <var-decl name='dot11MeshHWMPnetDiameterTraversalTime' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1660' column='1'/>
+          <var-decl name='dot11MeshHWMPnetDiameterTraversalTime' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1663' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='304'>
-          <var-decl name='dot11MeshHWMPRootMode' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1661' column='1'/>
+          <var-decl name='dot11MeshHWMPRootMode' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1664' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='dot11MeshHWMPRannInterval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1662' column='1'/>
+          <var-decl name='dot11MeshHWMPRannInterval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1665' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='336'>
-          <var-decl name='dot11MeshGateAnnouncementProtocol' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1663' column='1'/>
+          <var-decl name='dot11MeshGateAnnouncementProtocol' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1666' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='344'>
-          <var-decl name='dot11MeshForwarding' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1664' column='1'/>
+          <var-decl name='dot11MeshForwarding' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1667' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='352'>
-          <var-decl name='rssi_threshold' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='1665' column='1'/>
+          <var-decl name='rssi_threshold' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='1668' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='ht_opmode' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1666' column='1'/>
+          <var-decl name='ht_opmode' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1669' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='416'>
-          <var-decl name='dot11MeshHWMPactivePathToRootTimeout' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1667' column='1'/>
+          <var-decl name='dot11MeshHWMPactivePathToRootTimeout' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1670' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='dot11MeshHWMProotInterval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1668' column='1'/>
+          <var-decl name='dot11MeshHWMProotInterval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1671' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='464'>
-          <var-decl name='dot11MeshHWMPconfirmationInterval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1669' column='1'/>
+          <var-decl name='dot11MeshHWMPconfirmationInterval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1672' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='480'>
-          <var-decl name='power_mode' type-id='8fbf0816' visibility='default' filepath='include/net/cfg80211.h' line='1670' column='1'/>
+          <var-decl name='power_mode' type-id='8fbf0816' visibility='default' filepath='include/net/cfg80211.h' line='1673' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='dot11MeshAwakeWindowDuration' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1671' column='1'/>
+          <var-decl name='dot11MeshAwakeWindowDuration' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1674' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='544'>
-          <var-decl name='plink_timeout' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1672' column='1'/>
+          <var-decl name='plink_timeout' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1675' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='mesh_setup' size-in-bits='1536' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1702' column='1' id='d5e39a52'>
+      <class-decl name='mesh_setup' size-in-bits='1536' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1705' column='1' id='d5e39a52'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='1703' column='1'/>
+          <var-decl name='chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='1706' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='mesh_id' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1704' column='1'/>
+          <var-decl name='mesh_id' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1707' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='mesh_id_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1705' column='1'/>
+          <var-decl name='mesh_id_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1708' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='328'>
-          <var-decl name='sync_method' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1706' column='1'/>
+          <var-decl name='sync_method' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1709' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='336'>
-          <var-decl name='path_sel_proto' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1707' column='1'/>
+          <var-decl name='path_sel_proto' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1710' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='344'>
-          <var-decl name='path_metric' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1708' column='1'/>
+          <var-decl name='path_metric' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1711' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='352'>
-          <var-decl name='auth_id' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1709' column='1'/>
+          <var-decl name='auth_id' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1712' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1710' column='1'/>
+          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1713' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='ie_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1711' column='1'/>
+          <var-decl name='ie_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1714' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='456'>
-          <var-decl name='is_authenticated' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1712' column='1'/>
+          <var-decl name='is_authenticated' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1715' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='464'>
-          <var-decl name='is_secure' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1713' column='1'/>
+          <var-decl name='is_secure' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1716' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='472'>
-          <var-decl name='user_mpm' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1714' column='1'/>
+          <var-decl name='user_mpm' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1717' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='480'>
-          <var-decl name='dtim_period' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1715' column='1'/>
+          <var-decl name='dtim_period' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1718' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='496'>
-          <var-decl name='beacon_interval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1716' column='1'/>
+          <var-decl name='beacon_interval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1719' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='mcast_rate' type-id='e024279b' visibility='default' filepath='include/net/cfg80211.h' line='1717' column='1'/>
+          <var-decl name='mcast_rate' type-id='e024279b' visibility='default' filepath='include/net/cfg80211.h' line='1720' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='608'>
-          <var-decl name='basic_rates' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1718' column='1'/>
+          <var-decl name='basic_rates' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1721' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='beacon_rate' type-id='febb0cbe' visibility='default' filepath='include/net/cfg80211.h' line='1719' column='1'/>
+          <var-decl name='beacon_rate' type-id='febb0cbe' visibility='default' filepath='include/net/cfg80211.h' line='1722' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1504'>
-          <var-decl name='userspace_handles_dfs' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1720' column='1'/>
+          <var-decl name='userspace_handles_dfs' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1723' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1512'>
-          <var-decl name='control_port_over_nl80211' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1721' column='1'/>
+          <var-decl name='control_port_over_nl80211' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1724' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='ocb_setup' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1730' column='1' id='8a88d915'>
+      <class-decl name='ocb_setup' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1733' column='1' id='8a88d915'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='1731' column='1'/>
+          <var-decl name='chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='1734' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='bss_parameters' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1563' column='1' id='5603c5c0'>
+      <class-decl name='bss_parameters' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1566' column='1' id='5603c5c0'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='use_cts_prot' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1564' column='1'/>
+          <var-decl name='use_cts_prot' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1567' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='use_short_preamble' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1565' column='1'/>
+          <var-decl name='use_short_preamble' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1568' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='use_short_slot_time' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1566' column='1'/>
+          <var-decl name='use_short_slot_time' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1569' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='basic_rates' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1567' column='1'/>
+          <var-decl name='basic_rates' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1570' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='basic_rates_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1568' column='1'/>
+          <var-decl name='basic_rates_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1571' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='224'>
-          <var-decl name='ap_isolate' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1569' column='1'/>
+          <var-decl name='ap_isolate' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1572' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ht_opmode' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1570' column='1'/>
+          <var-decl name='ht_opmode' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1573' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='288'>
-          <var-decl name='p2p_ctwindow' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1571' column='1'/>
+          <var-decl name='p2p_ctwindow' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1574' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='296'>
-          <var-decl name='p2p_opp_ps' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1571' column='1'/>
+          <var-decl name='p2p_opp_ps' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='1574' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='ieee80211_txq_params' size-in-bits='96' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1744' column='1' id='f16b7aee'>
+      <class-decl name='ieee80211_txq_params' size-in-bits='96' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1747' column='1' id='f16b7aee'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='ac' type-id='3ee1f5af' visibility='default' filepath='include/net/cfg80211.h' line='1745' column='1'/>
+          <var-decl name='ac' type-id='3ee1f5af' visibility='default' filepath='include/net/cfg80211.h' line='1748' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='txop' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1746' column='1'/>
+          <var-decl name='txop' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1749' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='48'>
-          <var-decl name='cwmin' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1747' column='1'/>
+          <var-decl name='cwmin' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1750' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='cwmax' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1748' column='1'/>
+          <var-decl name='cwmax' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1751' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='80'>
-          <var-decl name='aifs' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1749' column='1'/>
+          <var-decl name='aifs' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='1752' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_ac' filepath='include/uapi/linux/nl80211.h' line='4154' column='1' id='3ee1f5af'>
@@ -133358,285 +133439,285 @@
         <enumerator name='NL80211_AC_BK' value='3'/>
         <enumerator name='NL80211_NUM_ACS' value='4'/>
       </enum-decl>
-      <class-decl name='cfg80211_scan_request' size-in-bits='1088' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1829' column='1' id='6834abc3'>
+      <class-decl name='cfg80211_scan_request' size-in-bits='1088' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1832' column='1' id='6834abc3'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='ssids' type-id='a1fa7fb7' visibility='default' filepath='include/net/cfg80211.h' line='1830' column='1'/>
+          <var-decl name='ssids' type-id='a1fa7fb7' visibility='default' filepath='include/net/cfg80211.h' line='1833' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='n_ssids' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1831' column='1'/>
+          <var-decl name='n_ssids' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='1834' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='n_channels' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1832' column='1'/>
+          <var-decl name='n_channels' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1835' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='scan_width' type-id='95d46034' visibility='default' filepath='include/net/cfg80211.h' line='1833' column='1'/>
+          <var-decl name='scan_width' type-id='95d46034' visibility='default' filepath='include/net/cfg80211.h' line='1836' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1834' column='1'/>
+          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='1837' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='1835' column='1'/>
+          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='1838' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='duration' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1836' column='1'/>
+          <var-decl name='duration' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='1839' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='336'>
-          <var-decl name='duration_mandatory' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1837' column='1'/>
+          <var-decl name='duration_mandatory' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1840' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='352'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1838' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='1841' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='rates' type-id='1c745afe' visibility='default' filepath='include/net/cfg80211.h' line='1840' column='1'/>
+          <var-decl name='rates' type-id='1c745afe' visibility='default' filepath='include/net/cfg80211.h' line='1843' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='wdev' type-id='63c7e8e1' visibility='default' filepath='include/net/cfg80211.h' line='1842' column='1'/>
+          <var-decl name='wdev' type-id='63c7e8e1' visibility='default' filepath='include/net/cfg80211.h' line='1845' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='mac_addr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1844' column='1'/>
+          <var-decl name='mac_addr' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1847' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='624'>
-          <var-decl name='mac_addr_mask' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1845' column='1'/>
+          <var-decl name='mac_addr_mask' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1848' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='672'>
-          <var-decl name='bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1846' column='1'/>
+          <var-decl name='bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1849' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='wiphy' type-id='666fb412' visibility='default' filepath='include/net/cfg80211.h' line='1849' column='1'/>
+          <var-decl name='wiphy' type-id='666fb412' visibility='default' filepath='include/net/cfg80211.h' line='1852' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='scan_start' type-id='7359adad' visibility='default' filepath='include/net/cfg80211.h' line='1850' column='1'/>
+          <var-decl name='scan_start' type-id='7359adad' visibility='default' filepath='include/net/cfg80211.h' line='1853' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='info' type-id='b1493ece' visibility='default' filepath='include/net/cfg80211.h' line='1851' column='1'/>
+          <var-decl name='info' type-id='b1493ece' visibility='default' filepath='include/net/cfg80211.h' line='1854' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='notified' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1852' column='1'/>
+          <var-decl name='notified' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1855' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1032'>
-          <var-decl name='no_cck' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1853' column='1'/>
+          <var-decl name='no_cck' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1856' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='channels' type-id='14cad687' visibility='default' filepath='include/net/cfg80211.h' line='1856' column='1'/>
+          <var-decl name='channels' type-id='14cad687' visibility='default' filepath='include/net/cfg80211.h' line='1859' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_scan_info' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1794' column='1' id='b1493ece'>
+      <class-decl name='cfg80211_scan_info' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='1797' column='1' id='b1493ece'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='scan_start_tsf' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1795' column='1'/>
+          <var-decl name='scan_start_tsf' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='1798' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='tsf_bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1796' column='1'/>
+          <var-decl name='tsf_bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='1799' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='112'>
-          <var-decl name='aborted' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1797' column='1'/>
+          <var-decl name='aborted' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='1800' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_auth_request' size-in-bits='512' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2147' column='1' id='5668e288'>
+      <class-decl name='cfg80211_auth_request' size-in-bits='512' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2150' column='1' id='5668e288'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='2148' column='1'/>
+          <var-decl name='bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='2151' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2149' column='1'/>
+          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2152' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2150' column='1'/>
+          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2153' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='auth_type' type-id='f7dadf06' visibility='default' filepath='include/net/cfg80211.h' line='2151' column='1'/>
+          <var-decl name='auth_type' type-id='f7dadf06' visibility='default' filepath='include/net/cfg80211.h' line='2154' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='key' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2152' column='1'/>
+          <var-decl name='key' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2155' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='key_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2153' column='1'/>
+          <var-decl name='key_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2156' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='328'>
-          <var-decl name='key_idx' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2153' column='1'/>
+          <var-decl name='key_idx' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2156' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='auth_data' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2154' column='1'/>
+          <var-decl name='auth_data' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2157' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='auth_data_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2155' column='1'/>
+          <var-decl name='auth_data_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2158' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_assoc_request' size-in-bits='1792' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2208' column='1' id='63cd0279'>
+      <class-decl name='cfg80211_assoc_request' size-in-bits='1792' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2211' column='1' id='63cd0279'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='2209' column='1'/>
+          <var-decl name='bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='2212' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2210' column='1'/>
+          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2213' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='prev_bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2210' column='1'/>
+          <var-decl name='prev_bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2213' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2211' column='1'/>
+          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2214' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='crypto' type-id='f81bbd3b' visibility='default' filepath='include/net/cfg80211.h' line='2212' column='1'/>
+          <var-decl name='crypto' type-id='f81bbd3b' visibility='default' filepath='include/net/cfg80211.h' line='2215' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='896'>
-          <var-decl name='use_mfp' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2213' column='1'/>
+          <var-decl name='use_mfp' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2216' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='928'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2214' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2217' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='960'>
-          <var-decl name='ht_capa' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2215' column='1'/>
+          <var-decl name='ht_capa' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2218' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1168'>
-          <var-decl name='ht_capa_mask' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2216' column='1'/>
+          <var-decl name='ht_capa_mask' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2219' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1376'>
-          <var-decl name='vht_capa' type-id='2eec6999' visibility='default' filepath='include/net/cfg80211.h' line='2217' column='1'/>
+          <var-decl name='vht_capa' type-id='2eec6999' visibility='default' filepath='include/net/cfg80211.h' line='2220' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1472'>
-          <var-decl name='vht_capa_mask' type-id='2eec6999' visibility='default' filepath='include/net/cfg80211.h' line='2217' column='1'/>
+          <var-decl name='vht_capa_mask' type-id='2eec6999' visibility='default' filepath='include/net/cfg80211.h' line='2220' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1600'>
-          <var-decl name='fils_kek' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2218' column='1'/>
+          <var-decl name='fils_kek' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2221' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1664'>
-          <var-decl name='fils_kek_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2219' column='1'/>
+          <var-decl name='fils_kek_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2222' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1728'>
-          <var-decl name='fils_nonces' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2220' column='1'/>
+          <var-decl name='fils_nonces' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2223' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_deauth_request' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2236' column='1' id='93d4232f'>
+      <class-decl name='cfg80211_deauth_request' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2239' column='1' id='93d4232f'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2237' column='1'/>
+          <var-decl name='bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2240' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2238' column='1'/>
+          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2241' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2239' column='1'/>
+          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2242' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='reason_code' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2240' column='1'/>
+          <var-decl name='reason_code' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2243' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='208'>
-          <var-decl name='local_state_change' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2241' column='1'/>
+          <var-decl name='local_state_change' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2244' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_disassoc_request' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2257' column='1' id='1b35ffb5'>
+      <class-decl name='cfg80211_disassoc_request' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2260' column='1' id='1b35ffb5'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='2258' column='1'/>
+          <var-decl name='bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='2261' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2259' column='1'/>
+          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2262' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2260' column='1'/>
+          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2263' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='reason_code' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2261' column='1'/>
+          <var-decl name='reason_code' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2264' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='208'>
-          <var-decl name='local_state_change' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2262' column='1'/>
+          <var-decl name='local_state_change' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2265' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_connect_params' size-in-bits='2816' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2400' column='1' id='1291defd'>
+      <class-decl name='cfg80211_connect_params' size-in-bits='2816' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2403' column='1' id='1291defd'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='channel' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2401' column='1'/>
+          <var-decl name='channel' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2404' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='channel_hint' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2402' column='1'/>
+          <var-decl name='channel_hint' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2405' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2403' column='1'/>
+          <var-decl name='bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2406' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='bssid_hint' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2404' column='1'/>
+          <var-decl name='bssid_hint' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2407' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2405' column='1'/>
+          <var-decl name='ssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2408' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='ssid_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2406' column='1'/>
+          <var-decl name='ssid_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2409' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='auth_type' type-id='f7dadf06' visibility='default' filepath='include/net/cfg80211.h' line='2407' column='1'/>
+          <var-decl name='auth_type' type-id='f7dadf06' visibility='default' filepath='include/net/cfg80211.h' line='2410' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2408' column='1'/>
+          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2411' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2409' column='1'/>
+          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2412' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='privacy' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2410' column='1'/>
+          <var-decl name='privacy' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2413' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='608'>
-          <var-decl name='mfp' type-id='dfb2486c' visibility='default' filepath='include/net/cfg80211.h' line='2411' column='1'/>
+          <var-decl name='mfp' type-id='dfb2486c' visibility='default' filepath='include/net/cfg80211.h' line='2414' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='crypto' type-id='f81bbd3b' visibility='default' filepath='include/net/cfg80211.h' line='2412' column='1'/>
+          <var-decl name='crypto' type-id='f81bbd3b' visibility='default' filepath='include/net/cfg80211.h' line='2415' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1280'>
-          <var-decl name='key' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2413' column='1'/>
+          <var-decl name='key' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2416' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1344'>
-          <var-decl name='key_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2414' column='1'/>
+          <var-decl name='key_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2417' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1352'>
-          <var-decl name='key_idx' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2414' column='1'/>
+          <var-decl name='key_idx' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2417' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1376'>
-          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2415' column='1'/>
+          <var-decl name='flags' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2418' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1408'>
-          <var-decl name='bg_scan_period' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2416' column='1'/>
+          <var-decl name='bg_scan_period' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2419' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1440'>
-          <var-decl name='ht_capa' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2417' column='1'/>
+          <var-decl name='ht_capa' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2420' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1648'>
-          <var-decl name='ht_capa_mask' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2418' column='1'/>
+          <var-decl name='ht_capa_mask' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2421' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1856'>
-          <var-decl name='vht_capa' type-id='2eec6999' visibility='default' filepath='include/net/cfg80211.h' line='2419' column='1'/>
+          <var-decl name='vht_capa' type-id='2eec6999' visibility='default' filepath='include/net/cfg80211.h' line='2422' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1952'>
-          <var-decl name='vht_capa_mask' type-id='2eec6999' visibility='default' filepath='include/net/cfg80211.h' line='2420' column='1'/>
+          <var-decl name='vht_capa_mask' type-id='2eec6999' visibility='default' filepath='include/net/cfg80211.h' line='2423' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2048'>
-          <var-decl name='pbss' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2421' column='1'/>
+          <var-decl name='pbss' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2424' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2080'>
-          <var-decl name='bss_select' type-id='d24a933d' visibility='default' filepath='include/net/cfg80211.h' line='2422' column='1'/>
+          <var-decl name='bss_select' type-id='d24a933d' visibility='default' filepath='include/net/cfg80211.h' line='2425' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2176'>
-          <var-decl name='prev_bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2423' column='1'/>
+          <var-decl name='prev_bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2426' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2240'>
-          <var-decl name='fils_erp_username' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2424' column='1'/>
+          <var-decl name='fils_erp_username' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2427' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2304'>
-          <var-decl name='fils_erp_username_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2425' column='1'/>
+          <var-decl name='fils_erp_username_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2428' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2368'>
-          <var-decl name='fils_erp_realm' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2426' column='1'/>
+          <var-decl name='fils_erp_realm' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2429' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2432'>
-          <var-decl name='fils_erp_realm_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2427' column='1'/>
+          <var-decl name='fils_erp_realm_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2430' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2496'>
-          <var-decl name='fils_erp_next_seq_num' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2428' column='1'/>
+          <var-decl name='fils_erp_next_seq_num' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2431' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2560'>
-          <var-decl name='fils_erp_rrk' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2429' column='1'/>
+          <var-decl name='fils_erp_rrk' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2432' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2624'>
-          <var-decl name='fils_erp_rrk_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2430' column='1'/>
+          <var-decl name='fils_erp_rrk_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2433' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2688'>
-          <var-decl name='want_1x' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2431' column='1'/>
+          <var-decl name='want_1x' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2434' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2720'>
-          <var-decl name='edmg' type-id='d87e6929' visibility='default' filepath='include/net/cfg80211.h' line='2432' column='1'/>
+          <var-decl name='edmg' type-id='d87e6929' visibility='default' filepath='include/net/cfg80211.h' line='2435' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_mfp' filepath='include/uapi/linux/nl80211.h' line='4381' column='1' id='dfb2486c'>
@@ -133645,12 +133726,12 @@
         <enumerator name='NL80211_MFP_REQUIRED' value='1'/>
         <enumerator name='NL80211_MFP_OPTIONAL' value='2'/>
       </enum-decl>
-      <class-decl name='cfg80211_bss_selection' size-in-bits='96' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2329' column='1' id='d24a933d'>
+      <class-decl name='cfg80211_bss_selection' size-in-bits='96' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2332' column='1' id='d24a933d'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='behaviour' type-id='10fd9108' visibility='default' filepath='include/net/cfg80211.h' line='2330' column='1'/>
+          <var-decl name='behaviour' type-id='10fd9108' visibility='default' filepath='include/net/cfg80211.h' line='2333' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='param' type-id='0532d6f6' visibility='default' filepath='include/net/cfg80211.h' line='2334' column='1'/>
+          <var-decl name='param' type-id='0532d6f6' visibility='default' filepath='include/net/cfg80211.h' line='2337' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_bss_select_attr' filepath='include/uapi/linux/nl80211.h' line='5822' column='1' id='10fd9108'>
@@ -133662,68 +133743,68 @@
         <enumerator name='__NL80211_BSS_SELECT_ATTR_AFTER_LAST' value='4'/>
         <enumerator name='NL80211_BSS_SELECT_ATTR_MAX' value='3'/>
       </enum-decl>
-      <union-decl name='__anonymous_union__3' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/net/cfg80211.h' line='2331' column='1' id='0532d6f6'>
+      <union-decl name='__anonymous_union__3' size-in-bits='64' is-anonymous='yes' visibility='default' filepath='include/net/cfg80211.h' line='2334' column='1' id='0532d6f6'>
         <data-member access='public'>
-          <var-decl name='band_pref' type-id='3eaa0294' visibility='default' filepath='include/net/cfg80211.h' line='2332' column='1'/>
+          <var-decl name='band_pref' type-id='3eaa0294' visibility='default' filepath='include/net/cfg80211.h' line='2335' column='1'/>
         </data-member>
         <data-member access='public'>
-          <var-decl name='adjust' type-id='5da08e25' visibility='default' filepath='include/net/cfg80211.h' line='2333' column='1'/>
+          <var-decl name='adjust' type-id='5da08e25' visibility='default' filepath='include/net/cfg80211.h' line='2336' column='1'/>
         </data-member>
       </union-decl>
-      <class-decl name='cfg80211_ibss_params' size-in-bits='1216' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2301' column='1' id='0bac05a4'>
+      <class-decl name='cfg80211_ibss_params' size-in-bits='1216' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2304' column='1' id='0bac05a4'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='ssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2302' column='1'/>
+          <var-decl name='ssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2305' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2303' column='1'/>
+          <var-decl name='bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2306' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='2304' column='1'/>
+          <var-decl name='chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='2307' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2305' column='1'/>
+          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2308' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='ssid_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2306' column='1'/>
+          <var-decl name='ssid_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2309' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='456'>
-          <var-decl name='ie_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2306' column='1'/>
+          <var-decl name='ie_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2309' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='464'>
-          <var-decl name='beacon_interval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2307' column='1'/>
+          <var-decl name='beacon_interval' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2310' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='480'>
-          <var-decl name='basic_rates' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2308' column='1'/>
+          <var-decl name='basic_rates' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2311' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='channel_fixed' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2309' column='1'/>
+          <var-decl name='channel_fixed' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2312' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='520'>
-          <var-decl name='privacy' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2310' column='1'/>
+          <var-decl name='privacy' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2313' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='528'>
-          <var-decl name='control_port' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2311' column='1'/>
+          <var-decl name='control_port' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2314' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='536'>
-          <var-decl name='control_port_over_nl80211' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2312' column='1'/>
+          <var-decl name='control_port_over_nl80211' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2315' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='544'>
-          <var-decl name='userspace_handles_dfs' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2313' column='1'/>
+          <var-decl name='userspace_handles_dfs' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2316' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='mcast_rate' type-id='e024279b' visibility='default' filepath='include/net/cfg80211.h' line='2314' column='1'/>
+          <var-decl name='mcast_rate' type-id='e024279b' visibility='default' filepath='include/net/cfg80211.h' line='2317' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='672'>
-          <var-decl name='ht_capa' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2315' column='1'/>
+          <var-decl name='ht_capa' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2318' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='880'>
-          <var-decl name='ht_capa_mask' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2316' column='1'/>
+          <var-decl name='ht_capa_mask' type-id='16e7829f' visibility='default' filepath='include/net/cfg80211.h' line='2319' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='wep_keys' type-id='706d79ff' visibility='default' filepath='include/net/cfg80211.h' line='2317' column='1'/>
+          <var-decl name='wep_keys' type-id='706d79ff' visibility='default' filepath='include/net/cfg80211.h' line='2320' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='wep_tx_key' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2318' column='1'/>
+          <var-decl name='wep_tx_key' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2321' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_tx_power_setting' filepath='include/uapi/linux/nl80211.h' line='4594' column='1' id='d46e3e96'>
@@ -133732,99 +133813,99 @@
         <enumerator name='NL80211_TX_POWER_LIMITED' value='1'/>
         <enumerator name='NL80211_TX_POWER_FIXED' value='2'/>
       </enum-decl>
-      <class-decl name='survey_info' size-in-bits='512' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='783' column='1' id='8cd7231c'>
+      <class-decl name='survey_info' size-in-bits='512' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='786' column='1' id='8cd7231c'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='channel' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='784' column='1'/>
+          <var-decl name='channel' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='787' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='time' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='785' column='1'/>
+          <var-decl name='time' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='788' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='time_busy' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='786' column='1'/>
+          <var-decl name='time_busy' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='789' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='time_ext_busy' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='787' column='1'/>
+          <var-decl name='time_ext_busy' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='790' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='time_rx' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='788' column='1'/>
+          <var-decl name='time_rx' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='791' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='time_tx' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='789' column='1'/>
+          <var-decl name='time_tx' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='792' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='time_scan' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='790' column='1'/>
+          <var-decl name='time_scan' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='793' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='filled' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='791' column='1'/>
+          <var-decl name='filled' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='794' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='480'>
-          <var-decl name='noise' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='792' column='1'/>
+          <var-decl name='noise' type-id='fdbf7a0f' visibility='default' filepath='include/net/cfg80211.h' line='795' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_pmksa' size-in-bits='448' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2495' column='1' id='938cf680'>
+      <class-decl name='cfg80211_pmksa' size-in-bits='448' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2498' column='1' id='938cf680'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2496' column='1'/>
+          <var-decl name='bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2499' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='pmkid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2497' column='1'/>
+          <var-decl name='pmkid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2500' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='pmk' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2498' column='1'/>
+          <var-decl name='pmk' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2501' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='pmk_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2499' column='1'/>
+          <var-decl name='pmk_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2502' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2500' column='1'/>
+          <var-decl name='ssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2503' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='ssid_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2501' column='1'/>
+          <var-decl name='ssid_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2504' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='cache_id' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2502' column='1'/>
+          <var-decl name='cache_id' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2505' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_mgmt_tx_params' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2717' column='1' id='b52f43dd'>
+      <class-decl name='cfg80211_mgmt_tx_params' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2720' column='1' id='b52f43dd'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='chan' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2718' column='1'/>
+          <var-decl name='chan' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2721' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='offchan' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2719' column='1'/>
+          <var-decl name='offchan' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2722' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='wait' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='2720' column='1'/>
+          <var-decl name='wait' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='2723' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='buf' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2721' column='1'/>
+          <var-decl name='buf' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2724' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2722' column='1'/>
+          <var-decl name='len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2725' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='no_cck' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2723' column='1'/>
+          <var-decl name='no_cck' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2726' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='264'>
-          <var-decl name='dont_wait_for_ack' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2724' column='1'/>
+          <var-decl name='dont_wait_for_ack' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2727' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='288'>
-          <var-decl name='n_csa_offsets' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2725' column='1'/>
+          <var-decl name='n_csa_offsets' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2728' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='csa_offsets' type-id='80455526' visibility='default' filepath='include/net/cfg80211.h' line='2726' column='1'/>
+          <var-decl name='csa_offsets' type-id='80455526' visibility='default' filepath='include/net/cfg80211.h' line='2729' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_gtk_rekey_data' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2682' column='1' id='f569a53c'>
+      <class-decl name='cfg80211_gtk_rekey_data' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2685' column='1' id='f569a53c'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='kek' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2683' column='1'/>
+          <var-decl name='kek' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2686' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='kck' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2683' column='1'/>
+          <var-decl name='kck' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2686' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='replay_ctr' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2683' column='1'/>
+          <var-decl name='replay_ctr' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2686' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='kek_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2684' column='1'/>
+          <var-decl name='kek_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2687' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_tdls_operation' filepath='include/uapi/linux/nl80211.h' line='5159' column='1' id='ee1b00fc'>
@@ -133835,15 +133916,15 @@
         <enumerator name='NL80211_TDLS_ENABLE_LINK' value='3'/>
         <enumerator name='NL80211_TDLS_DISABLE_LINK' value='4'/>
       </enum-decl>
-      <class-decl name='cfg80211_update_ft_ies_params' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2696' column='1' id='6038e38f'>
+      <class-decl name='cfg80211_update_ft_ies_params' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2699' column='1' id='6038e38f'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='md' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2697' column='1'/>
+          <var-decl name='md' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2700' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2698' column='1'/>
+          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2701' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2699' column='1'/>
+          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2702' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_crit_proto_id' filepath='include/uapi/linux/nl80211.h' line='5700' column='1' id='2981c44a'>
@@ -133854,26 +133935,26 @@
         <enumerator name='NL80211_CRIT_PROTO_APIPA' value='3'/>
         <enumerator name='NUM_NL80211_CRIT_PROTO' value='4'/>
       </enum-decl>
-      <class-decl name='cfg80211_coalesce' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2609' column='1' id='6ef02a2f'>
+      <class-decl name='cfg80211_coalesce' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2612' column='1' id='6ef02a2f'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='rules' type-id='9c46a2bf' visibility='default' filepath='include/net/cfg80211.h' line='2610' column='1'/>
+          <var-decl name='rules' type-id='9c46a2bf' visibility='default' filepath='include/net/cfg80211.h' line='2613' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='n_rules' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2611' column='1'/>
+          <var-decl name='n_rules' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2614' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_coalesce_rules' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2595' column='1' id='b370f027'>
+      <class-decl name='cfg80211_coalesce_rules' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2598' column='1' id='b370f027'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='delay' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2596' column='1'/>
+          <var-decl name='delay' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2599' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='condition' type-id='a1c2ea1e' visibility='default' filepath='include/net/cfg80211.h' line='2597' column='1'/>
+          <var-decl name='condition' type-id='a1c2ea1e' visibility='default' filepath='include/net/cfg80211.h' line='2600' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='patterns' type-id='1ed3660c' visibility='default' filepath='include/net/cfg80211.h' line='2598' column='1'/>
+          <var-decl name='patterns' type-id='1ed3660c' visibility='default' filepath='include/net/cfg80211.h' line='2601' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='n_patterns' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2599' column='1'/>
+          <var-decl name='n_patterns' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2602' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_coalesce_condition' filepath='include/uapi/linux/nl80211.h' line='4930' column='1' id='a1c2ea1e'>
@@ -133881,145 +133962,145 @@
         <enumerator name='NL80211_COALESCE_CONDITION_MATCH' value='0'/>
         <enumerator name='NL80211_COALESCE_CONDITION_NO_MATCH' value='1'/>
       </enum-decl>
-      <class-decl name='cfg80211_csa_settings' size-in-bits='2048' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='986' column='1' id='7f4edaa7'>
+      <class-decl name='cfg80211_csa_settings' size-in-bits='2048' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='989' column='1' id='7f4edaa7'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='987' column='1'/>
+          <var-decl name='chandef' type-id='e07d69c8' visibility='default' filepath='include/net/cfg80211.h' line='990' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='beacon_csa' type-id='e61c5935' visibility='default' filepath='include/net/cfg80211.h' line='988' column='1'/>
+          <var-decl name='beacon_csa' type-id='e61c5935' visibility='default' filepath='include/net/cfg80211.h' line='991' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1024'>
-          <var-decl name='counter_offsets_beacon' type-id='80455526' visibility='default' filepath='include/net/cfg80211.h' line='989' column='1'/>
+          <var-decl name='counter_offsets_beacon' type-id='80455526' visibility='default' filepath='include/net/cfg80211.h' line='992' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1088'>
-          <var-decl name='counter_offsets_presp' type-id='80455526' visibility='default' filepath='include/net/cfg80211.h' line='990' column='1'/>
+          <var-decl name='counter_offsets_presp' type-id='80455526' visibility='default' filepath='include/net/cfg80211.h' line='993' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1152'>
-          <var-decl name='n_counter_offsets_beacon' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='991' column='1'/>
+          <var-decl name='n_counter_offsets_beacon' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='994' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1184'>
-          <var-decl name='n_counter_offsets_presp' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='992' column='1'/>
+          <var-decl name='n_counter_offsets_presp' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='995' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1216'>
-          <var-decl name='beacon_after' type-id='e61c5935' visibility='default' filepath='include/net/cfg80211.h' line='993' column='1'/>
+          <var-decl name='beacon_after' type-id='e61c5935' visibility='default' filepath='include/net/cfg80211.h' line='996' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1984'>
-          <var-decl name='radar_required' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='994' column='1'/>
+          <var-decl name='radar_required' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='997' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='1992'>
-          <var-decl name='block_tx' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='995' column='1'/>
+          <var-decl name='block_tx' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='998' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='2000'>
-          <var-decl name='count' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='996' column='1'/>
+          <var-decl name='count' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='999' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_qos_map' size-in-bits='472' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2767' column='1' id='762d0cdc'>
+      <class-decl name='cfg80211_qos_map' size-in-bits='472' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2770' column='1' id='762d0cdc'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='num_des' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2768' column='1'/>
+          <var-decl name='num_des' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2771' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8'>
-          <var-decl name='dscp_exception' type-id='113a8bef' visibility='default' filepath='include/net/cfg80211.h' line='2769' column='1'/>
+          <var-decl name='dscp_exception' type-id='113a8bef' visibility='default' filepath='include/net/cfg80211.h' line='2772' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='344'>
-          <var-decl name='up' type-id='62f1ceae' visibility='default' filepath='include/net/cfg80211.h' line='2770' column='1'/>
+          <var-decl name='up' type-id='62f1ceae' visibility='default' filepath='include/net/cfg80211.h' line='2773' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_dscp_exception' size-in-bits='16' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2735' column='1' id='c0e72c08'>
+      <class-decl name='cfg80211_dscp_exception' size-in-bits='16' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2738' column='1' id='c0e72c08'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='dscp' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2736' column='1'/>
+          <var-decl name='dscp' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2739' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8'>
-          <var-decl name='up' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2737' column='1'/>
+          <var-decl name='up' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2740' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_dscp_range' size-in-bits='16' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2746' column='1' id='0f438714'>
+      <class-decl name='cfg80211_dscp_range' size-in-bits='16' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2749' column='1' id='0f438714'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='low' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2747' column='1'/>
+          <var-decl name='low' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2750' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8'>
-          <var-decl name='high' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2748' column='1'/>
+          <var-decl name='high' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2751' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_nan_conf' size-in-bits='16' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2783' column='1' id='7fec8d58'>
+      <class-decl name='cfg80211_nan_conf' size-in-bits='16' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2786' column='1' id='7fec8d58'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='master_pref' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2784' column='1'/>
+          <var-decl name='master_pref' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2787' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='8'>
-          <var-decl name='bands' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2785' column='1'/>
+          <var-decl name='bands' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2788' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_nan_func' size-in-bits='896' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2840' column='1' id='f3945544'>
+      <class-decl name='cfg80211_nan_func' size-in-bits='896' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2843' column='1' id='f3945544'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='type' type-id='f796e63e' visibility='default' filepath='include/net/cfg80211.h' line='2841' column='1'/>
+          <var-decl name='type' type-id='f796e63e' visibility='default' filepath='include/net/cfg80211.h' line='2844' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='service_id' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2842' column='1'/>
+          <var-decl name='service_id' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2845' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='80'>
-          <var-decl name='publish_type' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2843' column='1'/>
+          <var-decl name='publish_type' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2846' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='88'>
-          <var-decl name='close_range' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2844' column='1'/>
+          <var-decl name='close_range' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2847' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='publish_bcast' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2845' column='1'/>
+          <var-decl name='publish_bcast' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2848' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='104'>
-          <var-decl name='subscribe_active' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2846' column='1'/>
+          <var-decl name='subscribe_active' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2849' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='112'>
-          <var-decl name='followup_id' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2847' column='1'/>
+          <var-decl name='followup_id' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2850' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='120'>
-          <var-decl name='followup_reqid' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2848' column='1'/>
+          <var-decl name='followup_reqid' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2851' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='followup_dest' type-id='6d8d26fb' visibility='default' filepath='include/net/cfg80211.h' line='2849' column='1'/>
+          <var-decl name='followup_dest' type-id='6d8d26fb' visibility='default' filepath='include/net/cfg80211.h' line='2852' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='ttl' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2850' column='1'/>
+          <var-decl name='ttl' type-id='19c2251e' visibility='default' filepath='include/net/cfg80211.h' line='2853' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='serv_spec_info' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2851' column='1'/>
+          <var-decl name='serv_spec_info' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2854' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='serv_spec_info_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2852' column='1'/>
+          <var-decl name='serv_spec_info_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2855' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='328'>
-          <var-decl name='srf_include' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2853' column='1'/>
+          <var-decl name='srf_include' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='2856' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='srf_bf' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2854' column='1'/>
+          <var-decl name='srf_bf' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2857' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='srf_bf_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2855' column='1'/>
+          <var-decl name='srf_bf_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2858' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='456'>
-          <var-decl name='srf_bf_idx' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2856' column='1'/>
+          <var-decl name='srf_bf_idx' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2859' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='512'>
-          <var-decl name='srf_macs' type-id='01b378ab' visibility='default' filepath='include/net/cfg80211.h' line='2857' column='1'/>
+          <var-decl name='srf_macs' type-id='01b378ab' visibility='default' filepath='include/net/cfg80211.h' line='2860' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='576'>
-          <var-decl name='srf_num_macs' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2858' column='1'/>
+          <var-decl name='srf_num_macs' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='2861' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='640'>
-          <var-decl name='rx_filters' type-id='ee7e85c3' visibility='default' filepath='include/net/cfg80211.h' line='2859' column='1'/>
+          <var-decl name='rx_filters' type-id='ee7e85c3' visibility='default' filepath='include/net/cfg80211.h' line='2862' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='704'>
-          <var-decl name='tx_filters' type-id='ee7e85c3' visibility='default' filepath='include/net/cfg80211.h' line='2860' column='1'/>
+          <var-decl name='tx_filters' type-id='ee7e85c3' visibility='default' filepath='include/net/cfg80211.h' line='2863' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='768'>
-          <var-decl name='num_tx_filters' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2861' column='1'/>
+          <var-decl name='num_tx_filters' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2864' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='776'>
-          <var-decl name='num_rx_filters' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2862' column='1'/>
+          <var-decl name='num_rx_filters' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2865' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='784'>
-          <var-decl name='instance_id' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2863' column='1'/>
+          <var-decl name='instance_id' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2866' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='cookie' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='2864' column='1'/>
+          <var-decl name='cookie' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='2867' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_nan_function_type' filepath='include/uapi/linux/nl80211.h' line='5842' column='1' id='f796e63e'>
@@ -134030,46 +134111,46 @@
         <enumerator name='__NL80211_NAN_FUNC_TYPE_AFTER_LAST' value='3'/>
         <enumerator name='NL80211_NAN_FUNC_MAX_TYPE' value='2'/>
       </enum-decl>
-      <class-decl name='cfg80211_nan_func_filter' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2806' column='1' id='fef37f13'>
+      <class-decl name='cfg80211_nan_func_filter' size-in-bits='128' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2809' column='1' id='fef37f13'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='filter' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2807' column='1'/>
+          <var-decl name='filter' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2810' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2808' column='1'/>
+          <var-decl name='len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2811' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_pmk_conf' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2877' column='1' id='1316fd07'>
+      <class-decl name='cfg80211_pmk_conf' size-in-bits='256' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2880' column='1' id='1316fd07'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='aa' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2878' column='1'/>
+          <var-decl name='aa' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2881' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='pmk_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2879' column='1'/>
+          <var-decl name='pmk_len' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2882' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='pmk' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2880' column='1'/>
+          <var-decl name='pmk' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2883' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='pmk_r0_name' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2881' column='1'/>
+          <var-decl name='pmk_r0_name' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2884' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_external_auth_params' size-in-bits='512' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2904' column='1' id='5e0fcaa5'>
+      <class-decl name='cfg80211_external_auth_params' size-in-bits='512' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2907' column='1' id='5e0fcaa5'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='action' type-id='93b938a2' visibility='default' filepath='include/net/cfg80211.h' line='2905' column='1'/>
+          <var-decl name='action' type-id='93b938a2' visibility='default' filepath='include/net/cfg80211.h' line='2908' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='32'>
-          <var-decl name='bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2906' column='1'/>
+          <var-decl name='bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2909' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='80'>
-          <var-decl name='ssid' type-id='0c960fcf' visibility='default' filepath='include/net/cfg80211.h' line='2907' column='1'/>
+          <var-decl name='ssid' type-id='0c960fcf' visibility='default' filepath='include/net/cfg80211.h' line='2910' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='352'>
-          <var-decl name='key_mgmt_suite' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='2908' column='1'/>
+          <var-decl name='key_mgmt_suite' type-id='f0981eeb' visibility='default' filepath='include/net/cfg80211.h' line='2911' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='status' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2909' column='1'/>
+          <var-decl name='status' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2912' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='pmkid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2910' column='1'/>
+          <var-decl name='pmkid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2913' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_external_auth_action' filepath='include/uapi/linux/nl80211.h' line='6006' column='1' id='93b938a2'>
@@ -134077,18 +134158,18 @@
         <enumerator name='NL80211_EXTERNAL_AUTH_START' value='0'/>
         <enumerator name='NL80211_EXTERNAL_AUTH_ABORT' value='1'/>
       </enum-decl>
-      <class-decl name='cfg80211_update_owe_info' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2932' column='1' id='aabc6610'>
+      <class-decl name='cfg80211_update_owe_info' size-in-bits='192' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2935' column='1' id='aabc6610'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='peer' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2933' column='1'/>
+          <var-decl name='peer' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2936' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='48'>
-          <var-decl name='status' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2934' column='1'/>
+          <var-decl name='status' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='2937' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2935' column='1'/>
+          <var-decl name='ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='2938' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2936' column='1'/>
+          <var-decl name='ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='2939' column='1'/>
         </data-member>
       </class-decl>
       <pointer-type-def type-id='5603c5c0' size-in-bits='64' id='fa1cae16'/>
@@ -134156,10 +134237,6 @@
       <pointer-type-def type-id='64b77daa' size-in-bits='64' id='0cda9080'/>
       <qualified-type-def type-id='2eec6999' const='yes' id='46f53066'/>
       <pointer-type-def type-id='46f53066' size-in-bits='64' id='fffb07a4'/>
-      <qualified-type-def type-id='bcc5cab3' const='yes' id='208298e3'/>
-      <pointer-type-def type-id='208298e3' size-in-bits='64' id='f696846b'/>
-      <qualified-type-def type-id='0c842ad9' const='yes' id='afa36b70'/>
-      <pointer-type-def type-id='afa36b70' size-in-bits='64' id='d841feae'/>
       <qualified-type-def type-id='50718ec3' const='yes' id='3666ea54'/>
       <pointer-type-def type-id='3666ea54' size-in-bits='64' id='2203245a'/>
       <qualified-type-def type-id='d5e39a52' const='yes' id='be356197'/>
@@ -134184,7 +134261,6 @@
       <pointer-type-def type-id='ce30b5d2' size-in-bits='64' id='4343d470'/>
       <pointer-type-def type-id='f7e1259c' size-in-bits='64' id='3cad9e1a'/>
       <pointer-type-def type-id='f16b7aee' size-in-bits='64' id='bf642844'/>
-      <pointer-type-def type-id='97488913' size-in-bits='64' id='2c8ff697'/>
       <pointer-type-def type-id='045f8e20' size-in-bits='64' id='518c633a'/>
       <pointer-type-def type-id='49390c3d' size-in-bits='64' id='40a250d9'/>
       <pointer-type-def type-id='06206c42' size-in-bits='64' id='ee39fcb4'/>
@@ -134268,13 +134344,7 @@
       <pointer-type-def type-id='d91d4c07' size-in-bits='64' id='dcf81beb'/>
       <pointer-type-def type-id='48be0748' size-in-bits='64' id='6a7c3ba2'/>
       <pointer-type-def type-id='c756879f' size-in-bits='64' id='a9032da3'/>
-      <pointer-type-def type-id='e90b3b44' size-in-bits='64' id='4780e252'/>
-      <pointer-type-def type-id='f8292115' size-in-bits='64' id='96efb615'/>
-      <pointer-type-def type-id='1c8cc2fd' size-in-bits='64' id='003642fd'/>
-      <pointer-type-def type-id='cfdbff8a' size-in-bits='64' id='55e2a83c'/>
-      <pointer-type-def type-id='ed626d0d' size-in-bits='64' id='00e2a7ce'/>
       <pointer-type-def type-id='45947737' size-in-bits='64' id='706d79ff'/>
-      <pointer-type-def type-id='9c91a761' size-in-bits='64' id='29244949'/>
       <pointer-type-def type-id='6d8d26fb' size-in-bits='64' id='01b378ab'/>
       <pointer-type-def type-id='50718ec3' size-in-bits='64' id='fce83a73'/>
       <pointer-type-def type-id='1cac2bf4' size-in-bits='64' id='9362acb2'/>
@@ -134314,18 +134384,11 @@
         <parameter type-id='666fb412' name='wiphy' filepath='net/wireless/core.c' line='930' column='1'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-decl name='cfg80211_put_bss' mangled-name='cfg80211_put_bss' filepath='include/net/cfg80211.h' line='5310' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='cfg80211_put_bss'>
+      <function-decl name='cfg80211_put_bss' mangled-name='cfg80211_put_bss' filepath='include/net/cfg80211.h' line='5313' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='cfg80211_put_bss'>
         <parameter type-id='666fb412'/>
         <parameter type-id='bda81d86'/>
         <return type-id='48b5725f'/>
       </function-decl>
-      <function-type size-in-bits='64' id='97488913'>
-        <parameter type-id='68a2d05b'/>
-        <parameter type-id='4780e252'/>
-        <parameter type-id='00e2a7ce'/>
-        <parameter type-id='26a90f95'/>
-        <return type-id='95e97e5e'/>
-      </function-type>
       <function-type size-in-bits='64' id='045f8e20'>
         <parameter type-id='666fb412'/>
         <return type-id='95e97e5e'/>
@@ -134879,10 +134942,6 @@
         <parameter type-id='95e97e5e'/>
         <return type-id='95e97e5e'/>
       </function-type>
-      <function-type size-in-bits='64' id='cfdbff8a'>
-        <parameter type-id='68a2d05b'/>
-        <return type-id='003642fd'/>
-      </function-type>
       <function-type size-in-bits='64' id='a2365ade'>
         <parameter type-id='eaa32e2f'/>
         <parameter type-id='706d79ff'/>
@@ -135414,21 +135473,21 @@
         <enumerator name='NUM_NL80211_ATTR' value='285'/>
         <enumerator name='NL80211_ATTR_MAX' value='284'/>
       </enum-decl>
-      <class-decl name='cfg80211_ft_event_params' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='6479' column='1' id='cc4b6920'>
+      <class-decl name='cfg80211_ft_event_params' size-in-bits='320' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='6482' column='1' id='cc4b6920'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='ies' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='6480' column='1'/>
+          <var-decl name='ies' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='6483' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='ies_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='6481' column='1'/>
+          <var-decl name='ies_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='6484' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='target_ap' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='6482' column='1'/>
+          <var-decl name='target_ap' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='6485' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='ric_ies' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='6483' column='1'/>
+          <var-decl name='ric_ies' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='6486' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='ric_ies_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='6484' column='1'/>
+          <var-decl name='ric_ies_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='6487' column='1'/>
         </data-member>
       </class-decl>
       <pointer-type-def type-id='cc4b6920' size-in-bits='64' id='76db5996'/>
@@ -135567,7 +135626,7 @@
         <parameter type-id='c24e05b4' name='rd' filepath='net/wireless/reg.c' line='3712' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
-      <function-decl name='cfg80211_chandef_create' mangled-name='cfg80211_chandef_create' filepath='include/net/cfg80211.h' line='609' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='cfg80211_chandef_create'>
+      <function-decl name='cfg80211_chandef_create' mangled-name='cfg80211_chandef_create' filepath='include/net/cfg80211.h' line='612' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='cfg80211_chandef_create'>
         <parameter type-id='0953fbfe'/>
         <parameter type-id='ec00acfb'/>
         <parameter type-id='9e446de7'/>
@@ -135581,33 +135640,33 @@
         <enumerator name='IEEE80211_PRIVACY_OFF' value='1'/>
         <enumerator name='IEEE80211_PRIVACY_ANY' value='2'/>
       </enum-decl>
-      <class-decl name='cfg80211_inform_bss' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2030' column='1' id='616d6efe'>
+      <class-decl name='cfg80211_inform_bss' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='2033' column='1' id='616d6efe'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='chan' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2031' column='1'/>
+          <var-decl name='chan' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='2034' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='scan_width' type-id='95d46034' visibility='default' filepath='include/net/cfg80211.h' line='2032' column='1'/>
+          <var-decl name='scan_width' type-id='95d46034' visibility='default' filepath='include/net/cfg80211.h' line='2035' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='96'>
-          <var-decl name='signal' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='2033' column='1'/>
+          <var-decl name='signal' type-id='a7832498' visibility='default' filepath='include/net/cfg80211.h' line='2036' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='boottime_ns' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='2034' column='1'/>
+          <var-decl name='boottime_ns' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='2037' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='parent_tsf' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='2035' column='1'/>
+          <var-decl name='parent_tsf' type-id='91ce1af9' visibility='default' filepath='include/net/cfg80211.h' line='2038' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='parent_bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2036' column='1'/>
+          <var-decl name='parent_bssid' type-id='cf1a4160' visibility='default' filepath='include/net/cfg80211.h' line='2039' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='304'>
-          <var-decl name='chains' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2037' column='1'/>
+          <var-decl name='chains' type-id='f9b06939' visibility='default' filepath='include/net/cfg80211.h' line='2040' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='312'>
-          <var-decl name='chain_signal' type-id='da004b74' visibility='default' filepath='include/net/cfg80211.h' line='2038' column='1'/>
+          <var-decl name='chain_signal' type-id='da004b74' visibility='default' filepath='include/net/cfg80211.h' line='2041' column='1'/>
         </data-member>
       </class-decl>
-      <enum-decl name='cfg80211_bss_frame_type' filepath='include/net/cfg80211.h' line='5195' column='1' id='b556f108'>
+      <enum-decl name='cfg80211_bss_frame_type' filepath='include/net/cfg80211.h' line='5198' column='1' id='b556f108'>
         <underlying-type type-id='9cac1fee'/>
         <enumerator name='CFG80211_BSS_FTYPE_UNKNOWN' value='0'/>
         <enumerator name='CFG80211_BSS_FTYPE_BEACON' value='1'/>
@@ -136106,56 +136165,56 @@
         <enumerator name='CFG80211_CONN_ABANDON' value='10'/>
         <enumerator name='CFG80211_CONN_CONNECTED' value='11'/>
       </enum-decl>
-      <class-decl name='cfg80211_connect_resp_params' size-in-bits='896' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='5799' column='1' id='77e8064c'>
+      <class-decl name='cfg80211_connect_resp_params' size-in-bits='896' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='5802' column='1' id='77e8064c'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='status' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='5800' column='1'/>
+          <var-decl name='status' type-id='95e97e5e' visibility='default' filepath='include/net/cfg80211.h' line='5803' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5801' column='1'/>
+          <var-decl name='bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5804' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='5802' column='1'/>
+          <var-decl name='bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='5805' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='req_ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5803' column='1'/>
+          <var-decl name='req_ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5806' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='req_ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='5804' column='1'/>
+          <var-decl name='req_ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='5807' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='resp_ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5805' column='1'/>
+          <var-decl name='resp_ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5808' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='resp_ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='5806' column='1'/>
+          <var-decl name='resp_ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='5809' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='fils' type-id='73962ae2' visibility='default' filepath='include/net/cfg80211.h' line='5807' column='1'/>
+          <var-decl name='fils' type-id='73962ae2' visibility='default' filepath='include/net/cfg80211.h' line='5810' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='832'>
-          <var-decl name='timeout_reason' type-id='e4422617' visibility='default' filepath='include/net/cfg80211.h' line='5808' column='1'/>
+          <var-decl name='timeout_reason' type-id='e4422617' visibility='default' filepath='include/net/cfg80211.h' line='5811' column='1'/>
         </data-member>
       </class-decl>
-      <class-decl name='cfg80211_fils_resp_params' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='5763' column='1' id='73962ae2'>
+      <class-decl name='cfg80211_fils_resp_params' size-in-bits='384' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='5766' column='1' id='73962ae2'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='kek' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5764' column='1'/>
+          <var-decl name='kek' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5767' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='kek_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='5765' column='1'/>
+          <var-decl name='kek_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='5768' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='update_erp_next_seq_num' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='5766' column='1'/>
+          <var-decl name='update_erp_next_seq_num' type-id='b50a4934' visibility='default' filepath='include/net/cfg80211.h' line='5769' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='144'>
-          <var-decl name='erp_next_seq_num' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='5767' column='1'/>
+          <var-decl name='erp_next_seq_num' type-id='1dc6a898' visibility='default' filepath='include/net/cfg80211.h' line='5770' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='pmk' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5768' column='1'/>
+          <var-decl name='pmk' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5771' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='pmk_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='5769' column='1'/>
+          <var-decl name='pmk_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='5772' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='pmkid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5770' column='1'/>
+          <var-decl name='pmkid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5773' column='1'/>
         </data-member>
       </class-decl>
       <enum-decl name='nl80211_timeout_reason' filepath='include/uapi/linux/nl80211.h' line='5513' column='1' id='e4422617'>
@@ -136165,30 +136224,30 @@
         <enumerator name='NL80211_TIMEOUT_AUTH' value='2'/>
         <enumerator name='NL80211_TIMEOUT_ASSOC' value='3'/>
       </enum-decl>
-      <class-decl name='cfg80211_roam_info' size-in-bits='832' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='5955' column='1' id='883d1dc6'>
+      <class-decl name='cfg80211_roam_info' size-in-bits='832' is-struct='yes' visibility='default' filepath='include/net/cfg80211.h' line='5958' column='1' id='883d1dc6'>
         <data-member access='public' layout-offset-in-bits='0'>
-          <var-decl name='channel' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='5956' column='1'/>
+          <var-decl name='channel' type-id='ec00acfb' visibility='default' filepath='include/net/cfg80211.h' line='5959' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='64'>
-          <var-decl name='bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='5957' column='1'/>
+          <var-decl name='bss' type-id='bda81d86' visibility='default' filepath='include/net/cfg80211.h' line='5960' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='128'>
-          <var-decl name='bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5958' column='1'/>
+          <var-decl name='bssid' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5961' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='192'>
-          <var-decl name='req_ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5959' column='1'/>
+          <var-decl name='req_ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5962' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='256'>
-          <var-decl name='req_ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='5960' column='1'/>
+          <var-decl name='req_ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='5963' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='320'>
-          <var-decl name='resp_ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5961' column='1'/>
+          <var-decl name='resp_ie' type-id='bbaf3419' visibility='default' filepath='include/net/cfg80211.h' line='5964' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='384'>
-          <var-decl name='resp_ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='5962' column='1'/>
+          <var-decl name='resp_ie_len' type-id='b59d7dce' visibility='default' filepath='include/net/cfg80211.h' line='5965' column='1'/>
         </data-member>
         <data-member access='public' layout-offset-in-bits='448'>
-          <var-decl name='fils' type-id='73962ae2' visibility='default' filepath='include/net/cfg80211.h' line='5963' column='1'/>
+          <var-decl name='fils' type-id='73962ae2' visibility='default' filepath='include/net/cfg80211.h' line='5966' column='1'/>
         </data-member>
       </class-decl>
       <pointer-type-def type-id='77e8064c' size-in-bits='64' id='b1d9990a'/>
@@ -136250,11 +136309,11 @@
       </function-decl>
     </abi-instr>
     <abi-instr address-size='64' path='net/xfrm/xfrm_policy.c' language='LANG_C89'>
-      <function-decl name='__xfrm_policy_check' mangled-name='__xfrm_policy_check' filepath='net/xfrm/xfrm_policy.c' line='2316' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__xfrm_policy_check'>
-        <parameter type-id='f772df6d' name='sk' filepath='net/xfrm/xfrm_policy.c' line='2316' column='1'/>
-        <parameter type-id='95e97e5e' name='dir' filepath='net/xfrm/xfrm_policy.c' line='2316' column='1'/>
-        <parameter type-id='0fbf3cfd' name='skb' filepath='net/xfrm/xfrm_policy.c' line='2316' column='1'/>
-        <parameter type-id='8efea9e5' name='family' filepath='net/xfrm/xfrm_policy.c' line='2317' column='1'/>
+      <function-decl name='__xfrm_policy_check' mangled-name='__xfrm_policy_check' filepath='net/xfrm/xfrm_policy.c' line='2317' column='1' visibility='default' binding='global' size-in-bits='64' elf-symbol-id='__xfrm_policy_check'>
+        <parameter type-id='f772df6d' name='sk' filepath='net/xfrm/xfrm_policy.c' line='2317' column='1'/>
+        <parameter type-id='95e97e5e' name='dir' filepath='net/xfrm/xfrm_policy.c' line='2317' column='1'/>
+        <parameter type-id='0fbf3cfd' name='skb' filepath='net/xfrm/xfrm_policy.c' line='2317' column='1'/>
+        <parameter type-id='8efea9e5' name='family' filepath='net/xfrm/xfrm_policy.c' line='2318' column='1'/>
         <return type-id='95e97e5e'/>
       </function-decl>
     </abi-instr>
@@ -143010,7 +143069,7 @@
     </abi-instr>
     <abi-instr address-size='64' path='drivers/scsi/ufs/ufshcd.c' language='LANG_C89'>
       <pointer-type-def type-id='b984f4f2' size-in-bits='64' id='4c0ab7c4'/>
-      <function-decl name='bpf_trace_run8' filepath='include/linux/trace_events.h' line='604' column='1' visibility='default' binding='global' size-in-bits='64'>
+      <function-decl name='bpf_trace_run8' filepath='include/linux/trace_events.h' line='605' column='1' visibility='default' binding='global' size-in-bits='64'>
         <parameter type-id='bdcee7ae'/>
         <parameter type-id='3a47d82b'/>
         <parameter type-id='3a47d82b'/>
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index bac97441074a..12f7c7138702 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -597,6 +597,9 @@ struct perf_event {
 	/* The cumulative AND of all event_caps for events in this group. */
 	int				group_caps;
 
+#ifndef __GENKSYMS__	/* ANDROID Bug: 307236803 to keep the crc preserved */
+	unsigned int			group_generation;
+#endif
 	struct perf_event		*group_leader;
 	struct pmu			*pmu;
 	void				*pmu_private;
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 5fc26042a906..cb9b49a5d71c 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -1848,6 +1848,7 @@ static void perf_group_attach(struct perf_event *event)
 
 	list_add_tail(&event->sibling_list, &group_leader->sibling_list);
 	group_leader->nr_siblings++;
+	group_leader->group_generation++;
 
 	perf_event__header_size(group_leader);
 
@@ -1918,6 +1919,7 @@ static void perf_group_detach(struct perf_event *event)
 	if (event->group_leader != event) {
 		list_del_init(&event->sibling_list);
 		event->group_leader->nr_siblings--;
+		event->group_leader->group_generation++;
 		goto out;
 	}
 
@@ -4736,7 +4738,7 @@ static int __perf_read_group_add(struct perf_event *leader,
 					u64 read_format, u64 *values)
 {
 	struct perf_event_context *ctx = leader->ctx;
-	struct perf_event *sub;
+	struct perf_event *sub, *parent;
 	unsigned long flags;
 	int n = 1; /* skip @nr */
 	int ret;
@@ -4746,6 +4748,33 @@ static int __perf_read_group_add(struct perf_event *leader,
 		return ret;
 
 	raw_spin_lock_irqsave(&ctx->lock, flags);
+	/*
+	 * Verify the grouping between the parent and child (inherited)
+	 * events is still in tact.
+	 *
+	 * Specifically:
+	 *  - leader->ctx->lock pins leader->sibling_list
+	 *  - parent->child_mutex pins parent->child_list
+	 *  - parent->ctx->mutex pins parent->sibling_list
+	 *
+	 * Because parent->ctx != leader->ctx (and child_list nests inside
+	 * ctx->mutex), group destruction is not atomic between children, also
+	 * see perf_event_release_kernel(). Additionally, parent can grow the
+	 * group.
+	 *
+	 * Therefore it is possible to have parent and child groups in a
+	 * different configuration and summing over such a beast makes no sense
+	 * what so ever.
+	 *
+	 * Reject this.
+	 */
+	parent = leader->parent;
+	if (parent &&
+	    (parent->group_generation != leader->group_generation ||
+	     parent->nr_siblings != leader->nr_siblings)) {
+		ret = -ECHILD;
+		goto unlock;
+	}
 
 	/*
 	 * Since we co-schedule groups, {enabled,running} times of siblings
@@ -4775,8 +4804,9 @@ static int __perf_read_group_add(struct perf_event *leader,
 			values[n++] = primary_event_id(sub);
 	}
 
+unlock:
 	raw_spin_unlock_irqrestore(&ctx->lock, flags);
-	return 0;
+	return ret;
 }
 
 static int perf_read_group(struct perf_event *event,
@@ -4795,10 +4825,6 @@ static int perf_read_group(struct perf_event *event,
 
 	values[0] = 1 + leader->nr_siblings;
 
-	/*
-	 * By locking the child_mutex of the leader we effectively
-	 * lock the child list of all siblings.. XXX explain how.
-	 */
 	mutex_lock(&leader->child_mutex);
 
 	ret = __perf_read_group_add(leader, read_format, values);
@@ -11587,6 +11613,7 @@ static int inherit_group(struct perf_event *parent_event,
 		if (IS_ERR(child_ctr))
 			return PTR_ERR(child_ctr);
 	}
+	leader->group_generation = parent_event->group_generation;
 	return 0;
 }
 
-- 
GitLab


From 2f041349d12f46371f9e9e80bfa5427e6640d5a8 Mon Sep 17 00:00:00 2001
From: lucaswei <lucaswei@google.com>
Date: Tue, 10 Nov 2020 01:30:25 +0800
Subject: [PATCH 298/298] techpack: video: hfi_iris2: Fix -Wpointer-to-int-cast

msm/vidc/hfi_iris2.c:170:3: error: cast to smaller integer type 'u32' (aka 'unsigned int') from 'u8 *' (aka 'unsigned char *') [-Werror,-Wpointer-to-int-cast]
                (u32)device->iface_q_table.align_virtual_addr, sid);
                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Casting `device->iface_q_table.align_virtual_addr` to uintptr_t first, then
cast to u32 to avoid pointer-to-int-cast errors.

Bug: 171827315
Signed-off-by: lucaswei <lucaswei@google.com>
Change-Id: I687af3df978841d4cba8ea658176187d1fb56837
---
 techpack/video/msm/vidc/hfi_iris2.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/techpack/video/msm/vidc/hfi_iris2.c b/techpack/video/msm/vidc/hfi_iris2.c
index 179fb2abaefb..0f16e9b0044f 100644
--- a/techpack/video/msm/vidc/hfi_iris2.c
+++ b/techpack/video/msm/vidc/hfi_iris2.c
@@ -2,6 +2,7 @@
 /*
  * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
  */
+#include <linux/kernel.h>
 
 #include "msm_vidc_debug.h"
 #include "hfi_common.h"
@@ -167,9 +168,9 @@ void __setup_ucregion_memory_map_iris2(struct venus_hfi_device *device, u32 sid)
 				(u32)device->qdss.align_device_addr, sid);
 	/* update queues vaddr for debug purpose */
 	__write_register(device, CPU_CS_VCICMDARG0_IRIS2,
-		(u32)device->iface_q_table.align_virtual_addr, sid);
+		(u32)((uintptr_t)device->iface_q_table.align_virtual_addr & UINT_MAX), sid);
 	__write_register(device, CPU_CS_VCICMDARG1_IRIS2,
-		(u32)((u64)device->iface_q_table.align_virtual_addr >> 32),
+		(u32)((uintptr_t)device->iface_q_table.align_virtual_addr >> 32),
 		sid);
 }
 
-- 
GitLab