diff --git a/Makefile b/Makefile
index de2b3bc6f674ba0cb97044a10ca2457bf17ccac2..15f60fb9af49bdff9bcc352e036d30040e12d769 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 4
PATCHLEVEL = 19
-SUBLEVEL = 295
+SUBLEVEL = 297
EXTRAVERSION =
NAME = "People's Front"
diff --git a/android/abi_gki_aarch64.xml b/android/abi_gki_aarch64.xml
index 18c8d22e584d3f935a86129d6f7279f9bb99cdc7..20921dd6c6f611632dcaf1294130100930c8ad13 100644
--- a/android/abi_gki_aarch64.xml
+++ b/android/abi_gki_aarch64.xml
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-
@@ -134184,7 +134261,6 @@
-
@@ -134268,13 +134344,7 @@
-
-
-
-
-
-
@@ -134314,18 +134384,11 @@
-
+
-
-
-
-
-
-
-
@@ -134879,10 +134942,6 @@
-
-
-
-
@@ -135414,21 +135473,21 @@
-
+
-
+
-
+
-
+
-
+
-
+
@@ -135567,7 +135626,7 @@
-
+
@@ -135581,33 +135640,33 @@
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
@@ -136106,56 +136165,56 @@
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
@@ -136165,30 +136224,30 @@
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
@@ -136250,11 +136309,11 @@
-
-
-
-
-
+
+
+
+
+
@@ -143010,7 +143069,7 @@
-
+
diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts
index 67d77eee9433c655e0bd8f0c1dbf7c25aba3ecce..91c8a05ab67ae5a198d856fcdf140e3324fbf3a0 100644
--- a/arch/arm/boot/dts/omap4-droid4-xt894.dts
+++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts
@@ -647,12 +647,12 @@
/* Configure pwm clock source for timers 8 & 9 */
&timer8 {
assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
- assigned-clock-parents = <&sys_clkin_ck>;
+ assigned-clock-parents = <&sys_32k_ck>;
};
&timer9 {
assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>;
- assigned-clock-parents = <&sys_clkin_ck>;
+ assigned-clock-parents = <&sys_32k_ck>;
};
/*
@@ -669,6 +669,7 @@
&uart3 {
interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core 0x17c>;
+ overrun-throttle-ms = <500>;
};
&uart4 {
diff --git a/arch/arm64/configs/vendor/kona-perf_defconfig b/arch/arm64/configs/vendor/kona-perf_defconfig
index bd643fe4efb3b1da9bdfd1d76affd4a8a566fad5..5335e0ca084f2114d35e8edf2d9efd3a255bcce9 100644
--- a/arch/arm64/configs/vendor/kona-perf_defconfig
+++ b/arch/arm64/configs/vendor/kona-perf_defconfig
@@ -462,8 +462,6 @@ CONFIG_HID_MICROSOFT=y
CONFIG_HID_MULTITOUCH=y
CONFIG_HID_NINTENDO=y
CONFIG_HID_PLANTRONICS=y
-CONFIG_HID_PLAYSTATION=y
-CONFIG_PLAYSTATION_FF=y
CONFIG_HID_SONY=y
CONFIG_SONY_FF=y
CONFIG_HID_QVR=y
diff --git a/arch/arm64/configs/vendor/kona_defconfig b/arch/arm64/configs/vendor/kona_defconfig
index f6dade1f20b787f7525ccc98c19d6c489dde8940..cdfbb07a3ec51904a939fda9855c8c96d88998c1 100644
--- a/arch/arm64/configs/vendor/kona_defconfig
+++ b/arch/arm64/configs/vendor/kona_defconfig
@@ -478,8 +478,6 @@ CONFIG_HID_MICROSOFT=y
CONFIG_HID_MULTITOUCH=y
CONFIG_HID_NINTENDO=y
CONFIG_HID_PLANTRONICS=y
-CONFIG_HID_PLAYSTATION=y
-CONFIG_PLAYSTATION_FF=y
CONFIG_HID_SONY=y
CONFIG_SONY_FF=y
CONFIG_HID_QVR=y
diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c
index 6fe0f0f95ed7c5f5fa761f6f9da7d5d8d68c385c..548bd4db0f9760fa90b6b187cf202ef3bf992b61 100644
--- a/arch/mips/alchemy/devboards/db1000.c
+++ b/arch/mips/alchemy/devboards/db1000.c
@@ -173,6 +173,7 @@ static struct platform_device db1x00_audio_dev = {
/******************************************************************************/
+#ifdef CONFIG_MMC_AU1X
static irqreturn_t db1100_mmc_cd(int irq, void *ptr)
{
mmc_detect_change(ptr, msecs_to_jiffies(500));
@@ -380,6 +381,7 @@ static struct platform_device db1100_mmc1_dev = {
.num_resources = ARRAY_SIZE(au1100_mmc1_res),
.resource = au1100_mmc1_res,
};
+#endif /* CONFIG_MMC_AU1X */
/******************************************************************************/
@@ -497,9 +499,11 @@ static struct platform_device *db1000_devs[] = {
static struct platform_device *db1100_devs[] = {
&au1100_lcd_device,
+#ifdef CONFIG_MMC_AU1X
&db1100_mmc0_dev,
&db1100_mmc1_dev,
&db1000_irda_dev,
+#endif
};
int __init db1000_dev_setup(void)
diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c
index ae81e05fcb2c9a41bf671b042b0bca0dd83f8cd0..48840e48e79a0e6a5daddc23308bff5be3e9e448 100644
--- a/arch/mips/alchemy/devboards/db1200.c
+++ b/arch/mips/alchemy/devboards/db1200.c
@@ -341,6 +341,7 @@ static struct platform_device db1200_ide_dev = {
/**********************************************************************/
+#ifdef CONFIG_MMC_AU1X
/* SD carddetects: they're supposed to be edge-triggered, but ack
* doesn't seem to work (CPLD Rev 2). Instead, the screaming one
* is disabled and its counterpart enabled. The 200ms timeout is
@@ -601,6 +602,7 @@ static struct platform_device pb1200_mmc1_dev = {
.num_resources = ARRAY_SIZE(au1200_mmc1_res),
.resource = au1200_mmc1_res,
};
+#endif /* CONFIG_MMC_AU1X */
/**********************************************************************/
@@ -768,7 +770,9 @@ static struct platform_device db1200_audiodma_dev = {
static struct platform_device *db1200_devs[] __initdata = {
NULL, /* PSC0, selected by S6.8 */
&db1200_ide_dev,
+#ifdef CONFIG_MMC_AU1X
&db1200_mmc0_dev,
+#endif
&au1200_lcd_dev,
&db1200_eth_dev,
&db1200_nand_dev,
@@ -779,7 +783,9 @@ static struct platform_device *db1200_devs[] __initdata = {
};
static struct platform_device *pb1200_devs[] __initdata = {
+#ifdef CONFIG_MMC_AU1X
&pb1200_mmc1_dev,
+#endif
};
/* Some peripheral base addresses differ on the PB1200 */
diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c
index 0c12fbc07117a12a631a85040d4ef3311fff706a..664a5a783d2c5118605654811625a4e3b4d45dd5 100644
--- a/arch/mips/alchemy/devboards/db1300.c
+++ b/arch/mips/alchemy/devboards/db1300.c
@@ -448,6 +448,7 @@ static struct platform_device db1300_ide_dev = {
/**********************************************************************/
+#ifdef CONFIG_MMC_AU1X
static irqreturn_t db1300_mmc_cd(int irq, void *ptr)
{
disable_irq_nosync(irq);
@@ -626,6 +627,7 @@ static struct platform_device db1300_sd0_dev = {
.resource = au1300_sd0_res,
.num_resources = ARRAY_SIZE(au1300_sd0_res),
};
+#endif /* CONFIG_MMC_AU1X */
/**********************************************************************/
@@ -756,8 +758,10 @@ static struct platform_device *db1300_dev[] __initdata = {
&db1300_5waysw_dev,
&db1300_nand_dev,
&db1300_ide_dev,
+#ifdef CONFIG_MMC_AU1X
&db1300_sd0_dev,
&db1300_sd1_dev,
+#endif
&db1300_lcd_dev,
&db1300_ac97_dev,
&db1300_i2s_dev,
diff --git a/arch/parisc/include/asm/ldcw.h b/arch/parisc/include/asm/ldcw.h
index 3eb4bfc1fb365478f11c9c87bfb3b3124fab567a..5ed52819e956a415527750a8f84c07805f10d55d 100644
--- a/arch/parisc/include/asm/ldcw.h
+++ b/arch/parisc/include/asm/ldcw.h
@@ -2,14 +2,28 @@
#ifndef __PARISC_LDCW_H
#define __PARISC_LDCW_H
-#ifndef CONFIG_PA20
/* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
and GCC only guarantees 8-byte alignment for stack locals, we can't
be assured of 16-byte alignment for atomic lock data even if we
specify "__attribute ((aligned(16)))" in the type declaration. So,
we use a struct containing an array of four ints for the atomic lock
type and dynamically select the 16-byte aligned int from the array
- for the semaphore. */
+ for the semaphore. */
+
+/* From: "Jim Hull"
+ I've attached a summary of the change, but basically, for PA 2.0, as
+ long as the ",CO" (coherent operation) completer is implemented, then the
+ 16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
+ they only require "natural" alignment (4-byte for ldcw, 8-byte for
+ ldcd).
+
+ Although the cache control hint is accepted by all PA 2.0 processors,
+ it is only implemented on PA8800/PA8900 CPUs. Prior PA8X00 CPUs still
+ require 16-byte alignment. If the address is unaligned, the operation
+ of the instruction is undefined. The ldcw instruction does not generate
+ unaligned data reference traps so misaligned accesses are not detected.
+ This hid the problem for years. So, restore the 16-byte alignment dropped
+ by Kyle McMartin in "Remove __ldcw_align for PA-RISC 2.0 processors". */
#define __PA_LDCW_ALIGNMENT 16
#define __PA_LDCW_ALIGN_ORDER 4
@@ -19,22 +33,12 @@
& ~(__PA_LDCW_ALIGNMENT - 1); \
(volatile unsigned int *) __ret; \
})
-#define __LDCW "ldcw"
-#else /*CONFIG_PA20*/
-/* From: "Jim Hull"
- I've attached a summary of the change, but basically, for PA 2.0, as
- long as the ",CO" (coherent operation) completer is specified, then the
- 16-byte alignment requirement for ldcw and ldcd is relaxed, and instead
- they only require "natural" alignment (4-byte for ldcw, 8-byte for
- ldcd). */
-
-#define __PA_LDCW_ALIGNMENT 4
-#define __PA_LDCW_ALIGN_ORDER 2
-#define __ldcw_align(a) (&(a)->slock)
+#ifdef CONFIG_PA20
#define __LDCW "ldcw,co"
-
-#endif /*!CONFIG_PA20*/
+#else
+#define __LDCW "ldcw"
+#endif
/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.
We don't explicitly expose that "*a" may be written as reload
diff --git a/arch/parisc/include/asm/ropes.h b/arch/parisc/include/asm/ropes.h
index 8e51c775c80a6f9a8cfd55b12575956082bc9470..62399c7ea94a1cf58906607139fcb9c9cd196fd4 100644
--- a/arch/parisc/include/asm/ropes.h
+++ b/arch/parisc/include/asm/ropes.h
@@ -86,6 +86,9 @@ struct sba_device {
struct ioc ioc[MAX_IOC];
};
+/* list of SBA's in system, see drivers/parisc/sba_iommu.c */
+extern struct sba_device *sba_list;
+
#define ASTRO_RUNWAY_PORT 0x582
#define IKE_MERCED_PORT 0x803
#define REO_MERCED_PORT 0x804
diff --git a/arch/parisc/include/asm/spinlock_types.h b/arch/parisc/include/asm/spinlock_types.h
index 42979c5704dc64a455b35fdd80a22b2c346abfa9..82d2384c3f2227a9e85ddc442d8eeccc0ca3801f 100644
--- a/arch/parisc/include/asm/spinlock_types.h
+++ b/arch/parisc/include/asm/spinlock_types.h
@@ -3,13 +3,8 @@
#define __ASM_SPINLOCK_TYPES_H
typedef struct {
-#ifdef CONFIG_PA20
- volatile unsigned int slock;
-# define __ARCH_SPIN_LOCK_UNLOCKED { 1 }
-#else
volatile unsigned int lock[4];
# define __ARCH_SPIN_LOCK_UNLOCKED { { 1, 1, 1, 1 } }
-#endif
} arch_spinlock_t;
typedef struct {
diff --git a/arch/parisc/kernel/drivers.c b/arch/parisc/kernel/drivers.c
index 01a2ed59d2f2ac35025af0903e8fb43606a3f671..94037c8512f782ab9604202970fb5db1f01e808d 100644
--- a/arch/parisc/kernel/drivers.c
+++ b/arch/parisc/kernel/drivers.c
@@ -903,9 +903,9 @@ static __init void qemu_header(void)
pr_info("#define PARISC_MODEL \"%s\"\n\n",
boot_cpu_data.pdc.sys_model_name);
+ #define p ((unsigned long *)&boot_cpu_data.pdc.model)
pr_info("#define PARISC_PDC_MODEL 0x%lx, 0x%lx, 0x%lx, "
"0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx\n\n",
- #define p ((unsigned long *)&boot_cpu_data.pdc.model)
p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]);
#undef p
diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c
index c152c30c2d06d0a5670f334f7542279ffe0419e8..11c1505775f87416026a50fdb7002c18710d0555 100644
--- a/arch/parisc/kernel/irq.c
+++ b/arch/parisc/kernel/irq.c
@@ -392,7 +392,7 @@ union irq_stack_union {
volatile unsigned int lock[1];
};
-DEFINE_PER_CPU(union irq_stack_union, irq_stack_union) = {
+static DEFINE_PER_CPU(union irq_stack_union, irq_stack_union) = {
.slock = { 1,1,1,1 },
};
#endif
diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h b/arch/powerpc/include/asm/nohash/64/pgtable.h
index 7cd6809f4d332321e5f7eb806693e94fd5915b48..30fcffc02caad75018adab9e5c359c323ba32be3 100644
--- a/arch/powerpc/include/asm/nohash/64/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/64/pgtable.h
@@ -215,7 +215,7 @@ static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
{
unsigned long old;
- if (pte_young(*ptep))
+ if (!pte_young(*ptep))
return 0;
old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
return (old & _PAGE_ACCESSED) != 0;
diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c
index 2bb798918483dc9029b59e2b0d33fa34d24925b3..e6eb2b4cf97eaaf89fc79d73dd4510133501d557 100644
--- a/arch/powerpc/perf/hv-24x7.c
+++ b/arch/powerpc/perf/hv-24x7.c
@@ -1326,7 +1326,7 @@ static int h_24x7_event_init(struct perf_event *event)
}
domain = event_get_domain(event);
- if (domain >= HV_PERF_DOMAIN_MAX) {
+ if (domain == 0 || domain >= HV_PERF_DOMAIN_MAX) {
pr_devel("invalid domain %d\n", domain);
return -EINVAL;
}
diff --git a/arch/s390/pci/pci_dma.c b/arch/s390/pci/pci_dma.c
index d387a0fbdd7e4d6d2cb3f3e646bbdad6c42ff2a3..76d27a5947d541a8f33a3b5262aac765e2c03119 100644
--- a/arch/s390/pci/pci_dma.c
+++ b/arch/s390/pci/pci_dma.c
@@ -545,6 +545,17 @@ static void s390_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
s->dma_length = 0;
}
}
+
+static unsigned long *bitmap_vzalloc(size_t bits, gfp_t flags)
+{
+ size_t n = BITS_TO_LONGS(bits);
+ size_t bytes;
+
+ if (unlikely(check_mul_overflow(n, sizeof(unsigned long), &bytes)))
+ return NULL;
+
+ return vzalloc(bytes);
+}
static int s390_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
@@ -586,13 +597,13 @@ int zpci_dma_init_device(struct zpci_dev *zdev)
zdev->end_dma - zdev->start_dma + 1);
zdev->end_dma = zdev->start_dma + zdev->iommu_size - 1;
zdev->iommu_pages = zdev->iommu_size >> PAGE_SHIFT;
- zdev->iommu_bitmap = vzalloc(zdev->iommu_pages / 8);
+ zdev->iommu_bitmap = bitmap_vzalloc(zdev->iommu_pages, GFP_KERNEL);
if (!zdev->iommu_bitmap) {
rc = -ENOMEM;
goto free_dma_table;
}
if (!s390_iommu_strict) {
- zdev->lazy_bitmap = vzalloc(zdev->iommu_pages / 8);
+ zdev->lazy_bitmap = bitmap_vzalloc(zdev->iommu_pages, GFP_KERNEL);
if (!zdev->lazy_bitmap) {
rc = -ENOMEM;
goto free_bitmap;
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index efedd16231ff4575aabdbc759fff0f3065285a9e..2ee7b3e0dcc1e4eeea3f1ddbb2f2d77d0f60e443 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -446,6 +446,10 @@
#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
+/* Zen4 */
+#define MSR_ZEN4_BP_CFG 0xc001102e
+#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
+
/* Fam 17h MSRs */
#define MSR_F17H_IRPERF 0xc00000e9
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 918a23704c0c5b487050da26801e26aef55e01a5..dee94961a667ab85940f8861cdb6cf1d5c45fb0d 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -366,6 +366,17 @@ void __init_or_module noinline apply_alternatives(struct alt_instr *start,
u8 insnbuf[MAX_PATCH_LEN];
DPRINTK("alt table %px, -> %px", start, end);
+
+ /*
+ * In the case CONFIG_X86_5LEVEL=y, KASAN_SHADOW_START is defined using
+ * cpu_feature_enabled(X86_FEATURE_LA57) and is therefore patched here.
+ * During the process, KASAN becomes confused seeing partial LA57
+ * conversion and triggers a false-positive out-of-bound report.
+ *
+ * Disable KASAN until the patching is complete.
+ */
+ kasan_disable_current();
+
/*
* The scan order should be from start to end. A later scanned
* alternative code can overwrite previously scanned alternative code.
@@ -426,6 +437,8 @@ void __init_or_module noinline apply_alternatives(struct alt_instr *start,
text_poke_early(instr, insnbuf, insnbuf_sz);
}
+
+ kasan_enable_current();
}
#ifdef CONFIG_SMP
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 69eb6a804d1d6b9be475509b64724607d0e3c8f9..dc41d4d7836e337191d508a01559161f8fbbaa05 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -72,6 +72,10 @@ static const int amd_zenbleed[] =
AMD_MODEL_RANGE(0x17, 0x90, 0x0, 0x91, 0xf),
AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
+static const int amd_erratum_1485[] =
+ AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
+ AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));
+
static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
{
int osvw_id = *erratum++;
@@ -1122,6 +1126,10 @@ static void init_amd(struct cpuinfo_x86 *c)
check_null_seg_clears_base(c);
zenbleed_check(c);
+
+ if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
+ cpu_has_amd_erratum(c, amd_erratum_1485))
+ msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
}
#ifdef CONFIG_X86_32
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 027941e3df682e6d97544fca66ce9ee949493cf3..256b00f456e6c81c8404edd7c13f2c88472d528c 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2201,13 +2201,17 @@ int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
{
u32 reg = kvm_lapic_get_reg(apic, lvt_type);
int vector, mode, trig_mode;
+ int r;
if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
vector = reg & APIC_VECTOR_MASK;
mode = reg & APIC_MODE_MASK;
trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
- return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
- NULL);
+
+ r = __apic_accept_irq(apic, mode, vector, 1, trig_mode, NULL);
+ if (r && lvt_type == APIC_LVTPC)
+ kvm_lapic_set_reg(apic, APIC_LVTPC, reg | APIC_LVT_MASKED);
+ return r;
}
return 0;
}
diff --git a/block/blk-core.c b/block/blk-core.c
index 73cd6b412ad3a4a125e7fd8f2550fc76dad61d7b..505a4cdaab11a7260c963537cb6548496c93eb2e 100644
--- a/block/blk-core.c
+++ b/block/blk-core.c
@@ -2133,11 +2133,11 @@ static void handle_bad_sector(struct bio *bio, sector_t maxsector)
{
char b[BDEVNAME_SIZE];
- printk(KERN_INFO "attempt to access beyond end of device\n");
- printk(KERN_INFO "%s: rw=%d, want=%Lu, limit=%Lu\n",
- bio_devname(bio, b), bio->bi_opf,
- (unsigned long long)bio_end_sector(bio),
- (long long)maxsector);
+ pr_info_ratelimited("attempt to access beyond end of device\n"
+ "%s: rw=%d, want=%Lu, limit=%Lu\n",
+ bio_devname(bio, b), bio->bi_opf,
+ (unsigned long long)bio_end_sector(bio),
+ (long long)maxsector);
}
#ifdef CONFIG_FAIL_MAKE_REQUEST
diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c
index 7c352cba052893bb59f135b597f797a345974cd4..8ac01375fe8fdd47452b67c09cadfaa15cafe714 100644
--- a/drivers/acpi/irq.c
+++ b/drivers/acpi/irq.c
@@ -55,6 +55,7 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger,
int polarity)
{
struct irq_fwspec fwspec;
+ unsigned int irq;
if (WARN_ON(!acpi_gsi_domain_id)) {
pr_warn("GSI: No registered irqchip, giving up\n");
@@ -66,7 +67,11 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger,
fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity);
fwspec.param_count = 2;
- return irq_create_fwspec_mapping(&fwspec);
+ irq = irq_create_fwspec_mapping(&fwspec);
+ if (!irq)
+ return -EINVAL;
+
+ return irq;
}
EXPORT_SYMBOL_GPL(acpi_register_gsi);
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 13fb983b3413e50ae6488dc54f8cadf7fb67b43c..ab3ea47ecce3a8dedab513be15ea622f22bbec35 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -694,7 +694,7 @@ static void ahci_pci_init_controller(struct ata_host *host)
/* clear port IRQ */
tmp = readl(port_mmio + PORT_IRQ_STAT);
- VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
+ dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
if (tmp)
writel(tmp, port_mmio + PORT_IRQ_STAT);
}
@@ -1504,7 +1504,6 @@ static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
u32 irq_stat, irq_masked;
unsigned int handled = 1;
- VPRINTK("ENTER\n");
hpriv = host->private_data;
mmio = hpriv->mmio;
irq_stat = readl(mmio + HOST_IRQ_STAT);
@@ -1521,7 +1520,6 @@ static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
irq_stat = readl(mmio + HOST_IRQ_STAT);
spin_unlock(&host->lock);
} while (irq_stat);
- VPRINTK("EXIT\n");
return IRQ_RETVAL(handled);
}
@@ -1866,6 +1864,15 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
else
dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
+ if (!(hpriv->cap & HOST_CAP_PART))
+ host->flags |= ATA_HOST_NO_PART;
+
+ if (!(hpriv->cap & HOST_CAP_SSC))
+ host->flags |= ATA_HOST_NO_SSC;
+
+ if (!(hpriv->cap2 & HOST_CAP2_SDS))
+ host->flags |= ATA_HOST_NO_DEVSLP;
+
if (pi.flags & ATA_FLAG_EM)
ahci_reset_em(host);
diff --git a/drivers/ata/ahci_xgene.c b/drivers/ata/ahci_xgene.c
index 7e157e1bf65e47f160a10b9e8a6a335bbaaa8d5c..04ad6a2250145f1e39e850927f3f5653c4eff7c2 100644
--- a/drivers/ata/ahci_xgene.c
+++ b/drivers/ata/ahci_xgene.c
@@ -601,8 +601,6 @@ static irqreturn_t xgene_ahci_irq_intr(int irq, void *dev_instance)
void __iomem *mmio;
u32 irq_stat, irq_masked;
- VPRINTK("ENTER\n");
-
hpriv = host->private_data;
mmio = hpriv->mmio;
@@ -625,8 +623,6 @@ static irqreturn_t xgene_ahci_irq_intr(int irq, void *dev_instance)
spin_unlock(&host->lock);
- VPRINTK("EXIT\n");
-
return IRQ_RETVAL(rc);
}
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index f1153e7ba3b3a2abc3769bf38fe5304ee25b7c0b..b93fad6939dac9aabf54f1544bfa2df56947f4ea 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -1210,6 +1210,26 @@ static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
return sprintf(buf, "%d\n", emp->blink_policy);
}
+static void ahci_port_clear_pending_irq(struct ata_port *ap)
+{
+ struct ahci_host_priv *hpriv = ap->host->private_data;
+ void __iomem *port_mmio = ahci_port_base(ap);
+ u32 tmp;
+
+ /* clear SError */
+ tmp = readl(port_mmio + PORT_SCR_ERR);
+ dev_dbg(ap->host->dev, "PORT_SCR_ERR 0x%x\n", tmp);
+ writel(tmp, port_mmio + PORT_SCR_ERR);
+
+ /* clear port IRQ */
+ tmp = readl(port_mmio + PORT_IRQ_STAT);
+ dev_dbg(ap->host->dev, "PORT_IRQ_STAT 0x%x\n", tmp);
+ if (tmp)
+ writel(tmp, port_mmio + PORT_IRQ_STAT);
+
+ writel(1 << ap->port_no, hpriv->mmio + HOST_IRQ_STAT);
+}
+
static void ahci_port_init(struct device *dev, struct ata_port *ap,
int port_no, void __iomem *mmio,
void __iomem *port_mmio)
@@ -1224,18 +1244,7 @@ static void ahci_port_init(struct device *dev, struct ata_port *ap,
if (rc)
dev_warn(dev, "%s (%d)\n", emsg, rc);
- /* clear SError */
- tmp = readl(port_mmio + PORT_SCR_ERR);
- VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
- writel(tmp, port_mmio + PORT_SCR_ERR);
-
- /* clear port IRQ */
- tmp = readl(port_mmio + PORT_IRQ_STAT);
- VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
- if (tmp)
- writel(tmp, port_mmio + PORT_IRQ_STAT);
-
- writel(1 << port_no, mmio + HOST_IRQ_STAT);
+ ahci_port_clear_pending_irq(ap);
/* mark esata ports */
tmp = readl(port_mmio + PORT_CMD);
@@ -1262,10 +1271,10 @@ void ahci_init_controller(struct ata_host *host)
}
tmp = readl(mmio + HOST_CTL);
- VPRINTK("HOST_CTL 0x%x\n", tmp);
+ dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
tmp = readl(mmio + HOST_CTL);
- VPRINTK("HOST_CTL 0x%x\n", tmp);
+ dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp);
}
EXPORT_SYMBOL_GPL(ahci_init_controller);
@@ -1565,6 +1574,8 @@ int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
tf.command = ATA_BUSY;
ata_tf_to_fis(&tf, 0, 0, d2h_fis);
+ ahci_port_clear_pending_irq(ap);
+
rc = sata_link_hardreset(link, timing, deadline, online,
ahci_check_ready);
@@ -1916,8 +1927,6 @@ static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
void __iomem *port_mmio = ahci_port_base(ap);
u32 status;
- VPRINTK("ENTER\n");
-
status = readl(port_mmio + PORT_IRQ_STAT);
writel(status, port_mmio + PORT_IRQ_STAT);
@@ -1925,8 +1934,6 @@ static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
ahci_handle_port_interrupt(ap, port_mmio, status);
spin_unlock(ap->lock);
- VPRINTK("EXIT\n");
-
return IRQ_HANDLED;
}
@@ -1943,9 +1950,7 @@ u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
ap = host->ports[i];
if (ap) {
ahci_port_intr(ap);
- VPRINTK("port %u\n", i);
} else {
- VPRINTK("port %u (no irq)\n", i);
if (ata_ratelimit())
dev_warn(host->dev,
"interrupt on disabled port %u\n", i);
@@ -1966,8 +1971,6 @@ static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
void __iomem *mmio;
u32 irq_stat, irq_masked;
- VPRINTK("ENTER\n");
-
hpriv = host->private_data;
mmio = hpriv->mmio;
@@ -1995,8 +1998,6 @@ static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
spin_unlock(&host->lock);
- VPRINTK("EXIT\n");
-
return IRQ_RETVAL(rc);
}
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 4a7da8f744e03eb0ab8b581df4c713418f876dbe..2b9f6769f80d714af909d297ee714aa69b707ce5 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -3997,10 +3997,23 @@ int sata_link_scr_lpm(struct ata_link *link, enum ata_lpm_policy policy,
case ATA_LPM_MED_POWER_WITH_DIPM:
case ATA_LPM_MIN_POWER_WITH_PARTIAL:
case ATA_LPM_MIN_POWER:
- if (ata_link_nr_enabled(link) > 0)
- /* no restrictions on LPM transitions */
+ if (ata_link_nr_enabled(link) > 0) {
+ /* assume no restrictions on LPM transitions */
scontrol &= ~(0x7 << 8);
- else {
+
+ /*
+ * If the controller does not support partial, slumber,
+ * or devsleep, then disallow these transitions.
+ */
+ if (link->ap->host->flags & ATA_HOST_NO_PART)
+ scontrol |= (0x1 << 8);
+
+ if (link->ap->host->flags & ATA_HOST_NO_SSC)
+ scontrol |= (0x2 << 8);
+
+ if (link->ap->host->flags & ATA_HOST_NO_DEVSLP)
+ scontrol |= (0x4 << 8);
+ } else {
/* empty port, power off */
scontrol &= ~0xf;
scontrol |= (0x1 << 2);
@@ -5756,17 +5769,19 @@ static void ata_port_request_pm(struct ata_port *ap, pm_message_t mesg,
struct ata_link *link;
unsigned long flags;
- /* Previous resume operation might still be in
- * progress. Wait for PM_PENDING to clear.
+ spin_lock_irqsave(ap->lock, flags);
+
+ /*
+ * A previous PM operation might still be in progress. Wait for
+ * ATA_PFLAG_PM_PENDING to clear.
*/
if (ap->pflags & ATA_PFLAG_PM_PENDING) {
+ spin_unlock_irqrestore(ap->lock, flags);
ata_port_wait_eh(ap);
- WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
+ spin_lock_irqsave(ap->lock, flags);
}
- /* request PM ops to EH */
- spin_lock_irqsave(ap->lock, flags);
-
+ /* Request PM operation to EH */
ap->pm_mesg = mesg;
ap->pflags |= ATA_PFLAG_PM_PENDING;
ata_for_each_link(link, ap, HOST_FIRST) {
@@ -5778,10 +5793,8 @@ static void ata_port_request_pm(struct ata_port *ap, pm_message_t mesg,
spin_unlock_irqrestore(ap->lock, flags);
- if (!async) {
+ if (!async)
ata_port_wait_eh(ap);
- WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING);
- }
}
/*
@@ -5947,7 +5960,7 @@ void ata_host_resume(struct ata_host *host)
#endif
const struct device_type ata_port_type = {
- .name = "ata_port",
+ .name = ATA_PORT_TYPE_NAME,
#ifdef CONFIG_PM
.pm = &ata_port_pm_ops,
#endif
@@ -6750,11 +6763,30 @@ static void ata_port_detach(struct ata_port *ap)
if (!ap->ops->error_handler)
goto skip_eh;
- /* tell EH we're leaving & flush EH */
+ /* Wait for any ongoing EH */
+ ata_port_wait_eh(ap);
+
+ mutex_lock(&ap->scsi_scan_mutex);
spin_lock_irqsave(ap->lock, flags);
+
+ /* Remove scsi devices */
+ ata_for_each_link(link, ap, HOST_FIRST) {
+ ata_for_each_dev(dev, link, ALL) {
+ if (dev->sdev) {
+ spin_unlock_irqrestore(ap->lock, flags);
+ scsi_remove_device(dev->sdev);
+ spin_lock_irqsave(ap->lock, flags);
+ dev->sdev = NULL;
+ }
+ }
+ }
+
+ /* Tell EH to disable all devices */
ap->pflags |= ATA_PFLAG_UNLOADING;
ata_port_schedule_eh(ap);
+
spin_unlock_irqrestore(ap->lock, flags);
+ mutex_unlock(&ap->scsi_scan_mutex);
/* wait till EH commits suicide */
ata_port_wait_eh(ap);
diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c
index fcc3d7985762a3a7066ecdff550a81e5ca970009..63423d9e1457c6fa6e34b79bb9c695638c5a7804 100644
--- a/drivers/ata/libata-eh.c
+++ b/drivers/ata/libata-eh.c
@@ -2443,7 +2443,7 @@ static void ata_eh_link_report(struct ata_link *link)
struct ata_eh_context *ehc = &link->eh_context;
struct ata_queued_cmd *qc;
const char *frozen, *desc;
- char tries_buf[6] = "";
+ char tries_buf[16] = "";
int tag, nr_failed = 0;
if (ehc->i.flags & ATA_EHI_QUIET)
@@ -2922,18 +2922,11 @@ int ata_eh_reset(struct ata_link *link, int classify,
postreset(slave, classes);
}
- /*
- * Some controllers can't be frozen very well and may set spurious
- * error conditions during reset. Clear accumulated error
- * information and re-thaw the port if frozen. As reset is the
- * final recovery action and we cross check link onlineness against
- * device classification later, no hotplug event is lost by this.
- */
+ /* clear cached SError */
spin_lock_irqsave(link->ap->lock, flags);
- memset(&link->eh_info, 0, sizeof(link->eh_info));
+ link->eh_info.serror = 0;
if (slave)
- memset(&slave->eh_info, 0, sizeof(link->eh_info));
- ap->pflags &= ~ATA_PFLAG_EH_PENDING;
+ slave->eh_info.serror = 0;
spin_unlock_irqrestore(link->ap->lock, flags);
if (ap->pflags & ATA_PFLAG_FROZEN)
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index 2295b74714e15aafdb83a590b2f29c6b4465c78e..dc52239812709dbccfb9394622dcc18778f4b9bf 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -4561,7 +4561,7 @@ void ata_scsi_simulate(struct ata_device *dev, struct scsi_cmnd *cmd)
break;
case MAINTENANCE_IN:
- if (scsicmd[1] == MI_REPORT_SUPPORTED_OPERATION_CODES)
+ if ((scsicmd[1] & 0x1f) == MI_REPORT_SUPPORTED_OPERATION_CODES)
ata_scsi_rbuf_fill(&args, ata_scsiop_maint_in);
else
ata_scsi_set_invalid_field(dev, cmd, 1, 0xff);
diff --git a/drivers/ata/libata-transport.c b/drivers/ata/libata-transport.c
index f04f4f977400da0f179b0c9d03646c7fb8e8f503..5eae76d8b65509aeda849ade5ec1a71a26f92645 100644
--- a/drivers/ata/libata-transport.c
+++ b/drivers/ata/libata-transport.c
@@ -266,6 +266,10 @@ void ata_tport_delete(struct ata_port *ap)
put_device(dev);
}
+static const struct device_type ata_port_sas_type = {
+ .name = ATA_PORT_TYPE_NAME,
+};
+
/** ata_tport_add - initialize a transport ATA port structure
*
* @parent: parent device
@@ -283,7 +287,10 @@ int ata_tport_add(struct device *parent,
struct device *dev = &ap->tdev;
device_initialize(dev);
- dev->type = &ata_port_type;
+ if (ap->flags & ATA_FLAG_SAS_HOST)
+ dev->type = &ata_port_sas_type;
+ else
+ dev->type = &ata_port_type;
dev->parent = parent;
ata_host_get(ap->host);
diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h
index f953cb4bb1ba8fe015167d522e08c11b17fa91c7..b568d6b9350a6e00075277194542f5245920f778 100644
--- a/drivers/ata/libata.h
+++ b/drivers/ata/libata.h
@@ -46,6 +46,8 @@ enum {
ATA_DNXFER_QUIET = (1 << 31),
};
+#define ATA_PORT_TYPE_NAME "ata_port"
+
extern atomic_t ata_print_id;
extern int atapi_passthru16;
extern int libata_fua;
diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
index 80c987446607ab3af4b12bdad67f88dd6435fc73..b5f61f2840d0136a55491e131cc15f74a3a1b71e 100644
--- a/drivers/base/arch_topology.c
+++ b/drivers/base/arch_topology.c
@@ -68,7 +68,7 @@ static ssize_t cpu_capacity_show(struct device *dev,
{
struct cpu *cpu = container_of(dev, struct cpu, dev);
- return sysfs_emit(buf, "%lu\n", topology_get_cpu_scale(NULL, cpu->dev.id));
+ return sprintf(buf, "%lu\n", topology_get_cpu_scale(NULL, cpu->dev.id));
}
static void update_topology_flags_workfn(struct work_struct *work);
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index 51eb403f89de677ca878f21e5d50f964f194aea2..ce015ce2977c47a898b6c1d0de66ac2e9b2d89c4 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -372,7 +372,7 @@ static ssize_t size_show(struct device *dev,
{
struct cacheinfo *this_leaf = dev_get_drvdata(dev);
- return sysfs_emit(buf, "%uK\n", this_leaf->size >> 10);
+ return sprintf(buf, "%uK\n", this_leaf->size >> 10);
}
static ssize_t shared_cpumap_show_func(struct device *dev, bool list, char *buf)
@@ -402,11 +402,11 @@ static ssize_t type_show(struct device *dev,
switch (this_leaf->type) {
case CACHE_TYPE_DATA:
- return sysfs_emit(buf, "Data\n");
+ return sprintf(buf, "Data\n");
case CACHE_TYPE_INST:
- return sysfs_emit(buf, "Instruction\n");
+ return sprintf(buf, "Instruction\n");
case CACHE_TYPE_UNIFIED:
- return sysfs_emit(buf, "Unified\n");
+ return sprintf(buf, "Unified\n");
default:
return -EINVAL;
}
@@ -420,11 +420,11 @@ static ssize_t allocation_policy_show(struct device *dev,
int n = 0;
if ((ci_attr & CACHE_READ_ALLOCATE) && (ci_attr & CACHE_WRITE_ALLOCATE))
- n = sysfs_emit(buf, "ReadWriteAllocate\n");
+ n = sprintf(buf, "ReadWriteAllocate\n");
else if (ci_attr & CACHE_READ_ALLOCATE)
- n = sysfs_emit(buf, "ReadAllocate\n");
+ n = sprintf(buf, "ReadAllocate\n");
else if (ci_attr & CACHE_WRITE_ALLOCATE)
- n = sysfs_emit(buf, "WriteAllocate\n");
+ n = sprintf(buf, "WriteAllocate\n");
return n;
}
@@ -436,9 +436,9 @@ static ssize_t write_policy_show(struct device *dev,
int n = 0;
if (ci_attr & CACHE_WRITE_THROUGH)
- n = sysfs_emit(buf, "WriteThrough\n");
+ n = sprintf(buf, "WriteThrough\n");
else if (ci_attr & CACHE_WRITE_BACK)
- n = sysfs_emit(buf, "WriteBack\n");
+ n = sprintf(buf, "WriteBack\n");
return n;
}
diff --git a/drivers/base/core.c b/drivers/base/core.c
index 6239159e44d84e7c7b55a05201fae1c85b629078..18b08b4cb760cf4845fe4dafe1062f1b035db197 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -1442,7 +1442,7 @@ ssize_t device_show_ulong(struct device *dev,
char *buf)
{
struct dev_ext_attribute *ea = to_ext_attr(attr);
- return sysfs_emit(buf, "%lx\n", *(unsigned long *)(ea->var));
+ return snprintf(buf, PAGE_SIZE, "%lx\n", *(unsigned long *)(ea->var));
}
EXPORT_SYMBOL_GPL(device_show_ulong);
@@ -1467,7 +1467,7 @@ ssize_t device_show_int(struct device *dev,
{
struct dev_ext_attribute *ea = to_ext_attr(attr);
- return sysfs_emit(buf, "%d\n", *(int *)(ea->var));
+ return snprintf(buf, PAGE_SIZE, "%d\n", *(int *)(ea->var));
}
EXPORT_SYMBOL_GPL(device_show_int);
@@ -1488,7 +1488,7 @@ ssize_t device_show_bool(struct device *dev, struct device_attribute *attr,
{
struct dev_ext_attribute *ea = to_ext_attr(attr);
- return sysfs_emit(buf, "%d\n", *(bool *)(ea->var));
+ return snprintf(buf, PAGE_SIZE, "%d\n", *(bool *)(ea->var));
}
EXPORT_SYMBOL_GPL(device_show_bool);
@@ -1721,7 +1721,7 @@ static ssize_t online_show(struct device *dev, struct device_attribute *attr,
device_lock(dev);
val = !dev->offline;
device_unlock(dev);
- return sysfs_emit(buf, "%u\n", val);
+ return sprintf(buf, "%u\n", val);
}
static ssize_t online_store(struct device *dev, struct device_attribute *attr,
diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c
index 64be4372919c9e1661afe6020e6f1bb6f8e529aa..b9b249843e076baf602bc0df63559762c84cd778 100644
--- a/drivers/base/cpu.c
+++ b/drivers/base/cpu.c
@@ -156,7 +156,7 @@ static ssize_t show_crash_notes(struct device *dev, struct device_attribute *att
* operation should be safe. No locking required.
*/
addr = per_cpu_ptr_to_phys(per_cpu_ptr(crash_notes, cpunum));
- rc = sysfs_emit(buf, "%Lx\n", addr);
+ rc = sprintf(buf, "%Lx\n", addr);
return rc;
}
static DEVICE_ATTR(crash_notes, 0400, show_crash_notes, NULL);
@@ -167,7 +167,7 @@ static ssize_t show_crash_notes_size(struct device *dev,
{
ssize_t rc;
- rc = sysfs_emit(buf, "%zu\n", sizeof(note_buf_t));
+ rc = sprintf(buf, "%zu\n", sizeof(note_buf_t));
return rc;
}
static DEVICE_ATTR(crash_notes_size, 0400, show_crash_notes_size, NULL);
@@ -354,7 +354,7 @@ static ssize_t print_cpus_offline(struct device *dev,
nr_cpu_ids, total_cpus-1);
}
- n += sysfs_emit(&buf[n], "\n");
+ n += snprintf(&buf[n], len - n, "\n");
return n;
}
static DEVICE_ATTR(offline, 0444, print_cpus_offline, NULL);
@@ -362,7 +362,7 @@ static DEVICE_ATTR(offline, 0444, print_cpus_offline, NULL);
static ssize_t print_cpus_isolated(struct device *dev,
struct device_attribute *attr, char *buf)
{
- int n = 0;
+ int n = 0, len = PAGE_SIZE-2;
cpumask_var_t isolated;
if (!alloc_cpumask_var(&isolated, GFP_KERNEL))
@@ -370,7 +370,7 @@ static ssize_t print_cpus_isolated(struct device *dev,
cpumask_andnot(isolated, cpu_possible_mask,
housekeeping_cpumask(HK_FLAG_DOMAIN));
- n = sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(isolated));
+ n = scnprintf(buf, len, "%*pbl\n", cpumask_pr_args(isolated));
free_cpumask_var(isolated);
@@ -382,9 +382,9 @@ static DEVICE_ATTR(isolated, 0444, print_cpus_isolated, NULL);
static ssize_t print_cpus_nohz_full(struct device *dev,
struct device_attribute *attr, char *buf)
{
- int n = 0;
+ int n = 0, len = PAGE_SIZE-2;
- n = sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(tick_nohz_full_mask));
+ n = scnprintf(buf, len, "%*pbl\n", cpumask_pr_args(tick_nohz_full_mask));
return n;
}
@@ -418,7 +418,7 @@ static ssize_t print_cpu_modalias(struct device *dev,
ssize_t n;
u32 i;
- n = sysfs_emit(buf, "cpu:type:" CPU_FEATURE_TYPEFMT ":feature:",
+ n = sprintf(buf, "cpu:type:" CPU_FEATURE_TYPEFMT ":feature:",
CPU_FEATURE_TYPEVAL);
for (i = 0; i < MAX_CPU_FEATURES; i++)
@@ -612,56 +612,56 @@ static void __init cpu_dev_register_generic(void)
ssize_t __weak cpu_show_meltdown(struct device *dev,
struct device_attribute *attr, char *buf)
{
- return sysfs_emit(buf, "Not affected\n");
+ return sprintf(buf, "Not affected\n");
}
ssize_t __weak cpu_show_spectre_v1(struct device *dev,
struct device_attribute *attr, char *buf)
{
- return sysfs_emit(buf, "Not affected\n");
+ return sprintf(buf, "Not affected\n");
}
ssize_t __weak cpu_show_spectre_v2(struct device *dev,
struct device_attribute *attr, char *buf)
{
- return sysfs_emit(buf, "Not affected\n");
+ return sprintf(buf, "Not affected\n");
}
ssize_t __weak cpu_show_spec_store_bypass(struct device *dev,
struct device_attribute *attr, char *buf)
{
- return sysfs_emit(buf, "Not affected\n");
+ return sprintf(buf, "Not affected\n");
}
ssize_t __weak cpu_show_l1tf(struct device *dev,
struct device_attribute *attr, char *buf)
{
- return sysfs_emit(buf, "Not affected\n");
+ return sprintf(buf, "Not affected\n");
}
ssize_t __weak cpu_show_mds(struct device *dev,
struct device_attribute *attr, char *buf)
{
- return sysfs_emit(buf, "Not affected\n");
+ return sprintf(buf, "Not affected\n");
}
ssize_t __weak cpu_show_tsx_async_abort(struct device *dev,
struct device_attribute *attr,
char *buf)
{
- return sysfs_emit(buf, "Not affected\n");
+ return sprintf(buf, "Not affected\n");
}
ssize_t __weak cpu_show_itlb_multihit(struct device *dev,
struct device_attribute *attr, char *buf)
{
- return sysfs_emit(buf, "Not affected\n");
+ return sprintf(buf, "Not affected\n");
}
ssize_t __weak cpu_show_srbds(struct device *dev,
struct device_attribute *attr, char *buf)
{
- return sysfs_emit(buf, "Not affected\n");
+ return sprintf(buf, "Not affected\n");
}
ssize_t __weak cpu_show_mmio_stale_data(struct device *dev,
diff --git a/drivers/base/firmware_loader/fallback.c b/drivers/base/firmware_loader/fallback.c
index 2116926cc1d57b627f0d91813a10301359f20ddf..821e27bda4ca21c06e9621b750d9339952d7467d 100644
--- a/drivers/base/firmware_loader/fallback.c
+++ b/drivers/base/firmware_loader/fallback.c
@@ -215,7 +215,7 @@ static ssize_t firmware_loading_show(struct device *dev,
loading = fw_sysfs_loading(fw_sysfs->fw_priv);
mutex_unlock(&fw_lock);
- return sysfs_emit(buf, "%d\n", loading);
+ return sprintf(buf, "%d\n", loading);
}
/* one pages buffer should be mapped/unmapped only once */
diff --git a/drivers/base/memory.c b/drivers/base/memory.c
index 6f0df3ece568c27cb22c42575c1f9c53f50285d8..25090f9284f729e877ae9a5afaa1cb83dafd593a 100644
--- a/drivers/base/memory.c
+++ b/drivers/base/memory.c
@@ -121,7 +121,7 @@ static ssize_t phys_index_show(struct device *dev,
unsigned long phys_index;
phys_index = mem->start_section_nr / sections_per_block;
- return sysfs_emit(buf, "%08lx\n", phys_index);
+ return sprintf(buf, "%08lx\n", phys_index);
}
/*
@@ -145,7 +145,7 @@ static ssize_t show_mem_removable(struct device *dev,
}
out:
- return sysfs_emit(buf, "%d\n", ret);
+ return sprintf(buf, "%d\n", ret);
}
/*
@@ -163,17 +163,17 @@ static ssize_t show_mem_state(struct device *dev,
*/
switch (mem->state) {
case MEM_ONLINE:
- len = sysfs_emit(buf, "online\n");
+ len = sprintf(buf, "online\n");
break;
case MEM_OFFLINE:
- len = sysfs_emit(buf, "offline\n");
+ len = sprintf(buf, "offline\n");
break;
case MEM_GOING_OFFLINE:
- len = sysfs_emit(buf, "going-offline\n");
+ len = sprintf(buf, "going-offline\n");
break;
default:
- len = sysfs_emit(buf, "ERROR-UNKNOWN-%ld\n",
- mem->state);
+ len = sprintf(buf, "ERROR-UNKNOWN-%ld\n",
+ mem->state);
WARN_ON(1);
break;
}
@@ -384,7 +384,7 @@ static ssize_t show_phys_device(struct device *dev,
struct device_attribute *attr, char *buf)
{
struct memory_block *mem = to_memory_block(dev);
- return sysfs_emit(buf, "%d\n", mem->phys_device);
+ return sprintf(buf, "%d\n", mem->phys_device);
}
#ifdef CONFIG_MEMORY_HOTREMOVE
@@ -422,7 +422,7 @@ static ssize_t show_valid_zones(struct device *dev,
*/
if (!test_pages_in_a_zone(start_pfn, start_pfn + nr_pages,
&valid_start_pfn, &valid_end_pfn))
- return sysfs_emit(buf, "none\n");
+ return sprintf(buf, "none\n");
start_pfn = valid_start_pfn;
strcat(buf, page_zone(pfn_to_page(start_pfn))->name);
goto out;
@@ -508,7 +508,7 @@ static ssize_t
print_block_size(struct device *dev, struct device_attribute *attr,
char *buf)
{
- return sysfs_emit(buf, "%lx\n", get_memory_block_size());
+ return sprintf(buf, "%lx\n", get_memory_block_size());
}
static DEVICE_ATTR(block_size_bytes, 0444, print_block_size, NULL);
@@ -522,9 +522,9 @@ show_auto_online_blocks(struct device *dev, struct device_attribute *attr,
char *buf)
{
if (memhp_auto_online)
- return sysfs_emit(buf, "online\n");
+ return sprintf(buf, "online\n");
else
- return sysfs_emit(buf, "offline\n");
+ return sprintf(buf, "offline\n");
}
static ssize_t
diff --git a/drivers/base/node.c b/drivers/base/node.c
index 845fcb17842d988ed4282bd42729f7df2e4dd50c..2d49e972537a45091e1233bc638baa45911bf5a8 100644
--- a/drivers/base/node.c
+++ b/drivers/base/node.c
@@ -99,7 +99,7 @@ static ssize_t node_read_meminfo(struct device *dev,
nid, K(sum_zone_node_page_state(nid, NR_MLOCK)));
#ifdef CONFIG_HIGHMEM
- n += sysfs_emit(buf + n,
+ n += sprintf(buf + n,
"Node %d HighTotal: %8lu kB\n"
"Node %d HighFree: %8lu kB\n"
"Node %d LowTotal: %8lu kB\n"
@@ -109,7 +109,7 @@ static ssize_t node_read_meminfo(struct device *dev,
nid, K(i.totalram - i.totalhigh),
nid, K(i.freeram - i.freehigh));
#endif
- n += sysfs_emit(buf + n,
+ n += sprintf(buf + n,
"Node %d Dirty: %8lu kB\n"
"Node %d Writeback: %8lu kB\n"
"Node %d FilePages: %8lu kB\n"
@@ -173,19 +173,19 @@ static DEVICE_ATTR(meminfo, S_IRUGO, node_read_meminfo, NULL);
static ssize_t node_read_numastat(struct device *dev,
struct device_attribute *attr, char *buf)
{
- return sysfs_emit(buf,
- "numa_hit %lu\n"
- "numa_miss %lu\n"
- "numa_foreign %lu\n"
- "interleave_hit %lu\n"
- "local_node %lu\n"
- "other_node %lu\n",
- sum_zone_numa_state(dev->id, NUMA_HIT),
- sum_zone_numa_state(dev->id, NUMA_MISS),
- sum_zone_numa_state(dev->id, NUMA_FOREIGN),
- sum_zone_numa_state(dev->id, NUMA_INTERLEAVE_HIT),
- sum_zone_numa_state(dev->id, NUMA_LOCAL),
- sum_zone_numa_state(dev->id, NUMA_OTHER));
+ return sprintf(buf,
+ "numa_hit %lu\n"
+ "numa_miss %lu\n"
+ "numa_foreign %lu\n"
+ "interleave_hit %lu\n"
+ "local_node %lu\n"
+ "other_node %lu\n",
+ sum_zone_numa_state(dev->id, NUMA_HIT),
+ sum_zone_numa_state(dev->id, NUMA_MISS),
+ sum_zone_numa_state(dev->id, NUMA_FOREIGN),
+ sum_zone_numa_state(dev->id, NUMA_INTERLEAVE_HIT),
+ sum_zone_numa_state(dev->id, NUMA_LOCAL),
+ sum_zone_numa_state(dev->id, NUMA_OTHER));
}
static DEVICE_ATTR(numastat, S_IRUGO, node_read_numastat, NULL);
@@ -623,7 +623,7 @@ static ssize_t print_nodes_state(enum node_states state, char *buf)
{
int n;
- n = sysfs_emit(buf, "%*pbl",
+ n = scnprintf(buf, PAGE_SIZE - 1, "%*pbl",
nodemask_pr_args(&node_states[state]));
buf[n++] = '\n';
buf[n] = '\0';
diff --git a/drivers/base/platform.c b/drivers/base/platform.c
index 1819da6889a71e00b75c1068f980e916edc78acb..2f89e618b142c32afad7c8369b3d28170fa20744 100644
--- a/drivers/base/platform.c
+++ b/drivers/base/platform.c
@@ -927,7 +927,7 @@ static ssize_t driver_override_show(struct device *dev,
ssize_t len;
device_lock(dev);
- len = sysfs_emit(buf, "%s\n", pdev->driver_override);
+ len = sprintf(buf, "%s\n", pdev->driver_override);
device_unlock(dev);
return len;
}
diff --git a/drivers/base/power/sysfs.c b/drivers/base/power/sysfs.c
index e92e1ab71c0c7f268e8d3834cc0fc12efafe4da2..48ddeefd69328b510c0fd785a311faa81177ca85 100644
--- a/drivers/base/power/sysfs.c
+++ b/drivers/base/power/sysfs.c
@@ -102,7 +102,7 @@ static const char ctrl_on[] = "on";
static ssize_t control_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
- return sysfs_emit(buf, "%s\n",
+ return sprintf(buf, "%s\n",
dev->power.runtime_auto ? ctrl_auto : ctrl_on);
}
@@ -128,7 +128,7 @@ static ssize_t runtime_active_time_show(struct device *dev,
int ret;
spin_lock_irq(&dev->power.lock);
update_pm_runtime_accounting(dev);
- ret = sysfs_emit(buf, "%i\n", jiffies_to_msecs(dev->power.active_jiffies));
+ ret = sprintf(buf, "%i\n", jiffies_to_msecs(dev->power.active_jiffies));
spin_unlock_irq(&dev->power.lock);
return ret;
}
@@ -141,7 +141,7 @@ static ssize_t runtime_suspended_time_show(struct device *dev,
int ret;
spin_lock_irq(&dev->power.lock);
update_pm_runtime_accounting(dev);
- ret = sysfs_emit(buf, "%i\n",
+ ret = sprintf(buf, "%i\n",
jiffies_to_msecs(dev->power.suspended_jiffies));
spin_unlock_irq(&dev->power.lock);
return ret;
@@ -176,7 +176,7 @@ static ssize_t runtime_status_show(struct device *dev,
return -EIO;
}
}
- return sysfs_emit(buf, p);
+ return sprintf(buf, p);
}
static DEVICE_ATTR_RO(runtime_status);
@@ -186,7 +186,7 @@ static ssize_t autosuspend_delay_ms_show(struct device *dev,
{
if (!dev->power.use_autosuspend)
return -EIO;
- return sysfs_emit(buf, "%d\n", dev->power.autosuspend_delay);
+ return sprintf(buf, "%d\n", dev->power.autosuspend_delay);
}
static ssize_t autosuspend_delay_ms_store(struct device *dev,
@@ -215,11 +215,11 @@ static ssize_t pm_qos_resume_latency_us_show(struct device *dev,
s32 value = dev_pm_qos_requested_resume_latency(dev);
if (value == 0)
- return sysfs_emit(buf, "n/a\n");
+ return sprintf(buf, "n/a\n");
if (value == PM_QOS_RESUME_LATENCY_NO_CONSTRAINT)
value = 0;
- return sysfs_emit(buf, "%d\n", value);
+ return sprintf(buf, "%d\n", value);
}
static ssize_t pm_qos_resume_latency_us_store(struct device *dev,
@@ -259,11 +259,11 @@ static ssize_t pm_qos_latency_tolerance_us_show(struct device *dev,
s32 value = dev_pm_qos_get_user_latency_tolerance(dev);
if (value < 0)
- return sysfs_emit(buf, "auto\n");
+ return sprintf(buf, "auto\n");
if (value == PM_QOS_LATENCY_ANY)
- return sysfs_emit(buf, "any\n");
+ return sprintf(buf, "any\n");
- return sysfs_emit(buf, "%d\n", value);
+ return sprintf(buf, "%d\n", value);
}
static ssize_t pm_qos_latency_tolerance_us_store(struct device *dev,
@@ -295,8 +295,8 @@ static ssize_t pm_qos_no_power_off_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
- return sysfs_emit(buf, "%d\n", !!(dev_pm_qos_requested_flags(dev)
- & PM_QOS_FLAG_NO_POWER_OFF));
+ return sprintf(buf, "%d\n", !!(dev_pm_qos_requested_flags(dev)
+ & PM_QOS_FLAG_NO_POWER_OFF));
}
static ssize_t pm_qos_no_power_off_store(struct device *dev,
@@ -324,9 +324,9 @@ static const char _disabled[] = "disabled";
static ssize_t wakeup_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
- return sysfs_emit(buf, "%s\n", device_can_wakeup(dev)
- ? (device_may_wakeup(dev) ? _enabled : _disabled)
- : "");
+ return sprintf(buf, "%s\n", device_can_wakeup(dev)
+ ? (device_may_wakeup(dev) ? _enabled : _disabled)
+ : "");
}
static ssize_t wakeup_store(struct device *dev, struct device_attribute *attr,
@@ -512,7 +512,7 @@ static DEVICE_ATTR_RO(wakeup_prevent_sleep_time_ms);
static ssize_t runtime_usage_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
- return sysfs_emit(buf, "%d\n", atomic_read(&dev->power.usage_count));
+ return sprintf(buf, "%d\n", atomic_read(&dev->power.usage_count));
}
static DEVICE_ATTR_RO(runtime_usage);
@@ -520,8 +520,8 @@ static ssize_t runtime_active_kids_show(struct device *dev,
struct device_attribute *attr,
char *buf)
{
- return sysfs_emit(buf, "%d\n", dev->power.ignore_children ?
- 0 : atomic_read(&dev->power.child_count));
+ return sprintf(buf, "%d\n", dev->power.ignore_children ?
+ 0 : atomic_read(&dev->power.child_count));
}
static DEVICE_ATTR_RO(runtime_active_kids);
@@ -529,12 +529,12 @@ static ssize_t runtime_enabled_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
if (dev->power.disable_depth && (dev->power.runtime_auto == false))
- return sysfs_emit(buf, "disabled & forbidden\n");
+ return sprintf(buf, "disabled & forbidden\n");
if (dev->power.disable_depth)
- return sysfs_emit(buf, "disabled\n");
+ return sprintf(buf, "disabled\n");
if (dev->power.runtime_auto == false)
- return sysfs_emit(buf, "forbidden\n");
- return sysfs_emit(buf, "enabled\n");
+ return sprintf(buf, "forbidden\n");
+ return sprintf(buf, "enabled\n");
}
static DEVICE_ATTR_RO(runtime_enabled);
@@ -542,9 +542,9 @@ static DEVICE_ATTR_RO(runtime_enabled);
static ssize_t async_show(struct device *dev, struct device_attribute *attr,
char *buf)
{
- return sysfs_emit(buf, "%s\n",
- device_async_suspend_enabled(dev) ?
- _enabled : _disabled);
+ return sprintf(buf, "%s\n",
+ device_async_suspend_enabled(dev) ?
+ _enabled : _disabled);
}
static ssize_t async_store(struct device *dev, struct device_attribute *attr,
diff --git a/drivers/base/regmap/regcache-rbtree.c b/drivers/base/regmap/regcache-rbtree.c
index 7353c552708741f23a6cfa271aa6a7c68858b057..b6f8f4059e255407d40a54a1d534835e4e8225ea 100644
--- a/drivers/base/regmap/regcache-rbtree.c
+++ b/drivers/base/regmap/regcache-rbtree.c
@@ -467,7 +467,8 @@ static int regcache_rbtree_write(struct regmap *map, unsigned int reg,
if (!rbnode)
return -ENOMEM;
regcache_rbtree_set_register(map, rbnode,
- reg - rbnode->base_reg, value);
+ (reg - rbnode->base_reg) / map->reg_stride,
+ value);
regcache_rbtree_insert(map, &rbtree_ctx->root, rbnode);
rbtree_ctx->cached_rbnode = rbnode;
}
diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index 540c879abe52c5ba5ce3efcf6ec229a220c540ea..5e03735374ae23fe1f77fb0214c18ac69870194f 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -1343,7 +1343,7 @@ static int dev_get_regmap_match(struct device *dev, void *res, void *data)
/* If the user didn't specify a name match any */
if (data)
- return !strcmp((*r)->name, data);
+ return (*r)->name && !strcmp((*r)->name, data);
else
return 1;
}
diff --git a/drivers/base/soc.c b/drivers/base/soc.c
index 4ae8cc77fb5efefc5a3ba0c3aaeffe3e3e2f9311..61638acf6695f4338851eb60f155bc983881dbd3 100644
--- a/drivers/base/soc.c
+++ b/drivers/base/soc.c
@@ -73,13 +73,13 @@ static ssize_t soc_info_get(struct device *dev,
struct soc_device *soc_dev = container_of(dev, struct soc_device, dev);
if (attr == &dev_attr_machine)
- return sysfs_emit(buf, "%s\n", soc_dev->attr->machine);
+ return sprintf(buf, "%s\n", soc_dev->attr->machine);
if (attr == &dev_attr_family)
- return sysfs_emit(buf, "%s\n", soc_dev->attr->family);
+ return sprintf(buf, "%s\n", soc_dev->attr->family);
if (attr == &dev_attr_revision)
- return sysfs_emit(buf, "%s\n", soc_dev->attr->revision);
+ return sprintf(buf, "%s\n", soc_dev->attr->revision);
if (attr == &dev_attr_soc_id)
- return sysfs_emit(buf, "%s\n", soc_dev->attr->soc_id);
+ return sprintf(buf, "%s\n", soc_dev->attr->soc_id);
return -EINVAL;
diff --git a/drivers/bluetooth/btfm_slim_slave.c b/drivers/bluetooth/btfm_slim_slave.c
index f02e31950093de54961bedee34d09769204b4482..25f2774b65b73300959799c845dee0e004821bf3 100644
--- a/drivers/bluetooth/btfm_slim_slave.c
+++ b/drivers/bluetooth/btfm_slim_slave.c
@@ -81,14 +81,12 @@ int btfm_slim_slave_enable_port(struct btfmslim *btfmslim, uint8_t port_num,
uint8_t reg_val = 0, en;
uint8_t rxport_num = 0;
uint16_t reg;
+ uint8_t prev_reg_val = 0;
BTFMSLIM_DBG("port(%d) enable(%d)", port_num, enable);
if (rxport) {
BTFMSLIM_DBG("sample rate is %d", btfmslim->sample_rate);
- if (enable &&
- btfmslim->sample_rate != 44100 &&
- btfmslim->sample_rate != 88200) {
- BTFMSLIM_DBG("setting multichannel bit");
+ if (enable) {
/* For SCO Rx, A2DP Rx other than 44.1 and 88.2Khz */
if (port_num < 24) {
rxport_num = port_num - 16;
@@ -102,6 +100,21 @@ int btfm_slim_slave_enable_port(struct btfmslim *btfmslim, uint8_t port_num,
rxport_num);
}
+ if (btfmslim->sample_rate == 44100 ||
+ btfmslim->sample_rate == 88200) {
+ BTFMSLIM_DBG("unsetting multichannel bit");
+ ret = btfm_slim_read(btfmslim, reg, 1,
+ &prev_reg_val, IFD);
+ if (ret < 0) {
+ BTFMSLIM_ERR("error %d reading", ret);
+ prev_reg_val = 0;
+ }
+ BTFMSLIM_DBG("prev_reg_val (%d) from reg(%x)",
+ prev_reg_val, reg);
+ reg_val = prev_reg_val & ~reg_val;
+ } else
+ BTFMSLIM_DBG("setting multichannel bit");
+
BTFMSLIM_DBG("writing reg_val (%d) to reg(%x)",
reg_val, reg);
ret = btfm_slim_write(btfmslim, reg, 1, ®_val, IFD);
diff --git a/drivers/bluetooth/hci_vhci.c b/drivers/bluetooth/hci_vhci.c
index 22f9145a426fdd962a17ea9816be43c86a922b8d..29d8b5896d6e424239ddf50a54944271dcb60b2e 100644
--- a/drivers/bluetooth/hci_vhci.c
+++ b/drivers/bluetooth/hci_vhci.c
@@ -82,7 +82,10 @@ static int vhci_send_frame(struct hci_dev *hdev, struct sk_buff *skb)
struct vhci_data *data = hci_get_drvdata(hdev);
memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1);
+
+ mutex_lock(&data->open_mutex);
skb_queue_tail(&data->readq, skb);
+ mutex_unlock(&data->open_mutex);
wake_up_interruptible(&data->read_wait);
return 0;
diff --git a/drivers/bus/mhi/devices/mhi_satellite.c b/drivers/bus/mhi/devices/mhi_satellite.c
index 24621475a26867ea68a6e04c369740a050bbae94..2f226093157faa99d570ed96dc27f001a05a9521 100644
--- a/drivers/bus/mhi/devices/mhi_satellite.c
+++ b/drivers/bus/mhi/devices/mhi_satellite.c
@@ -358,7 +358,7 @@ static struct mhi_sat_device *find_sat_dev_by_id(
static bool mhi_sat_isvalid_header(struct sat_header *hdr, int len)
{
/* validate payload size */
- if (len >= sizeof(*hdr) && (len != hdr->payload_size + sizeof(*hdr)))
+ if (len < sizeof(*hdr) || len != hdr->payload_size + sizeof(*hdr))
return false;
/* validate SAT IPC version */
diff --git a/drivers/char/agp/parisc-agp.c b/drivers/char/agp/parisc-agp.c
index 1d5510cb6db4e7fe0cad57946d2485c401944d1c..1962ff624b7c5ec6dc62827c25c4a91498f32845 100644
--- a/drivers/char/agp/parisc-agp.c
+++ b/drivers/char/agp/parisc-agp.c
@@ -385,8 +385,6 @@ find_quicksilver(struct device *dev, void *data)
static int __init
parisc_agp_init(void)
{
- extern struct sba_device *sba_list;
-
int err = -1;
struct parisc_device *sba = NULL, *lba = NULL;
struct lba_device *lbadev = NULL;
diff --git a/drivers/clk/tegra/clk-bpmp.c b/drivers/clk/tegra/clk-bpmp.c
index 5847241022074b4eec2d35fac920169ffff7a840..f1b9721a035842c5b21255654592b747f3857ba8 100644
--- a/drivers/clk/tegra/clk-bpmp.c
+++ b/drivers/clk/tegra/clk-bpmp.c
@@ -162,7 +162,7 @@ static unsigned long tegra_bpmp_clk_recalc_rate(struct clk_hw *hw,
err = tegra_bpmp_clk_transfer(clk->bpmp, &msg);
if (err < 0)
- return err;
+ return 0;
return response.rate;
}
diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c
index 219704cd87ebf1b36f133fa67dd91cbcf8856e62..3b71fe130337865649796dd03f1245f4dc332174 100644
--- a/drivers/cpuidle/cpuidle.c
+++ b/drivers/cpuidle/cpuidle.c
@@ -142,13 +142,14 @@ static void enter_s2idle_proper(struct cpuidle_driver *drv,
* executing it contains RCU usage regarded as invalid in the idle
* context, so tell RCU about that.
*/
- RCU_NONIDLE(tick_freeze());
+ tick_freeze();
/*
* The state used here cannot be a "coupled" one, because the "coupled"
* cpuidle mechanism enables interrupts and doing that with timekeeping
* suspended is generally unsafe.
*/
stop_critical_timings();
+ rcu_idle_enter();
drv->states[index].enter_s2idle(dev, drv, index);
if (WARN_ON_ONCE(!irqs_disabled()))
local_irq_disable();
@@ -157,7 +158,8 @@ static void enter_s2idle_proper(struct cpuidle_driver *drv,
* first CPU executing it calls functions containing RCU read-side
* critical sections, so tell RCU about that.
*/
- RCU_NONIDLE(tick_unfreeze());
+ rcu_idle_exit();
+ tick_unfreeze();
start_critical_timings();
time_end = ns_to_ktime(local_clock());
@@ -226,16 +228,18 @@ int cpuidle_enter_state(struct cpuidle_device *dev, struct cpuidle_driver *drv,
/* Take note of the planned idle state. */
sched_idle_set_state(target_state, index);
- trace_cpu_idle_rcuidle(index, dev->cpu);
+ trace_cpu_idle(index, dev->cpu);
time_start = ns_to_ktime(local_clock());
stop_critical_timings();
+ rcu_idle_enter();
entered_state = target_state->enter(dev, drv, index);
+ rcu_idle_exit();
start_critical_timings();
sched_clock_idle_wakeup_event();
time_end = ns_to_ktime(local_clock());
- trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, dev->cpu);
+ trace_cpu_idle(PWR_EVENT_EXIT, dev->cpu);
/* The cpu is no longer idle or about to enter idle. */
sched_idle_set_state(NULL, -1);
diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c
index 3259c450544ca0111ed02e4d072ecf7ec5321ef2..ad9be6ed47a30ed888b02e2a29392e68013343c7 100644
--- a/drivers/dma/stm32-mdma.c
+++ b/drivers/dma/stm32-mdma.c
@@ -1217,6 +1217,10 @@ static int stm32_mdma_resume(struct dma_chan *c)
unsigned long flags;
u32 status, reg;
+ /* Transfer can be terminated */
+ if (!chan->desc || (stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & STM32_MDMA_CCR_EN))
+ return -EPERM;
+
hwdesc = chan->desc->node[chan->curr_hwdesc].hwdesc;
spin_lock_irqsave(&chan->vchan.lock, flags);
diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
index e627e0e9001ae2e0dd5ccecec849e900038c046a..ba1cd971d50b68911a4d03c764892d8b2bc7405d 100644
--- a/drivers/gpio/gpio-aspeed.c
+++ b/drivers/gpio/gpio-aspeed.c
@@ -999,7 +999,7 @@ static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
else if (param == PIN_CONFIG_BIAS_DISABLE ||
param == PIN_CONFIG_BIAS_PULL_DOWN ||
param == PIN_CONFIG_DRIVE_STRENGTH)
- return pinctrl_gpio_set_config(offset, config);
+ return pinctrl_gpio_set_config(chip->base + offset, config);
else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN ||
param == PIN_CONFIG_DRIVE_OPEN_SOURCE)
/* Return -ENOTSUPP to trigger emulation, as per datasheet */
diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c
index 29e044ff4b17d0c607a6fbe1388aac18d527b5a6..7697cb96bf36f3e1073249ed08731e2dafbd9f04 100644
--- a/drivers/gpio/gpio-pmic-eic-sprd.c
+++ b/drivers/gpio/gpio-pmic-eic-sprd.c
@@ -341,6 +341,7 @@ static int sprd_pmic_eic_probe(struct platform_device *pdev)
pmic_eic->chip.set_config = sprd_pmic_eic_set_config;
pmic_eic->chip.set = sprd_pmic_eic_set;
pmic_eic->chip.get = sprd_pmic_eic_get;
+ pmic_eic->chip.can_sleep = true;
pmic_eic->intc.name = dev_name(&pdev->dev);
pmic_eic->intc.irq_mask = sprd_pmic_eic_irq_mask;
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index bcc6be4a5cb2ed38c000c6e15a99e91692c81c2c..61df316e0d17a42c7679273c4b1cfe4e85374d05 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -246,6 +246,7 @@ static bool pxa_gpio_has_pinctrl(void)
switch (gpio_type) {
case PXA3XX_GPIO:
case MMP2_GPIO:
+ case MMP_GPIO:
return false;
default:
diff --git a/drivers/gpio/gpio-tb10x.c b/drivers/gpio/gpio-tb10x.c
index a12cd0b5c9721d487583c09b58fddebeaa8ab136..1d80bae86ec96c6c79f7f39087c05022136cea86 100644
--- a/drivers/gpio/gpio-tb10x.c
+++ b/drivers/gpio/gpio-tb10x.c
@@ -246,7 +246,7 @@ static int tb10x_gpio_probe(struct platform_device *pdev)
handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
IRQ_GC_INIT_MASK_CACHE);
if (ret)
- return ret;
+ goto err_remove_domain;
gc = tb10x_gpio->domain->gc->gc[0];
gc->reg_base = tb10x_gpio->base;
@@ -260,6 +260,10 @@ static int tb10x_gpio_probe(struct platform_device *pdev)
}
return 0;
+
+err_remove_domain:
+ irq_domain_remove(tb10x_gpio->domain);
+ return ret;
}
static int tb10x_gpio_remove(struct platform_device *pdev)
diff --git a/drivers/gpio/gpio-timberdale.c b/drivers/gpio/gpio-timberdale.c
index 314e300d6ba33ac0724eb41510caa08a697aff1d..1e6925c27ae2911e790763e1d59028e968e54faa 100644
--- a/drivers/gpio/gpio-timberdale.c
+++ b/drivers/gpio/gpio-timberdale.c
@@ -55,9 +55,10 @@ static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
unsigned offset, bool enabled)
{
struct timbgpio *tgpio = gpiochip_get_data(gpio);
+ unsigned long flags;
u32 reg;
- spin_lock(&tgpio->lock);
+ spin_lock_irqsave(&tgpio->lock, flags);
reg = ioread32(tgpio->membase + offset);
if (enabled)
@@ -66,7 +67,7 @@ static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
reg &= ~(1 << index);
iowrite32(reg, tgpio->membase + offset);
- spin_unlock(&tgpio->lock);
+ spin_unlock_irqrestore(&tgpio->lock, flags);
return 0;
}
diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
index 01865b3e0a5f5a03edfa218412bfc2910d7b4472..df400d14ed17a114bc17885730e8ec0bd08a101d 100644
--- a/drivers/gpio/gpio-vf610.c
+++ b/drivers/gpio/gpio-vf610.c
@@ -137,14 +137,14 @@ static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
unsigned long mask = BIT(gpio);
u32 val;
+ vf610_gpio_set(chip, gpio, value);
+
if (port->sdata && port->sdata->have_paddr) {
val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
val |= mask;
vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
}
- vf610_gpio_set(chip, gpio, value);
-
return pinctrl_gpio_direction_output(chip->base + gpio);
}
diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c
index 7a2a148b8ec628351ebef75c140e872546cc59f0..597db0acef95a8110bf2ed0ae5b1ae66fdf9b620 100644
--- a/drivers/gpu/drm/drm_panel_orientation_quirks.c
+++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c
@@ -44,6 +44,14 @@ static const struct drm_dmi_panel_orientation_data gpd_micropc = {
.orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
};
+static const struct drm_dmi_panel_orientation_data gpd_onemix2s = {
+ .width = 1200,
+ .height = 1920,
+ .bios_dates = (const char * const []){ "05/21/2018", "10/26/2018",
+ "03/04/2019", NULL },
+ .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP,
+};
+
static const struct drm_dmi_panel_orientation_data gpd_pocket = {
.width = 1200,
.height = 1920,
@@ -219,6 +227,14 @@ static const struct dmi_system_id orientation_data[] = {
DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "LTH17"),
},
.driver_data = (void *)&lcd800x1280_rightside_up,
+ }, { /* One Mix 2S (generic strings, also match on bios date) */
+ .matches = {
+ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Default string"),
+ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Default string"),
+ DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Default string"),
+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"),
+ },
+ .driver_data = (void *)&gpd_onemix2s,
},
{}
};
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c
index a9506a390f98d88666bc6cf773284fdcc513a93c..3f9ff6bc7644288a82a88b3f68db82c3db0fe6c1 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c
@@ -96,7 +96,7 @@ static int etnaviv_gem_prime_mmap_obj(struct etnaviv_gem_object *etnaviv_obj,
ret = dma_buf_mmap(etnaviv_obj->base.dma_buf, vma, 0);
if (!ret) {
/* Drop the reference acquired by drm_gem_mmap_obj(). */
- drm_gem_object_put(&etnaviv_obj->base);
+ drm_gem_object_put_unlocked(&etnaviv_obj->base);
}
return ret;
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 059578faa1c6dabd6801ed49d71b06956185ee18..5f4dd3659bf967ad5e333551c41a71aa96319093 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1059,9 +1059,21 @@ static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
{
+ u32 data;
+
if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
return;
+ data = dsi_read(msm_host, REG_DSI_STATUS0);
+
+ /* if video mode engine is not busy, its because
+ * either timing engine was not turned on or the
+ * DSI controller has finished transmitting the video
+ * data already, so no need to wait in those cases
+ */
+ if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY))
+ return;
+
if (msm_host->power_on && msm_host->enabled) {
dsi_wait4video_done(msm_host);
/* delay 4 ms to skip BLLP */
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index e65554f5a89d509b9c722adf398d2b4e25d44d35..2480afa466f2b17fff11c84918d651659ebfe7f2 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -1834,7 +1834,7 @@ static int vmw_cmd_tex_state(struct vmw_private *dev_priv,
} *cmd;
SVGA3dTextureState *last_state = (SVGA3dTextureState *)
- ((unsigned long) header + header->size + sizeof(header));
+ ((unsigned long) header + header->size + sizeof(*header));
SVGA3dTextureState *cur_state = (SVGA3dTextureState *)
((unsigned long) header + sizeof(struct vmw_tex_state_cmd));
struct vmw_resource_val_node *ctx_node;
diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c
index f3c37d7a0670013ec13e9c421a453725f1171fc1..12424453806059edcbf31836af4e5eb76e936403 100644
--- a/drivers/gpu/msm/kgsl.c
+++ b/drivers/gpu/msm/kgsl.c
@@ -2129,6 +2129,10 @@ long kgsl_ioctl_gpu_aux_command(struct kgsl_device_private *dev_priv,
if (!(param->flags & KGSL_GPU_AUX_COMMAND_TIMELINE))
return -EINVAL;
+ if ((param->flags & KGSL_GPU_AUX_COMMAND_SYNC) &&
+ (param->numsyncs > KGSL_MAX_SYNCPOINTS))
+ return -EINVAL;
+
context = kgsl_context_get_owner(dev_priv, param->context_id);
if (!context)
return -EINVAL;
diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c
index e4b9924baec205838223078a4537da3d4bfcbf23..c54f6edaf6fc008d4756c244bc8d69438390b4c3 100644
--- a/drivers/gpu/msm/kgsl_iommu.c
+++ b/drivers/gpu/msm/kgsl_iommu.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2011-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include
@@ -2428,14 +2428,18 @@ static uint64_t kgsl_iommu_find_svm_region(struct kgsl_pagetable *pagetable,
static bool iommu_addr_in_svm_ranges(struct kgsl_iommu_pt *pt,
u64 gpuaddr, u64 size)
{
+ u64 end = gpuaddr + size;
+
+ /* Make sure size is not zero and we don't wrap around */
+ if (end <= gpuaddr)
+ return false;
+
if ((gpuaddr >= pt->compat_va_start && gpuaddr < pt->compat_va_end) &&
- ((gpuaddr + size) > pt->compat_va_start &&
- (gpuaddr + size) <= pt->compat_va_end))
+ (end > pt->compat_va_start && end <= pt->compat_va_end))
return true;
if ((gpuaddr >= pt->svm_start && gpuaddr < pt->svm_end) &&
- ((gpuaddr + size) > pt->svm_start &&
- (gpuaddr + size) <= pt->svm_end))
+ (end > pt->svm_start && end <= pt->svm_end))
return true;
return false;
diff --git a/drivers/hid/hid-holtek-kbd.c b/drivers/hid/hid-holtek-kbd.c
index 2f8eb663974445f88d18e56e3d07a61b9a5385bb..72788ca260e08643a2f7ace47820da3faded4ff2 100644
--- a/drivers/hid/hid-holtek-kbd.c
+++ b/drivers/hid/hid-holtek-kbd.c
@@ -133,6 +133,10 @@ static int holtek_kbd_input_event(struct input_dev *dev, unsigned int type,
return -ENODEV;
boot_hid = usb_get_intfdata(boot_interface);
+ if (list_empty(&boot_hid->inputs)) {
+ hid_err(hid, "no inputs found\n");
+ return -ENODEV;
+ }
boot_hid_input = list_first_entry(&boot_hid->inputs,
struct hid_input, list);
diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c
index 5b6bb24df63e0cbf6e45436c859a98b1a9cff382..f2982784c4fea619b670f905e0144719978d32ec 100644
--- a/drivers/hid/hid-logitech-hidpp.c
+++ b/drivers/hid/hid-logitech-hidpp.c
@@ -3129,7 +3129,8 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id)
/* Allow incoming packets */
hid_device_io_start(hdev);
- hidpp_connect_event(hidpp);
+ schedule_work(&hidpp->work);
+ flush_work(&hidpp->work);
return ret;
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index fb0ddaad87d2e8854f14af0c24f6fad98fc2bcb5..6017f6aeee89f44aff644f4dd6c5bafb4c14c4ab 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -1679,6 +1679,7 @@ static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
"SMBus I801 adapter at %04lx", priv->smba);
err = i2c_add_adapter(&priv->adapter);
if (err) {
+ platform_device_unregister(priv->tco_pdev);
i801_acpi_remove(priv);
return err;
}
diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c
index f330690b41253ff75e352b321575cc008fcf0353..83a79bcb71ea5aa60e2fc845f7eedff19050072d 100644
--- a/drivers/i2c/i2c-mux.c
+++ b/drivers/i2c/i2c-mux.c
@@ -334,7 +334,7 @@ int i2c_mux_add_adapter(struct i2c_mux_core *muxc,
priv->adap.lock_ops = &i2c_parent_lock_ops;
/* Sanity check on class */
- if (i2c_mux_parent_classes(parent) & class)
+ if (i2c_mux_parent_classes(parent) & class & ~I2C_CLASS_DEPRECATED)
dev_err(&parent->dev,
"Segment %d behind mux can't share classes with ancestors\n",
chan_id);
diff --git a/drivers/i2c/muxes/i2c-demux-pinctrl.c b/drivers/i2c/muxes/i2c-demux-pinctrl.c
index 1b99d0b928a0dcca16eeb7243694e0633d30f2d4..092ebc08549ffb5389e6f663bbf03417bd4ecd7c 100644
--- a/drivers/i2c/muxes/i2c-demux-pinctrl.c
+++ b/drivers/i2c/muxes/i2c-demux-pinctrl.c
@@ -244,6 +244,10 @@ static int i2c_demux_pinctrl_probe(struct platform_device *pdev)
props[i].name = devm_kstrdup(&pdev->dev, "status", GFP_KERNEL);
props[i].value = devm_kstrdup(&pdev->dev, "ok", GFP_KERNEL);
+ if (!props[i].name || !props[i].value) {
+ err = -ENOMEM;
+ goto err_rollback;
+ }
props[i].length = 3;
of_changeset_init(&priv->chan[i].chgset);
diff --git a/drivers/iio/pressure/bmp280-core.c b/drivers/iio/pressure/bmp280-core.c
index 074f6f865008c5c096b7f3d8419f03e2098643ce..5efc50d93d1c5158a118560dc41bbf13887d1861 100644
--- a/drivers/iio/pressure/bmp280-core.c
+++ b/drivers/iio/pressure/bmp280-core.c
@@ -1110,7 +1110,7 @@ int bmp280_common_probe(struct device *dev,
* however as it happens, the BMP085 shares the chip ID of BMP180
* so we look for an IRQ if we have that.
*/
- if (irq > 0 || (chip_id == BMP180_CHIP_ID)) {
+ if (irq > 0 && (chip_id == BMP180_CHIP_ID)) {
ret = bmp085_fetch_eoc_irq(dev, name, irq, data);
if (ret)
goto out_disable_vdda;
diff --git a/drivers/iio/pressure/ms5611_core.c b/drivers/iio/pressure/ms5611_core.c
index 5c7a734ede54c4f9fc37e3873855fe3301cf3499..9980c6f3335e2db6cfda50ce5cd3d49ff498364b 100644
--- a/drivers/iio/pressure/ms5611_core.c
+++ b/drivers/iio/pressure/ms5611_core.c
@@ -79,7 +79,7 @@ static bool ms5611_prom_is_valid(u16 *prom, size_t len)
crc = (crc >> 12) & 0x000F;
- return crc_orig != 0x0000 && crc == crc_orig;
+ return crc == crc_orig;
}
static int ms5611_read_prom(struct iio_dev *indio_dev)
diff --git a/drivers/infiniband/core/cma_configfs.c b/drivers/infiniband/core/cma_configfs.c
index ce183d054785269fa41dcda6e071702e3073749d..f9b0303b3a01b6227a6757b413b94f7e7e236808 100644
--- a/drivers/infiniband/core/cma_configfs.c
+++ b/drivers/infiniband/core/cma_configfs.c
@@ -215,7 +215,7 @@ static int make_cma_ports(struct cma_dev_group *cma_dev_group,
}
for (i = 0; i < ports_num; i++) {
- char port_str[10];
+ char port_str[11];
ports[i].port_num = i + 1;
snprintf(port_str, sizeof(port_str), "%u", i + 1);
diff --git a/drivers/infiniband/hw/cxgb4/cm.c b/drivers/infiniband/hw/cxgb4/cm.c
index a252b13958b3b576e1b831d9ae4ab14229bf45d5..e8d2135df22db5bae18d94973acfd5f2f676d4f3 100644
--- a/drivers/infiniband/hw/cxgb4/cm.c
+++ b/drivers/infiniband/hw/cxgb4/cm.c
@@ -1922,6 +1922,9 @@ static int send_fw_act_open_req(struct c4iw_ep *ep, unsigned int atid)
int win;
skb = get_skb(NULL, sizeof(*req), GFP_KERNEL);
+ if (!skb)
+ return -ENOMEM;
+
req = __skb_put_zero(skb, sizeof(*req));
req->op_compl = htonl(WR_OP_V(FW_OFLD_CONNECTION_WR));
req->len16_pkd = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*req), 16)));
diff --git a/drivers/infiniband/hw/mlx4/sysfs.c b/drivers/infiniband/hw/mlx4/sysfs.c
index d2da28d613f2cc41397de8f2a9d7af99510aaa54..eb95292d12dcb7644e4a489e9e46e276c3f75659 100644
--- a/drivers/infiniband/hw/mlx4/sysfs.c
+++ b/drivers/infiniband/hw/mlx4/sysfs.c
@@ -221,7 +221,7 @@ void del_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num,
static int add_port_entries(struct mlx4_ib_dev *device, int port_num)
{
int i;
- char buff[11];
+ char buff[12];
struct mlx4_ib_iov_port *port = NULL;
int ret = 0 ;
struct ib_port_attr attr;
diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c
index 1688c06d5c3c79410fc7230f246a675aa8971dfa..f7df27c7c634493f8dd9fe919a93136d346854d3 100644
--- a/drivers/infiniband/hw/mlx5/main.c
+++ b/drivers/infiniband/hw/mlx5/main.c
@@ -2005,7 +2005,7 @@ static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
case MLX5_IB_MMAP_DEVICE_MEM:
return "Device Memory";
default:
- return NULL;
+ return "Unknown";
}
}
diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c
index 1537ce6272386c14c806aecfe200fc1d1e66c5de..4591f60dd6e2dda25e66d9c9953ac31dde68dae9 100644
--- a/drivers/input/joystick/xpad.c
+++ b/drivers/input/joystick/xpad.c
@@ -266,6 +266,7 @@ static const struct xpad_device {
{ 0x1038, 0x1430, "SteelSeries Stratus Duo", 0, XTYPE_XBOX360 },
{ 0x1038, 0x1431, "SteelSeries Stratus Duo", 0, XTYPE_XBOX360 },
{ 0x11c9, 0x55f0, "Nacon GC-100XF", 0, XTYPE_XBOX360 },
+ { 0x11ff, 0x0511, "PXN V900", 0, XTYPE_XBOX360 },
{ 0x1209, 0x2882, "Ardwiino Controller", 0, XTYPE_XBOX360 },
{ 0x12ab, 0x0004, "Honey Bee Xbox360 dancepad", MAP_DPAD_TO_BUTTONS, XTYPE_XBOX360 },
{ 0x12ab, 0x0301, "PDP AFTERGLOW AX.1", 0, XTYPE_XBOX360 },
@@ -460,6 +461,7 @@ static const struct usb_device_id xpad_table[] = {
XPAD_XBOXONE_VENDOR(0x0f0d), /* Hori Controllers */
XPAD_XBOX360_VENDOR(0x1038), /* SteelSeries Controllers */
XPAD_XBOX360_VENDOR(0x11c9), /* Nacon GC100XF */
+ XPAD_XBOX360_VENDOR(0x11ff), /* PXN V900 */
XPAD_XBOX360_VENDOR(0x1209), /* Ardwiino Controllers */
XPAD_XBOX360_VENDOR(0x12ab), /* X-Box 360 dance pads */
XPAD_XBOX360_VENDOR(0x1430), /* RedOctane X-Box 360 controllers */
diff --git a/drivers/input/misc/powermate.c b/drivers/input/misc/powermate.c
index e8de3aaf9f6330a276c99387fab80573a5bf6dd6..14f48e10f589e81b8d5f38314cb0d6f6708589bb 100644
--- a/drivers/input/misc/powermate.c
+++ b/drivers/input/misc/powermate.c
@@ -424,6 +424,7 @@ static void powermate_disconnect(struct usb_interface *intf)
pm->requires_update = 0;
usb_kill_urb(pm->irq);
input_unregister_device(pm->input);
+ usb_kill_urb(pm->config);
usb_free_urb(pm->irq);
usb_free_urb(pm->config);
powermate_free_buffers(interface_to_usbdev(intf), pm);
diff --git a/drivers/input/mouse/elantech.c b/drivers/input/mouse/elantech.c
index e78db2dd0348ca85bef840024ba96c066e7028d4..6759cab82a7239ecd737e8059540b62156bbbfc0 100644
--- a/drivers/input/mouse/elantech.c
+++ b/drivers/input/mouse/elantech.c
@@ -1996,6 +1996,7 @@ static int elantech_setup_ps2(struct psmouse *psmouse,
psmouse->protocol_handler = elantech_process_byte;
psmouse->disconnect = elantech_disconnect;
psmouse->reconnect = elantech_reconnect;
+ psmouse->fast_reconnect = NULL;
psmouse->pktsize = info->hw_version > 1 ? 6 : 4;
return 0;
diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c
index c6d393114502d45c545ac3db019813eeca786f30..794a7f17d024cbad10f959735fcd74447af214e9 100644
--- a/drivers/input/mouse/synaptics.c
+++ b/drivers/input/mouse/synaptics.c
@@ -1620,6 +1620,7 @@ static int synaptics_init_ps2(struct psmouse *psmouse,
psmouse->set_rate = synaptics_set_rate;
psmouse->disconnect = synaptics_disconnect;
psmouse->reconnect = synaptics_reconnect;
+ psmouse->fast_reconnect = NULL;
psmouse->cleanup = synaptics_reset;
/* Synaptics can usually stay in sync without extra help */
psmouse->resync_time = 0;
diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h
index da2bf8259330e236637d881fb5a938e79731f806..0cf9a37873261f09e5d05f87a1c7a984b1a49d04 100644
--- a/drivers/input/serio/i8042-x86ia64io.h
+++ b/drivers/input/serio/i8042-x86ia64io.h
@@ -1188,6 +1188,13 @@ static const struct dmi_system_id i8042_dmi_quirk_table[] __initconst = {
.driver_data = (void *)(SERIO_QUIRK_NOMUX | SERIO_QUIRK_RESET_ALWAYS |
SERIO_QUIRK_NOLOOP | SERIO_QUIRK_NOPNP)
},
+ /* See comment on TUXEDO InfinityBook S17 Gen6 / Clevo NS70MU above */
+ {
+ .matches = {
+ DMI_MATCH(DMI_BOARD_NAME, "PD5x_7xPNP_PNR_PNN_PNT"),
+ },
+ .driver_data = (void *)(SERIO_QUIRK_NOAUX)
+ },
{
.matches = {
DMI_MATCH(DMI_BOARD_NAME, "X170SM"),
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index a6fad3ab73156c56a725c06f74ed13b40dc59bb1..5b69ba8a9a8f88d6a092bb057bd23a001b541405 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -670,9 +670,11 @@ static int arm_lpae_map_sg(struct io_pgtable_ops *ops, unsigned long iova,
arm_lpae_iopte *ptep = ms.pgtable +
ARM_LPAE_LVL_IDX(iova, MAP_STATE_LVL,
data);
- arm_lpae_init_pte(
+ ret = arm_lpae_init_pte(
data, iova, phys, prot, MAP_STATE_LVL,
ptep, ms.prev_pgtable, false);
+ if (ret)
+ goto out_err;
ms.num_pte++;
} else {
ret = __arm_lpae_map(data, iova, phys, pgsize,
diff --git a/drivers/mcb/mcb-core.c b/drivers/mcb/mcb-core.c
index 7fd32b0183dc106e556d927ffed5d8addbfc99d0..6e7e91387f3c468a60c7fb066ffcdabd8c2d7f2c 100644
--- a/drivers/mcb/mcb-core.c
+++ b/drivers/mcb/mcb-core.c
@@ -392,17 +392,13 @@ EXPORT_SYMBOL_GPL(mcb_free_dev);
static int __mcb_bus_add_devices(struct device *dev, void *data)
{
- struct mcb_device *mdev = to_mcb_device(dev);
int retval;
- if (mdev->is_added)
- return 0;
-
retval = device_attach(dev);
- if (retval < 0)
+ if (retval < 0) {
dev_err(dev, "Error adding device (%d)\n", retval);
-
- mdev->is_added = true;
+ return retval;
+ }
return 0;
}
diff --git a/drivers/mcb/mcb-parse.c b/drivers/mcb/mcb-parse.c
index 3636349648b4f0e15cfbec120575c9428472ca3f..08a85e43ef88507dda8279b60c033d6f67892c98 100644
--- a/drivers/mcb/mcb-parse.c
+++ b/drivers/mcb/mcb-parse.c
@@ -98,8 +98,6 @@ static int chameleon_parse_gdd(struct mcb_bus *bus,
mdev->mem.end = mdev->mem.start + size - 1;
mdev->mem.flags = IORESOURCE_MEM;
- mdev->is_added = false;
-
ret = mcb_device_register(bus, mdev);
if (ret < 0)
goto err;
diff --git a/drivers/media/dvb-frontends/sp8870.c b/drivers/media/dvb-frontends/sp8870.c
index 3a577788041d5091ad29e39532c602838ba0f1c5..c55bcd809458c8ab918eff31ee816b1f6739a9a4 100644
--- a/drivers/media/dvb-frontends/sp8870.c
+++ b/drivers/media/dvb-frontends/sp8870.c
@@ -619,4 +619,4 @@ MODULE_DESCRIPTION("Spase SP8870 DVB-T Demodulator driver");
MODULE_AUTHOR("Juergen Peitz");
MODULE_LICENSE("GPL");
-EXPORT_SYMBOL(sp8870_attach);
+EXPORT_SYMBOL_GPL(sp8870_attach);
diff --git a/drivers/media/tuners/tuner-xc2028.c b/drivers/media/tuners/tuner-xc2028.c
index aa6861dcd3fd78fd0df75c358b1149564564371a..802a4d77f26bf8410832c5bf384597829e6b9ca4 100644
--- a/drivers/media/tuners/tuner-xc2028.c
+++ b/drivers/media/tuners/tuner-xc2028.c
@@ -1513,7 +1513,7 @@ struct dvb_frontend *xc2028_attach(struct dvb_frontend *fe,
return NULL;
}
-EXPORT_SYMBOL(xc2028_attach);
+EXPORT_SYMBOL_GPL(xc2028_attach);
MODULE_DESCRIPTION("Xceive xc2028/xc3028 tuner driver");
MODULE_AUTHOR("Michel Ludwig ");
diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c
index 0c5dfee9b71a369bcbff4e00cb6796ef78a81aff..d7e8e349862c21c28a0316f8061511e3975ee963 100644
--- a/drivers/misc/qseecom.c
+++ b/drivers/misc/qseecom.c
@@ -3,7 +3,7 @@
* QTI Secure Execution Environment Communicator (QSEECOM) driver
*
* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#define pr_fmt(fmt) "QSEECOM: %s: " fmt, __func__
@@ -375,7 +375,7 @@ struct qseecom_client_handle {
struct qseecom_listener_handle {
u32 id;
- bool unregister_pending;
+ bool register_pending;
bool release_called;
};
@@ -1525,6 +1525,11 @@ static int qseecom_register_listener(struct qseecom_dev_handle *data,
struct qseecom_registered_listener_list *new_entry;
struct qseecom_registered_listener_list *ptr_svc;
+ if (data->listener.register_pending) {
+ pr_err("Already a listner registration is in process on this FD\n");
+ return -EINVAL;
+ }
+
ret = copy_from_user(&rcvd_lstnr, argp, sizeof(rcvd_lstnr));
if (ret) {
pr_err("copy_from_user failed\n");
@@ -1534,6 +1539,13 @@ static int qseecom_register_listener(struct qseecom_dev_handle *data,
rcvd_lstnr.sb_size))
return -EFAULT;
+ ptr_svc = __qseecom_find_svc(data->listener.id);
+ if (ptr_svc) {
+ pr_err("Already a listener registered on this data: lid=%d\n",
+ data->listener.id);
+ return -EINVAL;
+ }
+
ptr_svc = __qseecom_find_svc(rcvd_lstnr.listener_id);
if (ptr_svc) {
if (!ptr_svc->unregister_pending) {
@@ -1577,13 +1589,16 @@ static int qseecom_register_listener(struct qseecom_dev_handle *data,
new_entry->svc.listener_id = rcvd_lstnr.listener_id;
new_entry->sb_length = rcvd_lstnr.sb_size;
new_entry->user_virt_sb_base = rcvd_lstnr.virt_sb_base;
+ data->listener.register_pending = true;
if (__qseecom_set_sb_memory(new_entry, data, &rcvd_lstnr)) {
pr_err("qseecom_set_sb_memory failed for listener %d, size %d\n",
rcvd_lstnr.listener_id, rcvd_lstnr.sb_size);
__qseecom_free_tzbuf(&new_entry->sglistinfo_shm);
kzfree(new_entry);
+ data->listener.register_pending = false;
return -ENOMEM;
}
+ data->listener.register_pending = false;
init_waitqueue_head(&new_entry->rcv_req_wq);
init_waitqueue_head(&new_entry->listener_block_app_wq);
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 5777cf9f47c97ae1ef97fd05d3ba7e72df41faaa..32ffbc3cdc31a64278611ba4da54f354f3e97147 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -100,7 +100,7 @@ static int mmc_decode_cid(struct mmc_card *card)
case 3: /* MMC v3.1 - v3.3 */
case 4: /* MMC v4 */
card->cid.manfid = UNSTUFF_BITS(resp, 120, 8);
- card->cid.oemid = UNSTUFF_BITS(resp, 104, 16);
+ card->cid.oemid = UNSTUFF_BITS(resp, 104, 8);
card->cid.prod_name[0] = UNSTUFF_BITS(resp, 96, 8);
card->cid.prod_name[1] = UNSTUFF_BITS(resp, 88, 8);
card->cid.prod_name[2] = UNSTUFF_BITS(resp, 80, 8);
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index c64b408f080a9ca637e2fcde27b8fa4b10839ff8..783cdc8728cb59bd5871288f2d1e19ed0f4c0e1d 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -2987,7 +2987,7 @@ static int qcom_nandc_probe(struct platform_device *pdev)
err_aon_clk:
clk_disable_unprepare(nandc->core_clk);
err_core_clk:
- dma_unmap_resource(dev, res->start, resource_size(res),
+ dma_unmap_resource(dev, nandc->base_dma, resource_size(res),
DMA_BIDIRECTIONAL, 0);
return ret;
}
diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index 9c4381d6847b34d225514a990ce1ff6cc5a82b39..fabca2c3632169e2b095db3520244941c4205773 100644
--- a/drivers/mtd/nand/spi/micron.c
+++ b/drivers/mtd/nand/spi/micron.c
@@ -12,7 +12,7 @@
#define SPINAND_MFR_MICRON 0x2c
-#define MICRON_STATUS_ECC_MASK GENMASK(7, 4)
+#define MICRON_STATUS_ECC_MASK GENMASK(6, 4)
#define MICRON_STATUS_ECC_NO_BITFLIPS (0 << 4)
#define MICRON_STATUS_ECC_1TO3_BITFLIPS (1 << 4)
#define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4)
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index 3eb14c68cb9b285ec98caf6f2a0dadd8c22792a5..3e7e5b51eafd00abd7f51fbd019b256b094ec262 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -878,6 +878,13 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num,
return -EINVAL;
}
+ /* UBI cannot work on flashes with zero erasesize. */
+ if (!mtd->erasesize) {
+ pr_err("ubi: refuse attaching mtd%d - zero erasesize flash is not supported\n",
+ mtd->index);
+ return -EINVAL;
+ }
+
if (ubi_num == UBI_DEV_NUM_AUTO) {
/* Search for an empty slot in the @ubi_devices array */
for (ubi_num = 0; ubi_num < UBI_MAX_DEVICES; ubi_num++)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index 2c334b56fd42c081cfd0ad8cd757735110dfcab3..d668d25ae7e76dc0d4e605730c7404fb68ff335f 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -2517,8 +2517,13 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
u32 regclr)
{
+#define HCLGE_IMP_RESET_DELAY 5
+
switch (event_type) {
case HCLGE_VECTOR0_EVENT_RST:
+ if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B))
+ mdelay(HCLGE_IMP_RESET_DELAY);
+
hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
break;
case HCLGE_VECTOR0_EVENT_MBX:
diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c
index e75b4c4872c0947e0b0df93eec1d13d51171b24b..95cd3c35b0034430df810a797121b19aab317965 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_common.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c
@@ -1332,7 +1332,7 @@ void i40e_clear_hw(struct i40e_hw *hw)
I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
I40E_PFLAN_QALLOC_LASTQ_SHIFT;
- if (val & I40E_PFLAN_QALLOC_VALID_MASK)
+ if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue)
num_queues = (j - base_queue) + 1;
else
num_queues = 0;
@@ -1342,7 +1342,7 @@ void i40e_clear_hw(struct i40e_hw *hw)
I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
- if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
+ if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i)
num_vfs = (j - i) + 1;
else
num_vfs = 0;
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
index 6055a4917ff6942924d39c3716ae08ead0ef7eed..9b463ef62be5589ff973d75e59c598555699b68e 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
@@ -28,6 +28,9 @@ static inline void ixgbe_alloc_vf_macvlans(struct ixgbe_adapter *adapter,
struct vf_macvlans *mv_list;
int num_vf_macvlans, i;
+ /* Initialize list of VF macvlans */
+ INIT_LIST_HEAD(&adapter->vf_mvs.l);
+
num_vf_macvlans = hw->mac.num_rar_entries -
(IXGBE_MAX_PF_MACVLANS + 1 + num_vfs);
if (!num_vf_macvlans)
@@ -36,8 +39,6 @@ static inline void ixgbe_alloc_vf_macvlans(struct ixgbe_adapter *adapter,
mv_list = kcalloc(num_vf_macvlans, sizeof(struct vf_macvlans),
GFP_KERNEL);
if (mv_list) {
- /* Initialize list of VF macvlans */
- INIT_LIST_HEAD(&adapter->vf_mvs.l);
for (i = 0; i < num_vf_macvlans; i++) {
mv_list[i].vf = -1;
mv_list[i].free = true;
diff --git a/drivers/net/ethernet/marvell/sky2.h b/drivers/net/ethernet/marvell/sky2.h
index b02b6523083ce988f743bac543c595d776fe908e..99451585a45f2d1052bcc5ec43bda76a6d858139 100644
--- a/drivers/net/ethernet/marvell/sky2.h
+++ b/drivers/net/ethernet/marvell/sky2.h
@@ -2201,7 +2201,7 @@ struct rx_ring_info {
struct sk_buff *skb;
dma_addr_t data_addr;
DEFINE_DMA_UNMAP_LEN(data_size);
- dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT];
+ dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT ?: 1];
};
enum flow_control {
diff --git a/drivers/net/ethernet/qlogic/qed/qed_ll2.h b/drivers/net/ethernet/qlogic/qed/qed_ll2.h
index f65817012e9722e5a47458d30a47ef79209075a7..785899d3511cb9df3f0208d96222618bbc5fa797 100644
--- a/drivers/net/ethernet/qlogic/qed/qed_ll2.h
+++ b/drivers/net/ethernet/qlogic/qed/qed_ll2.h
@@ -122,9 +122,9 @@ struct qed_ll2_info {
enum core_tx_dest tx_dest;
u8 tx_stats_en;
bool main_func_queue;
+ struct qed_ll2_cbs cbs;
struct qed_ll2_rx_queue rx_queue;
struct qed_ll2_tx_queue tx_queue;
- struct qed_ll2_cbs cbs;
};
/**
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 7e2e79dedebf2c23ae93fef4dd9cc651701feaf0..df7fc6b675a53e56a742f1ddade8a2ec343b0f32 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -57,6 +57,7 @@ struct stm32_ops {
int (*parse_data)(struct stm32_dwmac *dwmac,
struct device *dev);
u32 syscfg_eth_mask;
+ bool clk_rx_enable_in_suspend;
};
static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat)
@@ -74,7 +75,8 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat)
if (ret)
return ret;
- if (!dwmac->dev->power.is_suspended) {
+ if (!dwmac->ops->clk_rx_enable_in_suspend ||
+ !dwmac->dev->power.is_suspended) {
ret = clk_prepare_enable(dwmac->clk_rx);
if (ret) {
clk_disable_unprepare(dwmac->clk_tx);
@@ -413,7 +415,8 @@ static struct stm32_ops stm32mp1_dwmac_data = {
.suspend = stm32mp1_suspend,
.resume = stm32mp1_resume,
.parse_data = stm32mp1_parse_data,
- .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK
+ .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK,
+ .clk_rx_enable_in_suspend = true
};
static const struct of_device_id stm32_dwmac_match[] = {
diff --git a/drivers/net/ieee802154/ca8210.c b/drivers/net/ieee802154/ca8210.c
index f75faec23cc98013d78a635204d0c6532046c9fe..525f92e896699abdc5a6dfa9967d4adb8096013b 100644
--- a/drivers/net/ieee802154/ca8210.c
+++ b/drivers/net/ieee802154/ca8210.c
@@ -2781,7 +2781,6 @@ static int ca8210_register_ext_clock(struct spi_device *spi)
struct device_node *np = spi->dev.of_node;
struct ca8210_priv *priv = spi_get_drvdata(spi);
struct ca8210_platform_data *pdata = spi->dev.platform_data;
- int ret = 0;
if (!np)
return -EFAULT;
@@ -2798,18 +2797,8 @@ static int ca8210_register_ext_clock(struct spi_device *spi)
dev_crit(&spi->dev, "Failed to register external clk\n");
return PTR_ERR(priv->clk);
}
- ret = of_clk_add_provider(np, of_clk_src_simple_get, priv->clk);
- if (ret) {
- clk_unregister(priv->clk);
- dev_crit(
- &spi->dev,
- "Failed to register external clock as clock provider\n"
- );
- } else {
- dev_info(&spi->dev, "External clock set as clock provider\n");
- }
- return ret;
+ return of_clk_add_provider(np, of_clk_src_simple_get, priv->clk);
}
/**
@@ -2821,8 +2810,8 @@ static void ca8210_unregister_ext_clock(struct spi_device *spi)
{
struct ca8210_priv *priv = spi_get_drvdata(spi);
- if (!priv->clk)
- return
+ if (IS_ERR_OR_NULL(priv->clk))
+ return;
of_clk_del_provider(spi->dev.of_node);
clk_unregister(priv->clk);
diff --git a/drivers/net/team/team.c b/drivers/net/team/team.c
index 8b5e1ec6aabfba3756e180d60485c12140b1f626..08f9530fd5b1573cb92ec75e32391a2133a0eddc 100644
--- a/drivers/net/team/team.c
+++ b/drivers/net/team/team.c
@@ -2095,7 +2095,12 @@ static const struct ethtool_ops team_ethtool_ops = {
static void team_setup_by_port(struct net_device *dev,
struct net_device *port_dev)
{
- dev->header_ops = port_dev->header_ops;
+ struct team *team = netdev_priv(dev);
+
+ if (port_dev->type == ARPHRD_ETHER)
+ dev->header_ops = team->header_ops_cache;
+ else
+ dev->header_ops = port_dev->header_ops;
dev->type = port_dev->type;
dev->hard_header_len = port_dev->hard_header_len;
dev->needed_headroom = port_dev->needed_headroom;
@@ -2142,8 +2147,11 @@ static int team_dev_type_check_change(struct net_device *dev,
static void team_setup(struct net_device *dev)
{
+ struct team *team = netdev_priv(dev);
+
ether_setup(dev);
dev->max_mtu = ETH_MAX_MTU;
+ team->header_ops_cache = dev->header_ops;
dev->netdev_ops = &team_netdev_ops;
dev->ethtool_ops = &team_ethtool_ops;
diff --git a/drivers/net/thunderbolt.c b/drivers/net/thunderbolt.c
index 51b5442fbc668eef0cdbe1a0b35dc71c65eb336c..e0b4c54e6c08f6f3c48da69cbe53307266e2efd4 100644
--- a/drivers/net/thunderbolt.c
+++ b/drivers/net/thunderbolt.c
@@ -961,12 +961,11 @@ static bool tbnet_xmit_csum_and_map(struct tbnet *net, struct sk_buff *skb,
*tucso = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
ip_hdr(skb)->daddr, 0,
ip_hdr(skb)->protocol, 0);
- } else if (skb_is_gso_v6(skb)) {
+ } else if (skb_is_gso(skb) && skb_is_gso_v6(skb)) {
tucso = dest + ((void *)&(tcp_hdr(skb)->check) - data);
*tucso = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
&ipv6_hdr(skb)->daddr, 0,
IPPROTO_TCP, 0);
- return false;
} else if (protocol == htons(ETH_P_IPV6)) {
tucso = dest + skb_checksum_start_offset(skb) + skb->csum_offset;
*tucso = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
diff --git a/drivers/net/usb/dm9601.c b/drivers/net/usb/dm9601.c
index 915ac75b55fc7c43f55db19b379983216b93de5f..5aad26600b03eb0a94446b4509375e5f6d40e042 100644
--- a/drivers/net/usb/dm9601.c
+++ b/drivers/net/usb/dm9601.c
@@ -221,13 +221,18 @@ static int dm9601_mdio_read(struct net_device *netdev, int phy_id, int loc)
struct usbnet *dev = netdev_priv(netdev);
__le16 res;
+ int err;
if (phy_id) {
netdev_dbg(dev->net, "Only internal phy supported\n");
return 0;
}
- dm_read_shared_word(dev, 1, loc, &res);
+ err = dm_read_shared_word(dev, 1, loc, &res);
+ if (err < 0) {
+ netdev_err(dev->net, "MDIO read error: %d\n", err);
+ return err;
+ }
netdev_dbg(dev->net,
"dm9601_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
diff --git a/drivers/net/usb/smsc75xx.c b/drivers/net/usb/smsc75xx.c
index 313a4b0edc6b3847a3177a86bccc2255b6009edd..573d7ad2e7082f88775fe7326f57783cf56cbb9c 100644
--- a/drivers/net/usb/smsc75xx.c
+++ b/drivers/net/usb/smsc75xx.c
@@ -102,7 +102,9 @@ static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
| USB_TYPE_VENDOR | USB_RECIP_DEVICE,
0, index, &buf, 4);
- if (unlikely(ret < 0)) {
+ if (unlikely(ret < 4)) {
+ ret = ret < 0 ? ret : -ENODATA;
+
netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
index, ret);
return ret;
diff --git a/drivers/net/usb/smsc95xx.c b/drivers/net/usb/smsc95xx.c
index 085048686413524febe3b4b42998f9402316bb89..37547ac72840fd067a156f1f58ba22ab7d9ec3d3 100644
--- a/drivers/net/usb/smsc95xx.c
+++ b/drivers/net/usb/smsc95xx.c
@@ -1054,7 +1054,7 @@ static int smsc95xx_reset(struct usbnet *dev)
if (timeout >= 100) {
netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n");
- return ret;
+ return -ETIMEDOUT;
}
ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_);
diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
index 5df6e85e7ccb7884590ec635f2748c1ba3760da2..c8cff000a931f969958771c7b0ae48a1f0f6966f 100644
--- a/drivers/net/wan/fsl_ucc_hdlc.c
+++ b/drivers/net/wan/fsl_ucc_hdlc.c
@@ -37,6 +37,8 @@
#define TDM_PPPOHT_SLIC_MAXIN
+static int uhdlc_close(struct net_device *dev);
+
static struct ucc_tdm_info utdm_primary_info = {
.uf_info = {
.tsa = 0,
@@ -661,6 +663,7 @@ static int uhdlc_open(struct net_device *dev)
hdlc_device *hdlc = dev_to_hdlc(dev);
struct ucc_hdlc_private *priv = hdlc->priv;
struct ucc_tdm *utdm = priv->utdm;
+ int rc = 0;
if (priv->hdlc_busy != 1) {
if (request_irq(priv->ut_info->uf_info.irq,
@@ -683,10 +686,13 @@ static int uhdlc_open(struct net_device *dev)
netif_device_attach(priv->ndev);
napi_enable(&priv->napi);
netif_start_queue(dev);
- hdlc_open(dev);
+
+ rc = hdlc_open(dev);
+ if (rc)
+ uhdlc_close(dev);
}
- return 0;
+ return rc;
}
static void uhdlc_memclean(struct ucc_hdlc_private *priv)
@@ -775,6 +781,8 @@ static int uhdlc_close(struct net_device *dev)
netif_stop_queue(dev);
priv->hdlc_busy = 0;
+ hdlc_close(dev);
+
return 0;
}
diff --git a/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c b/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c
index 5380fba652cc49ff2a2aef2528b35e674b8f1a4a..1aa0bcdab8ef4a12fd55681583482aaf54b66aa1 100644
--- a/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c
+++ b/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c
@@ -986,8 +986,8 @@ void mwifiex_11n_rxba_sync_event(struct mwifiex_private *priv,
}
}
- tlv_buf_left -= (sizeof(*tlv_rxba) + tlv_len);
- tmp = (u8 *)tlv_rxba + tlv_len + sizeof(*tlv_rxba);
+ tlv_buf_left -= (sizeof(tlv_rxba->header) + tlv_len);
+ tmp = (u8 *)tlv_rxba + sizeof(tlv_rxba->header) + tlv_len;
tlv_rxba = (struct mwifiex_ie_types_rxba_sync *)tmp;
}
}
diff --git a/drivers/net/wireless/marvell/mwifiex/sta_rx.c b/drivers/net/wireless/marvell/mwifiex/sta_rx.c
index f3c6daeba1b852a182c6b88bbc9a741670cbde54..346e91b9f2ad7bfe4d7bebbb427b956a973cf133 100644
--- a/drivers/net/wireless/marvell/mwifiex/sta_rx.c
+++ b/drivers/net/wireless/marvell/mwifiex/sta_rx.c
@@ -98,7 +98,8 @@ int mwifiex_process_rx_packet(struct mwifiex_private *priv,
rx_pkt_len = le16_to_cpu(local_rx_pd->rx_pkt_length);
rx_pkt_hdr = (void *)local_rx_pd + rx_pkt_off;
- if (sizeof(*rx_pkt_hdr) + rx_pkt_off > skb->len) {
+ if (sizeof(rx_pkt_hdr->eth803_hdr) + sizeof(rfc1042_header) +
+ rx_pkt_off > skb->len) {
mwifiex_dbg(priv->adapter, ERROR,
"wrong rx packet offset: len=%d, rx_pkt_off=%d\n",
skb->len, rx_pkt_off);
@@ -107,12 +108,13 @@ int mwifiex_process_rx_packet(struct mwifiex_private *priv,
return -1;
}
- if ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header,
- sizeof(bridge_tunnel_header))) ||
- (!memcmp(&rx_pkt_hdr->rfc1042_hdr, rfc1042_header,
- sizeof(rfc1042_header)) &&
- ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_AARP &&
- ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_IPX)) {
+ if (sizeof(*rx_pkt_hdr) + rx_pkt_off <= skb->len &&
+ ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header,
+ sizeof(bridge_tunnel_header))) ||
+ (!memcmp(&rx_pkt_hdr->rfc1042_hdr, rfc1042_header,
+ sizeof(rfc1042_header)) &&
+ ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_AARP &&
+ ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_IPX))) {
/*
* Replace the 803 header and rfc1042 header (llc/snap) with an
* EthernetII header, keep the src/dst and snap_type
diff --git a/drivers/net/xen-netback/interface.c b/drivers/net/xen-netback/interface.c
index df20270827631069f53232d2c120f57d84575e9f..fadbde1d21add4a7a34ce9fd0990bf3d5a1c6a42 100644
--- a/drivers/net/xen-netback/interface.c
+++ b/drivers/net/xen-netback/interface.c
@@ -41,7 +41,6 @@
#include
#include
-#define XENVIF_QUEUE_LENGTH 32
#define XENVIF_NAPI_WEIGHT 64
/* Number of bytes allowed on the internal guest Rx queue. */
@@ -526,8 +525,6 @@ struct xenvif *xenvif_alloc(struct device *parent, domid_t domid,
dev->features = dev->hw_features | NETIF_F_RXCSUM;
dev->ethtool_ops = &xenvif_ethtool_ops;
- dev->tx_queue_len = XENVIF_QUEUE_LENGTH;
-
dev->min_mtu = ETH_MIN_MTU;
dev->max_mtu = ETH_MAX_MTU - VLAN_ETH_HLEN;
diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index b06d2b6bd3febc5417372d134df245be989c6d95..163497ef48fd7dc06d07655ea7a5bad51c08dd0c 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -2501,8 +2501,6 @@ static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
size_t alloc_size;
node = dev_to_node(&pdev->dev);
- if (node == NUMA_NO_NODE)
- set_dev_node(&pdev->dev, first_memory_node);
dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
if (!dev)
diff --git a/drivers/parisc/iosapic.c b/drivers/parisc/iosapic.c
index eb9137faccf74e09f98731014b4d19d0570387bc..4cc08d13b82fae284837ed44ffd271fbfa213126 100644
--- a/drivers/parisc/iosapic.c
+++ b/drivers/parisc/iosapic.c
@@ -216,9 +216,9 @@ static inline void iosapic_write(void __iomem *iosapic, unsigned int reg, u32 va
static DEFINE_SPINLOCK(iosapic_lock);
-static inline void iosapic_eoi(void __iomem *addr, unsigned int data)
+static inline void iosapic_eoi(__le32 __iomem *addr, __le32 data)
{
- __raw_writel(data, addr);
+ __raw_writel((__force u32)data, addr);
}
/*
diff --git a/drivers/parisc/iosapic_private.h b/drivers/parisc/iosapic_private.h
index 6e05e30a2450a052c9d1f4d0d460826a10514b52..7a928c03d5201d6284cba250cbda20a1c1e1df40 100644
--- a/drivers/parisc/iosapic_private.h
+++ b/drivers/parisc/iosapic_private.h
@@ -132,8 +132,8 @@ struct iosapic_irt {
struct vector_info {
struct iosapic_info *iosapic; /* I/O SAPIC this vector is on */
struct irt_entry *irte; /* IRT entry */
- u32 __iomem *eoi_addr; /* precalculate EOI reg address */
- u32 eoi_data; /* IA64: ? PA: swapped txn_data */
+ __le32 __iomem *eoi_addr; /* precalculate EOI reg address */
+ __le32 eoi_data; /* IA64: ? PA: swapped txn_data */
int txn_irq; /* virtual IRQ number for processor */
ulong txn_addr; /* IA64: id_eid PA: partial HPA */
u32 txn_data; /* CPU interrupt bit */
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index ea0cd2401d6b7486caa60df2de5cf4c1b7fb38b6..133fad284c9fa7fc26c2c68fb6597bebc35d9e5c 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -758,8 +758,6 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
if (IS_ERR(res->phy_ahb_reset))
return PTR_ERR(res->phy_ahb_reset);
- dw_pcie_dbi_ro_wr_dis(pci);
-
return 0;
}
diff --git a/drivers/phy/motorola/phy-mapphone-mdm6600.c b/drivers/phy/motorola/phy-mapphone-mdm6600.c
index 77518010adc88353002561543c3ebf3b66de3ceb..44ad15ca881ee248fd546c1c02d127c8c8ccc20f 100644
--- a/drivers/phy/motorola/phy-mapphone-mdm6600.c
+++ b/drivers/phy/motorola/phy-mapphone-mdm6600.c
@@ -612,6 +612,7 @@ static int phy_mdm6600_remove(struct platform_device *pdev)
struct phy_mdm6600 *ddata = platform_get_drvdata(pdev);
struct gpio_desc *reset_gpio = ddata->ctrl_gpios[PHY_MDM6600_RESET];
+ pm_runtime_get_noresume(ddata->dev);
pm_runtime_dont_use_autosuspend(ddata->dev);
pm_runtime_put_sync(ddata->dev);
pm_runtime_disable(ddata->dev);
diff --git a/drivers/s390/scsi/zfcp_aux.c b/drivers/s390/scsi/zfcp_aux.c
index d1b531fe9ada1d72403a8181ccaae2270b866a07..e5697ae9b4a3fc2d01200f59c4117ba03b0537e3 100644
--- a/drivers/s390/scsi/zfcp_aux.c
+++ b/drivers/s390/scsi/zfcp_aux.c
@@ -493,12 +493,12 @@ struct zfcp_port *zfcp_port_enqueue(struct zfcp_adapter *adapter, u64 wwpn,
if (port) {
put_device(&port->dev);
retval = -EEXIST;
- goto err_out;
+ goto err_put;
}
port = kzalloc(sizeof(struct zfcp_port), GFP_KERNEL);
if (!port)
- goto err_out;
+ goto err_put;
rwlock_init(&port->unit_list_lock);
INIT_LIST_HEAD(&port->unit_list);
@@ -521,7 +521,7 @@ struct zfcp_port *zfcp_port_enqueue(struct zfcp_adapter *adapter, u64 wwpn,
if (dev_set_name(&port->dev, "0x%016llx", (unsigned long long)wwpn)) {
kfree(port);
- goto err_out;
+ goto err_put;
}
retval = -EINVAL;
@@ -538,8 +538,9 @@ struct zfcp_port *zfcp_port_enqueue(struct zfcp_adapter *adapter, u64 wwpn,
return port;
-err_out:
+err_put:
zfcp_ccw_adapter_put(adapter);
+err_out:
return ERR_PTR(retval);
}
diff --git a/drivers/scsi/megaraid/megaraid_sas.h b/drivers/scsi/megaraid/megaraid_sas.h
index 67d356d84717631eb7f1c85726a6eff334e2da7f..0d7cca9365aacd4837226ed2a4df177cbad848ce 100644
--- a/drivers/scsi/megaraid/megaraid_sas.h
+++ b/drivers/scsi/megaraid/megaraid_sas.h
@@ -2193,7 +2193,8 @@ struct megasas_instance {
u32 secure_jbod_support;
u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */
bool use_seqnum_jbod_fp; /* Added for PD sequence */
- spinlock_t crashdump_lock;
+ bool smp_affinity_enable;
+ struct mutex crashdump_lock;
struct megasas_register_set __iomem *reg_set;
u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
@@ -2210,6 +2211,7 @@ struct megasas_instance {
u16 ldio_threshold;
u16 cur_can_queue;
u32 max_sectors_per_req;
+ bool msix_load_balance;
struct megasas_aen_event *ev;
struct megasas_cmd **cmd_list;
@@ -2246,6 +2248,7 @@ struct megasas_instance {
atomic_t sge_holes_type1;
atomic_t sge_holes_type2;
atomic_t sge_holes_type3;
+ atomic64_t total_io_count;
struct megasas_instance_template *instancet;
struct tasklet_struct isr_tasklet;
diff --git a/drivers/scsi/megaraid/megaraid_sas_base.c b/drivers/scsi/megaraid/megaraid_sas_base.c
index 8d1df03386b4fe2b119e6abd3e7443781032a24e..ac4800fb1a7fb40fc780f6b636eead0cb745fdbd 100644
--- a/drivers/scsi/megaraid/megaraid_sas_base.c
+++ b/drivers/scsi/megaraid/megaraid_sas_base.c
@@ -3004,14 +3004,13 @@ megasas_fw_crash_buffer_store(struct device *cdev,
struct megasas_instance *instance =
(struct megasas_instance *) shost->hostdata;
int val = 0;
- unsigned long flags;
if (kstrtoint(buf, 0, &val) != 0)
return -EINVAL;
- spin_lock_irqsave(&instance->crashdump_lock, flags);
+ mutex_lock(&instance->crashdump_lock);
instance->fw_crash_buffer_offset = val;
- spin_unlock_irqrestore(&instance->crashdump_lock, flags);
+ mutex_unlock(&instance->crashdump_lock);
return strlen(buf);
}
@@ -3027,17 +3026,16 @@ megasas_fw_crash_buffer_show(struct device *cdev,
unsigned long dmachunk = CRASH_DMA_BUF_SIZE;
unsigned long chunk_left_bytes;
unsigned long src_addr;
- unsigned long flags;
u32 buff_offset;
- spin_lock_irqsave(&instance->crashdump_lock, flags);
+ mutex_lock(&instance->crashdump_lock);
buff_offset = instance->fw_crash_buffer_offset;
if (!instance->crash_dump_buf ||
!((instance->fw_crash_state == AVAILABLE) ||
(instance->fw_crash_state == COPYING))) {
dev_err(&instance->pdev->dev,
"Firmware crash dump is not available\n");
- spin_unlock_irqrestore(&instance->crashdump_lock, flags);
+ mutex_unlock(&instance->crashdump_lock);
return -EINVAL;
}
@@ -3046,7 +3044,7 @@ megasas_fw_crash_buffer_show(struct device *cdev,
if (buff_offset > (instance->fw_crash_buffer_size * dmachunk)) {
dev_err(&instance->pdev->dev,
"Firmware crash dump offset is out of range\n");
- spin_unlock_irqrestore(&instance->crashdump_lock, flags);
+ mutex_unlock(&instance->crashdump_lock);
return 0;
}
@@ -3058,7 +3056,7 @@ megasas_fw_crash_buffer_show(struct device *cdev,
src_addr = (unsigned long)instance->crash_buf[buff_offset / dmachunk] +
(buff_offset % dmachunk);
memcpy(buf, (void *)src_addr, size);
- spin_unlock_irqrestore(&instance->crashdump_lock, flags);
+ mutex_unlock(&instance->crashdump_lock);
return size;
}
@@ -3083,7 +3081,6 @@ megasas_fw_crash_state_store(struct device *cdev,
struct megasas_instance *instance =
(struct megasas_instance *) shost->hostdata;
int val = 0;
- unsigned long flags;
if (kstrtoint(buf, 0, &val) != 0)
return -EINVAL;
@@ -3097,9 +3094,9 @@ megasas_fw_crash_state_store(struct device *cdev,
instance->fw_crash_state = val;
if ((val == COPIED) || (val == COPY_ERROR)) {
- spin_lock_irqsave(&instance->crashdump_lock, flags);
+ mutex_lock(&instance->crashdump_lock);
megasas_free_host_crash_buffer(instance);
- spin_unlock_irqrestore(&instance->crashdump_lock, flags);
+ mutex_unlock(&instance->crashdump_lock);
if (val == COPY_ERROR)
dev_info(&instance->pdev->dev, "application failed to "
"copy Firmware crash dump\n");
@@ -5101,6 +5098,7 @@ megasas_setup_irqs_msix(struct megasas_instance *instance, u8 is_probe)
&instance->irq_context[j]);
/* Retry irq register for IO_APIC*/
instance->msix_vectors = 0;
+ instance->msix_load_balance = false;
if (is_probe) {
pci_free_irq_vectors(instance->pdev);
return megasas_setup_irqs_ioapic(instance);
@@ -5109,6 +5107,7 @@ megasas_setup_irqs_msix(struct megasas_instance *instance, u8 is_probe)
}
}
}
+
return 0;
}
@@ -5364,6 +5363,13 @@ static int megasas_init_fw(struct megasas_instance *instance)
if (rdpq_enable)
instance->is_rdpq = (scratch_pad_2 & MR_RDPQ_MODE_OFFSET) ?
1 : 0;
+
+ if (instance->adapter_type >= INVADER_SERIES &&
+ !instance->msix_combined) {
+ instance->msix_load_balance = true;
+ instance->smp_affinity_enable = false;
+ }
+
fw_msix_count = instance->msix_vectors;
/* Save 1-15 reply post index address to local memory
* Index 0 is already saved from reg offset
@@ -5382,17 +5388,20 @@ static int megasas_init_fw(struct megasas_instance *instance)
instance->msix_vectors);
} else /* MFI adapters */
instance->msix_vectors = 1;
+
/* Don't bother allocating more MSI-X vectors than cpus */
instance->msix_vectors = min(instance->msix_vectors,
(unsigned int)num_online_cpus());
- if (smp_affinity_enable)
+ if (instance->smp_affinity_enable)
irq_flags |= PCI_IRQ_AFFINITY;
i = pci_alloc_irq_vectors(instance->pdev, 1,
instance->msix_vectors, irq_flags);
- if (i > 0)
+ if (i > 0) {
instance->msix_vectors = i;
- else
+ } else {
instance->msix_vectors = 0;
+ instance->msix_load_balance = false;
+ }
}
/*
* MSI-X host index 0 is common for all adapter.
@@ -6447,11 +6456,12 @@ static inline void megasas_init_ctrl_params(struct megasas_instance *instance)
INIT_LIST_HEAD(&instance->internal_reset_pending_q);
atomic_set(&instance->fw_outstanding, 0);
+ atomic64_set(&instance->total_io_count, 0);
init_waitqueue_head(&instance->int_cmd_wait_q);
init_waitqueue_head(&instance->abort_cmd_wait_q);
- spin_lock_init(&instance->crashdump_lock);
+ mutex_init(&instance->crashdump_lock);
spin_lock_init(&instance->mfi_pool_lock);
spin_lock_init(&instance->hba_lock);
spin_lock_init(&instance->stream_lock);
@@ -6469,6 +6479,8 @@ static inline void megasas_init_ctrl_params(struct megasas_instance *instance)
instance->last_time = 0;
instance->disableOnlineCtrlReset = 1;
instance->UnevenSpanSupport = 0;
+ instance->smp_affinity_enable = smp_affinity_enable ? true : false;
+ instance->msix_load_balance = false;
if (instance->adapter_type != MFI_SERIES) {
INIT_WORK(&instance->work_init, megasas_fusion_ocr_wq);
@@ -6818,7 +6830,7 @@ megasas_resume(struct pci_dev *pdev)
/* Now re-enable MSI-X */
if (instance->msix_vectors) {
irq_flags = PCI_IRQ_MSIX;
- if (smp_affinity_enable)
+ if (instance->smp_affinity_enable)
irq_flags |= PCI_IRQ_AFFINITY;
}
rval = pci_alloc_irq_vectors(instance->pdev, 1,
diff --git a/drivers/scsi/megaraid/megaraid_sas_fusion.c b/drivers/scsi/megaraid/megaraid_sas_fusion.c
index b400167f9ad428ea9a7faca85072b090f7f15d00..294e1a3a6adfa70d2dea243e75214678d6531bf2 100644
--- a/drivers/scsi/megaraid/megaraid_sas_fusion.c
+++ b/drivers/scsi/megaraid/megaraid_sas_fusion.c
@@ -2641,8 +2641,13 @@ megasas_build_ldio_fusion(struct megasas_instance *instance,
fp_possible = (io_info.fpOkForIo > 0) ? true : false;
}
- cmd->request_desc->SCSIIO.MSIxIndex =
- instance->reply_map[raw_smp_processor_id()];
+ if (instance->msix_load_balance)
+ cmd->request_desc->SCSIIO.MSIxIndex =
+ (mega_mod64(atomic64_add_return(1, &instance->total_io_count),
+ instance->msix_vectors));
+ else
+ cmd->request_desc->SCSIIO.MSIxIndex =
+ instance->reply_map[raw_smp_processor_id()];
praid_context = &io_request->RaidContext;
@@ -2969,8 +2974,13 @@ megasas_build_syspd_fusion(struct megasas_instance *instance,
cmd->request_desc->SCSIIO.DevHandle = io_request->DevHandle;
- cmd->request_desc->SCSIIO.MSIxIndex =
- instance->reply_map[raw_smp_processor_id()];
+ if (instance->msix_load_balance)
+ cmd->request_desc->SCSIIO.MSIxIndex =
+ (mega_mod64(atomic64_add_return(1, &instance->total_io_count),
+ instance->msix_vectors));
+ else
+ cmd->request_desc->SCSIIO.MSIxIndex =
+ instance->reply_map[raw_smp_processor_id()];
if (!fp_possible) {
/* system pd firmware path */
diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c
index 6c9095d0aa0f4fbf4139d618fc6f113d75e623f5..9a25e92ef1abeb43199e06a4937e41177d71fdd9 100644
--- a/drivers/scsi/qla2xxx/qla_attr.c
+++ b/drivers/scsi/qla2xxx/qla_attr.c
@@ -2088,8 +2088,6 @@ qla24xx_vport_create(struct fc_vport *fc_vport, bool disable)
vha->flags.difdix_supported = 1;
ql_dbg(ql_dbg_user, vha, 0x7082,
"Registered for DIF/DIX type 1 and 3 protection.\n");
- if (ql2xenabledif == 1)
- prot = SHOST_DIX_TYPE0_PROTECTION;
scsi_host_set_prot(vha->host,
prot | SHOST_DIF_TYPE1_PROTECTION
| SHOST_DIF_TYPE2_PROTECTION
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c
index 36871760a5d372da9b63109a2be5fa8d4edb22ec..fcbadd41856c20a3fee6850095ca17b69c716a09 100644
--- a/drivers/scsi/qla2xxx/qla_dbg.c
+++ b/drivers/scsi/qla2xxx/qla_dbg.c
@@ -22,7 +22,7 @@
* | Queue Command and IO tracing | 0x3074 | 0x300b |
* | | | 0x3027-0x3028 |
* | | | 0x303d-0x3041 |
- * | | | 0x302d,0x3033 |
+ * | | | 0x302e,0x3033 |
* | | | 0x3036,0x3038 |
* | | | 0x303a |
* | DPC Thread | 0x4023 | 0x4002,0x4013 |
diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
index 4580774b2c3e7fd5dbad847db40af16e3650cd54..36dca08166f295d9447fb72cf209366ed968f3ff 100644
--- a/drivers/scsi/qla2xxx/qla_os.c
+++ b/drivers/scsi/qla2xxx/qla_os.c
@@ -277,6 +277,20 @@ MODULE_PARM_DESC(qla2xuseresexchforels,
"Reserve 1/2 of emergency exchanges for ELS.\n"
" 0 (default): disabled");
+int ql2xprotmask;
+module_param(ql2xprotmask, int, 0644);
+MODULE_PARM_DESC(ql2xprotmask,
+ "Override DIF/DIX protection capabilities mask\n"
+ "Default is 0 which sets protection mask based on "
+ "capabilities reported by HBA firmware.\n");
+
+int ql2xprotguard;
+module_param(ql2xprotguard, int, 0644);
+MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n"
+ " 0 -- Let HBA firmware decide\n"
+ " 1 -- Force T10 CRC\n"
+ " 2 -- Force IP checksum\n");
+
/*
* SCSI host template entry points
*/
@@ -3055,6 +3069,13 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
host->max_id = ha->max_fibre_devices;
host->cmd_per_lun = 3;
host->unique_id = host->host_no;
+
+ if (ql2xenabledif && ql2xenabledif != 2) {
+ ql_log(ql_log_warn, base_vha, 0x302d,
+ "Invalid value for ql2xenabledif, resetting it to default (2)\n");
+ ql2xenabledif = 2;
+ }
+
if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
host->max_cmd_len = 32;
else
@@ -3291,15 +3312,16 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
base_vha->flags.difdix_supported = 1;
ql_dbg(ql_dbg_init, base_vha, 0x00f1,
"Registering for DIF/DIX type 1 and 3 protection.\n");
- if (ql2xenabledif == 1)
- prot = SHOST_DIX_TYPE0_PROTECTION;
- scsi_host_set_prot(host,
- prot | SHOST_DIF_TYPE1_PROTECTION
- | SHOST_DIF_TYPE2_PROTECTION
- | SHOST_DIF_TYPE3_PROTECTION
- | SHOST_DIX_TYPE1_PROTECTION
- | SHOST_DIX_TYPE2_PROTECTION
- | SHOST_DIX_TYPE3_PROTECTION);
+ if (ql2xprotmask)
+ scsi_host_set_prot(host, ql2xprotmask);
+ else
+ scsi_host_set_prot(host,
+ prot | SHOST_DIF_TYPE1_PROTECTION
+ | SHOST_DIF_TYPE2_PROTECTION
+ | SHOST_DIF_TYPE3_PROTECTION
+ | SHOST_DIX_TYPE1_PROTECTION
+ | SHOST_DIX_TYPE2_PROTECTION
+ | SHOST_DIX_TYPE3_PROTECTION);
guard = SHOST_DIX_GUARD_CRC;
@@ -3307,7 +3329,10 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
(ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
guard |= SHOST_DIX_GUARD_IP;
- scsi_host_set_guard(host, guard);
+ if (ql2xprotguard)
+ scsi_host_set_guard(host, ql2xprotguard);
+ else
+ scsi_host_set_guard(host, guard);
} else
base_vha->flags.difdix_supported = 0;
}
diff --git a/drivers/staging/fw-api/fw/htt.h b/drivers/staging/fw-api/fw/htt.h
index 37e9514f8014eb1811e0bc009d32be3aef1df14c..0b6c085ad6236f1a15a6cb4661a5afc7e2518558 100644
--- a/drivers/staging/fw-api/fw/htt.h
+++ b/drivers/staging/fw-api/fw/htt.h
@@ -251,9 +251,13 @@
* 3.123 Add HTT_OPTION_TLV_TCL_METADATA_V21 def.
* 3.124 Add HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT def.
* 3.125 Expand fisa_aggr_limit bits in fisa_control_bits_v2.
+ * 3.126 Add HTT_RXDATA_ERR_INVALID_PEER def.
+ * 3.127 Add transmit_count fields in htt_tx_wbm_completion_vX structs.
+ * 3.128 Add H2T TX_LATENCY_STATS_CFG + T2H TX_LATENCY_STATS_PERIODIC_IND
+ * msg defs
*/
#define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 125
+#define HTT_CURRENT_VERSION_MINOR 128
#define HTT_NUM_TX_FRAG_DESC 1024
@@ -807,6 +811,8 @@ typedef enum {
HTT_STATS_PDEV_TDMA_TAG = 187, /* htt_pdev_tdma_stats_tlv */
HTT_STATS_CODEL_SVC_CLASS_TAG = 188, /* htt_codel_svc_class_stats_tlv */
HTT_STATS_CODEL_MSDUQ_TAG = 189, /* htt_codel_msduq_stats_tlv */
+ HTT_STATS_MLO_SCHED_STATS_TAG = 190, /* htt_mlo_sched_stats_tlv */
+ HTT_STATS_PDEV_MLO_IPC_STATS_TAG = 191, /* htt_pdev_mlo_ipc_stats_tlv */
HTT_STATS_MAX_TAG,
@@ -879,6 +885,7 @@ enum htt_h2t_msg_type {
HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET = 0x22,
HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23,
HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP = 0x24,
+ HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG = 0x25,
/* keep this last */
HTT_H2T_NUM_MSGS
@@ -2876,7 +2883,8 @@ PREPACK struct htt_tx_wbm_completion_v2 {
tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */
reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */
exception_frame: 1,
- rsvd0: 12, /* For future use */
+ transmit_count: 7, /* Refer to struct wbm_release_ring */
+ rsvd0: 5, /* For future use */
used_by_hw4: 1, /* wbm_internal_error bit being used by HW */
rsvd1: 1; /* For future use */
A_UINT32
@@ -2902,6 +2910,8 @@ PREPACK struct htt_tx_wbm_completion_v2 {
#define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S 13
#define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_M 0x00020000
#define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S 17
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M 0x01FC0000
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S 18
/* DWORD 3 */
#define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(_var) \
@@ -2934,6 +2944,16 @@ PREPACK struct htt_tx_wbm_completion_v2 {
((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S)); \
} while (0)
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_GET(_var) \
+ (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M) >> \
+ HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S)
+
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT, _val); \
+ ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S)); \
+ } while (0)
+
/**
* @brief HTT TX WBM Completion from firmware to host (V3)
* @details
@@ -2959,7 +2979,8 @@ PREPACK struct htt_tx_wbm_completion_v3 {
A_UINT32
reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */
exception_frame: 1,
- rsvd0: 27; /* For future use */
+ transmit_count: 7, /* Refer to struct wbm_release_ring */
+ rsvd0: 20; /* For future use */
A_UINT32
data0: 32; /* data0,1 and 2 changes based on tx_status type
* if HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP
@@ -2976,13 +2997,17 @@ PREPACK struct htt_tx_wbm_completion_v3 {
used_by_hw4: 12; /* Refer to struct wbm_release_ring */
} POSTPACK;
-
+/* DWORD 3 */
#define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_M 0x0001E000
#define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S 13
+
+/* DWORD 4 */
#define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_M 0x0000000F
#define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S 0
#define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_M 0x00000010
#define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S 4
+#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M 0x00000FE0
+#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S 5
#define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(_var) \
@@ -3015,6 +3040,16 @@ PREPACK struct htt_tx_wbm_completion_v3 {
((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S)); \
} while (0)
+#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_GET(_var) \
+ (((_var) & HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M) >> \
+ HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S)
+
+#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT, _val); \
+ ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S)); \
+ } while (0)
+
typedef enum {
TX_FRAME_TYPE_UNDEFINED = 0,
@@ -3055,7 +3090,11 @@ PREPACK struct htt_tx_wbm_transmit_status {
* contains valid data.
*/
frame_type: 4, /* holds htt_tx_wbm_status_frame_type value */
- reserved: 4;
+ transmit_count_valid: 1, /* If this "transmit_count_valid" is set, the
+ * transmit_count field in struct
+ * htt_tx_wbm_completion_vx has valid data.
+ */
+ reserved: 3;
A_UINT32
ppdu_start_tsf: 32; /* PPDU Start timestamp added for multicast
* packets in the wbm completion path
@@ -3079,6 +3118,10 @@ PREPACK struct htt_tx_wbm_transmit_status {
#define HTT_TX_WBM_COMPLETION_V2_MCAST_S 22
#define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_M 0x00800000
#define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S 23
+#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M 0x0F000000
+#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S 24
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M 0x10000000
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S 28
/* DWORD 4 */
#define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(_var) \
@@ -3152,6 +3195,26 @@ PREPACK struct htt_tx_wbm_transmit_status {
((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S)); \
} while (0)
+#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_GET(_var) \
+ (((_var) & HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M) >> \
+ HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S)
+
+#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE, _val); \
+ ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S)); \
+
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_GET(_var) \
+ (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M) >> \
+ HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S)
+
+#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST_VALID, _val); \
+ ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S)); \
+ } while (0)
+
+
/**
* @brief HTT TX WBM reinject status from firmware to host
* @details
@@ -10714,6 +10777,88 @@ typedef struct {
} while (0)
+/**
+ * @brief host -> tgt msg to configure params for PPDU tx latency stats report
+ *
+ * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG
+ *
+ * @details
+ * HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG message is sent by the host to
+ * configure the parameters needed for FW to report PPDU tx latency stats
+ * for latency prediction in user space.
+ *
+ * The message would appear as follows:
+ * |31 28|27 12|11|10 8|7 0|
+ * |-----------+-------------------+--+-------+--------------|
+ * |granularity| periodic interval | E|vdev ID| msg type |
+ * |-----------+-------------------+--+-------+--------------|
+ * Where: E = enable
+ *
+ * The message is interpreted as follows:
+ * dword0 - b'0:7 - msg_type: This will be set to 0x25
+ * (HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG)
+ * b'8:10 - vdev_id: Indicate which vdev is configuration is for
+ * b'11 - enable: Indicate this message is to enable/disable
+ * PPDU latency report from FW
+ * b'12:27 - periodic_interval: Indicate the report interval in MS
+ * b'28:31 - granularity: Indicate the granularity of the latency
+ * stats report, in ms
+ */
+
+/* HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG */
+PREPACK struct htt_h2t_tx_latency_stats_cfg {
+ A_UINT32 msg_type :8,
+ vdev_id :3,
+ enable :1,
+ periodic_interval :16,
+ granularity :4;
+} POSTPACK;
+
+#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M 0x00000700
+#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S 8
+#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_GET(_var) \
+ (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M) >> \
+ HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S)
+#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID, _val); \
+ ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S)); \
+ } while (0)
+
+#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M 0x00000800
+#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S 11
+#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_GET(_var) \
+ (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M) >> \
+ HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S)
+#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE, _val); \
+ ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S)); \
+ } while (0)
+
+#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M 0x0FFFF000
+#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S 12
+#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_GET(_var) \
+ (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M) >> \
+ HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S)
+#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL, _val); \
+ ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S)); \
+ } while (0)
+
+#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M 0xF0000000
+#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S 28
+#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_GET(_var) \
+ (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M) >> \
+ HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S)
+#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY, _val); \
+ ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S)); \
+ } while (0)
+
+
/*=== target -> host messages ===============================================*/
@@ -10784,6 +10929,7 @@ enum htt_t2h_msg_type {
HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND = 0x37,
HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND = 0x38,
HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT = 0x39,
+ HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND = 0x3a,
HTT_T2H_MSG_TYPE_TEST,
@@ -21383,6 +21529,12 @@ typedef enum htt_t2h_rx_data_msdu_err {
*/
HTT_RXDATA_ERR_ZERO_LEN_MSDU = 7,
+ /* ERR_INVALID_PEER:
+ * FW sets this error flag when MSDU is recived from invalid PEER
+ * HOST decides to send DEAUTH or not, recyles buffer.
+ */
+ HTT_RXDATA_ERR_INVALID_PEER = 8,
+
/* add new error codes here */
HTT_RXDATA_ERR_MAX = 32
@@ -21925,5 +22077,141 @@ typedef struct {
#define HTT_PEER_AST_OVERRIDE_INDEX_IND_BYTES 16
+/**
+ * @brief target -> periodic report of tx latency to host
+ *
+ * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND
+ *
+ * @details
+ * The message starts with a message header followed by one or more
+ * htt_t2h_peer_tx_latency_stats structs, one for each peer within the vdev.
+ * After each upload, these tx latency stats will be reset.
+ *
+ * |31 24|23 16|15 14|13 10|9 8|7 0|
+ * +-------------------------+-----+-----+---+----------|
+ * hdr | |pyld elem sz| | GR | P | msg type |
+ *- -|=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-|
+ * pyld | peer ID |
+ * |----------------------------------------------------|
+ * | peer_tx_latency[0] |
+ * |----------------------------------------------------|
+ * 1st | peer_tx_latency[1] |
+ * peer |----------------------------------------------------|
+ * | peer_tx_latency[2] |
+ * |----------------------------------------------------|
+ * | peer_tx_latency[3] |
+ * |----------------------------------------------------|
+ * | avg latency |
+ * |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-|
+ * | peer ID |
+ * |----------------------------------------------------|
+ * | peer_tx_latency[0] |
+ * |----------------------------------------------------|
+ * 2nd | peer_tx_latency[1] |
+ * peer |----------------------------------------------------|
+ * | peer_tx_latency[2] |
+ * |----------------------------------------------------|
+ * | peer_tx_latency[3] |
+ * |----------------------------------------------------|
+ * | avg latency |
+ * |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-|
+ * Where:
+ * P = pdev ID
+ * GR = granularity
+ *
+ * @details
+ * htt_t2h_tx_latency_stats_periodic_hdr_t:
+ * - msg_type
+ * Bits 7:0
+ * Purpose: identifies this as a tx latency report message
+ * Value: 0x3a (HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND)
+ * - pdev_id
+ * Bits 9:8
+ * Purpose: Indicates which pdev this message is associated with.
+ * - granularity
+ * Bits 13:10
+ * Purpose: specifies the granulairty of each tx latency bucket in MS.
+ * There are 4 buckets in total. E.g. if granularity is set to 5 ms,
+ * then the ranges for the 4 latency histogram buckets will be
+ * 0-5ms, 5ms-10ms, 10ms-15ms, 15ms-max, respectively.
+ * - payload_elem_size
+ * Bits 23:16
+ * Purpose: specifies the size of each element within the msg's payload
+ * In other words, this field specified the value of
+ * sizeof(htt_t2h_peer_tx_latency_stats) based on the target's
+ * revision of the htt_t2h_peer_tx_latency_stats definition.
+ * If the payload_elem_size reported in the message exceeds the
+ * sizeof(htt_t2h_peer_tx_latency_stats) based on the host's
+ * revision of the htt_t2h_peer_tx_latency_stats definition,
+ * the host shall ignore the excess data.
+ * Conversely, if the payload_elem_size reported in the message is
+ * less than sizeof(htt_t2h_peer_tx_latency_stats) based on the host's
+ * revision of the htt_t2h_peer_tx_latency_stats definition,
+ * the host shall use 0x0 values for the portion of the data not
+ * provided by the target.
+ * The host can compare the payload_elem_size to the total size of
+ * the message minus the size of the message header to determine
+ * how many peer payload elements are present in the message.
+ * - sw_peer_id
+ * Purpose: The peer to which the following stats belong
+ * - peer_tx_latency
+ * Purpose: tx latency histogram for this peer, with 4 buckets whose
+ * size (in milliseconds) is specified by the granularity field
+ * - avg_latency
+ * Purpose: average tx latency (in ms) for this peer in this report interval
+*/
+typedef struct {
+ A_UINT32 msg_type: 8,
+ pdev_id: 2,
+ granularity: 4,
+ reserved1: 2,
+ payload_elem_size: 8,
+ reserved2: 8;
+} htt_t2h_tx_latency_stats_periodic_hdr_t;
+
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_HDR_SIZE \
+ (sizeof(htt_t2h_tx_latency_stats_periodic_hdr_t))
+#define HTT_PEER_TX_LATENCY_REPORT_BINS 4
+
+typedef struct _htt_tx_latency_stats {
+ A_UINT32 peer_id;
+ A_UINT32 peer_tx_latency[HTT_PEER_TX_LATENCY_REPORT_BINS];
+ A_UINT32 avg_latency;
+} htt_t2h_peer_tx_latency_stats;
+
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M 0x00000300
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S 8
+
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_GET(_var) \
+ (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S)
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID, _val); \
+ ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S)); \
+ } while (0)
+
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M 0x00003C00
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S 10
+
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_GET(_var) \
+ (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S)
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY, _val); \
+ ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S)); \
+ } while (0)
+
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M 0x00FF0000
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S 16
+
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_GET(_var) \
+ (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S)
+#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE, _val); \
+ ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S)); \
+ } while (0)
+
+
#endif
diff --git a/drivers/staging/fw-api/fw/htt_ppdu_stats.h b/drivers/staging/fw-api/fw/htt_ppdu_stats.h
index 54dd0b67c1fd362e8d7e2d41be3bc2484b6b32f4..fed6e2d63975fa4a2bb1db54784c986928426f95 100644
--- a/drivers/staging/fw-api/fw/htt_ppdu_stats.h
+++ b/drivers/staging/fw-api/fw/htt_ppdu_stats.h
@@ -1057,6 +1057,20 @@ typedef struct {
((_var) |= ((_val) << HTT_PPDU_STATS_USER_COMMON_TLV_CHAIN_ENABLE_BITS_S)); \
} while (0)
+#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_M 0x00010000
+#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_S 16
+
+#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_GET(_var) \
+ (((_var) & HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_M) >> \
+ HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_S)
+
+#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG, _val); \
+ ((_var) |= ((_val) << HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_S)); \
+ } while (0)
+
+
#define HTT_PPDU_STATS_USER_COMMON_TLV_TX_PWR_CHAINS_PER_U32 4
#define HTT_PPDU_STATS_USER_COMMON_TLV_TX_PWR_MASK 0x000000ff
@@ -1194,10 +1208,15 @@ typedef struct {
* Default value: 1
* tx_pwr[0] value is used for all chains if chain_enable_bits field
* is set to 1.
+ *
+ * is_smart_ulofdma_basic_trig:
+ * To check if user grouped in UL OFDMA Basic Trigger Frame is
+ * due to Smart Basic Trigger.
*/
- A_UINT32 tx_pwr_multiplier : 8,
- chain_enable_bits : 8,
- reserved2 : 16;
+ A_UINT32 tx_pwr_multiplier : 8,
+ chain_enable_bits : 8,
+ is_smart_ulofdma_basic_trig: 1,
+ reserved2 : 15;
/*
* Transmit powers (signed values packed into unsigned bitfields)
@@ -1819,6 +1838,19 @@ typedef enum HTT_PPDU_STATS_RESP_PPDU_TYPE HTT_PPDU_STATS_RESP_PPDU_TYPE;
((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_S)); \
} while (0)
+#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_M 0x00020000
+#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_S 17
+
+#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_GET(_var) \
+ (((_var) & HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_M) >> \
+ HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_S)
+
+#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_SET (_var , _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE, _val); \
+ ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_S)); \
+ } while (0)
+
typedef enum HTT_PPDU_STATS_RU_SIZE {
HTT_PPDU_STATS_RU_26,
HTT_PPDU_STATS_RU_52,
@@ -2009,7 +2041,8 @@ typedef struct {
*/
A_UINT32 punc_pattern_bitmap: 16,
extra_eht_ltf: 1,
- reserved4: 15;
+ is_min_rate: 1,
+ reserved4: 14;
} htt_ppdu_stats_user_rate_tlv;
#define HTT_PPDU_STATS_USR_RATE_VALID_M 0x80000000
@@ -2479,6 +2512,11 @@ typedef struct {
* for BW supported by Smart Antenna - 320 MHZ
*/
A_UINT32 max_rates_ext;
+
+ /* hw_prot_dur_us:
+ * hw protection frame's FES duration in micro seconds.
+ */
+ A_UINT32 hw_prot_dur_us;
} htt_ppdu_stats_user_cmpltn_common_tlv;
#define HTT_PPDU_STATS_USER_CMPLTN_BA_BITMAP_TLV_TID_NUM_M 0x000000ff
diff --git a/drivers/staging/fw-api/fw/htt_stats.h b/drivers/staging/fw-api/fw/htt_stats.h
index 11e67bc1ff6a1642f53a35423242da75569dadd2..c779f6fd16e811ed8d4f25930c4e2467c1fc7c69 100644
--- a/drivers/staging/fw-api/fw/htt_stats.h
+++ b/drivers/staging/fw-api/fw/htt_stats.h
@@ -555,6 +555,50 @@ enum htt_dbg_ext_stats_type {
*/
HTT_DBG_CODEL_STATS = 58,
+ /** HTT_DBG_ODD_PDEV_BE_TX_MU_OFDMA_STATS
+ * PARAMS:
+ * - No Params
+ * RESP MSG:
+ * - htt_tx_pdev_mpdu_stats_tlv
+ */
+ HTT_DBG_ODD_PDEV_BE_TX_MU_OFDMA_STATS = 59,
+
+ /** HTT_DBG_EXT_STATS_PDEV_UL_TRIGGER
+ * PARAMS:
+ * - No Params
+ * RESP MSG:
+ * - htt_rx_pdev_be_ul_ofdma_user_stats_tlv
+ */
+ HTT_DBG_ODD_UL_BE_OFDMA_STATS = 60,
+
+ /** HTT_DBG_ODD_BE_TXBF_OFDMA_STATS
+ */
+ HTT_DBG_ODD_BE_TXBF_OFDMA_STATS = 61,
+
+ /** HTT_DBG_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG_STATS
+ * PARAMS:
+ * - No Params
+ * RESP MSG:
+ * - htt_rx_pdev_be_ul_ofdma_user_stats_tlv
+ */
+ HTT_DBG_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG_STATS = 62,
+
+ /** HTT_DBG_MLO_SCHED_STATS
+ * PARAMS:
+ * - No Params
+ * RESP MSG:
+ * - htt_pdev_mlo_sched_stats_tlv
+ */
+ HTT_DBG_MLO_SCHED_STATS = 63,
+
+ /** HTT_DBG_PDEV_MLO_IPC_STATS
+ * PARAMS:
+ * - No Params
+ * RESP MSG:
+ * - htt_pdev_mlo_ipc_stats_tlv
+ */
+ HTT_DBG_PDEV_MLO_IPC_STATS = 64,
+
/* keep this last */
HTT_DBG_NUM_EXT_STATS = 256,
@@ -1636,6 +1680,13 @@ typedef struct {
#define HTT_PEER_DETAILS_ML_PEER_ID_S 1
#define HTT_PEER_DETAILS_LINK_IDX_M 0x001fe000
#define HTT_PEER_DETAILS_LINK_IDX_S 13
+#define HTT_PEER_DETAILS_USE_PPE_M 0x00200000
+#define HTT_PEER_DETAILS_USE_PPE_S 21
+
+
+#define HTT_PEER_DETAILS_SRC_INFO_M 0x00000fff
+#define HTT_PEER_DETAILS_SRC_INFO_S 0
+
#define HTT_PEER_DETAILS_SET(word, httsym, val) \
do { \
@@ -1664,7 +1715,11 @@ typedef struct {
A_UINT32 ml_peer_id_valid : 1, /* [0:0] */
ml_peer_id : 12, /* [12:1] */
link_idx : 8, /* [20:13] */
- rsvd : 11; /* [31:21] */
+ use_ppe : 1, /* [21:21] */
+ rsvd0 : 10; /* [31:22] */
+ /* Dword 9 */
+ A_UINT32 src_info : 12, /* [11:0] */
+ rsvd1 : 20; /* [31:12] */
} htt_peer_details_tlv;
typedef struct {
@@ -2417,6 +2472,8 @@ typedef enum {
#define HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS \
(HTT_STATS_MAX_MUMIMO_GRP_SZ * HTT_STATS_MAX_INVALID_REASON_CODE)
+#define HTT_MAX_NUM_SBT_INTR 4
+
typedef struct {
htt_tlv_hdr_t tlv_hdr;
@@ -2469,6 +2526,19 @@ typedef struct {
/** 11AX HE MU Standalone Freq. BSRP Trigger completed with error(s) */
A_UINT32 standalone_ax_bsr_trigger_err[HTT_NUM_AC_WMM];
/* END DEPRECATED FIELDS */
+ /** smart_basic_trig_sch_histogram:
+ * Count how many times the interval between predictive basic triggers
+ * sent to a given STA based on analysis of that STA's traffic patterns
+ * is within a given range:
+ *
+ * smart_basic_trig_sch_histogram[0]: SBT interval <= 10 ms
+ * smart_basic_trig_sch_histogram[1]: 10 ms < SBT interval <= 20 ms
+ * smart_basic_trig_sch_histogram[2]: 20 ms < SBT interval <= 30 ms
+ * smart_basic_trig_sch_histogram[3]: 30 ms < SBT interval <= 40 ms
+ *
+ * (Smart basic triggers are only used with intervals <= 40 ms.)
+ */
+ A_UINT32 smart_basic_trig_sch_histogram[HTT_MAX_NUM_SBT_INTR];
} htt_tx_selfgen_cmn_stats_tlv;
typedef struct {
@@ -2568,6 +2638,14 @@ typedef struct {
A_UINT32 manual_ax_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM];
/** 11AX HE Manual Multi-User UL OFDMA Trigger completed with error(s) */
A_UINT32 manual_ax_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM];
+ /** 11AX HE UL OFDMA Basic Trigger frames per AC */
+ A_UINT32 ax_basic_trigger_per_ac[HTT_NUM_AC_WMM];
+ /** 11AX HE UL OFDMA Basic Trigger frames per AC completed with error(s) */
+ A_UINT32 ax_basic_trigger_errors_per_ac[HTT_NUM_AC_WMM];
+ /** 11AX HE MU-BAR Trigger frames per AC */
+ A_UINT32 ax_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM];
+ /** 11AX HE MU-BAR Trigger frames per AC completed with error(s) */
+ A_UINT32 ax_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM];
} htt_tx_selfgen_ax_stats_tlv;
typedef struct {
@@ -2623,6 +2701,14 @@ typedef struct {
A_UINT32 manual_be_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM];
/** 11BE EHT Manual Multi-User UL OFDMA Trigger completed with error(s) */
A_UINT32 manual_be_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM];
+ /** 11BE EHT UL OFDMA Basic Trigger frames per AC */
+ A_UINT32 be_basic_trigger_per_ac[HTT_NUM_AC_WMM];
+ /** 11BE EHT UL OFDMA Basic Trigger frames per AC completed with error(s) */
+ A_UINT32 be_basic_trigger_errors_per_ac[HTT_NUM_AC_WMM];
+ /** 11BE EHT MU-BAR Trigger frames per AC */
+ A_UINT32 be_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM];
+ /** 11BE EHT MU-BAR Trigger frames per AC completed with error(s) */
+ A_UINT32 be_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM];
} htt_tx_selfgen_be_stats_tlv;
typedef struct { /* DEPRECATED */
@@ -5621,6 +5707,12 @@ typedef struct {
* response to basic trigger. Typically a data response is expected.
*/
A_UINT32 be_ul_ofdma_basic_trigger_rx_qos_null_only;
+
+ /* UL MLO Queue Depth Sharing Stats */
+ A_UINT32 ul_mlo_send_qdepth_params_count;
+ A_UINT32 ul_mlo_proc_qdepth_params_count;
+ A_UINT32 ul_mlo_proc_accepted_qdepth_params_count;
+ A_UINT32 ul_mlo_proc_discarded_qdepth_params_count;
} htt_rx_pdev_be_ul_trigger_stats_tlv;
/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS
@@ -6221,6 +6313,7 @@ typedef struct {
A_UINT32 med_rx_idle_usec;
A_UINT32 med_tx_idle_global_usec;
A_UINT32 cca_obss_usec;
+ A_UINT32 pre_rx_frame_usec;
} htt_pdev_stats_cca_counters_tlv;
/* NOTE: THIS htt_pdev_cca_stats_hist_tlv STRUCTURE IS DEPRECATED,
@@ -6496,12 +6589,15 @@ typedef enum {
} htt_txbf_sound_steer_modes;
typedef enum {
- HTT_TX_AC_SOUNDING_MODE = 0,
- HTT_TX_AX_SOUNDING_MODE = 1,
- HTT_TX_BE_SOUNDING_MODE = 2,
+ HTT_TX_AC_SOUNDING_MODE = 0,
+ HTT_TX_AX_SOUNDING_MODE = 1,
+ HTT_TX_BE_SOUNDING_MODE = 2,
HTT_TX_CMN_SOUNDING_MODE = 3,
+ HTT_TX_CV_CORR_MODE = 4,
} htt_stats_sounding_tx_mode;
+#define HTT_TX_CV_CORR_MAX_NUM_COLUMNS 8
+
typedef struct {
htt_tlv_hdr_t tlv_hdr;
A_UINT32 tx_sounding_mode; /* HTT_TX_XX_SOUNDING_MODE */
@@ -6614,6 +6710,65 @@ typedef struct {
A_UINT32 adaptive_snd_kicked_in;
/** Total number of times we switched back to normal sounding interval */
A_UINT32 adaptive_snd_back_to_default;
+
+ /**
+ * Below are CV correlation feature related stats.
+ * This feature is used for DL MU MIMO, but is not available
+ * from certain legacy targets.
+ */
+
+ /** number of CV Correlation triggers for online mode */
+ A_UINT32 cv_corr_trigger_online_mode;
+ /** number of CV Correlation triggers for offline mode */
+ A_UINT32 cv_corr_trigger_offline_mode;
+ /** number of CV Correlation triggers for hybrid mode */
+ A_UINT32 cv_corr_trigger_hybrid_mode;
+ /** number of CV Correlation triggers with computation level 0 */
+ A_UINT32 cv_corr_trigger_computation_level_0;
+ /** number of CV Correlation triggers with computation level 1 */
+ A_UINT32 cv_corr_trigger_computation_level_1;
+ /** number of CV Correlation triggers with computation level 2 */
+ A_UINT32 cv_corr_trigger_computation_level_2;
+ /** number of users for which CV Correlation was triggered */
+ A_UINT32 cv_corr_trigger_num_users[HTT_TX_CV_CORR_MAX_NUM_COLUMNS];
+ /** number of streams for which CV Correlation was triggered */
+ A_UINT32 cv_corr_trigger_num_streams[HTT_TX_CV_CORR_MAX_NUM_COLUMNS];
+ /** number of CV Correlation buffers received through IPC tickle */
+ A_UINT32 cv_corr_upload_total_buf_received;
+ /** number of CV Correlation buffers fed back to the IPC ring */
+ A_UINT32 cv_corr_upload_total_buf_fed_back;
+ /** number of CV Correlation buffers for which processing failed */
+ A_UINT32 cv_corr_upload_total_processing_failed;
+ /**
+ * number of CV Correlation buffers for which processing failed,
+ * due to no users being present in parsed buffer
+ */
+ A_UINT32 cv_corr_upload_failed_total_users_zero;
+ /**
+ * number of CV Correlation buffers for which processing failed,
+ * due to number of users present in parsed buffer exceeded
+ * CV_CORR_MAX_NUM_COLUMNS
+ */
+ A_UINT32 cv_corr_upload_failed_total_users_exceeded;
+ /**
+ * number of CV Correlation buffers for which processing failed,
+ * due to peer pointer for parsed peer not available
+ */
+ A_UINT32 cv_corr_upload_failed_peer_not_found;
+ /**
+ * number of CV Correlation buffers for which processing encountered,
+ * Nss of peer exceeding SCHED_ALGO_MAX_SUPPORTED_MUMIMO_NSS
+ */
+ A_UINT32 cv_corr_upload_user_nss_exceeded;
+ /**
+ * number of CV Correlation buffers for which processing encountered,
+ * invalid reverse look up index for fetching CV correlation results
+ */
+ A_UINT32 cv_corr_upload_invalid_lookup_index;
+ /** number of users present in uploaded CV Correlation results buffer */
+ A_UINT32 cv_corr_upload_total_num_users[HTT_TX_CV_CORR_MAX_NUM_COLUMNS];
+ /** number of streams present in uploaded CV Correlation results buffer */
+ A_UINT32 cv_corr_upload_total_num_streams[HTT_TX_CV_CORR_MAX_NUM_COLUMNS];
} htt_tx_sounding_stats_tlv;
/* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SOUNDING_INFO
@@ -7814,6 +7969,58 @@ typedef struct {
/* Considering 320 MHz maximum 16 power levels */
#define HTT_MAX_CH_PWR_INFO_SIZE 16
+#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_M 0x000000ff
+#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_S 0
+
+#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_GET(_var) \
+ (((_var) & HTT_PHY_TPC_STATS_CTL_REGION_GRP_M) >> \
+ HTT_PHY_TPC_STATS_CTL_REGION_GRP_S)
+#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_REGION_GRP, _val); \
+ ((_var) &= ~(HTT_PHY_TPC_STATS_CTL_REGION_GRP_M)); \
+ ((_var) |= ((_val) << HTT_PHY_TPC_STATS_CTL_REGION_GRP_S)); \
+ } while (0)
+
+#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M 0x0000ff00
+#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S 8
+
+#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_GET(_var) \
+ (((_var) & HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M) >> \
+ HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S)
+#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_SUB_BAND_INDEX, _val); \
+ ((_var) &= ~(HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M)); \
+ ((_var) |= ((_val) << HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S)); \
+ } while (0)
+
+#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M 0x00ff0000
+#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S 16
+
+#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_GET(_var) \
+ (((_var) & HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M) >> \
+ HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S)
+#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED, _val); \
+ ((_var) &= ~(HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M)); \
+ ((_var) |= ((_val) << HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S)); \
+ } while (0)
+
+#define HTT_PHY_TPC_STATS_CTL_FLAG_M 0xff000000
+#define HTT_PHY_TPC_STATS_CTL_FLAG_S 24
+
+#define HTT_PHY_TPC_STATS_CTL_FLAG_GET(_var) \
+ (((_var) & HTT_PHY_TPC_STATS_CTL_FLAG_M) >> \
+ HTT_PHY_TPC_STATS_CTL_FLAG_S)
+#define HTT_PHY_TPC_STATS_CTL_FLAG_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_FLAG, _val); \
+ ((_var) &= ~(HTT_PHY_TPC_STATS_CTL_FLAG_M)); \
+ ((_var) |= ((_val) << HTT_PHY_TPC_STATS_CTL_FLAG_S)); \
+ } while (0)
+
typedef struct {
htt_tlv_hdr_t tlv_hdr;
@@ -7852,6 +8059,33 @@ typedef struct {
/** sub-band channels and corresponding Tx-power */
A_UINT32 sub_band_cfreq[HTT_MAX_CH_PWR_INFO_SIZE];
A_UINT32 sub_band_txpower[HTT_MAX_CH_PWR_INFO_SIZE];
+
+ /** array_gain_cap:
+ * CTL Array Gain cap, units are dB
+ * The lower-triangular portion of this square matrix is stored, i.e.
+ * array element 0 stores matrix element (0,0)
+ * array element 1 stores matrix element (1,0)
+ * array element 2 stores matrix element (1,1)
+ * array element 3 stores matrix element (2,0)
+ * ...
+ * array element 35 stores matrix element (7,7)
+ */
+ A_INT32 array_gain_cap[HTT_STATS_MAX_CHAINS * ((HTT_STATS_MAX_CHAINS/2)+1)];
+ union {
+ struct {
+ A_UINT32
+ ctl_region_grp:8, /** Group to which the ctl region belongs */
+ sub_band_index:8, /** Frequency subband index */
+ /** Array Gain Cap Ext2 feature enablement status */
+ array_gain_cap_ext2_enabled:8,
+ /** ctl_flag:
+ * 1st bit ULOFDMA supported
+ * 2nd bit DLOFDMA shared Exception supported
+ */
+ ctl_flag:8;
+ };
+ A_UINT32 ctl_args;
+ };
} htt_phy_tpc_stats_tlv;
/* NOTE:
@@ -8714,6 +8948,18 @@ typedef struct _htt_odd_mandatory_muofdma_pdev_stats_tlv {
((_var) |= ((_val) << HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_S)); \
} while (0)
+typedef enum {
+ HTT_STATS_SCHED_OFDMA_TXBF = 0, /* 0 */
+ HTT_STATS_SCHED_OFDMA_TXBF_IS_SANITY_FAILED, /* 1 */
+ HTT_STATS_SCHED_OFDMA_TXBF_IS_EBF_ALLOWED_FAILIED, /* 2 */
+ HTT_STATS_SCHED_OFDMA_TXBF_RU_ALLOC_BW_DROP_COUNT, /* 3 */
+ HTT_STATS_SCHED_OFDMA_TXBF_INVALID_CV_QUERY_COUNT, /* 4 */
+ HTT_STATS_SCHED_OFDMA_TXBF_AVG_TXTIME_LESS_THAN_TXBF_SND_THERHOLD, /* 5 */
+ HTT_STATS_SCHED_OFDMA_TXBF_IS_CANDIDATE_KICKED_OUT, /* 6 */
+ HTT_STATS_SCHED_OFDMA_TXBF_CV_IMAGE_BUF_INVALID, /* 7 */
+ HTT_STATS_SCHED_OFDMA_TXBF_INELIGIBILITY_MAX,
+} htt_stats_sched_ofdma_txbf_ineligibility_t;
+
typedef struct {
htt_tlv_hdr_t tlv_hdr;
/**
@@ -8756,6 +9002,7 @@ typedef struct {
A_UINT32 dlofdma_disabled_consec_no_mpdus_tried[HTT_NUM_AC_WMM];
/** Num of instances where dl ofdma is disabled because there are consecutive mpdu failure */
A_UINT32 dlofdma_disabled_consec_no_mpdus_success[HTT_NUM_AC_WMM];
+ A_UINT32 txbf_ofdma_ineligibility_stat[HTT_STATS_SCHED_OFDMA_TXBF_INELIGIBILITY_MAX];
} htt_pdev_sched_algo_ofdma_stats_tlv;
typedef struct {
@@ -9647,4 +9894,129 @@ typedef struct {
};
} htt_codel_msduq_stats_tlv;
+/*===================== start MLO stats ====================*/
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ A_UINT32 pref_link_num_sec_link_sched;
+ A_UINT32 pref_link_num_pref_link_timeout;
+ A_UINT32 pref_link_num_pref_link_sch_delay_ipc;
+ A_UINT32 pref_link_num_pref_link_timeout_ipc;
+} htt_mlo_sched_stats_tlv;
+
+/* STATS_TYPE : HTT_DBG_MLO_SCHED_STATS
+ * TLV_TAGS:
+ * - HTT_STATS_MLO_SCHED_STATS_TAG
+ */
+/* NOTE:
+ * This structure is for documentation, and cannot be safely used directly.
+ * Instead, use the constituent TLV structures to fill/parse.
+ */
+typedef struct _htt_mlo_sched_stats {
+ htt_mlo_sched_stats_tlv preferred_link_stats;
+} htt_mlo_sched_stats_t;
+
+#define HTT_STATS_HWMLO_MAX_LINKS 6
+#define HTT_STATS_MLO_MAX_IPC_RINGS 7
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ A_UINT32 mlo_ipc_ring_full_cnt[HTT_STATS_HWMLO_MAX_LINKS][HTT_STATS_MLO_MAX_IPC_RINGS];
+} htt_pdev_mlo_ipc_stats_tlv;
+
+/* STATS_TYPE : HTT_DBG_MLO_IPC_STATS
+ * TLV_TAGS:
+ * - HTT_STATS_PDEV_MLO_IPC_STATS_TAG
+ */
+/* NOTE:
+ * This structure is for documentation, and cannot be safely used directly.
+ * Instead, use the constituent TLV structures to fill/parse.
+ */
+typedef struct _htt_mlo_ipc_stats {
+ htt_pdev_mlo_ipc_stats_tlv mlo_ipc_stats;
+} htt_pdev_mlo_ipc_stats_t;
+
+/*===================== end MLO stats ======================*/
+
+typedef enum {
+ HTT_CTRL_PATH_STATS_CAL_TYPE_ADC = 0x0,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_DAC = 0x1,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_PROCESS = 0x2,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR = 0x3,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO = 0x4,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ = 0x5,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_TXLO = 0x6,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_TXIQ = 0x7,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_RXIQ = 0x8,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_IM2 = 0x9,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_LNA = 0xa,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO = 0xb,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ = 0xc,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS = 0xd,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY = 0xe,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_IBF = 0xf,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL = 0x10,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ = 0x11,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM = 0x12,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL = 0x13,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ = 0x14,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_BWFILTER = 0x15,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_PEF = 0x16,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP = 0x17,
+ HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC = 0x18,
+
+ /* add new cal types above this line */
+ HTT_CTRL_PATH_STATS_CAL_TYPE_INVALID = 0xFF
+} htt_ctrl_path_stats_cal_type_ids;
+
+#define HTT_RETURN_STRING(str) case ((str)): return (A_UINT8 *)(# str);
+
+#define HTT_GET_BITS(_val, _index, _num_bits) \
+ (((_val) >> (_index)) & ((1 << (_num_bits)) - 1))
+
+#define HTT_CTRL_PATH_CALIBRATION_STATS_CAL_TYPE_GET(cal_info) \
+ HTT_GET_BITS(cal_info, 0, 8)
+
+/*
+ * Used by some hosts to print names of cal type, based on
+ * htt_ctrl_path_cal_type_ids values specified in
+ * htt_ctrl_path_calibration_stats_struct in ctrl_path_stats event msg.
+ */
+#ifdef HTT_CTRL_PATH_STATS_CAL_TYPE_STRINGS
+static INLINE A_UINT8 *htt_ctrl_path_cal_type_id_to_name(A_UINT32 cal_type_id)
+{
+ switch (cal_type_id)
+ {
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_ADC);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DAC);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PROCESS);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TXLO);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TXIQ);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXIQ);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_IM2);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_LNA);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_IBF);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_BWFILTER);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PEF);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP);
+ HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC);
+ }
+
+ return (A_UINT8 *) "HTT_CTRL_PATH_STATS_CAL_TYPE_UNKNOWN";
+}
+#endif /* HTT_CTRL_PATH_STATS_CAL_TYPE_STRINGS */
+
+
#endif /* __HTT_STATS_H__ */
diff --git a/drivers/staging/fw-api/fw/wmi_services.h b/drivers/staging/fw-api/fw/wmi_services.h
index 016c7c25e08afcba74cb02696c14e935e0ca1397..53be26388e6fddf2d000dff0eea1faf373077abe 100644
--- a/drivers/staging/fw-api/fw/wmi_services.h
+++ b/drivers/staging/fw-api/fw/wmi_services.h
@@ -634,6 +634,14 @@ typedef enum {
WMI_SERVICE_N_LINK_MLO_SUPPORT = 381, /* Indicate FW supports N MLO link & vdev re-purpose between links */
WMI_SERVICE_ATF_MAX_CLIENT_512_SUPPORT = 382, /* Indicates FW supports maximum of 512 clients when ATF is enabled */
WMI_SERVICE_FISA_DYNAMIC_MSDU_AGGR_SIZE_SUPPORT = 383, /* Indicates FW support for FISA aggregation size up to 64 instead of only 16 */
+ WMI_SERVICE_BRIDGE_VDEV_SUPPORT = 384, /* Indicated FW supports Bridge VDEV */
+ WMI_SERVICE_MLO_MODE1_RECOVERY_SUPPORTED = 385, /* Indicate fw support for mlo mode1 recovery */
+ WMI_SERVICE_TX_PWR_PER_PPDU_STATS_SUPPORT = 386, /* FW support to check tx power stats per PPDU */
+ WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT = 387, /* Indicate FW support to disable wds peer map/unmap events */
+ WMI_SERVICE_PDEV_WSI_STATS_INFO_SUPPORT = 388, /* Support for WSI Stats Info. */
+ WMI_SERVICE_MULTIPLE_RF_PATH_SOC_SUPPORT = 389, /* Indicates FW supports Multiple RF Path on SOC Level */
+ WMI_SERVICE_RADAR_FLAGS_SUPPORT = 390, /* Indicates FW supports radar flags, such as full bandwidth need put to NOL */
+ WMI_SERVICE_XPAN_SUPPORT = 391, /* Indicate FW support XPAN configuration */
WMI_MAX_EXT2_SERVICE
diff --git a/drivers/staging/fw-api/fw/wmi_tlv_defs.h b/drivers/staging/fw-api/fw/wmi_tlv_defs.h
index 624b8449afe213e4afe4b9c78be7b462dff6ab28..21ca4d8b1cb197cfc329bc51e89c97062b2ce6a3 100644
--- a/drivers/staging/fw-api/fw/wmi_tlv_defs.h
+++ b/drivers/staging/fw-api/fw/wmi_tlv_defs.h
@@ -1392,6 +1392,17 @@ typedef enum {
WMITLV_TAG_STRUC_wmi_aux_dev_capabilities,
WMITLV_TAG_STRUC_wmi_nan_oem_data_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_nan_oem_data_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param,
+ WMITLV_TAG_STRUC_wmi_enhanced_aoa_gain_phase_data_hdr,
+ WMITLV_TAG_STRUC_wmi_ctrl_path_sta_rrm_stats_struct,
+ WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_enhanced_aoa_caps_param,
+ WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param,
+ WMITLV_TAG_STRUC_WMI_RADAR_FLAGS,
+ WMITLV_TAG_STRUC_wmi_dma_buf_release_cqi_upload_meta_data,
+ WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param,
+ WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_req_evt_fixed_param,
+ WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_trigger_reason_tlv_param,
} WMITLV_TAG_ID;
/*
* IMPORTANT: Please add _ALL_ WMI Commands Here.
@@ -1926,6 +1937,8 @@ typedef enum {
OP(WMI_MLO_LINK_SET_BSS_PARAMS_CMDID) \
OP(WMI_MLO_LINK_SWITCH_CONF_CMDID) \
OP(WMI_NAN_OEM_DATA_CMDID) \
+ OP(WMI_PDEV_WSI_STATS_INFO_CMDID) \
+ OP(WMI_CSA_EVENT_STATUS_INDICATION_CMDID) \
/* add new CMD_LIST elements above this line */
@@ -2241,6 +2254,8 @@ typedef enum {
OP(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID) \
OP(WMI_MLO_LINK_SWITCH_REQUEST_EVENTID) \
OP(WMI_NAN_OEM_DATA_EVENTID) \
+ OP(WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID) \
+ OP(WMI_MLO_LINK_STATE_SWITCH_EVENTID) \
/* add new EVT_LIST elements above this line */
@@ -5449,9 +5464,23 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_BSS_PARAMS_CMDID);
/* MLO link switch confirmation command to inform FW about host side status and reason code */
#define WMITLV_TABLE_WMI_MLO_LINK_SWITCH_CONF_CMDID(id,op,buf,len) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_cnf_fixed_param, wmi_mlo_link_switch_cnf_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_cnf_fixed_param, wmi_mlo_link_switch_cnf_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_set_active_cmd_fixed_param, set_link_params, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_set_active_link_number_param, link_number_param, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ieee_link_id_bitmap, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ieee_link_id_bitmap2, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SWITCH_CONF_CMDID);
+/* WMI CMD used to send WSI stats info. */
+#define WMITLV_TABLE_WMI_PDEV_WSI_STATS_INFO_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param, wmi_pdev_wsi_stats_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_WSI_STATS_INFO_CMDID);
+
+/* CSA status indication command to inform FW about host accepting or rejecting csa event*/
+#define WMITLV_TABLE_WMI_CSA_EVENT_STATUS_INDICATION_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param , wmi_csa_event_status_ind_fixed_param,fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_CSA_EVENT_STATUS_INDICATION_CMDID);
+
/************************** TLV definitions of WMI events *******************************/
@@ -5508,7 +5537,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_sw_cal_ver_cap, sw_cal_ver_cap, WMITLV_SIZE_VAR) \
WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_INT32, A_INT32, hw_tx_power_signed, WMITLV_SIZE_FIX, WMI_HW_TX_POWER_CAPS_MAX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_COEX_FIX_CHANNEL_CAPABILITIES, coex_fix_channel_caps, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_aux_dev_capabilities, aux_dev_caps, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_aux_dev_capabilities, aux_dev_caps, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_caps_param, aoa_caps_param, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_per_band_caps_param, aoa_per_band_caps_param, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID);
#define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \
@@ -5725,7 +5756,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STA_KICKOUT_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bpcc_bufp, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_is_my_mgmt_frame, my_frame, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_removal_tbtt_count, link_removal_tbtt_count, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_bcast_t2lm_info, mlo_bcast_t2lm_info, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_bcast_t2lm_info, mlo_bcast_t2lm_info, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_RX_EVENTID);
/* Management Rx FW Consumed Event */
@@ -6239,7 +6271,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_OPER_MODE_CHANGE_EVENTID);
WMITLV_CREATE_PARAM_STRUC(WMI_DFS_RADAR_EVENTID);
#define WMITLV_TABLE_WMI_PDEV_DFS_RADAR_DETECTION_EVENTID(id,op,buf,len) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_radar_detection_event_fixed_param, wmi_pdev_dfs_radar_detection_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_radar_detection_event_fixed_param, wmi_pdev_dfs_radar_detection_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_RADAR_FLAGS, radar_flags, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DFS_RADAR_DETECTION_EVENTID);
#define WMITLV_TABLE_WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID(id,op,buf,len) \
@@ -6916,7 +6949,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_t2lm_stats_struct, ctrl_path_t2lm_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_blanking_stats_struct, ctrl_path_blanking_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_peer_stats_struct, ctrl_path_peer_stats, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_vdev_stats_struct, ctrl_path_vdev_stats, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_vdev_stats_struct, ctrl_path_vdev_stats, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_sta_rrm_stats_struct, ctrl_path_sta_rrm_stats, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID);
/*
@@ -6992,7 +7026,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_CFG_RSP_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dma_buf_release_fixed_param, wmi_dma_buf_release_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_entry, entries, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_spectral_meta_data, meta_data, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cv_upload_meta_data, cv_meta_data, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cv_upload_meta_data, cv_meta_data, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cqi_upload_meta_data, cqi_meta_data, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID);
/* ctl failsafe check event */
@@ -7224,7 +7259,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_TWT_SESSION_STATS_EVENTID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_active_vdev_bitmap, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_inactive_vdev_bitmap, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_active_ieee_link_id_bitmap, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_inactive_ieee_link_id_bitmap, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_inactive_ieee_link_id_bitmap, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, current_active_ieee_link_id_bitmap, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, current_inactive_ieee_link_id_bitmap, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_ACTIVE_RESP_EVENTID);
/* Get DPD status Event */
@@ -7431,6 +7468,22 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID);
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_primary_link_peer_migration_status, primary_link_peer_migration_status, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID);
+/*
+ * Update AOA Phase delta values for all gain tables event
+ * Below definition shows TLV packing of AOA Phase delta values for all gain tables event
+ */
+#define WMITLV_TABLE_WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID(id, op, buf, len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param, wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_gain_phase_data_hdr, aoa_data_hdr, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, aoa_data_buf, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID);
+
+/* MLO Link State Switch Event */
+#define WMITLV_TABLE_WMI_MLO_LINK_STATE_SWITCH_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_req_evt_fixed_param, wmi_mlo_link_state_switch_req_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_state_switch_trigger_reason, switch_trigger_reason, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_STATE_SWITCH_EVENTID);
+
#ifdef __cplusplus
}
diff --git a/drivers/staging/fw-api/fw/wmi_unified.h b/drivers/staging/fw-api/fw/wmi_unified.h
index 781425119ca2fdaffbbd226f2c0bd313ecc7cb9a..65610e75108eab0808537da8b7c2871ad0dd0ca2 100644
--- a/drivers/staging/fw-api/fw/wmi_unified.h
+++ b/drivers/staging/fw-api/fw/wmi_unified.h
@@ -98,6 +98,8 @@ extern "C" {
#define WMI_MAX_PN_LEN 8
+#define MAX_NUM_CQI_USERS_IN_STANDALONE_SND 3
+
/*
* These don't necessarily belong here; but as the MS/SM macros require
* ar6000_internal.h to be included, it may not be defined as yet.
@@ -512,6 +514,8 @@ typedef enum {
WMI_PDEV_SET_TGTR2P_TABLE_CMDID,
/* WMI cmd to set RF path for PHY */
WMI_PDEV_SET_RF_PATH_CMDID,
+ /** WSI stats info WMI command */
+ WMI_PDEV_WSI_STATS_INFO_CMDID,
/* VDEV (virtual device) specific commands */
@@ -623,6 +627,10 @@ typedef enum {
/** pause vdev's Tx, Rx, or both for a specific duration */
WMI_VDEV_PAUSE_CMDID,
+ /** WMI Command to set status of CSA event from HOST */
+ WMI_CSA_EVENT_STATUS_INDICATION_CMDID,
+
+
/* peer specific commands */
/** create a peer */
@@ -1748,6 +1756,8 @@ typedef enum {
/* Event to indicate completion on RF path */
WMI_PDEV_SET_RF_PATH_RESP_EVENTID,
+ /* Event to get AOA phasedelta values for all gain tables from HALPHY */
+ WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID,
/* VDEV specific events */
/** VDEV started event in response to VDEV_START request */
@@ -2408,6 +2418,8 @@ typedef enum {
WMI_MLO_LINK_SWITCH_REQUEST_EVENTID,
/** Response event for WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID */
WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID,
+ /** WMI Event to spcify reason for link state switch */
+ WMI_MLO_LINK_STATE_SWITCH_EVENTID,
/* WMI event specific to Quiet handling */
WMI_QUIET_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_QUIET_OFL),
@@ -4478,8 +4490,17 @@ typedef struct {
* 0 - Primary
* 1 - Secondary
* Refer to WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_GET/SET macros.
+ * Bit 18 - disable_wds_peer_map_unmap_event
+ * Flag to indicate whether the WDS peer map/unmap event should be
+ * processed or ignored.
+ * 0 - leave the WDS peer map/unmap event enabled
+ * 1 - disable the WDS peer map/unmap event
+ * This flag shall only be set if the target has set the
+ * WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT flag.
+ * Refer to WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_GET
+ * and _SET macros.
*
- * Bits 31:18 - Reserved
+ * Bits 31:19 - Reserved
*/
A_UINT32 flags2;
/** @brief host_service_flags - can be used by Host to indicate
@@ -4578,7 +4599,15 @@ typedef struct {
* Refer to the below definitions of the
* WMI_RSRC_CFG_HOST_SERVICE_FLAG_BANG_RADAR_320M_SUPPORT_GET
* and _SET macros.
- * Bits 31:14 - Reserved
+ * Bit 14
+ * This bit will be set when host wants to enable/disable
+ * full BW NOL feature.
+ * When set to 1: Enable full BW NOL feature.
+ * When set to 0: Disable the full BW NOL feature.
+ * Refer to the below definitions of the
+ * WMI_RSRC_CFG_HOST_SERVICE_FLAG_RADAR_FLAGS_FULL_BW_NOL_GET
+ * and _SET macros.
+ * Bits 31:15 - Reserved
*/
A_UINT32 host_service_flags;
@@ -4945,6 +4974,11 @@ typedef struct {
#define WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_SET(flags2, value) \
WMI_SET_BITS(flags2, 17, 1, value)
+#define WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_GET(flags2) \
+ WMI_GET_BITS(flags2, 18, 1)
+#define WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SET(flags2, value) \
+ WMI_SET_BITS(flags2, 18, 1, value)
+
#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET(host_service_flags) \
WMI_GET_BITS(host_service_flags, 0, 1)
@@ -5016,6 +5050,11 @@ typedef struct {
#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_BANG_RADAR_320M_SUPPORT_SET(host_service_flags, val) \
WMI_SET_BITS(host_service_flags, 13, 1, val)
+#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_RADAR_FLAGS_FULL_BW_NOL_GET(host_service_flags) \
+ WMI_GET_BITS(host_service_flags, 14, 1)
+#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_RADAR_FLAGS_FULL_BW_NOL_SET(host_service_flags, val) \
+ WMI_SET_BITS(host_service_flags, 14, 1, val)
+
#define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_GET(carrier_config) \
WMI_GET_BITS(carrier_config, 0, 1)
@@ -5576,6 +5615,9 @@ typedef struct {
/* NOTE: This constant cannot be changed without breaking WMI compatibility */
#define WMI_IE_BITMAP_SIZE 8
+#define WMI_SCAN_MLD_PARAM_MLD_ID_GET(mld_param) WMI_GET_BITS(mld_param, 0, 8)
+#define WMI_SCAN_MLD_PARAM_MLD_ID_SET(mld_param, val) WMI_SET_BITS(mld_param, 0, 8, val)
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_start_scan_cmd_fixed_param */
/** Scan ID (lower 16 bits) MSB 4 bits is used to identify scan client based on enum WMI_SCAN_CLIENT_ID */
@@ -5667,6 +5709,11 @@ typedef struct {
* dwell time in msec for 6 GHz channel of spectral scan channel list
*/
A_UINT32 dwell_time_spectral_ch;
+ /**
+ * B0-B7: mld id to be inserted in ML probe request
+ * B8-B31: reserved
+ */
+ A_UINT32 mld_parameter;
/**
* TLV (tag length value) parameters follow the scan_cmd
@@ -9241,6 +9288,30 @@ typedef enum {
* units are microseconds
*/
WMI_PDEV_PARAM_SLOT_TIME,
+
+ /** VO dedicated time -
+ * allocate dedicated time slots for VO access category across all
+ * ATF groups in a pdev.
+ * Note :
+ * 1. Per AC airtime per group is already available through
+ * ATF WMM WMI commands
+ * 2. The dedicated time slot is applicable per second
+ * 3. Units are in milli-seconds
+ */
+ WMI_PDEV_PARAM_ATF_VO_DEDICATED_TIME,
+
+ /** VI dedicated time -
+ * allocate dedicated time slots for VI access category across all
+ * ATF groups in a pdev.
+ * Note :
+ * 1. Per AC airtime per group is already given through ATF WMM WMI cmds
+ * 2. The dedicated time slot is applicable per second
+ * 3. Units are in milli-seconds
+ */
+ WMI_PDEV_PARAM_ATF_VI_DEDICATED_TIME,
+
+ /** Parameter used for enabling/disabling RFA toggle for SAP mode */
+ WMI_PDEV_PARAM_SET_SAP_RFA_TOGGLE,
} WMI_PDEV_PARAM;
#define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
@@ -10535,20 +10606,6 @@ typedef enum {
WMI_CHAN_WIDTH_MAX,
} wmi_channel_width;
-/* channel width switch type */
-typedef enum {
- WMI_CHAN_WIDTH_SWITCH_TYPE_TXRX = 0,
- WMI_CHAN_WIDTH_SWITCH_TYPE_TXONLY = 1,
-
- WMI_CHAN_WIDTH_SWITCH_TYPE_MAX,
-} wmi_chan_width_switch_type;
-
-#define WMI_VDEV_CHAN_WIDTH_NOTIFY_GET_CHAN_WIDTH(chwidth_notify) WMI_GET_BITS(chwidth_notify, 0, 8)
-#define WMI_VDEV_CHAN_WIDTH_NOTIFY_SET_CHAN_WIDTH(chwidth_notify, value) WMI_SET_BITS(chwidth_notify, 0, 8, value)
-
-#define WMI_VDEV_CHAN_WIDTH_NOTIFY_GET_SWITCH_TYPE(chwidth_notify) WMI_GET_BITS(chwidth_notify, 8, 2)
-#define WMI_VDEV_CHAN_WIDTH_NOTIFY_SET_SWITCH_TYPE(chwidth_notify, value) WMI_SET_BITS(chwidth_notify, 8, 2, value)
-
/* Clear stats */
typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_clear_link_stats_cmd_fixed_param */
@@ -15675,6 +15732,18 @@ typedef struct {
#define WMI_VDEV_STATS_IS_MULTI_GROUP_KEY_ENABLED_GET(flag) \
WMI_GET_BITS(flag, 31, 1)
+typedef struct {
+ /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_sta_rrm_stats_struct */
+ A_UINT32 tlv_header;
+ A_UINT32 dot11GroupTransmittedFrameCount;
+ A_UINT32 dot11GroupReceivedFrameCount;
+ A_UINT32 dot11TransmittedFrameCount;
+ A_UINT32 dot11AckFailureCount;
+ A_UINT32 dot11FailedCount;
+ A_UINT32 dot11FCSErrorCount;
+ A_UINT32 dot11RTSSuccessCount;
+ A_UINT32 dot11RTSFailureCount;
+} wmi_ctrl_path_sta_rrm_stats_struct;
/**
* peer statistics.
@@ -16168,6 +16237,12 @@ typedef enum {
* If SW encryption is enabled, key plumbing will not happen in FW.
*/
#define WMI_UNIFIED_VDEV_START_HW_ENCRYPTION_DISABLED (1<<4)
+/** Indicates VAP is used for MLO repurpose.
+ * This Indicates that vap can be brought up as 11ax or 11be and can be
+ * repurposed based on the above stack on the fly to change from MLO to
+ * non MLO, currently we support only 11ax and 11be transition.
+ */
+#define WMI_UNIFIED_VDEV_START_MLO_REPURPOSE_VAP (1<<5)
/* BSS color 0-6 */
#define WMI_HEOPS_COLOR_GET_D2(he_ops) WMI_GET_BITS(he_ops, 0, 6)
@@ -18058,11 +18133,7 @@ typedef enum {
* Please note incase of STA VDEV only BSS peer gets updated,
* associated TDLS peer bandwidth won't be impacted.
*
- * bit 7:0 the updated bandwidth is specified with
- * a wmi_channel_width value
- * bit 9:8 the updated bandwidth switch type is specified with
- * a wmi_chan_width_switch_type value
- * bit 31:10 reserved
+ * The updated bandwidth is specified with a wmi_channel_width value.
*/
WMI_VDEV_PARAM_CHWIDTH_WITH_NOTIFY, /* 0xBA */
@@ -18084,6 +18155,18 @@ typedef enum {
*/
WMI_VDEV_PARAM_RTT_11AZ_TB_MAX_SESSION_EXPIRY, /* 0xBD */
+ /*
+ * WiFi Standard version to be supported.
+ * Value is from enum WMI_WIFI_STANDARD
+ */
+ WMI_VDEV_PARAM_WIFI_STANDARD_VERSION, /* 0xBE */
+
+ /*
+ * Allow to disable TWT on 2G channel
+ * if corresponding INI is set
+ */
+ WMI_VDEV_PARAM_DISABLE_2G_TWT, /* 0xBF */
+
/*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE ===
* The below vdev param types are used for prototyping, and are
@@ -19076,6 +19159,12 @@ enum wmi_sta_ps_param_uapsd {
WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7),
};
+enum wmi_sta_ps_scheme_cfg {
+ WMI_STA_PS_OPM_CONSERVATIVE = 0,
+ WMI_STA_PS_OPM_AGGRESSIVE = 1,
+ WMI_STA_PS_USER_DEF = 2,
+};
+
enum wmi_sta_powersave_param {
/**
* Controls how frames are retrievd from AP while STA is sleeping
@@ -19121,9 +19210,10 @@ WMI_STA_PS_PARAM_UAPSD = 4,
WMI_STA_PS_PARAM_QPOWER_PSPOLL_COUNT = 5,
/**
- * Enable QPower
+ * Enable OPM
*/
WMI_STA_PS_ENABLE_QPOWER = 6,
+ WMI_STA_PS_ENABLE_OPM = WMI_STA_PS_ENABLE_QPOWER, /* alias */
/**
* Number of TX frames before the entering the Active state
@@ -19152,6 +19242,12 @@ WMI_STA_PS_PARAM_MAX_RESET_ITO_COUNT_ON_TIM_NO_TXRX = 10,
* in WOW
*/
WMI_STA_PS_PARAM_ENABLE_PS_OPT_IN_WOW = 11,
+
+/**
+ * Speculative interval in ms
+ */
+WMI_STA_PS_PARAM_SPEC_WAKE_INTERVAL = 12,
+
};
typedef struct {
@@ -20147,6 +20243,8 @@ typedef struct {
#define WMI_PEER_FT_ROAMING_PEER_UPDATE 0x29
+#define WMI_PEER_PARAM_DMS_SUPPORT 0x2A
+
typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param */
/** unique id identifying the VDEV, generated by the caller */
@@ -20468,6 +20566,9 @@ typedef struct {
A_UINT32 max_num_simultaneous_links;
/** NSTR indication bitmap received in assoc req */
A_UINT32 nstr_indication_bitmap;
+
+ /** max num of active links recommended by AP or applications */
+ A_UINT32 recommended_max_num_simultaneous_links;
} wmi_peer_assoc_mlo_params;
typedef struct {
@@ -23202,6 +23303,8 @@ typedef enum wake_reason_e {
WOW_REASON_XGAP,
/* COEX channel avoid event */
WOW_REASON_COEX_CHAVD,
+ /* vdev repurpose request event */
+ WOW_REASON_VDEV_REPURPOSE,
/* add new WOW_REASON_ defs before this line */
WOW_REASON_MAX,
@@ -24853,6 +24956,13 @@ typedef enum
*/
WMI_VENDOR_OUI_ACTION_ENABLE_CTS2SELF_WITH_QOS_NULL = 11,
+ /*
+ * Send SMPS frame following OMN frame on VHT conncection if specific
+ * vendor OUI received in beacon.
+ */
+ WMI_VENDOR_OUI_ACTION_SEND_SMPS_FRAME_WITH_OMN = 12,
+
+
/* Add any action before this line */
WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID
} wmi_vendor_oui_action_id;
@@ -25472,6 +25582,30 @@ typedef struct {
A_INT32 sidx; /* segment index (where was the radar within the channel) */
} wmi_pdev_dfs_radar_detection_event_fixed_param;
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_RADAR_FLAGS */
+ /*
+ * Bit 0:
+ * 0 - need check sub channel marking
+ * 1 - full bandwidth need put to NOL
+ * Refer to WMI_RADAR_FLAGS_FULL_BW_NOL_GET and _SET macros
+ * [1:31] reserved
+ */
+ A_UINT32 flags;
+} WMI_RADAR_FLAGS;
+
+#define WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS 0
+#define WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS 1
+
+#define WMI_RADAR_FLAGS_FULL_BW_NOL_GET(flag) \
+ WMI_GET_BITS(flag, \
+ WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \
+ WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS)
+#define WMI_RADAR_FLAGS_FULL_BW_NOL_SET(flag, val) \
+ WMI_GET_BITS(flag, \
+ WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \
+ WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS, val)
+
typedef enum {
OCAC_COMPLETE = 0,
OCAC_ABORT,
@@ -34409,6 +34543,22 @@ typedef enum wmi_coex_config_type {
* config BT RX PER threshold
*/
WMI_COEX_CONFIG_BT_RX_PER_THRESHOLD = 49,
+ /* WMI_COEX_SET_TRAFFIC_SHAPING_MODE
+ * arg1: 0 (WMI_COEX_TRAFFIC_SHAPING_MODE_DISABLED)
+ * Disable coex policies and set fixed arbitration config.
+ * 1 (WMI_COEX_TRAFFIC_SHAPING_MODE_ENABLED)
+ * Enable all coex policies.
+ */
+ WMI_COEX_SET_TRAFFIC_SHAPING_MODE = 50,
+ /* WMI_COEX_CONFIG_ENABLE_CONT_INFO
+ * enable contention info log
+ * arg1:
+ * 0: disable both cont/sched log
+ * 1: enable cont log
+ * 2: enable sched log
+ * 3: enable both cont and sched log
+ */
+ WMI_COEX_CONFIG_ENABLE_CONT_INFO = 51,
} WMI_COEX_CONFIG_TYPE;
typedef struct {
@@ -34429,6 +34579,11 @@ typedef enum wmi_coex_dbam_mode_type {
WMI_COEX_DBAM_FORCED = 2,
} WMI_COEX_DBAM_MODE_TYPE;
+typedef enum {
+ WMI_COEX_TRAFFIC_SHAPING_MODE_DISABLED = 0,
+ WMI_COEX_TRAFFIC_SHAPING_MODE_ENABLED = 1,
+} WMI_COEX_TRAFFIC_SHAPING_MODE;
+
typedef struct {
A_UINT32 tlv_header;
A_UINT32 vdev_id;
@@ -34624,6 +34779,7 @@ typedef enum {
WMI_REQUEST_CTRL_PATH_BLANKING_STAT = 15,
WMI_REQUEST_CTRL_PATH_PEER_STAT = 16,
WMI_REQUEST_CTRL_PATH_VDEV_DEBUG_STAT = 17,
+ WMI_REQUEST_CTRL_STA_RRM_STAT = 18,
} wmi_ctrl_path_stats_id;
typedef enum {
@@ -35719,10 +35875,22 @@ typedef struct {
**************************************************************************/
} WMI_OEM_DMA_RING_CAPABILITIES;
+typedef enum {
+ WMI_SAR_VERSION_0_ORIGINAL = 0x00,
+ WMI_SAR_VERSION_1_FULL_TABLE = 0x01,
+ WMI_SAR_VERSION_2_DBS_SAR = 0x02,
+ WMI_SAR_VERSION_3_SBS_SAR = 0x03,
+
+ WMI_SAR_VERSION_SMART_TX = 0x04,
+ WMI_SAR_VERSION_TAS = 0x05,
+
+ WMI_SAR_VERSION_INVALID = 0x80
+} wmi_sar_version_t;
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_SAR_CAPABILITIES*/
/* sar version in bdf */
- A_UINT32 active_version;
+ A_UINT32 active_version; /* contains a wmi_sar_version_t value */
/**************************************************************************
* DON'T ADD ANY FURTHER FIELDS HERE -
@@ -36748,6 +36916,8 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command)
WMI_RETURN_STRING(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID);
WMI_RETURN_STRING(WMI_MLO_LINK_RECOMMENDATION_CMDID);
WMI_RETURN_STRING(WMI_NAN_OEM_DATA_CMDID);
+ WMI_RETURN_STRING(WMI_PDEV_WSI_STATS_INFO_CMDID);
+ WMI_RETURN_STRING(WMI_CSA_EVENT_STATUS_INDICATION_CMDID);
}
return (A_UINT8 *) "Invalid WMI cmd";
@@ -38385,6 +38555,8 @@ typedef enum _WMI_ADD_TWT_STATUS_T {
WMI_ADD_TWT_STATUS_DIALOG_ID_BUSY, /* FW is in the process of handling this dialog */
WMI_ADD_TWT_STATUS_BTWT_NOT_ENBABLED, /* Broadcast TWT is not enabled */
WMI_ADD_TWT_STATUS_RTWT_NOT_ENBABLED, /* Restricted TWT is not enabled */
+ WMI_ADD_TWT_STATUS_LINK_SWITCH_IN_PROGRESS, /* Link switch is ongoing */
+ WMI_ADD_TWT_STATUS_UNSUPPORTED_MODE_MLMR, /* Unsupported in MLMR mode */
} WMI_ADD_TWT_STATUS_T;
typedef struct {
@@ -38773,6 +38945,8 @@ typedef struct {
* wmi_dma_buf_release_entry entries[num_buf_release_entry];
* wmi_dma_buf_release_spectral_meta_data meta_datat[num_meta_data_entry];
* wmi_dma_buf_release_cv_upload_meta_data cv_meta_data[num_meta_data_entry]
+ * wmi_dma_buf_release_cqi_upload_meta_data
+ * cqi_meta_data[num_meta_data_entry]
*/
} wmi_dma_buf_release_fixed_param;
@@ -39401,6 +39575,16 @@ typedef struct {
#define WMI_GET_BTCONNECT_STATUS(flags) WMI_GET_BITS(flags, 0, 1)
#define WMI_SET_BTCONNECT_STATUS(flags, val) WMI_SET_BITS(flags, 0, 1, val)
+#define WMI_GET_MLO_BAND(flags) WMI_GET_BITS(flags, 1, 3)
+#define WMI_SET_MLO_BAND(flags, val) WMI_SET_BITS(flags, 1, 3, val)
+
+typedef enum wmi_mlo_band_info {
+ WMI_MLO_BAND_NO_MLO = 0,
+ WMI_MLO_BAND_2GHZ_MLO,
+ WMI_MLO_BAND_5GHZ_MLO,
+ WMI_MLO_BAND_6GHZ_MLO,
+} wmi_mlo_band_info_t;
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_info_tlv_param */
/* roam_scan_type:
@@ -39424,7 +39608,10 @@ typedef struct {
/*
* Flags capturing factors involved during roam scan:
* Bit 0 : Bluetooth connect status, 0(not connected) or 1(connected).
- * Bit 1-31 : reserved for future use.
+ * Bit 1-3 : Indicates which link triggered roaming in MLD cases.
+ * The value is one of the wmi_mlo_band_info_t enum constants.
+ * Refer to WMI_[GET,SET]_MLO_BAND macros.
+ * Bit 4-31 : reserved for future use.
*/
A_UINT32 flags;
} wmi_roam_scan_info;
@@ -39439,6 +39626,9 @@ typedef struct {
*/
} wmi_roam_scan_channel_info;
+#define WMI_GET_AP_INFO_MLO_STATUS(flags) WMI_GET_BITS(flags, 0, 1)
+#define WMI_SET_AP_INFO_MLO_STATUS(flags, val) WMI_SET_BITS(flags, 0, 1, val)
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_ap_info_tlv_param */
/*
@@ -39474,6 +39664,12 @@ typedef struct {
A_UINT32 bl_timestamp;
/* Original timeout value in milli seconds when AP added to BL */
A_UINT32 bl_original_timeout;
+ /* flags:
+ * bit 0: MLD AP FLAG -> 1: MLD AP, 0: non-MLD AP
+ * Refer to WMI_[GET,SET]_AP_INFO_MLO_STATUS macros.
+ * bit 1-31: reserved.
+ */
+ A_UINT32 flags;
} wmi_roam_ap_info;
typedef enum {
@@ -39551,6 +39747,8 @@ typedef struct {
#define WMI_ROAM_NEIGHBOR_REPORT_INFO_RESPONSE_TOKEN_SET(detail,val) WMI_SET_BITS(detail, 8, 8, val)
#define WMI_ROAM_NEIGHBOR_REPORT_INFO_NUM_OF_NRIE_GET(detail) WMI_GET_BITS(detail, 16, 8)
#define WMI_ROAM_NEIGHBOR_REPORT_INFO_NUM_OF_NRIE_SET(detail,val) WMI_SET_BITS(detail, 16, 8, val)
+#define WMI_ROAM_NEIGHBOR_REPORT_INFO_MLO_BAND_INFO_GET(detail) WMI_GET_BITS(detail, 24, 3)
+#define WMI_ROAM_NEIGHBOR_REPORT_INFO_MLO_BAND_INFO_SET(detail,val) WMI_SET_BITS(detail, 24, 3, val)
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_neighbor_report_info_tlv_param */
@@ -39581,13 +39779,20 @@ typedef struct {
* [7:0] : neighbor report request token
* [15:8] : neighbor report response token
* [23:16] : the number of neighbor report elements in response frame
- * [31:24] : reserved
+ * [26:24] : band on which frame is sent; the value will be one of the
+ * wmi_mlo_band_info enum constants
+ * Refer to WMI_ROAM_NEIGHBOR_REPORT_INFO_MLO_BAND_INFO_GET,SET
+ * macros.
+ * [31:27] : reserved
* Refer to the above WMI_ROAM_NEIGHBOR_REPORT_INFO_*_GET,_SET macros for
* reading and writing these bitfields.
*/
A_UINT32 neighbor_report_detail;
} wmi_roam_neighbor_report_info;
+#define WMI_ROAM_BTM_RESP_MLO_BAND_INFO_GET(detail) WMI_GET_BITS(detail, 0, 3)
+#define WMI_ROAM_BTM_RESP_MLO_BAND_INFO_SET(detail,val) WMI_SET_BITS(detail, 0, 3, val)
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_btm_response_info_tlv_param */
@@ -39621,6 +39826,13 @@ typedef struct {
* that the responding STA requests the BSS to delay termination.
*/
A_UINT32 btm_resp_bss_termination_delay;
+ /* info:
+ * Bit[0:2] - band on which frame is sent, band value will be one of the
+ * wmi_mlo_band_info_t enum constants
+ * Refer to WMI_ROAM_BTM_RESP_MLO_BAND_INFO_GET,SET macros.
+ * Bit[3:31] - reserved.
+ */
+ A_UINT32 info;
} wmi_roam_btm_response_info;
typedef struct {
@@ -39637,6 +39849,15 @@ typedef struct {
#define WMI_GET_ASSOC_ID(frame_info_ext) WMI_GET_BITS(frame_info_ext, 0, 16)
#define WMI_SET_ASSOC_ID(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 0, 16, val)
+#define WMI_GET_MLO_BITMAP_BAND_INFO(frame_info_ext) WMI_GET_BITS(frame_info_ext, 16, 5)
+#define WMI_SET_MLO_BITMAP_BAND_INFO(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 16, 5, val)
+
+#define WMI_GET_RX_INDICATE(frame_info_ext) WMI_GET_BITS(frame_info_ext, 21, 1)
+#define WMI_SET_RX_INDICATE(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 21, 1, val)
+
+#define WMI_GET_TX_FAILED_REASON(frame_info_ext) WMI_GET_BITS(frame_info_ext, 22, 4)
+#define WMI_SET_TX_FAILED_REASON(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 22, 4, val)
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_frame_info_tlv_param */
/* timestamp is the absolute time w.r.t host timer which is synchronized between the host and target */
@@ -39684,7 +39905,14 @@ typedef struct {
* frame_info_ext captures below fields:
* Bit 0-15 : (re)assoc id of (re)association response frame,
* section 9.4.1.8 AID field.
- * Bit 16~31 : reserved for future use.
+ * Bit 16-20 : MLO bitmap band info,
+ * bit0: 2GHz, bit1: 5GHz, bit2: 6GHz, bits 3-4: reserved
+ * Refer to WMI_[GET,SET]_MLO_BITMAP_BAND_INFO macros.
+ * Bit 21 : indicate whether this frame is rx :0-not rx; 1-rx
+ * Refer to WMI_[GET,SET]_RX_INDICATE macros.
+ * Bit 22-25 : opaque tx failure reason
+ * Refer to WMI_[GET,SET]_TX_FAILED_REASON macros.
+ * Bit 26-31 : reserved for future use.
*/
A_UINT32 frame_info_ext;
} wmi_roam_frame_info;
@@ -40132,6 +40360,22 @@ typedef enum {
*/
WMI_ROAM_PARAM_ROAM_RSSI_BOOST_FOR_6GHZ_CAND_AP = 8,
+ /*
+ * Roam param to indicate unsupported Power Type for 6 GHz Candidate AP
+ * found during Roam Scan. If AP operates on the power type disabled by
+ * the host, then that candidate should not be selected.
+ * This unsupported Power Type will be configured based
+ * on disabled 6GHz Power Types in Regdomain
+ *
+ * If below bits in the obtianed Bitmap is set then any AP
+ * broadcasting these Power Types should not be selected
+ * BIT 0 - Indoor Access Point
+ * BIT 1 - Standard Power (SP) Access Point
+ * BIT 2 - Very Low Power (VLP) Access Point
+ * BIT 3-7 - Reserved
+ */
+ WMI_ROAM_PARAM_ROAM_UNSUPPORTED_6GHZ_POWERTYPE = 9,
+
/*=== END ROAM_PARAM_PROTOTYPE SECTION ===*/
} WMI_ROAM_PARAM;
@@ -40385,6 +40629,229 @@ typedef struct {
A_UINT32 perChainIbfCalVal[WMI_MAX_CHAINS_FOR_AOA_RCC];
} wmi_pdev_aoa_phasedelta_evt_fixed_param;
+#define WMI_AOA_MAX_SUPPORTED_CHAINS_GET(chain_data) \
+ WMI_GET_BITS(chain_data, 0, 16)
+#define WMI_AOA_MAX_SUPPORTED_CHAINS_SET(chain_data, value) \
+ WMI_SET_BITS(chain_data, 0, 16, value)
+
+#define WMI_AOA_SUPPORTED_CHAINMASK_GET(chain_data) \
+ WMI_GET_BITS(chain_data, 16, 16)
+#define WMI_AOA_SUPPORTED_CHAINMASK_SET(chain_data, value) \
+ WMI_SET_BITS(chain_data, 16, 16, value)
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_eventid */
+ A_UINT32 tlv_header;
+ /* Current Operating Channel Frequency in MHz */
+ A_UINT32 freq;
+ /** pdev_id:
+ * Identify the MAC.
+ * See macros starting with WMI_PDEV_ID_ for values.
+ * In non-DBDC case host should set it to 0.
+ */
+ A_UINT32 pdev_id;
+ /** chain_info:
+ * B0 -- B15 : Max number of chains supported
+ * B16 --B31 : Data shared for chainmask -
+ * indicates the chains to which the data shared.
+ */
+ union {
+ struct {
+ A_UINT32 max_supported_chains:16,
+ data_for_chainmask:16;
+ };
+ A_UINT32 chain_info;
+ };
+ /** XBAR configuration to get RF2BB/BB2RF chain mapping
+ * Samples of xbar_config,
+ * If xbar_config is 0xFAC688(hex):
+ * RF chains 0-7 are connected to BB chains 0-7
+ * here,
+ * bits 0 to 2 = 0, maps BB chain 0 for RF chain 0
+ * bits 3 to 5 = 1, maps BB chain 1 for RF chain 1
+ * bits 6 to 8 = 2, maps BB chain 2 for RF chain 2
+ * bits 9 to 11 = 3, maps BB chain 3 for RF chain 3
+ * bits 12 to 14 = 4, maps BB chain 4 for RF chain 4
+ * bits 15 to 17 = 5, maps BB chain 5 for RF chain 5
+ * bits 18 to 20 = 6, maps BB chain 6 for RF chain 6
+ * bits 21 to 23 = 7, maps BB chain 7 for RF chain 7
+ *
+ * If xbar_config is 0x688FAC(hex):
+ * RF chains 0-3 are connected to BB chains 4-7
+ * RF chains 4-7 are connected to BB chains 0-3
+ * here,
+ * bits 0 to 2 = 4, maps BB chain 4 for RF chain 0
+ * bits 3 to 5 = 5, maps BB chain 5 for RF chain 1
+ * bits 6 to 8 = 6, maps BB chain 6 for RF chain 2
+ * bits 9 to 11 = 7, maps BB chain 7 for RF chain 3
+ * bits 12 to 14 = 0, maps BB chain 0 for RF chain 4
+ * bits 15 to 17 = 1, maps BB chain 1 for RF chain 5
+ * bits 18 to 20 = 2, maps BB chain 2 for RF chain 6
+ * bits 21 to 23 = 3, maps BB chain 3 for RF chain 7
+ */
+ A_UINT32 xbar_config;
+ /**
+ * IBF cal values:
+ * Used for final AoA calculation
+ * [AoAPhase = ( PhaseDeltaValue + IBFcalValue ) % 1024]
+ */
+ A_UINT32 per_chain_ibf_cal_val[WMI_MAX_CHAINS];
+ /**
+ * This TLV is followed by TLV arrays containing
+ * different types of data header and data buffer TLVs:
+ * 1. wmi_enhanced_aoa_gain_phase_data_hdr.
+ * This TLV contains the array of structure fields which indicate
+ * the type and format of data carried in the following data buffer
+ * TLV.
+ * 2. aoa_data_buf[] - Data buffer TLV.
+ * TLV header contains the total buffer size.
+ * Data buffer contains the phase_delta_array[Chains][GainEntries]
+ * in absolute phase values ranging 0-1024 and
+ * gain_delta_array[Chains][GainEntries] are gain index values.
+ */
+} wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param;
+
+#define WMI_AOA_DATA_TYPE_GET(data_info) \
+ WMI_GET_BITS(data_info, 0, 8)
+#define WMI_AOA_DATA_TYPE_SET(data_info,value) \
+ WMI_SET_BITS(data_info, 0, 8, value)
+
+#define WMI_AOA_NUM_ENTIRES_GET(data_info) \
+ WMI_GET_BITS(data_info, 8, 8)
+#define WMI_AOA_NUM_DATA_ENTRIES_SET(data_info,value) \
+ WMI_SET_BITS(data_info, 8, 8, value)
+
+typedef enum _WMI_AOA_EVENT_DATA_TYPE {
+ WMI_PHASE_DELTA_ARRAY = 0x0,
+ WMI_GAIN_GROUP_STOP_ARRAY = 0x1,
+ /* add new types here */
+ WMI_MAX_DATA_TYPE_ARRAY,
+} WMI_AOA_EVENT_DATA_TYPE;
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_eventid */
+ A_UINT32 tlv_header;
+ /** data_info:
+ * Data follows the LSB first and MSB second order in a 32bit word
+ * bit mapping:
+ * B0 -- B7 : Data type
+ * B8 -- B15 : Number of entries to be parsed in terms of 32bit word
+ *
+ * If data is Phase delta values - Data type is 0x0
+ * group stop gain index values - Data type is 0x1
+ *
+ * num_entries - Total number of data entries in uint32
+ */
+ union {
+ struct {
+ A_UINT32 data_type:8,
+ num_entries:8,
+ reserved:16;
+ };
+ A_UINT32 data_info;
+ };
+} wmi_enhanced_aoa_gain_phase_data_hdr;
+
+typedef enum _WMI_AGC_GAIN_TABLE_IDX {
+ WMI_AGC_DG_TABLE_IDX = 0,
+ WMI_AGC_LG_TABLE_IDX,
+ WMI_AGC_VLG_TABLE_IDX,
+ WMI_AGC_MAX_GAIN_TABLE_IDX = 8,
+} WMI_AGC_GAIN_TABLE_IDX;
+
+#define WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD 4
+#define WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD 2
+#define WMI_AOA_NUM_BYTES_FOR_BDF_GAIN_TBL_ELEM 1
+#define WMI_AOA_NUM_BYTES_FOR_GAIN_TBL_ELEM 2
+
+/* Number of words required to store max number of gain table elements = ((max number of gain table elements)/(number of gain table elements per word)) */
+/* 2 bytes (at most)used to store each gain table elements */
+#define WMI_AOA_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS (WMI_AGC_MAX_GAIN_TABLE_IDX / WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD)
+
+/* 1 byte (at most) used to store each gain table elements obtained from BDF */
+#define WMI_AOA_BDF_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS (WMI_AGC_MAX_GAIN_TABLE_IDX / WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD)
+
+typedef enum {
+ WMI_AOA_2G = 0,
+ WMI_AOA_5G,
+ WMI_AOA_6G,
+ WMI_AOA_MAX_BAND,
+} WMI_AOA_SUPPORTED_BANDS;
+
+#define WMI_AOA_MAX_AGC_GAIN_GET(pcap_var, tbl_idx, output) \
+ do { \
+ A_UINT8 word_idx = 0; \
+ A_UINT8 bit_index = 0; \
+ A_UINT8 nth_byte = 0; \
+ word_idx = tbl_idx >> 1; \
+ nth_byte = (tbl_idx % WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD); \
+ bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_GAIN_TBL_ELEM; \
+ output = WMI_GET_BITS(*(pcap_var + word_idx), bit_index, 16); \
+ } while (0)
+
+#define WMI_AOA_MAX_AGC_GAIN_SET(pcap_var, tbl_idx, value) \
+ do { \
+ A_UINT8 word_idx = 0; \
+ A_UINT8 bit_index = 0; \
+ A_UINT8 nth_byte = 0; \
+ word_idx = tbl_idx >> 1; \
+ nth_byte = (tbl_idx % WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD); \
+ bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_GAIN_TBL_ELEM; \
+ WMI_SET_BITS(*(pcap_var+word_idx), bit_index, 16, value); \
+ } while (0)
+
+#define WMI_AOA_MAX_BDF_ENTRIES_GET(pcap_var, tbl_idx, output) \
+ do { \
+ A_UINT8 word_idx = 0; \
+ A_UINT8 bit_index = 0; \
+ A_UINT8 nth_byte = 0; \
+ word_idx = tbl_idx >> 2; \
+ nth_byte = (tbl_idx % WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD); \
+ bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_BDF_GAIN_TBL_ELEM; \
+ output = WMI_GET_BITS(*(pcap_var+word_idx), bit_index, 8); \
+ } while (0)
+
+#define WMI_AOA_MAX_BDF_ENTRIES_SET(pcap_var, tbl_idx, value) \
+ do { \
+ A_UINT8 word_idx = 0; \
+ A_UINT8 nth_byte = 0; \
+ A_UINT8 bit_index = 0; \
+ word_idx = tbl_idx >> 2; \
+ nth_byte = (tbl_idx % WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD); \
+ bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_BDF_GAIN_TBL_ELEM; \
+ WMI_SET_BITS(*(pcap_var+word_idx), bit_index, 8, value); \
+ } while (0)
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_enhanced_aoa_caps_param */
+ A_UINT32 tlv_header;
+
+ /* Maximum number of Rx AGC gain tables supported */
+ A_UINT32 max_agc_gain_tbls;
+
+ /* 1 byte is used to store bdf max number of elements in each gain tables */
+ A_UINT32 max_bdf_gain_entries[WMI_AOA_BDF_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS];
+
+ /** This TLV is followed by TLV array - wmi_enhanced_aoa_per_band_caps_param
+ * containing band specifc agc gain table information.
+ */
+} wmi_enhanced_aoa_caps_param;
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param */
+ A_UINT32 tlv_header;
+
+ /* Band information - WMI_AOA_SUPPORTED_BANDS */
+ A_UINT32 band_info;
+
+ /* 2 bytes are used to store agc max number of elements in each gain tables */
+ A_UINT32 max_agc_gain[WMI_AOA_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS];
+} wmi_enhanced_aoa_per_band_caps_param;
+
/* WMI_HALPHY_CAL_LIST:
*
* Below is the list of HALPHY online CAL currently enabled in
@@ -44006,6 +44473,7 @@ typedef enum {
WMI_MLO_LINK_FORCE_REASON_NEW_DISCONNECT = 2, /* Set force specific links because of new dis-connection */
WMI_MLO_LINK_FORCE_REASON_LINK_REMOVAL = 3, /* Set force specific links because of AP-side link removal */
WMI_MLO_LINK_FORCE_REASON_TDLS = 4, /* Set force specific links because of 11BE MLO TDLS setup/teardown */
+ WMI_MLO_LINK_FORCE_REASON_REVERT_FAILURE = 5, /* Set force specific links for revert previous failed due to host reject */
} WMI_MLO_LINK_FORCE_REASON;
#define WMI_MLO_CONTROL_FLAGS_GET_OVERWRITE_FORCE_ACTIVE(mlo_flags) \
@@ -44112,6 +44580,11 @@ typedef struct wmi_mlo_set_active_link_number_param
} wmi_mlo_set_active_link_number_param;
+typedef enum {
+ WMI_MLO_LINK_SET_ACTIVE_STATUS_SUCCESS = 0,
+ WMI_MLO_LINK_SET_ACTIVE_STATUS_HOST_REJECT = 1,
+} WMI_MLO_LINK_SET_ACTIVE_STATUS;
+
typedef struct wmi_mlo_link_set_active_resp_event
{
/** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_set_active_resp_event_fixed_param; */
@@ -44134,6 +44607,10 @@ typedef struct wmi_mlo_link_set_active_resp_event
* If use_ieee_link_id_bitmap equals 1, ieee_link_id_bitmap[] are valid.
* A_UINT32 force_active_ieee_link_id_bitmap[];
* A_UINT32 force_inactive_ieee_link_id_bitmap[];
+ *---
+ * current active ieee link id bitmap & inactive ieee link id bitmap
+ * A_UINT32 current_active_ieee_link_id_bitmap[];
+ * A_UINT32 current_inactive_ieee_link_id_bitmap[];
*/
} wmi_mlo_link_set_active_resp_event_fixed_param;
@@ -44174,8 +44651,14 @@ typedef struct {
} wmi_mlo_ready_cmd_fixed_param;
typedef enum wmi_mlo_tear_down_reason_code_type {
- WMI_MLO_TEARDOWN_SSR_REASON,
- WMI_MLO_TEARDOWN_HOST_INITIATED_REASON,
+ WMI_MLO_TEARDOWN_REASON_SSR,
+ /* keep old name as alias for new name */
+ WMI_MLO_TEARDOWN_SSR_REASON = WMI_MLO_TEARDOWN_REASON_SSR,
+ WMI_MLO_TEARDOWN_REASON_HOST_INITIATED,
+ /* keep old name as alias for new name */
+ WMI_MLO_TEARDOWN_HOST_INITIATED_REASON =
+ WMI_MLO_TEARDOWN_REASON_HOST_INITIATED,
+ WMI_MLO_TEARDOWN_REASON_STANDBY_DOWN,
} WMI_MLO_TEARDOWN_REASON_TYPE;
typedef struct {
@@ -44187,6 +44670,8 @@ typedef struct {
A_UINT32 reason_code;
/* trigger_umac_reset : of type A_BOOL to indicate the umac reset for the partner chip. */
A_UINT32 trigger_umac_reset;
+ /* erp_standby_mode : of type A_BOOL to indicate the chip is going to be active in ERP */
+ A_UINT32 erp_standby_mode;
} wmi_mlo_teardown_fixed_param;
typedef struct {
@@ -45606,7 +46091,7 @@ typedef struct {
struct {
A_UINT32 vdev_id:8, /* vdev id for this link */
link_id:8, /* link id defined as in 802.11 BE spec. */
- link_status:2, /* link_status - 0: active, 1: inactive */
+ link_status:2, /* link_status - 0: inactive, 1: active */
reserved:14;
};
A_UINT32 link_info;
@@ -45689,6 +46174,9 @@ typedef struct {
} wmi_vdev_set_manual_su_trig_cmd_fixed_param;
+#define CQI_UPLOAD_META_DATA_NC_IDX(idx) \
+ (MAX_NUM_CQI_USERS_IN_STANDALONE_SND + (idx * 2))
+
#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_ASNR_LENGTH(asnr_params, value) \
WMI_SET_BITS(asnr_params, 0, 16, value)
#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_ASNR_LENGTH(asnr_params) \
@@ -45719,26 +46207,46 @@ typedef struct {
#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_FB_PARAMS_NSS_NUM(fb_params) \
WMI_GET_BITS(fb_params, 2, 2)
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_DDR_BUF_IDX(ddr_buffer_idx, value) \
+ WMI_SET_BITS(ddr_buffer_idx, 4, 2, value)
+#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_DDR_BUF_IDX(ddr_buffer_idx) \
+ WMI_GET_BITS(ddr_buffer_idx, 4, 2)
+
#define WMI_SET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params, value) \
- WMI_SET_BITS(snd_params, 0, 1, value)
+ WMI_SET_BITS(snd_params, 0, 2, value)
#define WMI_GET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params) \
- WMI_GET_BITS(snd_params, 0, 1)
+ WMI_GET_BITS(snd_params, 0, 2)
#define WMI_SET_STANDALONE_SOUND_PARAMS_NG(snd_params, value) \
- WMI_SET_BITS(snd_params, 1, 2, value)
+ WMI_SET_BITS(snd_params, 2, 2, value)
#define WMI_GET_STANDALONE_SOUND_PARAMS_NG(snd_params) \
- WMI_GET_BITS(snd_params, 1, 2)
+ WMI_GET_BITS(snd_params, 2, 2)
#define WMI_SET_STANDALONE_SOUND_PARAMS_CB(snd_params, value) \
- WMI_SET_BITS(snd_params, 3, 1, value)
+ WMI_SET_BITS(snd_params, 4, 1, value)
#define WMI_GET_STANDALONE_SOUND_PARAMS_CB(snd_params) \
- WMI_GET_BITS(snd_params, 3, 1)
+ WMI_GET_BITS(snd_params, 4, 1)
#define WMI_SET_STANDALONE_SOUND_PARAMS_BW(snd_params, value) \
- WMI_SET_BITS(snd_params, 4, 3, value)
+ WMI_SET_BITS(snd_params, 5, 3, value)
#define WMI_GET_STANDALONE_SOUND_PARAMS_BW(snd_params) \
- WMI_GET_BITS(snd_params, 4, 3)
+ WMI_GET_BITS(snd_params, 5, 3)
+
+#define WMI_SET_STANDALONE_SOUND_PARAMS_CQI_TYPE(snd_params, value) \
+ WMI_SET_BITS(snd_params, 8, 1, value)
+#define WMI_GET_STANDALONE_SOUND_PARAMS_CQI_TYPE(snd_params) \
+ WMI_GET_BITS(snd_params, 8, 1)
+
+#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_SET_FB_PARAMS_IS_VALID(fb_params_cqi, value, idx) \
+ WMI_SET_BITS(fb_params_cqi, idx, 1, value)
+#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_GET_FB_PARAMS_IS_VALID(fb_params_cqi, idx) \
+ WMI_GET_BITS(fb_params_cqi, idx, 1)
+
+#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_SET_FB_PARAMS_NC(fb_params_cqi, value, idx) \
+ WMI_SET_BITS(fb_params_cqi, CQI_UPLOAD_META_DATA_NC_IDX(idx), 2, value)
+#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_GET_FB_PARAMS_NC(fb_params_cqi, idx) \
+ WMI_GET_BITS(fb_params_cqi, CQI_UPLOAD_META_DATA_NC_IDX(idx), 2)
typedef enum _WMI_STANDALONE_SOUND_STATUS_T {
@@ -45772,37 +46280,67 @@ typedef struct {
A_UINT32 dsnr_params;
/** Peer mac address */
wmi_mac_addr peer_mac_address;
- /**
+ /** fb_params:
* [1:0] Nc
+ * Refer to WMI_DMA_BUF_RELEASE_CV_UPLOAD_[SET,GET]_FB_PARAMS_NC
* [3:2] nss_num
+ * Refer to WMI_DMA_BUF_RELEASE_CV_UPLOAD_[SET,GET]_FB_PARAMS_NSS_NUM
+ * [5:4] ddr_buffer_idx
+ * Refer to WMI_DMA_BUF_RELEASE_CV_UPLOAD_[SET,GET]_DDR_BUF_IDX
*/
A_UINT32 fb_params;
} wmi_dma_buf_release_cv_upload_meta_data;
+typedef struct {
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_dma_buf_release_cqi_upload_meta_data */
+ A_UINT32 tlv_header;
+
+ /**
+ * [15:0] ASNR length
+ * [31:16] ASNR offset
+ */
+ A_UINT32 asnr_params;
+
+ /** Peer mac address */
+ wmi_mac_addr peer_mac_address[MAX_NUM_CQI_USERS_IN_STANDALONE_SND];
+
+ /**
+ * [0] is_user0_valid
+ * [1] is_user1_valid
+ * [2] is_user2_valid
+ * [4:3] User0_Nc
+ * [6:5] User1_Nc
+ * [8:7] User2_Nc
+ */
+ A_UINT32 fb_params_cqi : 9,
+ reserved : 23;
+} wmi_dma_buf_release_cqi_upload_meta_data;
+
typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param */
/** vdev identifier */
A_UINT32 vdev_id;
/** sounding_params:
- * [0] Feedback type
- * [2:1] Ng
- * [3] Codebook
- * [6:4] BW
- * 0 = 20 MHz
- * 1 = 40 MHz
- * 2 = 80 MHz
- * 3 = 160 MHz
- * 4 = 320 MHz
- * [31:7] Reserved
- */
+ * [1:0] Feedback type
+ * [3:2] Ng
+ * [4] Codebook
+ * [7:5] BW
+ * 0 = 20 MHz
+ * 1 = 40 MHz
+ * 2 = 80 MHz
+ * 3 = 160 MHz
+ * 4 = 320 MHz
+ * [8] Triggered/Non-Triggered CQI
+ * [31:9] Reserved
+ */
A_UINT32 sounding_params;
/** The number of sounding repeats */
A_UINT32 num_sounding_repeats;
/**
- * TLV (tag length value) parameters follow the
- * structure. The TLV's are:
- * wmi_mac_addr peer_list[num_peers];
- */
+ * TLV (tag length value) parameters follow the
+ * structure. The TLV's are:
+ * wmi_mac_addr peer_list[num_peers];
+ */
} wmi_standalone_sounding_cmd_fixed_param;
typedef struct {
@@ -45978,6 +46516,9 @@ typedef struct {
A_UINT32 tlv_header;
wmi_mac_addr ap_mld_macaddr;
+ /* max num of active links recommended by AP or applications */
+ A_UINT32 recommended_max_num_simultaneous_links;
+
/*
* The TLVs listed below follow this fixed_param TLV:
* wmi_mlo_link_bss_param link_bss_params[]:
@@ -46009,6 +46550,7 @@ typedef enum _WMI_LINK_SWITCH_CNF_REASON{
WMI_MLO_LINK_SWITCH_CNF_REASON_BSS_PARAMS_CHANGED = 1,
WMI_MLO_LINK_SWITCH_CNF_REASON_CONCURRECNY_CONFLICT = 2,
WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_INTERNAL_ERROR = 3,
+ WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_RESTORE_FORCE = 4,
WMI_MLO_LINK_SWITCH_CNF_REASON_MAX,
} WMI_LINK_SWITCH_CNF_REASON;
@@ -46021,10 +46563,71 @@ typedef struct {
A_UINT32 tlv_header;
A_UINT32 vdev_id;
- A_UINT32 status; /*see definition of WMI_LINK_SWITCH_CNF_STATUS*/
- A_UINT32 reason; /*see definition of WMI_LINK_SWITCH_CNF_REASON*/
+ A_UINT32 status; /* see definition of WMI_LINK_SWITCH_CNF_STATUS */
+ A_UINT32 reason; /* see definition of WMI_LINK_SWITCH_CNF_REASON */
+
+/*
+ * The following optional TLVs may follow this fixed_praam TLV,
+ * depending on the value of the reason field.
+ *
+ * wmi_mlo_link_set_active_cmd_fixed_param set_link_params[];
+ * The set_link_params array has one element when reason is
+ * WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_RESTORE_FORCE and
+ * use_ieee_link_id_bitmap should always be filled with 1.
+ * In other cases the length of the set_link_params array shall be 0.
+ *
+ * wmi_mlo_set_active_link_number_param link_number_param[];
+ * Link number parameters, optional TLV.
+ * Present when force type is WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or
+ * WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM.
+ * In other cases the length of array shall be 0.
+ *
+ * A_UINT32 ieee_link_id_bitmap[];
+ * present for WMI_MLO_LINK_FORCE_ACTIVE
+ * or WMI_MLO_LINK_FORCE_INACTIVE or WMI_MLO_LINK_NO_FORCE
+ * or WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or
+ * WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM
+ * In other cases the length of array shall be 0.
+ *
+ * A_UINT32 ieee_link_id_bitmap2[];
+ * For force mode WMI_MLO_LINK_FORCE_ACTIVE_INACTIVE ieee_link_id_bitmap2[]
+ * carries the inactive linkid bitmap.
+ * In other cases the length of the array shall be 0.
+ */
} wmi_mlo_link_switch_cnf_fixed_param;
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_req_evt_fixed_param */
+ A_UINT32 link_state_switch_count; /* Number of link state switch event pending, MAX 5 iteration */
+} wmi_mlo_link_state_switch_req_evt_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_trigger_reason_tlv_param */
+ A_UINT32 cur_active_ieee_bitmap; /* current active ieee linkbitmap */
+ A_UINT32 prev_active_ieee_bitmap; /* previous active iee linkbitmap */
+ A_UINT32 host_ref_fw_timestamp_ms; /* fw time stamp on refrence of TIME_STAMP_SYNC_CMD */
+ A_UINT32 reason_code; /* reason for link state switch trigger -
+ * refer to WMI_LINK_STATE_SWITCH_REASON
+ */
+ wmi_mac_addr ml_bssid; /* mac address of mld device */
+} wmi_mlo_link_state_switch_trigger_reason;
+
+typedef enum _WMI_LINK_STATE_SWITCH_REASON {
+ WMI_MLO_PS_LINK_STATE_SWITCH_REASON_VDEV_READY = 0,
+ WMI_MLO_PS_LINK_STATE_SWITCH_REASON_ULL_MODE = 1,
+ WMI_MLO_PS_LINK_STATE_SWITCH_REASON_T2LM_ENABLED = 2,
+ WMI_MLO_PS_LINK_STATE_SWITCH_REASON_T2LM_DISABLED = 3,
+ WMI_MLO_PS_LINK_STATE_SWITCH_REASON_FORCE_ENABLED = 4,
+ WMI_MLO_PS_LINK_STATE_SWITCH_REASON_FORCE_DISABLED = 5,
+ WMI_MLO_PS_LINK_STATE_SWITCH_REASON_LINK_QUALITY = 6,
+ WMI_MLO_PS_LINK_STATE_SWITCH_REASON_LINK_CAPACITY = 7,
+ WMI_MLO_PS_LINK_STATE_SWITCH_REASON_RSSI = 8,
+ WMI_MLO_PS_LINK_STATE_SWITCH_REASON_BMISS = 9,
+ WMI_MLO_PS_LINK_STATE_SWITCH_REASON_BT_STATUS = 10,
+
+ WMI_MLO_PS_LINK_STATE_SWITCH_REASON_MAX,
+} WMI_LINK_STATE_SWITCH_REASON;
+
#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_ML_PEER_ID_GET(new_link_info) WMI_GET_BITS(new_link_info, 0, 16)
#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_ML_PEER_ID_SET(new_link_info, value) WMI_SET_BITS(new_link_info, 0, 16, value)
@@ -46196,6 +46799,25 @@ typedef struct {
A_UINT32 emlsr_pdev_id_map;
} wmi_aux_dev_capabilities;
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param
+ */
+ A_UINT32 tlv_header;
+ A_UINT32 pdev_id; /* for identifying the MAC */
+ A_UINT32 wsi_ingress_load_info;
+ A_UINT32 wsi_egress_load_info;
+} wmi_pdev_wsi_stats_info_cmd_fixed_param;
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param
+ */
+ A_UINT32 tlv_header;
+ A_UINT32 vdev_id;
+ A_UINT32 status; /* accept: 1 reject : 0 */
+} wmi_csa_event_status_ind_fixed_param;
+
/* ADD NEW DEFS HERE */
diff --git a/drivers/staging/fw-api/fw/wmi_version.h b/drivers/staging/fw-api/fw/wmi_version.h
index cd7766461b8a24bc104e61d41bc1bc13e35eb6ed..35aa809e0fc8cdb156a1fed067d5c31e07c02fe3 100644
--- a/drivers/staging/fw-api/fw/wmi_version.h
+++ b/drivers/staging/fw-api/fw/wmi_version.h
@@ -37,7 +37,7 @@
#define __WMI_VER_MINOR_ 0
/** WMI revision number has to be incremented when there is a
* change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1357
+#define __WMI_REVISION_ 1392
/** The Version Namespace should not be normally changed. Only
* host and firmware of the same WMI namespace will work
diff --git a/drivers/staging/fw-api/hw/peach/v1/HALcomdef.h b/drivers/staging/fw-api/hw/peach/v1/HALcomdef.h
new file mode 100644
index 0000000000000000000000000000000000000000..307eb8d09aa6994a79429dc82efe953c8dcca0e2
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/HALcomdef.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef HAL_COMDEF_H
+#define HAL_COMDEF_H
+
+#ifndef _ARM_ASM_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "com_dtypes.h"
+
+#ifndef _BOOL32_DEFINED
+typedef unsigned long int bool32;
+#define _BOOL32_DEFINED
+#endif
+
+#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
+
+ #define inp(port) (*((volatile byte *) (port)))
+ #define inpw(port) (*((volatile word *) (port)))
+ #define inpdw(port) (*((volatile dword *)(port)))
+
+ #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val)))
+ #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val)))
+ #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
diff --git a/drivers/staging/fw-api/hw/peach/v1/HALhwio.h b/drivers/staging/fw-api/hw/peach/v1/HALhwio.h
new file mode 100644
index 0000000000000000000000000000000000000000..1fce6d0729b26783d565d149c72fcb4f6516ca93
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/HALhwio.h
@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef HAL_HWIO_H
+#define HAL_HWIO_H
+
+#include "HALcomdef.h"
+
+#define HWIO_BASE_PTR(base) base##_BASE_PTR
+
+#ifdef __ARMCC_VERSION
+ #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
+#else
+ #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
+#endif
+
+#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym)
+#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index)
+#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2)
+#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3)
+
+#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym)
+#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index)
+#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2)
+#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym)
+#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index)
+#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2)
+#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3)
+
+#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym)
+#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index)
+#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2)
+#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym)
+#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index)
+#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2)
+#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3)
+
+#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym)
+#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index)
+#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2)
+#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3)
+
+#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask)
+#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask)
+#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask)
+#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym)
+#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index)
+#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2)
+#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask)
+#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask)
+#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
+#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val)
+#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val)
+#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val)
+#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val)
+#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val)
+#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
+#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val)
+#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val)
+#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val)
+#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val)
+#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
+#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
+#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
+#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val)
+#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
+#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
+#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
+#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
+
+#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym)
+#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index)
+#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym)
+#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym)
+#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
+#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val)
+#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+
+#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym)
+#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index)
+
+#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN
+#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index)
+#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2)
+#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3)
+#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask)
+#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask)
+#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask)
+#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
+#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val)
+#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val)
+#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val)
+#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
+#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val)
+#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val)
+#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
+#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
+#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR
+#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index)
+#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2)
+#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
+#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS
+#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index)
+#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2)
+#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
+#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS
+#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index)
+#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2)
+#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
+#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK
+#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index)
+#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK
+#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT
+#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT
+#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow
+#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index)
+#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
+
+#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base)
+#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index)
+#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2)
+#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3)
+#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask)
+#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask)
+#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
+#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
+#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val)
+#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val)
+#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
+#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
+#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val)
+#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \
+ static unsigned int Readdata, Val_temp, Val;\
+ Readdata = HWIO_INX(base, hwiosym); \
+ Val_temp = Readdata & ~mask1 & ~mask2; \
+ Val = Val_temp | val1 | val2; \
+ HWIO_##hwiosym##_OUT(base, Val); \
+ }
+
+#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \
+ static unsigned int Readdata1, Val_temp1, Val1;\
+ Readdata1 = HWIO_INX(base, hwiosym); \
+ Val_temp1 = Readdata1 & ~mask1 & ~mask2 & ~mask3; \
+ Val1 = Val_temp1 | val1 | val2 | val3; \
+ HWIO_##hwiosym##_OUT(base, Val1); \
+ }
+
+#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
+ static unsigned int Readdata2, Val_temp2, Val2;\
+ Readdata2 = HWIO_INX(base, hwiosym); \
+ Val_temp2 = Readdata2 & ~mask1 & ~mask2 & ~mask3 & ~mask4; \
+ Val2 = Val_temp2 | val1 | val2 | val3 | val4; \
+ HWIO_##hwiosym##_OUT(base, Val2); \
+ }
+
+#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val)
+#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
+#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
+#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base)
+#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index)
+#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2)
+#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
+#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base)
+#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index)
+#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2)
+#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
+
+#define HWIO_INTLOCK()
+#define HWIO_INTFREE()
+
+#define __inp(port) (*((volatile uint8 *) (port)))
+#define __inpw(port) (*((volatile uint16 *) (port)))
+#define __inpdw(port) (*((volatile uint32 *) (port)))
+#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val)))
+#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val)))
+#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
+
+#ifdef HAL_HWIO_EXTERNAL
+
+#undef __inp
+#undef __inpw
+#undef __inpdw
+#undef __outp
+#undef __outpw
+#undef __outpdw
+
+#define __inp(port) __inp_extern(port)
+#define __inpw(port) __inpw_extern(port)
+#define __inpdw(port) __inpdw_extern(port)
+#define __outp(port, val) __outp_extern(port, val)
+#define __outpw(port, val) __outpw_extern(port, val)
+#define __outpdw(port, val) __outpdw_extern(port, val)
+
+extern uint8 __inp_extern ( uint32 nAddr );
+extern uint16 __inpw_extern ( uint32 nAddr );
+extern uint32 __inpdw_extern ( uint32 nAddr );
+extern void __outp_extern ( uint32 nAddr, uint8 nData );
+extern void __outpw_extern ( uint32 nAddr, uint16 nData );
+extern void __outpdw_extern ( uint32 nAddr, uint32 nData );
+
+#endif
+
+#define in_byte(addr) (__inp(addr))
+#define in_byte_masked(addr, mask) (__inp(addr) & (mask))
+#define out_byte(addr, val) __outp(addr,val)
+#define out_byte_masked(io, mask, val, shadow) \
+ HWIO_INTLOCK(); \
+ out_byte( io, shadow); \
+ shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
+ HWIO_INTFREE()
+#define out_byte_masked_ns(io, mask, val, current_reg_content) \
+ out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
+ ((uint16)((val) & (mask)))) )
+
+#define in_word(addr) (__inpw(addr))
+#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
+#define out_word(addr, val) __outpw(addr,val)
+#define out_word_masked(io, mask, val, shadow) \
+ HWIO_INTLOCK( ); \
+ shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
+ out_word( io, shadow); \
+ HWIO_INTFREE( )
+#define out_word_masked_ns(io, mask, val, current_reg_content) \
+ out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
+ ((uint16)((val) & (mask)))) )
+
+#define in_dword(addr) (__inpdw(addr))
+#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
+#define out_dword(addr, val) __outpdw(addr,val)
+#define out_dword_masked(io, mask, val, shadow) \
+ HWIO_INTLOCK(); \
+ shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
+ out_dword( io, shadow); \
+ HWIO_INTFREE()
+#define out_dword_masked_ns(io, mask, val, current_reg_content) \
+ out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
+ ((uint32)((val) & (mask)))) )
+
+#endif
+
diff --git a/drivers/staging/fw-api/hw/peach/v1/ack_report.h b/drivers/staging/fw-api/hw/peach/v1/ack_report.h
new file mode 100644
index 0000000000000000000000000000000000000000..6b00b2ee99f0c24f36d4607b0b1a537a8ab6125a
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/ack_report.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _ACK_REPORT_H_
+#define _ACK_REPORT_H_
+
+#define NUM_OF_DWORDS_ACK_REPORT 1
+
+struct ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t selfgen_response_reason : 4,
+ ax_trigger_type : 4,
+ sr_ppdu : 1,
+ reserved : 7,
+ frame_control : 16;
+#else
+ uint32_t frame_control : 16,
+ reserved : 7,
+ sr_ppdu : 1,
+ ax_trigger_type : 4,
+ selfgen_response_reason : 4;
+#endif
+};
+
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3
+#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f
+
+#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000
+#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4
+#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7
+#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0
+
+#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000
+#define ACK_REPORT_SR_PPDU_LSB 8
+#define ACK_REPORT_SR_PPDU_MSB 8
+#define ACK_REPORT_SR_PPDU_MASK 0x00000100
+
+#define ACK_REPORT_RESERVED_OFFSET 0x00000000
+#define ACK_REPORT_RESERVED_LSB 9
+#define ACK_REPORT_RESERVED_MSB 15
+#define ACK_REPORT_RESERVED_MASK 0x0000fe00
+
+#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000
+#define ACK_REPORT_FRAME_CONTROL_LSB 16
+#define ACK_REPORT_FRAME_CONTROL_MSB 31
+#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/beryllium_top_reg.h b/drivers/staging/fw-api/hw/peach/v1/beryllium_top_reg.h
new file mode 100644
index 0000000000000000000000000000000000000000..5477be24828e81c2c59ad4b76df8ce54ed971999
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/beryllium_top_reg.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef BERYLLIUM_TOP_REG_H
+#define BERYLLIUM_TOP_REG_H
+
+#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C)
+#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050)
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/buffer_addr_info.h b/drivers/staging/fw-api/hw/peach/v1/buffer_addr_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..4a8c064ecd163474f6b09ceb012d276fed827e05
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/buffer_addr_info.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _BUFFER_ADDR_INFO_H_
+#define _BUFFER_ADDR_INFO_H_
+
+#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
+
+struct buffer_addr_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t buffer_addr_31_0 : 32;
+ uint32_t buffer_addr_39_32 : 8,
+ return_buffer_manager : 4,
+ sw_buffer_cookie : 20;
+#else
+ uint32_t buffer_addr_31_0 : 32;
+ uint32_t sw_buffer_cookie : 20,
+ return_buffer_manager : 4,
+ buffer_addr_39_32 : 8;
+#endif
+};
+
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/ce_src_desc.h b/drivers/staging/fw-api/hw/peach/v1/ce_src_desc.h
new file mode 100644
index 0000000000000000000000000000000000000000..3aa8b5850feade17e44bf502fa7029f4ee937286
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/ce_src_desc.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _CE_SRC_DESC_H_
+#define _CE_SRC_DESC_H_
+
+#define NUM_OF_DWORDS_CE_SRC_DESC 4
+
+struct ce_src_desc {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t src_buffer_low : 32;
+ uint32_t src_buffer_high : 8,
+ toeplitz_en : 1,
+ src_swap : 1,
+ dest_swap : 1,
+ gather : 1,
+ ce_res_0 : 1,
+ barrier_read : 1,
+ ce_res_1 : 2,
+ length : 16;
+ uint32_t fw_metadata : 16,
+ ce_res_2 : 16;
+ uint32_t ce_res_3 : 20,
+ ring_id : 8,
+ looping_count : 4;
+#else
+ uint32_t src_buffer_low : 32;
+ uint32_t length : 16,
+ ce_res_1 : 2,
+ barrier_read : 1,
+ ce_res_0 : 1,
+ gather : 1,
+ dest_swap : 1,
+ src_swap : 1,
+ toeplitz_en : 1,
+ src_buffer_high : 8;
+ uint32_t ce_res_2 : 16,
+ fw_metadata : 16;
+ uint32_t looping_count : 4,
+ ring_id : 8,
+ ce_res_3 : 20;
+#endif
+};
+
+#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000
+#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0
+#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31
+#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff
+
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7
+#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff
+
+#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004
+#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8
+#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8
+#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100
+
+#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004
+#define CE_SRC_DESC_SRC_SWAP_LSB 9
+#define CE_SRC_DESC_SRC_SWAP_MSB 9
+#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200
+
+#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004
+#define CE_SRC_DESC_DEST_SWAP_LSB 10
+#define CE_SRC_DESC_DEST_SWAP_MSB 10
+#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400
+
+#define CE_SRC_DESC_GATHER_OFFSET 0x00000004
+#define CE_SRC_DESC_GATHER_LSB 11
+#define CE_SRC_DESC_GATHER_MSB 11
+#define CE_SRC_DESC_GATHER_MASK 0x00000800
+
+#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004
+#define CE_SRC_DESC_CE_RES_0_LSB 12
+#define CE_SRC_DESC_CE_RES_0_MSB 12
+#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000
+
+#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004
+#define CE_SRC_DESC_BARRIER_READ_LSB 13
+#define CE_SRC_DESC_BARRIER_READ_MSB 13
+#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000
+
+#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004
+#define CE_SRC_DESC_CE_RES_1_LSB 14
+#define CE_SRC_DESC_CE_RES_1_MSB 15
+#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000
+
+#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004
+#define CE_SRC_DESC_LENGTH_LSB 16
+#define CE_SRC_DESC_LENGTH_MSB 31
+#define CE_SRC_DESC_LENGTH_MASK 0xffff0000
+
+#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008
+#define CE_SRC_DESC_FW_METADATA_LSB 0
+#define CE_SRC_DESC_FW_METADATA_MSB 15
+#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff
+
+#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008
+#define CE_SRC_DESC_CE_RES_2_LSB 16
+#define CE_SRC_DESC_CE_RES_2_MSB 31
+#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000
+
+#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c
+#define CE_SRC_DESC_CE_RES_3_LSB 0
+#define CE_SRC_DESC_CE_RES_3_MSB 19
+#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff
+
+#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c
+#define CE_SRC_DESC_RING_ID_LSB 20
+#define CE_SRC_DESC_RING_ID_MSB 27
+#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000
+
+#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c
+#define CE_SRC_DESC_LOOPING_COUNT_LSB 28
+#define CE_SRC_DESC_LOOPING_COUNT_MSB 31
+#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/ce_stat_desc.h b/drivers/staging/fw-api/hw/peach/v1/ce_stat_desc.h
new file mode 100644
index 0000000000000000000000000000000000000000..199c25775c0c83c9bd036a63da58b834ae2cf6ef
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/ce_stat_desc.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _CE_STAT_DESC_H_
+#define _CE_STAT_DESC_H_
+
+#define NUM_OF_DWORDS_CE_STAT_DESC 4
+
+struct ce_stat_desc {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t ce_res_5 : 8,
+ toeplitz_en : 1,
+ src_swap : 1,
+ dest_swap : 1,
+ gather : 1,
+ barrier_read : 1,
+ ce_res_6 : 3,
+ length : 16;
+ uint32_t toeplitz_hash_0 : 32;
+ uint32_t toeplitz_hash_1 : 32;
+ uint32_t fw_metadata : 16,
+ ce_res_7 : 4,
+ ring_id : 8,
+ looping_count : 4;
+#else
+ uint32_t length : 16,
+ ce_res_6 : 3,
+ barrier_read : 1,
+ gather : 1,
+ dest_swap : 1,
+ src_swap : 1,
+ toeplitz_en : 1,
+ ce_res_5 : 8;
+ uint32_t toeplitz_hash_0 : 32;
+ uint32_t toeplitz_hash_1 : 32;
+ uint32_t looping_count : 4,
+ ring_id : 8,
+ ce_res_7 : 4,
+ fw_metadata : 16;
+#endif
+};
+
+#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000
+#define CE_STAT_DESC_CE_RES_5_LSB 0
+#define CE_STAT_DESC_CE_RES_5_MSB 7
+#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff
+
+#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000
+#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8
+#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8
+#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100
+
+#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000
+#define CE_STAT_DESC_SRC_SWAP_LSB 9
+#define CE_STAT_DESC_SRC_SWAP_MSB 9
+#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200
+
+#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000
+#define CE_STAT_DESC_DEST_SWAP_LSB 10
+#define CE_STAT_DESC_DEST_SWAP_MSB 10
+#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400
+
+#define CE_STAT_DESC_GATHER_OFFSET 0x00000000
+#define CE_STAT_DESC_GATHER_LSB 11
+#define CE_STAT_DESC_GATHER_MSB 11
+#define CE_STAT_DESC_GATHER_MASK 0x00000800
+
+#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000
+#define CE_STAT_DESC_BARRIER_READ_LSB 12
+#define CE_STAT_DESC_BARRIER_READ_MSB 12
+#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000
+
+#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000
+#define CE_STAT_DESC_CE_RES_6_LSB 13
+#define CE_STAT_DESC_CE_RES_6_MSB 15
+#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000
+
+#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000
+#define CE_STAT_DESC_LENGTH_LSB 16
+#define CE_STAT_DESC_LENGTH_MSB 31
+#define CE_STAT_DESC_LENGTH_MASK 0xffff0000
+
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31
+#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff
+
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31
+#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff
+
+#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c
+#define CE_STAT_DESC_FW_METADATA_LSB 0
+#define CE_STAT_DESC_FW_METADATA_MSB 15
+#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff
+
+#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c
+#define CE_STAT_DESC_CE_RES_7_LSB 16
+#define CE_STAT_DESC_CE_RES_7_MSB 19
+#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000
+
+#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c
+#define CE_STAT_DESC_RING_ID_LSB 20
+#define CE_STAT_DESC_RING_ID_MSB 27
+#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000
+
+#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c
+#define CE_STAT_DESC_LOOPING_COUNT_LSB 28
+#define CE_STAT_DESC_LOOPING_COUNT_MSB 31
+#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/coex_rx_status.h b/drivers/staging/fw-api/hw/peach/v1/coex_rx_status.h
new file mode 100644
index 0000000000000000000000000000000000000000..86db6aad11162879759cd68c4b85cb7a53faaa1e
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/coex_rx_status.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _COEX_RX_STATUS_H_
+#define _COEX_RX_STATUS_H_
+
+#define NUM_OF_DWORDS_COEX_RX_STATUS 2
+
+struct coex_rx_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t rx_mac_frame_status : 2,
+ rx_with_tx_response : 1,
+ rx_rate : 5,
+ rx_bw : 3,
+ single_mpdu : 1,
+ filter_status : 1,
+ ampdu : 1,
+ directed : 1,
+ reserved_0 : 1,
+ rx_nss : 3,
+ rx_rssi : 8,
+ rx_type : 3,
+ retry_bit_setting : 1,
+ more_data_bit_setting : 1;
+ uint32_t remain_rx_packet_time : 16,
+ rx_remaining_fes_time : 16;
+#else
+ uint32_t more_data_bit_setting : 1,
+ retry_bit_setting : 1,
+ rx_type : 3,
+ rx_rssi : 8,
+ rx_nss : 3,
+ reserved_0 : 1,
+ directed : 1,
+ ampdu : 1,
+ filter_status : 1,
+ single_mpdu : 1,
+ rx_bw : 3,
+ rx_rate : 5,
+ rx_with_tx_response : 1,
+ rx_mac_frame_status : 2;
+ uint32_t rx_remaining_fes_time : 16,
+ remain_rx_packet_time : 16;
+#endif
+};
+
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x00000000
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1
+#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x00000003
+
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x00000000
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2
+#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x00000004
+
+#define COEX_RX_STATUS_RX_RATE_OFFSET 0x00000000
+#define COEX_RX_STATUS_RX_RATE_LSB 3
+#define COEX_RX_STATUS_RX_RATE_MSB 7
+#define COEX_RX_STATUS_RX_RATE_MASK 0x000000f8
+
+#define COEX_RX_STATUS_RX_BW_OFFSET 0x00000000
+#define COEX_RX_STATUS_RX_BW_LSB 8
+#define COEX_RX_STATUS_RX_BW_MSB 10
+#define COEX_RX_STATUS_RX_BW_MASK 0x00000700
+
+#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x00000000
+#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11
+#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11
+#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x00000800
+
+#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x00000000
+#define COEX_RX_STATUS_FILTER_STATUS_LSB 12
+#define COEX_RX_STATUS_FILTER_STATUS_MSB 12
+#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x00001000
+
+#define COEX_RX_STATUS_AMPDU_OFFSET 0x00000000
+#define COEX_RX_STATUS_AMPDU_LSB 13
+#define COEX_RX_STATUS_AMPDU_MSB 13
+#define COEX_RX_STATUS_AMPDU_MASK 0x00002000
+
+#define COEX_RX_STATUS_DIRECTED_OFFSET 0x00000000
+#define COEX_RX_STATUS_DIRECTED_LSB 14
+#define COEX_RX_STATUS_DIRECTED_MSB 14
+#define COEX_RX_STATUS_DIRECTED_MASK 0x00004000
+
+#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x00000000
+#define COEX_RX_STATUS_RESERVED_0_LSB 15
+#define COEX_RX_STATUS_RESERVED_0_MSB 15
+#define COEX_RX_STATUS_RESERVED_0_MASK 0x00008000
+
+#define COEX_RX_STATUS_RX_NSS_OFFSET 0x00000000
+#define COEX_RX_STATUS_RX_NSS_LSB 16
+#define COEX_RX_STATUS_RX_NSS_MSB 18
+#define COEX_RX_STATUS_RX_NSS_MASK 0x00070000
+
+#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x00000000
+#define COEX_RX_STATUS_RX_RSSI_LSB 19
+#define COEX_RX_STATUS_RX_RSSI_MSB 26
+#define COEX_RX_STATUS_RX_RSSI_MASK 0x07f80000
+
+#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x00000000
+#define COEX_RX_STATUS_RX_TYPE_LSB 27
+#define COEX_RX_STATUS_RX_TYPE_MSB 29
+#define COEX_RX_STATUS_RX_TYPE_MASK 0x38000000
+
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x00000000
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30
+#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x40000000
+
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x00000000
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31
+#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x80000000
+
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x00000004
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 0
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 15
+#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff
+
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x00000004
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 16
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 31
+#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/coex_tx_req.h b/drivers/staging/fw-api/hw/peach/v1/coex_tx_req.h
new file mode 100644
index 0000000000000000000000000000000000000000..a116adb2a132a0e8d5f0db0e3a065864adaa5e38
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/coex_tx_req.h
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _COEX_TX_REQ_H_
+#define _COEX_TX_REQ_H_
+
+#define NUM_OF_DWORDS_COEX_TX_REQ 4
+
+struct coex_tx_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tx_pwr : 8,
+ min_tx_pwr : 8,
+ nss : 3,
+ tx_chain_mask : 8,
+ bw : 3,
+ reserved_0 : 2;
+ uint32_t alt_tx_pwr : 8,
+ alt_min_tx_pwr : 8,
+ alt_nss : 3,
+ alt_tx_chain_mask : 8,
+ alt_bw : 3,
+ reserved_1 : 2;
+ uint32_t tx_pwr_1 : 8,
+ alt_tx_pwr_1 : 8,
+ wlan_request_duration : 16;
+ uint32_t wlan_pkt_type : 4,
+ coex_tx_reason : 2,
+ response_frame_type : 5,
+ wlan_low_priority_slicing_allowed : 1,
+ wlan_high_priority_slicing_allowed : 1,
+ sch_tx_burst_ongoing : 1,
+ coex_tx_priority : 4,
+ reserved_3a : 14;
+#else
+ uint32_t reserved_0 : 2,
+ bw : 3,
+ tx_chain_mask : 8,
+ nss : 3,
+ min_tx_pwr : 8,
+ tx_pwr : 8;
+ uint32_t reserved_1 : 2,
+ alt_bw : 3,
+ alt_tx_chain_mask : 8,
+ alt_nss : 3,
+ alt_min_tx_pwr : 8,
+ alt_tx_pwr : 8;
+ uint32_t wlan_request_duration : 16,
+ alt_tx_pwr_1 : 8,
+ tx_pwr_1 : 8;
+ uint32_t reserved_3a : 14,
+ coex_tx_priority : 4,
+ sch_tx_burst_ongoing : 1,
+ wlan_high_priority_slicing_allowed : 1,
+ wlan_low_priority_slicing_allowed : 1,
+ response_frame_type : 5,
+ coex_tx_reason : 2,
+ wlan_pkt_type : 4;
+#endif
+};
+
+#define COEX_TX_REQ_TX_PWR_OFFSET 0x00000000
+#define COEX_TX_REQ_TX_PWR_LSB 0
+#define COEX_TX_REQ_TX_PWR_MSB 7
+#define COEX_TX_REQ_TX_PWR_MASK 0x000000ff
+
+#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x00000000
+#define COEX_TX_REQ_MIN_TX_PWR_LSB 8
+#define COEX_TX_REQ_MIN_TX_PWR_MSB 15
+#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x0000ff00
+
+#define COEX_TX_REQ_NSS_OFFSET 0x00000000
+#define COEX_TX_REQ_NSS_LSB 16
+#define COEX_TX_REQ_NSS_MSB 18
+#define COEX_TX_REQ_NSS_MASK 0x00070000
+
+#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x00000000
+#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19
+#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26
+#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define COEX_TX_REQ_BW_OFFSET 0x00000000
+#define COEX_TX_REQ_BW_LSB 27
+#define COEX_TX_REQ_BW_MSB 29
+#define COEX_TX_REQ_BW_MASK 0x38000000
+
+#define COEX_TX_REQ_RESERVED_0_OFFSET 0x00000000
+#define COEX_TX_REQ_RESERVED_0_LSB 30
+#define COEX_TX_REQ_RESERVED_0_MSB 31
+#define COEX_TX_REQ_RESERVED_0_MASK 0xc0000000
+
+#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x00000004
+#define COEX_TX_REQ_ALT_TX_PWR_LSB 0
+#define COEX_TX_REQ_ALT_TX_PWR_MSB 7
+#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff
+
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x00000004
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 8
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 15
+#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff00
+
+#define COEX_TX_REQ_ALT_NSS_OFFSET 0x00000004
+#define COEX_TX_REQ_ALT_NSS_LSB 16
+#define COEX_TX_REQ_ALT_NSS_MSB 18
+#define COEX_TX_REQ_ALT_NSS_MASK 0x00070000
+
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x00000004
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 19
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 26
+#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define COEX_TX_REQ_ALT_BW_OFFSET 0x00000004
+#define COEX_TX_REQ_ALT_BW_LSB 27
+#define COEX_TX_REQ_ALT_BW_MSB 29
+#define COEX_TX_REQ_ALT_BW_MASK 0x38000000
+
+#define COEX_TX_REQ_RESERVED_1_OFFSET 0x00000004
+#define COEX_TX_REQ_RESERVED_1_LSB 30
+#define COEX_TX_REQ_RESERVED_1_MSB 31
+#define COEX_TX_REQ_RESERVED_1_MASK 0xc0000000
+
+#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x00000008
+#define COEX_TX_REQ_TX_PWR_1_LSB 0
+#define COEX_TX_REQ_TX_PWR_1_MSB 7
+#define COEX_TX_REQ_TX_PWR_1_MASK 0x000000ff
+
+#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x00000008
+#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8
+#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15
+#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x0000ff00
+
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x00000008
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31
+#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0xffff0000
+
+#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000c
+#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 0
+#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 3
+#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f
+
+#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000c
+#define COEX_TX_REQ_COEX_TX_REASON_LSB 4
+#define COEX_TX_REQ_COEX_TX_REASON_MSB 5
+#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x00000030
+
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000c
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 6
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 10
+#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c0
+
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000c
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 11
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 11
+#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x00000800
+
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000c
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 12
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 12
+#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x00001000
+
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000c
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 13
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 13
+#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x00002000
+
+#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000c
+#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 14
+#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 17
+#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c000
+
+#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000c
+#define COEX_TX_REQ_RESERVED_3A_LSB 18
+#define COEX_TX_REQ_RESERVED_3A_MSB 31
+#define COEX_TX_REQ_RESERVED_3A_MASK 0xfffc0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/coex_tx_status.h b/drivers/staging/fw-api/hw/peach/v1/coex_tx_status.h
new file mode 100644
index 0000000000000000000000000000000000000000..7331ea9094b09b1b65e41adbb0da71272c3c8050
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/coex_tx_status.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _COEX_TX_STATUS_H_
+#define _COEX_TX_STATUS_H_
+
+#define NUM_OF_DWORDS_COEX_TX_STATUS 3
+
+struct coex_tx_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t reserved_0a : 7,
+ tx_bw : 3,
+ tx_status_reason : 3,
+ tx_wait_ack : 1,
+ fes_tx_is_gen_frame : 1,
+ sch_tx_burst_ongoing : 1,
+ current_tx_duration : 16;
+ uint32_t next_rx_active_time : 16,
+ remaining_fes_time : 16;
+ uint32_t tx_antenna_mask : 8,
+ shared_ant_tx_pwr : 8,
+ other_ant_tx_pwr : 8,
+ reserved_2 : 8;
+#else
+ uint32_t current_tx_duration : 16,
+ sch_tx_burst_ongoing : 1,
+ fes_tx_is_gen_frame : 1,
+ tx_wait_ack : 1,
+ tx_status_reason : 3,
+ tx_bw : 3,
+ reserved_0a : 7;
+ uint32_t remaining_fes_time : 16,
+ next_rx_active_time : 16;
+ uint32_t reserved_2 : 8,
+ other_ant_tx_pwr : 8,
+ shared_ant_tx_pwr : 8,
+ tx_antenna_mask : 8;
+#endif
+};
+
+#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x00000000
+#define COEX_TX_STATUS_RESERVED_0A_LSB 0
+#define COEX_TX_STATUS_RESERVED_0A_MSB 6
+#define COEX_TX_STATUS_RESERVED_0A_MASK 0x0000007f
+
+#define COEX_TX_STATUS_TX_BW_OFFSET 0x00000000
+#define COEX_TX_STATUS_TX_BW_LSB 7
+#define COEX_TX_STATUS_TX_BW_MSB 9
+#define COEX_TX_STATUS_TX_BW_MASK 0x00000380
+
+#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x00000000
+#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10
+#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12
+#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x00001c00
+
+#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x00000000
+#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13
+#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13
+#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x00002000
+
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x00000000
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14
+#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x00004000
+
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x00000000
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15
+#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x00008000
+
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x00000000
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31
+#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0xffff0000
+
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x00000004
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 0
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 15
+#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff
+
+#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x00000004
+#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 16
+#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 31
+#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff0000
+
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x00000008
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7
+#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x000000ff
+
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x00000008
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15
+#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x0000ff00
+
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x00000008
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23
+#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x00ff0000
+
+#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x00000008
+#define COEX_TX_STATUS_RESERVED_2_LSB 24
+#define COEX_TX_STATUS_RESERVED_2_MSB 31
+#define COEX_TX_STATUS_RESERVED_2_MASK 0xff000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/com_dtypes.h b/drivers/staging/fw-api/hw/peach/v1/com_dtypes.h
new file mode 100644
index 0000000000000000000000000000000000000000..dc2da8338fcf6b13936a6d86e03172a21764b239
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/com_dtypes.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef COM_DTYPES_H
+#define COM_DTYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef T_WINNT
+ #ifndef WIN32
+ #define WIN32
+ #endif
+ #include
+#endif
+
+#ifdef TRUE
+#undef TRUE
+#endif
+
+#ifdef FALSE
+#undef FALSE
+#endif
+
+#define TRUE 1
+#define FALSE 0
+
+#define ON 1
+#define OFF 0
+
+#ifndef NULL
+ #define NULL 0
+#endif
+
+#ifndef _ARM_ASM_
+#ifndef _BOOLEAN_DEFINED
+
+typedef unsigned char boolean;
+#define _BOOLEAN_DEFINED
+#endif
+
+#if defined(DALSTDDEF_H)
+#define _BOOLEAN_DEFINED
+#define _UINT32_DEFINED
+#define _UINT16_DEFINED
+#define _UINT8_DEFINED
+#define _INT32_DEFINED
+#define _INT16_DEFINED
+#define _INT8_DEFINED
+#define _UINT64_DEFINED
+#define _INT64_DEFINED
+#define _BYTE_DEFINED
+#endif
+
+#ifndef _UINT32_DEFINED
+
+typedef unsigned int uint32;
+#define _UINT32_DEFINED
+#endif
+
+#ifndef _UINT16_DEFINED
+
+typedef unsigned short uint16;
+#define _UINT16_DEFINED
+#endif
+
+#ifndef _UINT8_DEFINED
+
+typedef unsigned char uint8;
+#define _UINT8_DEFINED
+#endif
+
+#ifndef _INT32_DEFINED
+
+typedef signed int int32;
+#define _INT32_DEFINED
+#endif
+
+#ifndef _INT16_DEFINED
+
+typedef signed short int16;
+#define _INT16_DEFINED
+#endif
+
+#ifndef _INT8_DEFINED
+
+typedef signed char int8;
+#define _INT8_DEFINED
+#endif
+
+#ifndef _BYTE_DEFINED
+
+typedef unsigned char byte;
+#define _BYTE_DEFINED
+#endif
+
+typedef unsigned short word;
+
+typedef unsigned long dword;
+
+typedef unsigned char uint1;
+
+typedef unsigned short uint2;
+
+typedef unsigned long uint4;
+
+typedef signed char int1;
+
+typedef signed short int2;
+
+typedef long int int4;
+
+typedef signed long sint31;
+
+typedef signed short sint15;
+
+typedef signed char sint7;
+
+typedef uint16 UWord16 ;
+typedef uint32 UWord32 ;
+typedef int32 Word32 ;
+typedef int16 Word16 ;
+typedef uint8 UWord8 ;
+typedef int8 Word8 ;
+typedef int32 Vect32 ;
+
+#if (! defined T_WINNT) && (! defined __GNUC__)
+
+ #ifndef _INT64_DEFINED
+
+ typedef long long int64;
+ #define _INT64_DEFINED
+ #endif
+ #ifndef _UINT64_DEFINED
+
+ typedef unsigned long long uint64;
+ #define _UINT64_DEFINED
+ #endif
+#else
+
+ #if (defined __GNUC__)
+ #ifndef _INT64_DEFINED
+ typedef long long int64;
+ #define _INT64_DEFINED
+ #endif
+ #ifndef _UINT64_DEFINED
+ typedef unsigned long long uint64;
+ #define _UINT64_DEFINED
+ #endif
+ #else
+ typedef __int64 int64;
+ #ifndef _UINT64_DEFINED
+ typedef unsigned __int64 uint64;
+ #define _UINT64_DEFINED
+ #endif
+ #endif
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_mu_mimo_info.h b/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_mu_mimo_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..c83784ae4b62c3c3d639098671c2e685a5d13e71
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_mu_mimo_info.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_
+#define _EHT_SIG_USR_MU_MIMO_INFO_H_
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2
+
+struct eht_sig_usr_mu_mimo_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t sta_id : 11,
+ sta_mcs : 4,
+ sta_coding : 1,
+ sta_spatial_config : 6,
+ reserved_0a : 1,
+ rx_integrity_check_passed : 1,
+ subband80_cc_mask : 8;
+ uint32_t user_order_subband80_0 : 8,
+ user_order_subband80_1 : 8,
+ user_order_subband80_2 : 8,
+ user_order_subband80_3 : 8;
+#else
+ uint32_t subband80_cc_mask : 8,
+ rx_integrity_check_passed : 1,
+ reserved_0a : 1,
+ sta_spatial_config : 6,
+ sta_coding : 1,
+ sta_mcs : 4,
+ sta_id : 11;
+ uint32_t user_order_subband80_3 : 8,
+ user_order_subband80_2 : 8,
+ user_order_subband80_1 : 8,
+ user_order_subband80_0 : 8;
+#endif
+};
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21
+#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22
+#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23
+#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31
+#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
+
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31
+#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_ofdma_info.h b/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_ofdma_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..8455629f5b273711d960ac7c1e3e5d795eca2668
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_ofdma_info.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _EHT_SIG_USR_OFDMA_INFO_H_
+#define _EHT_SIG_USR_OFDMA_INFO_H_
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2
+
+struct eht_sig_usr_ofdma_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t sta_id : 11,
+ sta_mcs : 4,
+ validate_0a : 1,
+ nss : 4,
+ txbf : 1,
+ sta_coding : 1,
+ reserved_0b : 1,
+ rx_integrity_check_passed : 1,
+ subband80_cc_mask : 8;
+ uint32_t user_order_subband80_0 : 8,
+ user_order_subband80_1 : 8,
+ user_order_subband80_2 : 8,
+ user_order_subband80_3 : 8;
+#else
+ uint32_t subband80_cc_mask : 8,
+ rx_integrity_check_passed : 1,
+ reserved_0b : 1,
+ sta_coding : 1,
+ txbf : 1,
+ nss : 4,
+ validate_0a : 1,
+ sta_mcs : 4,
+ sta_id : 11;
+ uint32_t user_order_subband80_3 : 8,
+ user_order_subband80_2 : 8,
+ user_order_subband80_1 : 8,
+ user_order_subband80_0 : 8;
+#endif
+};
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10
+#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14
+#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800
+
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15
+#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000
+
+#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16
+#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19
+#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000
+
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20
+#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000
+
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21
+#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000
+
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22
+#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000
+
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23
+#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
+
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31
+#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
+
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31
+#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_su_info.h b/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_su_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..29127112fa5316dfdd4a027f482bc30c3be70291
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/eht_sig_usr_su_info.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _EHT_SIG_USR_SU_INFO_H_
+#define _EHT_SIG_USR_SU_INFO_H_
+
+#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1
+
+struct eht_sig_usr_su_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t sta_id : 11,
+ sta_mcs : 4,
+ validate_0a : 1,
+ nss : 4,
+ txbf : 1,
+ sta_coding : 1,
+ reserved_0b : 9,
+ rx_integrity_check_passed : 1;
+#else
+ uint32_t rx_integrity_check_passed : 1,
+ reserved_0b : 9,
+ sta_coding : 1,
+ txbf : 1,
+ nss : 4,
+ validate_0a : 1,
+ sta_mcs : 4,
+ sta_id : 11;
+#endif
+};
+
+#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0
+#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10
+#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff
+
+#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11
+#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14
+#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800
+
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15
+#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000
+
+#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000
+#define EHT_SIG_USR_SU_INFO_NSS_LSB 16
+#define EHT_SIG_USR_SU_INFO_NSS_MSB 19
+#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000
+
+#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000
+#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20
+#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20
+#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000
+
+#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000
+#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21
+#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21
+#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000
+
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30
+#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000
+
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/expected_response.h b/drivers/staging/fw-api/hw/peach/v1/expected_response.h
new file mode 100644
index 0000000000000000000000000000000000000000..fe18eca09123929d9752b8def91a3fdd7b645bf9
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/expected_response.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _EXPECTED_RESPONSE_H_
+#define _EXPECTED_RESPONSE_H_
+
+#define NUM_OF_DWORDS_EXPECTED_RESPONSE 5
+
+struct expected_response {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tx_ad2_31_0 : 32;
+ uint32_t tx_ad2_47_32 : 16,
+ expected_response_type : 5,
+ response_to_response : 3,
+ su_ba_user_number : 1,
+ response_info_part2_required : 1,
+ transmitted_bssid_check_en : 1,
+ reserved_1 : 5;
+ uint32_t ndp_sta_partial_aid_2_8_0 : 11,
+ reserved_2 : 10,
+ ndp_sta_partial_aid1_8_0 : 11;
+ uint32_t ast_index : 16,
+ capture_ack_ba_sounding : 1,
+ capture_sounding_1str_20mhz : 1,
+ capture_sounding_1str_40mhz : 1,
+ capture_sounding_1str_80mhz : 1,
+ capture_sounding_1str_160mhz : 1,
+ capture_sounding_1str_240mhz : 1,
+ capture_sounding_1str_320mhz : 1,
+ reserved_3a : 9;
+ uint32_t fcs : 9,
+ reserved_4a : 1,
+ crc : 4,
+ scrambler_seed : 7,
+ reserved_4b : 11;
+#else
+ uint32_t tx_ad2_31_0 : 32;
+ uint32_t reserved_1 : 5,
+ transmitted_bssid_check_en : 1,
+ response_info_part2_required : 1,
+ su_ba_user_number : 1,
+ response_to_response : 3,
+ expected_response_type : 5,
+ tx_ad2_47_32 : 16;
+ uint32_t ndp_sta_partial_aid1_8_0 : 11,
+ reserved_2 : 10,
+ ndp_sta_partial_aid_2_8_0 : 11;
+ uint32_t reserved_3a : 9,
+ capture_sounding_1str_320mhz : 1,
+ capture_sounding_1str_240mhz : 1,
+ capture_sounding_1str_160mhz : 1,
+ capture_sounding_1str_80mhz : 1,
+ capture_sounding_1str_40mhz : 1,
+ capture_sounding_1str_20mhz : 1,
+ capture_ack_ba_sounding : 1,
+ ast_index : 16;
+ uint32_t reserved_4b : 11,
+ scrambler_seed : 7,
+ crc : 4,
+ reserved_4a : 1,
+ fcs : 9;
+#endif
+};
+
+#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x00000000
+#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0
+#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31
+#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0xffffffff
+
+#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x00000004
+#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 0
+#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 15
+#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff
+
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x00000004
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 16
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 20
+#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f0000
+
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x00000004
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 21
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 23
+#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e00000
+
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x00000004
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 24
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 24
+#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x01000000
+
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x00000004
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 25
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 25
+#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x02000000
+
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x00000004
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 26
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 26
+#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x04000000
+
+#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x00000004
+#define EXPECTED_RESPONSE_RESERVED_1_LSB 27
+#define EXPECTED_RESPONSE_RESERVED_1_MSB 31
+#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf8000000
+
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x00000008
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x000007ff
+
+#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x00000008
+#define EXPECTED_RESPONSE_RESERVED_2_LSB 11
+#define EXPECTED_RESPONSE_RESERVED_2_MSB 20
+#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x001ff800
+
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x00000008
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31
+#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0xffe00000
+
+#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000c
+#define EXPECTED_RESPONSE_AST_INDEX_LSB 0
+#define EXPECTED_RESPONSE_AST_INDEX_MSB 15
+#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff
+
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000c
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 16
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 16
+#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x00010000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000c
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 17
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 17
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x00020000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000c
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 18
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 18
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x00040000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000c
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 19
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 19
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x00080000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000c
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 20
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 20
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x00100000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000c
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 21
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 21
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x00200000
+
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000c
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 22
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 22
+#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x00400000
+
+#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000c
+#define EXPECTED_RESPONSE_RESERVED_3A_LSB 23
+#define EXPECTED_RESPONSE_RESERVED_3A_MSB 31
+#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff800000
+
+#define EXPECTED_RESPONSE_FCS_OFFSET 0x00000010
+#define EXPECTED_RESPONSE_FCS_LSB 0
+#define EXPECTED_RESPONSE_FCS_MSB 8
+#define EXPECTED_RESPONSE_FCS_MASK 0x000001ff
+
+#define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x00000010
+#define EXPECTED_RESPONSE_RESERVED_4A_LSB 9
+#define EXPECTED_RESPONSE_RESERVED_4A_MSB 9
+#define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x00000200
+
+#define EXPECTED_RESPONSE_CRC_OFFSET 0x00000010
+#define EXPECTED_RESPONSE_CRC_LSB 10
+#define EXPECTED_RESPONSE_CRC_MSB 13
+#define EXPECTED_RESPONSE_CRC_MASK 0x00003c00
+
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x00000010
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20
+#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x001fc000
+
+#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x00000010
+#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21
+#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31
+#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0xffe00000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_dl_info.h b/drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_dl_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..6c5c1c293aa52eb97b694e0a2f108e038e5a88a5
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_dl_info.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _HE_SIG_A_MU_DL_INFO_H_
+#define _HE_SIG_A_MU_DL_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2
+
+struct he_sig_a_mu_dl_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t dl_ul_flag : 1,
+ mcs_of_sig_b : 3,
+ dcm_of_sig_b : 1,
+ bss_color_id : 6,
+ spatial_reuse : 4,
+ transmit_bw : 3,
+ num_sig_b_symbols : 4,
+ comp_mode_sig_b : 1,
+ cp_ltf_size : 2,
+ doppler_indication : 1,
+ reserved_0a : 6;
+ uint32_t txop_duration : 7,
+ reserved_1a : 1,
+ num_ltf_symbols : 3,
+ ldpc_extra_symbol : 1,
+ stbc : 1,
+ packet_extension_a_factor : 2,
+ packet_extension_pe_disambiguity : 1,
+ crc : 4,
+ tail : 6,
+ reserved_1b : 5,
+ rx_integrity_check_passed : 1;
+#else
+ uint32_t reserved_0a : 6,
+ doppler_indication : 1,
+ cp_ltf_size : 2,
+ comp_mode_sig_b : 1,
+ num_sig_b_symbols : 4,
+ transmit_bw : 3,
+ spatial_reuse : 4,
+ bss_color_id : 6,
+ dcm_of_sig_b : 1,
+ mcs_of_sig_b : 3,
+ dl_ul_flag : 1;
+ uint32_t rx_integrity_check_passed : 1,
+ reserved_1b : 5,
+ tail : 6,
+ crc : 4,
+ packet_extension_pe_disambiguity : 1,
+ packet_extension_a_factor : 2,
+ stbc : 1,
+ ldpc_extra_symbol : 1,
+ num_ltf_symbols : 3,
+ reserved_1a : 1,
+ txop_duration : 7;
+#endif
+};
+
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0
+#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001
+
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3
+#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e
+
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4
+#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010
+
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10
+#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0
+
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14
+#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800
+
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17
+#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000
+
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21
+#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
+
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22
+#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000
+
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24
+#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000
+
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25
+#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000
+
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31
+#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000
+
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6
+#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f
+
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080
+
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10
+#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700
+
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11
+#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800
+
+#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12
+#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12
+#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000
+
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
+
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15
+#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
+
+#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16
+#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19
+#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000
+
+#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20
+#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25
+#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000
+
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30
+#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000
+
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_ul_info.h b/drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_ul_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..947a6f8e2cba46436bb6d5e94c8f7a5a182eab34
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/he_sig_a_mu_ul_info.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _HE_SIG_A_MU_UL_INFO_H_
+#define _HE_SIG_A_MU_UL_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
+
+struct he_sig_a_mu_ul_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t format_indication : 1,
+ bss_color_id : 6,
+ spatial_reuse : 16,
+ reserved_0a : 1,
+ transmit_bw : 2,
+ reserved_0b : 6;
+ uint32_t txop_duration : 7,
+ reserved_1a : 9,
+ crc : 4,
+ tail : 6,
+ reserved_1b : 5,
+ rx_integrity_check_passed : 1;
+#else
+ uint32_t reserved_0b : 6,
+ transmit_bw : 2,
+ reserved_0a : 1,
+ spatial_reuse : 16,
+ bss_color_id : 6,
+ format_indication : 1;
+ uint32_t rx_integrity_check_passed : 1,
+ reserved_1b : 5,
+ tail : 6,
+ crc : 4,
+ reserved_1a : 9,
+ txop_duration : 7;
+#endif
+};
+
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0
+#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001
+
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6
+#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e
+
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22
+#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000
+
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25
+#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31
+#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000
+
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6
+#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80
+
+#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16
+#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19
+#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000
+
+#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20
+#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25
+#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000
+
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30
+#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000
+
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/he_sig_a_su_info.h b/drivers/staging/fw-api/hw/peach/v1/he_sig_a_su_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..c82cc61e966d5b4cfd8a6ea9439986c1583928a2
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/he_sig_a_su_info.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _HE_SIG_A_SU_INFO_H_
+#define _HE_SIG_A_SU_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2
+
+struct he_sig_a_su_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t format_indication : 1,
+ beam_change : 1,
+ dl_ul_flag : 1,
+ transmit_mcs : 4,
+ dcm : 1,
+ bss_color_id : 6,
+ reserved_0a : 1,
+ spatial_reuse : 4,
+ transmit_bw : 2,
+ cp_ltf_size : 2,
+ nsts : 3,
+ reserved_0b : 6;
+ uint32_t txop_duration : 7,
+ coding : 1,
+ ldpc_extra_symbol : 1,
+ stbc : 1,
+ txbf : 1,
+ packet_extension_a_factor : 2,
+ packet_extension_pe_disambiguity : 1,
+ reserved_1a : 1,
+ doppler_indication : 1,
+ crc : 4,
+ tail : 6,
+ dot11ax_su_extended : 1,
+ dot11ax_ext_ru_size : 3,
+ rx_ndp : 1,
+ rx_integrity_check_passed : 1;
+#else
+ uint32_t reserved_0b : 6,
+ nsts : 3,
+ cp_ltf_size : 2,
+ transmit_bw : 2,
+ spatial_reuse : 4,
+ reserved_0a : 1,
+ bss_color_id : 6,
+ dcm : 1,
+ transmit_mcs : 4,
+ dl_ul_flag : 1,
+ beam_change : 1,
+ format_indication : 1;
+ uint32_t rx_integrity_check_passed : 1,
+ rx_ndp : 1,
+ dot11ax_ext_ru_size : 3,
+ dot11ax_su_extended : 1,
+ tail : 6,
+ crc : 4,
+ doppler_indication : 1,
+ reserved_1a : 1,
+ packet_extension_pe_disambiguity : 1,
+ packet_extension_a_factor : 2,
+ txbf : 1,
+ stbc : 1,
+ ldpc_extra_symbol : 1,
+ coding : 1,
+ txop_duration : 7;
+#endif
+};
+
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0
+#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001
+
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1
+#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002
+
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2
+#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004
+
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6
+#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078
+
+#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_DCM_LSB 7
+#define HE_SIG_A_SU_INFO_DCM_MSB 7
+#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080
+
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13
+#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00
+
+#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14
+#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14
+#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000
+
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18
+#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000
+
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20
+#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000
+
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22
+#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000
+
+#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_NSTS_LSB 23
+#define HE_SIG_A_SU_INFO_NSTS_MSB 25
+#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000
+
+#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26
+#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31
+#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000
+
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6
+#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f
+
+#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_CODING_LSB 7
+#define HE_SIG_A_SU_INFO_CODING_MSB 7
+#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080
+
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8
+#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100
+
+#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_STBC_LSB 9
+#define HE_SIG_A_SU_INFO_STBC_MSB 9
+#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200
+
+#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_TXBF_LSB 10
+#define HE_SIG_A_SU_INFO_TXBF_MSB 10
+#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400
+
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
+
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13
+#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
+
+#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14
+#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14
+#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000
+
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15
+#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000
+
+#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_CRC_LSB 16
+#define HE_SIG_A_SU_INFO_CRC_MSB 19
+#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000
+
+#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_TAIL_LSB 20
+#define HE_SIG_A_SU_INFO_TAIL_MSB 25
+#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000
+
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26
+#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000
+
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29
+#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000
+
+#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30
+#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30
+#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000
+
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/he_sig_b1_mu_info.h b/drivers/staging/fw-api/hw/peach/v1/he_sig_b1_mu_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..2cb4633311a5d26746e5bead98967875576ba498
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/he_sig_b1_mu_info.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _HE_SIG_B1_MU_INFO_H_
+#define _HE_SIG_B1_MU_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
+
+struct he_sig_b1_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t ru_allocation : 8,
+ reserved_0 : 23,
+ rx_integrity_check_passed : 1;
+#else
+ uint32_t rx_integrity_check_passed : 1,
+ reserved_0 : 23,
+ ru_allocation : 8;
+#endif
+};
+
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7
+#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff
+
+#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000
+#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8
+#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30
+#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00
+
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/he_sig_b2_mu_info.h b/drivers/staging/fw-api/hw/peach/v1/he_sig_b2_mu_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..8f198333aa7e6b0a55dc7ce6e8b9578b638e270d
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/he_sig_b2_mu_info.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _HE_SIG_B2_MU_INFO_H_
+#define _HE_SIG_B2_MU_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2
+
+struct he_sig_b2_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t sta_id : 11,
+ sta_spatial_config : 4,
+ sta_mcs : 4,
+ reserved_set_to_1 : 1,
+ sta_coding : 1,
+ reserved_0a : 7,
+ nsts : 3,
+ rx_integrity_check_passed : 1;
+ uint32_t user_order : 8,
+ cc_mask : 8,
+ reserved_1a : 16;
+#else
+ uint32_t rx_integrity_check_passed : 1,
+ nsts : 3,
+ reserved_0a : 7,
+ sta_coding : 1,
+ reserved_set_to_1 : 1,
+ sta_mcs : 4,
+ sta_spatial_config : 4,
+ sta_id : 11;
+ uint32_t reserved_1a : 16,
+ cc_mask : 8,
+ user_order : 8;
+#endif
+};
+
+#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0
+#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10
+#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff
+
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14
+#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800
+
+#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15
+#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18
+#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000
+
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19
+#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000
+
+#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20
+#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20
+#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000
+
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27
+#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000
+
+#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_NSTS_LSB 28
+#define HE_SIG_B2_MU_INFO_NSTS_MSB 30
+#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000
+
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004
+#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0
+#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7
+#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff
+
+#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004
+#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8
+#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15
+#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00
+
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31
+#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/he_sig_b2_ofdma_info.h b/drivers/staging/fw-api/hw/peach/v1/he_sig_b2_ofdma_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..9cb9d4228ebf57b1948c4e9943d7924ae669d7de
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/he_sig_b2_ofdma_info.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _HE_SIG_B2_OFDMA_INFO_H_
+#define _HE_SIG_B2_OFDMA_INFO_H_
+
+#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2
+
+struct he_sig_b2_ofdma_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t sta_id : 11,
+ nsts : 3,
+ txbf : 1,
+ sta_mcs : 4,
+ sta_dcm : 1,
+ sta_coding : 1,
+ reserved_0 : 10,
+ rx_integrity_check_passed : 1;
+ uint32_t user_order : 8,
+ cc_mask : 8,
+ reserved_1a : 16;
+#else
+ uint32_t rx_integrity_check_passed : 1,
+ reserved_0 : 10,
+ sta_coding : 1,
+ sta_dcm : 1,
+ sta_mcs : 4,
+ txbf : 1,
+ nsts : 3,
+ sta_id : 11;
+ uint32_t reserved_1a : 16,
+ cc_mask : 8,
+ user_order : 8;
+#endif
+};
+
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10
+#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff
+
+#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11
+#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13
+#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800
+
+#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14
+#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14
+#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000
+
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18
+#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000
+
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19
+#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000
+
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20
+#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000
+
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000
+
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7
+#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff
+
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15
+#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00
+
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31
+#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/ht_sig_info.h b/drivers/staging/fw-api/hw/peach/v1/ht_sig_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..faf40148e6f45b0414778950cf97a53ad866c5f3
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/ht_sig_info.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _HT_SIG_INFO_H_
+#define _HT_SIG_INFO_H_
+
+#define NUM_OF_DWORDS_HT_SIG_INFO 2
+
+struct ht_sig_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t mcs : 7,
+ cbw : 1,
+ length : 16,
+ reserved_0 : 8;
+ uint32_t smoothing : 1,
+ not_sounding : 1,
+ ht_reserved : 1,
+ aggregation : 1,
+ stbc : 2,
+ fec_coding : 1,
+ short_gi : 1,
+ num_ext_sp_str : 2,
+ crc : 8,
+ signal_tail : 6,
+ reserved_1 : 7,
+ rx_integrity_check_passed : 1;
+#else
+ uint32_t reserved_0 : 8,
+ length : 16,
+ cbw : 1,
+ mcs : 7;
+ uint32_t rx_integrity_check_passed : 1,
+ reserved_1 : 7,
+ signal_tail : 6,
+ crc : 8,
+ num_ext_sp_str : 2,
+ short_gi : 1,
+ fec_coding : 1,
+ stbc : 2,
+ aggregation : 1,
+ ht_reserved : 1,
+ not_sounding : 1,
+ smoothing : 1;
+#endif
+};
+
+#define HT_SIG_INFO_MCS_OFFSET 0x00000000
+#define HT_SIG_INFO_MCS_LSB 0
+#define HT_SIG_INFO_MCS_MSB 6
+#define HT_SIG_INFO_MCS_MASK 0x0000007f
+
+#define HT_SIG_INFO_CBW_OFFSET 0x00000000
+#define HT_SIG_INFO_CBW_LSB 7
+#define HT_SIG_INFO_CBW_MSB 7
+#define HT_SIG_INFO_CBW_MASK 0x00000080
+
+#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000
+#define HT_SIG_INFO_LENGTH_LSB 8
+#define HT_SIG_INFO_LENGTH_MSB 23
+#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00
+
+#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000
+#define HT_SIG_INFO_RESERVED_0_LSB 24
+#define HT_SIG_INFO_RESERVED_0_MSB 31
+#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000
+
+#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004
+#define HT_SIG_INFO_SMOOTHING_LSB 0
+#define HT_SIG_INFO_SMOOTHING_MSB 0
+#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001
+
+#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004
+#define HT_SIG_INFO_NOT_SOUNDING_LSB 1
+#define HT_SIG_INFO_NOT_SOUNDING_MSB 1
+#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002
+
+#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004
+#define HT_SIG_INFO_HT_RESERVED_LSB 2
+#define HT_SIG_INFO_HT_RESERVED_MSB 2
+#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004
+
+#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004
+#define HT_SIG_INFO_AGGREGATION_LSB 3
+#define HT_SIG_INFO_AGGREGATION_MSB 3
+#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008
+
+#define HT_SIG_INFO_STBC_OFFSET 0x00000004
+#define HT_SIG_INFO_STBC_LSB 4
+#define HT_SIG_INFO_STBC_MSB 5
+#define HT_SIG_INFO_STBC_MASK 0x00000030
+
+#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004
+#define HT_SIG_INFO_FEC_CODING_LSB 6
+#define HT_SIG_INFO_FEC_CODING_MSB 6
+#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040
+
+#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004
+#define HT_SIG_INFO_SHORT_GI_LSB 7
+#define HT_SIG_INFO_SHORT_GI_MSB 7
+#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080
+
+#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004
+#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8
+#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9
+#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300
+
+#define HT_SIG_INFO_CRC_OFFSET 0x00000004
+#define HT_SIG_INFO_CRC_LSB 10
+#define HT_SIG_INFO_CRC_MSB 17
+#define HT_SIG_INFO_CRC_MASK 0x0003fc00
+
+#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004
+#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18
+#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23
+#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000
+
+#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004
+#define HT_SIG_INFO_RESERVED_1_LSB 24
+#define HT_SIG_INFO_RESERVED_1_MSB 30
+#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000
+
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/l_sig_a_info.h b/drivers/staging/fw-api/hw/peach/v1/l_sig_a_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..f6b1fbff5190ed72fe6216f9169cca3fdfc4fab9
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/l_sig_a_info.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _L_SIG_A_INFO_H_
+#define _L_SIG_A_INFO_H_
+
+#define NUM_OF_DWORDS_L_SIG_A_INFO 1
+
+struct l_sig_a_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t rate : 4,
+ lsig_reserved : 1,
+ length : 12,
+ parity : 1,
+ tail : 6,
+ pkt_type : 4,
+ captured_implicit_sounding : 1,
+ reserved : 2,
+ rx_integrity_check_passed : 1;
+#else
+ uint32_t rx_integrity_check_passed : 1,
+ reserved : 2,
+ captured_implicit_sounding : 1,
+ pkt_type : 4,
+ tail : 6,
+ parity : 1,
+ length : 12,
+ lsig_reserved : 1,
+ rate : 4;
+#endif
+};
+
+#define L_SIG_A_INFO_RATE_OFFSET 0x00000000
+#define L_SIG_A_INFO_RATE_LSB 0
+#define L_SIG_A_INFO_RATE_MSB 3
+#define L_SIG_A_INFO_RATE_MASK 0x0000000f
+
+#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000
+#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4
+#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4
+#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010
+
+#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000
+#define L_SIG_A_INFO_LENGTH_LSB 5
+#define L_SIG_A_INFO_LENGTH_MSB 16
+#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0
+
+#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000
+#define L_SIG_A_INFO_PARITY_LSB 17
+#define L_SIG_A_INFO_PARITY_MSB 17
+#define L_SIG_A_INFO_PARITY_MASK 0x00020000
+
+#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000
+#define L_SIG_A_INFO_TAIL_LSB 18
+#define L_SIG_A_INFO_TAIL_MSB 23
+#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000
+
+#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000
+#define L_SIG_A_INFO_PKT_TYPE_LSB 24
+#define L_SIG_A_INFO_PKT_TYPE_MSB 27
+#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000
+
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28
+#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
+
+#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000
+#define L_SIG_A_INFO_RESERVED_LSB 29
+#define L_SIG_A_INFO_RESERVED_MSB 30
+#define L_SIG_A_INFO_RESERVED_MASK 0x60000000
+
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/l_sig_b_info.h b/drivers/staging/fw-api/hw/peach/v1/l_sig_b_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..c6f0f3a0cadc597bef8fe4c904cf4d96cda96ecd
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/l_sig_b_info.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _L_SIG_B_INFO_H_
+#define _L_SIG_B_INFO_H_
+
+#define NUM_OF_DWORDS_L_SIG_B_INFO 1
+
+struct l_sig_b_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t rate : 4,
+ length : 12,
+ reserved : 15,
+ rx_integrity_check_passed : 1;
+#else
+ uint32_t rx_integrity_check_passed : 1,
+ reserved : 15,
+ length : 12,
+ rate : 4;
+#endif
+};
+
+#define L_SIG_B_INFO_RATE_OFFSET 0x00000000
+#define L_SIG_B_INFO_RATE_LSB 0
+#define L_SIG_B_INFO_RATE_MSB 3
+#define L_SIG_B_INFO_RATE_MASK 0x0000000f
+
+#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000
+#define L_SIG_B_INFO_LENGTH_LSB 4
+#define L_SIG_B_INFO_LENGTH_MSB 15
+#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0
+
+#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000
+#define L_SIG_B_INFO_RESERVED_LSB 16
+#define L_SIG_B_INFO_RESERVED_MSB 30
+#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000
+
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/macrx_abort_request_info.h b/drivers/staging/fw-api/hw/peach/v1/macrx_abort_request_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..197f4e5d41ee16a6524c4936424f4a774600f71b
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/macrx_abort_request_info.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACRX_ABORT_REQUEST_INFO_H_
+#define _MACRX_ABORT_REQUEST_INFO_H_
+
+#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1
+
+struct macrx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint16_t macrx_abort_reason : 8,
+ reserved_0 : 8;
+#else
+ uint16_t reserved_0 : 8,
+ macrx_abort_reason : 8;
+#endif
+};
+
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7
+#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff
+
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15
+#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h b/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h
new file mode 100644
index 0000000000000000000000000000000000000000..c9c7f41822f90fda733c92fc671cf70c3ef2a503
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_
+#define _MACTX_EHT_SIG_USR_MU_MIMO_H_
+
+#include "eht_sig_usr_mu_mimo_info.h"
+#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2
+
+struct mactx_eht_sig_usr_mu_mimo {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details;
+#else
+ struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details;
+#endif
+};
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x000007ff
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x00007800
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x00008000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x003f0000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x00400000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0xff000000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 0
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 7
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 8
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 15
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 16
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 23
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
+
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 24
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 31
+#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_ofdma.h b/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_ofdma.h
new file mode 100644
index 0000000000000000000000000000000000000000..98d98d500a9f020264feff17f615d81b335ecbe2
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_ofdma.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_
+#define _MACTX_EHT_SIG_USR_OFDMA_H_
+
+#include "eht_sig_usr_ofdma_info.h"
+#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2
+
+struct mactx_eht_sig_usr_ofdma {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details;
+#else
+ struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details;
+#endif
+};
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00007800
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x00008000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x000f0000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x00100000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00200000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x00400000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0xff000000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 0
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 7
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 8
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 15
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 16
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 23
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
+
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 24
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 31
+#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_su.h b/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_su.h
new file mode 100644
index 0000000000000000000000000000000000000000..aaef05617272e69fd5f98ce299f8140ef983c120
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_eht_sig_usr_su.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_EHT_SIG_USR_SU_H_
+#define _MACTX_EHT_SIG_USR_SU_H_
+
+#include "eht_sig_usr_su_info.h"
+#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 1
+
+struct mactx_eht_sig_usr_su {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details;
+#else
+ struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details;
+#endif
+};
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x000007ff
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x00007800
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x00008000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x000f0000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x00100000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x00200000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x7fc00000
+
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_dl.h
new file mode 100644
index 0000000000000000000000000000000000000000..19db380bb47383a0862acbcc92a4ee84ae41959b
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_dl.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_HE_SIG_A_MU_DL_H_
+#define _MACTX_HE_SIG_A_MU_DL_H_
+
+#include "he_sig_a_mu_dl_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2
+
+struct mactx_he_sig_a_mu_dl {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details;
+#else
+ struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 6
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 7
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 10
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 11
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 12
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 14
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 19
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 25
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 30
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000
+
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_ul.h
new file mode 100644
index 0000000000000000000000000000000000000000..ddc528393428d51ce6336b89eced98190bad8bf4
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_mu_ul.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_HE_SIG_A_MU_UL_H_
+#define _MACTX_HE_SIG_A_MU_UL_H_
+
+#include "he_sig_a_mu_ul_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2
+
+struct mactx_he_sig_a_mu_ul {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details;
+#else
+ struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 6
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 15
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 19
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 25
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 30
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000
+
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_su.h b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_su.h
new file mode 100644
index 0000000000000000000000000000000000000000..449e9bc875c47c2c48b988877cae579778e5df10
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_a_su.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_HE_SIG_A_SU_H_
+#define _MACTX_HE_SIG_A_SU_H_
+
+#include "he_sig_a_su_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2
+
+struct mactx_he_sig_a_su {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct he_sig_a_su_info mactx_he_sig_a_su_info_details;
+#else
+ struct he_sig_a_su_info mactx_he_sig_a_su_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 6
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 7
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 8
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 9
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 10
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 12
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 14
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 15
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 19
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 25
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 29
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x38000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 30
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 30
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x40000000
+
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b1_mu.h
new file mode 100644
index 0000000000000000000000000000000000000000..177d7666b6414aaad4ae122c165576ba8a086318
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b1_mu.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_HE_SIG_B1_MU_H_
+#define _MACTX_HE_SIG_B1_MU_H_
+
+#include "he_sig_b1_mu_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 1
+
+struct mactx_he_sig_b1_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details;
+#else
+ struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff
+
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x7fffff00
+
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_mu.h
new file mode 100644
index 0000000000000000000000000000000000000000..6439af73ecb2e6ec7f947cfd70feb5219fc769ad
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_mu.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_HE_SIG_B2_MU_H_
+#define _MACTX_HE_SIG_B2_MU_H_
+
+#include "he_sig_b2_mu_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2
+
+struct mactx_he_sig_b2_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details;
+#else
+ struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x0fe00000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x70000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 0
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 7
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x00000004
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 8
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 15
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff00
+
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 16
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 31
+#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_ofdma.h
new file mode 100644
index 0000000000000000000000000000000000000000..b1563803a0ecaac5c3e0ca678811982a84c39719
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_he_sig_b2_ofdma.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_HE_SIG_B2_OFDMA_H_
+#define _MACTX_HE_SIG_B2_OFDMA_H_
+
+#include "he_sig_b2_ofdma_info.h"
+#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2
+
+struct mactx_he_sig_b2_ofdma {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details;
+#else
+ struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details;
+#endif
+};
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x7fe00000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 0
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 7
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x00000004
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 8
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 15
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff00
+
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 16
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 31
+#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_ht_sig.h b/drivers/staging/fw-api/hw/peach/v1/mactx_ht_sig.h
new file mode 100644
index 0000000000000000000000000000000000000000..96f653ce831ac2f4512b3738251640012c03e871
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_ht_sig.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_HT_SIG_H_
+#define _MACTX_HT_SIG_H_
+
+#include "ht_sig_info.h"
+#define NUM_OF_DWORDS_MACTX_HT_SIG 2
+
+struct mactx_ht_sig {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct ht_sig_info mactx_ht_sig_info_details;
+#else
+ struct ht_sig_info mactx_ht_sig_info_details;
+#endif
+};
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 0
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 1
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 2
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 3
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 4
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 5
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 6
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 7
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 9
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 10
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 17
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 23
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 30
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f000000
+
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_a.h b/drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_a.h
new file mode 100644
index 0000000000000000000000000000000000000000..5ba28f73ec8c54031ec3763ee1d77bce9e83ffa1
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_a.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_L_SIG_A_H_
+#define _MACTX_L_SIG_A_H_
+
+#include "l_sig_a_info.h"
+#define NUM_OF_DWORDS_MACTX_L_SIG_A 1
+
+struct mactx_l_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct l_sig_a_info mactx_l_sig_a_info_details;
+#else
+ struct l_sig_a_info mactx_l_sig_a_info_details;
+#endif
+};
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x60000000
+
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_b.h b/drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_b.h
new file mode 100644
index 0000000000000000000000000000000000000000..4e05a7b71b19095acbfe5ac9e7e1d4e66f724884
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_l_sig_b.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_L_SIG_B_H_
+#define _MACTX_L_SIG_B_H_
+
+#include "l_sig_b_info.h"
+#define NUM_OF_DWORDS_MACTX_L_SIG_B 1
+
+struct mactx_l_sig_b {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct l_sig_b_info mactx_l_sig_b_info_details;
+#else
+ struct l_sig_b_info mactx_l_sig_b_info_details;
+#endif
+};
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x7fff0000
+
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_phy_desc.h b/drivers/staging/fw-api/hw/peach/v1/mactx_phy_desc.h
new file mode 100644
index 0000000000000000000000000000000000000000..a7f61e8108d71820026a1838f594da4f0e139fb4
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_phy_desc.h
@@ -0,0 +1,365 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_PHY_DESC_H_
+#define _MACTX_PHY_DESC_H_
+
+#define NUM_OF_DWORDS_MACTX_PHY_DESC 4
+
+struct mactx_phy_desc {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t reserved_0a : 16,
+ bf_type : 2,
+ wait_sifs : 2,
+ dot11b_preamble_type : 1,
+ pkt_type : 4,
+ su_or_mu : 2,
+ mu_type : 1,
+ bandwidth : 3,
+ channel_capture : 1;
+ uint32_t mcs : 4,
+ global_ofdma_mimo_enable : 1,
+ reserved_1a : 1,
+ stbc : 1,
+ dot11ax_su_extended : 1,
+ dot11ax_trigger_frame_embedded : 1,
+ tx_pwr_shared : 8,
+ tx_pwr_unshared : 8,
+ measure_power : 1,
+ tpc_glut_self_cal : 1,
+ back_to_back_transmission_expected : 1,
+ heavy_clip_nss : 3,
+ txbf_per_packet_no_csd_no_walsh : 1;
+ uint32_t ndp : 2,
+ ul_flag : 1,
+ triggered : 1,
+ ap_pkt_bw : 3,
+ ru_position_start : 8,
+ pcu_ppdu_setup_start_reason : 3,
+ tlv_source : 1,
+ reserved_2a : 2,
+ nss : 3,
+ stream_offset : 3,
+ reserved_2b : 2,
+ clpc_enable : 1,
+ mu_ndp : 1,
+ response_expected : 1;
+ uint32_t rx_chain_mask : 8,
+ rx_chain_mask_valid : 1,
+ ant_sel_valid : 1,
+ ant_sel : 1,
+ cp_setting : 2,
+ he_ppdu_subtype : 2,
+ active_channel : 3,
+ generate_phyrx_tx_start_timing : 1,
+ ltf_size : 2,
+ ru_size_updated_v2 : 4,
+ reserved_3c : 1,
+ u_sig_puncture_pattern_encoding : 6;
+#else
+ uint32_t channel_capture : 1,
+ bandwidth : 3,
+ mu_type : 1,
+ su_or_mu : 2,
+ pkt_type : 4,
+ dot11b_preamble_type : 1,
+ wait_sifs : 2,
+ bf_type : 2,
+ reserved_0a : 16;
+ uint32_t txbf_per_packet_no_csd_no_walsh : 1,
+ heavy_clip_nss : 3,
+ back_to_back_transmission_expected : 1,
+ tpc_glut_self_cal : 1,
+ measure_power : 1,
+ tx_pwr_unshared : 8,
+ tx_pwr_shared : 8,
+ dot11ax_trigger_frame_embedded : 1,
+ dot11ax_su_extended : 1,
+ stbc : 1,
+ reserved_1a : 1,
+ global_ofdma_mimo_enable : 1,
+ mcs : 4;
+ uint32_t response_expected : 1,
+ mu_ndp : 1,
+ clpc_enable : 1,
+ reserved_2b : 2,
+ stream_offset : 3,
+ nss : 3,
+ reserved_2a : 2,
+ tlv_source : 1,
+ pcu_ppdu_setup_start_reason : 3,
+ ru_position_start : 8,
+ ap_pkt_bw : 3,
+ triggered : 1,
+ ul_flag : 1,
+ ndp : 2;
+ uint32_t u_sig_puncture_pattern_encoding : 6,
+ reserved_3c : 1,
+ ru_size_updated_v2 : 4,
+ ltf_size : 2,
+ generate_phyrx_tx_start_timing : 1,
+ active_channel : 3,
+ he_ppdu_subtype : 2,
+ cp_setting : 2,
+ ant_sel : 1,
+ ant_sel_valid : 1,
+ rx_chain_mask_valid : 1,
+ rx_chain_mask : 8;
+#endif
+};
+
+#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x00000000
+#define MACTX_PHY_DESC_RESERVED_0A_LSB 0
+#define MACTX_PHY_DESC_RESERVED_0A_MSB 15
+#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x0000ffff
+
+#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x00000000
+#define MACTX_PHY_DESC_BF_TYPE_LSB 16
+#define MACTX_PHY_DESC_BF_TYPE_MSB 17
+#define MACTX_PHY_DESC_BF_TYPE_MASK 0x00030000
+
+#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x00000000
+#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18
+#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19
+#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x000c0000
+
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x00000000
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20
+#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x00100000
+
+#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x00000000
+#define MACTX_PHY_DESC_PKT_TYPE_LSB 21
+#define MACTX_PHY_DESC_PKT_TYPE_MSB 24
+#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x01e00000
+
+#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x00000000
+#define MACTX_PHY_DESC_SU_OR_MU_LSB 25
+#define MACTX_PHY_DESC_SU_OR_MU_MSB 26
+#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x06000000
+
+#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x00000000
+#define MACTX_PHY_DESC_MU_TYPE_LSB 27
+#define MACTX_PHY_DESC_MU_TYPE_MSB 27
+#define MACTX_PHY_DESC_MU_TYPE_MASK 0x08000000
+
+#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x00000000
+#define MACTX_PHY_DESC_BANDWIDTH_LSB 28
+#define MACTX_PHY_DESC_BANDWIDTH_MSB 30
+#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x70000000
+
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x00000000
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31
+#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x80000000
+
+#define MACTX_PHY_DESC_MCS_OFFSET 0x00000004
+#define MACTX_PHY_DESC_MCS_LSB 0
+#define MACTX_PHY_DESC_MCS_MSB 3
+#define MACTX_PHY_DESC_MCS_MASK 0x0000000f
+
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x00000004
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 4
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 4
+#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x00000010
+
+#define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x00000004
+#define MACTX_PHY_DESC_RESERVED_1A_LSB 5
+#define MACTX_PHY_DESC_RESERVED_1A_MSB 5
+#define MACTX_PHY_DESC_RESERVED_1A_MASK 0x00000020
+
+#define MACTX_PHY_DESC_STBC_OFFSET 0x00000004
+#define MACTX_PHY_DESC_STBC_LSB 6
+#define MACTX_PHY_DESC_STBC_MSB 6
+#define MACTX_PHY_DESC_STBC_MASK 0x00000040
+
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 7
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 7
+#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x00000080
+
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x00000004
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 8
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 8
+#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x00000100
+
+#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x00000004
+#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 9
+#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 16
+#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe00
+
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x00000004
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 17
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 24
+#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe0000
+
+#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x00000004
+#define MACTX_PHY_DESC_MEASURE_POWER_LSB 25
+#define MACTX_PHY_DESC_MEASURE_POWER_MSB 25
+#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x02000000
+
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x00000004
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 26
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 26
+#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x04000000
+
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x00000004
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 27
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 27
+#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x08000000
+
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x00000004
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 28
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 30
+#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x70000000
+
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x00000004
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 31
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 31
+#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x80000000
+
+#define MACTX_PHY_DESC_NDP_OFFSET 0x00000008
+#define MACTX_PHY_DESC_NDP_LSB 0
+#define MACTX_PHY_DESC_NDP_MSB 1
+#define MACTX_PHY_DESC_NDP_MASK 0x00000003
+
+#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x00000008
+#define MACTX_PHY_DESC_UL_FLAG_LSB 2
+#define MACTX_PHY_DESC_UL_FLAG_MSB 2
+#define MACTX_PHY_DESC_UL_FLAG_MASK 0x00000004
+
+#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x00000008
+#define MACTX_PHY_DESC_TRIGGERED_LSB 3
+#define MACTX_PHY_DESC_TRIGGERED_MSB 3
+#define MACTX_PHY_DESC_TRIGGERED_MASK 0x00000008
+
+#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x00000008
+#define MACTX_PHY_DESC_AP_PKT_BW_LSB 4
+#define MACTX_PHY_DESC_AP_PKT_BW_MSB 6
+#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x00000070
+
+#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x00000008
+#define MACTX_PHY_DESC_RU_POSITION_START_LSB 7
+#define MACTX_PHY_DESC_RU_POSITION_START_MSB 14
+#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x00007f80
+
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x00000008
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17
+#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x00038000
+
+#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x00000008
+#define MACTX_PHY_DESC_TLV_SOURCE_LSB 18
+#define MACTX_PHY_DESC_TLV_SOURCE_MSB 18
+#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x00040000
+
+#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x00000008
+#define MACTX_PHY_DESC_RESERVED_2A_LSB 19
+#define MACTX_PHY_DESC_RESERVED_2A_MSB 20
+#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x00180000
+
+#define MACTX_PHY_DESC_NSS_OFFSET 0x00000008
+#define MACTX_PHY_DESC_NSS_LSB 21
+#define MACTX_PHY_DESC_NSS_MSB 23
+#define MACTX_PHY_DESC_NSS_MASK 0x00e00000
+
+#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x00000008
+#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24
+#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26
+#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x07000000
+
+#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x00000008
+#define MACTX_PHY_DESC_RESERVED_2B_LSB 27
+#define MACTX_PHY_DESC_RESERVED_2B_MSB 28
+#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x18000000
+
+#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x00000008
+#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29
+#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29
+#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x20000000
+
+#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x00000008
+#define MACTX_PHY_DESC_MU_NDP_LSB 30
+#define MACTX_PHY_DESC_MU_NDP_MSB 30
+#define MACTX_PHY_DESC_MU_NDP_MASK 0x40000000
+
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x00000008
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31
+#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x80000000
+
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000c
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 0
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 7
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff
+
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000c
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 8
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 8
+#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x00000100
+
+#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000c
+#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 9
+#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 9
+#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x00000200
+
+#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000c
+#define MACTX_PHY_DESC_ANT_SEL_LSB 10
+#define MACTX_PHY_DESC_ANT_SEL_MSB 10
+#define MACTX_PHY_DESC_ANT_SEL_MASK 0x00000400
+
+#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000c
+#define MACTX_PHY_DESC_CP_SETTING_LSB 11
+#define MACTX_PHY_DESC_CP_SETTING_MSB 12
+#define MACTX_PHY_DESC_CP_SETTING_MASK 0x00001800
+
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000c
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 13
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 14
+#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x00006000
+
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000c
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 15
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 17
+#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x00038000
+
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000c
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 18
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 18
+#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x00040000
+
+#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000c
+#define MACTX_PHY_DESC_LTF_SIZE_LSB 19
+#define MACTX_PHY_DESC_LTF_SIZE_MSB 20
+#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x00180000
+
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000c
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 21
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 24
+#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e00000
+
+#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000c
+#define MACTX_PHY_DESC_RESERVED_3C_LSB 25
+#define MACTX_PHY_DESC_RESERVED_3C_MSB 25
+#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x02000000
+
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000c
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_su_mu.h b/drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_su_mu.h
new file mode 100644
index 0000000000000000000000000000000000000000..6ccc7d2e25485e250e8af493a0cd86023e7dc3e2
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_su_mu.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_U_SIG_EHT_SU_MU_H_
+#define _MACTX_U_SIG_EHT_SU_MU_H_
+
+#include "u_sig_eht_su_mu_info.h"
+#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2
+
+struct mactx_u_sig_eht_su_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details;
+#else
+ struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details;
+#endif
+};
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x00000007
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00000038
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000040
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00001f80
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x000fe000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x01f00000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x02000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0xfc000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 0
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 1
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 2
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 2
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x00000004
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 3
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 7
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 8
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 8
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x00000100
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 9
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 10
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x00000600
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 11
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 15
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 16
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 19
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f0000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 20
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 25
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 27
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 29
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x38000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 30
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 30
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x40000000
+
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_tb.h b/drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_tb.h
new file mode 100644
index 0000000000000000000000000000000000000000..a305e5640a0d74209cdcc422b930b6f28d534292
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_u_sig_eht_tb.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_U_SIG_EHT_TB_H_
+#define _MACTX_U_SIG_EHT_TB_H_
+
+#include "u_sig_eht_tb_info.h"
+#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2
+
+struct mactx_u_sig_eht_tb {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details;
+#else
+ struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details;
+#endif
+};
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x00000007
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x00000038
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000040
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00001f80
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x000fe000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x03f00000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x00000000
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0xfc000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 0
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 1
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 2
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 2
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x00000004
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 3
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 10
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f8
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 11
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 15
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f800
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 16
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 19
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f0000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 20
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 25
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 26
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 30
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c000000
+
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_common.h b/drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_common.h
new file mode 100644
index 0000000000000000000000000000000000000000..6ccbfc2e57fe305f7d5c3914c2bac5896405f4ca
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_common.h
@@ -0,0 +1,478 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_USER_DESC_COMMON_H_
+#define _MACTX_USER_DESC_COMMON_H_
+
+#include "unallocated_ru_160_info.h"
+#include "ru_allocation_160_info.h"
+#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16
+
+struct mactx_user_desc_common {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t num_users : 6,
+ reserved_0b : 5,
+ ltf_size : 2,
+ reserved_0c : 3,
+ he_stf_long : 1,
+ reserved_0d : 7,
+ num_users_he_sigb_band0 : 8;
+ uint32_t num_ltf_symbols : 3,
+ reserved_1a : 5,
+ num_users_he_sigb_band1 : 8,
+ reserved_1b : 16;
+ uint32_t packet_extension_a_factor : 2,
+ packet_extension_pe_disambiguity : 1,
+ packet_extension : 3,
+ reserved : 2,
+ he_sigb_dcm : 1,
+ reserved_2b : 7,
+ he_sigb_compression : 1,
+ reserved_2c : 15;
+ uint32_t he_sigb_0_mcs : 3,
+ reserved_3a : 13,
+ num_he_sigb_sym : 5,
+ center_ru_0 : 1,
+ center_ru_1 : 1,
+ reserved_3b : 1,
+ ftm_en : 1,
+ pe_nss : 3,
+ pe_ltf_size : 2,
+ pe_content : 1,
+ pe_chain_csd_en : 1;
+ struct ru_allocation_160_info ru_allocation_0123_details;
+ struct ru_allocation_160_info ru_allocation_4567_details;
+ struct unallocated_ru_160_info ru_allocation_160_0_details;
+ struct unallocated_ru_160_info ru_allocation_160_1_details;
+ uint32_t num_data_symbols : 16,
+ ndp_ru_tone_set_index : 7,
+ ndp_feedback_status : 1,
+ doppler_indication : 1,
+ reserved_14a : 7;
+ uint32_t spatial_reuse : 16,
+ reserved_15a : 16;
+#else
+ uint32_t num_users_he_sigb_band0 : 8,
+ reserved_0d : 7,
+ he_stf_long : 1,
+ reserved_0c : 3,
+ ltf_size : 2,
+ reserved_0b : 5,
+ num_users : 6;
+ uint32_t reserved_1b : 16,
+ num_users_he_sigb_band1 : 8,
+ reserved_1a : 5,
+ num_ltf_symbols : 3;
+ uint32_t reserved_2c : 15,
+ he_sigb_compression : 1,
+ reserved_2b : 7,
+ he_sigb_dcm : 1,
+ reserved : 2,
+ packet_extension : 3,
+ packet_extension_pe_disambiguity : 1,
+ packet_extension_a_factor : 2;
+ uint32_t pe_chain_csd_en : 1,
+ pe_content : 1,
+ pe_ltf_size : 2,
+ pe_nss : 3,
+ ftm_en : 1,
+ reserved_3b : 1,
+ center_ru_1 : 1,
+ center_ru_0 : 1,
+ num_he_sigb_sym : 5,
+ reserved_3a : 13,
+ he_sigb_0_mcs : 3;
+ struct ru_allocation_160_info ru_allocation_0123_details;
+ struct ru_allocation_160_info ru_allocation_4567_details;
+ struct unallocated_ru_160_info ru_allocation_160_0_details;
+ struct unallocated_ru_160_info ru_allocation_160_1_details;
+ uint32_t reserved_14a : 7,
+ doppler_indication : 1,
+ ndp_feedback_status : 1,
+ ndp_ru_tone_set_index : 7,
+ num_data_symbols : 16;
+ uint32_t reserved_15a : 16,
+ spatial_reuse : 16;
+#endif
+};
+
+#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x00000000
+#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0
+#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5
+#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x0000003f
+
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x00000000
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10
+#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x000007c0
+
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x00000000
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12
+#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x00001800
+
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x00000000
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15
+#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x0000e000
+
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x00000000
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16
+#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x00010000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x00000000
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23
+#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x00fe0000
+
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x00000000
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0xff000000
+
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x00000004
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 0
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 2
+#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x00000007
+
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x00000004
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 3
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 7
+#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f8
+
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x00000004
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 8
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 15
+#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff00
+
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x00000004
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 16
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 31
+#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff0000
+
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000008
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x00000003
+
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000008
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000004
+
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x00000008
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5
+#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x00000038
+
+#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x00000008
+#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6
+#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7
+#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x000000c0
+
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x00000008
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8
+#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x00000100
+
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x00000008
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15
+#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x0000fe00
+
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x00000008
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16
+#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x00010000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x00000008
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31
+#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0xfffe0000
+
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000c
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 0
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 2
+#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x00000007
+
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000c
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 3
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 15
+#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff8
+
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000c
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 16
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 20
+#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f0000
+
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000c
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 21
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 21
+#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x00200000
+
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000c
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 22
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 22
+#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x00400000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000c
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 23
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 23
+#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x00800000
+
+#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000c
+#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 24
+#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 24
+#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x01000000
+
+#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000c
+#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 25
+#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 27
+#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e000000
+
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000c
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 28
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 29
+#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x30000000
+
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000c
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 30
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 30
+#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x40000000
+
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000c
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 31
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 31
+#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x80000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x00000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x00000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x00000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x00fc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000010
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x00000014
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x00000014
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x00000014
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x00000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x00000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x00000018
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0xfffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000001c
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000001c
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000001c
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x00000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x00000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x00000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x00fc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000020
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x00000024
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x00000024
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x00000024
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x00000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x00000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x00000028
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0xfffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000002c
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000002c
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 9
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 17
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000002c
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 18
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x00000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x00000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x00000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x00000030
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0xff000000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x00000034
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 0
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 7
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x00000034
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 8
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 15
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff00
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x00000034
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 16
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 23
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff0000
+
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x00000034
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 24
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 31
+#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff000000
+
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x00000038
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15
+#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x0000ffff
+
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x00000038
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22
+#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x007f0000
+
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x00000038
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23
+#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x00800000
+
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x00000038
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24
+#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x01000000
+
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x00000038
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31
+#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0xfe000000
+
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000003c
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 0
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 15
+#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff
+
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000003c
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 16
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 31
+#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_per_user.h b/drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_per_user.h
new file mode 100644
index 0000000000000000000000000000000000000000..7e70429874b080c8e5bb4efa68daa5d23e57e553
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_user_desc_per_user.h
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_USER_DESC_PER_USER_H_
+#define _MACTX_USER_DESC_PER_USER_H_
+
+#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4
+
+struct mactx_user_desc_per_user {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t psdu_length : 24,
+ reserved_0a : 8;
+ uint32_t ru_start_index : 8,
+ ru_size : 4,
+ reserved_1b : 4,
+ ofdma_mu_mimo_enabled : 1,
+ nss : 3,
+ stream_offset : 3,
+ reserved_1c : 1,
+ mcs : 4,
+ dcm : 1,
+ reserved_1d : 3;
+ uint32_t fec_type : 1,
+ reserved_2a : 7,
+ user_bf_type : 2,
+ reserved_2b : 6,
+ drop_user_cbf : 1,
+ reserved_2c : 7,
+ ldpc_extra_symbol : 1,
+ force_extra_symbol : 1,
+ reserved_2d : 6;
+ uint32_t sw_peer_id : 16,
+ per_user_subband_mask : 16;
+#else
+ uint32_t reserved_0a : 8,
+ psdu_length : 24;
+ uint32_t reserved_1d : 3,
+ dcm : 1,
+ mcs : 4,
+ reserved_1c : 1,
+ stream_offset : 3,
+ nss : 3,
+ ofdma_mu_mimo_enabled : 1,
+ reserved_1b : 4,
+ ru_size : 4,
+ ru_start_index : 8;
+ uint32_t reserved_2d : 6,
+ force_extra_symbol : 1,
+ ldpc_extra_symbol : 1,
+ reserved_2c : 7,
+ drop_user_cbf : 1,
+ reserved_2b : 6,
+ user_bf_type : 2,
+ reserved_2a : 7,
+ fec_type : 1;
+ uint32_t per_user_subband_mask : 16,
+ sw_peer_id : 16;
+#endif
+};
+
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x00000000
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23
+#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x00ffffff
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x00000000
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31
+#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0xff000000
+
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x00000004
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 0
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 7
+#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff
+
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x00000004
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 8
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 11
+#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f00
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x00000004
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 12
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 15
+#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f000
+
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x00000004
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 16
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 16
+#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x00010000
+
+#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x00000004
+#define MACTX_USER_DESC_PER_USER_NSS_LSB 17
+#define MACTX_USER_DESC_PER_USER_NSS_MSB 19
+#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e0000
+
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x00000004
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 20
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 22
+#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x00700000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x00000004
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 23
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 23
+#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x00800000
+
+#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x00000004
+#define MACTX_USER_DESC_PER_USER_MCS_LSB 24
+#define MACTX_USER_DESC_PER_USER_MCS_MSB 27
+#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x0f000000
+
+#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x00000004
+#define MACTX_USER_DESC_PER_USER_DCM_LSB 28
+#define MACTX_USER_DESC_PER_USER_DCM_MSB 28
+#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x10000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x00000004
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 29
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 31
+#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xe0000000
+
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x00000008
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0
+#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x00000001
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x00000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 7
+#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x000000fe
+
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x00000008
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9
+#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x00000300
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x00000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 10
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15
+#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x0000fc00
+
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x00000008
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16
+#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x00010000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET 0x00000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB 17
+#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB 23
+#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK 0x00fe0000
+
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x00000008
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24
+#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x01000000
+
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x00000008
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25
+#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x02000000
+
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x00000008
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 26
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31
+#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0xfc000000
+
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000c
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 0
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 15
+#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff
+
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000c
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 16
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 31
+#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_a.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_a.h
new file mode 100644
index 0000000000000000000000000000000000000000..3252a84ea556520f2563d26e904fbdc7d86adeea
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_a.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_A_H_
+#define _MACTX_VHT_SIG_A_H_
+
+#include "vht_sig_a_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2
+
+struct mactx_vht_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct vht_sig_a_info mactx_vht_sig_a_info_details;
+#else
+ struct vht_sig_a_info mactx_vht_sig_a_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 1
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 2
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 3
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 7
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 8
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 9
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 17
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 23
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 30
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f000000
+
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu160.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu160.h
new file mode 100644
index 0000000000000000000000000000000000000000..b26ede5f8f3b18b69ae236ac743ebd9009deffec
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu160.h
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_MU160_H_
+#define _MACTX_VHT_SIG_B_MU160_H_
+
+#include "vht_sig_b_mu160_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8
+
+struct mactx_vht_sig_b_mu160 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details;
+#else
+ struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0xe0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0xe0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x00000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x00000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x00000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x00000010
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0xe0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x00000014
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x00000014
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x00000014
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x00000014
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000001c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 0
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 18
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000001c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 19
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 22
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x00780000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000001c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 23
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 28
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000001c
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 29
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 31
+#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu20.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu20.h
new file mode 100644
index 0000000000000000000000000000000000000000..994a1ae4c235bfbf9e885bb1915a9ca035c1ec0e
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu20.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_MU20_H_
+#define _MACTX_VHT_SIG_B_MU20_H_
+
+#include "vht_sig_b_mu20_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 1
+
+struct mactx_vht_sig_b_mu20 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details;
+#else
+ struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x0000ffff
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x000f0000
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x1c000000
+
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31
+#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0xe0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu40.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu40.h
new file mode 100644
index 0000000000000000000000000000000000000000..bdbe562d6ad97a53dcf9aae32020e2db6c458610
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu40.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_MU40_H_
+#define _MACTX_VHT_SIG_B_MU40_H_
+
+#include "vht_sig_b_mu40_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2
+
+struct mactx_vht_sig_b_mu40 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details;
+#else
+ struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x0001ffff
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x001e0000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x07e00000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x18000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 0
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 16
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 17
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 20
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e0000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 21
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 26
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e00000
+
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 27
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 31
+#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf8000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu80.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu80.h
new file mode 100644
index 0000000000000000000000000000000000000000..e150bf89b643f4f7b720ed531dfc08450e758516
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_mu80.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_MU80_H_
+#define _MACTX_VHT_SIG_B_MU80_H_
+
+#include "vht_sig_b_mu80_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4
+
+struct mactx_vht_sig_b_mu80 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details;
+#else
+ struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x00780000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0xe0000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 0
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 18
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 19
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 22
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x00780000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 23
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 28
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 29
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 31
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe0000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x00780000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 0
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 18
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 19
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 22
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x00780000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 23
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 28
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 29
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 31
+#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su160.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su160.h
new file mode 100644
index 0000000000000000000000000000000000000000..edde887c102b008e5f14f89ac05f82e9985bdaaa
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su160.h
@@ -0,0 +1,232 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_SU160_H_
+#define _MACTX_VHT_SIG_B_SU160_H_
+
+#include "vht_sig_b_su160_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8
+
+struct mactx_vht_sig_b_su160 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details;
+#else
+ struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x00000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x00000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x00000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x00000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x00000010
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x00000014
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x00000014
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x00000014
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x00000014
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x00000014
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x00000018
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000001c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 0
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 20
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 21
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 22
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000001c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 23
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 28
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000001c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 29
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 30
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x60000000
+
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000001c
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 31
+#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su20.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su20.h
new file mode 100644
index 0000000000000000000000000000000000000000..3543c7f7057502200dcf80f0db9593771dc3e8f5
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su20.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_SU20_H_
+#define _MACTX_VHT_SIG_B_SU20_H_
+
+#include "vht_sig_b_su20_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 1
+
+struct mactx_vht_sig_b_su20 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details;
+#else
+ struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x0001ffff
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x000e0000
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x7c000000
+
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31
+#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su40.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su40.h
new file mode 100644
index 0000000000000000000000000000000000000000..f9136e2a6c2168d7766d92ccc8415c81861ef0cf
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su40.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_SU40_H_
+#define _MACTX_VHT_SIG_B_SU40_H_
+
+#include "vht_sig_b_su40_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2
+
+struct mactx_vht_sig_b_su40 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details;
+#else
+ struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x00180000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x07e00000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x78000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 0
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 18
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 19
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 20
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x00180000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 21
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 26
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e00000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 27
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 30
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x78000000
+
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 31
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 31
+#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su80.h b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su80.h
new file mode 100644
index 0000000000000000000000000000000000000000..881918cbb8657aa1f93a82632a7f829147d06deb
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mactx_vht_sig_b_su80.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MACTX_VHT_SIG_B_SU80_H_
+#define _MACTX_VHT_SIG_B_SU80_H_
+
+#include "vht_sig_b_su80_info.h"
+#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4
+
+struct mactx_vht_sig_b_su80 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details;
+#else
+ struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details;
+#endif
+};
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x60000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x00000000
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 0
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 20
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 21
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 22
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 23
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 28
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 29
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 30
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x60000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x00000004
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x60000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x00000008
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x80000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 0
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 20
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 21
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 22
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x00600000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 23
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 28
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 29
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 30
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x60000000
+
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000c
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 31
+#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mlo_sta_id_details.h b/drivers/staging/fw-api/hw/peach/v1/mlo_sta_id_details.h
new file mode 100644
index 0000000000000000000000000000000000000000..50448cc4e075984b568ae4bf06f78a85f6c365a8
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mlo_sta_id_details.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MLO_STA_ID_DETAILS_H_
+#define _MLO_STA_ID_DETAILS_H_
+
+#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1
+
+struct mlo_sta_id_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint16_t nstr_mlo_sta_id : 10,
+ block_self_ml_sync : 1,
+ block_partner_ml_sync : 1,
+ nstr_mlo_sta_id_valid : 1,
+ reserved_0a : 3;
+#else
+ uint16_t reserved_0a : 3,
+ nstr_mlo_sta_id_valid : 1,
+ block_partner_ml_sync : 1,
+ block_self_ml_sync : 1,
+ nstr_mlo_sta_id : 10;
+#endif
+};
+
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10
+#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12
+#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13
+#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15
+#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mon_buffer_addr.h b/drivers/staging/fw-api/hw/peach/v1/mon_buffer_addr.h
new file mode 100644
index 0000000000000000000000000000000000000000..7c3c60a57d8f768c61f7f28de0c03b801d78198b
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mon_buffer_addr.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MON_BUFFER_ADDR_H_
+#define _MON_BUFFER_ADDR_H_
+
+#define NUM_OF_DWORDS_MON_BUFFER_ADDR 3
+
+struct mon_buffer_addr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t buffer_virt_addr_31_0 : 32;
+ uint32_t buffer_virt_addr_63_32 : 32;
+ uint32_t dma_length : 12,
+ reserved_2a : 4,
+ msdu_continuation : 1,
+ truncated : 1,
+ reserved_2b : 14;
+#else
+ uint32_t buffer_virt_addr_31_0 : 32;
+ uint32_t buffer_virt_addr_63_32 : 32;
+ uint32_t reserved_2b : 14,
+ truncated : 1,
+ msdu_continuation : 1,
+ reserved_2a : 4,
+ dma_length : 12;
+#endif
+};
+
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
+
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 0
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 31
+#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
+
+#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x00000008
+#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0
+#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11
+#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x00000fff
+
+#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x00000008
+#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12
+#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15
+#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x0000f000
+
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x00000008
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16
+#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x00010000
+
+#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x00000008
+#define MON_BUFFER_ADDR_TRUNCATED_LSB 17
+#define MON_BUFFER_ADDR_TRUNCATED_MSB 17
+#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x00020000
+
+#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x00000008
+#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18
+#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31
+#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0xfffc0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mon_destination_ring.h b/drivers/staging/fw-api/hw/peach/v1/mon_destination_ring.h
new file mode 100644
index 0000000000000000000000000000000000000000..e1feca4d70fd83b6041eef5ab995a7d381e239b3
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mon_destination_ring.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MON_DESTINATION_RING_H_
+#define _MON_DESTINATION_RING_H_
+
+#define NUM_OF_DWORDS_MON_DESTINATION_RING 4
+
+struct mon_destination_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t stat_buf_virt_addr_31_0 : 32;
+ uint32_t stat_buf_virt_addr_63_32 : 32;
+ uint32_t ppdu_id : 32;
+ uint32_t end_offset : 12,
+ reserved_3a : 2,
+ link_info : 2,
+ end_reason : 2,
+ initiator : 1,
+ empty_descriptor : 1,
+ ring_id : 8,
+ looping_count : 4;
+#else
+ uint32_t stat_buf_virt_addr_31_0 : 32;
+ uint32_t stat_buf_virt_addr_63_32 : 32;
+ uint32_t ppdu_id : 32;
+ uint32_t looping_count : 4,
+ ring_id : 8,
+ empty_descriptor : 1,
+ initiator : 1,
+ end_reason : 2,
+ link_info : 2,
+ reserved_3a : 2,
+ end_offset : 12;
+#endif
+};
+
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff
+
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31
+#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff
+
+#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008
+#define MON_DESTINATION_RING_PPDU_ID_LSB 0
+#define MON_DESTINATION_RING_PPDU_ID_MSB 31
+#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff
+
+#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c
+#define MON_DESTINATION_RING_END_OFFSET_LSB 0
+#define MON_DESTINATION_RING_END_OFFSET_MSB 11
+#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff
+
+#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c
+#define MON_DESTINATION_RING_RESERVED_3A_LSB 12
+#define MON_DESTINATION_RING_RESERVED_3A_MSB 13
+#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x00003000
+
+#define MON_DESTINATION_RING_LINK_INFO_OFFSET 0x0000000c
+#define MON_DESTINATION_RING_LINK_INFO_LSB 14
+#define MON_DESTINATION_RING_LINK_INFO_MSB 15
+#define MON_DESTINATION_RING_LINK_INFO_MASK 0x0000c000
+
+#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c
+#define MON_DESTINATION_RING_END_REASON_LSB 16
+#define MON_DESTINATION_RING_END_REASON_MSB 17
+#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000
+
+#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c
+#define MON_DESTINATION_RING_INITIATOR_LSB 18
+#define MON_DESTINATION_RING_INITIATOR_MSB 18
+#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000
+
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19
+#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000
+
+#define MON_DESTINATION_RING_RING_ID_OFFSET 0x0000000c
+#define MON_DESTINATION_RING_RING_ID_LSB 20
+#define MON_DESTINATION_RING_RING_ID_MSB 27
+#define MON_DESTINATION_RING_RING_ID_MASK 0x0ff00000
+
+#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c
+#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28
+#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31
+#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mon_drop.h b/drivers/staging/fw-api/hw/peach/v1/mon_drop.h
new file mode 100644
index 0000000000000000000000000000000000000000..99d782f9f5850b6c22cd424dfe9e71d418cb9b59
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mon_drop.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MON_DROP_H_
+#define _MON_DROP_H_
+
+#define NUM_OF_DWORDS_MON_DROP 2
+
+struct mon_drop {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t ppdu_id : 32;
+ uint32_t ppdu_drop_cnt : 10,
+ mpdu_drop_cnt : 10,
+ tlv_drop_cnt : 10,
+ end_of_ppdu_seen : 1,
+ reserved_1a : 1;
+#else
+ uint32_t ppdu_id : 32;
+ uint32_t reserved_1a : 1,
+ end_of_ppdu_seen : 1,
+ tlv_drop_cnt : 10,
+ mpdu_drop_cnt : 10,
+ ppdu_drop_cnt : 10;
+#endif
+};
+
+#define MON_DROP_PPDU_ID_OFFSET 0x00000000
+#define MON_DROP_PPDU_ID_LSB 0
+#define MON_DROP_PPDU_ID_MSB 31
+#define MON_DROP_PPDU_ID_MASK 0xffffffff
+
+#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x00000004
+#define MON_DROP_PPDU_DROP_CNT_LSB 0
+#define MON_DROP_PPDU_DROP_CNT_MSB 9
+#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff
+
+#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x00000004
+#define MON_DROP_MPDU_DROP_CNT_LSB 10
+#define MON_DROP_MPDU_DROP_CNT_MSB 19
+#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc00
+
+#define MON_DROP_TLV_DROP_CNT_OFFSET 0x00000004
+#define MON_DROP_TLV_DROP_CNT_LSB 20
+#define MON_DROP_TLV_DROP_CNT_MSB 29
+#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff00000
+
+#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x00000004
+#define MON_DROP_END_OF_PPDU_SEEN_LSB 30
+#define MON_DROP_END_OF_PPDU_SEEN_MSB 30
+#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x40000000
+
+#define MON_DROP_RESERVED_1A_OFFSET 0x00000004
+#define MON_DROP_RESERVED_1A_LSB 31
+#define MON_DROP_RESERVED_1A_MSB 31
+#define MON_DROP_RESERVED_1A_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/mon_ingress_ring.h b/drivers/staging/fw-api/hw/peach/v1/mon_ingress_ring.h
new file mode 100644
index 0000000000000000000000000000000000000000..f284a530bb58abccf70bcfc859ce04df9192ce84
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/mon_ingress_ring.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _MON_INGRESS_RING_H_
+#define _MON_INGRESS_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_MON_INGRESS_RING 4
+
+struct mon_ingress_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct buffer_addr_info buffer_addr_info_details;
+ uint32_t buffer_virt_addr_31_0 : 32;
+ uint32_t buffer_virt_addr_63_32 : 32;
+#else
+ struct buffer_addr_info buffer_addr_info_details;
+ uint32_t buffer_virt_addr_31_0 : 32;
+ uint32_t buffer_virt_addr_63_32 : 32;
+#endif
+};
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31
+#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
+
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31
+#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/msmhwiobase.h b/drivers/staging/fw-api/hw/peach/v1/msmhwiobase.h
new file mode 100644
index 0000000000000000000000000000000000000000..a251141f304a17491b6d3adf75db22dffe889271
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/msmhwiobase.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef __MSMHWIOBASE_H__
+#define __MSMHWIOBASE_H__
+
+#define WCSS_WCSS_BASE 0x00000000
+#define WCSS_WCSS_BASE_SIZE 0x01000000
+#define WCSS_WCSS_BASE_PHYS 0x00000000
+
+#define QDSS_STM_SIZE_BASE 0x00100000
+#define QDSS_STM_SIZE_BASE_SIZE 0x100000000
+#define QDSS_STM_SIZE_BASE_PHYS 0x00100000
+
+#define BOOT_ROM_SIZE_BASE 0x00200000
+#define BOOT_ROM_SIZE_BASE_SIZE 0x100000000
+#define BOOT_ROM_SIZE_BASE_PHYS 0x00200000
+
+#define SYSTEM_IRAM_SIZE_BASE 0x00400000
+#define SYSTEM_IRAM_SIZE_BASE_SIZE 0x100000000
+#define SYSTEM_IRAM_SIZE_BASE_PHYS 0x00400000
+
+#define BOOT_ROM_START_ADDRESS_BASE 0x01200000
+#define BOOT_ROM_START_ADDRESS_BASE_SIZE 0x100000000
+#define BOOT_ROM_START_ADDRESS_BASE_PHYS 0x01200000
+
+#define BOOT_ROM_END_ADDRESS_BASE 0x013fffff
+#define BOOT_ROM_END_ADDRESS_BASE_SIZE 0x100000000
+#define BOOT_ROM_END_ADDRESS_BASE_PHYS 0x013fffff
+
+#define SYSTEM_IRAM_START_ADDRESS_BASE 0x01400000
+#define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE 0x100000000
+#define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS 0x01400000
+
+#define SYSTEM_IRAM_END_ADDRESS_BASE 0x017fffff
+#define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE 0x100000000
+#define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS 0x017fffff
+
+#define QDSS_STM_BASE 0x01800000
+#define QDSS_STM_BASE_SIZE 0x100000000
+#define QDSS_STM_BASE_PHYS 0x01800000
+
+#define QDSS_STM_END_BASE 0x018fffff
+#define QDSS_STM_END_BASE_SIZE 0x100000000
+#define QDSS_STM_END_BASE_PHYS 0x018fffff
+
+#define TLMM_BASE 0x01900000
+#define TLMM_BASE_SIZE 0x00200000
+#define TLMM_BASE_PHYS 0x01900000
+
+#define CORE_TOP_CSR_BASE 0x01b00000
+#define CORE_TOP_CSR_BASE_SIZE 0x00040000
+#define CORE_TOP_CSR_BASE_PHYS 0x01b00000
+
+#define BLSP1_BLSP_BASE 0x01b40000
+#define BLSP1_BLSP_BASE_SIZE 0x00040000
+#define BLSP1_BLSP_BASE_PHYS 0x01b40000
+
+#define SOC_WFSS_CE_REG_BASE 0x01b80000
+#define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000
+#define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000
+
+#define WL_TLMM_BASE 0x01bc0000
+#define WL_TLMM_BASE_SIZE 0x00020000
+#define WL_TLMM_BASE_PHYS 0x01bc0000
+
+#define MEMSS_CSR_BASE 0x01be0000
+#define MEMSS_CSR_BASE_SIZE 0x0000001c
+#define MEMSS_CSR_BASE_PHYS 0x01be0000
+
+#define TSENS_SROT_BASE 0x01bf0000
+#define TSENS_SROT_BASE_SIZE 0x00001000
+#define TSENS_SROT_BASE_PHYS 0x01bf0000
+
+#define TSENS_TM_BASE 0x01bf1000
+#define TSENS_TM_BASE_SIZE 0x00001000
+#define TSENS_TM_BASE_PHYS 0x01bf1000
+
+#define QDSS_APB_DEC_QDSS_APB_BASE 0x01c00000
+#define QDSS_APB_DEC_QDSS_APB_BASE_SIZE 0x00080000
+#define QDSS_APB_DEC_QDSS_APB_BASE_PHYS 0x01c00000
+
+#define QDSS_WRAPPER_TOP_BASE 0x01c80000
+#define QDSS_WRAPPER_TOP_BASE_SIZE 0x0007fffd
+#define QDSS_WRAPPER_TOP_BASE_PHYS 0x01c80000
+
+#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE 0x01d00000
+#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE 0x00100000
+#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS 0x01d00000
+
+#define PCIE_PCIE_TOP_WRAPPER_BASE 0x01e00000
+#define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000
+#define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000
+
+#define SECURITY_CONTROL_WLAN_BASE 0x01e20000
+#define SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000
+#define SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000
+
+#define EDPD_CAL_ACC_BASE 0x01e28000
+#define EDPD_CAL_ACC_BASE_SIZE 0x00003000
+#define EDPD_CAL_ACC_BASE_PHYS 0x01e28000
+
+#define CPR_CX_CPR3_BASE 0x01e30000
+#define CPR_CX_CPR3_BASE_SIZE 0x00004000
+#define CPR_CX_CPR3_BASE_PHYS 0x01e30000
+
+#define CPR_MX_CPR3_BASE 0x01e34000
+#define CPR_MX_CPR3_BASE_SIZE 0x00004000
+#define CPR_MX_CPR3_BASE_PHYS 0x01e34000
+
+#define GCC_GCC_BASE 0x01e40000
+#define GCC_GCC_BASE_SIZE 0x000003e8
+#define GCC_GCC_BASE_PHYS 0x01e40000
+
+#define PRNG_PRNG_TOP_BASE 0x01e50000
+#define PRNG_PRNG_TOP_BASE_SIZE 0x00010000
+#define PRNG_PRNG_TOP_BASE_PHYS 0x01e50000
+
+#define PCNOC_0_BUS_TIMEOUT_BASE 0x01e60000
+#define PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000
+#define PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000
+
+#define PCNOC_1_BUS_TIMEOUT_BASE 0x01e61000
+#define PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000
+#define PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000
+
+#define PCNOC_2_BUS_TIMEOUT_BASE 0x01e62000
+#define PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000
+#define PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000
+
+#define PCNOC_3_BUS_TIMEOUT_BASE 0x01e63000
+#define PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000
+#define PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000
+
+#define RRI_PREFETCH_REG_BASE 0x01e70000
+#define RRI_PREFETCH_REG_BASE_SIZE 0x00010000
+#define RRI_PREFETCH_REG_BASE_PHYS 0x01e70000
+
+#define SYSTEM_NOC_BASE 0x01e80000
+#define SYSTEM_NOC_BASE_SIZE 0x0000a000
+#define SYSTEM_NOC_BASE_PHYS 0x01e80000
+
+#define PC_NOC_BASE 0x01f00000
+#define PC_NOC_BASE_SIZE 0x00003880
+#define PC_NOC_BASE_PHYS 0x01f00000
+
+#define WLAON_WL_AON_REG_BASE 0x01f80000
+#define WLAON_WL_AON_REG_BASE_SIZE 0x000007c8
+#define WLAON_WL_AON_REG_BASE_PHYS 0x01f80000
+
+#define SYSPM_SYSPM_REG_BASE 0x01f82000
+#define SYSPM_SYSPM_REG_BASE_SIZE 0x00001000
+#define SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000
+
+#define PMU_WLAN_PMU_TOP_BASE 0x01f88000
+#define PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000340
+#define PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000
+
+#define PMU_NOC_BASE 0x01f8a000
+#define PMU_NOC_BASE_SIZE 0x00000080
+#define PMU_NOC_BASE_PHYS 0x01f8a000
+
+#define PCIE_ATU_REGION_BASE 0x04000000
+#define PCIE_ATU_REGION_BASE_SIZE 0x100000000
+#define PCIE_ATU_REGION_BASE_PHYS 0x04000000
+
+#define PCIE_ATU_REGION_SIZE_BASE 0x40000000
+#define PCIE_ATU_REGION_SIZE_BASE_SIZE 0x100000000
+#define PCIE_ATU_REGION_SIZE_BASE_PHYS 0x40000000
+
+#define PCIE_ATU_REGION_END_BASE 0x43ffffff
+#define PCIE_ATU_REGION_END_BASE_SIZE 0x100000000
+#define PCIE_ATU_REGION_END_BASE_PHYS 0x43ffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/msmhwioreg.h b/drivers/staging/fw-api/hw/peach/v1/msmhwioreg.h
new file mode 100644
index 0000000000000000000000000000000000000000..4953fc29e4827685153d33d9186bb2b61cdb823e
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/msmhwioreg.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __MSMHWIOREG_H__
+#define __MSMHWIOREG_H__
+
+#include "msmhwiobase.h"
+
+#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000408)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0xfffffffc
+#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 0x2
+#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000000)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \
+ in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \
+ in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \
+ out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000004)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \
+ in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \
+ in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \
+ out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000000)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \
+ in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \
+ in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \
+ out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000004)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \
+ in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \
+ in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \
+ out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000400)
+#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000000)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \
+ in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \
+ in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \
+ out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000004)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \
+ in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \
+ in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \
+ out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \
+ out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000400)
+#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000058)
+
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/no_ack_report.h b/drivers/staging/fw-api/hw/peach/v1/no_ack_report.h
new file mode 100644
index 0000000000000000000000000000000000000000..c80f32fe47d2c9905ac72fe9dbb417cfaa0828f9
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/no_ack_report.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _NO_ACK_REPORT_H_
+#define _NO_ACK_REPORT_H_
+
+#define NUM_OF_DWORDS_NO_ACK_REPORT 4
+
+struct no_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t no_ack_transmit_reason : 4,
+ macrx_abort_reason : 4,
+ phyrx_abort_reason : 8,
+ frame_control : 16;
+ uint32_t rx_ppdu_duration : 24,
+ sr_ppdu_during_obss : 1,
+ selfgen_response_reason_to_sr_ppdu : 4,
+ reserved_1 : 3;
+ uint32_t pre_bt_broadcast_status_details : 12,
+ first_bt_broadcast_status_details : 12,
+ reserved_2 : 8;
+ uint32_t second_bt_broadcast_status_details : 12,
+ reserved_3 : 20;
+#else
+ uint32_t frame_control : 16,
+ phyrx_abort_reason : 8,
+ macrx_abort_reason : 4,
+ no_ack_transmit_reason : 4;
+ uint32_t reserved_1 : 3,
+ selfgen_response_reason_to_sr_ppdu : 4,
+ sr_ppdu_during_obss : 1,
+ rx_ppdu_duration : 24;
+ uint32_t reserved_2 : 8,
+ first_bt_broadcast_status_details : 12,
+ pre_bt_broadcast_status_details : 12;
+ uint32_t reserved_3 : 20,
+ second_bt_broadcast_status_details : 12;
+#endif
+};
+
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3
+#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f
+
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7
+#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0
+
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15
+#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00
+
+#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000
+#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16
+#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31
+#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000
+
+#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004
+#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0
+#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23
+#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff
+
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24
+#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000
+
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28
+#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000
+
+#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004
+#define NO_ACK_REPORT_RESERVED_1_LSB 29
+#define NO_ACK_REPORT_RESERVED_1_MSB 31
+#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000
+
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11
+#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
+
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23
+#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000
+
+#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008
+#define NO_ACK_REPORT_RESERVED_2_LSB 24
+#define NO_ACK_REPORT_RESERVED_2_MSB 31
+#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000
+
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11
+#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
+
+#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c
+#define NO_ACK_REPORT_RESERVED_3_LSB 12
+#define NO_ACK_REPORT_RESERVED_3_MSB 31
+#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/ofdma_trigger_details.h b/drivers/staging/fw-api/hw/peach/v1/ofdma_trigger_details.h
new file mode 100644
index 0000000000000000000000000000000000000000..e842d347bb56a31c71e9e199d53fca63dda4eadf
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/ofdma_trigger_details.h
@@ -0,0 +1,834 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _OFDMA_TRIGGER_DETAILS_H_
+#define _OFDMA_TRIGGER_DETAILS_H_
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22
+
+struct ofdma_trigger_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t ax_trigger_source : 1,
+ rx_trigger_frame_user_source : 2,
+ received_bandwidth : 3,
+ txop_duration_all_ones : 1,
+ eht_trigger_response : 1,
+ pre_rssi_comb : 8,
+ rssi_comb : 8,
+ rxpcu_pcie_l0_req_duration : 8;
+ uint32_t he_trigger_ul_ppdu_length : 5,
+ he_trigger_ru_allocation : 8,
+ he_trigger_dl_tx_power : 5,
+ he_trigger_ul_target_rssi : 5,
+ he_trigger_ul_mcs : 2,
+ he_trigger_reserved : 1,
+ bss_color : 6;
+ uint32_t trigger_type : 4,
+ lsig_response_length : 12,
+ cascade_indication : 1,
+ carrier_sense : 1,
+ bandwidth : 2,
+ cp_ltf_size : 2,
+ mu_mimo_ltf_mode : 1,
+ number_of_ltfs : 3,
+ stbc : 1,
+ ldpc_extra_symbol : 1,
+ ap_tx_power_lsb_part : 4;
+ uint32_t ap_tx_power_msb_part : 2,
+ packet_extension_a_factor : 2,
+ packet_extension_pe_disambiguity : 1,
+ spatial_reuse : 16,
+ doppler : 1,
+ he_siga_reserved : 9,
+ reserved_3b : 1;
+ uint32_t aid12 : 12,
+ ru_allocation : 9,
+ mcs : 4,
+ dcm : 1,
+ start_spatial_stream : 3,
+ number_of_spatial_stream : 3;
+ uint32_t target_rssi : 7,
+ coding_type : 1,
+ mpdu_mu_spacing_factor : 2,
+ tid_aggregation_limit : 3,
+ reserved_5b : 1,
+ prefered_ac : 2,
+ bar_control_ack_policy : 1,
+ bar_control_multi_tid : 1,
+ bar_control_compressed_bitmap : 1,
+ bar_control_reserved : 9,
+ bar_control_tid_info : 4;
+ uint32_t nr0_per_tid_info_reserved : 12,
+ nr0_per_tid_info_tid_value : 4,
+ nr0_start_seq_ctrl_frag_number : 4,
+ nr0_start_seq_ctrl_start_seq_number : 12;
+ uint32_t nr1_per_tid_info_reserved : 12,
+ nr1_per_tid_info_tid_value : 4,
+ nr1_start_seq_ctrl_frag_number : 4,
+ nr1_start_seq_ctrl_start_seq_number : 12;
+ uint32_t nr2_per_tid_info_reserved : 12,
+ nr2_per_tid_info_tid_value : 4,
+ nr2_start_seq_ctrl_frag_number : 4,
+ nr2_start_seq_ctrl_start_seq_number : 12;
+ uint32_t nr3_per_tid_info_reserved : 12,
+ nr3_per_tid_info_tid_value : 4,
+ nr3_start_seq_ctrl_frag_number : 4,
+ nr3_start_seq_ctrl_start_seq_number : 12;
+ uint32_t nr4_per_tid_info_reserved : 12,
+ nr4_per_tid_info_tid_value : 4,
+ nr4_start_seq_ctrl_frag_number : 4,
+ nr4_start_seq_ctrl_start_seq_number : 12;
+ uint32_t nr5_per_tid_info_reserved : 12,
+ nr5_per_tid_info_tid_value : 4,
+ nr5_start_seq_ctrl_frag_number : 4,
+ nr5_start_seq_ctrl_start_seq_number : 12;
+ uint32_t nr6_per_tid_info_reserved : 12,
+ nr6_per_tid_info_tid_value : 4,
+ nr6_start_seq_ctrl_frag_number : 4,
+ nr6_start_seq_ctrl_start_seq_number : 12;
+ uint32_t nr7_per_tid_info_reserved : 12,
+ nr7_per_tid_info_tid_value : 4,
+ nr7_start_seq_ctrl_frag_number : 4,
+ nr7_start_seq_ctrl_start_seq_number : 12;
+ uint32_t fb_segment_retransmission_bitmap : 8,
+ reserved_14a : 2,
+ u_sig_puncture_pattern_encoding : 6,
+ dot11be_puncture_bitmap : 16;
+ uint32_t rx_chain_mask : 8,
+ rx_duration_field : 16,
+ scrambler_seed : 7,
+ rx_chain_mask_type : 1;
+ struct mlo_sta_id_details mlo_sta_id_details_rx;
+ uint16_t normalized_pre_rssi_comb : 8,
+ normalized_rssi_comb : 8;
+ uint32_t sw_peer_id : 16,
+ response_tx_duration : 16;
+ uint32_t __reserved_g_0005_trigger_subtype : 4,
+ tbr_trigger_common_info_79_68 : 12,
+ tbr_trigger_sound_reserved_20_12 : 9,
+ i2r_rep : 3,
+ tbr_trigger_sound_reserved_25_24 : 2,
+ reserved_18a : 1,
+ qos_null_only_response_tx : 1;
+ uint32_t tbr_trigger_sound_sac : 16,
+ reserved_19a : 8,
+ u_sig_reserved2 : 5,
+ reserved_19b : 3;
+ uint32_t eht_special_aid12 : 12,
+ phy_version : 3,
+ bandwidth_ext : 2,
+ eht_spatial_reuse : 8,
+ u_sig_reserved1 : 7;
+ uint32_t eht_trigger_special_user_info_71_40 : 32;
+#else
+ uint32_t rxpcu_pcie_l0_req_duration : 8,
+ rssi_comb : 8,
+ pre_rssi_comb : 8,
+ eht_trigger_response : 1,
+ txop_duration_all_ones : 1,
+ received_bandwidth : 3,
+ rx_trigger_frame_user_source : 2,
+ ax_trigger_source : 1;
+ uint32_t bss_color : 6,
+ he_trigger_reserved : 1,
+ he_trigger_ul_mcs : 2,
+ he_trigger_ul_target_rssi : 5,
+ he_trigger_dl_tx_power : 5,
+ he_trigger_ru_allocation : 8,
+ he_trigger_ul_ppdu_length : 5;
+ uint32_t ap_tx_power_lsb_part : 4,
+ ldpc_extra_symbol : 1,
+ stbc : 1,
+ number_of_ltfs : 3,
+ mu_mimo_ltf_mode : 1,
+ cp_ltf_size : 2,
+ bandwidth : 2,
+ carrier_sense : 1,
+ cascade_indication : 1,
+ lsig_response_length : 12,
+ trigger_type : 4;
+ uint32_t reserved_3b : 1,
+ he_siga_reserved : 9,
+ doppler : 1,
+ spatial_reuse : 16,
+ packet_extension_pe_disambiguity : 1,
+ packet_extension_a_factor : 2,
+ ap_tx_power_msb_part : 2;
+ uint32_t number_of_spatial_stream : 3,
+ start_spatial_stream : 3,
+ dcm : 1,
+ mcs : 4,
+ ru_allocation : 9,
+ aid12 : 12;
+ uint32_t bar_control_tid_info : 4,
+ bar_control_reserved : 9,
+ bar_control_compressed_bitmap : 1,
+ bar_control_multi_tid : 1,
+ bar_control_ack_policy : 1,
+ prefered_ac : 2,
+ reserved_5b : 1,
+ tid_aggregation_limit : 3,
+ mpdu_mu_spacing_factor : 2,
+ coding_type : 1,
+ target_rssi : 7;
+ uint32_t nr0_start_seq_ctrl_start_seq_number : 12,
+ nr0_start_seq_ctrl_frag_number : 4,
+ nr0_per_tid_info_tid_value : 4,
+ nr0_per_tid_info_reserved : 12;
+ uint32_t nr1_start_seq_ctrl_start_seq_number : 12,
+ nr1_start_seq_ctrl_frag_number : 4,
+ nr1_per_tid_info_tid_value : 4,
+ nr1_per_tid_info_reserved : 12;
+ uint32_t nr2_start_seq_ctrl_start_seq_number : 12,
+ nr2_start_seq_ctrl_frag_number : 4,
+ nr2_per_tid_info_tid_value : 4,
+ nr2_per_tid_info_reserved : 12;
+ uint32_t nr3_start_seq_ctrl_start_seq_number : 12,
+ nr3_start_seq_ctrl_frag_number : 4,
+ nr3_per_tid_info_tid_value : 4,
+ nr3_per_tid_info_reserved : 12;
+ uint32_t nr4_start_seq_ctrl_start_seq_number : 12,
+ nr4_start_seq_ctrl_frag_number : 4,
+ nr4_per_tid_info_tid_value : 4,
+ nr4_per_tid_info_reserved : 12;
+ uint32_t nr5_start_seq_ctrl_start_seq_number : 12,
+ nr5_start_seq_ctrl_frag_number : 4,
+ nr5_per_tid_info_tid_value : 4,
+ nr5_per_tid_info_reserved : 12;
+ uint32_t nr6_start_seq_ctrl_start_seq_number : 12,
+ nr6_start_seq_ctrl_frag_number : 4,
+ nr6_per_tid_info_tid_value : 4,
+ nr6_per_tid_info_reserved : 12;
+ uint32_t nr7_start_seq_ctrl_start_seq_number : 12,
+ nr7_start_seq_ctrl_frag_number : 4,
+ nr7_per_tid_info_tid_value : 4,
+ nr7_per_tid_info_reserved : 12;
+ uint32_t dot11be_puncture_bitmap : 16,
+ u_sig_puncture_pattern_encoding : 6,
+ reserved_14a : 2,
+ fb_segment_retransmission_bitmap : 8;
+ uint32_t rx_chain_mask_type : 1,
+ scrambler_seed : 7,
+ rx_duration_field : 16,
+ rx_chain_mask : 8;
+ uint32_t normalized_rssi_comb : 8,
+ normalized_pre_rssi_comb : 8;
+ struct mlo_sta_id_details mlo_sta_id_details_rx;
+ uint32_t response_tx_duration : 16,
+ sw_peer_id : 16;
+ uint32_t qos_null_only_response_tx : 1,
+ reserved_18a : 1,
+ tbr_trigger_sound_reserved_25_24 : 2,
+ i2r_rep : 3,
+ tbr_trigger_sound_reserved_20_12 : 9,
+ tbr_trigger_common_info_79_68 : 12,
+ __reserved_g_0005_trigger_subtype : 4;
+ uint32_t reserved_19b : 3,
+ u_sig_reserved2 : 5,
+ reserved_19a : 8,
+ tbr_trigger_sound_sac : 16;
+ uint32_t u_sig_reserved1 : 7,
+ eht_spatial_reuse : 8,
+ bandwidth_ext : 2,
+ phy_version : 3,
+ eht_special_aid12 : 12;
+ uint32_t eht_trigger_special_user_info_71_40 : 32;
+#endif
+};
+
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0
+#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000001
+
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x00000000
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2
+#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x00000006
+
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x00000000
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5
+#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x00000038
+
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x00000000
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6
+#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x00000040
+
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x00000000
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x00000080
+
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x00000000
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15
+#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x0000ff00
+
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x00000000
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23
+#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x00ff0000
+
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x00000000
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31
+#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0xff000000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x00000004
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 0
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 4
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x00000004
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 5
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 12
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe0
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x00000004
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 13
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 17
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x00000004
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 18
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 22
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c0000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x00000004
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 23
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 24
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x01800000
+
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x00000004
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 25
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 25
+#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x02000000
+
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x00000004
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 26
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 31
+#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc000000
+
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x00000008
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3
+#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x0000000f
+
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000008
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15
+#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0000fff0
+
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x00000008
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16
+#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x00010000
+
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x00000008
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17
+#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x00020000
+
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x00000008
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x000c0000
+
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x00000008
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21
+#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x00300000
+
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x00000008
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22
+#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x00400000
+
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x00000008
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x03800000
+
+#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x00000008
+#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26
+#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26
+#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x04000000
+
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000008
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27
+#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x08000000
+
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x00000008
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0xf0000000
+
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000c
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 0
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 1
+#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x00000003
+
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000c
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 2
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 3
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c
+
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000c
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 4
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 4
+#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000010
+
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000c
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 5
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 20
+#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe0
+
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000c
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 21
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 21
+#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x00200000
+
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000c
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 22
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 30
+#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc00000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000c
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 31
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 31
+#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x80000000
+
+#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x00000010
+#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0
+#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11
+#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x00000010
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20
+#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x001ff000
+
+#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x00000010
+#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21
+#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24
+#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x01e00000
+
+#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x00000010
+#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25
+#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25
+#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x02000000
+
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x00000010
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28
+#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x1c000000
+
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x00000010
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31
+#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0xe0000000
+
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x00000014
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 0
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 6
+#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f
+
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x00000014
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 7
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 7
+#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x00000080
+
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x00000014
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 8
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 9
+#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x00000300
+
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x00000014
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 10
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 12
+#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c00
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x00000014
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 13
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 13
+#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x00002000
+
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x00000014
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 14
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 15
+#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x00000014
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 16
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 16
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x00010000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x00000014
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 17
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 17
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x00020000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x00000014
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 18
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 18
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x00040000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x00000014
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 19
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 27
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff80000
+
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x00000014
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 28
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 31
+#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf0000000
+
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x00000018
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x00000018
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15
+#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000018
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000018
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
+#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000001c
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 0
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 11
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000001c
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 12
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 15
+#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000001c
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000001c
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
+#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x00000020
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x00000020
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15
+#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000020
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000020
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
+#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x00000024
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 0
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 11
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x00000024
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 12
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 15
+#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000024
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000024
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
+#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x00000028
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x00000028
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15
+#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000028
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000028
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
+#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000002c
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 0
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 11
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000002c
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 12
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 15
+#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000002c
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000002c
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
+#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x00000030
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x00000030
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15
+#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000030
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000030
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
+#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x00000034
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 0
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 11
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x00000034
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 12
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 15
+#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000034
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000
+
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000034
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
+#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000
+
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x00000038
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7
+#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x000000ff
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x00000038
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9
+#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x00000300
+
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000038
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15
+#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000fc00
+
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x00000038
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31
+#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0xffff0000
+
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000003c
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 0
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 7
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff
+
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000003c
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 8
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 23
+#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff00
+
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000003c
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 24
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 30
+#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f000000
+
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000003c
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 31
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 31
+#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x80000000
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000040
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000040
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000
+
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x00000040
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31
+#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0xff000000
+
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x00000044
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 0
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 15
+#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff
+
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x00000044
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 16
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 31
+#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff0000
+
+#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000048
+#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 0
+#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 3
+#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x0000000f
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x00000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x0000fff0
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x00000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x01ff0000
+
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x00000048
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27
+#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x0e000000
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x00000048
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x30000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x00000048
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30
+#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x40000000
+
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x00000048
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31
+#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x80000000
+
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000004c
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 0
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 15
+#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000004c
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 16
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 23
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff0000
+
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000004c
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 24
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 28
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f000000
+
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000004c
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 29
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 31
+#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe0000000
+
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x00000050
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11
+#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x00000fff
+
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x00000050
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14
+#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x00007000
+
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x00000050
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16
+#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x00018000
+
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x00000050
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24
+#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x01fe0000
+
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x00000050
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31
+#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0xfe000000
+
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x00000054
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 0
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 31
+#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/pcu_ppdu_setup_init.h b/drivers/staging/fw-api/hw/peach/v1/pcu_ppdu_setup_init.h
new file mode 100644
index 0000000000000000000000000000000000000000..90d022543c271434c2db5f19eb4ad6c1e316120a
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/pcu_ppdu_setup_init.h
@@ -0,0 +1,2282 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PCU_PPDU_SETUP_INIT_H_
+#define _PCU_PPDU_SETUP_INIT_H_
+
+#include "pdg_response_rate_setting.h"
+#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58
+
+struct pcu_ppdu_setup_init {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t medium_prot_type : 3,
+ response_type : 5,
+ response_info_part2_required : 1,
+ response_to_response : 3,
+ mba_user_order : 2,
+ expected_mba_size : 11,
+ required_ul_mu_resp_user_count : 6,
+ transmitted_bssid_check_en : 1;
+ uint32_t mprot_required_bw1 : 1,
+ mprot_required_bw20 : 1,
+ mprot_required_bw40 : 1,
+ mprot_required_bw80 : 1,
+ mprot_required_bw160 : 1,
+ mprot_required_bw240 : 1,
+ mprot_required_bw320 : 1,
+ ppdu_allowed_bw1 : 1,
+ ppdu_allowed_bw20 : 1,
+ ppdu_allowed_bw40 : 1,
+ ppdu_allowed_bw80 : 1,
+ ppdu_allowed_bw160 : 1,
+ ppdu_allowed_bw240 : 1,
+ ppdu_allowed_bw320 : 1,
+ set_fc_pwr_mgt : 1,
+ use_cts_duration_for_data_tx : 1,
+ update_timestamp_64 : 1,
+ update_timestamp_32_lower : 1,
+ update_timestamp_32_upper : 1,
+ reserved_1a : 13;
+ uint32_t insert_timestamp_offset_0 : 16,
+ insert_timestamp_offset_1 : 16;
+ uint32_t max_bw40_try_count : 4,
+ max_bw80_try_count : 4,
+ max_bw160_try_count : 4,
+ max_bw240_try_count : 4,
+ max_bw320_try_count : 4,
+ insert_wur_timestamp_offset : 6,
+ update_wur_timestamp : 1,
+ wur_embedded_bssid_present : 1,
+ insert_wur_fcs : 1,
+ reserved_3b : 3;
+ struct pdg_response_rate_setting response_to_response_rate_info_bw20;
+ struct pdg_response_rate_setting response_to_response_rate_info_bw40;
+ struct pdg_response_rate_setting response_to_response_rate_info_bw80;
+ struct pdg_response_rate_setting response_to_response_rate_info_bw160;
+ struct pdg_response_rate_setting response_to_response_rate_info_bw240;
+ struct pdg_response_rate_setting response_to_response_rate_info_bw320;
+ uint32_t r2r_hw_response_tx_duration : 16,
+ r2r_rx_duration_field : 16;
+ uint32_t r2r_group_id : 6,
+ r2r_response_frame_type : 4,
+ r2r_sta_partial_aid : 11,
+ use_address_fields_for_protection : 1,
+ r2r_set_required_response_time : 1,
+ reserved_29a : 3,
+ r2r_bw20_active_channel : 3,
+ r2r_bw40_active_channel : 3;
+ uint32_t r2r_bw80_active_channel : 3,
+ r2r_bw160_active_channel : 3,
+ r2r_bw240_active_channel : 3,
+ r2r_bw320_active_channel : 3,
+ r2r_bw20 : 3,
+ r2r_bw40 : 3,
+ r2r_bw80 : 3,
+ r2r_bw160 : 3,
+ r2r_bw240 : 3,
+ r2r_bw320 : 3,
+ reserved_30a : 2;
+ uint32_t mu_response_expected_bitmap_31_0 : 32;
+ uint32_t mu_response_expected_bitmap_36_32 : 5,
+ mu_expected_response_cbf_count : 6,
+ mu_expected_response_sta_count : 6,
+ transmit_includes_multidestination : 1,
+ insert_prev_tx_start_timing_info : 1,
+ insert_current_tx_start_timing_info : 1,
+ tx_start_transmit_time_byte_offset : 12;
+ uint32_t protection_frame_ad1_31_0 : 32;
+ uint32_t protection_frame_ad1_47_32 : 16,
+ protection_frame_ad2_15_0 : 16;
+ uint32_t protection_frame_ad2_47_16 : 32;
+ uint32_t dynamic_medium_prot_threshold : 24,
+ dynamic_medium_prot_type : 1,
+ reserved_54a : 7;
+ uint32_t protection_frame_ad3_31_0 : 32;
+ uint32_t protection_frame_ad3_47_32 : 16,
+ protection_frame_ad4_15_0 : 16;
+ uint32_t protection_frame_ad4_47_16 : 32;
+#else
+ uint32_t transmitted_bssid_check_en : 1,
+ required_ul_mu_resp_user_count : 6,
+ expected_mba_size : 11,
+ mba_user_order : 2,
+ response_to_response : 3,
+ response_info_part2_required : 1,
+ response_type : 5,
+ medium_prot_type : 3;
+ uint32_t reserved_1a : 13,
+ update_timestamp_32_upper : 1,
+ update_timestamp_32_lower : 1,
+ update_timestamp_64 : 1,
+ use_cts_duration_for_data_tx : 1,
+ set_fc_pwr_mgt : 1,
+ ppdu_allowed_bw320 : 1,
+ ppdu_allowed_bw240 : 1,
+ ppdu_allowed_bw160 : 1,
+ ppdu_allowed_bw80 : 1,
+ ppdu_allowed_bw40 : 1,
+ ppdu_allowed_bw20 : 1,
+ ppdu_allowed_bw1 : 1,
+ mprot_required_bw320 : 1,
+ mprot_required_bw240 : 1,
+ mprot_required_bw160 : 1,
+ mprot_required_bw80 : 1,
+ mprot_required_bw40 : 1,
+ mprot_required_bw20 : 1,
+ mprot_required_bw1 : 1;
+ uint32_t insert_timestamp_offset_1 : 16,
+ insert_timestamp_offset_0 : 16;
+ uint32_t reserved_3b : 3,
+ insert_wur_fcs : 1,
+ wur_embedded_bssid_present : 1,
+ update_wur_timestamp : 1,
+ insert_wur_timestamp_offset : 6,
+ max_bw320_try_count : 4,
+ max_bw240_try_count : 4,
+ max_bw160_try_count : 4,
+ max_bw80_try_count : 4,
+ max_bw40_try_count : 4;
+ struct pdg_response_rate_setting response_to_response_rate_info_bw20;
+ struct pdg_response_rate_setting response_to_response_rate_info_bw40;
+ struct pdg_response_rate_setting response_to_response_rate_info_bw80;
+ struct pdg_response_rate_setting response_to_response_rate_info_bw160;
+ struct pdg_response_rate_setting response_to_response_rate_info_bw240;
+ struct pdg_response_rate_setting response_to_response_rate_info_bw320;
+ uint32_t r2r_rx_duration_field : 16,
+ r2r_hw_response_tx_duration : 16;
+ uint32_t r2r_bw40_active_channel : 3,
+ r2r_bw20_active_channel : 3,
+ reserved_29a : 3,
+ r2r_set_required_response_time : 1,
+ use_address_fields_for_protection : 1,
+ r2r_sta_partial_aid : 11,
+ r2r_response_frame_type : 4,
+ r2r_group_id : 6;
+ uint32_t reserved_30a : 2,
+ r2r_bw320 : 3,
+ r2r_bw240 : 3,
+ r2r_bw160 : 3,
+ r2r_bw80 : 3,
+ r2r_bw40 : 3,
+ r2r_bw20 : 3,
+ r2r_bw320_active_channel : 3,
+ r2r_bw240_active_channel : 3,
+ r2r_bw160_active_channel : 3,
+ r2r_bw80_active_channel : 3;
+ uint32_t mu_response_expected_bitmap_31_0 : 32;
+ uint32_t tx_start_transmit_time_byte_offset : 12,
+ insert_current_tx_start_timing_info : 1,
+ insert_prev_tx_start_timing_info : 1,
+ transmit_includes_multidestination : 1,
+ mu_expected_response_sta_count : 6,
+ mu_expected_response_cbf_count : 6,
+ mu_response_expected_bitmap_36_32 : 5;
+ uint32_t protection_frame_ad1_31_0 : 32;
+ uint32_t protection_frame_ad2_15_0 : 16,
+ protection_frame_ad1_47_32 : 16;
+ uint32_t protection_frame_ad2_47_16 : 32;
+ uint32_t reserved_54a : 7,
+ dynamic_medium_prot_type : 1,
+ dynamic_medium_prot_threshold : 24;
+ uint32_t protection_frame_ad3_31_0 : 32;
+ uint32_t protection_frame_ad4_15_0 : 16,
+ protection_frame_ad3_47_32 : 16;
+ uint32_t protection_frame_ad4_47_16 : 32;
+#endif
+};
+
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET 0x00000000
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB 0
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB 2
+#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK 0x00000007
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET 0x00000000
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK 0x000000f8
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x00000000
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK 0x00000100
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET 0x00000000
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK 0x00000e00
+
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET 0x00000000
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB 12
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB 13
+#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK 0x00003000
+
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET 0x00000000
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB 14
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB 24
+#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK 0x01ffc000
+
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET 0x00000000
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB 25
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB 30
+#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK 0x7e000000
+
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x00000000
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB 31
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB 31
+#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB 0
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB 0
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK 0x00000001
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB 1
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB 1
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK 0x00000002
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB 2
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB 2
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK 0x00000004
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB 3
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB 3
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK 0x00000008
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB 4
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB 4
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK 0x00000010
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB 5
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB 5
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK 0x00000020
+
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB 6
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB 6
+#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK 0x00000040
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB 7
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB 7
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK 0x00000080
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB 8
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB 8
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK 0x00000100
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB 9
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB 9
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK 0x00000200
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB 10
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB 10
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB 11
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB 11
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK 0x00000800
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB 12
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB 12
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK 0x00001000
+
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB 13
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB 13
+#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK 0x00002000
+
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB 14
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB 14
+#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK 0x00004000
+
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB 15
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB 15
+#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK 0x00008000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB 16
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB 16
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK 0x00010000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB 17
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB 17
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK 0x00020000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB 18
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB 18
+#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK 0x00040000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET 0x00000004
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK 0xfff80000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET 0x00000008
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB 0
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB 15
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK 0x0000ffff
+
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET 0x00000008
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB 16
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB 31
+#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK 0xffff0000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET 0x0000000c
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB 0
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB 3
+#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET 0x0000000c
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB 4
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB 7
+#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK 0x000000f0
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET 0x0000000c
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB 8
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB 11
+#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK 0x00000f00
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET 0x0000000c
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB 12
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB 15
+#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK 0x0000f000
+
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET 0x0000000c
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB 16
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB 19
+#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK 0x000f0000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET 0x0000000c
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB 20
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB 25
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK 0x03f00000
+
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET 0x0000000c
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB 26
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB 26
+#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK 0x04000000
+
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET 0x0000000c
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB 27
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB 27
+#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK 0x08000000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET 0x0000000c
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB 28
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB 28
+#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK 0x10000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET 0x0000000c
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB 29
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK 0xe0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET 0x00000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK 0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET 0x00000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK 0x1e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET 0x00000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK 0x20000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET 0x00000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET 0x00000010
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET 0x00000014
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK 0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x00000014
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET 0x00000014
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK 0x00070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x00000014
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET 0x00000014
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK 0x38000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x00000014
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x00000014
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x00000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET 0x00000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK 0x00000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET 0x00000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK 0x00000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET 0x00000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET 0x00000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK 0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x00000018
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK 0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET 0x0000001c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK 0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET 0x0000001c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET 0x0000001c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK 0x00003c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_OFFSET 0x0000001c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MASK 0x0000c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET 0x0000001c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK 0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000001c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK 0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK 0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK 0x00002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x00008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x00200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x04000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET 0x00000020
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK 0xf8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK 0x00003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK 0x03f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000024
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x00000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000028
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET 0x0000002c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK 0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000002c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET 0x0000002c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK 0x1e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET 0x0000002c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK 0x20000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET 0x0000002c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET 0x0000002c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET 0x00000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK 0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x00000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET 0x00000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK 0x00070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x00000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET 0x00000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK 0x38000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x00000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x00000030
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x00000034
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET 0x00000034
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK 0x00000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET 0x00000034
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK 0x00000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET 0x00000034
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET 0x00000034
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK 0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x00000034
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK 0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET 0x00000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK 0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET 0x00000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET 0x00000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK 0x00003c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_OFFSET 0x00000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MASK 0x0000c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET 0x00000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK 0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x00000038
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK 0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK 0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK 0x00002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x00008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x00200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x04000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET 0x0000003c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK 0xf8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK 0x00003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x0007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK 0x03f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000040
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000044
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000044
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000044
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000044
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000044
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x00000044
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000044
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET 0x00000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK 0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET 0x00000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK 0x1e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET 0x00000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK 0x20000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET 0x00000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET 0x00000048
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET 0x0000004c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK 0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000004c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET 0x0000004c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK 0x00070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000004c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET 0x0000004c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK 0x38000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000004c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000004c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x00000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET 0x00000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK 0x00000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET 0x00000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK 0x00000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET 0x00000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET 0x00000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK 0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x00000050
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK 0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET 0x00000054
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK 0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET 0x00000054
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET 0x00000054
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK 0x00003c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_OFFSET 0x00000054
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MASK 0x0000c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET 0x00000054
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK 0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x00000054
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK 0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK 0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK 0x00002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x00008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x00200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x04000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET 0x00000058
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK 0xf8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK 0x00003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK 0x03f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000005c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x00000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000060
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x00000064
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK 0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000064
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET 0x00000064
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK 0x1e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET 0x00000064
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK 0x20000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET 0x00000064
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET 0x00000064
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET 0x00000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK 0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x00000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET 0x00000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK 0x00070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x00000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET 0x00000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK 0x38000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x00000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x00000068
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000006c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET 0x0000006c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK 0x00000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET 0x0000006c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK 0x00000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET 0x0000006c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET 0x0000006c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK 0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000006c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x00000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK 0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET 0x00000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET 0x00000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK 0x00003c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_OFFSET 0x00000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MASK 0x0000c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET 0x00000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK 0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x00000070
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK 0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK 0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK 0x00002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x00008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x00200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x04000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x00000074
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK 0xf8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x00003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x0007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK 0x03f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000078
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000007c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000007c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000007c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000007c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000007c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000007c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000007c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x00000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK 0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET 0x00000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK 0x1e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET 0x00000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK 0x20000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET 0x00000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET 0x00000080
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET 0x00000084
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK 0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x00000084
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET 0x00000084
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK 0x00070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x00000084
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET 0x00000084
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK 0x38000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x00000084
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x00000084
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x00000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET 0x00000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK 0x00000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET 0x00000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK 0x00000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET 0x00000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET 0x00000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK 0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x00000088
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000008c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK 0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET 0x0000008c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET 0x0000008c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK 0x00003c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_OFFSET 0x0000008c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MASK 0x0000c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET 0x0000008c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK 0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000008c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK 0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK 0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK 0x00002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x00008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x00200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x04000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x00000090
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK 0xf8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x00003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK 0x03f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000094
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x00000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000098
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000009c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK 0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000009c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET 0x0000009c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK 0x1e000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET 0x0000009c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK 0x20000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET 0x0000009c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET 0x0000009c
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET 0x000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK 0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET 0x000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK 0x00070000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET 0x000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB 29
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK 0x38000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x40000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x000000a0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x80000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x000000a4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET 0x000000a4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK 0x00000070
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET 0x000000a4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK 0x00000080
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET 0x000000a4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK 0x0000ff00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET 0x000000a4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK 0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x000000a4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK 0x000000ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET 0x000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET 0x000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK 0x00003c00
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_OFFSET 0x000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MASK 0x0000c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET 0x000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK 0x00ff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x000000a8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK 0xff000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK 0x00000001
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK 0x00002000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x00008000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 21
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x00200000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x04000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x000000ac
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK 0xf8000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x00000300
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x00003800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x0007c000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB 20
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK 0x03f00000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x000000b0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x000000b4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x000000b4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x000000b4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x000000b4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x000000b4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x000000b4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 16
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 27
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
+
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x000000b4
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET 0x000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB 0
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB 15
+#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff
+
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET 0x000000b8
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB 16
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB 31
+#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK 0xffff0000
+
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET 0x000000bc
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB 0
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB 5
+#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK 0x0000003f
+
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET 0x000000bc
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB 6
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB 9
+#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK 0x000003c0
+
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET 0x000000bc
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB 10
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB 20
+#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK 0x001ffc00
+
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET 0x000000bc
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB 21
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB 21
+#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK 0x00200000
+
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET 0x000000bc
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB 22
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB 22
+#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK 0x00400000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET 0x000000bc
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB 23
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB 25
+#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK 0x03800000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET 0x000000bc
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB 26
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB 28
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK 0x1c000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET 0x000000bc
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB 29
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB 31
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK 0xe0000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET 0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB 0
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB 2
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK 0x00000007
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET 0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB 3
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB 5
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK 0x00000038
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET 0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB 6
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB 8
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK 0x000001c0
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET 0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB 9
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB 11
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK 0x00000e00
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET 0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB 12
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB 14
+#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK 0x00007000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET 0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB 15
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB 17
+#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK 0x00038000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET 0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB 18
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB 20
+#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK 0x001c0000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET 0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB 21
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB 23
+#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK 0x00e00000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET 0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB 24
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB 26
+#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK 0x07000000
+
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET 0x000000c0
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB 27
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB 29
+#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK 0x38000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_30A_OFFSET 0x000000c0
+#define PCU_PPDU_SETUP_INIT_RESERVED_30A_LSB 30
+#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MASK 0xc0000000
+
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET 0x000000c4
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB 0
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB 31
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK 0xffffffff
+
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET 0x000000c8
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB 0
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB 4
+#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK 0x0000001f
+
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET 0x000000c8
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB 5
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB 10
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK 0x000007e0
+
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET 0x000000c8
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB 11
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB 16
+#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK 0x0001f800
+
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET 0x000000c8
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB 17
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB 17
+#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK 0x00020000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET 0x000000c8
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB 18
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB 18
+#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK 0x00040000
+
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET 0x000000c8
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB 19
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB 19
+#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK 0x00080000
+
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET 0x000000c8
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB 20
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB 31
+#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK 0xfff00000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET 0x000000cc
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB 0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB 31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK 0xffffffff
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET 0x000000d0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB 0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB 15
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK 0x0000ffff
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET 0x000000d0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB 16
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB 31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK 0xffff0000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET 0x000000d4
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB 0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB 31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK 0xffffffff
+
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET 0x000000d8
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB 0
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB 23
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK 0x00ffffff
+
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET 0x000000d8
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB 24
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB 24
+#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK 0x01000000
+
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET 0x000000d8
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB 25
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB 31
+#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK 0xfe000000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET 0x000000dc
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB 0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB 31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK 0xffffffff
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET 0x000000e0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB 0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB 15
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK 0x0000ffff
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET 0x000000e0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB 16
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB 31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK 0xffff0000
+
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET 0x000000e4
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB 0
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB 31
+#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/pdg_response.h b/drivers/staging/fw-api/hw/peach/v1/pdg_response.h
new file mode 100644
index 0000000000000000000000000000000000000000..7060494a33e7e6e6e392c13316cfedcbfc6566fb
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/pdg_response.h
@@ -0,0 +1,473 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PDG_RESPONSE_H_
+#define _PDG_RESPONSE_H_
+
+#include "pdg_response_rate_setting.h"
+#define NUM_OF_DWORDS_PDG_RESPONSE 12
+
+struct pdg_response {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct pdg_response_rate_setting hw_response_rate_info;
+ uint32_t hw_response_tx_duration : 16,
+ rx_duration_field : 16;
+ uint32_t punctured_response_transmission : 1,
+ cca_subband_channel_bonding_mask : 16,
+ scrambler_seed_override : 2,
+ response_density_valid : 1,
+ response_density : 5,
+ more_data : 1,
+ duration_indication : 1,
+ relayed_frame : 1,
+ address_indicator : 1,
+ bandwidth : 3;
+ uint32_t ack_id : 16,
+ block_ack_bitmap : 16;
+ uint32_t response_frame_type : 4,
+ ack_id_ext : 10,
+ ftm_en : 1,
+ group_id : 6,
+ sta_partial_aid : 11;
+ uint32_t ndp_ba_start_seq_ctrl : 12,
+ active_channel : 3,
+ txop_duration_all_ones : 1,
+ frame_length : 16;
+#else
+ struct pdg_response_rate_setting hw_response_rate_info;
+ uint32_t rx_duration_field : 16,
+ hw_response_tx_duration : 16;
+ uint32_t bandwidth : 3,
+ address_indicator : 1,
+ relayed_frame : 1,
+ duration_indication : 1,
+ more_data : 1,
+ response_density : 5,
+ response_density_valid : 1,
+ scrambler_seed_override : 2,
+ cca_subband_channel_bonding_mask : 16,
+ punctured_response_transmission : 1;
+ uint32_t block_ack_bitmap : 16,
+ ack_id : 16;
+ uint32_t sta_partial_aid : 11,
+ group_id : 6,
+ ftm_en : 1,
+ ack_id_ext : 10,
+ response_frame_type : 4;
+ uint32_t frame_length : 16,
+ txop_duration_all_ones : 1,
+ active_channel : 3,
+ ndp_ba_start_seq_ctrl : 12;
+#endif
+};
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x00000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x00000001
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x00000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x1e000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x00000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x20000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x00000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x40000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x00000000
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x80000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x00000004
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x00000004
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 8
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff00
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x00000004
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 18
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x00070000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x00000004
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 19
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 26
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x00000004
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 27
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 29
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x38000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x00000004
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 30
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 30
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x40000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x80000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x00000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 3
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x0000000f
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x00000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x00000070
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x00000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x00000080
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x00000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x0000ff00
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x00000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x00ff0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x00000008
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0xff000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000c
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000ff
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000c
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 8
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 9
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x00000300
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000c
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00003c00
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET 0x0000000c
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB 14
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB 15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK 0x0000c000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000c
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 23
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000c
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x00000001
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x00002000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x00008000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x001c0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x00200000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x04000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x00000010
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0xf8000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 8
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 9
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x00000300
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x00000400
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x00003800
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 14
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 18
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 20
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 25
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f00000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
+
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
+
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000001c
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 0
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 15
+#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff
+
+#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000001c
+#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 16
+#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 31
+#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff0000
+
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x00000020
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0
+#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x00000001
+
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x00000020
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16
+#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x0001fffe
+
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x00000020
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18
+#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x00060000
+
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x00000020
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19
+#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x00080000
+
+#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x00000020
+#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20
+#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24
+#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x01f00000
+
+#define PDG_RESPONSE_MORE_DATA_OFFSET 0x00000020
+#define PDG_RESPONSE_MORE_DATA_LSB 25
+#define PDG_RESPONSE_MORE_DATA_MSB 25
+#define PDG_RESPONSE_MORE_DATA_MASK 0x02000000
+
+#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x00000020
+#define PDG_RESPONSE_DURATION_INDICATION_LSB 26
+#define PDG_RESPONSE_DURATION_INDICATION_MSB 26
+#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x04000000
+
+#define PDG_RESPONSE_RELAYED_FRAME_OFFSET 0x00000020
+#define PDG_RESPONSE_RELAYED_FRAME_LSB 27
+#define PDG_RESPONSE_RELAYED_FRAME_MSB 27
+#define PDG_RESPONSE_RELAYED_FRAME_MASK 0x08000000
+
+#define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET 0x00000020
+#define PDG_RESPONSE_ADDRESS_INDICATOR_LSB 28
+#define PDG_RESPONSE_ADDRESS_INDICATOR_MSB 28
+#define PDG_RESPONSE_ADDRESS_INDICATOR_MASK 0x10000000
+
+#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x00000020
+#define PDG_RESPONSE_BANDWIDTH_LSB 29
+#define PDG_RESPONSE_BANDWIDTH_MSB 31
+#define PDG_RESPONSE_BANDWIDTH_MASK 0xe0000000
+
+#define PDG_RESPONSE_ACK_ID_OFFSET 0x00000024
+#define PDG_RESPONSE_ACK_ID_LSB 0
+#define PDG_RESPONSE_ACK_ID_MSB 15
+#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff
+
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x00000024
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 16
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 31
+#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff0000
+
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x00000028
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3
+#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x0000000f
+
+#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x00000028
+#define PDG_RESPONSE_ACK_ID_EXT_LSB 4
+#define PDG_RESPONSE_ACK_ID_EXT_MSB 13
+#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x00003ff0
+
+#define PDG_RESPONSE_FTM_EN_OFFSET 0x00000028
+#define PDG_RESPONSE_FTM_EN_LSB 14
+#define PDG_RESPONSE_FTM_EN_MSB 14
+#define PDG_RESPONSE_FTM_EN_MASK 0x00004000
+
+#define PDG_RESPONSE_GROUP_ID_OFFSET 0x00000028
+#define PDG_RESPONSE_GROUP_ID_LSB 15
+#define PDG_RESPONSE_GROUP_ID_MSB 20
+#define PDG_RESPONSE_GROUP_ID_MASK 0x001f8000
+
+#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x00000028
+#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21
+#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31
+#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0xffe00000
+
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000002c
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 0
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 11
+#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff
+
+#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000002c
+#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 12
+#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 14
+#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x00007000
+
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000002c
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 15
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 15
+#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x00008000
+
+#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000002c
+#define PDG_RESPONSE_FRAME_LENGTH_LSB 16
+#define PDG_RESPONSE_FRAME_LENGTH_MSB 31
+#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/pdg_response_rate_setting.h b/drivers/staging/fw-api/hw/peach/v1/pdg_response_rate_setting.h
new file mode 100644
index 0000000000000000000000000000000000000000..7a187717bf40b6849059f628f6bb385fd8be5dde
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/pdg_response_rate_setting.h
@@ -0,0 +1,414 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PDG_RESPONSE_RATE_SETTING_H_
+#define _PDG_RESPONSE_RATE_SETTING_H_
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7
+
+struct pdg_response_rate_setting {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t reserved_0a : 1,
+ tx_antenna_sector_ctrl : 24,
+ pkt_type : 4,
+ smoothing : 1,
+ ldpc : 1,
+ stbc : 1;
+ uint32_t alt_tx_pwr : 8,
+ alt_min_tx_pwr : 8,
+ alt_nss : 3,
+ alt_tx_chain_mask : 8,
+ alt_bw : 3,
+ stf_ltf_3db_boost : 1,
+ force_extra_symbol : 1;
+ uint32_t alt_rate_mcs : 4,
+ nss : 3,
+ dpd_enable : 1,
+ tx_pwr : 8,
+ min_tx_pwr : 8,
+ tx_chain_mask : 8;
+ uint32_t reserved_3a : 8,
+ sgi : 2,
+ rate_mcs : 4,
+ reserved_3b : 2,
+ tx_pwr_1 : 8,
+ alt_tx_pwr_1 : 8;
+ uint32_t aggregation : 1,
+ dot11ax_bss_color_id : 6,
+ dot11ax_spatial_reuse : 4,
+ dot11ax_cp_ltf_size : 2,
+ dot11ax_dcm : 1,
+ dot11ax_doppler_indication : 1,
+ dot11ax_su_extended : 1,
+ dot11ax_min_packet_extension : 2,
+ dot11ax_pe_nss : 3,
+ dot11ax_pe_content : 1,
+ dot11ax_pe_ltf_size : 2,
+ dot11ax_chain_csd_en : 1,
+ dot11ax_pe_chain_csd_en : 1,
+ dot11ax_dl_ul_flag : 1,
+ reserved_4a : 5;
+ uint32_t dot11ax_ext_ru_start_index : 4,
+ dot11ax_ext_ru_size : 4,
+ eht_duplicate_mode : 2,
+ he_sigb_dcm : 1,
+ he_sigb_0_mcs : 3,
+ num_he_sigb_sym : 5,
+ required_response_time_source : 1,
+ reserved_5a : 6,
+ u_sig_puncture_pattern_encoding : 6;
+ struct mlo_sta_id_details mlo_sta_id_details_rx;
+ uint16_t required_response_time : 12,
+ dot11be_params_placeholder : 4;
+#else
+ uint32_t stbc : 1,
+ ldpc : 1,
+ smoothing : 1,
+ pkt_type : 4,
+ tx_antenna_sector_ctrl : 24,
+ reserved_0a : 1;
+ uint32_t force_extra_symbol : 1,
+ stf_ltf_3db_boost : 1,
+ alt_bw : 3,
+ alt_tx_chain_mask : 8,
+ alt_nss : 3,
+ alt_min_tx_pwr : 8,
+ alt_tx_pwr : 8;
+ uint32_t tx_chain_mask : 8,
+ min_tx_pwr : 8,
+ tx_pwr : 8,
+ dpd_enable : 1,
+ nss : 3,
+ alt_rate_mcs : 4;
+ uint32_t alt_tx_pwr_1 : 8,
+ tx_pwr_1 : 8,
+ reserved_3b : 2,
+ rate_mcs : 4,
+ sgi : 2,
+ reserved_3a : 8;
+ uint32_t reserved_4a : 5,
+ dot11ax_dl_ul_flag : 1,
+ dot11ax_pe_chain_csd_en : 1,
+ dot11ax_chain_csd_en : 1,
+ dot11ax_pe_ltf_size : 2,
+ dot11ax_pe_content : 1,
+ dot11ax_pe_nss : 3,
+ dot11ax_min_packet_extension : 2,
+ dot11ax_su_extended : 1,
+ dot11ax_doppler_indication : 1,
+ dot11ax_dcm : 1,
+ dot11ax_cp_ltf_size : 2,
+ dot11ax_spatial_reuse : 4,
+ dot11ax_bss_color_id : 6,
+ aggregation : 1;
+ uint32_t u_sig_puncture_pattern_encoding : 6,
+ reserved_5a : 6,
+ required_response_time_source : 1,
+ num_he_sigb_sym : 5,
+ he_sigb_0_mcs : 3,
+ he_sigb_dcm : 1,
+ eht_duplicate_mode : 2,
+ dot11ax_ext_ru_size : 4,
+ dot11ax_ext_ru_start_index : 4;
+ uint32_t dot11be_params_placeholder : 4,
+ required_response_time : 12;
+ struct mlo_sta_id_details mlo_sta_id_details_rx;
+#endif
+};
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001
+
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24
+#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
+
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28
+#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000
+
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29
+#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000
+
+#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000
+#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30
+#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30
+#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000
+
+#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000
+#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31
+#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31
+#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15
+#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18
+#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29
+#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000
+
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30
+#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000
+
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31
+#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 3
+#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000000f
+
+#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4
+#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6
+#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070
+
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7
+#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080
+
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00
+
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23
+#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000
+
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31
+#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 0
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000ff
+
+#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8
+#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9
+#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300
+
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 13
+#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00003c00
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET 0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB 14
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB 15
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK 0x0000c000
+
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23
+#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000
+
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31
+#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000
+
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0
+#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7
+#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
+
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9
+#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300
+
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400
+
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13
+#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800
+
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18
+#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000
+
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
+
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25
+#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000
+
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27
+#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
+
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
+#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/pdg_tx_req.h b/drivers/staging/fw-api/hw/peach/v1/pdg_tx_req.h
new file mode 100644
index 0000000000000000000000000000000000000000..82333c6a21c55573c5f23fae85b4640ab970ce50
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/pdg_tx_req.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PDG_TX_REQ_H_
+#define _PDG_TX_REQ_H_
+
+#define NUM_OF_DWORDS_PDG_TX_REQ 2
+
+struct pdg_tx_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tx_reason : 2,
+ use_puncture_pattern : 2,
+ req_bw : 3,
+ puncture_pattern_number : 6,
+ reserved_0b : 1,
+ req_paprd : 1,
+ duration_field_boundary_valid : 1,
+ duration_field_boundary : 16;
+ uint32_t puncture_subband_mask : 16,
+ reserved_0c : 16;
+#else
+ uint32_t duration_field_boundary : 16,
+ duration_field_boundary_valid : 1,
+ req_paprd : 1,
+ reserved_0b : 1,
+ puncture_pattern_number : 6,
+ req_bw : 3,
+ use_puncture_pattern : 2,
+ tx_reason : 2;
+ uint32_t reserved_0c : 16,
+ puncture_subband_mask : 16;
+#endif
+};
+
+#define PDG_TX_REQ_TX_REASON_OFFSET 0x00000000
+#define PDG_TX_REQ_TX_REASON_LSB 0
+#define PDG_TX_REQ_TX_REASON_MSB 1
+#define PDG_TX_REQ_TX_REASON_MASK 0x00000003
+
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x00000000
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3
+#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x0000000c
+
+#define PDG_TX_REQ_REQ_BW_OFFSET 0x00000000
+#define PDG_TX_REQ_REQ_BW_LSB 4
+#define PDG_TX_REQ_REQ_BW_MSB 6
+#define PDG_TX_REQ_REQ_BW_MASK 0x00000070
+
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x00000000
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12
+#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x00001f80
+
+#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x00000000
+#define PDG_TX_REQ_RESERVED_0B_LSB 13
+#define PDG_TX_REQ_RESERVED_0B_MSB 13
+#define PDG_TX_REQ_RESERVED_0B_MASK 0x00002000
+
+#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x00000000
+#define PDG_TX_REQ_REQ_PAPRD_LSB 14
+#define PDG_TX_REQ_REQ_PAPRD_MSB 14
+#define PDG_TX_REQ_REQ_PAPRD_MASK 0x00004000
+
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x00000000
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x00008000
+
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x00000000
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31
+#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0xffff0000
+
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x00000004
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 0
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 15
+#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff
+
+#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x00000004
+#define PDG_TX_REQ_RESERVED_0C_LSB 16
+#define PDG_TX_REQ_RESERVED_0C_MSB 31
+#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_abort_request_info.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_abort_request_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..76d5ef73c2b90ea927f1ed3d0d03577eac0a0214
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_abort_request_info.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_ABORT_REQUEST_INFO_H_
+#define _PHYRX_ABORT_REQUEST_INFO_H_
+
+#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1
+
+struct phyrx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t phyrx_abort_reason : 8,
+ phy_enters_nap_state : 1,
+ phy_enters_defer_state : 1,
+ gain_change_by_main : 1,
+ gain_change_by_bt : 1,
+ main_tx_indication : 1,
+ bt_tx_indication : 1,
+ concurrent_mode : 1,
+ reserved_0 : 1,
+ receive_duration : 16;
+#else
+ uint32_t receive_duration : 16,
+ reserved_0 : 1,
+ concurrent_mode : 1,
+ bt_tx_indication : 1,
+ main_tx_indication : 1,
+ gain_change_by_bt : 1,
+ gain_change_by_main : 1,
+ phy_enters_defer_state : 1,
+ phy_enters_nap_state : 1,
+ phyrx_abort_reason : 8;
+#endif
+};
+
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7
+#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff
+
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100
+
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9
+#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200
+
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB 10
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB 10
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK 0x00000400
+
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB 11
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB 11
+#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK 0x00000800
+
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB 12
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB 12
+#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK 0x00001000
+
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB 13
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB 13
+#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK 0x00002000
+
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB 14
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB 14
+#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK 0x00004000
+
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 15
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15
+#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x00008000
+
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31
+#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_common_user_info.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_common_user_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..eeb21a463ecdc0cca8c72805e3fe920aa049ee97
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_common_user_info.h
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_COMMON_USER_INFO_H_
+#define _PHYRX_COMMON_USER_INFO_H_
+
+#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4
+
+struct phyrx_common_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t receive_duration : 16,
+ reserved_0a : 16;
+ uint32_t u_sig_puncture_pattern_encoding : 6,
+ reserved_1a : 9,
+ obss_nav_update_enable : 1,
+ obss_nav_value : 16;
+ uint32_t eht_ppdu_type : 2,
+ bss_color_id : 6,
+ dl_ul_flag : 1,
+ txop_duration : 7,
+ cp_setting : 2,
+ ltf_size : 2,
+ spatial_reuse : 4,
+ rx_ndp : 1,
+ dot11be_su_extended : 1,
+ reserved_2a : 6;
+ uint32_t eht_duplicate : 2,
+ eht_sig_cmn_field_type : 2,
+ doppler_indication : 1,
+ sta_id : 11,
+ puncture_bitmap : 16;
+#else
+ uint32_t reserved_0a : 16,
+ receive_duration : 16;
+ uint32_t obss_nav_value : 16,
+ obss_nav_update_enable : 1,
+ reserved_1a : 9,
+ u_sig_puncture_pattern_encoding : 6;
+ uint32_t reserved_2a : 6,
+ dot11be_su_extended : 1,
+ rx_ndp : 1,
+ spatial_reuse : 4,
+ ltf_size : 2,
+ cp_setting : 2,
+ txop_duration : 7,
+ dl_ul_flag : 1,
+ bss_color_id : 6,
+ eht_ppdu_type : 2;
+ uint32_t puncture_bitmap : 16,
+ sta_id : 11,
+ doppler_indication : 1,
+ eht_sig_cmn_field_type : 2,
+ eht_duplicate : 2;
+#endif
+};
+
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x00000000
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15
+#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x0000ffff
+
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31
+#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0xffff0000
+
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000004
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 0
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 5
+#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f
+
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 6
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 14
+#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0x00007fc0
+
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET 0x00000004
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB 15
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB 15
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK 0x00008000
+
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET 0x00000004
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB 16
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB 31
+#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK 0xffff0000
+
+#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_OFFSET 0x00000008
+#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_LSB 0
+#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MSB 1
+#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MASK 0x00000003
+
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x00000008
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7
+#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x000000fc
+
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x00000008
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8
+#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x00000100
+
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x00000008
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15
+#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x0000fe00
+
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x00000008
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17
+#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x00030000
+
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x00000008
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19
+#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x000c0000
+
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x00000008
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23
+#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x00f00000
+
+#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x00000008
+#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24
+#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24
+#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x01000000
+
+#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_OFFSET 0x00000008
+#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_LSB 25
+#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MSB 25
+#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MASK 0x02000000
+
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x00000008
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31
+#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0xfc000000
+
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000c
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 0
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 1
+#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x00000003
+
+#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000c
+#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_LSB 2
+#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MSB 3
+#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MASK 0x0000000c
+
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000c
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 4
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 4
+#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x00000010
+
+#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000c
+#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 5
+#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 15
+#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe0
+
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000c
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 16
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 31
+#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_dl.h
new file mode 100644
index 0000000000000000000000000000000000000000..d1c2b1e1b8e47d87cf1c8ac71a0a116d6a9e2e30
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_dl.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_HE_SIG_A_MU_DL_H_
+#define _PHYRX_HE_SIG_A_MU_DL_H_
+
+#include "he_sig_a_mu_dl_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2
+
+struct phyrx_he_sig_a_mu_dl {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details;
+#else
+ struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 6
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 7
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 10
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 11
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 12
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 14
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 19
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 25
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 30
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000
+
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_ul.h
new file mode 100644
index 0000000000000000000000000000000000000000..fdf4307f5ff7cb0bb68424276ce613fa829c0752
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_mu_ul.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_HE_SIG_A_MU_UL_H_
+#define _PHYRX_HE_SIG_A_MU_UL_H_
+
+#include "he_sig_a_mu_ul_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2
+
+struct phyrx_he_sig_a_mu_ul {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
+#else
+ struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 6
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 15
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 19
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 25
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 30
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000
+
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_su.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_su.h
new file mode 100644
index 0000000000000000000000000000000000000000..387503c0d79d9f13cb10e12ddd3275440393c605
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_a_su.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_HE_SIG_A_SU_H_
+#define _PHYRX_HE_SIG_A_SU_H_
+
+#include "he_sig_a_su_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2
+
+struct phyrx_he_sig_a_su {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct he_sig_a_su_info phyrx_he_sig_a_su_info_details;
+#else
+ struct he_sig_a_su_info phyrx_he_sig_a_su_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 6
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 7
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 8
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 9
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 10
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 12
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 14
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 15
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 19
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 25
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 29
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x38000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 30
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 30
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x40000000
+
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b1_mu.h
new file mode 100644
index 0000000000000000000000000000000000000000..cfe51c2026c0244343c79c84860cbd8bc808a175
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b1_mu.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_HE_SIG_B1_MU_H_
+#define _PHYRX_HE_SIG_B1_MU_H_
+
+#include "he_sig_b1_mu_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 1
+
+struct phyrx_he_sig_b1_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
+#else
+ struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff
+
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x7fffff00
+
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_mu.h
new file mode 100644
index 0000000000000000000000000000000000000000..1fc8f8b0da2246c038050d87b05ac8c82f5df536
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_mu.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_HE_SIG_B2_MU_H_
+#define _PHYRX_HE_SIG_B2_MU_H_
+
+#include "he_sig_b2_mu_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2
+
+struct phyrx_he_sig_b2_mu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details;
+#else
+ struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x0fe00000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x70000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 0
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 7
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x00000004
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 8
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 15
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff00
+
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 16
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 31
+#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_ofdma.h
new file mode 100644
index 0000000000000000000000000000000000000000..60f343a1eb1787d513f095aca4fa09c4e418918a
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_he_sig_b2_ofdma.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_
+#define _PHYRX_HE_SIG_B2_OFDMA_H_
+
+#include "he_sig_b2_ofdma_info.h"
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2
+
+struct phyrx_he_sig_b2_ofdma {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details;
+#else
+ struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details;
+#endif
+};
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x7fe00000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 0
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 7
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x00000004
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 8
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 15
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff00
+
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 16
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 31
+#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_ht_sig.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_ht_sig.h
new file mode 100644
index 0000000000000000000000000000000000000000..f9f1e04911a28758bb66c2e4852955d2d5f04e5d
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_ht_sig.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_HT_SIG_H_
+#define _PHYRX_HT_SIG_H_
+
+#include "ht_sig_info.h"
+#define NUM_OF_DWORDS_PHYRX_HT_SIG 2
+
+struct phyrx_ht_sig {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct ht_sig_info phyrx_ht_sig_info_details;
+#else
+ struct ht_sig_info phyrx_ht_sig_info_details;
+#endif
+};
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 0
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 1
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 2
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 3
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 4
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 5
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 6
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 7
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 9
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 10
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 17
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 23
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 30
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f000000
+
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_a.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_a.h
new file mode 100644
index 0000000000000000000000000000000000000000..568e3dfc27f12654661399e130026fbfe9c7cc6b
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_a.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_L_SIG_A_H_
+#define _PHYRX_L_SIG_A_H_
+
+#include "l_sig_a_info.h"
+#define NUM_OF_DWORDS_PHYRX_L_SIG_A 1
+
+struct phyrx_l_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct l_sig_a_info phyrx_l_sig_a_info_details;
+#else
+ struct l_sig_a_info phyrx_l_sig_a_info_details;
+#endif
+};
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x60000000
+
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_b.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_b.h
new file mode 100644
index 0000000000000000000000000000000000000000..6c472400e61406723327aeec7c18d4987258c65c
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_l_sig_b.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_L_SIG_B_H_
+#define _PHYRX_L_SIG_B_H_
+
+#include "l_sig_b_info.h"
+#define NUM_OF_DWORDS_PHYRX_L_SIG_B 1
+
+struct phyrx_l_sig_b {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct l_sig_b_info phyrx_l_sig_b_info_details;
+#else
+ struct l_sig_b_info phyrx_l_sig_b_info_details;
+#endif
+};
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x7fff0000
+
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_location.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_location.h
new file mode 100644
index 0000000000000000000000000000000000000000..1c92be1c6d5fc8fde77110df9a6851de718c6bc9
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_location.h
@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_LOCATION_H_
+#define _PHYRX_LOCATION_H_
+
+#include "rx_location_info.h"
+#define NUM_OF_DWORDS_PHYRX_LOCATION 28
+
+struct phyrx_location {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct rx_location_info rx_location_info_details;
+#else
+ struct rx_location_info rx_location_info_details;
+#endif
+};
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x00000001
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x00000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x00000002
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_OFFSET 0x00000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_LSB 2
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MSB 3
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MASK 0x0000000c
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x000000f0
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x00000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x0000ff00
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x00ff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x00000000
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0xff000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 7
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 8
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x00000004
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 23
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x00000004
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 24
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 8
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff00
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 19
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 20
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 23
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f00000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 24
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x00ff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000010
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0xff000000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000014
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x00000018
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0xffffffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000001c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x00000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x00000020
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x00000024
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x00000024
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x00000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x000000ff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x00000028
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000002c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000002c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x00000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x00000030
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x00000034
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x00000034
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x00000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x00000038
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000003c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000003c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x00000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x00000040
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x00000044
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x00000044
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x00000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x00000048
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000004c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000004c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x00000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x00000050
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x00000054
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x00000054
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x00000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x00000058
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000005c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000005c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x00000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x00000060
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x00000064
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x00000064
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x00000068
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x0000ffff
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x00000068
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0xffff0000
+
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000006c
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 0
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 31
+#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_other_receive_info_ru_details.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_other_receive_info_ru_details.h
new file mode 100644
index 0000000000000000000000000000000000000000..03f379615ad049b5ccb2fa7e990844485b8ae62a
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_other_receive_info_ru_details.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
+#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_
+
+#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 3
+
+struct phyrx_other_receive_info_ru_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t ru_details_channel_0 : 32;
+ uint32_t ru_details_channel_1 : 32;
+ uint32_t spare : 32;
+#else
+ uint32_t ru_details_channel_0 : 32;
+ uint32_t ru_details_channel_1 : 32;
+ uint32_t spare : 32;
+#endif
+};
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x00000000
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0xffffffff
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x00000004
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 31
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff
+
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x00000008
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31
+#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end.h
new file mode 100644
index 0000000000000000000000000000000000000000..ab6d45be6a99ce80cfffa1b55ec0eb752d67e44c
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end.h
@@ -0,0 +1,432 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_PKT_END_H_
+#define _PHYRX_PKT_END_H_
+
+#include "phyrx_pkt_end_info.h"
+#define NUM_OF_DWORDS_PHYRX_PKT_END 24
+
+struct phyrx_pkt_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct phyrx_pkt_end_info rx_pkt_end_details;
+#else
+ struct phyrx_pkt_end_info rx_pkt_end_details;
+#endif
+};
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x00000002
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x00000004
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x00000008
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x00000010
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x000000c0
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x00000000
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0xffff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB 12
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xfffff000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x00000058
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0xffffffff
+
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000005c
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 0
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 31
+#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end_info.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..31e6ca16566bd0b79ec6b9fbd41d16825b93bcde
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_pkt_end_info.h
@@ -0,0 +1,457 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_PKT_END_INFO_H_
+#define _PHYRX_PKT_END_INFO_H_
+
+#include "receive_rssi_info.h"
+#include "rx_timing_info.h"
+#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24
+
+struct phyrx_pkt_end_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t __reserved_g_0001 : 1,
+ location_info_valid : 1,
+ timing_info_valid : 1,
+ rssi_info_valid : 1,
+ reserved_0a : 1,
+ frameless_frame_received : 1,
+ reserved_0b : 2,
+ rssi_comb : 8,
+ reserved_0c : 16;
+ struct rx_timing_info rx_timing_info_details;
+ struct receive_rssi_info post_rssi_info_details;
+ uint32_t phy_sw_status_31_0 : 32;
+ uint32_t phy_sw_status_63_32 : 32;
+#else
+ uint32_t reserved_0c : 16,
+ rssi_comb : 8,
+ reserved_0b : 2,
+ frameless_frame_received : 1,
+ reserved_0a : 1,
+ rssi_info_valid : 1,
+ timing_info_valid : 1,
+ location_info_valid : 1,
+ __reserved_g_0001 : 1;
+ struct rx_timing_info rx_timing_info_details;
+ struct receive_rssi_info post_rssi_info_details;
+ uint32_t phy_sw_status_31_0 : 32;
+ uint32_t phy_sw_status_63_32 : 32;
+#endif
+};
+
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1
+#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002
+
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2
+#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004
+
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3
+#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008
+
+#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4
+#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4
+#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010
+
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5
+#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020
+
+#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6
+#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7
+#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0
+
+#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8
+#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15
+#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16
+#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31
+#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
+
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB 12
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31
+#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xfffff000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31
+#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
+
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff
+
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31
+#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_rssi_legacy.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_rssi_legacy.h
new file mode 100644
index 0000000000000000000000000000000000000000..61f865a012ce4608bf5068f38170bc1680946225
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_rssi_legacy.h
@@ -0,0 +1,811 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_RSSI_LEGACY_H_
+#define _PHYRX_RSSI_LEGACY_H_
+
+#include "receive_rssi_info.h"
+#include "receive_pkt_start_info.h"
+#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42
+
+struct phyrx_rssi_legacy {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct receive_pkt_start_info rx_pkt_start_details;
+ uint32_t sw_phy_meta_data : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ struct receive_rssi_info pre_rssi_info_details;
+ struct receive_rssi_info preamble_rssi_info_details;
+ uint32_t pre_rssi_comb : 8,
+ rssi_comb : 8,
+ normalized_pre_rssi_comb : 8,
+ normalized_rssi_comb : 8;
+ uint32_t rssi_comb_ppdu : 8,
+ rssi_db_to_dbm_offset : 8,
+ rssi_for_spatial_reuse : 8,
+ rssi_for_trigger_resp : 8;
+#else
+ struct receive_pkt_start_info rx_pkt_start_details;
+ uint32_t sw_phy_meta_data : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ struct receive_rssi_info pre_rssi_info_details;
+ struct receive_rssi_info preamble_rssi_info_details;
+ uint32_t normalized_rssi_comb : 8,
+ normalized_pre_rssi_comb : 8,
+ rssi_comb : 8,
+ pre_rssi_comb : 8;
+ uint32_t rssi_for_trigger_resp : 8,
+ rssi_for_spatial_reuse : 8,
+ rssi_db_to_dbm_offset : 8,
+ rssi_comb_ppdu : 8;
+#endif
+};
+
+#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_LSB 0
+#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MSB 3
+#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MASK 0x0000000f
+
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_LSB 4
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MSB 4
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MASK 0x00000010
+
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB 5
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB 7
+#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK 0x000000e0
+
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_LSB 8
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MSB 15
+#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_LSB 16
+#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MSB 31
+#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MASK 0xffff0000
+
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_LSB 0
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MSB 31
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff
+
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_LSB 0
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MSB 31
+#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c
+#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_LSB 8
+#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_MSB 8
+#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_MASK 0x00000100
+
+#define PHYRX_RSSI_LEGACY_RESERVED_3A_OFFSET 0x0000000c
+#define PHYRX_RSSI_LEGACY_RESERVED_3A_LSB 9
+#define PHYRX_RSSI_LEGACY_RESERVED_3A_MSB 31
+#define PHYRX_RSSI_LEGACY_RESERVED_3A_MASK 0xfffffe00
+
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x00000010
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 0
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 31
+#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0xffffffff
+
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x00000014
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 0
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 31
+#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0xffffffff
+
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x00000018
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31
+#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0xffffffff
+
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000001c
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 0
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 31
+#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000008c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000008c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000008c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000008c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000090
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000094
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000094
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000094
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000094
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000098
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000009c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000009c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000009c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000009c
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31
+#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x000000a0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7
+#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x000000a0
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x000000a0
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23
+#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x000000a0
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31
+#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0xff000000
+
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x000000a4
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 0
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 7
+#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff
+
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x000000a4
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 8
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 15
+#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff00
+
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x000000a4
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 16
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 23
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff0000
+
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x000000a4
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 24
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 31
+#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_user_info.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_user_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..b3b4cb6ced1526424c26b100436c34f42180063c
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_user_info.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_USER_INFO_H_
+#define _PHYRX_USER_INFO_H_
+
+#include "receive_user_info.h"
+#define NUM_OF_DWORDS_PHYRX_USER_INFO 8
+
+struct phyrx_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct receive_user_info receive_user_info_details;
+#else
+ struct receive_user_info receive_user_info_details;
+#endif
+};
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 3
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 5
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 7
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 7
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x00000080
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 16
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 18
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00070000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 19
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 23
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f80000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x00000004
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 24
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x000000fe
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x00000700
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x00003800
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x00004000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00008000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x000f0000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x00f00000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x0f000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x00000008
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0xf0000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 5
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 6
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 7
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c0
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 8
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 13
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f00
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 14
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 15
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 16
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 21
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f0000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 22
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 23
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c00000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 24
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 29
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 30
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc0000000
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x00000010
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0xffffffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x00000014
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x00000018
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0xffffffff
+
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000001c
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 0
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 31
+#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phyrx_vht_sig_a.h b/drivers/staging/fw-api/hw/peach/v1/phyrx_vht_sig_a.h
new file mode 100644
index 0000000000000000000000000000000000000000..dda1c96b070d010eda88ef2ab34d3a84fa27e6d4
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phyrx_vht_sig_a.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYRX_VHT_SIG_A_H_
+#define _PHYRX_VHT_SIG_A_H_
+
+#include "vht_sig_a_info.h"
+#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2
+
+struct phyrx_vht_sig_a {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct vht_sig_a_info phyrx_vht_sig_a_info_details;
+#else
+ struct vht_sig_a_info phyrx_vht_sig_a_info_details;
+#endif
+};
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 1
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 2
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 3
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 7
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 8
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 9
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 17
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 23
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 30
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f000000
+
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phytx_abort_request_info.h b/drivers/staging/fw-api/hw/peach/v1/phytx_abort_request_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..85b70949c5796f4a7afe5577e92f1ebadabfdfdd
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phytx_abort_request_info.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYTX_ABORT_REQUEST_INFO_H_
+#define _PHYTX_ABORT_REQUEST_INFO_H_
+
+#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1
+
+struct phytx_abort_request_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint16_t phytx_abort_reason : 8,
+ user_number : 6,
+ reserved : 2;
+#else
+ uint16_t reserved : 2,
+ user_number : 6,
+ phytx_abort_reason : 8;
+#endif
+};
+
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7
+#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff
+
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13
+#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00
+
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15
+#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phytx_pkt_end.h b/drivers/staging/fw-api/hw/peach/v1/phytx_pkt_end.h
new file mode 100644
index 0000000000000000000000000000000000000000..d055a48ac3d4bb4ce8cec6f28c7094d4ee2cc210
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phytx_pkt_end.h
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYTX_PKT_END_H_
+#define _PHYTX_PKT_END_H_
+
+#define NUM_OF_WORDS_PHYTX_PKT_END 26
+
+#define NUM_OF_DWORDS_PHYTX_PKT_END 13
+
+struct phytx_pkt_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint16_t start_of_frame_timestamp_15_0 : 16;
+ uint16_t start_of_frame_timestamp_31_16 : 16;
+ uint16_t end_of_frame_timestamp_15_0 : 16;
+ uint16_t end_of_frame_timestamp_31_16 : 16;
+ uint16_t tx_group_delay : 12,
+ timing_status : 2,
+ phyrx_entered_nap_state : 1,
+ dpdtrain_done : 1;
+ uint16_t transmit_delay : 16;
+ uint16_t tpc_dbg_info_cmn_15_0 : 16;
+ uint16_t tpc_dbg_info_cmn_31_16 : 16;
+ uint16_t tpc_dbg_info_cmn_47_32 : 16;
+ uint16_t tpc_dbg_info_chn1_15_0 : 16;
+ uint16_t tpc_dbg_info_chn1_31_16 : 16;
+ uint16_t tpc_dbg_info_chn1_47_32 : 16;
+ uint16_t tpc_dbg_info_chn1_63_48 : 16;
+ uint16_t tpc_dbg_info_chn1_79_64 : 16;
+ uint16_t tpc_dbg_info_chn2_15_0 : 16;
+ uint16_t tpc_dbg_info_chn2_31_16 : 16;
+ uint16_t tpc_dbg_info_chn2_47_32 : 16;
+ uint16_t tpc_dbg_info_chn2_63_48 : 16;
+ uint16_t tpc_dbg_info_chn2_79_64 : 16;
+ uint16_t phytx_tx_end_sw_info_15_0 : 16;
+ uint16_t phytx_tx_end_sw_info_31_16 : 16;
+ uint16_t phytx_tx_end_sw_info_47_32 : 16;
+ uint16_t phytx_tx_end_sw_info_63_48 : 16;
+ uint16_t beamform_masked_user_bitmap_15_0 : 16;
+ uint16_t beamform_masked_user_bitmap_31_16 : 16;
+ uint16_t beamform_masked_user_bitmap_36_32 : 5,
+ reserved_23 : 11;
+#else
+ uint16_t start_of_frame_timestamp_15_0 : 16;
+ uint16_t start_of_frame_timestamp_31_16 : 16;
+ uint16_t end_of_frame_timestamp_15_0 : 16;
+ uint16_t end_of_frame_timestamp_31_16 : 16;
+ uint16_t dpdtrain_done : 1,
+ phyrx_entered_nap_state : 1,
+ timing_status : 2,
+ tx_group_delay : 12;
+ uint16_t transmit_delay : 16;
+ uint16_t tpc_dbg_info_cmn_15_0 : 16;
+ uint16_t tpc_dbg_info_cmn_31_16 : 16;
+ uint16_t tpc_dbg_info_cmn_47_32 : 16;
+ uint16_t tpc_dbg_info_chn1_15_0 : 16;
+ uint16_t tpc_dbg_info_chn1_31_16 : 16;
+ uint16_t tpc_dbg_info_chn1_47_32 : 16;
+ uint16_t tpc_dbg_info_chn1_63_48 : 16;
+ uint16_t tpc_dbg_info_chn1_79_64 : 16;
+ uint16_t tpc_dbg_info_chn2_15_0 : 16;
+ uint16_t tpc_dbg_info_chn2_31_16 : 16;
+ uint16_t tpc_dbg_info_chn2_47_32 : 16;
+ uint16_t tpc_dbg_info_chn2_63_48 : 16;
+ uint16_t tpc_dbg_info_chn2_79_64 : 16;
+ uint16_t phytx_tx_end_sw_info_15_0 : 16;
+ uint16_t phytx_tx_end_sw_info_31_16 : 16;
+ uint16_t phytx_tx_end_sw_info_47_32 : 16;
+ uint16_t phytx_tx_end_sw_info_63_48 : 16;
+ uint16_t beamform_masked_user_bitmap_15_0 : 16;
+ uint16_t beamform_masked_user_bitmap_31_16 : 16;
+ uint16_t reserved_23 : 11,
+ beamform_masked_user_bitmap_36_32 : 5;
+#endif
+};
+
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000000
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000002
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 0
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 15
+#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000004
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 0
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 15
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000006
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 0
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 15
+#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET 0x00000008
+#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB 0
+#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB 11
+#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK 0x00000fff
+
+#define PHYTX_PKT_END_TIMING_STATUS_OFFSET 0x00000008
+#define PHYTX_PKT_END_TIMING_STATUS_LSB 12
+#define PHYTX_PKT_END_TIMING_STATUS_MSB 13
+#define PHYTX_PKT_END_TIMING_STATUS_MASK 0x00003000
+
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET 0x00000008
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB 14
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB 14
+#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK 0x00004000
+
+#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET 0x00000008
+#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB 15
+#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB 15
+#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK 0x00008000
+
+#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET 0x0000000a
+#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB 0
+#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB 15
+#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000c
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB 0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB 15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000e
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB 0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB 15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET 0x00000010
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB 0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB 15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x00000012
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB 0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB 15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x00000014
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB 0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB 15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x00000016
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB 0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB 15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x00000018
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB 0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB 15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000001a
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB 0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB 15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000001c
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB 0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB 15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000001e
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB 0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB 15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x00000020
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB 0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB 15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x00000022
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB 0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB 15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x00000024
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB 0
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB 15
+#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x00000026
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x00000028
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB 0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB 15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000002a
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB 0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB 15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000002c
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB 0
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB 15
+#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000002e
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x00000030
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 0
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 15
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x0000ffff
+
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000032
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 0
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 4
+#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x0000001f
+
+#define PHYTX_PKT_END_RESERVED_23_OFFSET 0x00000032
+#define PHYTX_PKT_END_RESERVED_23_LSB 5
+#define PHYTX_PKT_END_RESERVED_23_MSB 15
+#define PHYTX_PKT_END_RESERVED_23_MASK 0x0000ffe0
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/phytx_ppdu_header_info_request.h b/drivers/staging/fw-api/hw/peach/v1/phytx_ppdu_header_info_request.h
new file mode 100644
index 0000000000000000000000000000000000000000..c0d81901da8498b347a6ba6aa2fa99075c0454c3
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/phytx_ppdu_header_info_request.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
+#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
+
+#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2
+
+#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1
+
+struct phytx_ppdu_header_info_request {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint16_t request_type : 5,
+ reserved : 11;
+ uint16_t tlv32_padding : 16;
+#else
+ uint16_t reserved : 11,
+ request_type : 5;
+ uint16_t tlv32_padding : 16;
+#endif
+};
+
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f
+
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0
+
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15
+#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/receive_pkt_start_info.h b/drivers/staging/fw-api/hw/peach/v1/receive_pkt_start_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..d1c935cc6e728a312bb328f04675be77ebe770ca
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/receive_pkt_start_info.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVE_PKT_START_INFO_H_
+#define _RECEIVE_PKT_START_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4
+
+struct receive_pkt_start_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t reception_type : 4,
+ rx_chain_mask_type : 1,
+ receive_bandwidth : 3,
+ rx_chain_mask : 8,
+ phy_ppdu_id : 16;
+ uint32_t ppdu_start_timestamp_31_0 : 32;
+ uint32_t ppdu_start_timestamp_63_32 : 32;
+ uint32_t preamble_time_to_rxframe : 8,
+ standalone_sniffer_mode : 1,
+ reserved_3a : 23;
+#else
+ uint32_t phy_ppdu_id : 16,
+ rx_chain_mask : 8,
+ receive_bandwidth : 3,
+ rx_chain_mask_type : 1,
+ reception_type : 4;
+ uint32_t ppdu_start_timestamp_31_0 : 32;
+ uint32_t ppdu_start_timestamp_63_32 : 32;
+ uint32_t reserved_3a : 23,
+ standalone_sniffer_mode : 1,
+ preamble_time_to_rxframe : 8;
+#endif
+};
+
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET 0x00000000
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB 0
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB 3
+#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK 0x0000000f
+
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB 4
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB 4
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK 0x00000010
+
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000000
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB 5
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB 7
+#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK 0x000000e0
+
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET 0x00000000
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB 8
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB 15
+#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK 0x0000ff00
+
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET 0x00000000
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB 16
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB 31
+#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB 0
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB 31
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff
+
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB 0
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB 31
+#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff
+
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB 0
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB 7
+#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff
+
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB 8
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB 8
+#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK 0x00000100
+
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET 0x0000000c
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB 9
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB 31
+#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK 0xfffffe00
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/receive_rssi_info.h b/drivers/staging/fw-api/hw/peach/v1/receive_rssi_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..43fd1796f0eb4ba0e96a4066d5e471edc2697a00
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/receive_rssi_info.h
@@ -0,0 +1,477 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVE_RSSI_INFO_H_
+#define _RECEIVE_RSSI_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16
+
+struct receive_rssi_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t rssi_pri20_chain0 : 8,
+ rssi_ext20_chain0 : 8,
+ rssi_ext40_low20_chain0 : 8,
+ rssi_ext40_high20_chain0 : 8;
+ uint32_t rssi_ext80_low20_chain0 : 8,
+ rssi_ext80_low_high20_chain0 : 8,
+ rssi_ext80_high_low20_chain0 : 8,
+ rssi_ext80_high20_chain0 : 8;
+ uint32_t rssi_ext160_0_chain0 : 8,
+ rssi_ext160_1_chain0 : 8,
+ rssi_ext160_2_chain0 : 8,
+ rssi_ext160_3_chain0 : 8;
+ uint32_t rssi_ext160_4_chain0 : 8,
+ rssi_ext160_5_chain0 : 8,
+ rssi_ext160_6_chain0 : 8,
+ rssi_ext160_7_chain0 : 8;
+ uint32_t rssi_pri20_chain1 : 8,
+ rssi_ext20_chain1 : 8,
+ rssi_ext40_low20_chain1 : 8,
+ rssi_ext40_high20_chain1 : 8;
+ uint32_t rssi_ext80_low20_chain1 : 8,
+ rssi_ext80_low_high20_chain1 : 8,
+ rssi_ext80_high_low20_chain1 : 8,
+ rssi_ext80_high20_chain1 : 8;
+ uint32_t rssi_ext160_0_chain1 : 8,
+ rssi_ext160_1_chain1 : 8,
+ rssi_ext160_2_chain1 : 8,
+ rssi_ext160_3_chain1 : 8;
+ uint32_t rssi_ext160_4_chain1 : 8,
+ rssi_ext160_5_chain1 : 8,
+ rssi_ext160_6_chain1 : 8,
+ rssi_ext160_7_chain1 : 8;
+ uint32_t rssi_pri20_chain2 : 8,
+ rssi_ext20_chain2 : 8,
+ rssi_ext40_low20_chain2 : 8,
+ rssi_ext40_high20_chain2 : 8;
+ uint32_t rssi_ext80_low20_chain2 : 8,
+ rssi_ext80_low_high20_chain2 : 8,
+ rssi_ext80_high_low20_chain2 : 8,
+ rssi_ext80_high20_chain2 : 8;
+ uint32_t rssi_ext160_0_chain2 : 8,
+ rssi_ext160_1_chain2 : 8,
+ rssi_ext160_2_chain2 : 8,
+ rssi_ext160_3_chain2 : 8;
+ uint32_t rssi_ext160_4_chain2 : 8,
+ rssi_ext160_5_chain2 : 8,
+ rssi_ext160_6_chain2 : 8,
+ rssi_ext160_7_chain2 : 8;
+ uint32_t rssi_pri20_chain3 : 8,
+ rssi_ext20_chain3 : 8,
+ rssi_ext40_low20_chain3 : 8,
+ rssi_ext40_high20_chain3 : 8;
+ uint32_t rssi_ext80_low20_chain3 : 8,
+ rssi_ext80_low_high20_chain3 : 8,
+ rssi_ext80_high_low20_chain3 : 8,
+ rssi_ext80_high20_chain3 : 8;
+ uint32_t rssi_ext160_0_chain3 : 8,
+ rssi_ext160_1_chain3 : 8,
+ rssi_ext160_2_chain3 : 8,
+ rssi_ext160_3_chain3 : 8;
+ uint32_t rssi_ext160_4_chain3 : 8,
+ rssi_ext160_5_chain3 : 8,
+ rssi_ext160_6_chain3 : 8,
+ rssi_ext160_7_chain3 : 8;
+#else
+ uint32_t rssi_ext40_high20_chain0 : 8,
+ rssi_ext40_low20_chain0 : 8,
+ rssi_ext20_chain0 : 8,
+ rssi_pri20_chain0 : 8;
+ uint32_t rssi_ext80_high20_chain0 : 8,
+ rssi_ext80_high_low20_chain0 : 8,
+ rssi_ext80_low_high20_chain0 : 8,
+ rssi_ext80_low20_chain0 : 8;
+ uint32_t rssi_ext160_3_chain0 : 8,
+ rssi_ext160_2_chain0 : 8,
+ rssi_ext160_1_chain0 : 8,
+ rssi_ext160_0_chain0 : 8;
+ uint32_t rssi_ext160_7_chain0 : 8,
+ rssi_ext160_6_chain0 : 8,
+ rssi_ext160_5_chain0 : 8,
+ rssi_ext160_4_chain0 : 8;
+ uint32_t rssi_ext40_high20_chain1 : 8,
+ rssi_ext40_low20_chain1 : 8,
+ rssi_ext20_chain1 : 8,
+ rssi_pri20_chain1 : 8;
+ uint32_t rssi_ext80_high20_chain1 : 8,
+ rssi_ext80_high_low20_chain1 : 8,
+ rssi_ext80_low_high20_chain1 : 8,
+ rssi_ext80_low20_chain1 : 8;
+ uint32_t rssi_ext160_3_chain1 : 8,
+ rssi_ext160_2_chain1 : 8,
+ rssi_ext160_1_chain1 : 8,
+ rssi_ext160_0_chain1 : 8;
+ uint32_t rssi_ext160_7_chain1 : 8,
+ rssi_ext160_6_chain1 : 8,
+ rssi_ext160_5_chain1 : 8,
+ rssi_ext160_4_chain1 : 8;
+ uint32_t rssi_ext40_high20_chain2 : 8,
+ rssi_ext40_low20_chain2 : 8,
+ rssi_ext20_chain2 : 8,
+ rssi_pri20_chain2 : 8;
+ uint32_t rssi_ext80_high20_chain2 : 8,
+ rssi_ext80_high_low20_chain2 : 8,
+ rssi_ext80_low_high20_chain2 : 8,
+ rssi_ext80_low20_chain2 : 8;
+ uint32_t rssi_ext160_3_chain2 : 8,
+ rssi_ext160_2_chain2 : 8,
+ rssi_ext160_1_chain2 : 8,
+ rssi_ext160_0_chain2 : 8;
+ uint32_t rssi_ext160_7_chain2 : 8,
+ rssi_ext160_6_chain2 : 8,
+ rssi_ext160_5_chain2 : 8,
+ rssi_ext160_4_chain2 : 8;
+ uint32_t rssi_ext40_high20_chain3 : 8,
+ rssi_ext40_low20_chain3 : 8,
+ rssi_ext20_chain3 : 8,
+ rssi_pri20_chain3 : 8;
+ uint32_t rssi_ext80_high20_chain3 : 8,
+ rssi_ext80_high_low20_chain3 : 8,
+ rssi_ext80_low_high20_chain3 : 8,
+ rssi_ext80_low20_chain3 : 8;
+ uint32_t rssi_ext160_3_chain3 : 8,
+ rssi_ext160_2_chain3 : 8,
+ rssi_ext160_1_chain3 : 8,
+ rssi_ext160_0_chain3 : 8;
+ uint32_t rssi_ext160_7_chain3 : 8,
+ rssi_ext160_6_chain3 : 8,
+ rssi_ext160_5_chain3 : 8,
+ rssi_ext160_4_chain3 : 8;
+#endif
+};
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000
+
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31
+#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/receive_user_info.h b/drivers/staging/fw-api/hw/peach/v1/receive_user_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..7ecc5e4232c4aa6c89eb77cc3423b8fcbd75a0c9
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/receive_user_info.h
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVE_USER_INFO_H_
+#define _RECEIVE_USER_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8
+
+struct receive_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t phy_ppdu_id : 16,
+ user_rssi : 8,
+ pkt_type : 4,
+ stbc : 1,
+ reception_type : 3;
+ uint32_t rate_mcs : 4,
+ sgi : 2,
+ __reserved_g_0004 : 1,
+ reserved_1a : 1,
+ mimo_ss_bitmap : 8,
+ receive_bandwidth : 3,
+ reserved_1b : 5,
+ dl_ofdma_user_index : 8;
+ uint32_t dl_ofdma_content_channel : 1,
+ reserved_2a : 7,
+ nss : 3,
+ stream_offset : 3,
+ sta_dcm : 1,
+ ldpc : 1,
+ ru_type_80_0 : 4,
+ ru_type_80_1 : 4,
+ ru_type_80_2 : 4,
+ ru_type_80_3 : 4;
+ uint32_t ru_start_index_80_0 : 6,
+ reserved_3a : 2,
+ ru_start_index_80_1 : 6,
+ reserved_3b : 2,
+ ru_start_index_80_2 : 6,
+ reserved_3c : 2,
+ ru_start_index_80_3 : 6,
+ reserved_3d : 2;
+ uint32_t user_fd_rssi_seg0 : 32;
+ uint32_t user_fd_rssi_seg1 : 32;
+ uint32_t user_fd_rssi_seg2 : 32;
+ uint32_t user_fd_rssi_seg3 : 32;
+#else
+ uint32_t reception_type : 3,
+ stbc : 1,
+ pkt_type : 4,
+ user_rssi : 8,
+ phy_ppdu_id : 16;
+ uint32_t dl_ofdma_user_index : 8,
+ reserved_1b : 5,
+ receive_bandwidth : 3,
+ mimo_ss_bitmap : 8,
+ reserved_1a : 1,
+ __reserved_g_0004 : 1,
+ sgi : 2,
+ rate_mcs : 4;
+ uint32_t ru_type_80_3 : 4,
+ ru_type_80_2 : 4,
+ ru_type_80_1 : 4,
+ ru_type_80_0 : 4,
+ ldpc : 1,
+ sta_dcm : 1,
+ stream_offset : 3,
+ nss : 3,
+ reserved_2a : 7,
+ dl_ofdma_content_channel : 1;
+ uint32_t reserved_3d : 2,
+ ru_start_index_80_3 : 6,
+ reserved_3c : 2,
+ ru_start_index_80_2 : 6,
+ reserved_3b : 2,
+ ru_start_index_80_1 : 6,
+ reserved_3a : 2,
+ ru_start_index_80_0 : 6;
+ uint32_t user_fd_rssi_seg0 : 32;
+ uint32_t user_fd_rssi_seg1 : 32;
+ uint32_t user_fd_rssi_seg2 : 32;
+ uint32_t user_fd_rssi_seg3 : 32;
+#endif
+};
+
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15
+#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000
+#define RECEIVE_USER_INFO_USER_RSSI_LSB 16
+#define RECEIVE_USER_INFO_USER_RSSI_MSB 23
+#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000
+
+#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000
+#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24
+#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27
+#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000
+
+#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000
+#define RECEIVE_USER_INFO_STBC_LSB 28
+#define RECEIVE_USER_INFO_STBC_MSB 28
+#define RECEIVE_USER_INFO_STBC_MASK 0x10000000
+
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31
+#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000
+
+#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_RATE_MCS_LSB 0
+#define RECEIVE_USER_INFO_RATE_MCS_MSB 3
+#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000000f
+
+#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_SGI_LSB 4
+#define RECEIVE_USER_INFO_SGI_MSB 5
+#define RECEIVE_USER_INFO_SGI_MASK 0x00000030
+
+#define RECEIVE_USER_INFO_RESERVED_1A_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_RESERVED_1A_LSB 7
+#define RECEIVE_USER_INFO_RESERVED_1A_MSB 7
+#define RECEIVE_USER_INFO_RESERVED_1A_MASK 0x00000080
+
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15
+#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00
+
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18
+#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000
+
+#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19
+#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23
+#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000
+
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31
+#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000
+
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0
+#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001
+
+#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1
+#define RECEIVE_USER_INFO_RESERVED_2A_MSB 7
+#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x000000fe
+
+#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_NSS_LSB 8
+#define RECEIVE_USER_INFO_NSS_MSB 10
+#define RECEIVE_USER_INFO_NSS_MASK 0x00000700
+
+#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11
+#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13
+#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800
+
+#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_STA_DCM_LSB 14
+#define RECEIVE_USER_INFO_STA_DCM_MSB 14
+#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000
+
+#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_LDPC_LSB 15
+#define RECEIVE_USER_INFO_LDPC_MSB 15
+#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19
+#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23
+#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27
+#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000
+
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31
+#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f
+
+#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6
+#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7
+#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00
+
+#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14
+#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15
+#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000
+
+#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22
+#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23
+#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000
+
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29
+#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000
+
+#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c
+#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30
+#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31
+#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff
+
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31
+#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/received_response_user_15_8.h b/drivers/staging/fw-api/hw/peach/v1/received_response_user_15_8.h
new file mode 100644
index 0000000000000000000000000000000000000000..bce76aff2a0036b248ee4656183ec9a6d36ed84c
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/received_response_user_15_8.h
@@ -0,0 +1,1126 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_RESPONSE_USER_15_8_H_
+#define _RECEIVED_RESPONSE_USER_15_8_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64
+
+struct received_response_user_15_8 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct received_response_user_info received_response_details_user8;
+ struct received_response_user_info received_response_details_user9;
+ struct received_response_user_info received_response_details_user10;
+ struct received_response_user_info received_response_details_user11;
+ struct received_response_user_info received_response_details_user12;
+ struct received_response_user_info received_response_details_user13;
+ struct received_response_user_info received_response_details_user14;
+ struct received_response_user_info received_response_details_user15;
+#else
+ struct received_response_user_info received_response_details_user8;
+ struct received_response_user_info received_response_details_user9;
+ struct received_response_user_info received_response_details_user10;
+ struct received_response_user_info received_response_details_user11;
+ struct received_response_user_info received_response_details_user12;
+ struct received_response_user_info received_response_details_user13;
+ struct received_response_user_info received_response_details_user14;
+ struct received_response_user_info received_response_details_user15;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x00000008
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x00000028
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000002c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET 0x0000002c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x00000048
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000004c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET 0x0000004c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x00000068
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000006c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET 0x0000006c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x00000088
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000008c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET 0x0000008c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x000000a8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x000000ac
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET 0x000000ac
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x000000c8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x000000cc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET 0x000000cc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x000000e8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x000000ec
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET 0x000000ec
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/received_response_user_23_16.h b/drivers/staging/fw-api/hw/peach/v1/received_response_user_23_16.h
new file mode 100644
index 0000000000000000000000000000000000000000..ccd2d9191078317c8d053cbb8f5931d1cef4ab61
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/received_response_user_23_16.h
@@ -0,0 +1,1126 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_RESPONSE_USER_23_16_H_
+#define _RECEIVED_RESPONSE_USER_23_16_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64
+
+struct received_response_user_23_16 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct received_response_user_info received_response_details_user16;
+ struct received_response_user_info received_response_details_user17;
+ struct received_response_user_info received_response_details_user18;
+ struct received_response_user_info received_response_details_user19;
+ struct received_response_user_info received_response_details_user20;
+ struct received_response_user_info received_response_details_user21;
+ struct received_response_user_info received_response_details_user22;
+ struct received_response_user_info received_response_details_user23;
+#else
+ struct received_response_user_info received_response_details_user16;
+ struct received_response_user_info received_response_details_user17;
+ struct received_response_user_info received_response_details_user18;
+ struct received_response_user_info received_response_details_user19;
+ struct received_response_user_info received_response_details_user20;
+ struct received_response_user_info received_response_details_user21;
+ struct received_response_user_info received_response_details_user22;
+ struct received_response_user_info received_response_details_user23;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x00000008
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x00000028
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000002c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET 0x0000002c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x00000048
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000004c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET 0x0000004c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x00000068
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000006c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET 0x0000006c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x00000088
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000008c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET 0x0000008c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x000000a8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x000000ac
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET 0x000000ac
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x000000c8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x000000cc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET 0x000000cc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x000000e8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x000000ec
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET 0x000000ec
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/received_response_user_31_24.h b/drivers/staging/fw-api/hw/peach/v1/received_response_user_31_24.h
new file mode 100644
index 0000000000000000000000000000000000000000..81db62baa5daa9a978378908b9cbf76cc9aae283
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/received_response_user_31_24.h
@@ -0,0 +1,1126 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_RESPONSE_USER_31_24_H_
+#define _RECEIVED_RESPONSE_USER_31_24_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64
+
+struct received_response_user_31_24 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct received_response_user_info received_response_details_user24;
+ struct received_response_user_info received_response_details_user25;
+ struct received_response_user_info received_response_details_user26;
+ struct received_response_user_info received_response_details_user27;
+ struct received_response_user_info received_response_details_user28;
+ struct received_response_user_info received_response_details_user29;
+ struct received_response_user_info received_response_details_user30;
+ struct received_response_user_info received_response_details_user31;
+#else
+ struct received_response_user_info received_response_details_user24;
+ struct received_response_user_info received_response_details_user25;
+ struct received_response_user_info received_response_details_user26;
+ struct received_response_user_info received_response_details_user27;
+ struct received_response_user_info received_response_details_user28;
+ struct received_response_user_info received_response_details_user29;
+ struct received_response_user_info received_response_details_user30;
+ struct received_response_user_info received_response_details_user31;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x00000008
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x00000028
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000002c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET 0x0000002c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x00000048
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000004c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET 0x0000004c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x00000068
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000006c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET 0x0000006c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x00000088
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000008c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET 0x0000008c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x000000a8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x000000ac
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET 0x000000ac
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x000000c8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x000000cc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET 0x000000cc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x000000e8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x000000ec
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET 0x000000ec
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/received_response_user_36_32.h b/drivers/staging/fw-api/hw/peach/v1/received_response_user_36_32.h
new file mode 100644
index 0000000000000000000000000000000000000000..9ba8ee5d23e25c399edebc4ef7b28224cd2ca8d8
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/received_response_user_36_32.h
@@ -0,0 +1,715 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_RESPONSE_USER_36_32_H_
+#define _RECEIVED_RESPONSE_USER_36_32_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40
+
+struct received_response_user_36_32 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct received_response_user_info received_response_details_user32;
+ struct received_response_user_info received_response_details_user33;
+ struct received_response_user_info received_response_details_user34;
+ struct received_response_user_info received_response_details_user35;
+ struct received_response_user_info received_response_details_user36;
+#else
+ struct received_response_user_info received_response_details_user32;
+ struct received_response_user_info received_response_details_user33;
+ struct received_response_user_info received_response_details_user34;
+ struct received_response_user_info received_response_details_user35;
+ struct received_response_user_info received_response_details_user36;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x00000008
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x00000028
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000002c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000002c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x00000048
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000004c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000004c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x00000068
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000006c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000006c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x00000088
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000008c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000008c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/received_response_user_7_0.h b/drivers/staging/fw-api/hw/peach/v1/received_response_user_7_0.h
new file mode 100644
index 0000000000000000000000000000000000000000..6b39f5cbea9db18609cadb14fdf12a6c745b6466
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/received_response_user_7_0.h
@@ -0,0 +1,1126 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_RESPONSE_USER_7_0_H_
+#define _RECEIVED_RESPONSE_USER_7_0_H_
+
+#include "received_response_user_info.h"
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64
+
+struct received_response_user_7_0 {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct received_response_user_info received_response_details_user0;
+ struct received_response_user_info received_response_details_user1;
+ struct received_response_user_info received_response_details_user2;
+ struct received_response_user_info received_response_details_user3;
+ struct received_response_user_info received_response_details_user4;
+ struct received_response_user_info received_response_details_user5;
+ struct received_response_user_info received_response_details_user6;
+ struct received_response_user_info received_response_details_user7;
+#else
+ struct received_response_user_info received_response_details_user0;
+ struct received_response_user_info received_response_details_user1;
+ struct received_response_user_info received_response_details_user2;
+ struct received_response_user_info received_response_details_user3;
+ struct received_response_user_info received_response_details_user4;
+ struct received_response_user_info received_response_details_user5;
+ struct received_response_user_info received_response_details_user6;
+ struct received_response_user_info received_response_details_user7;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x00000008
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x00000020
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x00000024
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x00000028
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000002c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET 0x0000002c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x00000040
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x00000044
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x00000048
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000004c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET 0x0000004c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x00000060
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x00000064
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x00000068
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000006c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET 0x0000006c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x00000080
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x00000084
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x00000088
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000008c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET 0x0000008c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x000000a0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x000000a4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x000000a8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x000000ac
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET 0x000000ac
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x000000c0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x000000c4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x000000c8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x000000cc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET 0x000000cc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x000000e0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x000000e4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x000000e8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x000000ec
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET 0x000000ec
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/received_response_user_info.h b/drivers/staging/fw-api/hw/peach/v1/received_response_user_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..0f2676619a212057df049383bf77f767893ec513
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/received_response_user_info.h
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_RESPONSE_USER_INFO_H_
+#define _RECEIVED_RESPONSE_USER_INFO_H_
+
+#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8
+
+struct received_response_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t mpdu_fcs_pass_count : 12,
+ mpdu_fcs_fail_count : 12,
+ qosnull_frame_count : 4,
+ reserved_0a : 3,
+ user_info_valid : 1;
+ uint32_t null_delimiter_count : 22,
+ reserved_1a : 9,
+ ht_control_valid : 1;
+ uint32_t ht_control : 32;
+ uint32_t qos_control_valid : 16,
+ eosp : 16;
+ uint32_t qos_control_15_8_tid_0 : 8,
+ qos_control_15_8_tid_1 : 8,
+ qos_control_15_8_tid_2 : 8,
+ qos_control_15_8_tid_3 : 8;
+ uint32_t qos_control_15_8_tid_4 : 8,
+ qos_control_15_8_tid_5 : 8,
+ qos_control_15_8_tid_6 : 8,
+ qos_control_15_8_tid_7 : 8;
+ uint32_t qos_control_15_8_tid_8 : 8,
+ qos_control_15_8_tid_9 : 8,
+ qos_control_15_8_tid_10 : 8,
+ qos_control_15_8_tid_11 : 8;
+ uint32_t qos_control_15_8_tid_12 : 8,
+ qos_control_15_8_tid_13 : 8,
+ qos_control_15_8_tid_14 : 8,
+ qos_control_15_8_tid_15 : 8;
+#else
+ uint32_t user_info_valid : 1,
+ reserved_0a : 3,
+ qosnull_frame_count : 4,
+ mpdu_fcs_fail_count : 12,
+ mpdu_fcs_pass_count : 12;
+ uint32_t ht_control_valid : 1,
+ reserved_1a : 9,
+ null_delimiter_count : 22;
+ uint32_t ht_control : 32;
+ uint32_t eosp : 16,
+ qos_control_valid : 16;
+ uint32_t qos_control_15_8_tid_3 : 8,
+ qos_control_15_8_tid_2 : 8,
+ qos_control_15_8_tid_1 : 8,
+ qos_control_15_8_tid_0 : 8;
+ uint32_t qos_control_15_8_tid_7 : 8,
+ qos_control_15_8_tid_6 : 8,
+ qos_control_15_8_tid_5 : 8,
+ qos_control_15_8_tid_4 : 8;
+ uint32_t qos_control_15_8_tid_11 : 8,
+ qos_control_15_8_tid_10 : 8,
+ qos_control_15_8_tid_9 : 8,
+ qos_control_15_8_tid_8 : 8;
+ uint32_t qos_control_15_8_tid_15 : 8,
+ qos_control_15_8_tid_14 : 8,
+ qos_control_15_8_tid_13 : 8,
+ qos_control_15_8_tid_12 : 8;
+#endif
+};
+
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
+
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23
+#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27
+#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000
+
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000
+
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21
+#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff
+
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30
+#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000
+
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000
+
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31
+#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff
+
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31
+#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
+
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31
+#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/received_trigger_info.h b/drivers/staging/fw-api/hw/peach/v1/received_trigger_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..965dce76fbc4645bf68402e979f2d367990e4071
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/received_trigger_info.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_TRIGGER_INFO_H_
+#define _RECEIVED_TRIGGER_INFO_H_
+
+#include "received_trigger_info_details.h"
+#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 5
+
+struct received_trigger_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct received_trigger_info_details received_trigger_details;
+#else
+ struct received_trigger_info_details received_trigger_details;
+#endif
+};
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x0000000f
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_LSB 29
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MSB 30
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 15
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 28
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0xf0000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x00000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x00000008
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0xffff0000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000c
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 15
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000c
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 25
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xfe000000
+
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x00000010
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31
+#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/received_trigger_info_details.h b/drivers/staging/fw-api/hw/peach/v1/received_trigger_info_details.h
new file mode 100644
index 0000000000000000000000000000000000000000..b162adf0d8bcb7dee8e31ba1f057d9f62d38f7ca
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/received_trigger_info_details.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_
+#define _RECEIVED_TRIGGER_INFO_DETAILS_H_
+
+#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5
+
+struct received_trigger_info_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t trigger_type : 4,
+ ax_trigger_source : 1,
+ ax_trigger_type : 4,
+ trigger_source_sta_full_aid : 13,
+ frame_control_valid : 1,
+ qos_control_valid : 1,
+ he_control_info_valid : 1,
+ __reserved_g_0005_trigger_subtype : 4,
+ txop_sharing_mode : 2,
+ tid_aggregation_limit_is_zero : 1;
+ uint32_t phy_ppdu_id : 16,
+ lsig_response_length : 12,
+ reserved_1a : 4;
+ uint32_t frame_control : 16,
+ qos_control : 16;
+ uint32_t sw_peer_id : 16,
+ txop_sharing_allocation_duration : 9,
+ reserved_3a : 7;
+ uint32_t he_control : 32;
+#else
+ uint32_t tid_aggregation_limit_is_zero : 1,
+ txop_sharing_mode : 2,
+ __reserved_g_0005_trigger_subtype : 4,
+ he_control_info_valid : 1,
+ qos_control_valid : 1,
+ frame_control_valid : 1,
+ trigger_source_sta_full_aid : 13,
+ ax_trigger_type : 4,
+ ax_trigger_source : 1,
+ trigger_type : 4;
+ uint32_t reserved_1a : 4,
+ lsig_response_length : 12,
+ phy_ppdu_id : 16;
+ uint32_t qos_control : 16,
+ frame_control : 16;
+ uint32_t reserved_3a : 7,
+ txop_sharing_allocation_duration : 9,
+ sw_peer_id : 16;
+ uint32_t he_control : 32;
+#endif
+};
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8
+#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21
+#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25
+#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28
+#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB 29
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB 30
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31
+#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15
+#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27
+#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 28
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0xf0000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15
+#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31
+#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15
+#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24
+#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 25
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31
+#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xfe000000
+
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31
+#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_descriptor_threshold_reached_status.h b/drivers/staging/fw-api/hw/peach/v1/reo_descriptor_threshold_reached_status.h
new file mode 100644
index 0000000000000000000000000000000000000000..6c63c1dc02971493f392fb92a20b16c3958c0aeb
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_descriptor_threshold_reached_status.h
@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 27
+
+struct reo_descriptor_threshold_reached_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv32_ring_padding : 32;
+ struct uniform_reo_status_header status_header;
+ uint32_t threshold_index : 2,
+ reserved_2 : 30;
+ uint32_t link_descriptor_counter0 : 24,
+ reserved_3 : 8;
+ uint32_t link_descriptor_counter1 : 24,
+ reserved_4 : 8;
+ uint32_t link_descriptor_counter2 : 24,
+ reserved_5 : 8;
+ uint32_t link_descriptor_counter_sum : 26,
+ reserved_6 : 6;
+ uint32_t reserved_7 : 32;
+ uint32_t reserved_8 : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 32;
+ uint32_t reserved_25a : 28,
+ looping_count : 4;
+#else
+ uint32_t tlv32_ring_padding : 32;
+ struct uniform_reo_status_header status_header;
+ uint32_t reserved_2 : 30,
+ threshold_index : 2;
+ uint32_t reserved_3 : 8,
+ link_descriptor_counter0 : 24;
+ uint32_t reserved_4 : 8,
+ link_descriptor_counter1 : 24;
+ uint32_t reserved_5 : 8,
+ link_descriptor_counter2 : 24;
+ uint32_t reserved_6 : 6,
+ link_descriptor_counter_sum : 26;
+ uint32_t reserved_7 : 32;
+ uint32_t reserved_8 : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 32;
+ uint32_t looping_count : 4,
+ reserved_25a : 28;
+#endif
+};
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET 0x0000000c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB 1
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK 0x00000003
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET 0x0000000c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB 2
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK 0xfffffffc
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x00000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB 23
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET 0x00000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB 24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK 0xff000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000014
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB 23
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET 0x00000014
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB 24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK 0xff000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB 23
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET 0x00000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB 24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK 0xff000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x0000001c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB 25
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET 0x0000001c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB 26
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK 0xfc000000
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET 0x00000020
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET 0x00000024
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET 0x00000028
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET 0x0000002c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET 0x00000030
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET 0x00000034
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET 0x00000038
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET 0x0000003c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET 0x00000040
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET 0x00000044
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET 0x00000048
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET 0x0000004c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET 0x00000050
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET 0x00000054
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET 0x00000058
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET 0x0000005c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET 0x00000060
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET 0x00000064
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK 0xffffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET 0x00000068
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB 27
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK 0x0fffffff
+
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET 0x00000068
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB 28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB 31
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_destination_ring.h b/drivers/staging/fw-api/hw/peach/v1/reo_destination_ring.h
new file mode 100644
index 0000000000000000000000000000000000000000..fd54f690063dec08b3ba96fa481338ff5668813f
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_destination_ring.h
@@ -0,0 +1,275 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_DESTINATION_RING_H_
+#define _REO_DESTINATION_RING_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_REO_DESTINATION_RING 8
+
+struct reo_destination_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct buffer_addr_info buf_or_link_desc_addr_info;
+ struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+ struct rx_msdu_desc_info rx_msdu_desc_info_details;
+ uint32_t buffer_virt_addr_31_0 : 32;
+ uint32_t buffer_virt_addr_63_32 : 32;
+ uint32_t reo_dest_buffer_type : 1,
+ reo_push_reason : 2,
+ reo_error_code : 5,
+ captured_msdu_data_size : 4,
+ sw_exception : 1,
+ src_link_id : 3,
+ reo_destination_struct_signature : 4,
+ ring_id : 8,
+ looping_count : 4;
+#else
+ struct buffer_addr_info buf_or_link_desc_addr_info;
+ struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+ struct rx_msdu_desc_info rx_msdu_desc_info_details;
+ uint32_t buffer_virt_addr_31_0 : 32;
+ uint32_t buffer_virt_addr_63_32 : 32;
+ uint32_t looping_count : 4,
+ ring_id : 8,
+ reo_destination_struct_signature : 4,
+ src_link_id : 3,
+ sw_exception : 1,
+ captured_msdu_data_size : 4,
+ reo_error_code : 5,
+ reo_push_reason : 2,
+ reo_dest_buffer_type : 1;
+#endif
+};
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
+
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
+#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
+
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
+#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
+
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MSB 31
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_LSB 0
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MSB 31
+#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0
+#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001
+
+#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1
+#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2
+#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006
+
+#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3
+#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7
+#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8
+
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11
+#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00
+
+#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12
+#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12
+#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000
+
+#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13
+#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15
+#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000
+
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19
+#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000
+
+#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_RING_ID_LSB 20
+#define REO_DESTINATION_RING_RING_ID_MSB 27
+#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000
+
+#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28
+#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31
+#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_destination_ring_with_pn.h b/drivers/staging/fw-api/hw/peach/v1/reo_destination_ring_with_pn.h
new file mode 100644
index 0000000000000000000000000000000000000000..b8e162a8ab3396baaa07b6dbb79703835aafff1e
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_destination_ring_with_pn.h
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_DESTINATION_RING_WITH_PN_H_
+#define _REO_DESTINATION_RING_WITH_PN_H_
+
+#include "rx_msdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8
+
+struct reo_destination_ring_with_pn {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct buffer_addr_info buf_or_link_desc_addr_info;
+ uint32_t msdu_count : 8,
+ prev_pn_23_0 : 24;
+ uint32_t prev_pn_55_24 : 32;
+ struct rx_msdu_desc_info rx_msdu_desc_info_details;
+ uint32_t buffer_virt_addr_31_0 : 32;
+ uint32_t buffer_virt_addr_63_32 : 32;
+ uint32_t reo_dest_buffer_type : 1,
+ reo_push_reason : 2,
+ reo_error_code : 5,
+ captured_msdu_data_size : 4,
+ sw_exception : 1,
+ src_link_id : 3,
+ reo_destination_struct_signature : 4,
+ ring_id : 8,
+ looping_count : 4;
+#else
+ struct buffer_addr_info buf_or_link_desc_addr_info;
+ uint32_t prev_pn_23_0 : 24,
+ msdu_count : 8;
+ uint32_t prev_pn_55_24 : 32;
+ struct rx_msdu_desc_info rx_msdu_desc_info_details;
+ uint32_t buffer_virt_addr_31_0 : 32;
+ uint32_t buffer_virt_addr_63_32 : 32;
+ uint32_t looping_count : 4,
+ ring_id : 8,
+ reo_destination_struct_signature : 4,
+ src_link_id : 3,
+ sw_exception : 1,
+ captured_msdu_data_size : 4,
+ reo_error_code : 5,
+ reo_push_reason : 2,
+ reo_dest_buffer_type : 1;
+#endif
+};
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET 0x00000008
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB 7
+#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK 0x000000ff
+
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET 0x00000008
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB 8
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB 31
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK 0xffffff00
+
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_OFFSET 0x0000000c
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MSB 31
+#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
+
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
+#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
+
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MSB 31
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MSB 31
+#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
+
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB 0
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB 0
+#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK 0x00000001
+
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB 1
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB 2
+#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK 0x00000006
+
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB 3
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB 7
+#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK 0x000000f8
+
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB 8
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB 11
+#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00
+
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB 12
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB 12
+#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK 0x00001000
+
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB 13
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB 15
+#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK 0x0000e000
+
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19
+#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000
+
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB 20
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB 27
+#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK 0x0ff00000
+
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB 28
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB 31
+#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_entrance_ring.h b/drivers/staging/fw-api/hw/peach/v1/reo_entrance_ring.h
new file mode 100644
index 0000000000000000000000000000000000000000..c9c9df2bd53a88a748cd6e99efe0019e20b41502
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_entrance_ring.h
@@ -0,0 +1,252 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_ENTRANCE_RING_H_
+#define _REO_ENTRANCE_RING_H_
+
+#include "rx_mpdu_details.h"
+#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
+
+struct reo_entrance_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct rx_mpdu_details reo_level_mpdu_frame_info;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32;
+ uint32_t rx_reo_queue_desc_addr_39_32 : 8,
+ rounded_mpdu_byte_count : 14,
+ reo_destination_indication : 5,
+ frameless_bar : 1,
+ reserved_5a : 4;
+ uint32_t rxdma_push_reason : 2,
+ rxdma_error_code : 5,
+ mpdu_fragment_number : 4,
+ sw_exception : 1,
+ sw_exception_mpdu_delink : 1,
+ sw_exception_destination_ring_valid : 1,
+ sw_exception_destination_ring : 5,
+ mpdu_sequence_number : 12,
+ reserved_6a : 1;
+ uint32_t phy_ppdu_id : 16,
+ src_link_id : 3,
+ reserved_7a : 1,
+ ring_id : 8,
+ looping_count : 4;
+#else
+ struct rx_mpdu_details reo_level_mpdu_frame_info;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32;
+ uint32_t reserved_5a : 4,
+ frameless_bar : 1,
+ reo_destination_indication : 5,
+ rounded_mpdu_byte_count : 14,
+ rx_reo_queue_desc_addr_39_32 : 8;
+ uint32_t reserved_6a : 1,
+ mpdu_sequence_number : 12,
+ sw_exception_destination_ring : 5,
+ sw_exception_destination_ring_valid : 1,
+ sw_exception_mpdu_delink : 1,
+ sw_exception : 1,
+ mpdu_fragment_number : 4,
+ rxdma_error_code : 5,
+ rxdma_push_reason : 2;
+ uint32_t looping_count : 4,
+ ring_id : 8,
+ reserved_7a : 1,
+ src_link_id : 3,
+ phy_ppdu_id : 16;
+#endif
+};
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
+
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
+#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
+#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21
+#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00
+
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26
+#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000
+
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27
+#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000
+
+#define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_RESERVED_5A_LSB 28
+#define REO_ENTRANCE_RING_RESERVED_5A_MSB 31
+#define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000
+
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1
+#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003
+
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6
+#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c
+
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10
+#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12
+#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000
+
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18
+#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000
+
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30
+#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000
+
+#define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_RESERVED_6A_LSB 31
+#define REO_ENTRANCE_RING_RESERVED_6A_MSB 31
+#define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000
+
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15
+#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16
+#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18
+#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000
+
+#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_RESERVED_7A_LSB 19
+#define REO_ENTRANCE_RING_RESERVED_7A_MSB 19
+#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000
+
+#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_RING_ID_LSB 20
+#define REO_ENTRANCE_RING_RING_ID_MSB 27
+#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000
+
+#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28
+#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31
+#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_flush_cache.h b/drivers/staging/fw-api/hw/peach/v1/reo_flush_cache.h
new file mode 100644
index 0000000000000000000000000000000000000000..1d6e09f51d6f6b8000a5d0137076c80ed9f3ebba
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_flush_cache.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_FLUSH_CACHE_H_
+#define _REO_FLUSH_CACHE_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9
+
+struct reo_flush_cache {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t flush_addr_31_0 : 32;
+ uint32_t flush_addr_39_32 : 8,
+ forward_all_mpdus_in_queue : 1,
+ release_cache_block_index : 1,
+ cache_block_resource_index : 2,
+ flush_without_invalidate : 1,
+ block_cache_usage_after_flush : 1,
+ flush_entire_cache : 1,
+ flush_queue_1k_desc : 1,
+ reserved_2b : 16;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+#else
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t flush_addr_31_0 : 32;
+ uint32_t reserved_2b : 16,
+ flush_queue_1k_desc : 1,
+ flush_entire_cache : 1,
+ block_cache_usage_after_flush : 1,
+ flush_without_invalidate : 1,
+ cache_block_resource_index : 2,
+ release_cache_block_index : 1,
+ forward_all_mpdus_in_queue : 1,
+ flush_addr_39_32 : 8;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+#endif
+};
+
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
+#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31
+#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x00000004
+#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 0
+#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 31
+#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0
+#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7
+#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x000000ff
+
+#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8
+#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8
+#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100
+
+#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9
+#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9
+#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200
+
+#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10
+#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11
+#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00
+
+#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12
+#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12
+#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000
+
+#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13
+#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13
+#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000
+
+#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14
+#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14
+#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x00004000
+
+#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15
+#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15
+#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x00008000
+
+#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_RESERVED_2B_LSB 16
+#define REO_FLUSH_CACHE_RESERVED_2B_MSB 31
+#define REO_FLUSH_CACHE_RESERVED_2B_MASK 0xffff0000
+
+#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000c
+#define REO_FLUSH_CACHE_RESERVED_3A_LSB 0
+#define REO_FLUSH_CACHE_RESERVED_3A_MSB 31
+#define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x00000010
+#define REO_FLUSH_CACHE_RESERVED_4A_LSB 0
+#define REO_FLUSH_CACHE_RESERVED_4A_MSB 31
+#define REO_FLUSH_CACHE_RESERVED_4A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x00000014
+#define REO_FLUSH_CACHE_RESERVED_5A_LSB 0
+#define REO_FLUSH_CACHE_RESERVED_5A_MSB 31
+#define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x00000018
+#define REO_FLUSH_CACHE_RESERVED_6A_LSB 0
+#define REO_FLUSH_CACHE_RESERVED_6A_MSB 31
+#define REO_FLUSH_CACHE_RESERVED_6A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000001c
+#define REO_FLUSH_CACHE_RESERVED_7A_LSB 0
+#define REO_FLUSH_CACHE_RESERVED_7A_MSB 31
+#define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x00000020
+#define REO_FLUSH_CACHE_RESERVED_8A_LSB 0
+#define REO_FLUSH_CACHE_RESERVED_8A_MSB 31
+#define REO_FLUSH_CACHE_RESERVED_8A_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_flush_cache_status.h b/drivers/staging/fw-api/hw/peach/v1/reo_flush_cache_status.h
new file mode 100644
index 0000000000000000000000000000000000000000..6f2716362cd4f3d15a09dc67474ef8a19948c943
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_flush_cache_status.h
@@ -0,0 +1,302 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_FLUSH_CACHE_STATUS_H_
+#define _REO_FLUSH_CACHE_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 27
+
+struct reo_flush_cache_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv32_ring_padding : 32;
+ struct uniform_reo_status_header status_header;
+ uint32_t error_detected : 1,
+ block_error_details : 2,
+ reserved_2a : 5,
+ cache_controller_flush_status_hit : 1,
+ cache_controller_flush_status_desc_type : 3,
+ cache_controller_flush_status_client_id : 4,
+ cache_controller_flush_status_error : 2,
+ cache_controller_flush_count : 8,
+ flush_queue_1k_desc : 1,
+ reserved_2b : 5;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 32;
+ uint32_t reserved_25a : 28,
+ looping_count : 4;
+#else
+ uint32_t tlv32_ring_padding : 32;
+ struct uniform_reo_status_header status_header;
+ uint32_t reserved_2b : 5,
+ flush_queue_1k_desc : 1,
+ cache_controller_flush_count : 8,
+ cache_controller_flush_status_error : 2,
+ cache_controller_flush_status_client_id : 4,
+ cache_controller_flush_status_desc_type : 3,
+ cache_controller_flush_status_hit : 1,
+ reserved_2a : 5,
+ block_error_details : 2,
+ error_detected : 1;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 32;
+ uint32_t looping_count : 4,
+ reserved_25a : 28;
+#endif
+};
+
+#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_LSB 0
+#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_MSB 31
+#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31
+#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000c
+#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0
+#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0
+#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x00000001
+
+#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000c
+#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1
+#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2
+#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x00000006
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000c
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x000000f8
+
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000c
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100
+
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000c
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00
+
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000c
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000
+
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000c
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000
+
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000c
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25
+#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x03fc0000
+
+#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000c
+#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26
+#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26
+#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x04000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000c
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0xf8000000
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x00000010
+#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x00000014
+#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x00000018
+#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000001c
+#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x00000020
+#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x00000024
+#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x00000028
+#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000002c
+#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x00000030
+#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x00000034
+#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x00000038
+#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000003c
+#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x00000040
+#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x00000044
+#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x00000048
+#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000004c
+#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x00000050
+#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x00000054
+#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x00000058
+#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000005c
+#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x00000060
+#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x00000064
+#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31
+#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0xffffffff
+
+#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x00000068
+#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 27
+#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff
+
+#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x00000068
+#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 28
+#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 31
+#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_flush_queue.h b/drivers/staging/fw-api/hw/peach/v1/reo_flush_queue.h
new file mode 100644
index 0000000000000000000000000000000000000000..701a8546d33a7a42877f17a608986694d84a956a
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_flush_queue.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_FLUSH_QUEUE_H_
+#define _REO_FLUSH_QUEUE_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9
+
+struct reo_flush_queue {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t flush_desc_addr_31_0 : 32;
+ uint32_t flush_desc_addr_39_32 : 8,
+ block_desc_addr_usage_after_flush : 1,
+ block_resource_index : 2,
+ reserved_2a : 21;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+#else
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t flush_desc_addr_31_0 : 32;
+ uint32_t reserved_2a : 21,
+ block_resource_index : 2,
+ block_desc_addr_usage_after_flush : 1,
+ flush_desc_addr_39_32 : 8;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+#endif
+};
+
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
+#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31
+#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 0
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 31
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7
+#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff
+
+#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8
+#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8
+#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100
+
+#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9
+#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10
+#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x00000600
+
+#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11
+#define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31
+#define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0xfffff800
+
+#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000c
+#define REO_FLUSH_QUEUE_RESERVED_3A_LSB 0
+#define REO_FLUSH_QUEUE_RESERVED_3A_MSB 31
+#define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x00000010
+#define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0
+#define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31
+#define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x00000014
+#define REO_FLUSH_QUEUE_RESERVED_5A_LSB 0
+#define REO_FLUSH_QUEUE_RESERVED_5A_MSB 31
+#define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x00000018
+#define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0
+#define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31
+#define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000001c
+#define REO_FLUSH_QUEUE_RESERVED_7A_LSB 0
+#define REO_FLUSH_QUEUE_RESERVED_7A_MSB 31
+#define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x00000020
+#define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0
+#define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31
+#define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_flush_queue_status.h b/drivers/staging/fw-api/hw/peach/v1/reo_flush_queue_status.h
new file mode 100644
index 0000000000000000000000000000000000000000..51490730c0588d07249b651a89aaefbac8730696
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_flush_queue_status.h
@@ -0,0 +1,246 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_FLUSH_QUEUE_STATUS_H_
+#define _REO_FLUSH_QUEUE_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 27
+
+struct reo_flush_queue_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv32_ring_padding : 32;
+ struct uniform_reo_status_header status_header;
+ uint32_t error_detected : 1,
+ reserved_2a : 31;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 32;
+ uint32_t reserved_25a : 28,
+ looping_count : 4;
+#else
+ uint32_t tlv32_ring_padding : 32;
+ struct uniform_reo_status_header status_header;
+ uint32_t reserved_2a : 31,
+ error_detected : 1;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 32;
+ uint32_t looping_count : 4,
+ reserved_25a : 28;
+#endif
+};
+
+#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000c
+#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0
+#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x00000001
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000c
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0xfffffffe
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x00000010
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x00000014
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x00000018
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000001c
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x00000020
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x00000024
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x00000028
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000002c
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x00000030
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x00000034
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x00000038
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000003c
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x00000040
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x00000044
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x00000048
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000004c
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x00000050
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x00000054
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x00000058
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000005c
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x00000060
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x00000064
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0xffffffff
+
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x00000068
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 27
+#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff
+
+#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x00000068
+#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 28
+#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 31
+#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_flush_timeout_list.h b/drivers/staging/fw-api/hw/peach/v1/reo_flush_timeout_list.h
new file mode 100644
index 0000000000000000000000000000000000000000..02a307a3c18984c20eab208da1c4d01729b1047e
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_flush_timeout_list.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
+#define _REO_FLUSH_TIMEOUT_LIST_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9
+
+struct reo_flush_timeout_list {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t ac_timout_list : 2,
+ reserved_1 : 30;
+ uint32_t minimum_release_desc_count : 16,
+ minimum_forward_buf_count : 16;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+#else
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t reserved_1 : 30,
+ ac_timout_list : 2;
+ uint32_t minimum_forward_buf_count : 16,
+ minimum_release_desc_count : 16;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+#endif
+};
+
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB 15
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB 1
+#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK 0x00000003
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB 2
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK 0xfffffffc
+
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB 15
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK 0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB 16
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK 0xffff0000
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET 0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET 0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET 0x00000014
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET 0x00000018
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET 0x0000001c
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET 0x00000020
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_flush_timeout_list_status.h b/drivers/staging/fw-api/hw/peach/v1/reo_flush_timeout_list_status.h
new file mode 100644
index 0000000000000000000000000000000000000000..0bb7d402cd664e648e589a76fb59d734339c09e9
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_flush_timeout_list_status.h
@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 27
+
+struct reo_flush_timeout_list_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv32_ring_padding : 32;
+ struct uniform_reo_status_header status_header;
+ uint32_t error_detected : 1,
+ timout_list_empty : 1,
+ reserved_2a : 30;
+ uint32_t release_desc_count : 16,
+ forward_buf_count : 16;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 32;
+ uint32_t reserved_25a : 28,
+ looping_count : 4;
+#else
+ uint32_t tlv32_ring_padding : 32;
+ struct uniform_reo_status_header status_header;
+ uint32_t reserved_2a : 30,
+ timout_list_empty : 1,
+ error_detected : 1;
+ uint32_t forward_buf_count : 16,
+ release_desc_count : 16;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 32;
+ uint32_t looping_count : 4,
+ reserved_25a : 28;
+#endif
+};
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x00000001
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x00000002
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0xfffffffc
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 15
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 16
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff0000
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x00000014
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x00000018
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000001c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x00000020
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x00000024
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x00000028
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000002c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x00000030
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x00000034
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x00000038
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000003c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x00000040
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x00000044
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x00000048
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000004c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x00000050
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x00000054
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x00000058
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000005c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x00000060
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x00000064
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0xffffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x00000068
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 27
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff
+
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x00000068
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 31
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_get_queue_stats.h b/drivers/staging/fw-api/hw/peach/v1/reo_get_queue_stats.h
new file mode 100644
index 0000000000000000000000000000000000000000..6fff523c04a5fe85232f40f7fded017e1afaf9f0
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_get_queue_stats.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_GET_QUEUE_STATS_H_
+#define _REO_GET_QUEUE_STATS_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9
+
+struct reo_get_queue_stats {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32;
+ uint32_t rx_reo_queue_desc_addr_39_32 : 8,
+ clear_stats : 1,
+ reserved_2a : 23;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+#else
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32;
+ uint32_t reserved_2a : 23,
+ clear_stats : 1,
+ rx_reo_queue_desc_addr_39_32 : 8;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+#endif
+};
+
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB 15
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
+#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB 31
+#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
+#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+#define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB 8
+#define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB 8
+#define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK 0x00000100
+
+#define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_RESERVED_2A_LSB 9
+#define REO_GET_QUEUE_STATS_RESERVED_2A_MSB 31
+#define REO_GET_QUEUE_STATS_RESERVED_2A_MASK 0xfffffe00
+
+#define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET 0x0000000c
+#define REO_GET_QUEUE_STATS_RESERVED_3A_LSB 0
+#define REO_GET_QUEUE_STATS_RESERVED_3A_MSB 31
+#define REO_GET_QUEUE_STATS_RESERVED_3A_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET 0x00000010
+#define REO_GET_QUEUE_STATS_RESERVED_4A_LSB 0
+#define REO_GET_QUEUE_STATS_RESERVED_4A_MSB 31
+#define REO_GET_QUEUE_STATS_RESERVED_4A_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET 0x00000014
+#define REO_GET_QUEUE_STATS_RESERVED_5A_LSB 0
+#define REO_GET_QUEUE_STATS_RESERVED_5A_MSB 31
+#define REO_GET_QUEUE_STATS_RESERVED_5A_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET 0x00000018
+#define REO_GET_QUEUE_STATS_RESERVED_6A_LSB 0
+#define REO_GET_QUEUE_STATS_RESERVED_6A_MSB 31
+#define REO_GET_QUEUE_STATS_RESERVED_6A_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET 0x0000001c
+#define REO_GET_QUEUE_STATS_RESERVED_7A_LSB 0
+#define REO_GET_QUEUE_STATS_RESERVED_7A_MSB 31
+#define REO_GET_QUEUE_STATS_RESERVED_7A_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET 0x00000020
+#define REO_GET_QUEUE_STATS_RESERVED_8A_LSB 0
+#define REO_GET_QUEUE_STATS_RESERVED_8A_MSB 31
+#define REO_GET_QUEUE_STATS_RESERVED_8A_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_get_queue_stats_status.h b/drivers/staging/fw-api/hw/peach/v1/reo_get_queue_stats_status.h
new file mode 100644
index 0000000000000000000000000000000000000000..b80815d0d748fbbe002702d00870f5189f912c1a
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_get_queue_stats_status.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_GET_QUEUE_STATS_STATUS_H_
+#define _REO_GET_QUEUE_STATS_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 27
+
+struct reo_get_queue_stats_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv32_ring_padding : 32;
+ struct uniform_reo_status_header status_header;
+ uint32_t ssn : 12,
+ current_index : 10,
+ reserved_2 : 10;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_63_32 : 32;
+ uint32_t pn_95_64 : 32;
+ uint32_t pn_127_96 : 32;
+ uint32_t last_rx_enqueue_timestamp : 32;
+ uint32_t last_rx_dequeue_timestamp : 32;
+ uint32_t rx_bitmap_31_0 : 32;
+ uint32_t rx_bitmap_63_32 : 32;
+ uint32_t rx_bitmap_95_64 : 32;
+ uint32_t rx_bitmap_127_96 : 32;
+ uint32_t rx_bitmap_159_128 : 32;
+ uint32_t rx_bitmap_191_160 : 32;
+ uint32_t rx_bitmap_223_192 : 32;
+ uint32_t rx_bitmap_255_224 : 32;
+ uint32_t rx_bitmap_287_256 : 32;
+ uint32_t current_mpdu_count : 7,
+ current_msdu_count : 25;
+ uint32_t window_jump_2k : 4,
+ timeout_count : 6,
+ forward_due_to_bar_count : 6,
+ duplicate_count : 16;
+ uint32_t frames_in_order_count : 24,
+ bar_received_count : 8;
+ uint32_t mpdu_frames_processed_count : 32;
+ uint32_t msdu_frames_processed_count : 32;
+ uint32_t total_processed_byte_count : 32;
+ uint32_t late_receive_mpdu_count : 12,
+ hole_count : 16,
+ get_queue_1k_stats_status_to_follow : 1,
+ reserved_24a : 3;
+ uint32_t aging_drop_mpdu_count : 16,
+ aging_drop_interval : 8,
+ reserved_25a : 4,
+ looping_count : 4;
+#else
+ uint32_t tlv32_ring_padding : 32;
+ struct uniform_reo_status_header status_header;
+ uint32_t reserved_2 : 10,
+ current_index : 10,
+ ssn : 12;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_63_32 : 32;
+ uint32_t pn_95_64 : 32;
+ uint32_t pn_127_96 : 32;
+ uint32_t last_rx_enqueue_timestamp : 32;
+ uint32_t last_rx_dequeue_timestamp : 32;
+ uint32_t rx_bitmap_31_0 : 32;
+ uint32_t rx_bitmap_63_32 : 32;
+ uint32_t rx_bitmap_95_64 : 32;
+ uint32_t rx_bitmap_127_96 : 32;
+ uint32_t rx_bitmap_159_128 : 32;
+ uint32_t rx_bitmap_191_160 : 32;
+ uint32_t rx_bitmap_223_192 : 32;
+ uint32_t rx_bitmap_255_224 : 32;
+ uint32_t rx_bitmap_287_256 : 32;
+ uint32_t current_msdu_count : 25,
+ current_mpdu_count : 7;
+ uint32_t duplicate_count : 16,
+ forward_due_to_bar_count : 6,
+ timeout_count : 6,
+ window_jump_2k : 4;
+ uint32_t bar_received_count : 8,
+ frames_in_order_count : 24;
+ uint32_t mpdu_frames_processed_count : 32;
+ uint32_t msdu_frames_processed_count : 32;
+ uint32_t total_processed_byte_count : 32;
+ uint32_t reserved_24a : 3,
+ get_queue_1k_stats_status_to_follow : 1,
+ hole_count : 16,
+ late_receive_mpdu_count : 12;
+ uint32_t looping_count : 4,
+ reserved_25a : 4,
+ aging_drop_interval : 8,
+ aging_drop_mpdu_count : 16;
+#endif
+};
+
+#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_SSN_OFFSET 0x0000000c
+#define REO_GET_QUEUE_STATS_STATUS_SSN_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_SSN_MSB 11
+#define REO_GET_QUEUE_STATS_STATUS_SSN_MASK 0x00000fff
+
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_OFFSET 0x0000000c
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_LSB 12
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MSB 21
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MASK 0x003ff000
+
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_OFFSET 0x0000000c
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_LSB 22
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MASK 0xffc00000
+
+#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_OFFSET 0x00000010
+#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_OFFSET 0x00000014
+#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_OFFSET 0x00000018
+#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_OFFSET 0x0000001c
+#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_OFFSET 0x00000028
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_OFFSET 0x0000002c
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_OFFSET 0x00000030
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_OFFSET 0x00000034
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_OFFSET 0x00000038
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_OFFSET 0x0000003c
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_OFFSET 0x00000040
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_OFFSET 0x00000044
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_OFFSET 0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_OFFSET 0x0000004c
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MSB 6
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MASK 0x0000007f
+
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_OFFSET 0x0000004c
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_LSB 7
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MASK 0xffffff80
+
+#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_OFFSET 0x00000050
+#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MSB 3
+#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MASK 0x0000000f
+
+#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_OFFSET 0x00000050
+#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_LSB 4
+#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MSB 9
+#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MASK 0x000003f0
+
+#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000050
+#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_LSB 10
+#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MSB 15
+#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00
+
+#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_OFFSET 0x00000050
+#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_LSB 16
+#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MASK 0xffff0000
+
+#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000054
+#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MSB 23
+#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_OFFSET 0x00000054
+#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_LSB 24
+#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MASK 0xff000000
+
+#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000058
+#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000005c
+#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000060
+#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff
+
+#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000064
+#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MSB 11
+#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff
+
+#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_OFFSET 0x00000064
+#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_LSB 12
+#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MSB 27
+#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MASK 0x0ffff000
+
+#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_OFFSET 0x00000064
+#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_LSB 28
+#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MSB 28
+#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MASK 0x10000000
+
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_OFFSET 0x00000064
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_LSB 29
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MASK 0xe0000000
+
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_OFFSET 0x00000068
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MSB 15
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff
+
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_OFFSET 0x00000068
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_LSB 16
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MSB 23
+#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MASK 0x00ff0000
+
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_OFFSET 0x00000068
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_LSB 24
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MSB 27
+#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MASK 0x0f000000
+
+#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_OFFSET 0x00000068
+#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_LSB 28
+#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MSB 31
+#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_unblock_cache.h b/drivers/staging/fw-api/hw/peach/v1/reo_unblock_cache.h
new file mode 100644
index 0000000000000000000000000000000000000000..b3dd68876515db4112c36510399aeb0d4caa7054
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_unblock_cache.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_UNBLOCK_CACHE_H_
+#define _REO_UNBLOCK_CACHE_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9
+
+struct reo_unblock_cache {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t unblock_type : 1,
+ cache_block_resource_index : 2,
+ reserved_1a : 29;
+ uint32_t reserved_2a : 32;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+#else
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t reserved_1a : 29,
+ cache_block_resource_index : 2,
+ unblock_type : 1;
+ uint32_t reserved_2a : 32;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+#endif
+};
+
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
+#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB 31
+#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB 0
+#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB 0
+#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK 0x00000001
+
+#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 1
+#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 2
+#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000006
+
+#define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_RESERVED_1A_LSB 3
+#define REO_UNBLOCK_CACHE_RESERVED_1A_MSB 31
+#define REO_UNBLOCK_CACHE_RESERVED_1A_MASK 0xfffffff8
+
+#define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET 0x00000008
+#define REO_UNBLOCK_CACHE_RESERVED_2A_LSB 0
+#define REO_UNBLOCK_CACHE_RESERVED_2A_MSB 31
+#define REO_UNBLOCK_CACHE_RESERVED_2A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET 0x0000000c
+#define REO_UNBLOCK_CACHE_RESERVED_3A_LSB 0
+#define REO_UNBLOCK_CACHE_RESERVED_3A_MSB 31
+#define REO_UNBLOCK_CACHE_RESERVED_3A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET 0x00000010
+#define REO_UNBLOCK_CACHE_RESERVED_4A_LSB 0
+#define REO_UNBLOCK_CACHE_RESERVED_4A_MSB 31
+#define REO_UNBLOCK_CACHE_RESERVED_4A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET 0x00000014
+#define REO_UNBLOCK_CACHE_RESERVED_5A_LSB 0
+#define REO_UNBLOCK_CACHE_RESERVED_5A_MSB 31
+#define REO_UNBLOCK_CACHE_RESERVED_5A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET 0x00000018
+#define REO_UNBLOCK_CACHE_RESERVED_6A_LSB 0
+#define REO_UNBLOCK_CACHE_RESERVED_6A_MSB 31
+#define REO_UNBLOCK_CACHE_RESERVED_6A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET 0x0000001c
+#define REO_UNBLOCK_CACHE_RESERVED_7A_LSB 0
+#define REO_UNBLOCK_CACHE_RESERVED_7A_MSB 31
+#define REO_UNBLOCK_CACHE_RESERVED_7A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET 0x00000020
+#define REO_UNBLOCK_CACHE_RESERVED_8A_LSB 0
+#define REO_UNBLOCK_CACHE_RESERVED_8A_MSB 31
+#define REO_UNBLOCK_CACHE_RESERVED_8A_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_unblock_cache_status.h b/drivers/staging/fw-api/hw/peach/v1/reo_unblock_cache_status.h
new file mode 100644
index 0000000000000000000000000000000000000000..fe0de6cbb2825689672115fe6307fa5fd0476430
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_unblock_cache_status.h
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_UNBLOCK_CACHE_STATUS_H_
+#define _REO_UNBLOCK_CACHE_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 27
+
+struct reo_unblock_cache_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv32_ring_padding : 32;
+ struct uniform_reo_status_header status_header;
+ uint32_t error_detected : 1,
+ unblock_type : 1,
+ reserved_2a : 30;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 32;
+ uint32_t reserved_25a : 28,
+ looping_count : 4;
+#else
+ uint32_t tlv32_ring_padding : 32;
+ struct uniform_reo_status_header status_header;
+ uint32_t reserved_2a : 30,
+ unblock_type : 1,
+ error_detected : 1;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 32;
+ uint32_t looping_count : 4,
+ reserved_25a : 28;
+#endif
+};
+
+#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000c
+#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB 0
+#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK 0x00000001
+
+#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET 0x0000000c
+#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB 1
+#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB 1
+#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK 0x00000002
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000c
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB 2
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK 0xfffffffc
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET 0x00000010
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET 0x00000014
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET 0x00000018
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000001c
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET 0x00000020
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET 0x00000024
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET 0x00000028
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000002c
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET 0x00000030
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET 0x00000034
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET 0x00000038
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000003c
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET 0x00000040
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET 0x00000044
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET 0x00000048
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000004c
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET 0x00000050
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET 0x00000054
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET 0x00000058
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000005c
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET 0x00000060
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET 0x00000064
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK 0xffffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET 0x00000068
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB 27
+#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff
+
+#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x00000068
+#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB 28
+#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB 31
+#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_update_rx_reo_queue.h b/drivers/staging/fw-api/hw/peach/v1/reo_update_rx_reo_queue.h
new file mode 100644
index 0000000000000000000000000000000000000000..3aefb3f39a92e7ccc2f95c69c4d78ff140846be6
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_update_rx_reo_queue.h
@@ -0,0 +1,425 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_H_
+#define _REO_UPDATE_RX_REO_QUEUE_H_
+
+#include "uniform_reo_cmd_header.h"
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9
+
+struct reo_update_rx_reo_queue {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32;
+ uint32_t rx_reo_queue_desc_addr_39_32 : 8,
+ update_receive_queue_number : 1,
+ update_vld : 1,
+ update_associated_link_descriptor_counter : 1,
+ update_disable_duplicate_detection : 1,
+ update_soft_reorder_enable : 1,
+ update_ac : 1,
+ update_bar : 1,
+ update_rty : 1,
+ update_chk_2k_mode : 1,
+ update_oor_mode : 1,
+ update_ba_window_size : 1,
+ update_pn_check_needed : 1,
+ update_pn_shall_be_even : 1,
+ update_pn_shall_be_uneven : 1,
+ update_pn_handling_enable : 1,
+ update_pn_size : 1,
+ update_ignore_ampdu_flag : 1,
+ update_svld : 1,
+ update_ssn : 1,
+ update_seq_2k_error_detected_flag : 1,
+ update_pn_error_detected_flag : 1,
+ update_pn_valid : 1,
+ update_pn : 1,
+ clear_stat_counters : 1;
+ uint32_t receive_queue_number : 16,
+ vld : 1,
+ associated_link_descriptor_counter : 2,
+ disable_duplicate_detection : 1,
+ soft_reorder_enable : 1,
+ ac : 2,
+ bar : 1,
+ rty : 1,
+ chk_2k_mode : 1,
+ oor_mode : 1,
+ pn_check_needed : 1,
+ pn_shall_be_even : 1,
+ pn_shall_be_uneven : 1,
+ pn_handling_enable : 1,
+ ignore_ampdu_flag : 1;
+ uint32_t ba_window_size : 10,
+ pn_size : 2,
+ svld : 1,
+ ssn : 12,
+ seq_2k_error_detected_flag : 1,
+ pn_error_detected_flag : 1,
+ pn_valid : 1,
+ flush_from_cache : 1,
+ reserved_4a : 3;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_63_32 : 32;
+ uint32_t pn_95_64 : 32;
+ uint32_t pn_127_96 : 32;
+#else
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32;
+ uint32_t clear_stat_counters : 1,
+ update_pn : 1,
+ update_pn_valid : 1,
+ update_pn_error_detected_flag : 1,
+ update_seq_2k_error_detected_flag : 1,
+ update_ssn : 1,
+ update_svld : 1,
+ update_ignore_ampdu_flag : 1,
+ update_pn_size : 1,
+ update_pn_handling_enable : 1,
+ update_pn_shall_be_uneven : 1,
+ update_pn_shall_be_even : 1,
+ update_pn_check_needed : 1,
+ update_ba_window_size : 1,
+ update_oor_mode : 1,
+ update_chk_2k_mode : 1,
+ update_rty : 1,
+ update_bar : 1,
+ update_ac : 1,
+ update_soft_reorder_enable : 1,
+ update_disable_duplicate_detection : 1,
+ update_associated_link_descriptor_counter : 1,
+ update_vld : 1,
+ update_receive_queue_number : 1,
+ rx_reo_queue_desc_addr_39_32 : 8;
+ uint32_t ignore_ampdu_flag : 1,
+ pn_handling_enable : 1,
+ pn_shall_be_uneven : 1,
+ pn_shall_be_even : 1,
+ pn_check_needed : 1,
+ oor_mode : 1,
+ chk_2k_mode : 1,
+ rty : 1,
+ bar : 1,
+ ac : 2,
+ soft_reorder_enable : 1,
+ disable_duplicate_detection : 1,
+ associated_link_descriptor_counter : 2,
+ vld : 1,
+ receive_queue_number : 16;
+ uint32_t reserved_4a : 3,
+ flush_from_cache : 1,
+ pn_valid : 1,
+ pn_error_detected_flag : 1,
+ seq_2k_error_detected_flag : 1,
+ ssn : 12,
+ svld : 1,
+ pn_size : 2,
+ ba_window_size : 10;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_63_32 : 32;
+ uint32_t pn_95_64 : 32;
+ uint32_t pn_127_96 : 32;
+#endif
+};
+
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
+#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x00000100
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x00000200
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000400
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000800
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x00001000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x00002000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x00004000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x00008000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x00010000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x00020000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x00040000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x00080000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x00100000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x00200000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x00400000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x00800000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x01000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x02000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x04000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x08000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x10000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x20000000
+
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30
+#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x40000000
+
+#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31
+#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x80000000
+
+#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15
+#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff
+
+#define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 16
+#define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 16
+#define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x00010000
+
+#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 17
+#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 18
+#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00060000
+
+#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 19
+#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 19
+#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00080000
+
+#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 20
+#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 20
+#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00100000
+
+#define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_AC_LSB 21
+#define REO_UPDATE_RX_REO_QUEUE_AC_MSB 22
+#define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x00600000
+
+#define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 23
+#define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 23
+#define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x00800000
+
+#define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 24
+#define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 24
+#define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x01000000
+
+#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 25
+#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 25
+#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x02000000
+
+#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 26
+#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 26
+#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x04000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 27
+#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 27
+#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x08000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 28
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x10000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 29
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 29
+#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x20000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 30
+#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 30
+#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x40000000
+
+#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 31
+#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x80000000
+
+#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9
+#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x000003ff
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10
+#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11
+#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x00000c00
+
+#define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12
+#define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12
+#define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x00001000
+
+#define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13
+#define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24
+#define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x01ffe000
+
+#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25
+#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25
+#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x02000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26
+#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26
+#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x04000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27
+#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27
+#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x08000000
+
+#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28
+#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x10000000
+
+#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29
+#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0xe0000000
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x00000014
+#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x00000018
+#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000001c
+#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x00000020
+#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/reo_update_rx_reo_queue_status.h b/drivers/staging/fw-api/hw/peach/v1/reo_update_rx_reo_queue_status.h
new file mode 100644
index 0000000000000000000000000000000000000000..9ec7efc6ad3a60be42880f45ff92d79535e5bc62
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/reo_update_rx_reo_queue_status.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+
+#include "uniform_reo_status_header.h"
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 27
+
+struct reo_update_rx_reo_queue_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv32_ring_padding : 32;
+ struct uniform_reo_status_header status_header;
+ uint32_t reserved_2a : 32;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 32;
+ uint32_t reserved_25a : 28,
+ looping_count : 4;
+#else
+ uint32_t tlv32_ring_padding : 32;
+ struct uniform_reo_status_header status_header;
+ uint32_t reserved_2a : 32;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 32;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+ uint32_t reserved_10a : 32;
+ uint32_t reserved_11a : 32;
+ uint32_t reserved_12a : 32;
+ uint32_t reserved_13a : 32;
+ uint32_t reserved_14a : 32;
+ uint32_t reserved_15a : 32;
+ uint32_t reserved_16a : 32;
+ uint32_t reserved_17a : 32;
+ uint32_t reserved_18a : 32;
+ uint32_t reserved_19a : 32;
+ uint32_t reserved_20a : 32;
+ uint32_t reserved_21a : 32;
+ uint32_t reserved_22a : 32;
+ uint32_t reserved_23a : 32;
+ uint32_t reserved_24a : 32;
+ uint32_t looping_count : 4,
+ reserved_25a : 28;
+#endif
+};
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET 0x00000014
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET 0x00000018
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000001c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET 0x00000020
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET 0x00000024
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET 0x00000028
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000002c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET 0x00000030
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET 0x00000034
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET 0x00000038
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000003c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET 0x00000040
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET 0x00000044
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET 0x00000048
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000004c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET 0x00000050
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET 0x00000054
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET 0x00000058
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000005c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET 0x00000060
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET 0x00000064
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK 0xffffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET 0x00000068
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB 27
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff
+
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x00000068
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB 31
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/response_end_status.h b/drivers/staging/fw-api/hw/peach/v1/response_end_status.h
new file mode 100644
index 0000000000000000000000000000000000000000..600d007ce5727881a1f74b78cea7ca7c12af39db
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/response_end_status.h
@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RESPONSE_END_STATUS_H_
+#define _RESPONSE_END_STATUS_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_RESPONSE_END_STATUS 10
+
+struct response_end_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t coex_bt_tx_while_wlan_tx : 1,
+ coex_wan_tx_while_wlan_tx : 1,
+ coex_wlan_tx_while_wlan_tx : 1,
+ global_data_underflow_warning : 1,
+ response_transmit_status : 4,
+ phytx_pkt_end_info_valid : 1,
+ phytx_abort_request_info_valid : 1,
+ generated_response : 3,
+ mba_user_count : 7,
+ mba_fake_bitmap_count : 7,
+ coex_based_tx_bw : 3,
+ trig_response_related : 1,
+ reserved_0a : 1;
+ struct phytx_abort_request_info phytx_abort_request_info_details;
+ uint16_t cbf_segment_request_mask : 8,
+ cbf_segment_sent_mask : 8;
+ uint32_t underflow_mpdu_count : 9,
+ data_underflow_warning : 2,
+ reserved_2b : 10,
+ only_null_delim_sent : 1,
+ brp_info_valid : 1,
+ coex_uwb_tx_while_wlan_tx : 1,
+ coex_lte_tx_while_wlan_tx : 1,
+ reserved_2a : 7;
+ uint32_t mu_response_bitmap_31_0 : 32;
+ uint32_t mu_response_bitmap_36_32 : 5,
+ reserved_4a : 27;
+ uint32_t addr1_31_0 : 32;
+ uint32_t addr1_47_32 : 16,
+ addr2_15_0 : 16;
+ uint32_t addr2_47_16 : 32;
+ uint32_t addr3_31_0 : 32;
+ uint32_t addr3_47_32 : 16,
+ __reserved_g_0005 : 1,
+ secure : 1,
+ __reserved_g_0005_ftm_frame_sent : 1,
+ reserved_20a : 13;
+#else
+ uint32_t reserved_0a : 1,
+ trig_response_related : 1,
+ coex_based_tx_bw : 3,
+ mba_fake_bitmap_count : 7,
+ mba_user_count : 7,
+ generated_response : 3,
+ phytx_abort_request_info_valid : 1,
+ phytx_pkt_end_info_valid : 1,
+ response_transmit_status : 4,
+ global_data_underflow_warning : 1,
+ coex_wlan_tx_while_wlan_tx : 1,
+ coex_wan_tx_while_wlan_tx : 1,
+ coex_bt_tx_while_wlan_tx : 1;
+ uint32_t cbf_segment_sent_mask : 8,
+ cbf_segment_request_mask : 8;
+ struct phytx_abort_request_info phytx_abort_request_info_details;
+ uint32_t reserved_2a : 7,
+ coex_lte_tx_while_wlan_tx : 1,
+ coex_uwb_tx_while_wlan_tx : 1,
+ brp_info_valid : 1,
+ only_null_delim_sent : 1,
+ reserved_2b : 10,
+ data_underflow_warning : 2,
+ underflow_mpdu_count : 9;
+ uint32_t mu_response_bitmap_31_0 : 32;
+ uint32_t reserved_4a : 27,
+ mu_response_bitmap_36_32 : 5;
+ uint32_t addr1_31_0 : 32;
+ uint32_t addr2_15_0 : 16,
+ addr1_47_32 : 16;
+ uint32_t addr2_47_16 : 32;
+ uint32_t addr3_31_0 : 32;
+ uint32_t reserved_20a : 13,
+ __reserved_g_0005_ftm_frame_sent : 1,
+ secure : 1,
+ __reserved_g_0005 : 1,
+ addr3_47_32 : 16;
+#endif
+};
+
+#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x00000000
+#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0
+#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0
+#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x00000001
+
+#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000
+#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1
+#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1
+#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x00000002
+
+#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000
+#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2
+#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2
+#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x00000004
+
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x00000000
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3
+#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x00000008
+
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x00000000
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7
+#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x000000f0
+
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x00000000
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8
+#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x00000100
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000000
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x00000200
+
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x00000000
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12
+#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x00001c00
+
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x00000000
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19
+#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x000fe000
+
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x00000000
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26
+#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x07f00000
+
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x00000000
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29
+#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x38000000
+
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x00000000
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30
+#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x40000000
+
+#define RESPONSE_END_STATUS_RESERVED_0A_OFFSET 0x00000000
+#define RESPONSE_END_STATUS_RESERVED_0A_LSB 31
+#define RESPONSE_END_STATUS_RESERVED_0A_MSB 31
+#define RESPONSE_END_STATUS_RESERVED_0A_MASK 0x80000000
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000004
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00
+
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000004
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15
+#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000
+
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x00000004
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 16
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 23
+#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff0000
+
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x00000004
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 24
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 31
+#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff000000
+
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x00000008
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8
+#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x000001ff
+
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x00000008
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10
+#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x00000600
+
+#define RESPONSE_END_STATUS_RESERVED_2B_OFFSET 0x00000008
+#define RESPONSE_END_STATUS_RESERVED_2B_LSB 11
+#define RESPONSE_END_STATUS_RESERVED_2B_MSB 20
+#define RESPONSE_END_STATUS_RESERVED_2B_MASK 0x001ff800
+
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x00000008
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21
+#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x00200000
+
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x00000008
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22
+#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x00400000
+
+#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET 0x00000008
+#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_LSB 23
+#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_MSB 23
+#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_MASK 0x00800000
+
+#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET 0x00000008
+#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_LSB 24
+#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_MSB 24
+#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_MASK 0x01000000
+
+#define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x00000008
+#define RESPONSE_END_STATUS_RESERVED_2A_LSB 25
+#define RESPONSE_END_STATUS_RESERVED_2A_MSB 31
+#define RESPONSE_END_STATUS_RESERVED_2A_MASK 0xfe000000
+
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000c
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 0
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 31
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff
+
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x00000010
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4
+#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x0000001f
+
+#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x00000010
+#define RESPONSE_END_STATUS_RESERVED_4A_LSB 5
+#define RESPONSE_END_STATUS_RESERVED_4A_MSB 31
+#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0xffffffe0
+
+#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x00000014
+#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0
+#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31
+#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0xffffffff
+
+#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x00000018
+#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 0
+#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 15
+#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff
+
+#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x00000018
+#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 16
+#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 31
+#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff0000
+
+#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000001c
+#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0
+#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31
+#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0xffffffff
+
+#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x00000020
+#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 0
+#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 31
+#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff
+
+#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x00000024
+#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0
+#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15
+#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x0000ffff
+
+#define RESPONSE_END_STATUS_SECURE_OFFSET 0x00000024
+#define RESPONSE_END_STATUS_SECURE_LSB 17
+#define RESPONSE_END_STATUS_SECURE_MSB 17
+#define RESPONSE_END_STATUS_SECURE_MASK 0x00020000
+
+#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x00000024
+#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18
+#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18
+#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x00040000
+
+#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x00000024
+#define RESPONSE_END_STATUS_RESERVED_20A_LSB 19
+#define RESPONSE_END_STATUS_RESERVED_20A_MSB 31
+#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0xfff80000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/response_start_status.h b/drivers/staging/fw-api/hw/peach/v1/response_start_status.h
new file mode 100644
index 0000000000000000000000000000000000000000..2b54ed1da7abf42d1bc27719f2b6b0c1b0edde61
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/response_start_status.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RESPONSE_START_STATUS_H_
+#define _RESPONSE_START_STATUS_H_
+
+#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2
+
+struct response_start_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t generated_response : 3,
+ __reserved_g_0012 : 2,
+ trig_response_related : 1,
+ response_sta_count : 7,
+ reserved : 19;
+ uint32_t phy_ppdu_id : 16,
+ sw_peer_id : 16;
+#else
+ uint32_t reserved : 19,
+ response_sta_count : 7,
+ trig_response_related : 1,
+ __reserved_g_0012 : 2,
+ generated_response : 3;
+ uint32_t sw_peer_id : 16,
+ phy_ppdu_id : 16;
+#endif
+};
+
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x00000000
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2
+#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x00000007
+
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x00000000
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5
+#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x00000020
+
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x00000000
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12
+#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x00001fc0
+
+#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x00000000
+#define RESPONSE_START_STATUS_RESERVED_LSB 13
+#define RESPONSE_START_STATUS_RESERVED_MSB 31
+#define RESPONSE_START_STATUS_RESERVED_MASK 0xffffe000
+
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x00000004
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 0
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 15
+#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x00000004
+#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 16
+#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 31
+#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/ru_allocation_160_info.h b/drivers/staging/fw-api/hw/peach/v1/ru_allocation_160_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..3693e4ba64422f0ccecbea53204898979c1c0bf9
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/ru_allocation_160_info.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RU_ALLOCATION_160_INFO_H_
+#define _RU_ALLOCATION_160_INFO_H_
+
+#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4
+
+struct ru_allocation_160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t ru_allocation_band0_0 : 9,
+ ru_allocation_band0_1 : 9,
+ reserved_0a : 6,
+ ru_allocations_01_subband80_mask : 4,
+ ru_allocations_23_subband80_mask : 4;
+ uint32_t ru_allocation_band0_2 : 9,
+ ru_allocation_band0_3 : 9,
+ reserved_1a : 14;
+ uint32_t ru_allocation_band1_0 : 9,
+ ru_allocation_band1_1 : 9,
+ reserved_2a : 14;
+ uint32_t ru_allocation_band1_2 : 9,
+ ru_allocation_band1_3 : 9,
+ reserved_3a : 14;
+#else
+ uint32_t ru_allocations_23_subband80_mask : 4,
+ ru_allocations_01_subband80_mask : 4,
+ reserved_0a : 6,
+ ru_allocation_band0_1 : 9,
+ ru_allocation_band0_0 : 9;
+ uint32_t reserved_1a : 14,
+ ru_allocation_band0_3 : 9,
+ ru_allocation_band0_2 : 9;
+ uint32_t reserved_2a : 14,
+ ru_allocation_band1_1 : 9,
+ ru_allocation_band1_0 : 9;
+ uint32_t reserved_3a : 14,
+ ru_allocation_band1_3 : 9,
+ ru_allocation_band1_2 : 9;
+#endif
+};
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23
+#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31
+#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31
+#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff
+
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17
+#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00
+
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31
+#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_attention.h b/drivers/staging/fw-api/hw/peach/v1/rx_attention.h
new file mode 100644
index 0000000000000000000000000000000000000000..cafa2abe8ea7a5ee785116a4e722fb86003469cf
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_attention.h
@@ -0,0 +1,379 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_ATTENTION_H_
+#define _RX_ATTENTION_H_
+
+#define NUM_OF_DWORDS_RX_ATTENTION 3
+
+struct rx_attention {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t rxpcu_mpdu_filter_in_category : 2,
+ sw_frame_group_id : 7,
+ reserved_0 : 7,
+ phy_ppdu_id : 16;
+ uint32_t first_mpdu : 1,
+ reserved_1a : 1,
+ mcast_bcast : 1,
+ ast_index_not_found : 1,
+ ast_index_timeout : 1,
+ power_mgmt : 1,
+ non_qos : 1,
+ null_data : 1,
+ mgmt_type : 1,
+ ctrl_type : 1,
+ more_data : 1,
+ eosp : 1,
+ a_msdu_error : 1,
+ fragment_flag : 1,
+ order : 1,
+ cce_match : 1,
+ overflow_err : 1,
+ msdu_length_err : 1,
+ tcp_udp_chksum_fail : 1,
+ ip_chksum_fail : 1,
+ sa_idx_invalid : 1,
+ da_idx_invalid : 1,
+ reserved_1b : 1,
+ rx_in_tx_decrypt_byp : 1,
+ encrypt_required : 1,
+ directed : 1,
+ buffer_fragment : 1,
+ mpdu_length_err : 1,
+ tkip_mic_err : 1,
+ decrypt_err : 1,
+ unencrypted_frame_err : 1,
+ fcs_err : 1;
+ uint32_t flow_idx_timeout : 1,
+ flow_idx_invalid : 1,
+ wifi_parser_error : 1,
+ amsdu_parser_error : 1,
+ sa_idx_timeout : 1,
+ da_idx_timeout : 1,
+ msdu_limit_error : 1,
+ da_is_valid : 1,
+ da_is_mcbc : 1,
+ sa_is_valid : 1,
+ decrypt_status_code : 3,
+ rx_bitmap_not_updated : 1,
+ reserved_2 : 17,
+ msdu_done : 1;
+#else
+ uint32_t phy_ppdu_id : 16,
+ reserved_0 : 7,
+ sw_frame_group_id : 7,
+ rxpcu_mpdu_filter_in_category : 2;
+ uint32_t fcs_err : 1,
+ unencrypted_frame_err : 1,
+ decrypt_err : 1,
+ tkip_mic_err : 1,
+ mpdu_length_err : 1,
+ buffer_fragment : 1,
+ directed : 1,
+ encrypt_required : 1,
+ rx_in_tx_decrypt_byp : 1,
+ reserved_1b : 1,
+ da_idx_invalid : 1,
+ sa_idx_invalid : 1,
+ ip_chksum_fail : 1,
+ tcp_udp_chksum_fail : 1,
+ msdu_length_err : 1,
+ overflow_err : 1,
+ cce_match : 1,
+ order : 1,
+ fragment_flag : 1,
+ a_msdu_error : 1,
+ eosp : 1,
+ more_data : 1,
+ ctrl_type : 1,
+ mgmt_type : 1,
+ null_data : 1,
+ non_qos : 1,
+ power_mgmt : 1,
+ ast_index_timeout : 1,
+ ast_index_not_found : 1,
+ mcast_bcast : 1,
+ reserved_1a : 1,
+ first_mpdu : 1;
+ uint32_t msdu_done : 1,
+ reserved_2 : 17,
+ rx_bitmap_not_updated : 1,
+ decrypt_status_code : 3,
+ sa_is_valid : 1,
+ da_is_mcbc : 1,
+ da_is_valid : 1,
+ msdu_limit_error : 1,
+ da_idx_timeout : 1,
+ sa_idx_timeout : 1,
+ amsdu_parser_error : 1,
+ wifi_parser_error : 1,
+ flow_idx_invalid : 1,
+ flow_idx_timeout : 1;
+#endif
+};
+
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
+#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x00000000
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8
+#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+#define RX_ATTENTION_RESERVED_0_OFFSET 0x00000000
+#define RX_ATTENTION_RESERVED_0_LSB 9
+#define RX_ATTENTION_RESERVED_0_MSB 15
+#define RX_ATTENTION_RESERVED_0_MASK 0x0000fe00
+
+#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_ATTENTION_PHY_PPDU_ID_LSB 16
+#define RX_ATTENTION_PHY_PPDU_ID_MSB 31
+#define RX_ATTENTION_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x00000004
+#define RX_ATTENTION_FIRST_MPDU_LSB 0
+#define RX_ATTENTION_FIRST_MPDU_MSB 0
+#define RX_ATTENTION_FIRST_MPDU_MASK 0x00000001
+
+#define RX_ATTENTION_RESERVED_1A_OFFSET 0x00000004
+#define RX_ATTENTION_RESERVED_1A_LSB 1
+#define RX_ATTENTION_RESERVED_1A_MSB 1
+#define RX_ATTENTION_RESERVED_1A_MASK 0x00000002
+
+#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x00000004
+#define RX_ATTENTION_MCAST_BCAST_LSB 2
+#define RX_ATTENTION_MCAST_BCAST_MSB 2
+#define RX_ATTENTION_MCAST_BCAST_MASK 0x00000004
+
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x00000004
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 3
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 3
+#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x00000008
+
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x00000004
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 4
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 4
+#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x00000010
+
+#define RX_ATTENTION_POWER_MGMT_OFFSET 0x00000004
+#define RX_ATTENTION_POWER_MGMT_LSB 5
+#define RX_ATTENTION_POWER_MGMT_MSB 5
+#define RX_ATTENTION_POWER_MGMT_MASK 0x00000020
+
+#define RX_ATTENTION_NON_QOS_OFFSET 0x00000004
+#define RX_ATTENTION_NON_QOS_LSB 6
+#define RX_ATTENTION_NON_QOS_MSB 6
+#define RX_ATTENTION_NON_QOS_MASK 0x00000040
+
+#define RX_ATTENTION_NULL_DATA_OFFSET 0x00000004
+#define RX_ATTENTION_NULL_DATA_LSB 7
+#define RX_ATTENTION_NULL_DATA_MSB 7
+#define RX_ATTENTION_NULL_DATA_MASK 0x00000080
+
+#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x00000004
+#define RX_ATTENTION_MGMT_TYPE_LSB 8
+#define RX_ATTENTION_MGMT_TYPE_MSB 8
+#define RX_ATTENTION_MGMT_TYPE_MASK 0x00000100
+
+#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x00000004
+#define RX_ATTENTION_CTRL_TYPE_LSB 9
+#define RX_ATTENTION_CTRL_TYPE_MSB 9
+#define RX_ATTENTION_CTRL_TYPE_MASK 0x00000200
+
+#define RX_ATTENTION_MORE_DATA_OFFSET 0x00000004
+#define RX_ATTENTION_MORE_DATA_LSB 10
+#define RX_ATTENTION_MORE_DATA_MSB 10
+#define RX_ATTENTION_MORE_DATA_MASK 0x00000400
+
+#define RX_ATTENTION_EOSP_OFFSET 0x00000004
+#define RX_ATTENTION_EOSP_LSB 11
+#define RX_ATTENTION_EOSP_MSB 11
+#define RX_ATTENTION_EOSP_MASK 0x00000800
+
+#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x00000004
+#define RX_ATTENTION_A_MSDU_ERROR_LSB 12
+#define RX_ATTENTION_A_MSDU_ERROR_MSB 12
+#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x00001000
+
+#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x00000004
+#define RX_ATTENTION_FRAGMENT_FLAG_LSB 13
+#define RX_ATTENTION_FRAGMENT_FLAG_MSB 13
+#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x00002000
+
+#define RX_ATTENTION_ORDER_OFFSET 0x00000004
+#define RX_ATTENTION_ORDER_LSB 14
+#define RX_ATTENTION_ORDER_MSB 14
+#define RX_ATTENTION_ORDER_MASK 0x00004000
+
+#define RX_ATTENTION_CCE_MATCH_OFFSET 0x00000004
+#define RX_ATTENTION_CCE_MATCH_LSB 15
+#define RX_ATTENTION_CCE_MATCH_MSB 15
+#define RX_ATTENTION_CCE_MATCH_MASK 0x00008000
+
+#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_OVERFLOW_ERR_LSB 16
+#define RX_ATTENTION_OVERFLOW_ERR_MSB 16
+#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x00010000
+
+#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 17
+#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 17
+#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x00020000
+
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000004
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 18
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 18
+#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000
+
+#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x00000004
+#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 19
+#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 19
+#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x00080000
+
+#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x00000004
+#define RX_ATTENTION_SA_IDX_INVALID_LSB 20
+#define RX_ATTENTION_SA_IDX_INVALID_MSB 20
+#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x00100000
+
+#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x00000004
+#define RX_ATTENTION_DA_IDX_INVALID_LSB 21
+#define RX_ATTENTION_DA_IDX_INVALID_MSB 21
+#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x00200000
+
+#define RX_ATTENTION_RESERVED_1B_OFFSET 0x00000004
+#define RX_ATTENTION_RESERVED_1B_LSB 22
+#define RX_ATTENTION_RESERVED_1B_MSB 22
+#define RX_ATTENTION_RESERVED_1B_MASK 0x00400000
+
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 23
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 23
+#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000
+
+#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x00000004
+#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 24
+#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 24
+#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x01000000
+
+#define RX_ATTENTION_DIRECTED_OFFSET 0x00000004
+#define RX_ATTENTION_DIRECTED_LSB 25
+#define RX_ATTENTION_DIRECTED_MSB 25
+#define RX_ATTENTION_DIRECTED_MASK 0x02000000
+
+#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x00000004
+#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 26
+#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 26
+#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x04000000
+
+#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 27
+#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 27
+#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x08000000
+
+#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_TKIP_MIC_ERR_LSB 28
+#define RX_ATTENTION_TKIP_MIC_ERR_MSB 28
+#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x10000000
+
+#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_DECRYPT_ERR_LSB 29
+#define RX_ATTENTION_DECRYPT_ERR_MSB 29
+#define RX_ATTENTION_DECRYPT_ERR_MASK 0x20000000
+
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 30
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 30
+#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x40000000
+
+#define RX_ATTENTION_FCS_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_FCS_ERR_LSB 31
+#define RX_ATTENTION_FCS_ERR_MSB 31
+#define RX_ATTENTION_FCS_ERR_MASK 0x80000000
+
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0
+#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x00000001
+
+#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x00000008
+#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1
+#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1
+#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x00000002
+
+#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x00000008
+#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2
+#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2
+#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x00000004
+
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x00000008
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3
+#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x00000008
+
+#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4
+#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4
+#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x00000010
+
+#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5
+#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5
+#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x00000020
+
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x00000008
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6
+#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x00000040
+
+#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x00000008
+#define RX_ATTENTION_DA_IS_VALID_LSB 7
+#define RX_ATTENTION_DA_IS_VALID_MSB 7
+#define RX_ATTENTION_DA_IS_VALID_MASK 0x00000080
+
+#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x00000008
+#define RX_ATTENTION_DA_IS_MCBC_LSB 8
+#define RX_ATTENTION_DA_IS_MCBC_MSB 8
+#define RX_ATTENTION_DA_IS_MCBC_MASK 0x00000100
+
+#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x00000008
+#define RX_ATTENTION_SA_IS_VALID_LSB 9
+#define RX_ATTENTION_SA_IS_VALID_MSB 9
+#define RX_ATTENTION_SA_IS_VALID_MASK 0x00000200
+
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x00000008
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12
+#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x00001c00
+
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000008
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13
+#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x00002000
+
+#define RX_ATTENTION_RESERVED_2_OFFSET 0x00000008
+#define RX_ATTENTION_RESERVED_2_LSB 14
+#define RX_ATTENTION_RESERVED_2_MSB 30
+#define RX_ATTENTION_RESERVED_2_MASK 0x7fffc000
+
+#define RX_ATTENTION_MSDU_DONE_OFFSET 0x00000008
+#define RX_ATTENTION_MSDU_DONE_LSB 31
+#define RX_ATTENTION_MSDU_DONE_MSB 31
+#define RX_ATTENTION_MSDU_DONE_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_flow_search_entry.h b/drivers/staging/fw-api/hw/peach/v1/rx_flow_search_entry.h
new file mode 100644
index 0000000000000000000000000000000000000000..adcae02a8492a04a5e2232955263b240e160a944
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_flow_search_entry.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_FLOW_SEARCH_ENTRY_H_
+#define _RX_FLOW_SEARCH_ENTRY_H_
+
+#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16
+
+struct rx_flow_search_entry {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t src_ip_127_96 : 32;
+ uint32_t src_ip_95_64 : 32;
+ uint32_t src_ip_63_32 : 32;
+ uint32_t src_ip_31_0 : 32;
+ uint32_t dest_ip_127_96 : 32;
+ uint32_t dest_ip_95_64 : 32;
+ uint32_t dest_ip_63_32 : 32;
+ uint32_t dest_ip_31_0 : 32;
+ uint32_t src_port : 16,
+ dest_port : 16;
+ uint32_t l4_protocol : 8,
+ valid : 1,
+ reserved_9 : 4,
+ service_code : 9,
+ priority_valid : 1,
+ use_ppe : 1,
+ reo_destination_indication : 5,
+ msdu_drop : 1,
+ reo_destination_handler : 2;
+ uint32_t metadata : 32;
+ uint32_t aggregation_count : 7,
+ lro_eligible : 1,
+ msdu_count : 24;
+ uint32_t msdu_byte_count : 32;
+ uint32_t timestamp : 32;
+ uint32_t cumulative_ip_length_pmac1 : 16,
+ cumulative_ip_length : 16;
+ uint32_t tcp_sequence_number : 32;
+#else
+ uint32_t src_ip_127_96 : 32;
+ uint32_t src_ip_95_64 : 32;
+ uint32_t src_ip_63_32 : 32;
+ uint32_t src_ip_31_0 : 32;
+ uint32_t dest_ip_127_96 : 32;
+ uint32_t dest_ip_95_64 : 32;
+ uint32_t dest_ip_63_32 : 32;
+ uint32_t dest_ip_31_0 : 32;
+ uint32_t dest_port : 16,
+ src_port : 16;
+ uint32_t reo_destination_handler : 2,
+ msdu_drop : 1,
+ reo_destination_indication : 5,
+ use_ppe : 1,
+ priority_valid : 1,
+ service_code : 9,
+ reserved_9 : 4,
+ valid : 1,
+ l4_protocol : 8;
+ uint32_t metadata : 32;
+ uint32_t msdu_count : 24,
+ lro_eligible : 1,
+ aggregation_count : 7;
+ uint32_t msdu_byte_count : 32;
+ uint32_t timestamp : 32;
+ uint32_t cumulative_ip_length : 16,
+ cumulative_ip_length_pmac1 : 16;
+ uint32_t tcp_sequence_number : 32;
+#endif
+};
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15
+#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff
+
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000
+
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7
+#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff
+
+#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8
+#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8
+#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100
+
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12
+#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00
+
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21
+#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000
+
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22
+#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000
+
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23
+#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000
+
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000
+
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29
+#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000
+
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000
+
+#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028
+#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6
+#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f
+
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7
+#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080
+
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00
+
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff
+
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff
+
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000
+
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31
+#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_frame_1k_bitmap_ack.h b/drivers/staging/fw-api/hw/peach/v1/rx_frame_1k_bitmap_ack.h
new file mode 100644
index 0000000000000000000000000000000000000000..2698e5b0a5420e5e16b2b10d8450e9ed1a360cdc
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_frame_1k_bitmap_ack.h
@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_FRAME_1K_BITMAP_ACK_H_
+#define _RX_FRAME_1K_BITMAP_ACK_H_
+
+#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 37
+
+struct rx_frame_1k_bitmap_ack {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t reserved_0a : 5,
+ ba_bitmap_size : 2,
+ reserved_0b : 3,
+ ba_tid : 4,
+ sta_full_aid : 13,
+ reserved_0c : 5;
+ uint32_t addr1_31_0 : 32;
+ uint32_t addr1_47_32 : 16,
+ addr2_15_0 : 16;
+ uint32_t addr2_47_16 : 32;
+ uint32_t ba_ts_ctrl : 16,
+ ba_ts_seq : 16;
+ uint32_t ba_ts_bitmap_31_0 : 32;
+ uint32_t ba_ts_bitmap_63_32 : 32;
+ uint32_t ba_ts_bitmap_95_64 : 32;
+ uint32_t ba_ts_bitmap_127_96 : 32;
+ uint32_t ba_ts_bitmap_159_128 : 32;
+ uint32_t ba_ts_bitmap_191_160 : 32;
+ uint32_t ba_ts_bitmap_223_192 : 32;
+ uint32_t ba_ts_bitmap_255_224 : 32;
+ uint32_t ba_ts_bitmap_287_256 : 32;
+ uint32_t ba_ts_bitmap_319_288 : 32;
+ uint32_t ba_ts_bitmap_351_320 : 32;
+ uint32_t ba_ts_bitmap_383_352 : 32;
+ uint32_t ba_ts_bitmap_415_384 : 32;
+ uint32_t ba_ts_bitmap_447_416 : 32;
+ uint32_t ba_ts_bitmap_479_448 : 32;
+ uint32_t ba_ts_bitmap_511_480 : 32;
+ uint32_t ba_ts_bitmap_543_512 : 32;
+ uint32_t ba_ts_bitmap_575_544 : 32;
+ uint32_t ba_ts_bitmap_607_576 : 32;
+ uint32_t ba_ts_bitmap_639_608 : 32;
+ uint32_t ba_ts_bitmap_671_640 : 32;
+ uint32_t ba_ts_bitmap_703_672 : 32;
+ uint32_t ba_ts_bitmap_735_704 : 32;
+ uint32_t ba_ts_bitmap_767_736 : 32;
+ uint32_t ba_ts_bitmap_799_768 : 32;
+ uint32_t ba_ts_bitmap_831_800 : 32;
+ uint32_t ba_ts_bitmap_863_832 : 32;
+ uint32_t ba_ts_bitmap_895_864 : 32;
+ uint32_t ba_ts_bitmap_927_896 : 32;
+ uint32_t ba_ts_bitmap_959_928 : 32;
+ uint32_t ba_ts_bitmap_991_960 : 32;
+ uint32_t ba_ts_bitmap_1023_992 : 32;
+#else
+ uint32_t reserved_0c : 5,
+ sta_full_aid : 13,
+ ba_tid : 4,
+ reserved_0b : 3,
+ ba_bitmap_size : 2,
+ reserved_0a : 5;
+ uint32_t addr1_31_0 : 32;
+ uint32_t addr2_15_0 : 16,
+ addr1_47_32 : 16;
+ uint32_t addr2_47_16 : 32;
+ uint32_t ba_ts_seq : 16,
+ ba_ts_ctrl : 16;
+ uint32_t ba_ts_bitmap_31_0 : 32;
+ uint32_t ba_ts_bitmap_63_32 : 32;
+ uint32_t ba_ts_bitmap_95_64 : 32;
+ uint32_t ba_ts_bitmap_127_96 : 32;
+ uint32_t ba_ts_bitmap_159_128 : 32;
+ uint32_t ba_ts_bitmap_191_160 : 32;
+ uint32_t ba_ts_bitmap_223_192 : 32;
+ uint32_t ba_ts_bitmap_255_224 : 32;
+ uint32_t ba_ts_bitmap_287_256 : 32;
+ uint32_t ba_ts_bitmap_319_288 : 32;
+ uint32_t ba_ts_bitmap_351_320 : 32;
+ uint32_t ba_ts_bitmap_383_352 : 32;
+ uint32_t ba_ts_bitmap_415_384 : 32;
+ uint32_t ba_ts_bitmap_447_416 : 32;
+ uint32_t ba_ts_bitmap_479_448 : 32;
+ uint32_t ba_ts_bitmap_511_480 : 32;
+ uint32_t ba_ts_bitmap_543_512 : 32;
+ uint32_t ba_ts_bitmap_575_544 : 32;
+ uint32_t ba_ts_bitmap_607_576 : 32;
+ uint32_t ba_ts_bitmap_639_608 : 32;
+ uint32_t ba_ts_bitmap_671_640 : 32;
+ uint32_t ba_ts_bitmap_703_672 : 32;
+ uint32_t ba_ts_bitmap_735_704 : 32;
+ uint32_t ba_ts_bitmap_767_736 : 32;
+ uint32_t ba_ts_bitmap_799_768 : 32;
+ uint32_t ba_ts_bitmap_831_800 : 32;
+ uint32_t ba_ts_bitmap_863_832 : 32;
+ uint32_t ba_ts_bitmap_895_864 : 32;
+ uint32_t ba_ts_bitmap_927_896 : 32;
+ uint32_t ba_ts_bitmap_959_928 : 32;
+ uint32_t ba_ts_bitmap_991_960 : 32;
+ uint32_t ba_ts_bitmap_1023_992 : 32;
+#endif
+};
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x00000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x0000001f
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x00000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6
+#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x00000060
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x00000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 7
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x00000380
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x00000000
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13
+#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x00003c00
+
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x00000000
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26
+#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x07ffc000
+
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x00000000
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0xf8000000
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x00000004
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x00000008
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 15
+#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x00000008
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 16
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0xffff0000
+
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000c
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x00000010
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 15
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x00000010
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 16
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff0000
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x00000014
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x00000018
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000001c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x00000020
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x00000024
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x00000028
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000002c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x00000030
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x00000034
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x00000038
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000003c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x00000040
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x00000044
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x00000048
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000004c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x00000050
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x00000054
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x00000058
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000005c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x00000060
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x00000064
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x00000068
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000006c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x00000070
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x00000074
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x00000078
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000007c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x00000080
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x00000084
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x00000088
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000008c
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0xffffffff
+
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x00000090
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 0
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 31
+#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_frame_bitmap_ack.h b/drivers/staging/fw-api/hw/peach/v1/rx_frame_bitmap_ack.h
new file mode 100644
index 0000000000000000000000000000000000000000..c9db51691c319f7ca08d98610d2a0a861742a115
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_frame_bitmap_ack.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_FRAME_BITMAP_ACK_H_
+#define _RX_FRAME_BITMAP_ACK_H_
+
+#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 13
+
+struct rx_frame_bitmap_ack {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t no_bitmap_available : 1,
+ explicit_ack : 1,
+ explict_ack_type : 3,
+ ba_bitmap_size : 2,
+ reserved_0a : 3,
+ ba_tid : 4,
+ sta_full_aid : 13,
+ reserved_0b : 5;
+ uint32_t addr1_31_0 : 32;
+ uint32_t addr1_47_32 : 16,
+ addr2_15_0 : 16;
+ uint32_t addr2_47_16 : 32;
+ uint32_t ba_ts_ctrl : 16,
+ ba_ts_seq : 16;
+ uint32_t ba_ts_bitmap_31_0 : 32;
+ uint32_t ba_ts_bitmap_63_32 : 32;
+ uint32_t ba_ts_bitmap_95_64 : 32;
+ uint32_t ba_ts_bitmap_127_96 : 32;
+ uint32_t ba_ts_bitmap_159_128 : 32;
+ uint32_t ba_ts_bitmap_191_160 : 32;
+ uint32_t ba_ts_bitmap_223_192 : 32;
+ uint32_t ba_ts_bitmap_255_224 : 32;
+#else
+ uint32_t reserved_0b : 5,
+ sta_full_aid : 13,
+ ba_tid : 4,
+ reserved_0a : 3,
+ ba_bitmap_size : 2,
+ explict_ack_type : 3,
+ explicit_ack : 1,
+ no_bitmap_available : 1;
+ uint32_t addr1_31_0 : 32;
+ uint32_t addr2_15_0 : 16,
+ addr1_47_32 : 16;
+ uint32_t addr2_47_16 : 32;
+ uint32_t ba_ts_seq : 16,
+ ba_ts_ctrl : 16;
+ uint32_t ba_ts_bitmap_31_0 : 32;
+ uint32_t ba_ts_bitmap_63_32 : 32;
+ uint32_t ba_ts_bitmap_95_64 : 32;
+ uint32_t ba_ts_bitmap_127_96 : 32;
+ uint32_t ba_ts_bitmap_159_128 : 32;
+ uint32_t ba_ts_bitmap_191_160 : 32;
+ uint32_t ba_ts_bitmap_223_192 : 32;
+ uint32_t ba_ts_bitmap_255_224 : 32;
+#endif
+};
+
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x00000000
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0
+#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x00000001
+
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x00000000
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1
+#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x00000002
+
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x00000000
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4
+#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x0000001c
+
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x00000000
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6
+#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x00000060
+
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x00000000
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 7
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9
+#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x00000380
+
+#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x00000000
+#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10
+#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13
+#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x00003c00
+
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x00000000
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26
+#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x07ffc000
+
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x00000000
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31
+#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0xf8000000
+
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x00000004
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 0
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 31
+#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x00000008
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 0
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 15
+#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff
+
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x00000008
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 16
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 31
+#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0xffff0000
+
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000c
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 0
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 31
+#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x00000010
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 0
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 15
+#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x00000010
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 16
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 31
+#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff0000
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x00000014
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x00000018
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000001c
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x00000020
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x00000024
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x00000028
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000002c
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff
+
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x00000030
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31
+#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_frame_bitmap_req.h b/drivers/staging/fw-api/hw/peach/v1/rx_frame_bitmap_req.h
new file mode 100644
index 0000000000000000000000000000000000000000..160de339bdf63cdba53c52621ac767394f77fba5
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_frame_bitmap_req.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_FRAME_BITMAP_REQ_H_
+#define _RX_FRAME_BITMAP_REQ_H_
+
+#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 1
+
+struct rx_frame_bitmap_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t explicit_user_request : 1,
+ user_request_type : 1,
+ user_number : 6,
+ sw_peer_id : 16,
+ tid_specific_request : 1,
+ requested_tid : 4,
+ reserved_0 : 3;
+#else
+ uint32_t reserved_0 : 3,
+ requested_tid : 4,
+ tid_specific_request : 1,
+ sw_peer_id : 16,
+ user_number : 6,
+ user_request_type : 1,
+ explicit_user_request : 1;
+#endif
+};
+
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x00000000
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0
+#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x00000001
+
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x00000000
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1
+#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x00000002
+
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x00000000
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7
+#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x000000fc
+
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x00000000
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23
+#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x00ffff00
+
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x00000000
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24
+#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x01000000
+
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x00000000
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28
+#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x1e000000
+
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x00000000
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31
+#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0xe0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_location_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_location_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..77089c7cf312f960e120231fd28878ffccfe6e9d
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_location_info.h
@@ -0,0 +1,470 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_LOCATION_INFO_H_
+#define _RX_LOCATION_INFO_H_
+
+#define NUM_OF_DWORDS_RX_LOCATION_INFO 28
+
+struct rx_location_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t rx_location_info_valid : 1,
+ rtt_hw_ifft_mode : 1,
+ rtt_11az_mode : 2,
+ reserved_0 : 4,
+ rtt_num_fac : 8,
+ rtt_rx_chain_mask : 8,
+ rtt_num_streams : 8;
+ uint32_t rtt_first_selected_chain : 8,
+ rtt_second_selected_chain : 8,
+ rtt_cfr_status : 8,
+ rtt_cir_status : 8;
+ uint32_t rtt_che_buffer_pointer_low32 : 32;
+ uint32_t rtt_che_buffer_pointer_high8 : 8,
+ reserved_3 : 8,
+ rtt_pkt_bw_vht : 4,
+ rtt_pkt_bw_leg : 4,
+ rtt_mcs_rate : 8;
+ uint32_t rtt_cfo_measurement : 16,
+ rtt_preamble_type : 8,
+ rtt_gi_type : 8;
+ uint32_t rx_start_ts : 32;
+ uint32_t rx_start_ts_upper : 32;
+ uint32_t rx_end_ts : 32;
+ uint32_t gain_chain0 : 16,
+ gain_chain1 : 16;
+ uint32_t gain_chain2 : 16,
+ gain_chain3 : 16;
+ uint32_t gain_report_status : 8,
+ rtt_timing_backoff_sel : 8,
+ rtt_fac_combined : 16;
+ uint32_t rtt_fac_0 : 16,
+ rtt_fac_1 : 16;
+ uint32_t rtt_fac_2 : 16,
+ rtt_fac_3 : 16;
+ uint32_t rtt_fac_4 : 16,
+ rtt_fac_5 : 16;
+ uint32_t rtt_fac_6 : 16,
+ rtt_fac_7 : 16;
+ uint32_t rtt_fac_8 : 16,
+ rtt_fac_9 : 16;
+ uint32_t rtt_fac_10 : 16,
+ rtt_fac_11 : 16;
+ uint32_t rtt_fac_12 : 16,
+ rtt_fac_13 : 16;
+ uint32_t rtt_fac_14 : 16,
+ rtt_fac_15 : 16;
+ uint32_t rtt_fac_16 : 16,
+ rtt_fac_17 : 16;
+ uint32_t rtt_fac_18 : 16,
+ rtt_fac_19 : 16;
+ uint32_t rtt_fac_20 : 16,
+ rtt_fac_21 : 16;
+ uint32_t rtt_fac_22 : 16,
+ rtt_fac_23 : 16;
+ uint32_t rtt_fac_24 : 16,
+ rtt_fac_25 : 16;
+ uint32_t rtt_fac_26 : 16,
+ rtt_fac_27 : 16;
+ uint32_t rtt_fac_28 : 16,
+ rtt_fac_29 : 16;
+ uint32_t rtt_fac_30 : 16,
+ rtt_fac_31 : 16;
+ uint32_t reserved_27a : 32;
+#else
+ uint32_t rtt_num_streams : 8,
+ rtt_rx_chain_mask : 8,
+ rtt_num_fac : 8,
+ reserved_0 : 4,
+ rtt_11az_mode : 2,
+ rtt_hw_ifft_mode : 1,
+ rx_location_info_valid : 1;
+ uint32_t rtt_cir_status : 8,
+ rtt_cfr_status : 8,
+ rtt_second_selected_chain : 8,
+ rtt_first_selected_chain : 8;
+ uint32_t rtt_che_buffer_pointer_low32 : 32;
+ uint32_t rtt_mcs_rate : 8,
+ rtt_pkt_bw_leg : 4,
+ rtt_pkt_bw_vht : 4,
+ reserved_3 : 8,
+ rtt_che_buffer_pointer_high8 : 8;
+ uint32_t rtt_gi_type : 8,
+ rtt_preamble_type : 8,
+ rtt_cfo_measurement : 16;
+ uint32_t rx_start_ts : 32;
+ uint32_t rx_start_ts_upper : 32;
+ uint32_t rx_end_ts : 32;
+ uint32_t gain_chain1 : 16,
+ gain_chain0 : 16;
+ uint32_t gain_chain3 : 16,
+ gain_chain2 : 16;
+ uint32_t rtt_fac_combined : 16,
+ rtt_timing_backoff_sel : 8,
+ gain_report_status : 8;
+ uint32_t rtt_fac_1 : 16,
+ rtt_fac_0 : 16;
+ uint32_t rtt_fac_3 : 16,
+ rtt_fac_2 : 16;
+ uint32_t rtt_fac_5 : 16,
+ rtt_fac_4 : 16;
+ uint32_t rtt_fac_7 : 16,
+ rtt_fac_6 : 16;
+ uint32_t rtt_fac_9 : 16,
+ rtt_fac_8 : 16;
+ uint32_t rtt_fac_11 : 16,
+ rtt_fac_10 : 16;
+ uint32_t rtt_fac_13 : 16,
+ rtt_fac_12 : 16;
+ uint32_t rtt_fac_15 : 16,
+ rtt_fac_14 : 16;
+ uint32_t rtt_fac_17 : 16,
+ rtt_fac_16 : 16;
+ uint32_t rtt_fac_19 : 16,
+ rtt_fac_18 : 16;
+ uint32_t rtt_fac_21 : 16,
+ rtt_fac_20 : 16;
+ uint32_t rtt_fac_23 : 16,
+ rtt_fac_22 : 16;
+ uint32_t rtt_fac_25 : 16,
+ rtt_fac_24 : 16;
+ uint32_t rtt_fac_27 : 16,
+ rtt_fac_26 : 16;
+ uint32_t rtt_fac_29 : 16,
+ rtt_fac_28 : 16;
+ uint32_t rtt_fac_31 : 16,
+ rtt_fac_30 : 16;
+ uint32_t reserved_27a : 32;
+#endif
+};
+
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0
+#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001
+
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1
+#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002
+
+#define RX_LOCATION_INFO_RTT_11AZ_MODE_OFFSET 0x00000000
+#define RX_LOCATION_INFO_RTT_11AZ_MODE_LSB 2
+#define RX_LOCATION_INFO_RTT_11AZ_MODE_MSB 3
+#define RX_LOCATION_INFO_RTT_11AZ_MODE_MASK 0x0000000c
+
+#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000
+#define RX_LOCATION_INFO_RESERVED_0_LSB 4
+#define RX_LOCATION_INFO_RESERVED_0_MSB 7
+#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0
+
+#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000
+#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8
+#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15
+#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23
+#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000
+
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31
+#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000
+
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7
+#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff
+
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15
+#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23
+#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000
+
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31
+#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000
+
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff
+
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7
+#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff
+
+#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_RESERVED_3_LSB 8
+#define RX_LOCATION_INFO_RESERVED_3_MSB 15
+#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19
+#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000
+
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23
+#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000
+
+#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24
+#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31
+#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000
+
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15
+#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23
+#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000
+
+#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010
+#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24
+#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31
+#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000
+
+#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014
+#define RX_LOCATION_INFO_RX_START_TS_LSB 0
+#define RX_LOCATION_INFO_RX_START_TS_MSB 31
+#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff
+
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31
+#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff
+
+#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c
+#define RX_LOCATION_INFO_RX_END_TS_LSB 0
+#define RX_LOCATION_INFO_RX_END_TS_MSB 31
+#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff
+
+#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020
+#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0
+#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15
+#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020
+#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16
+#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31
+#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024
+#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0
+#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15
+#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024
+#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16
+#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31
+#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7
+#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff
+
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15
+#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00
+
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c
+#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c
+#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030
+#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030
+#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034
+#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034
+#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038
+#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038
+#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c
+#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c
+#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040
+#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040
+#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044
+#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044
+#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048
+#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048
+#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c
+#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c
+#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050
+#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050
+#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054
+#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054
+#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058
+#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058
+#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c
+#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c
+#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060
+#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060
+#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064
+#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064
+#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068
+#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0
+#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15
+#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff
+
+#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068
+#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16
+#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31
+#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000
+
+#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c
+#define RX_LOCATION_INFO_RESERVED_27A_LSB 0
+#define RX_LOCATION_INFO_RESERVED_27A_MSB 31
+#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_desc_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_desc_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..c88ba6a17199cd5bc1d57512c8cbb0f4bb23e47e
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_desc_info.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MPDU_DESC_INFO_H_
+#define _RX_MPDU_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2
+
+struct rx_mpdu_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t msdu_count : 8,
+ fragment_flag : 1,
+ mpdu_retry_bit : 1,
+ ampdu_flag : 1,
+ bar_frame : 1,
+ pn_fields_contain_valid_info : 1,
+ raw_mpdu : 1,
+ more_fragment_flag : 1,
+ src_info : 12,
+ mpdu_qos_control_valid : 1,
+ tid : 4;
+ uint32_t peer_meta_data : 32;
+#else
+ uint32_t tid : 4,
+ mpdu_qos_control_valid : 1,
+ src_info : 12,
+ more_fragment_flag : 1,
+ raw_mpdu : 1,
+ pn_fields_contain_valid_info : 1,
+ bar_frame : 1,
+ ampdu_flag : 1,
+ mpdu_retry_bit : 1,
+ fragment_flag : 1,
+ msdu_count : 8;
+ uint32_t peer_meta_data : 32;
+#endif
+};
+
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7
+#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff
+
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8
+#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100
+
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9
+#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200
+
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10
+#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400
+
+#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11
+#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11
+#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800
+
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13
+#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13
+#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000
+
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14
+#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_SRC_INFO_LSB 15
+#define RX_MPDU_DESC_INFO_SRC_INFO_MSB 26
+#define RX_MPDU_DESC_INFO_SRC_INFO_MASK 0x07ff8000
+
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27
+#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
+
+#define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_TID_LSB 28
+#define RX_MPDU_DESC_INFO_TID_MSB 31
+#define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000
+
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31
+#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_details.h b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_details.h
new file mode 100644
index 0000000000000000000000000000000000000000..9c909a87e2c11ec028182b17899363948d325793
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_details.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MPDU_DETAILS_H_
+#define _RX_MPDU_DETAILS_H_
+
+#include "rx_mpdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4
+
+struct rx_mpdu_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct buffer_addr_info msdu_link_desc_addr_info;
+ struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+#else
+ struct buffer_addr_info msdu_link_desc_addr_info;
+ struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+#endif
+};
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
+
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
+#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_end.h b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_end.h
new file mode 100644
index 0000000000000000000000000000000000000000..26824a03ee3a2df9c53b05c0f9a9dea404852ae5
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_end.h
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MPDU_END_H_
+#define _RX_MPDU_END_H_
+
+#define NUM_OF_DWORDS_RX_MPDU_END 4
+
+struct rx_mpdu_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t rxpcu_mpdu_filter_in_category : 2,
+ sw_frame_group_id : 7,
+ reserved_0 : 7,
+ phy_ppdu_id : 16;
+ uint32_t reserved_1a : 11,
+ unsup_ktype_short_frame : 1,
+ rx_in_tx_decrypt_byp : 1,
+ overflow_err : 1,
+ mpdu_length_err : 1,
+ tkip_mic_err : 1,
+ decrypt_err : 1,
+ unencrypted_frame_err : 1,
+ pn_fields_contain_valid_info : 1,
+ fcs_err : 1,
+ msdu_length_err : 1,
+ rxdma0_destination_ring : 3,
+ rxdma1_destination_ring : 3,
+ decrypt_status_code : 3,
+ rx_bitmap_not_updated : 1,
+ reserved_1b : 1;
+ uint32_t reserved_2a : 15,
+ rxpcu_mgmt_sequence_nr_valid : 1,
+ rxpcu_mgmt_sequence_nr : 16;
+ uint32_t __reserved_g_0002 : 32;
+#else
+ uint32_t phy_ppdu_id : 16,
+ reserved_0 : 7,
+ sw_frame_group_id : 7,
+ rxpcu_mpdu_filter_in_category : 2;
+ uint32_t reserved_1b : 1,
+ rx_bitmap_not_updated : 1,
+ decrypt_status_code : 3,
+ rxdma1_destination_ring : 3,
+ rxdma0_destination_ring : 3,
+ msdu_length_err : 1,
+ fcs_err : 1,
+ pn_fields_contain_valid_info : 1,
+ unencrypted_frame_err : 1,
+ decrypt_err : 1,
+ tkip_mic_err : 1,
+ mpdu_length_err : 1,
+ overflow_err : 1,
+ rx_in_tx_decrypt_byp : 1,
+ unsup_ktype_short_frame : 1,
+ reserved_1a : 11;
+ uint32_t rxpcu_mgmt_sequence_nr : 16,
+ rxpcu_mgmt_sequence_nr_valid : 1,
+ reserved_2a : 15;
+ uint32_t __reserved_g_0002 : 32;
+#endif
+};
+
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
+#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x00000000
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8
+#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+#define RX_MPDU_END_RESERVED_0_OFFSET 0x00000000
+#define RX_MPDU_END_RESERVED_0_LSB 9
+#define RX_MPDU_END_RESERVED_0_MSB 15
+#define RX_MPDU_END_RESERVED_0_MASK 0x0000fe00
+
+#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_MPDU_END_PHY_PPDU_ID_LSB 16
+#define RX_MPDU_END_PHY_PPDU_ID_MSB 31
+#define RX_MPDU_END_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_MPDU_END_RESERVED_1A_OFFSET 0x00000004
+#define RX_MPDU_END_RESERVED_1A_LSB 0
+#define RX_MPDU_END_RESERVED_1A_MSB 10
+#define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff
+
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 11
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 11
+#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800
+
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 12
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 12
+#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000
+
+#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_OVERFLOW_ERR_LSB 13
+#define RX_MPDU_END_OVERFLOW_ERR_MSB 13
+#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x00002000
+
+#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 14
+#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 14
+#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x00004000
+
+#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_TKIP_MIC_ERR_LSB 15
+#define RX_MPDU_END_TKIP_MIC_ERR_MSB 15
+#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x00008000
+
+#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_DECRYPT_ERR_LSB 16
+#define RX_MPDU_END_DECRYPT_ERR_MSB 16
+#define RX_MPDU_END_DECRYPT_ERR_MASK 0x00010000
+
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 17
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 17
+#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x00020000
+
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 18
+#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000
+
+#define RX_MPDU_END_FCS_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_FCS_ERR_LSB 19
+#define RX_MPDU_END_FCS_ERR_MSB 19
+#define RX_MPDU_END_FCS_ERR_MASK 0x00080000
+
+#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 20
+#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 20
+#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x00100000
+
+#define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x00000004
+#define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 21
+#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 23
+#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e00000
+
+#define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x00000004
+#define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 24
+#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 26
+#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x07000000
+
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x00000004
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 27
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 29
+#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x38000000
+
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 30
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 30
+#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x40000000
+
+#define RX_MPDU_END_RESERVED_1B_OFFSET 0x00000004
+#define RX_MPDU_END_RESERVED_1B_LSB 31
+#define RX_MPDU_END_RESERVED_1B_MSB 31
+#define RX_MPDU_END_RESERVED_1B_MASK 0x80000000
+
+#define RX_MPDU_END_RESERVED_2A_OFFSET 0x00000008
+#define RX_MPDU_END_RESERVED_2A_LSB 0
+#define RX_MPDU_END_RESERVED_2A_MSB 14
+#define RX_MPDU_END_RESERVED_2A_MASK 0x00007fff
+
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x00000008
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x00008000
+
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x00000008
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31
+#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..2231090a035a0f8056365ab1b2cfe8ff40ff1b15
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_info.h
@@ -0,0 +1,835 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MPDU_INFO_H_
+#define _RX_MPDU_INFO_H_
+
+#include "rxpt_classify_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_INFO 30
+
+struct rx_mpdu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct rxpt_classify_info rxpt_classify_info_details;
+ uint32_t epd_en : 1,
+ all_frames_shall_be_encrypted : 1,
+ encrypt_type : 4,
+ wep_key_width_for_variable_key : 2,
+ __reserved_g_0003 : 2,
+ bssid_hit : 1,
+ bssid_number : 4,
+ tid : 4,
+ reserved_7a : 13;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32;
+ uint32_t rx_reo_queue_desc_addr_39_32 : 8,
+ receive_queue_number : 16,
+ pre_delim_err_warning : 1,
+ first_delim_err : 1,
+ reserved_2a : 6;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_63_32 : 32;
+ uint32_t pn_95_64 : 32;
+ uint32_t pn_127_96 : 32;
+ uint32_t mpdu_frame_control_valid : 1,
+ mpdu_duration_valid : 1,
+ mac_addr_ad1_valid : 1,
+ mac_addr_ad2_valid : 1,
+ mac_addr_ad3_valid : 1,
+ mac_addr_ad4_valid : 1,
+ mpdu_sequence_control_valid : 1,
+ mpdu_qos_control_valid : 1,
+ mpdu_ht_control_valid : 1,
+ frame_encryption_info_valid : 1,
+ mpdu_fragment_number : 4,
+ more_fragment_flag : 1,
+ reserved_11a : 1,
+ fr_ds : 1,
+ to_ds : 1,
+ encrypted : 1,
+ mpdu_retry : 1,
+ mpdu_sequence_number : 12;
+ uint32_t peer_meta_data : 32;
+ uint32_t ast_index : 16,
+ sw_peer_id : 16;
+ uint32_t rxpcu_mpdu_filter_in_category : 2,
+ sw_frame_group_id : 7,
+ ndp_frame : 1,
+ phy_err : 1,
+ phy_err_during_mpdu_header : 1,
+ protocol_version_err : 1,
+ ast_based_lookup_valid : 1,
+ __reserved_g_0005 : 1,
+ reserved_9a : 1,
+ phy_ppdu_id : 16;
+ uint32_t key_id_octet : 8,
+ new_peer_entry : 1,
+ decrypt_needed : 1,
+ decap_type : 2,
+ rx_insert_vlan_c_tag_padding : 1,
+ rx_insert_vlan_s_tag_padding : 1,
+ strip_vlan_c_tag_decap : 1,
+ strip_vlan_s_tag_decap : 1,
+ pre_delim_count : 12,
+ ampdu_flag : 1,
+ bar_frame : 1,
+ raw_mpdu : 1,
+ reserved_12 : 1;
+ uint32_t mpdu_length : 14,
+ first_mpdu : 1,
+ mcast_bcast : 1,
+ ast_index_not_found : 1,
+ ast_index_timeout : 1,
+ power_mgmt : 1,
+ non_qos : 1,
+ null_data : 1,
+ mgmt_type : 1,
+ ctrl_type : 1,
+ more_data : 1,
+ eosp : 1,
+ fragment_flag : 1,
+ order : 1,
+ u_apsd_trigger : 1,
+ encrypt_required : 1,
+ directed : 1,
+ amsdu_present : 1,
+ reserved_13 : 1;
+ uint32_t mpdu_frame_control_field : 16,
+ mpdu_duration_field : 16;
+ uint32_t mac_addr_ad1_31_0 : 32;
+ uint32_t mac_addr_ad1_47_32 : 16,
+ mac_addr_ad2_15_0 : 16;
+ uint32_t mac_addr_ad2_47_16 : 32;
+ uint32_t mac_addr_ad3_31_0 : 32;
+ uint32_t mac_addr_ad3_47_32 : 16,
+ mpdu_sequence_control_field : 16;
+ uint32_t mac_addr_ad4_31_0 : 32;
+ uint32_t mac_addr_ad4_47_32 : 16,
+ mpdu_qos_control_field : 16;
+ uint32_t mpdu_ht_control_field : 32;
+ uint32_t vdev_id : 8,
+ service_code : 9,
+ priority_valid : 1,
+ src_info : 12,
+ reserved_23a : 1,
+ __reserved_g_0006 : 1;
+ uint32_t __reserved_g_0007 : 32;
+ uint32_t __reserved_g_0008 : 16,
+ __reserved_g_0009 : 16;
+ uint32_t __reserved_g_0010 : 32;
+ uint32_t authorized_to_send_wds : 1,
+ reserved_27a : 31;
+ uint32_t reserved_28a : 32;
+ uint32_t reserved_29a : 32;
+#else
+ struct rxpt_classify_info rxpt_classify_info_details;
+ uint32_t reserved_7a : 13,
+ tid : 4,
+ bssid_number : 4,
+ bssid_hit : 1,
+ __reserved_g_0003 : 2,
+ wep_key_width_for_variable_key : 2,
+ encrypt_type : 4,
+ all_frames_shall_be_encrypted : 1,
+ epd_en : 1;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32;
+ uint32_t reserved_2a : 6,
+ first_delim_err : 1,
+ pre_delim_err_warning : 1,
+ receive_queue_number : 16,
+ rx_reo_queue_desc_addr_39_32 : 8;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_63_32 : 32;
+ uint32_t pn_95_64 : 32;
+ uint32_t pn_127_96 : 32;
+ uint32_t mpdu_sequence_number : 12,
+ mpdu_retry : 1,
+ encrypted : 1,
+ to_ds : 1,
+ fr_ds : 1,
+ reserved_11a : 1,
+ more_fragment_flag : 1,
+ mpdu_fragment_number : 4,
+ frame_encryption_info_valid : 1,
+ mpdu_ht_control_valid : 1,
+ mpdu_qos_control_valid : 1,
+ mpdu_sequence_control_valid : 1,
+ mac_addr_ad4_valid : 1,
+ mac_addr_ad3_valid : 1,
+ mac_addr_ad2_valid : 1,
+ mac_addr_ad1_valid : 1,
+ mpdu_duration_valid : 1,
+ mpdu_frame_control_valid : 1;
+ uint32_t peer_meta_data : 32;
+ uint32_t sw_peer_id : 16,
+ ast_index : 16;
+ uint32_t phy_ppdu_id : 16,
+ reserved_9a : 1,
+ __reserved_g_0005 : 1,
+ ast_based_lookup_valid : 1,
+ protocol_version_err : 1,
+ phy_err_during_mpdu_header : 1,
+ phy_err : 1,
+ ndp_frame : 1,
+ sw_frame_group_id : 7,
+ rxpcu_mpdu_filter_in_category : 2;
+ uint32_t reserved_12 : 1,
+ raw_mpdu : 1,
+ bar_frame : 1,
+ ampdu_flag : 1,
+ pre_delim_count : 12,
+ strip_vlan_s_tag_decap : 1,
+ strip_vlan_c_tag_decap : 1,
+ rx_insert_vlan_s_tag_padding : 1,
+ rx_insert_vlan_c_tag_padding : 1,
+ decap_type : 2,
+ decrypt_needed : 1,
+ new_peer_entry : 1,
+ key_id_octet : 8;
+ uint32_t reserved_13 : 1,
+ amsdu_present : 1,
+ directed : 1,
+ encrypt_required : 1,
+ u_apsd_trigger : 1,
+ order : 1,
+ fragment_flag : 1,
+ eosp : 1,
+ more_data : 1,
+ ctrl_type : 1,
+ mgmt_type : 1,
+ null_data : 1,
+ non_qos : 1,
+ power_mgmt : 1,
+ ast_index_timeout : 1,
+ ast_index_not_found : 1,
+ mcast_bcast : 1,
+ first_mpdu : 1,
+ mpdu_length : 14;
+ uint32_t mpdu_duration_field : 16,
+ mpdu_frame_control_field : 16;
+ uint32_t mac_addr_ad1_31_0 : 32;
+ uint32_t mac_addr_ad2_15_0 : 16,
+ mac_addr_ad1_47_32 : 16;
+ uint32_t mac_addr_ad2_47_16 : 32;
+ uint32_t mac_addr_ad3_31_0 : 32;
+ uint32_t mpdu_sequence_control_field : 16,
+ mac_addr_ad3_47_32 : 16;
+ uint32_t mac_addr_ad4_31_0 : 32;
+ uint32_t mpdu_qos_control_field : 16,
+ mac_addr_ad4_47_32 : 16;
+ uint32_t mpdu_ht_control_field : 32;
+ uint32_t __reserved_g_0006 : 1,
+ reserved_23a : 1,
+ src_info : 12,
+ priority_valid : 1,
+ service_code : 9,
+ vdev_id : 8;
+ uint32_t __reserved_g_0007 : 32;
+ uint32_t __reserved_g_0009 : 16,
+ __reserved_g_0008 : 16;
+ uint32_t __reserved_g_0010 : 32;
+ uint32_t reserved_27a : 31,
+ authorized_to_send_wds : 1;
+ uint32_t reserved_28a : 32;
+ uint32_t reserved_29a : 32;
+#endif
+};
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000
+
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31
+#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000
+
+#define RX_MPDU_INFO_EPD_EN_OFFSET 0x00000004
+#define RX_MPDU_INFO_EPD_EN_LSB 0
+#define RX_MPDU_INFO_EPD_EN_MSB 0
+#define RX_MPDU_INFO_EPD_EN_MASK 0x00000001
+
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x00000004
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1
+#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002
+
+#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x00000004
+#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2
+#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5
+#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c
+
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x00000004
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7
+#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0
+
+#define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x00000004
+#define RX_MPDU_INFO_BSSID_HIT_LSB 10
+#define RX_MPDU_INFO_BSSID_HIT_MSB 10
+#define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400
+
+#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x00000004
+#define RX_MPDU_INFO_BSSID_NUMBER_LSB 11
+#define RX_MPDU_INFO_BSSID_NUMBER_MSB 14
+#define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800
+
+#define RX_MPDU_INFO_TID_OFFSET 0x00000004
+#define RX_MPDU_INFO_TID_LSB 15
+#define RX_MPDU_INFO_TID_MSB 18
+#define RX_MPDU_INFO_TID_MASK 0x00078000
+
+#define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x00000004
+#define RX_MPDU_INFO_RESERVED_7A_LSB 19
+#define RX_MPDU_INFO_RESERVED_7A_MSB 31
+#define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000
+
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000008
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000c
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
+#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23
+#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00
+
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000c
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24
+#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000
+
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x0000000c
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25
+#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000
+
+#define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x0000000c
+#define RX_MPDU_INFO_RESERVED_2A_LSB 26
+#define RX_MPDU_INFO_RESERVED_2A_MSB 31
+#define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000
+
+#define RX_MPDU_INFO_PN_31_0_OFFSET 0x00000010
+#define RX_MPDU_INFO_PN_31_0_LSB 0
+#define RX_MPDU_INFO_PN_31_0_MSB 31
+#define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff
+
+#define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000014
+#define RX_MPDU_INFO_PN_63_32_LSB 0
+#define RX_MPDU_INFO_PN_63_32_MSB 31
+#define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff
+
+#define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000018
+#define RX_MPDU_INFO_PN_95_64_LSB 0
+#define RX_MPDU_INFO_PN_95_64_MSB 31
+#define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff
+
+#define RX_MPDU_INFO_PN_127_96_OFFSET 0x0000001c
+#define RX_MPDU_INFO_PN_127_96_LSB 0
+#define RX_MPDU_INFO_PN_127_96_MSB 31
+#define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff
+
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000020
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001
+
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x00000020
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1
+#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002
+
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2
+#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004
+
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3
+#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008
+
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4
+#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010
+
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x00000020
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5
+#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020
+
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000020
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040
+
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000020
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080
+
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x00000020
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100
+
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000020
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9
+#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200
+
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13
+#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00
+
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000020
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14
+#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x00000020
+#define RX_MPDU_INFO_RESERVED_11A_LSB 15
+#define RX_MPDU_INFO_RESERVED_11A_MSB 15
+#define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000
+
+#define RX_MPDU_INFO_FR_DS_OFFSET 0x00000020
+#define RX_MPDU_INFO_FR_DS_LSB 16
+#define RX_MPDU_INFO_FR_DS_MSB 16
+#define RX_MPDU_INFO_FR_DS_MASK 0x00010000
+
+#define RX_MPDU_INFO_TO_DS_OFFSET 0x00000020
+#define RX_MPDU_INFO_TO_DS_LSB 17
+#define RX_MPDU_INFO_TO_DS_MSB 17
+#define RX_MPDU_INFO_TO_DS_MASK 0x00020000
+
+#define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x00000020
+#define RX_MPDU_INFO_ENCRYPTED_LSB 18
+#define RX_MPDU_INFO_ENCRYPTED_MSB 18
+#define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000
+
+#define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x00000020
+#define RX_MPDU_INFO_MPDU_RETRY_LSB 19
+#define RX_MPDU_INFO_MPDU_RETRY_MSB 19
+#define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000
+
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31
+#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000
+
+#define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000024
+#define RX_MPDU_INFO_PEER_META_DATA_LSB 0
+#define RX_MPDU_INFO_PEER_META_DATA_MSB 31
+#define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff
+
+#define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028
+#define RX_MPDU_INFO_AST_INDEX_LSB 0
+#define RX_MPDU_INFO_AST_INDEX_MSB 15
+#define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff
+
+#define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028
+#define RX_MPDU_INFO_SW_PEER_ID_LSB 16
+#define RX_MPDU_INFO_SW_PEER_ID_MSB 31
+#define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000
+
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000002c
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
+#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8
+#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+#define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x0000002c
+#define RX_MPDU_INFO_NDP_FRAME_LSB 9
+#define RX_MPDU_INFO_NDP_FRAME_MSB 9
+#define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200
+
+#define RX_MPDU_INFO_PHY_ERR_OFFSET 0x0000002c
+#define RX_MPDU_INFO_PHY_ERR_LSB 10
+#define RX_MPDU_INFO_PHY_ERR_MSB 10
+#define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400
+
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000002c
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11
+#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800
+
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x0000002c
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12
+#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000
+
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13
+#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000
+
+#define RX_MPDU_INFO_RESERVED_9A_OFFSET 0x0000002c
+#define RX_MPDU_INFO_RESERVED_9A_LSB 15
+#define RX_MPDU_INFO_RESERVED_9A_MSB 15
+#define RX_MPDU_INFO_RESERVED_9A_MASK 0x00008000
+
+#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16
+#define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31
+#define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030
+#define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0
+#define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7
+#define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff
+
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8
+#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100
+
+#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030
+#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9
+#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9
+#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200
+
+#define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030
+#define RX_MPDU_INFO_DECAP_TYPE_LSB 10
+#define RX_MPDU_INFO_DECAP_TYPE_MSB 11
+#define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00
+
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12
+#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000
+
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13
+#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000
+
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14
+#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000
+
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15
+#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000
+
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27
+#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000
+
+#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030
+#define RX_MPDU_INFO_AMPDU_FLAG_LSB 28
+#define RX_MPDU_INFO_AMPDU_FLAG_MSB 28
+#define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000
+
+#define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030
+#define RX_MPDU_INFO_BAR_FRAME_LSB 29
+#define RX_MPDU_INFO_BAR_FRAME_MSB 29
+#define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000
+
+#define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030
+#define RX_MPDU_INFO_RAW_MPDU_LSB 30
+#define RX_MPDU_INFO_RAW_MPDU_MSB 30
+#define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000
+
+#define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030
+#define RX_MPDU_INFO_RESERVED_12_LSB 31
+#define RX_MPDU_INFO_RESERVED_12_MSB 31
+#define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000
+
+#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034
+#define RX_MPDU_INFO_MPDU_LENGTH_LSB 0
+#define RX_MPDU_INFO_MPDU_LENGTH_MSB 13
+#define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff
+
+#define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034
+#define RX_MPDU_INFO_FIRST_MPDU_LSB 14
+#define RX_MPDU_INFO_FIRST_MPDU_MSB 14
+#define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000
+
+#define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034
+#define RX_MPDU_INFO_MCAST_BCAST_LSB 15
+#define RX_MPDU_INFO_MCAST_BCAST_MSB 15
+#define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000
+
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16
+#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000
+
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17
+#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000
+
+#define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034
+#define RX_MPDU_INFO_POWER_MGMT_LSB 18
+#define RX_MPDU_INFO_POWER_MGMT_MSB 18
+#define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000
+
+#define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034
+#define RX_MPDU_INFO_NON_QOS_LSB 19
+#define RX_MPDU_INFO_NON_QOS_MSB 19
+#define RX_MPDU_INFO_NON_QOS_MASK 0x00080000
+
+#define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034
+#define RX_MPDU_INFO_NULL_DATA_LSB 20
+#define RX_MPDU_INFO_NULL_DATA_MSB 20
+#define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000
+
+#define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034
+#define RX_MPDU_INFO_MGMT_TYPE_LSB 21
+#define RX_MPDU_INFO_MGMT_TYPE_MSB 21
+#define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000
+
+#define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034
+#define RX_MPDU_INFO_CTRL_TYPE_LSB 22
+#define RX_MPDU_INFO_CTRL_TYPE_MSB 22
+#define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000
+
+#define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034
+#define RX_MPDU_INFO_MORE_DATA_LSB 23
+#define RX_MPDU_INFO_MORE_DATA_MSB 23
+#define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000
+
+#define RX_MPDU_INFO_EOSP_OFFSET 0x00000034
+#define RX_MPDU_INFO_EOSP_LSB 24
+#define RX_MPDU_INFO_EOSP_MSB 24
+#define RX_MPDU_INFO_EOSP_MASK 0x01000000
+
+#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034
+#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25
+#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25
+#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000
+
+#define RX_MPDU_INFO_ORDER_OFFSET 0x00000034
+#define RX_MPDU_INFO_ORDER_LSB 26
+#define RX_MPDU_INFO_ORDER_MSB 26
+#define RX_MPDU_INFO_ORDER_MASK 0x04000000
+
+#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034
+#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27
+#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27
+#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000
+
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28
+#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000
+
+#define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034
+#define RX_MPDU_INFO_DIRECTED_LSB 29
+#define RX_MPDU_INFO_DIRECTED_MSB 29
+#define RX_MPDU_INFO_DIRECTED_MASK 0x20000000
+
+#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034
+#define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30
+#define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30
+#define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000
+
+#define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034
+#define RX_MPDU_INFO_RESERVED_13_LSB 31
+#define RX_MPDU_INFO_RESERVED_13_MSB 31
+#define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000
+
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15
+#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff
+
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31
+#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000
+
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31
+#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15
+#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31
+#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000
+
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31
+#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31
+#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15
+#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff
+
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31
+#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000
+
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31
+#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff
+
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15
+#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff
+
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31
+#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000
+
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31
+#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff
+
+#define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c
+#define RX_MPDU_INFO_VDEV_ID_LSB 0
+#define RX_MPDU_INFO_VDEV_ID_MSB 7
+#define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff
+
+#define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c
+#define RX_MPDU_INFO_SERVICE_CODE_LSB 8
+#define RX_MPDU_INFO_SERVICE_CODE_MSB 16
+#define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00
+
+#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c
+#define RX_MPDU_INFO_PRIORITY_VALID_LSB 17
+#define RX_MPDU_INFO_PRIORITY_VALID_MSB 17
+#define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000
+
+#define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c
+#define RX_MPDU_INFO_SRC_INFO_LSB 18
+#define RX_MPDU_INFO_SRC_INFO_MSB 29
+#define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000
+
+#define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c
+#define RX_MPDU_INFO_RESERVED_23A_LSB 30
+#define RX_MPDU_INFO_RESERVED_23A_MSB 30
+#define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000
+
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0
+#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001
+
+#define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c
+#define RX_MPDU_INFO_RESERVED_27A_LSB 1
+#define RX_MPDU_INFO_RESERVED_27A_MSB 31
+#define RX_MPDU_INFO_RESERVED_27A_MASK 0xfffffffe
+
+#define RX_MPDU_INFO_RESERVED_28A_OFFSET 0x00000070
+#define RX_MPDU_INFO_RESERVED_28A_LSB 0
+#define RX_MPDU_INFO_RESERVED_28A_MSB 31
+#define RX_MPDU_INFO_RESERVED_28A_MASK 0xffffffff
+
+#define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074
+#define RX_MPDU_INFO_RESERVED_29A_LSB 0
+#define RX_MPDU_INFO_RESERVED_29A_MSB 31
+#define RX_MPDU_INFO_RESERVED_29A_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_link_ptr.h b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_link_ptr.h
new file mode 100644
index 0000000000000000000000000000000000000000..d356550543f4fd81bc669853446acb455cab7266
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_link_ptr.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MPDU_LINK_PTR_H_
+#define _RX_MPDU_LINK_PTR_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2
+
+struct rx_mpdu_link_ptr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct buffer_addr_info mpdu_link_desc_addr_info;
+#else
+ struct buffer_addr_info mpdu_link_desc_addr_info;
+#endif
+};
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_start.h b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_start.h
new file mode 100644
index 0000000000000000000000000000000000000000..18032824c2f046cd98d27b51ba372c5d925625ec
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_mpdu_start.h
@@ -0,0 +1,617 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MPDU_START_H_
+#define _RX_MPDU_START_H_
+
+#include "rx_mpdu_info.h"
+#define NUM_OF_DWORDS_RX_MPDU_START 30
+
+struct rx_mpdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct rx_mpdu_info rx_mpdu_info_details;
+#else
+ struct rx_mpdu_info rx_mpdu_info_details;
+#endif
+};
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x00000001
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 2
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x00000400
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x00007800
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x00078000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x00000004
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff80000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000008
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 23
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 24
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 25
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x02000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x00000010
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x00000014
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x00000018
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000001c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 2
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 3
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 4
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 5
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 6
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MSB 15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x00008000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x00010000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x00020000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x00040000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x00080000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000024
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x00000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x0000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x00000028
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0xffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 2
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x00000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x00000400
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 12
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MSB 15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x00008000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000002c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x000000ff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x00000100
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x00000200
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x00000c00
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x0fff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x10000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x20000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x00000030
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x80000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 13
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 14
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x00004000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x00008000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x00040000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 19
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x00080000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 20
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x00100000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 21
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 21
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x00200000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 22
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 22
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x00400000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 23
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 23
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x00800000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 24
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 24
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x01000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 25
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 25
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x02000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 26
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 26
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x04000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 27
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 27
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x08000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 28
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 28
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x10000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x20000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x40000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x00000034
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x80000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 15
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000005c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 7
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 8
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 16
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff00
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 17
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x00020000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000005c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 18
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 29
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc0000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_OFFSET 0x0000005c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_LSB 30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MSB 30
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MASK 0x40000000
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000006c
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 1
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xfffffffe
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_OFFSET 0x00000070
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MASK 0xffffffff
+
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x00000074
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 0
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 31
+#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_msdu_desc_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_desc_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..90a3df7973a276172e7ce6c2a736b8bf146568c0
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_desc_info.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MSDU_DESC_INFO_H_
+#define _RX_MSDU_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1
+
+struct rx_msdu_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t first_msdu_in_mpdu_flag : 1,
+ last_msdu_in_mpdu_flag : 1,
+ msdu_continuation : 1,
+ msdu_length : 14,
+ msdu_drop : 1,
+ sa_is_valid : 1,
+ da_is_valid : 1,
+ da_is_mcbc : 1,
+ l3_header_padding_msb : 1,
+ tcp_udp_chksum_fail : 1,
+ ip_chksum_fail : 1,
+ fr_ds : 1,
+ to_ds : 1,
+ intra_bss : 1,
+ dest_chip_id : 2,
+ decap_format : 2,
+ reserved_0a : 1;
+#else
+ uint32_t reserved_0a : 1,
+ decap_format : 2,
+ dest_chip_id : 2,
+ intra_bss : 1,
+ to_ds : 1,
+ fr_ds : 1,
+ ip_chksum_fail : 1,
+ tcp_udp_chksum_fail : 1,
+ l3_header_padding_msb : 1,
+ da_is_mcbc : 1,
+ da_is_valid : 1,
+ sa_is_valid : 1,
+ msdu_drop : 1,
+ msdu_length : 14,
+ msdu_continuation : 1,
+ last_msdu_in_mpdu_flag : 1,
+ first_msdu_in_mpdu_flag : 1;
+#endif
+};
+
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2
+#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16
+#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17
+#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17
+#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000
+
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18
+#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000
+
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19
+#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000
+
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20
+#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000
+
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21
+#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23
+#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000
+
+#define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_FR_DS_LSB 24
+#define RX_MSDU_DESC_INFO_FR_DS_MSB 24
+#define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000
+
+#define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_TO_DS_LSB 25
+#define RX_MSDU_DESC_INFO_TO_DS_MSB 25
+#define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000
+
+#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26
+#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26
+#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000
+
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28
+#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000
+
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30
+#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_msdu_details.h b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_details.h
new file mode 100644
index 0000000000000000000000000000000000000000..39313f38b3aeec5c10e0e49e88f65179bce319bd
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_details.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MSDU_DETAILS_H_
+#define _RX_MSDU_DETAILS_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_msdu_ext_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4
+
+struct rx_msdu_details {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct buffer_addr_info buffer_addr_info_details;
+ struct rx_msdu_desc_info rx_msdu_desc_info_details;
+ struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details;
+#else
+ struct buffer_addr_info buffer_addr_info_details;
+ struct rx_msdu_desc_info rx_msdu_desc_info_details;
+ struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details;
+#endif
+};
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31
+#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
+#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000
+
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
+#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_msdu_end.h b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_end.h
new file mode 100644
index 0000000000000000000000000000000000000000..15b0aa3f017b82acba0fb6893c31a46b08b27c7a
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_end.h
@@ -0,0 +1,1097 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MSDU_END_H_
+#define _RX_MSDU_END_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_END 32
+
+struct rx_msdu_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t rxpcu_mpdu_filter_in_category : 2,
+ sw_frame_group_id : 7,
+ reserved_0 : 7,
+ phy_ppdu_id : 16;
+ uint32_t ip_hdr_chksum : 16,
+ reported_mpdu_length : 14,
+ reserved_1a : 2;
+ uint32_t reserved_2a : 8,
+ cce_super_rule : 6,
+ cce_classify_not_done_truncate : 1,
+ cce_classify_not_done_cce_dis : 1,
+ cumulative_l3_checksum : 16;
+ uint32_t rule_indication_31_0 : 32;
+ uint32_t ipv6_options_crc : 32;
+ uint32_t da_offset : 6,
+ sa_offset : 6,
+ da_offset_valid : 1,
+ sa_offset_valid : 1,
+ reserved_5a : 2,
+ l3_type : 16;
+ uint32_t rule_indication_63_32 : 32;
+ uint32_t tcp_seq_number : 32;
+ uint32_t tcp_ack_number : 32;
+ uint32_t tcp_flag : 9,
+ lro_eligible : 1,
+ reserved_9a : 6,
+ window_size : 16;
+ uint32_t sa_sw_peer_id : 16,
+ sa_idx_timeout : 1,
+ da_idx_timeout : 1,
+ to_ds : 1,
+ tid : 4,
+ sa_is_valid : 1,
+ da_is_valid : 1,
+ da_is_mcbc : 1,
+ l3_header_padding : 2,
+ first_msdu : 1,
+ last_msdu : 1,
+ fr_ds : 1,
+ ip_chksum_fail_copy : 1;
+ uint32_t sa_idx : 16,
+ da_idx_or_sw_peer_id : 16;
+ uint32_t msdu_drop : 1,
+ reo_destination_indication : 5,
+ flow_idx : 20,
+ use_ppe : 1,
+ __reserved_g_0003 : 2,
+ vlan_ctag_stripped : 1,
+ vlan_stag_stripped : 1,
+ fragment_flag : 1;
+ uint32_t fse_metadata : 32;
+ uint32_t cce_metadata : 16,
+ tcp_udp_chksum : 16;
+ uint32_t aggregation_count : 8,
+ flow_aggregation_continuation : 1,
+ fisa_timeout : 1,
+ tcp_udp_chksum_fail_copy : 1,
+ msdu_limit_error : 1,
+ flow_idx_timeout : 1,
+ flow_idx_invalid : 1,
+ cce_match : 1,
+ amsdu_parser_error : 1,
+ cumulative_ip_length : 16;
+ uint32_t key_id_octet : 8,
+ reserved_16a : 24;
+ uint32_t reserved_17a : 6,
+ service_code : 9,
+ priority_valid : 1,
+ intra_bss : 1,
+ dest_chip_id : 2,
+ multicast_echo : 1,
+ wds_learning_event : 1,
+ wds_roaming_event : 1,
+ wds_keep_alive_event : 1,
+ __reserved_g_0015 : 1,
+ reserved_17b : 8;
+ uint32_t msdu_length : 14,
+ stbc : 1,
+ ipsec_esp : 1,
+ l3_offset : 7,
+ ipsec_ah : 1,
+ l4_offset : 8;
+ uint32_t msdu_number : 8,
+ decap_format : 2,
+ ipv4_proto : 1,
+ ipv6_proto : 1,
+ tcp_proto : 1,
+ udp_proto : 1,
+ ip_frag : 1,
+ tcp_only_ack : 1,
+ da_is_bcast_mcast : 1,
+ toeplitz_hash_sel : 2,
+ ip_fixed_header_valid : 1,
+ ip_extn_header_valid : 1,
+ tcp_udp_header_valid : 1,
+ mesh_control_present : 1,
+ ldpc : 1,
+ ip4_protocol_ip6_next_header : 8;
+ uint32_t vlan_ctag_ci : 16,
+ vlan_stag_ci : 16;
+ uint32_t peer_meta_data : 32;
+ uint32_t user_rssi : 8,
+ pkt_type : 4,
+ sgi : 2,
+ rate_mcs : 4,
+ receive_bandwidth : 3,
+ reception_type : 3,
+ mimo_ss_bitmap : 7,
+ msdu_done_copy : 1;
+ uint32_t flow_id_toeplitz : 32;
+ uint32_t ppdu_start_timestamp_63_32 : 32;
+ uint32_t sw_phy_meta_data : 32;
+ uint32_t ppdu_start_timestamp_31_0 : 32;
+ uint32_t toeplitz_hash_2_or_4 : 32;
+ uint32_t reserved_28a : 16,
+ sa_15_0 : 16;
+ uint32_t sa_47_16 : 32;
+ uint32_t first_mpdu : 1,
+ reserved_30a : 1,
+ mcast_bcast : 1,
+ ast_index_not_found : 1,
+ ast_index_timeout : 1,
+ power_mgmt : 1,
+ non_qos : 1,
+ null_data : 1,
+ mgmt_type : 1,
+ ctrl_type : 1,
+ more_data : 1,
+ eosp : 1,
+ a_msdu_error : 1,
+ reserved_30b : 1,
+ order : 1,
+ wifi_parser_error : 1,
+ overflow_err : 1,
+ msdu_length_err : 1,
+ tcp_udp_chksum_fail : 1,
+ ip_chksum_fail : 1,
+ sa_idx_invalid : 1,
+ da_idx_invalid : 1,
+ amsdu_addr_mismatch : 1,
+ rx_in_tx_decrypt_byp : 1,
+ encrypt_required : 1,
+ directed : 1,
+ buffer_fragment : 1,
+ mpdu_length_err : 1,
+ tkip_mic_err : 1,
+ decrypt_err : 1,
+ unencrypted_frame_err : 1,
+ fcs_err : 1;
+ uint32_t reserved_31a : 10,
+ decrypt_status_code : 3,
+ rx_bitmap_not_updated : 1,
+ reserved_31b : 17,
+ msdu_done : 1;
+#else
+ uint32_t phy_ppdu_id : 16,
+ reserved_0 : 7,
+ sw_frame_group_id : 7,
+ rxpcu_mpdu_filter_in_category : 2;
+ uint32_t reserved_1a : 2,
+ reported_mpdu_length : 14,
+ ip_hdr_chksum : 16;
+ uint32_t cumulative_l3_checksum : 16,
+ cce_classify_not_done_cce_dis : 1,
+ cce_classify_not_done_truncate : 1,
+ cce_super_rule : 6,
+ reserved_2a : 8;
+ uint32_t rule_indication_31_0 : 32;
+ uint32_t ipv6_options_crc : 32;
+ uint32_t l3_type : 16,
+ reserved_5a : 2,
+ sa_offset_valid : 1,
+ da_offset_valid : 1,
+ sa_offset : 6,
+ da_offset : 6;
+ uint32_t rule_indication_63_32 : 32;
+ uint32_t tcp_seq_number : 32;
+ uint32_t tcp_ack_number : 32;
+ uint32_t window_size : 16,
+ reserved_9a : 6,
+ lro_eligible : 1,
+ tcp_flag : 9;
+ uint32_t ip_chksum_fail_copy : 1,
+ fr_ds : 1,
+ last_msdu : 1,
+ first_msdu : 1,
+ l3_header_padding : 2,
+ da_is_mcbc : 1,
+ da_is_valid : 1,
+ sa_is_valid : 1,
+ tid : 4,
+ to_ds : 1,
+ da_idx_timeout : 1,
+ sa_idx_timeout : 1,
+ sa_sw_peer_id : 16;
+ uint32_t da_idx_or_sw_peer_id : 16,
+ sa_idx : 16;
+ uint32_t fragment_flag : 1,
+ vlan_stag_stripped : 1,
+ vlan_ctag_stripped : 1,
+ __reserved_g_0003 : 2,
+ use_ppe : 1,
+ flow_idx : 20,
+ reo_destination_indication : 5,
+ msdu_drop : 1;
+ uint32_t fse_metadata : 32;
+ uint32_t tcp_udp_chksum : 16,
+ cce_metadata : 16;
+ uint32_t cumulative_ip_length : 16,
+ amsdu_parser_error : 1,
+ cce_match : 1,
+ flow_idx_invalid : 1,
+ flow_idx_timeout : 1,
+ msdu_limit_error : 1,
+ tcp_udp_chksum_fail_copy : 1,
+ fisa_timeout : 1,
+ flow_aggregation_continuation : 1,
+ aggregation_count : 8;
+ uint32_t reserved_16a : 24,
+ key_id_octet : 8;
+ uint32_t reserved_17b : 8,
+ __reserved_g_0015 : 1,
+ wds_keep_alive_event : 1,
+ wds_roaming_event : 1,
+ wds_learning_event : 1,
+ multicast_echo : 1,
+ dest_chip_id : 2,
+ intra_bss : 1,
+ priority_valid : 1,
+ service_code : 9,
+ reserved_17a : 6;
+ uint32_t l4_offset : 8,
+ ipsec_ah : 1,
+ l3_offset : 7,
+ ipsec_esp : 1,
+ stbc : 1,
+ msdu_length : 14;
+ uint32_t ip4_protocol_ip6_next_header : 8,
+ ldpc : 1,
+ mesh_control_present : 1,
+ tcp_udp_header_valid : 1,
+ ip_extn_header_valid : 1,
+ ip_fixed_header_valid : 1,
+ toeplitz_hash_sel : 2,
+ da_is_bcast_mcast : 1,
+ tcp_only_ack : 1,
+ ip_frag : 1,
+ udp_proto : 1,
+ tcp_proto : 1,
+ ipv6_proto : 1,
+ ipv4_proto : 1,
+ decap_format : 2,
+ msdu_number : 8;
+ uint32_t vlan_stag_ci : 16,
+ vlan_ctag_ci : 16;
+ uint32_t peer_meta_data : 32;
+ uint32_t msdu_done_copy : 1,
+ mimo_ss_bitmap : 7,
+ reception_type : 3,
+ receive_bandwidth : 3,
+ rate_mcs : 4,
+ sgi : 2,
+ pkt_type : 4,
+ user_rssi : 8;
+ uint32_t flow_id_toeplitz : 32;
+ uint32_t ppdu_start_timestamp_63_32 : 32;
+ uint32_t sw_phy_meta_data : 32;
+ uint32_t ppdu_start_timestamp_31_0 : 32;
+ uint32_t toeplitz_hash_2_or_4 : 32;
+ uint32_t sa_15_0 : 16,
+ reserved_28a : 16;
+ uint32_t sa_47_16 : 32;
+ uint32_t fcs_err : 1,
+ unencrypted_frame_err : 1,
+ decrypt_err : 1,
+ tkip_mic_err : 1,
+ mpdu_length_err : 1,
+ buffer_fragment : 1,
+ directed : 1,
+ encrypt_required : 1,
+ rx_in_tx_decrypt_byp : 1,
+ amsdu_addr_mismatch : 1,
+ da_idx_invalid : 1,
+ sa_idx_invalid : 1,
+ ip_chksum_fail : 1,
+ tcp_udp_chksum_fail : 1,
+ msdu_length_err : 1,
+ overflow_err : 1,
+ wifi_parser_error : 1,
+ order : 1,
+ reserved_30b : 1,
+ a_msdu_error : 1,
+ eosp : 1,
+ more_data : 1,
+ ctrl_type : 1,
+ mgmt_type : 1,
+ null_data : 1,
+ non_qos : 1,
+ power_mgmt : 1,
+ ast_index_timeout : 1,
+ ast_index_not_found : 1,
+ mcast_bcast : 1,
+ reserved_30a : 1,
+ first_mpdu : 1;
+ uint32_t msdu_done : 1,
+ reserved_31b : 17,
+ rx_bitmap_not_updated : 1,
+ decrypt_status_code : 3,
+ reserved_31a : 10;
+#endif
+};
+
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
+#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x00000000
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8
+#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+#define RX_MSDU_END_RESERVED_0_OFFSET 0x00000000
+#define RX_MSDU_END_RESERVED_0_LSB 9
+#define RX_MSDU_END_RESERVED_0_MSB 15
+#define RX_MSDU_END_RESERVED_0_MASK 0x0000fe00
+
+#define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_MSDU_END_PHY_PPDU_ID_LSB 16
+#define RX_MSDU_END_PHY_PPDU_ID_MSB 31
+#define RX_MSDU_END_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x00000004
+#define RX_MSDU_END_IP_HDR_CHKSUM_LSB 0
+#define RX_MSDU_END_IP_HDR_CHKSUM_MSB 15
+#define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff
+
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x00000004
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 16
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 29
+#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff0000
+
+#define RX_MSDU_END_RESERVED_1A_OFFSET 0x00000004
+#define RX_MSDU_END_RESERVED_1A_LSB 30
+#define RX_MSDU_END_RESERVED_1A_MSB 31
+#define RX_MSDU_END_RESERVED_1A_MASK 0xc0000000
+
+#define RX_MSDU_END_RESERVED_2A_OFFSET 0x00000008
+#define RX_MSDU_END_RESERVED_2A_LSB 0
+#define RX_MSDU_END_RESERVED_2A_MSB 7
+#define RX_MSDU_END_RESERVED_2A_MASK 0x000000ff
+
+#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x00000008
+#define RX_MSDU_END_CCE_SUPER_RULE_LSB 8
+#define RX_MSDU_END_CCE_SUPER_RULE_MSB 13
+#define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x00003f00
+
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000
+
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15
+#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000
+
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x00000008
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31
+#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0xffff0000
+
+#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000c
+#define RX_MSDU_END_RULE_INDICATION_31_0_LSB 0
+#define RX_MSDU_END_RULE_INDICATION_31_0_MSB 31
+#define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff
+
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x00000010
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31
+#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0xffffffff
+
+#define RX_MSDU_END_DA_OFFSET_OFFSET 0x00000014
+#define RX_MSDU_END_DA_OFFSET_LSB 0
+#define RX_MSDU_END_DA_OFFSET_MSB 5
+#define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f
+
+#define RX_MSDU_END_SA_OFFSET_OFFSET 0x00000014
+#define RX_MSDU_END_SA_OFFSET_LSB 6
+#define RX_MSDU_END_SA_OFFSET_MSB 11
+#define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc0
+
+#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x00000014
+#define RX_MSDU_END_DA_OFFSET_VALID_LSB 12
+#define RX_MSDU_END_DA_OFFSET_VALID_MSB 12
+#define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x00001000
+
+#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x00000014
+#define RX_MSDU_END_SA_OFFSET_VALID_LSB 13
+#define RX_MSDU_END_SA_OFFSET_VALID_MSB 13
+#define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x00002000
+
+#define RX_MSDU_END_RESERVED_5A_OFFSET 0x00000014
+#define RX_MSDU_END_RESERVED_5A_LSB 14
+#define RX_MSDU_END_RESERVED_5A_MSB 15
+#define RX_MSDU_END_RESERVED_5A_MASK 0x0000c000
+
+#define RX_MSDU_END_L3_TYPE_OFFSET 0x00000014
+#define RX_MSDU_END_L3_TYPE_LSB 16
+#define RX_MSDU_END_L3_TYPE_MSB 31
+#define RX_MSDU_END_L3_TYPE_MASK 0xffff0000
+
+#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x00000018
+#define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0
+#define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31
+#define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0xffffffff
+
+#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000001c
+#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 0
+#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 31
+#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff
+
+#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x00000020
+#define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0
+#define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31
+#define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0xffffffff
+
+#define RX_MSDU_END_TCP_FLAG_OFFSET 0x00000024
+#define RX_MSDU_END_TCP_FLAG_LSB 0
+#define RX_MSDU_END_TCP_FLAG_MSB 8
+#define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff
+
+#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x00000024
+#define RX_MSDU_END_LRO_ELIGIBLE_LSB 9
+#define RX_MSDU_END_LRO_ELIGIBLE_MSB 9
+#define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x00000200
+
+#define RX_MSDU_END_RESERVED_9A_OFFSET 0x00000024
+#define RX_MSDU_END_RESERVED_9A_LSB 10
+#define RX_MSDU_END_RESERVED_9A_MSB 15
+#define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc00
+
+#define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x00000024
+#define RX_MSDU_END_WINDOW_SIZE_LSB 16
+#define RX_MSDU_END_WINDOW_SIZE_MSB 31
+#define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff0000
+
+#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x00000028
+#define RX_MSDU_END_SA_SW_PEER_ID_LSB 0
+#define RX_MSDU_END_SA_SW_PEER_ID_MSB 15
+#define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x0000ffff
+
+#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x00000028
+#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16
+#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16
+#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x00010000
+
+#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x00000028
+#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17
+#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17
+#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x00020000
+
+#define RX_MSDU_END_TO_DS_OFFSET 0x00000028
+#define RX_MSDU_END_TO_DS_LSB 18
+#define RX_MSDU_END_TO_DS_MSB 18
+#define RX_MSDU_END_TO_DS_MASK 0x00040000
+
+#define RX_MSDU_END_TID_OFFSET 0x00000028
+#define RX_MSDU_END_TID_LSB 19
+#define RX_MSDU_END_TID_MSB 22
+#define RX_MSDU_END_TID_MASK 0x00780000
+
+#define RX_MSDU_END_SA_IS_VALID_OFFSET 0x00000028
+#define RX_MSDU_END_SA_IS_VALID_LSB 23
+#define RX_MSDU_END_SA_IS_VALID_MSB 23
+#define RX_MSDU_END_SA_IS_VALID_MASK 0x00800000
+
+#define RX_MSDU_END_DA_IS_VALID_OFFSET 0x00000028
+#define RX_MSDU_END_DA_IS_VALID_LSB 24
+#define RX_MSDU_END_DA_IS_VALID_MSB 24
+#define RX_MSDU_END_DA_IS_VALID_MASK 0x01000000
+
+#define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x00000028
+#define RX_MSDU_END_DA_IS_MCBC_LSB 25
+#define RX_MSDU_END_DA_IS_MCBC_MSB 25
+#define RX_MSDU_END_DA_IS_MCBC_MASK 0x02000000
+
+#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x00000028
+#define RX_MSDU_END_L3_HEADER_PADDING_LSB 26
+#define RX_MSDU_END_L3_HEADER_PADDING_MSB 27
+#define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x0c000000
+
+#define RX_MSDU_END_FIRST_MSDU_OFFSET 0x00000028
+#define RX_MSDU_END_FIRST_MSDU_LSB 28
+#define RX_MSDU_END_FIRST_MSDU_MSB 28
+#define RX_MSDU_END_FIRST_MSDU_MASK 0x10000000
+
+#define RX_MSDU_END_LAST_MSDU_OFFSET 0x00000028
+#define RX_MSDU_END_LAST_MSDU_LSB 29
+#define RX_MSDU_END_LAST_MSDU_MSB 29
+#define RX_MSDU_END_LAST_MSDU_MASK 0x20000000
+
+#define RX_MSDU_END_FR_DS_OFFSET 0x00000028
+#define RX_MSDU_END_FR_DS_LSB 30
+#define RX_MSDU_END_FR_DS_MSB 30
+#define RX_MSDU_END_FR_DS_MASK 0x40000000
+
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x00000028
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31
+#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x80000000
+
+#define RX_MSDU_END_SA_IDX_OFFSET 0x0000002c
+#define RX_MSDU_END_SA_IDX_LSB 0
+#define RX_MSDU_END_SA_IDX_MSB 15
+#define RX_MSDU_END_SA_IDX_MASK 0x0000ffff
+
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 16
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 31
+#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000
+
+#define RX_MSDU_END_MSDU_DROP_OFFSET 0x00000030
+#define RX_MSDU_END_MSDU_DROP_LSB 0
+#define RX_MSDU_END_MSDU_DROP_MSB 0
+#define RX_MSDU_END_MSDU_DROP_MASK 0x00000001
+
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x00000030
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5
+#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x0000003e
+
+#define RX_MSDU_END_FLOW_IDX_OFFSET 0x00000030
+#define RX_MSDU_END_FLOW_IDX_LSB 6
+#define RX_MSDU_END_FLOW_IDX_MSB 25
+#define RX_MSDU_END_FLOW_IDX_MASK 0x03ffffc0
+
+#define RX_MSDU_END_USE_PPE_OFFSET 0x00000030
+#define RX_MSDU_END_USE_PPE_LSB 26
+#define RX_MSDU_END_USE_PPE_MSB 26
+#define RX_MSDU_END_USE_PPE_MASK 0x04000000
+
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x00000030
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29
+#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x20000000
+
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x00000030
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30
+#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x40000000
+
+#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x00000030
+#define RX_MSDU_END_FRAGMENT_FLAG_LSB 31
+#define RX_MSDU_END_FRAGMENT_FLAG_MSB 31
+#define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x80000000
+
+#define RX_MSDU_END_FSE_METADATA_OFFSET 0x00000034
+#define RX_MSDU_END_FSE_METADATA_LSB 0
+#define RX_MSDU_END_FSE_METADATA_MSB 31
+#define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff
+
+#define RX_MSDU_END_CCE_METADATA_OFFSET 0x00000038
+#define RX_MSDU_END_CCE_METADATA_LSB 0
+#define RX_MSDU_END_CCE_METADATA_MSB 15
+#define RX_MSDU_END_CCE_METADATA_MASK 0x0000ffff
+
+#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x00000038
+#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16
+#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31
+#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0xffff0000
+
+#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000003c
+#define RX_MSDU_END_AGGREGATION_COUNT_LSB 0
+#define RX_MSDU_END_AGGREGATION_COUNT_MSB 7
+#define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff
+
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 8
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 8
+#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100
+
+#define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000003c
+#define RX_MSDU_END_FISA_TIMEOUT_LSB 9
+#define RX_MSDU_END_FISA_TIMEOUT_MSB 9
+#define RX_MSDU_END_FISA_TIMEOUT_MASK 0x00000200
+
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000003c
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 10
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 10
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x00000400
+
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000003c
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 11
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 11
+#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x00000800
+
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000003c
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 12
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 12
+#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x00001000
+
+#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000003c
+#define RX_MSDU_END_FLOW_IDX_INVALID_LSB 13
+#define RX_MSDU_END_FLOW_IDX_INVALID_MSB 13
+#define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x00002000
+
+#define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000003c
+#define RX_MSDU_END_CCE_MATCH_LSB 14
+#define RX_MSDU_END_CCE_MATCH_MSB 14
+#define RX_MSDU_END_CCE_MATCH_MASK 0x00004000
+
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000003c
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 15
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 15
+#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x00008000
+
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000003c
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 16
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 31
+#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff0000
+
+#define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x00000040
+#define RX_MSDU_END_KEY_ID_OCTET_LSB 0
+#define RX_MSDU_END_KEY_ID_OCTET_MSB 7
+#define RX_MSDU_END_KEY_ID_OCTET_MASK 0x000000ff
+
+#define RX_MSDU_END_RESERVED_16A_OFFSET 0x00000040
+#define RX_MSDU_END_RESERVED_16A_LSB 8
+#define RX_MSDU_END_RESERVED_16A_MSB 31
+#define RX_MSDU_END_RESERVED_16A_MASK 0xffffff00
+
+#define RX_MSDU_END_RESERVED_17A_OFFSET 0x00000044
+#define RX_MSDU_END_RESERVED_17A_LSB 0
+#define RX_MSDU_END_RESERVED_17A_MSB 5
+#define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f
+
+#define RX_MSDU_END_SERVICE_CODE_OFFSET 0x00000044
+#define RX_MSDU_END_SERVICE_CODE_LSB 6
+#define RX_MSDU_END_SERVICE_CODE_MSB 14
+#define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc0
+
+#define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x00000044
+#define RX_MSDU_END_PRIORITY_VALID_LSB 15
+#define RX_MSDU_END_PRIORITY_VALID_MSB 15
+#define RX_MSDU_END_PRIORITY_VALID_MASK 0x00008000
+
+#define RX_MSDU_END_INTRA_BSS_OFFSET 0x00000044
+#define RX_MSDU_END_INTRA_BSS_LSB 16
+#define RX_MSDU_END_INTRA_BSS_MSB 16
+#define RX_MSDU_END_INTRA_BSS_MASK 0x00010000
+
+#define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x00000044
+#define RX_MSDU_END_DEST_CHIP_ID_LSB 17
+#define RX_MSDU_END_DEST_CHIP_ID_MSB 18
+#define RX_MSDU_END_DEST_CHIP_ID_MASK 0x00060000
+
+#define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x00000044
+#define RX_MSDU_END_MULTICAST_ECHO_LSB 19
+#define RX_MSDU_END_MULTICAST_ECHO_MSB 19
+#define RX_MSDU_END_MULTICAST_ECHO_MASK 0x00080000
+
+#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x00000044
+#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 20
+#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 20
+#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x00100000
+
+#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x00000044
+#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 21
+#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 21
+#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x00200000
+
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x00000044
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 22
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 22
+#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x00400000
+
+#define RX_MSDU_END_RESERVED_17B_OFFSET 0x00000044
+#define RX_MSDU_END_RESERVED_17B_LSB 24
+#define RX_MSDU_END_RESERVED_17B_MSB 31
+#define RX_MSDU_END_RESERVED_17B_MASK 0xff000000
+
+#define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x00000048
+#define RX_MSDU_END_MSDU_LENGTH_LSB 0
+#define RX_MSDU_END_MSDU_LENGTH_MSB 13
+#define RX_MSDU_END_MSDU_LENGTH_MASK 0x00003fff
+
+#define RX_MSDU_END_STBC_OFFSET 0x00000048
+#define RX_MSDU_END_STBC_LSB 14
+#define RX_MSDU_END_STBC_MSB 14
+#define RX_MSDU_END_STBC_MASK 0x00004000
+
+#define RX_MSDU_END_IPSEC_ESP_OFFSET 0x00000048
+#define RX_MSDU_END_IPSEC_ESP_LSB 15
+#define RX_MSDU_END_IPSEC_ESP_MSB 15
+#define RX_MSDU_END_IPSEC_ESP_MASK 0x00008000
+
+#define RX_MSDU_END_L3_OFFSET_OFFSET 0x00000048
+#define RX_MSDU_END_L3_OFFSET_LSB 16
+#define RX_MSDU_END_L3_OFFSET_MSB 22
+#define RX_MSDU_END_L3_OFFSET_MASK 0x007f0000
+
+#define RX_MSDU_END_IPSEC_AH_OFFSET 0x00000048
+#define RX_MSDU_END_IPSEC_AH_LSB 23
+#define RX_MSDU_END_IPSEC_AH_MSB 23
+#define RX_MSDU_END_IPSEC_AH_MASK 0x00800000
+
+#define RX_MSDU_END_L4_OFFSET_OFFSET 0x00000048
+#define RX_MSDU_END_L4_OFFSET_LSB 24
+#define RX_MSDU_END_L4_OFFSET_MSB 31
+#define RX_MSDU_END_L4_OFFSET_MASK 0xff000000
+
+#define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000004c
+#define RX_MSDU_END_MSDU_NUMBER_LSB 0
+#define RX_MSDU_END_MSDU_NUMBER_MSB 7
+#define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff
+
+#define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000004c
+#define RX_MSDU_END_DECAP_FORMAT_LSB 8
+#define RX_MSDU_END_DECAP_FORMAT_MSB 9
+#define RX_MSDU_END_DECAP_FORMAT_MASK 0x00000300
+
+#define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000004c
+#define RX_MSDU_END_IPV4_PROTO_LSB 10
+#define RX_MSDU_END_IPV4_PROTO_MSB 10
+#define RX_MSDU_END_IPV4_PROTO_MASK 0x00000400
+
+#define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000004c
+#define RX_MSDU_END_IPV6_PROTO_LSB 11
+#define RX_MSDU_END_IPV6_PROTO_MSB 11
+#define RX_MSDU_END_IPV6_PROTO_MASK 0x00000800
+
+#define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000004c
+#define RX_MSDU_END_TCP_PROTO_LSB 12
+#define RX_MSDU_END_TCP_PROTO_MSB 12
+#define RX_MSDU_END_TCP_PROTO_MASK 0x00001000
+
+#define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000004c
+#define RX_MSDU_END_UDP_PROTO_LSB 13
+#define RX_MSDU_END_UDP_PROTO_MSB 13
+#define RX_MSDU_END_UDP_PROTO_MASK 0x00002000
+
+#define RX_MSDU_END_IP_FRAG_OFFSET 0x0000004c
+#define RX_MSDU_END_IP_FRAG_LSB 14
+#define RX_MSDU_END_IP_FRAG_MSB 14
+#define RX_MSDU_END_IP_FRAG_MASK 0x00004000
+
+#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000004c
+#define RX_MSDU_END_TCP_ONLY_ACK_LSB 15
+#define RX_MSDU_END_TCP_ONLY_ACK_MSB 15
+#define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x00008000
+
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000004c
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 16
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 16
+#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x00010000
+
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000004c
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 17
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 18
+#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x00060000
+
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000004c
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 19
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 19
+#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x00080000
+
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000004c
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 20
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 20
+#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x00100000
+
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000004c
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 21
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 21
+#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x00200000
+
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000004c
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 22
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 22
+#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x00400000
+
+#define RX_MSDU_END_LDPC_OFFSET 0x0000004c
+#define RX_MSDU_END_LDPC_LSB 23
+#define RX_MSDU_END_LDPC_MSB 23
+#define RX_MSDU_END_LDPC_MASK 0x00800000
+
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000004c
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31
+#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000
+
+#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x00000050
+#define RX_MSDU_END_VLAN_CTAG_CI_LSB 0
+#define RX_MSDU_END_VLAN_CTAG_CI_MSB 15
+#define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x0000ffff
+
+#define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x00000050
+#define RX_MSDU_END_VLAN_STAG_CI_LSB 16
+#define RX_MSDU_END_VLAN_STAG_CI_MSB 31
+#define RX_MSDU_END_VLAN_STAG_CI_MASK 0xffff0000
+
+#define RX_MSDU_END_PEER_META_DATA_OFFSET 0x00000054
+#define RX_MSDU_END_PEER_META_DATA_LSB 0
+#define RX_MSDU_END_PEER_META_DATA_MSB 31
+#define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff
+
+#define RX_MSDU_END_USER_RSSI_OFFSET 0x00000058
+#define RX_MSDU_END_USER_RSSI_LSB 0
+#define RX_MSDU_END_USER_RSSI_MSB 7
+#define RX_MSDU_END_USER_RSSI_MASK 0x000000ff
+
+#define RX_MSDU_END_PKT_TYPE_OFFSET 0x00000058
+#define RX_MSDU_END_PKT_TYPE_LSB 8
+#define RX_MSDU_END_PKT_TYPE_MSB 11
+#define RX_MSDU_END_PKT_TYPE_MASK 0x00000f00
+
+#define RX_MSDU_END_SGI_OFFSET 0x00000058
+#define RX_MSDU_END_SGI_LSB 12
+#define RX_MSDU_END_SGI_MSB 13
+#define RX_MSDU_END_SGI_MASK 0x00003000
+
+#define RX_MSDU_END_RATE_MCS_OFFSET 0x00000058
+#define RX_MSDU_END_RATE_MCS_LSB 14
+#define RX_MSDU_END_RATE_MCS_MSB 17
+#define RX_MSDU_END_RATE_MCS_MASK 0x0003c000
+
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x00000058
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20
+#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x001c0000
+
+#define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x00000058
+#define RX_MSDU_END_RECEPTION_TYPE_LSB 21
+#define RX_MSDU_END_RECEPTION_TYPE_MSB 23
+#define RX_MSDU_END_RECEPTION_TYPE_MASK 0x00e00000
+
+#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x00000058
+#define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24
+#define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30
+#define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x7f000000
+
+#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x00000058
+#define RX_MSDU_END_MSDU_DONE_COPY_LSB 31
+#define RX_MSDU_END_MSDU_DONE_COPY_MSB 31
+#define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x80000000
+
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000005c
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 0
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 31
+#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff
+
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000060
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff
+
+#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x00000064
+#define RX_MSDU_END_SW_PHY_META_DATA_LSB 0
+#define RX_MSDU_END_SW_PHY_META_DATA_MSB 31
+#define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff
+
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000068
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31
+#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff
+
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000006c
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 0
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 31
+#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff
+
+#define RX_MSDU_END_RESERVED_28A_OFFSET 0x00000070
+#define RX_MSDU_END_RESERVED_28A_LSB 0
+#define RX_MSDU_END_RESERVED_28A_MSB 15
+#define RX_MSDU_END_RESERVED_28A_MASK 0x0000ffff
+
+#define RX_MSDU_END_SA_15_0_OFFSET 0x00000070
+#define RX_MSDU_END_SA_15_0_LSB 16
+#define RX_MSDU_END_SA_15_0_MSB 31
+#define RX_MSDU_END_SA_15_0_MASK 0xffff0000
+
+#define RX_MSDU_END_SA_47_16_OFFSET 0x00000074
+#define RX_MSDU_END_SA_47_16_LSB 0
+#define RX_MSDU_END_SA_47_16_MSB 31
+#define RX_MSDU_END_SA_47_16_MASK 0xffffffff
+
+#define RX_MSDU_END_FIRST_MPDU_OFFSET 0x00000078
+#define RX_MSDU_END_FIRST_MPDU_LSB 0
+#define RX_MSDU_END_FIRST_MPDU_MSB 0
+#define RX_MSDU_END_FIRST_MPDU_MASK 0x00000001
+
+#define RX_MSDU_END_RESERVED_30A_OFFSET 0x00000078
+#define RX_MSDU_END_RESERVED_30A_LSB 1
+#define RX_MSDU_END_RESERVED_30A_MSB 1
+#define RX_MSDU_END_RESERVED_30A_MASK 0x00000002
+
+#define RX_MSDU_END_MCAST_BCAST_OFFSET 0x00000078
+#define RX_MSDU_END_MCAST_BCAST_LSB 2
+#define RX_MSDU_END_MCAST_BCAST_MSB 2
+#define RX_MSDU_END_MCAST_BCAST_MASK 0x00000004
+
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x00000078
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3
+#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x00000008
+
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x00000078
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4
+#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x00000010
+
+#define RX_MSDU_END_POWER_MGMT_OFFSET 0x00000078
+#define RX_MSDU_END_POWER_MGMT_LSB 5
+#define RX_MSDU_END_POWER_MGMT_MSB 5
+#define RX_MSDU_END_POWER_MGMT_MASK 0x00000020
+
+#define RX_MSDU_END_NON_QOS_OFFSET 0x00000078
+#define RX_MSDU_END_NON_QOS_LSB 6
+#define RX_MSDU_END_NON_QOS_MSB 6
+#define RX_MSDU_END_NON_QOS_MASK 0x00000040
+
+#define RX_MSDU_END_NULL_DATA_OFFSET 0x00000078
+#define RX_MSDU_END_NULL_DATA_LSB 7
+#define RX_MSDU_END_NULL_DATA_MSB 7
+#define RX_MSDU_END_NULL_DATA_MASK 0x00000080
+
+#define RX_MSDU_END_MGMT_TYPE_OFFSET 0x00000078
+#define RX_MSDU_END_MGMT_TYPE_LSB 8
+#define RX_MSDU_END_MGMT_TYPE_MSB 8
+#define RX_MSDU_END_MGMT_TYPE_MASK 0x00000100
+
+#define RX_MSDU_END_CTRL_TYPE_OFFSET 0x00000078
+#define RX_MSDU_END_CTRL_TYPE_LSB 9
+#define RX_MSDU_END_CTRL_TYPE_MSB 9
+#define RX_MSDU_END_CTRL_TYPE_MASK 0x00000200
+
+#define RX_MSDU_END_MORE_DATA_OFFSET 0x00000078
+#define RX_MSDU_END_MORE_DATA_LSB 10
+#define RX_MSDU_END_MORE_DATA_MSB 10
+#define RX_MSDU_END_MORE_DATA_MASK 0x00000400
+
+#define RX_MSDU_END_EOSP_OFFSET 0x00000078
+#define RX_MSDU_END_EOSP_LSB 11
+#define RX_MSDU_END_EOSP_MSB 11
+#define RX_MSDU_END_EOSP_MASK 0x00000800
+
+#define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x00000078
+#define RX_MSDU_END_A_MSDU_ERROR_LSB 12
+#define RX_MSDU_END_A_MSDU_ERROR_MSB 12
+#define RX_MSDU_END_A_MSDU_ERROR_MASK 0x00001000
+
+#define RX_MSDU_END_RESERVED_30B_OFFSET 0x00000078
+#define RX_MSDU_END_RESERVED_30B_LSB 13
+#define RX_MSDU_END_RESERVED_30B_MSB 13
+#define RX_MSDU_END_RESERVED_30B_MASK 0x00002000
+
+#define RX_MSDU_END_ORDER_OFFSET 0x00000078
+#define RX_MSDU_END_ORDER_LSB 14
+#define RX_MSDU_END_ORDER_MSB 14
+#define RX_MSDU_END_ORDER_MASK 0x00004000
+
+#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x00000078
+#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15
+#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15
+#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x00008000
+
+#define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x00000078
+#define RX_MSDU_END_OVERFLOW_ERR_LSB 16
+#define RX_MSDU_END_OVERFLOW_ERR_MSB 16
+#define RX_MSDU_END_OVERFLOW_ERR_MASK 0x00010000
+
+#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x00000078
+#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17
+#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17
+#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x00020000
+
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18
+#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000
+
+#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x00000078
+#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19
+#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19
+#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x00080000
+
+#define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x00000078
+#define RX_MSDU_END_SA_IDX_INVALID_LSB 20
+#define RX_MSDU_END_SA_IDX_INVALID_MSB 20
+#define RX_MSDU_END_SA_IDX_INVALID_MASK 0x00100000
+
+#define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x00000078
+#define RX_MSDU_END_DA_IDX_INVALID_LSB 21
+#define RX_MSDU_END_DA_IDX_INVALID_MSB 21
+#define RX_MSDU_END_DA_IDX_INVALID_MASK 0x00200000
+
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x00000078
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22
+#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x00400000
+
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000078
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23
+#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000
+
+#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x00000078
+#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24
+#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24
+#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x01000000
+
+#define RX_MSDU_END_DIRECTED_OFFSET 0x00000078
+#define RX_MSDU_END_DIRECTED_LSB 25
+#define RX_MSDU_END_DIRECTED_MSB 25
+#define RX_MSDU_END_DIRECTED_MASK 0x02000000
+
+#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x00000078
+#define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26
+#define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26
+#define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x04000000
+
+#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x00000078
+#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27
+#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27
+#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x08000000
+
+#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x00000078
+#define RX_MSDU_END_TKIP_MIC_ERR_LSB 28
+#define RX_MSDU_END_TKIP_MIC_ERR_MSB 28
+#define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x10000000
+
+#define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x00000078
+#define RX_MSDU_END_DECRYPT_ERR_LSB 29
+#define RX_MSDU_END_DECRYPT_ERR_MSB 29
+#define RX_MSDU_END_DECRYPT_ERR_MASK 0x20000000
+
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000078
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30
+#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x40000000
+
+#define RX_MSDU_END_FCS_ERR_OFFSET 0x00000078
+#define RX_MSDU_END_FCS_ERR_LSB 31
+#define RX_MSDU_END_FCS_ERR_MSB 31
+#define RX_MSDU_END_FCS_ERR_MASK 0x80000000
+
+#define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000007c
+#define RX_MSDU_END_RESERVED_31A_LSB 0
+#define RX_MSDU_END_RESERVED_31A_MSB 9
+#define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff
+
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000007c
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 10
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 12
+#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c00
+
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000007c
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 13
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 13
+#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x00002000
+
+#define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000007c
+#define RX_MSDU_END_RESERVED_31B_LSB 14
+#define RX_MSDU_END_RESERVED_31B_MSB 30
+#define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc000
+
+#define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000007c
+#define RX_MSDU_END_MSDU_DONE_LSB 31
+#define RX_MSDU_END_MSDU_DONE_MSB 31
+#define RX_MSDU_END_MSDU_DONE_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_msdu_ext_desc_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_ext_desc_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..3fc24d531259a9036968c22ccb3c253d85f0bfc5
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_ext_desc_info.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MSDU_EXT_DESC_INFO_H_
+#define _RX_MSDU_EXT_DESC_INFO_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1
+
+struct rx_msdu_ext_desc_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t reo_destination_indication : 5,
+ service_code : 9,
+ priority_valid : 1,
+ data_offset : 12,
+ src_link_id : 3,
+ reserved_0a : 2;
+#else
+ uint32_t reserved_0a : 2,
+ src_link_id : 3,
+ data_offset : 12,
+ priority_valid : 1,
+ service_code : 9,
+ reo_destination_indication : 5;
+#endif
+};
+
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13
+#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0
+
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14
+#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000
+
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26
+#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000
+
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29
+#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000
+
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31
+#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_msdu_link.h b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_link.h
new file mode 100644
index 0000000000000000000000000000000000000000..7506bfd60465a2a55cc7175379f2c29b29529808
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_link.h
@@ -0,0 +1,917 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MSDU_LINK_H_
+#define _RX_MSDU_LINK_H_
+
+#include "uniform_descriptor_header.h"
+#include "buffer_addr_info.h"
+#include "rx_msdu_details.h"
+#define NUM_OF_DWORDS_RX_MSDU_LINK 32
+
+struct rx_msdu_link {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct uniform_descriptor_header descriptor_header;
+ struct buffer_addr_info next_msdu_link_desc_addr_info;
+ uint32_t receive_queue_number : 16,
+ first_rx_msdu_link_struct : 1,
+ reserved_3a : 15;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_63_32 : 32;
+ uint32_t pn_95_64 : 32;
+ uint32_t pn_127_96 : 32;
+ struct rx_msdu_details msdu_0;
+ struct rx_msdu_details msdu_1;
+ struct rx_msdu_details msdu_2;
+ struct rx_msdu_details msdu_3;
+ struct rx_msdu_details msdu_4;
+ struct rx_msdu_details msdu_5;
+#else
+ struct uniform_descriptor_header descriptor_header;
+ struct buffer_addr_info next_msdu_link_desc_addr_info;
+ uint32_t reserved_3a : 15,
+ first_rx_msdu_link_struct : 1,
+ receive_queue_number : 16;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_63_32 : 32;
+ uint32_t pn_95_64 : 32;
+ uint32_t pn_127_96 : 32;
+ struct rx_msdu_details msdu_0;
+ struct rx_msdu_details msdu_1;
+ struct rx_msdu_details msdu_2;
+ struct rx_msdu_details msdu_3;
+ struct rx_msdu_details msdu_4;
+ struct rx_msdu_details msdu_5;
+#endif
+};
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
+
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
+#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c
+#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_LSB 0
+#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MSB 15
+#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff
+
+#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c
+#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_LSB 16
+#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MSB 16
+#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000
+
+#define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c
+#define RX_MSDU_LINK_RESERVED_3A_LSB 17
+#define RX_MSDU_LINK_RESERVED_3A_MSB 31
+#define RX_MSDU_LINK_RESERVED_3A_MASK 0xfffe0000
+
+#define RX_MSDU_LINK_PN_31_0_OFFSET 0x00000010
+#define RX_MSDU_LINK_PN_31_0_LSB 0
+#define RX_MSDU_LINK_PN_31_0_MSB 31
+#define RX_MSDU_LINK_PN_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_PN_63_32_OFFSET 0x00000014
+#define RX_MSDU_LINK_PN_63_32_LSB 0
+#define RX_MSDU_LINK_PN_63_32_MSB 31
+#define RX_MSDU_LINK_PN_63_32_MASK 0xffffffff
+
+#define RX_MSDU_LINK_PN_95_64_OFFSET 0x00000018
+#define RX_MSDU_LINK_PN_95_64_LSB 0
+#define RX_MSDU_LINK_PN_95_64_MSB 31
+#define RX_MSDU_LINK_PN_95_64_MASK 0xffffffff
+
+#define RX_MSDU_LINK_PN_127_96_OFFSET 0x0000001c
+#define RX_MSDU_LINK_PN_127_96_LSB 0
+#define RX_MSDU_LINK_PN_127_96_MSB 31
+#define RX_MSDU_LINK_PN_127_96_MASK 0xffffffff
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31
+#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000
+
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
+#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31
+#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000
+
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
+#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31
+#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000
+
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
+#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31
+#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000
+
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
+#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31
+#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000
+
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
+#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31
+#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000
+
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31
+#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_msdu_start.h b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_start.h
new file mode 100644
index 0000000000000000000000000000000000000000..6dbba779511559334b13ae66949381408ff18842
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_msdu_start.h
@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_MSDU_START_H_
+#define _RX_MSDU_START_H_
+
+#define NUM_OF_DWORDS_RX_MSDU_START 10
+
+struct rx_msdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t rxpcu_mpdu_filter_in_category : 2,
+ sw_frame_group_id : 7,
+ reserved_0 : 7,
+ phy_ppdu_id : 16;
+ uint32_t msdu_length : 14,
+ stbc : 1,
+ ipsec_esp : 1,
+ l3_offset : 7,
+ ipsec_ah : 1,
+ l4_offset : 8;
+ uint32_t msdu_number : 8,
+ decap_format : 2,
+ ipv4_proto : 1,
+ ipv6_proto : 1,
+ tcp_proto : 1,
+ udp_proto : 1,
+ ip_frag : 1,
+ tcp_only_ack : 1,
+ da_is_bcast_mcast : 1,
+ toeplitz_hash_sel : 2,
+ ip_fixed_header_valid : 1,
+ ip_extn_header_valid : 1,
+ tcp_udp_header_valid : 1,
+ mesh_control_present : 1,
+ ldpc : 1,
+ ip4_protocol_ip6_next_header : 8;
+ uint32_t toeplitz_hash_2_or_4 : 32;
+ uint32_t flow_id_toeplitz : 32;
+ uint32_t user_rssi : 8,
+ pkt_type : 4,
+ sgi : 2,
+ rate_mcs : 4,
+ receive_bandwidth : 3,
+ reception_type : 3,
+ mimo_ss_bitmap : 8;
+ uint32_t ppdu_start_timestamp_31_0 : 32;
+ uint32_t ppdu_start_timestamp_63_32 : 32;
+ uint32_t sw_phy_meta_data : 32;
+ uint32_t vlan_ctag_ci : 16,
+ vlan_stag_ci : 16;
+#else
+ uint32_t phy_ppdu_id : 16,
+ reserved_0 : 7,
+ sw_frame_group_id : 7,
+ rxpcu_mpdu_filter_in_category : 2;
+ uint32_t l4_offset : 8,
+ ipsec_ah : 1,
+ l3_offset : 7,
+ ipsec_esp : 1,
+ stbc : 1,
+ msdu_length : 14;
+ uint32_t ip4_protocol_ip6_next_header : 8,
+ ldpc : 1,
+ mesh_control_present : 1,
+ tcp_udp_header_valid : 1,
+ ip_extn_header_valid : 1,
+ ip_fixed_header_valid : 1,
+ toeplitz_hash_sel : 2,
+ da_is_bcast_mcast : 1,
+ tcp_only_ack : 1,
+ ip_frag : 1,
+ udp_proto : 1,
+ tcp_proto : 1,
+ ipv6_proto : 1,
+ ipv4_proto : 1,
+ decap_format : 2,
+ msdu_number : 8;
+ uint32_t toeplitz_hash_2_or_4 : 32;
+ uint32_t flow_id_toeplitz : 32;
+ uint32_t mimo_ss_bitmap : 8,
+ reception_type : 3,
+ receive_bandwidth : 3,
+ rate_mcs : 4,
+ sgi : 2,
+ pkt_type : 4,
+ user_rssi : 8;
+ uint32_t ppdu_start_timestamp_31_0 : 32;
+ uint32_t ppdu_start_timestamp_63_32 : 32;
+ uint32_t sw_phy_meta_data : 32;
+ uint32_t vlan_stag_ci : 16,
+ vlan_ctag_ci : 16;
+#endif
+};
+
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
+#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x00000000
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8
+#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+#define RX_MSDU_START_RESERVED_0_OFFSET 0x00000000
+#define RX_MSDU_START_RESERVED_0_LSB 9
+#define RX_MSDU_START_RESERVED_0_MSB 15
+#define RX_MSDU_START_RESERVED_0_MASK 0x0000fe00
+
+#define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_MSDU_START_PHY_PPDU_ID_LSB 16
+#define RX_MSDU_START_PHY_PPDU_ID_MSB 31
+#define RX_MSDU_START_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x00000004
+#define RX_MSDU_START_MSDU_LENGTH_LSB 0
+#define RX_MSDU_START_MSDU_LENGTH_MSB 13
+#define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff
+
+#define RX_MSDU_START_STBC_OFFSET 0x00000004
+#define RX_MSDU_START_STBC_LSB 14
+#define RX_MSDU_START_STBC_MSB 14
+#define RX_MSDU_START_STBC_MASK 0x00004000
+
+#define RX_MSDU_START_IPSEC_ESP_OFFSET 0x00000004
+#define RX_MSDU_START_IPSEC_ESP_LSB 15
+#define RX_MSDU_START_IPSEC_ESP_MSB 15
+#define RX_MSDU_START_IPSEC_ESP_MASK 0x00008000
+
+#define RX_MSDU_START_L3_OFFSET_OFFSET 0x00000004
+#define RX_MSDU_START_L3_OFFSET_LSB 16
+#define RX_MSDU_START_L3_OFFSET_MSB 22
+#define RX_MSDU_START_L3_OFFSET_MASK 0x007f0000
+
+#define RX_MSDU_START_IPSEC_AH_OFFSET 0x00000004
+#define RX_MSDU_START_IPSEC_AH_LSB 23
+#define RX_MSDU_START_IPSEC_AH_MSB 23
+#define RX_MSDU_START_IPSEC_AH_MASK 0x00800000
+
+#define RX_MSDU_START_L4_OFFSET_OFFSET 0x00000004
+#define RX_MSDU_START_L4_OFFSET_LSB 24
+#define RX_MSDU_START_L4_OFFSET_MSB 31
+#define RX_MSDU_START_L4_OFFSET_MASK 0xff000000
+
+#define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x00000008
+#define RX_MSDU_START_MSDU_NUMBER_LSB 0
+#define RX_MSDU_START_MSDU_NUMBER_MSB 7
+#define RX_MSDU_START_MSDU_NUMBER_MASK 0x000000ff
+
+#define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x00000008
+#define RX_MSDU_START_DECAP_FORMAT_LSB 8
+#define RX_MSDU_START_DECAP_FORMAT_MSB 9
+#define RX_MSDU_START_DECAP_FORMAT_MASK 0x00000300
+
+#define RX_MSDU_START_IPV4_PROTO_OFFSET 0x00000008
+#define RX_MSDU_START_IPV4_PROTO_LSB 10
+#define RX_MSDU_START_IPV4_PROTO_MSB 10
+#define RX_MSDU_START_IPV4_PROTO_MASK 0x00000400
+
+#define RX_MSDU_START_IPV6_PROTO_OFFSET 0x00000008
+#define RX_MSDU_START_IPV6_PROTO_LSB 11
+#define RX_MSDU_START_IPV6_PROTO_MSB 11
+#define RX_MSDU_START_IPV6_PROTO_MASK 0x00000800
+
+#define RX_MSDU_START_TCP_PROTO_OFFSET 0x00000008
+#define RX_MSDU_START_TCP_PROTO_LSB 12
+#define RX_MSDU_START_TCP_PROTO_MSB 12
+#define RX_MSDU_START_TCP_PROTO_MASK 0x00001000
+
+#define RX_MSDU_START_UDP_PROTO_OFFSET 0x00000008
+#define RX_MSDU_START_UDP_PROTO_LSB 13
+#define RX_MSDU_START_UDP_PROTO_MSB 13
+#define RX_MSDU_START_UDP_PROTO_MASK 0x00002000
+
+#define RX_MSDU_START_IP_FRAG_OFFSET 0x00000008
+#define RX_MSDU_START_IP_FRAG_LSB 14
+#define RX_MSDU_START_IP_FRAG_MSB 14
+#define RX_MSDU_START_IP_FRAG_MASK 0x00004000
+
+#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x00000008
+#define RX_MSDU_START_TCP_ONLY_ACK_LSB 15
+#define RX_MSDU_START_TCP_ONLY_ACK_MSB 15
+#define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x00008000
+
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x00000008
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16
+#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x00010000
+
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x00000008
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18
+#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x00060000
+
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x00000008
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19
+#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x00080000
+
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x00000008
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20
+#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x00100000
+
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x00000008
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21
+#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x00200000
+
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x00000008
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22
+#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x00400000
+
+#define RX_MSDU_START_LDPC_OFFSET 0x00000008
+#define RX_MSDU_START_LDPC_LSB 23
+#define RX_MSDU_START_LDPC_MSB 23
+#define RX_MSDU_START_LDPC_MASK 0x00800000
+
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x00000008
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31
+#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000
+
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000c
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 0
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 31
+#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff
+
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x00000010
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31
+#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0xffffffff
+
+#define RX_MSDU_START_USER_RSSI_OFFSET 0x00000014
+#define RX_MSDU_START_USER_RSSI_LSB 0
+#define RX_MSDU_START_USER_RSSI_MSB 7
+#define RX_MSDU_START_USER_RSSI_MASK 0x000000ff
+
+#define RX_MSDU_START_PKT_TYPE_OFFSET 0x00000014
+#define RX_MSDU_START_PKT_TYPE_LSB 8
+#define RX_MSDU_START_PKT_TYPE_MSB 11
+#define RX_MSDU_START_PKT_TYPE_MASK 0x00000f00
+
+#define RX_MSDU_START_SGI_OFFSET 0x00000014
+#define RX_MSDU_START_SGI_LSB 12
+#define RX_MSDU_START_SGI_MSB 13
+#define RX_MSDU_START_SGI_MASK 0x00003000
+
+#define RX_MSDU_START_RATE_MCS_OFFSET 0x00000014
+#define RX_MSDU_START_RATE_MCS_LSB 14
+#define RX_MSDU_START_RATE_MCS_MSB 17
+#define RX_MSDU_START_RATE_MCS_MASK 0x0003c000
+
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x00000014
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 18
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 20
+#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c0000
+
+#define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x00000014
+#define RX_MSDU_START_RECEPTION_TYPE_LSB 21
+#define RX_MSDU_START_RECEPTION_TYPE_MSB 23
+#define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e00000
+
+#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x00000014
+#define RX_MSDU_START_MIMO_SS_BITMAP_LSB 24
+#define RX_MSDU_START_MIMO_SS_BITMAP_MSB 31
+#define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff000000
+
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000018
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff
+
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000001c
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 0
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 31
+#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff
+
+#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x00000020
+#define RX_MSDU_START_SW_PHY_META_DATA_LSB 0
+#define RX_MSDU_START_SW_PHY_META_DATA_MSB 31
+#define RX_MSDU_START_SW_PHY_META_DATA_MASK 0xffffffff
+
+#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x00000024
+#define RX_MSDU_START_VLAN_CTAG_CI_LSB 0
+#define RX_MSDU_START_VLAN_CTAG_CI_MSB 15
+#define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff
+
+#define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x00000024
+#define RX_MSDU_START_VLAN_STAG_CI_LSB 16
+#define RX_MSDU_START_VLAN_STAG_CI_MSB 31
+#define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_ack_report.h b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_ack_report.h
new file mode 100644
index 0000000000000000000000000000000000000000..91bf124633865a289ef3586ce4b54d6e65767d91
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_ack_report.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_PPDU_ACK_REPORT_H_
+#define _RX_PPDU_ACK_REPORT_H_
+
+#include "ack_report.h"
+#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 1
+
+struct rx_ppdu_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct ack_report ack_report_details;
+#else
+ struct ack_report ack_report_details;
+#endif
+};
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x0000000f
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x000000f0
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x00000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x00000100
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x00000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x0000fe00
+
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x00000000
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31
+#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_end_user_stats.h b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_end_user_stats.h
new file mode 100644
index 0000000000000000000000000000000000000000..e08c0dbe0e0fa3d4a455f668d68b2b7593d49fb7
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_end_user_stats.h
@@ -0,0 +1,703 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_PPDU_END_USER_STATS_H_
+#define _RX_PPDU_END_USER_STATS_H_
+
+#include "rx_rxpcu_classification_overview.h"
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30
+
+struct rx_ppdu_end_user_stats {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct rx_rxpcu_classification_overview rxpcu_classification_details;
+ uint32_t sta_full_aid : 13,
+ mcs : 4,
+ nss : 3,
+ expected_response_ack_or_ba : 1,
+ reserved_1a : 11;
+ uint32_t sw_peer_id : 16,
+ mpdu_cnt_fcs_err : 11,
+ sw2rxdma0_buf_source_used : 1,
+ fw2rxdma_pmac0_buf_source_used : 1,
+ sw2rxdma1_buf_source_used : 1,
+ sw2rxdma_exception_buf_source_used : 1,
+ fw2rxdma_pmac1_buf_source_used : 1;
+ uint32_t mpdu_cnt_fcs_ok : 11,
+ frame_control_info_valid : 1,
+ qos_control_info_valid : 1,
+ ht_control_info_valid : 1,
+ data_sequence_control_info_valid : 1,
+ ht_control_info_null_valid : 1,
+ rxdma2fw_pmac1_ring_used : 1,
+ rxdma2reo_ring_used : 1,
+ rxdma2fw_pmac0_ring_used : 1,
+ rxdma2sw_ring_used : 1,
+ rxdma_release_ring_used : 1,
+ ht_control_field_pkt_type : 4,
+ rxdma2reo_remote0_ring_used : 1,
+ rxdma2reo_remote1_ring_used : 1,
+ reserved_3b : 5;
+ uint32_t ast_index : 16,
+ frame_control_field : 16;
+ uint32_t first_data_seq_ctrl : 16,
+ qos_control_field : 16;
+ uint32_t ht_control_field : 32;
+ uint32_t fcs_ok_bitmap_31_0 : 32;
+ uint32_t fcs_ok_bitmap_63_32 : 32;
+ uint32_t udp_msdu_count : 16,
+ tcp_msdu_count : 16;
+ uint32_t other_msdu_count : 16,
+ tcp_ack_msdu_count : 16;
+ uint32_t sw_response_reference_ptr : 32;
+ uint32_t received_qos_data_tid_bitmap : 16,
+ received_qos_data_tid_eosp_bitmap : 16;
+ uint32_t qosctrl_15_8_tid0 : 8,
+ qosctrl_15_8_tid1 : 8,
+ qosctrl_15_8_tid2 : 8,
+ qosctrl_15_8_tid3 : 8;
+ uint32_t qosctrl_15_8_tid4 : 8,
+ qosctrl_15_8_tid5 : 8,
+ qosctrl_15_8_tid6 : 8,
+ qosctrl_15_8_tid7 : 8;
+ uint32_t qosctrl_15_8_tid8 : 8,
+ qosctrl_15_8_tid9 : 8,
+ qosctrl_15_8_tid10 : 8,
+ qosctrl_15_8_tid11 : 8;
+ uint32_t qosctrl_15_8_tid12 : 8,
+ qosctrl_15_8_tid13 : 8,
+ qosctrl_15_8_tid14 : 8,
+ qosctrl_15_8_tid15 : 8;
+ uint32_t mpdu_ok_byte_count : 25,
+ ampdu_delim_ok_count_6_0 : 7;
+ uint32_t ampdu_delim_err_count : 25,
+ ampdu_delim_ok_count_13_7 : 7;
+ uint32_t mpdu_err_byte_count : 25,
+ ampdu_delim_ok_count_20_14 : 7;
+ uint32_t non_consecutive_delimiter_err : 16,
+ retried_msdu_count : 16;
+ uint32_t ht_control_null_field : 32;
+ uint32_t sw_response_reference_ptr_ext : 32;
+ uint32_t corrupted_due_to_fifo_delay : 1,
+ frame_control_info_null_valid : 1,
+ frame_control_field_null : 16,
+ retried_mpdu_count : 11,
+ reserved_23a : 3;
+ uint32_t rxpcu_mpdu_filter_in_category : 2,
+ sw_frame_group_id : 7,
+ reserved_24a : 4,
+ frame_control_info_mgmt_ctrl_valid : 1,
+ mac_addr_ad2_valid : 1,
+ mcast_bcast : 1,
+ frame_control_field_mgmt_ctrl : 16;
+ uint32_t user_ppdu_len : 24,
+ reserved_25a : 8;
+ uint32_t mac_addr_ad2_31_0 : 32;
+ uint32_t mac_addr_ad2_47_32 : 16,
+ amsdu_msdu_count : 16;
+ uint32_t non_amsdu_msdu_count : 16,
+ ucast_msdu_count : 16;
+ uint32_t bcast_msdu_count : 16,
+ mcast_bcast_msdu_count : 16;
+#else
+ struct rx_rxpcu_classification_overview rxpcu_classification_details;
+ uint32_t reserved_1a : 11,
+ expected_response_ack_or_ba : 1,
+ nss : 3,
+ mcs : 4,
+ sta_full_aid : 13;
+ uint32_t fw2rxdma_pmac1_buf_source_used : 1,
+ sw2rxdma_exception_buf_source_used : 1,
+ sw2rxdma1_buf_source_used : 1,
+ fw2rxdma_pmac0_buf_source_used : 1,
+ sw2rxdma0_buf_source_used : 1,
+ mpdu_cnt_fcs_err : 11,
+ sw_peer_id : 16;
+ uint32_t reserved_3b : 5,
+ rxdma2reo_remote1_ring_used : 1,
+ rxdma2reo_remote0_ring_used : 1,
+ ht_control_field_pkt_type : 4,
+ rxdma_release_ring_used : 1,
+ rxdma2sw_ring_used : 1,
+ rxdma2fw_pmac0_ring_used : 1,
+ rxdma2reo_ring_used : 1,
+ rxdma2fw_pmac1_ring_used : 1,
+ ht_control_info_null_valid : 1,
+ data_sequence_control_info_valid : 1,
+ ht_control_info_valid : 1,
+ qos_control_info_valid : 1,
+ frame_control_info_valid : 1,
+ mpdu_cnt_fcs_ok : 11;
+ uint32_t frame_control_field : 16,
+ ast_index : 16;
+ uint32_t qos_control_field : 16,
+ first_data_seq_ctrl : 16;
+ uint32_t ht_control_field : 32;
+ uint32_t fcs_ok_bitmap_31_0 : 32;
+ uint32_t fcs_ok_bitmap_63_32 : 32;
+ uint32_t tcp_msdu_count : 16,
+ udp_msdu_count : 16;
+ uint32_t tcp_ack_msdu_count : 16,
+ other_msdu_count : 16;
+ uint32_t sw_response_reference_ptr : 32;
+ uint32_t received_qos_data_tid_eosp_bitmap : 16,
+ received_qos_data_tid_bitmap : 16;
+ uint32_t qosctrl_15_8_tid3 : 8,
+ qosctrl_15_8_tid2 : 8,
+ qosctrl_15_8_tid1 : 8,
+ qosctrl_15_8_tid0 : 8;
+ uint32_t qosctrl_15_8_tid7 : 8,
+ qosctrl_15_8_tid6 : 8,
+ qosctrl_15_8_tid5 : 8,
+ qosctrl_15_8_tid4 : 8;
+ uint32_t qosctrl_15_8_tid11 : 8,
+ qosctrl_15_8_tid10 : 8,
+ qosctrl_15_8_tid9 : 8,
+ qosctrl_15_8_tid8 : 8;
+ uint32_t qosctrl_15_8_tid15 : 8,
+ qosctrl_15_8_tid14 : 8,
+ qosctrl_15_8_tid13 : 8,
+ qosctrl_15_8_tid12 : 8;
+ uint32_t ampdu_delim_ok_count_6_0 : 7,
+ mpdu_ok_byte_count : 25;
+ uint32_t ampdu_delim_ok_count_13_7 : 7,
+ ampdu_delim_err_count : 25;
+ uint32_t ampdu_delim_ok_count_20_14 : 7,
+ mpdu_err_byte_count : 25;
+ uint32_t retried_msdu_count : 16,
+ non_consecutive_delimiter_err : 16;
+ uint32_t ht_control_null_field : 32;
+ uint32_t sw_response_reference_ptr_ext : 32;
+ uint32_t reserved_23a : 3,
+ retried_mpdu_count : 11,
+ frame_control_field_null : 16,
+ frame_control_info_null_valid : 1,
+ corrupted_due_to_fifo_delay : 1;
+ uint32_t frame_control_field_mgmt_ctrl : 16,
+ mcast_bcast : 1,
+ mac_addr_ad2_valid : 1,
+ frame_control_info_mgmt_ctrl_valid : 1,
+ reserved_24a : 4,
+ sw_frame_group_id : 7,
+ rxpcu_mpdu_filter_in_category : 2;
+ uint32_t reserved_25a : 8,
+ user_ppdu_len : 24;
+ uint32_t mac_addr_ad2_31_0 : 32;
+ uint32_t amsdu_msdu_count : 16,
+ mac_addr_ad2_47_32 : 16;
+ uint32_t ucast_msdu_count : 16,
+ non_amsdu_msdu_count : 16;
+ uint32_t mcast_bcast_msdu_count : 16,
+ bcast_msdu_count : 16;
+#endif
+};
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000fe00
+
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31
+#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 0
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 12
+#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff
+
+#define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_MCS_LSB 13
+#define RX_PPDU_END_USER_STATS_MCS_MSB 16
+#define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e000
+
+#define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_NSS_LSB 17
+#define RX_PPDU_END_USER_STATS_NSS_MSB 19
+#define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e0000
+
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 20
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 20
+#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x00100000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 21
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 31
+#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffe00000
+
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15
+#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x07ff0000
+
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27
+#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x08000000
+
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x10000000
+
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29
+#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x20000000
+
+#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30
+#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30
+#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x40000000
+
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31
+#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x80000000
+
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 0
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 10
+#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 11
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 11
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x00000800
+
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 12
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 12
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x00001000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 13
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 13
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x00002000
+
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 14
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 14
+#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x00004000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 15
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 15
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x00008000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 16
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 16
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x00010000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 17
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 17
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x00020000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 18
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 18
+#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x00040000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 19
+#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 19
+#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x00080000
+
+#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 20
+#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 20
+#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x00100000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 21
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 24
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e00000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_LSB 25
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MSB 25
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MASK 0x02000000
+
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_LSB 26
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MSB 26
+#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MASK 0x04000000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 27
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 31
+#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xf8000000
+
+#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x00000010
+#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0
+#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15
+#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x00000010
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x00000014
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 0
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 15
+#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x00000014
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 16
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 31
+#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x00000018
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000001c
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 0
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 31
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x00000020
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31
+#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x00000024
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 15
+#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x00000024
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 16
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 31
+#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x00000028
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15
+#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x00000028
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31
+#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000002c
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 0
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 31
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x00000030
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x00000030
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31
+#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x00000034
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 0
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 7
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x00000034
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 8
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 15
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x00000034
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 16
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 23
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x00000034
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 24
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 31
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x00000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x000000ff
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x00000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x00000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x00000038
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0xff000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000003c
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 0
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 7
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000003c
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 8
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 15
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000003c
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 16
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 23
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000003c
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 24
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 31
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff000000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x00000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x000000ff
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x00000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x0000ff00
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x00000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x00ff0000
+
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x00000040
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31
+#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0xff000000
+
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x00000044
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 24
+#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x00000044
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 25
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 31
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe000000
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x00000048
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x01ffffff
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x00000048
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0xfe000000
+
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000004c
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 24
+#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff
+
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000004c
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 25
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 31
+#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe000000
+
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x00000050
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15
+#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x00000050
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31
+#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x00000054
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 0
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 31
+#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x00000058
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31
+#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000005c
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0
+#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x00000001
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000005c
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 1
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 1
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x00000002
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000005c
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 2
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 17
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc
+
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000005c
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 18
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 28
+#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc0000
+
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000005c
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 29
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 31
+#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe0000000
+
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000060
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1
+#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x00000060
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8
+#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x00000060
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12
+#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x00001e00
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x00000060
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x00002000
+
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x00000060
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x00004000
+
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x00000060
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x00008000
+
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x00000060
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31
+#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x00000064
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 0
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 23
+#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff
+
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x00000064
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 24
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 31
+#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff000000
+
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x00000068
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000006c
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 0
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 15
+#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000006c
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 16
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 31
+#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x00000070
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15
+#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x00000070
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31
+#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x00000074
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 15
+#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff
+
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x00000074
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 16
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 31
+#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_end_user_stats_ext.h b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_end_user_stats_ext.h
new file mode 100644
index 0000000000000000000000000000000000000000..8c41ae3057497e93aa638d90824a3d8afeb606b9
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_end_user_stats_ext.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_PPDU_END_USER_STATS_EXT_H_
+#define _RX_PPDU_END_USER_STATS_EXT_H_
+
+#include "rx_rxpcu_classification_overview.h"
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8
+
+struct rx_ppdu_end_user_stats_ext {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct rx_rxpcu_classification_overview rxpcu_classification_details;
+ uint32_t fcs_ok_bitmap_95_64 : 32;
+ uint32_t fcs_ok_bitmap_127_96 : 32;
+ uint32_t fcs_ok_bitmap_159_128 : 32;
+ uint32_t fcs_ok_bitmap_191_160 : 32;
+ uint32_t fcs_ok_bitmap_223_192 : 32;
+ uint32_t fcs_ok_bitmap_255_224 : 32;
+ uint32_t corrupted_due_to_fifo_delay : 1,
+ reserved_7a : 31;
+#else
+ struct rx_rxpcu_classification_overview rxpcu_classification_details;
+ uint32_t fcs_ok_bitmap_95_64 : 32;
+ uint32_t fcs_ok_bitmap_127_96 : 32;
+ uint32_t fcs_ok_bitmap_159_128 : 32;
+ uint32_t fcs_ok_bitmap_191_160 : 32;
+ uint32_t fcs_ok_bitmap_223_192 : 32;
+ uint32_t fcs_ok_bitmap_255_224 : 32;
+ uint32_t reserved_7a : 31,
+ corrupted_due_to_fifo_delay : 1;
+#endif
+};
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000fe00
+
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31
+#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x00000010
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x00000014
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x00000018
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31
+#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0xffffffff
+
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000001c
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0
+#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x00000001
+
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000001c
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 1
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 31
+#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_no_ack_report.h b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_no_ack_report.h
new file mode 100644
index 0000000000000000000000000000000000000000..c98fd8f9ac8c217667c0a8ac6f212ac2c8e9c81c
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_no_ack_report.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_PPDU_NO_ACK_REPORT_H_
+#define _RX_PPDU_NO_ACK_REPORT_H_
+
+#include "no_ack_report.h"
+#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4
+
+struct rx_ppdu_no_ack_report {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct no_ack_report no_ack_report_details;
+#else
+ struct no_ack_report no_ack_report_details;
+#endif
+};
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x000000f0
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x00000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x0000ff00
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x00000000
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0xffff0000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x00000004
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 0
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 23
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x00000004
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 24
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 24
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x01000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x00000004
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 29
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 31
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe0000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x00000008
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0xff000000
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
+
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000c
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 12
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 31
+#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_start.h b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_start.h
new file mode 100644
index 0000000000000000000000000000000000000000..174b88cda1fab984ca8f1b3a486313f26b32d306
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_start.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_PPDU_START_H_
+#define _RX_PPDU_START_H_
+
+#define NUM_OF_DWORDS_RX_PPDU_START 5
+
+struct rx_ppdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t phy_ppdu_id : 16,
+ preamble_time_to_rxframe : 8,
+ reserved_0a : 8;
+ uint32_t sw_phy_meta_data : 32;
+ uint32_t ppdu_start_timestamp_31_0 : 32;
+ uint32_t ppdu_start_timestamp_63_32 : 32;
+ uint32_t rxframe_assert_timestamp : 32;
+#else
+ uint32_t reserved_0a : 8,
+ preamble_time_to_rxframe : 8,
+ phy_ppdu_id : 16;
+ uint32_t sw_phy_meta_data : 32;
+ uint32_t ppdu_start_timestamp_31_0 : 32;
+ uint32_t ppdu_start_timestamp_63_32 : 32;
+ uint32_t rxframe_assert_timestamp : 32;
+#endif
+};
+
+#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_PPDU_START_PHY_PPDU_ID_LSB 0
+#define RX_PPDU_START_PHY_PPDU_ID_MSB 15
+#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x00000000
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23
+#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x00ff0000
+
+#define RX_PPDU_START_RESERVED_0A_OFFSET 0x00000000
+#define RX_PPDU_START_RESERVED_0A_LSB 24
+#define RX_PPDU_START_RESERVED_0A_MSB 31
+#define RX_PPDU_START_RESERVED_0A_MASK 0xff000000
+
+#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x00000004
+#define RX_PPDU_START_SW_PHY_META_DATA_LSB 0
+#define RX_PPDU_START_SW_PHY_META_DATA_MSB 31
+#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff
+
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000008
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff
+
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000c
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 0
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 31
+#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff
+
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x00000010
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31
+#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_start_user_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_start_user_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..544532ca7734ae51100d581324513afa58afb892
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_ppdu_start_user_info.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_PPDU_START_USER_INFO_H_
+#define _RX_PPDU_START_USER_INFO_H_
+
+#include "receive_user_info.h"
+#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8
+
+struct rx_ppdu_start_user_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct receive_user_info receive_user_info_details;
+#else
+ struct receive_user_info receive_user_info_details;
+#endif
+};
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 3
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 5
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 7
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 7
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x00000080
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 16
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 18
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00070000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 19
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 23
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f80000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 24
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x000000fe
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x00000700
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x00003800
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x00004000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00008000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x000f0000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x00f00000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x0f000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0xf0000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 5
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 6
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 7
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c0
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 8
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 13
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f00
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 14
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 15
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 16
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 21
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f0000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 22
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 23
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c00000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 24
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 29
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 30
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc0000000
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x00000010
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0xffffffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x00000014
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x00000018
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0xffffffff
+
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000001c
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 0
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 31
+#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_preamble.h b/drivers/staging/fw-api/hw/peach/v1/rx_preamble.h
new file mode 100644
index 0000000000000000000000000000000000000000..75862b6e9a8c1029945d1c67ac7b4af797dc0d8c
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_preamble.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_PREAMBLE_H_
+#define _RX_PREAMBLE_H_
+
+#define NUM_OF_DWORDS_RX_PREAMBLE 1
+
+struct rx_preamble {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t num_users : 6,
+ pkt_type : 4,
+ direction : 1,
+ reserved_0a : 21;
+#else
+ uint32_t reserved_0a : 21,
+ direction : 1,
+ pkt_type : 4,
+ num_users : 6;
+#endif
+};
+
+#define RX_PREAMBLE_NUM_USERS_OFFSET 0x00000000
+#define RX_PREAMBLE_NUM_USERS_LSB 0
+#define RX_PREAMBLE_NUM_USERS_MSB 5
+#define RX_PREAMBLE_NUM_USERS_MASK 0x0000003f
+
+#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x00000000
+#define RX_PREAMBLE_PKT_TYPE_LSB 6
+#define RX_PREAMBLE_PKT_TYPE_MSB 9
+#define RX_PREAMBLE_PKT_TYPE_MASK 0x000003c0
+
+#define RX_PREAMBLE_DIRECTION_OFFSET 0x00000000
+#define RX_PREAMBLE_DIRECTION_LSB 10
+#define RX_PREAMBLE_DIRECTION_MSB 10
+#define RX_PREAMBLE_DIRECTION_MASK 0x00000400
+
+#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x00000000
+#define RX_PREAMBLE_RESERVED_0A_LSB 11
+#define RX_PREAMBLE_RESERVED_0A_MSB 31
+#define RX_PREAMBLE_RESERVED_0A_MASK 0xfffff800
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue.h b/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue.h
new file mode 100644
index 0000000000000000000000000000000000000000..be630859dfd40daa3903ab55196b72c039f66d36
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue.h
@@ -0,0 +1,514 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_REO_QUEUE_H_
+#define _RX_REO_QUEUE_H_
+
+#include "uniform_descriptor_header.h"
+#define NUM_OF_DWORDS_RX_REO_QUEUE 32
+
+struct rx_reo_queue {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct uniform_descriptor_header descriptor_header;
+ uint32_t receive_queue_number : 16,
+ reserved_1b : 16;
+ uint32_t vld : 1,
+ associated_link_descriptor_counter : 2,
+ disable_duplicate_detection : 1,
+ soft_reorder_enable : 1,
+ ac : 2,
+ bar : 1,
+ rty : 1,
+ chk_2k_mode : 1,
+ oor_mode : 1,
+ ba_window_size : 10,
+ pn_check_needed : 1,
+ pn_shall_be_even : 1,
+ pn_shall_be_uneven : 1,
+ pn_handling_enable : 1,
+ pn_size : 2,
+ ignore_ampdu_flag : 1,
+ reserved_2b : 4;
+ uint32_t svld : 1,
+ ssn : 12,
+ current_index : 10,
+ seq_2k_error_detected_flag : 1,
+ pn_error_detected_flag : 1,
+ reserved_3a : 6,
+ pn_valid : 1;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_63_32 : 32;
+ uint32_t pn_95_64 : 32;
+ uint32_t pn_127_96 : 32;
+ uint32_t last_rx_enqueue_timestamp : 32;
+ uint32_t last_rx_dequeue_timestamp : 32;
+ uint32_t ptr_to_next_aging_queue_31_0 : 32;
+ uint32_t ptr_to_next_aging_queue_39_32 : 8,
+ reserved_11a : 24;
+ uint32_t ptr_to_previous_aging_queue_31_0 : 32;
+ uint32_t ptr_to_previous_aging_queue_39_32 : 8,
+ statistics_counter_index : 6,
+ reserved_13a : 18;
+ uint32_t rx_bitmap_31_0 : 32;
+ uint32_t rx_bitmap_63_32 : 32;
+ uint32_t rx_bitmap_95_64 : 32;
+ uint32_t rx_bitmap_127_96 : 32;
+ uint32_t rx_bitmap_159_128 : 32;
+ uint32_t rx_bitmap_191_160 : 32;
+ uint32_t rx_bitmap_223_192 : 32;
+ uint32_t rx_bitmap_255_224 : 32;
+ uint32_t rx_bitmap_287_256 : 32;
+ uint32_t current_mpdu_count : 7,
+ current_msdu_count : 25;
+ uint32_t last_sn_reg_index : 4,
+ timeout_count : 6,
+ forward_due_to_bar_count : 6,
+ duplicate_count : 16;
+ uint32_t frames_in_order_count : 24,
+ bar_received_count : 8;
+ uint32_t mpdu_frames_processed_count : 32;
+ uint32_t msdu_frames_processed_count : 32;
+ uint32_t total_processed_byte_count : 32;
+ uint32_t late_receive_mpdu_count : 12,
+ window_jump_2k : 4,
+ hole_count : 16;
+ uint32_t aging_drop_mpdu_count : 16,
+ aging_drop_interval : 8,
+ reserved_30 : 8;
+ uint32_t reserved_31 : 32;
+#else
+ struct uniform_descriptor_header descriptor_header;
+ uint32_t reserved_1b : 16,
+ receive_queue_number : 16;
+ uint32_t reserved_2b : 4,
+ ignore_ampdu_flag : 1,
+ pn_size : 2,
+ pn_handling_enable : 1,
+ pn_shall_be_uneven : 1,
+ pn_shall_be_even : 1,
+ pn_check_needed : 1,
+ ba_window_size : 10,
+ oor_mode : 1,
+ chk_2k_mode : 1,
+ rty : 1,
+ bar : 1,
+ ac : 2,
+ soft_reorder_enable : 1,
+ disable_duplicate_detection : 1,
+ associated_link_descriptor_counter : 2,
+ vld : 1;
+ uint32_t pn_valid : 1,
+ reserved_3a : 6,
+ pn_error_detected_flag : 1,
+ seq_2k_error_detected_flag : 1,
+ current_index : 10,
+ ssn : 12,
+ svld : 1;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_63_32 : 32;
+ uint32_t pn_95_64 : 32;
+ uint32_t pn_127_96 : 32;
+ uint32_t last_rx_enqueue_timestamp : 32;
+ uint32_t last_rx_dequeue_timestamp : 32;
+ uint32_t ptr_to_next_aging_queue_31_0 : 32;
+ uint32_t reserved_11a : 24,
+ ptr_to_next_aging_queue_39_32 : 8;
+ uint32_t ptr_to_previous_aging_queue_31_0 : 32;
+ uint32_t reserved_13a : 18,
+ statistics_counter_index : 6,
+ ptr_to_previous_aging_queue_39_32 : 8;
+ uint32_t rx_bitmap_31_0 : 32;
+ uint32_t rx_bitmap_63_32 : 32;
+ uint32_t rx_bitmap_95_64 : 32;
+ uint32_t rx_bitmap_127_96 : 32;
+ uint32_t rx_bitmap_159_128 : 32;
+ uint32_t rx_bitmap_191_160 : 32;
+ uint32_t rx_bitmap_223_192 : 32;
+ uint32_t rx_bitmap_255_224 : 32;
+ uint32_t rx_bitmap_287_256 : 32;
+ uint32_t current_msdu_count : 25,
+ current_mpdu_count : 7;
+ uint32_t duplicate_count : 16,
+ forward_due_to_bar_count : 6,
+ timeout_count : 6,
+ last_sn_reg_index : 4;
+ uint32_t bar_received_count : 8,
+ frames_in_order_count : 24;
+ uint32_t mpdu_frames_processed_count : 32;
+ uint32_t msdu_frames_processed_count : 32;
+ uint32_t total_processed_byte_count : 32;
+ uint32_t hole_count : 16,
+ window_jump_2k : 4,
+ late_receive_mpdu_count : 12;
+ uint32_t reserved_30 : 8,
+ aging_drop_interval : 8,
+ aging_drop_mpdu_count : 16;
+ uint32_t reserved_31 : 32;
+#endif
+};
+
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
+
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
+
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
+
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
+#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004
+#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0
+#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15
+#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff
+
+#define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004
+#define RX_REO_QUEUE_RESERVED_1B_LSB 16
+#define RX_REO_QUEUE_RESERVED_1B_MSB 31
+#define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000
+
+#define RX_REO_QUEUE_VLD_OFFSET 0x00000008
+#define RX_REO_QUEUE_VLD_LSB 0
+#define RX_REO_QUEUE_VLD_MSB 0
+#define RX_REO_QUEUE_VLD_MASK 0x00000001
+
+#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008
+#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1
+#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2
+#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006
+
+#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008
+#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3
+#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3
+#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008
+
+#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008
+#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4
+#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4
+#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010
+
+#define RX_REO_QUEUE_AC_OFFSET 0x00000008
+#define RX_REO_QUEUE_AC_LSB 5
+#define RX_REO_QUEUE_AC_MSB 6
+#define RX_REO_QUEUE_AC_MASK 0x00000060
+
+#define RX_REO_QUEUE_BAR_OFFSET 0x00000008
+#define RX_REO_QUEUE_BAR_LSB 7
+#define RX_REO_QUEUE_BAR_MSB 7
+#define RX_REO_QUEUE_BAR_MASK 0x00000080
+
+#define RX_REO_QUEUE_RTY_OFFSET 0x00000008
+#define RX_REO_QUEUE_RTY_LSB 8
+#define RX_REO_QUEUE_RTY_MSB 8
+#define RX_REO_QUEUE_RTY_MASK 0x00000100
+
+#define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008
+#define RX_REO_QUEUE_CHK_2K_MODE_LSB 9
+#define RX_REO_QUEUE_CHK_2K_MODE_MSB 9
+#define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200
+
+#define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008
+#define RX_REO_QUEUE_OOR_MODE_LSB 10
+#define RX_REO_QUEUE_OOR_MODE_MSB 10
+#define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400
+
+#define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008
+#define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11
+#define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20
+#define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800
+
+#define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008
+#define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21
+#define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21
+#define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000
+
+#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008
+#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22
+#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22
+#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000
+
+#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008
+#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23
+#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23
+#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000
+
+#define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008
+#define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24
+#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24
+#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000
+
+#define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008
+#define RX_REO_QUEUE_PN_SIZE_LSB 25
+#define RX_REO_QUEUE_PN_SIZE_MSB 26
+#define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000
+
+#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008
+#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27
+#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27
+#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000
+
+#define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008
+#define RX_REO_QUEUE_RESERVED_2B_LSB 28
+#define RX_REO_QUEUE_RESERVED_2B_MSB 31
+#define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000
+
+#define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c
+#define RX_REO_QUEUE_SVLD_LSB 0
+#define RX_REO_QUEUE_SVLD_MSB 0
+#define RX_REO_QUEUE_SVLD_MASK 0x00000001
+
+#define RX_REO_QUEUE_SSN_OFFSET 0x0000000c
+#define RX_REO_QUEUE_SSN_LSB 1
+#define RX_REO_QUEUE_SSN_MSB 12
+#define RX_REO_QUEUE_SSN_MASK 0x00001ffe
+
+#define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c
+#define RX_REO_QUEUE_CURRENT_INDEX_LSB 13
+#define RX_REO_QUEUE_CURRENT_INDEX_MSB 22
+#define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000
+
+#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c
+#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23
+#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23
+#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000
+
+#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c
+#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24
+#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24
+#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000
+
+#define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c
+#define RX_REO_QUEUE_RESERVED_3A_LSB 25
+#define RX_REO_QUEUE_RESERVED_3A_MSB 30
+#define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000
+
+#define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c
+#define RX_REO_QUEUE_PN_VALID_LSB 31
+#define RX_REO_QUEUE_PN_VALID_MSB 31
+#define RX_REO_QUEUE_PN_VALID_MASK 0x80000000
+
+#define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010
+#define RX_REO_QUEUE_PN_31_0_LSB 0
+#define RX_REO_QUEUE_PN_31_0_MSB 31
+#define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014
+#define RX_REO_QUEUE_PN_63_32_LSB 0
+#define RX_REO_QUEUE_PN_63_32_MSB 31
+#define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff
+
+#define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018
+#define RX_REO_QUEUE_PN_95_64_LSB 0
+#define RX_REO_QUEUE_PN_95_64_MSB 31
+#define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff
+
+#define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c
+#define RX_REO_QUEUE_PN_127_96_LSB 0
+#define RX_REO_QUEUE_PN_127_96_MSB 31
+#define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff
+
+#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020
+#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0
+#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31
+#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff
+
+#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024
+#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0
+#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31
+#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff
+
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7
+#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c
+#define RX_REO_QUEUE_RESERVED_11A_LSB 8
+#define RX_REO_QUEUE_RESERVED_11A_MSB 31
+#define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00
+
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7
+#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET 0x00000034
+#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB 8
+#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB 13
+#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK 0x00003f00
+
+#define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034
+#define RX_REO_QUEUE_RESERVED_13A_LSB 14
+#define RX_REO_QUEUE_RESERVED_13A_MSB 31
+#define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffc000
+
+#define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038
+#define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0
+#define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31
+#define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c
+#define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0
+#define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31
+#define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040
+#define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0
+#define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31
+#define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044
+#define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0
+#define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31
+#define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048
+#define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0
+#define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31
+#define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c
+#define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0
+#define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31
+#define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050
+#define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0
+#define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31
+#define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054
+#define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0
+#define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31
+#define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff
+
+#define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058
+#define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0
+#define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31
+#define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff
+
+#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c
+#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0
+#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6
+#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f
+
+#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c
+#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7
+#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31
+#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80
+
+#define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060
+#define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0
+#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3
+#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f
+
+#define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060
+#define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4
+#define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9
+#define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0
+
+#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060
+#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10
+#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15
+#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00
+
+#define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060
+#define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16
+#define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31
+#define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000
+
+#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064
+#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0
+#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23
+#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff
+
+#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064
+#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24
+#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31
+#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000
+
+#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068
+#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31
+#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c
+#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31
+#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070
+#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0
+#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31
+#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff
+
+#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074
+#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0
+#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11
+#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff
+
+#define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074
+#define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12
+#define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15
+#define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000
+
+#define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074
+#define RX_REO_QUEUE_HOLE_COUNT_LSB 16
+#define RX_REO_QUEUE_HOLE_COUNT_MSB 31
+#define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000
+
+#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET 0x00000078
+#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB 0
+#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB 15
+#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff
+
+#define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET 0x00000078
+#define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB 16
+#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB 23
+#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK 0x00ff0000
+
+#define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078
+#define RX_REO_QUEUE_RESERVED_30_LSB 24
+#define RX_REO_QUEUE_RESERVED_30_MSB 31
+#define RX_REO_QUEUE_RESERVED_30_MASK 0xff000000
+
+#define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c
+#define RX_REO_QUEUE_RESERVED_31_LSB 0
+#define RX_REO_QUEUE_RESERVED_31_MSB 31
+#define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue_1k.h b/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue_1k.h
new file mode 100644
index 0000000000000000000000000000000000000000..410c1d499c51453a8ff3d043cfe7b717849551ab
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue_1k.h
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_REO_QUEUE_1K_H_
+#define _RX_REO_QUEUE_1K_H_
+
+#include "uniform_descriptor_header.h"
+#define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32
+
+struct rx_reo_queue_1k {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct uniform_descriptor_header descriptor_header;
+ uint32_t rx_bitmap_319_288 : 32;
+ uint32_t rx_bitmap_351_320 : 32;
+ uint32_t rx_bitmap_383_352 : 32;
+ uint32_t rx_bitmap_415_384 : 32;
+ uint32_t rx_bitmap_447_416 : 32;
+ uint32_t rx_bitmap_479_448 : 32;
+ uint32_t rx_bitmap_511_480 : 32;
+ uint32_t rx_bitmap_543_512 : 32;
+ uint32_t rx_bitmap_575_544 : 32;
+ uint32_t rx_bitmap_607_576 : 32;
+ uint32_t rx_bitmap_639_608 : 32;
+ uint32_t rx_bitmap_671_640 : 32;
+ uint32_t rx_bitmap_703_672 : 32;
+ uint32_t rx_bitmap_735_704 : 32;
+ uint32_t rx_bitmap_767_736 : 32;
+ uint32_t rx_bitmap_799_768 : 32;
+ uint32_t rx_bitmap_831_800 : 32;
+ uint32_t rx_bitmap_863_832 : 32;
+ uint32_t rx_bitmap_895_864 : 32;
+ uint32_t rx_bitmap_927_896 : 32;
+ uint32_t rx_bitmap_959_928 : 32;
+ uint32_t rx_bitmap_991_960 : 32;
+ uint32_t rx_bitmap_1023_992 : 32;
+ uint32_t reserved_24 : 32;
+ uint32_t reserved_25 : 32;
+ uint32_t reserved_26 : 32;
+ uint32_t reserved_27 : 32;
+ uint32_t reserved_28 : 32;
+ uint32_t reserved_29 : 32;
+ uint32_t reserved_30 : 32;
+ uint32_t reserved_31 : 32;
+#else
+ struct uniform_descriptor_header descriptor_header;
+ uint32_t rx_bitmap_319_288 : 32;
+ uint32_t rx_bitmap_351_320 : 32;
+ uint32_t rx_bitmap_383_352 : 32;
+ uint32_t rx_bitmap_415_384 : 32;
+ uint32_t rx_bitmap_447_416 : 32;
+ uint32_t rx_bitmap_479_448 : 32;
+ uint32_t rx_bitmap_511_480 : 32;
+ uint32_t rx_bitmap_543_512 : 32;
+ uint32_t rx_bitmap_575_544 : 32;
+ uint32_t rx_bitmap_607_576 : 32;
+ uint32_t rx_bitmap_639_608 : 32;
+ uint32_t rx_bitmap_671_640 : 32;
+ uint32_t rx_bitmap_703_672 : 32;
+ uint32_t rx_bitmap_735_704 : 32;
+ uint32_t rx_bitmap_767_736 : 32;
+ uint32_t rx_bitmap_799_768 : 32;
+ uint32_t rx_bitmap_831_800 : 32;
+ uint32_t rx_bitmap_863_832 : 32;
+ uint32_t rx_bitmap_895_864 : 32;
+ uint32_t rx_bitmap_927_896 : 32;
+ uint32_t rx_bitmap_959_928 : 32;
+ uint32_t rx_bitmap_991_960 : 32;
+ uint32_t rx_bitmap_1023_992 : 32;
+ uint32_t reserved_24 : 32;
+ uint32_t reserved_25 : 32;
+ uint32_t reserved_26 : 32;
+ uint32_t reserved_27 : 32;
+ uint32_t reserved_28 : 32;
+ uint32_t reserved_29 : 32;
+ uint32_t reserved_30 : 32;
+ uint32_t reserved_31 : 32;
+#endif
+};
+
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
+
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
+
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
+
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
+#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004
+#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008
+#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c
+#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010
+#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014
+#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018
+#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c
+#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020
+#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024
+#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028
+#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c
+#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030
+#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034
+#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038
+#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c
+#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040
+#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044
+#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048
+#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c
+#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050
+#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054
+#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058
+#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c
+#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0
+#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31
+#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060
+#define RX_REO_QUEUE_1K_RESERVED_24_LSB 0
+#define RX_REO_QUEUE_1K_RESERVED_24_MSB 31
+#define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064
+#define RX_REO_QUEUE_1K_RESERVED_25_LSB 0
+#define RX_REO_QUEUE_1K_RESERVED_25_MSB 31
+#define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068
+#define RX_REO_QUEUE_1K_RESERVED_26_LSB 0
+#define RX_REO_QUEUE_1K_RESERVED_26_MSB 31
+#define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c
+#define RX_REO_QUEUE_1K_RESERVED_27_LSB 0
+#define RX_REO_QUEUE_1K_RESERVED_27_MSB 31
+#define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070
+#define RX_REO_QUEUE_1K_RESERVED_28_LSB 0
+#define RX_REO_QUEUE_1K_RESERVED_28_MSB 31
+#define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074
+#define RX_REO_QUEUE_1K_RESERVED_29_LSB 0
+#define RX_REO_QUEUE_1K_RESERVED_29_MSB 31
+#define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078
+#define RX_REO_QUEUE_1K_RESERVED_30_LSB 0
+#define RX_REO_QUEUE_1K_RESERVED_30_MSB 31
+#define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff
+
+#define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c
+#define RX_REO_QUEUE_1K_RESERVED_31_LSB 0
+#define RX_REO_QUEUE_1K_RESERVED_31_MSB 31
+#define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue_ext.h b/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue_ext.h
new file mode 100644
index 0000000000000000000000000000000000000000..32c25df690d31f1b057b554e892f51238ad14327
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_reo_queue_ext.h
@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_REO_QUEUE_EXT_H_
+#define _RX_REO_QUEUE_EXT_H_
+
+#include "rx_mpdu_link_ptr.h"
+#include "uniform_descriptor_header.h"
+#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32
+
+struct rx_reo_queue_ext {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct uniform_descriptor_header descriptor_header;
+ uint32_t reserved_1a : 32;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_0;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_1;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_2;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_3;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_4;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_5;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_6;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_7;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_8;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_9;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_10;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_11;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_12;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_13;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_14;
+#else
+ struct uniform_descriptor_header descriptor_header;
+ uint32_t reserved_1a : 32;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_0;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_1;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_2;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_3;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_4;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_5;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_6;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_7;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_8;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_9;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_10;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_11;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_12;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_13;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_14;
+#endif
+};
+
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB 0
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB 3
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
+
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
+
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
+
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
+#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET 0x00000004
+#define RX_REO_QUEUE_EXT_RESERVED_1A_LSB 0
+#define RX_REO_QUEUE_EXT_RESERVED_1A_MSB 31
+#define RX_REO_QUEUE_EXT_RESERVED_1A_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_response_required_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_response_required_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..516ea5180df1827d315f3e7af775f1d9a10f21d4
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_response_required_info.h
@@ -0,0 +1,700 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_RESPONSE_REQUIRED_INFO_H_
+#define _RX_RESPONSE_REQUIRED_INFO_H_
+
+#include "mlo_sta_id_details.h"
+#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 15
+
+struct rx_response_required_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t phy_ppdu_id : 16,
+ su_or_uplink_mu_reception : 1,
+ trigger_frame_received : 1,
+ __reserved_g_0012 : 2,
+ tb___reserved_g_0005_response_required : 2,
+ mac_security : 1,
+ filter_pass_monitor_ovrd : 1,
+ ast_search_incomplete : 1,
+ r2r_end_status_to_follow : 1,
+ __reserved_g_0016_listen_cca_check_at_phy_desc : 1,
+ __reserved_g_0016_listen_indication : 1,
+ three_or_more_type_subtypes : 1,
+ wait_sifs_config_valid : 1,
+ wait_sifs : 2;
+ uint32_t general_frame_control : 16,
+ second_frame_control : 16;
+ uint32_t duration : 16,
+ pkt_type : 4,
+ dot11ax_su_extended : 1,
+ rate_mcs : 4,
+ sgi : 2,
+ stbc : 1,
+ ldpc : 1,
+ ampdu : 1,
+ vht_ack : 1,
+ rts_ta_grp_bit : 1;
+ uint32_t ctrl_frame_soliciting_resp : 1,
+ ast_fail_for_dot11ax_su_ext : 1,
+ service_dynamic : 1,
+ m_pkt : 1,
+ sta_partial_aid : 12,
+ group_id : 6,
+ ctrl_resp_pwr_mgmt : 1,
+ response_indication : 2,
+ ndp_indication : 1,
+ ndp_frame_type : 3,
+ second_frame_control_valid : 1,
+ ack_ba_resp_more_data : 1,
+ reserved_3a : 1;
+ uint32_t ack_id : 16,
+ ack_id_ext : 10,
+ agc_cbw : 3,
+ service_cbw : 3;
+ uint32_t response_sta_count : 7,
+ reserved : 4,
+ ht_vht_sig_cbw : 3,
+ cts_cbw : 3,
+ response_ack_count : 7,
+ response_assoc_ack_count : 7,
+ txop_duration_all_ones : 1;
+ uint32_t response_ba32_count : 7,
+ response_ba64_count : 7,
+ response_ba128_count : 7,
+ response_ba256_count : 7,
+ multi_tid : 1,
+ sw_response_tlv_from_crypto : 1,
+ dot11ax_dl_ul_flag : 1,
+ emlsr_main_tlv_if : 1;
+ uint32_t sw_response_frame_length : 16,
+ response_ba512_count : 7,
+ response_ba1024_count : 7,
+ reserved_7a : 2;
+ uint32_t addr1_31_0 : 32;
+ uint32_t addr1_47_32 : 16,
+ addr2_15_0 : 16;
+ uint32_t addr2_47_16 : 32;
+ uint32_t dot11ax_received_format_indication : 1,
+ dot11ax_received_dl_ul_flag : 1,
+ dot11ax_received_bss_color_id : 6,
+ dot11ax_received_spatial_reuse : 4,
+ dot11ax_received_cp_size : 2,
+ dot11ax_received_ltf_size : 2,
+ dot11ax_received_coding : 1,
+ dot11ax_received_dcm : 1,
+ dot11ax_received_doppler_indication : 1,
+ dot11ax_received_ext_ru_size : 4,
+ ftm_fields_valid : 1,
+ ftm_pe_nss : 3,
+ ftm_pe_ltf_size : 2,
+ ftm_pe_content : 1,
+ ftm_chain_csd_en : 1,
+ ftm_pe_chain_csd_en : 1;
+ uint32_t dot11ax_response_rate_source : 8,
+ dot11ax_ext_response_rate_source : 8,
+ sw_peer_id : 16;
+ uint32_t dot11be_puncture_bitmap : 16,
+ dot11be_response : 1,
+ punctured_response : 1,
+ eht_duplicate_mode : 2,
+ force_extra_symbol : 1,
+ reserved_13a : 5,
+ u_sig_puncture_pattern_encoding : 6;
+ struct mlo_sta_id_details mlo_sta_id_details_rx;
+ uint16_t he_a_control_response_time : 12,
+ reserved_after_struct16 : 4;
+#else
+ uint32_t wait_sifs : 2,
+ wait_sifs_config_valid : 1,
+ three_or_more_type_subtypes : 1,
+ __reserved_g_0016_listen_indication : 1,
+ __reserved_g_0016_listen_cca_check_at_phy_desc : 1,
+ r2r_end_status_to_follow : 1,
+ ast_search_incomplete : 1,
+ filter_pass_monitor_ovrd : 1,
+ mac_security : 1,
+ tb___reserved_g_0005_response_required : 2,
+ __reserved_g_0012 : 2,
+ trigger_frame_received : 1,
+ su_or_uplink_mu_reception : 1,
+ phy_ppdu_id : 16;
+ uint32_t second_frame_control : 16,
+ general_frame_control : 16;
+ uint32_t rts_ta_grp_bit : 1,
+ vht_ack : 1,
+ ampdu : 1,
+ ldpc : 1,
+ stbc : 1,
+ sgi : 2,
+ rate_mcs : 4,
+ dot11ax_su_extended : 1,
+ pkt_type : 4,
+ duration : 16;
+ uint32_t reserved_3a : 1,
+ ack_ba_resp_more_data : 1,
+ second_frame_control_valid : 1,
+ ndp_frame_type : 3,
+ ndp_indication : 1,
+ response_indication : 2,
+ ctrl_resp_pwr_mgmt : 1,
+ group_id : 6,
+ sta_partial_aid : 12,
+ m_pkt : 1,
+ service_dynamic : 1,
+ ast_fail_for_dot11ax_su_ext : 1,
+ ctrl_frame_soliciting_resp : 1;
+ uint32_t service_cbw : 3,
+ agc_cbw : 3,
+ ack_id_ext : 10,
+ ack_id : 16;
+ uint32_t txop_duration_all_ones : 1,
+ response_assoc_ack_count : 7,
+ response_ack_count : 7,
+ cts_cbw : 3,
+ ht_vht_sig_cbw : 3,
+ reserved : 4,
+ response_sta_count : 7;
+ uint32_t emlsr_main_tlv_if : 1,
+ dot11ax_dl_ul_flag : 1,
+ sw_response_tlv_from_crypto : 1,
+ multi_tid : 1,
+ response_ba256_count : 7,
+ response_ba128_count : 7,
+ response_ba64_count : 7,
+ response_ba32_count : 7;
+ uint32_t reserved_7a : 2,
+ response_ba1024_count : 7,
+ response_ba512_count : 7,
+ sw_response_frame_length : 16;
+ uint32_t addr1_31_0 : 32;
+ uint32_t addr2_15_0 : 16,
+ addr1_47_32 : 16;
+ uint32_t addr2_47_16 : 32;
+ uint32_t ftm_pe_chain_csd_en : 1,
+ ftm_chain_csd_en : 1,
+ ftm_pe_content : 1,
+ ftm_pe_ltf_size : 2,
+ ftm_pe_nss : 3,
+ ftm_fields_valid : 1,
+ dot11ax_received_ext_ru_size : 4,
+ dot11ax_received_doppler_indication : 1,
+ dot11ax_received_dcm : 1,
+ dot11ax_received_coding : 1,
+ dot11ax_received_ltf_size : 2,
+ dot11ax_received_cp_size : 2,
+ dot11ax_received_spatial_reuse : 4,
+ dot11ax_received_bss_color_id : 6,
+ dot11ax_received_dl_ul_flag : 1,
+ dot11ax_received_format_indication : 1;
+ uint32_t sw_peer_id : 16,
+ dot11ax_ext_response_rate_source : 8,
+ dot11ax_response_rate_source : 8;
+ uint32_t u_sig_puncture_pattern_encoding : 6,
+ reserved_13a : 5,
+ force_extra_symbol : 1,
+ eht_duplicate_mode : 2,
+ punctured_response : 1,
+ dot11be_response : 1,
+ dot11be_puncture_bitmap : 16;
+ uint32_t reserved_after_struct16 : 4,
+ he_a_control_response_time : 12;
+ struct mlo_sta_id_details mlo_sta_id_details_rx;
+#endif
+};
+
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15
+#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x0000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16
+#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x00010000
+
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17
+#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x00020000
+
+#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 20
+#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 21
+#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x00300000
+
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22
+#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x00400000
+
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23
+#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x00800000
+
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24
+#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x01000000
+
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25
+#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x02000000
+
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28
+#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x10000000
+
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x20000000
+
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x00000000
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31
+#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0xc0000000
+
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x00000004
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 0
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 15
+#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x00000004
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 16
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 31
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15
+#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x0000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19
+#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x000f0000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x00100000
+
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 24
+#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x01e00000
+
+#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 25
+#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 26
+#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x06000000
+
+#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 27
+#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 27
+#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x08000000
+
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 28
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 28
+#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x10000000
+
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 29
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 29
+#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x20000000
+
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 30
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 30
+#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x40000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x00000008
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31
+#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x80000000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 0
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 0
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x00000001
+
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 1
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 1
+#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x00000002
+
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 2
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 2
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x00000004
+
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 3
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 3
+#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x00000008
+
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 4
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 15
+#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff0
+
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 16
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 21
+#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f0000
+
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 22
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 22
+#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x00400000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 23
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 24
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x01800000
+
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 25
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 25
+#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x02000000
+
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 26
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 28
+#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 29
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 29
+#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x20000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_OFFSET 0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_LSB 30
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MSB 30
+#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MASK 0x40000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_OFFSET 0x0000000c
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_LSB 31
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MSB 31
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MASK 0x80000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_OFFSET 0x00000010
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_LSB 0
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MSB 15
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MASK 0x0000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x00000010
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25
+#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x03ff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x00000010
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28
+#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x1c000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x00000010
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31
+#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0xe0000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x00000014
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 0
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 6
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x00000014
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 7
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 10
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x00000780
+
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x00000014
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 11
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 13
+#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x00003800
+
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x00000014
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 14
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 16
+#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x00000014
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 17
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 23
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe0000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x00000014
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 24
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 30
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f000000
+
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x00000014
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 31
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 31
+#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x80000000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x0000007f
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x00003f80
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x001fc000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x0fe00000
+
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28
+#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x10000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x20000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x40000000
+
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x00000018
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_LSB 31
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MSB 31
+#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MASK 0x80000000
+
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000001c
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15
+#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000001c
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 16
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 22
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f0000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000001c
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 23
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 29
+#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f800000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000001c
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 30
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 31
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc0000000
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x00000020
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0xffffffff
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x00000024
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 0
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 15
+#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x00000024
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 16
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 31
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x00000028
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31
+#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0xffffffff
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 0
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 0
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x00000001
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 1
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 1
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x00000002
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 2
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 7
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 8
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 11
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f00
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 12
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 13
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x00003000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 14
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 15
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 16
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 16
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x00010000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 17
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 17
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x00020000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 18
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 18
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x00040000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 19
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 22
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x00780000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 23
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 23
+#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x00800000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 24
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 26
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x07000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 27
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 28
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x18000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 29
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 29
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x20000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 30
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 30
+#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x40000000
+
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000002c
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 31
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 31
+#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x80000000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x00000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x000000ff
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x00000030
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15
+#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x0000ff00
+
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x00000030
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31
+#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0xffff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x00000034
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 0
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 15
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff
+
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x00000034
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 16
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 16
+#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x00010000
+
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x00000034
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 17
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 17
+#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x00020000
+
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x00000034
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 18
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 19
+#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c0000
+
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x00000034
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 20
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 20
+#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x00100000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x00000034
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 21
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 25
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x03e00000
+
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000034
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
+
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000038
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
+#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
+
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x00000038
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27
+#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x0fff0000
+
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x00000038
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31
+#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_rxpcu_classification_overview.h b/drivers/staging/fw-api/hw/peach/v1/rx_rxpcu_classification_overview.h
new file mode 100644
index 0000000000000000000000000000000000000000..36bc52b5415cbf78565f4d9c3350cad68ca16202
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_rxpcu_classification_overview.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+
+#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1
+
+struct rx_rxpcu_classification_overview {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t filter_pass_mpdus : 1,
+ filter_pass_mpdus_fcs_ok : 1,
+ monitor_direct_mpdus : 1,
+ monitor_direct_mpdus_fcs_ok : 1,
+ monitor_other_mpdus : 1,
+ monitor_other_mpdus_fcs_ok : 1,
+ phyrx_abort_received : 1,
+ filter_pass_monitor_ovrd_mpdus : 1,
+ filter_pass_monitor_ovrd_mpdus_fcs_ok : 1,
+ reserved_0 : 7,
+ phy_ppdu_id : 16;
+#else
+ uint32_t phy_ppdu_id : 16,
+ reserved_0 : 7,
+ filter_pass_monitor_ovrd_mpdus_fcs_ok : 1,
+ filter_pass_monitor_ovrd_mpdus : 1,
+ phyrx_abort_received : 1,
+ monitor_other_mpdus_fcs_ok : 1,
+ monitor_other_mpdus : 1,
+ monitor_direct_mpdus_fcs_ok : 1,
+ monitor_direct_mpdus : 1,
+ filter_pass_mpdus_fcs_ok : 1,
+ filter_pass_mpdus : 1;
+#endif
+};
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00
+
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_start_param.h b/drivers/staging/fw-api/hw/peach/v1/rx_start_param.h
new file mode 100644
index 0000000000000000000000000000000000000000..b10ffb979b3a4a35a71394e2af7310aee5e296ea
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_start_param.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_START_PARAM_H_
+#define _RX_START_PARAM_H_
+
+#define NUM_OF_DWORDS_RX_START_PARAM 1
+
+struct rx_start_param {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t pkt_type : 4,
+ reserved_0a : 12,
+ remaining_rx_time : 16;
+#else
+ uint32_t remaining_rx_time : 16,
+ reserved_0a : 12,
+ pkt_type : 4;
+#endif
+};
+
+#define RX_START_PARAM_PKT_TYPE_OFFSET 0x00000000
+#define RX_START_PARAM_PKT_TYPE_LSB 0
+#define RX_START_PARAM_PKT_TYPE_MSB 3
+#define RX_START_PARAM_PKT_TYPE_MASK 0x0000000f
+
+#define RX_START_PARAM_RESERVED_0A_OFFSET 0x00000000
+#define RX_START_PARAM_RESERVED_0A_LSB 4
+#define RX_START_PARAM_RESERVED_0A_MSB 15
+#define RX_START_PARAM_RESERVED_0A_MASK 0x0000fff0
+
+#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x00000000
+#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16
+#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31
+#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_timing_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_timing_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..50c0a41e408c1a091d4a983abe3c1d2fe3ca1e8d
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_timing_info.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_TIMING_INFO_H_
+#define _RX_TIMING_INFO_H_
+
+#define NUM_OF_DWORDS_RX_TIMING_INFO 5
+
+struct rx_timing_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t phy_timestamp_1_lower_32 : 32;
+ uint32_t phy_timestamp_1_upper_32 : 32;
+ uint32_t phy_timestamp_2_lower_32 : 32;
+ uint32_t phy_timestamp_2_upper_32 : 32;
+ uint32_t residual_phase_offset : 12,
+ reserved : 20;
+#else
+ uint32_t phy_timestamp_1_lower_32 : 32;
+ uint32_t phy_timestamp_1_upper_32 : 32;
+ uint32_t phy_timestamp_2_lower_32 : 32;
+ uint32_t phy_timestamp_2_upper_32 : 32;
+ uint32_t reserved : 20,
+ residual_phase_offset : 12;
+#endif
+};
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000000
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000004
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x00000008
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
+
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000c
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31
+#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
+
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000010
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_LSB 0
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MSB 11
+#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
+
+#define RX_TIMING_INFO_RESERVED_OFFSET 0x00000010
+#define RX_TIMING_INFO_RESERVED_LSB 12
+#define RX_TIMING_INFO_RESERVED_MSB 31
+#define RX_TIMING_INFO_RESERVED_MASK 0xfffff000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rx_trig_info.h b/drivers/staging/fw-api/hw/peach/v1/rx_trig_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..d13b2bed819ba74a2e68e9c11b5467c445e726e0
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rx_trig_info.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RX_TRIG_INFO_H_
+#define _RX_TRIG_INFO_H_
+
+#define NUM_OF_DWORDS_RX_TRIG_INFO 2
+
+struct rx_trig_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t rx_trigger_frame_type : 2,
+ trigger_resp_type : 3,
+ reserved_0 : 27;
+ uint32_t ppdu_duration : 16,
+ unique_destination_id : 16;
+#else
+ uint32_t reserved_0 : 27,
+ trigger_resp_type : 3,
+ rx_trigger_frame_type : 2;
+ uint32_t unique_destination_id : 16,
+ ppdu_duration : 16;
+#endif
+};
+
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x00000000
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1
+#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x00000003
+
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x00000000
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4
+#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x0000001c
+
+#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x00000000
+#define RX_TRIG_INFO_RESERVED_0_LSB 5
+#define RX_TRIG_INFO_RESERVED_0_MSB 31
+#define RX_TRIG_INFO_RESERVED_0_MASK 0xffffffe0
+
+#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x00000004
+#define RX_TRIG_INFO_PPDU_DURATION_LSB 0
+#define RX_TRIG_INFO_PPDU_DURATION_MSB 15
+#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff
+
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x00000004
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 16
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 31
+#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rxpcu_early_rx_indication.h b/drivers/staging/fw-api/hw/peach/v1/rxpcu_early_rx_indication.h
new file mode 100644
index 0000000000000000000000000000000000000000..92fcdb29560faca5053e7203b656abf05f6aedf5
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rxpcu_early_rx_indication.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RXPCU_EARLY_RX_INDICATION_H_
+#define _RXPCU_EARLY_RX_INDICATION_H_
+
+#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 1
+
+struct rxpcu_early_rx_indication {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t pkt_type : 4,
+ dot11ax_su_extended : 1,
+ rate_mcs : 4,
+ dot11ax_received_ext_ru_size : 4,
+ reserved_0a : 19;
+#else
+ uint32_t reserved_0a : 19,
+ dot11ax_received_ext_ru_size : 4,
+ rate_mcs : 4,
+ dot11ax_su_extended : 1,
+ pkt_type : 4;
+#endif
+};
+
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x00000000
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3
+#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x0000000f
+
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x00000000
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x00000010
+
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x00000000
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 8
+#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x000001e0
+
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x00000000
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 9
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 12
+#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x00001e00
+
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x00000000
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 13
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31
+#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0xffffe000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rxpcu_ppdu_end_info.h b/drivers/staging/fw-api/hw/peach/v1/rxpcu_ppdu_end_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..3248374744f9e1c06f3e746474b4019b90dc8c28
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rxpcu_ppdu_end_info.h
@@ -0,0 +1,861 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RXPCU_PPDU_END_INFO_H_
+#define _RXPCU_PPDU_END_INFO_H_
+
+#include "phyrx_abort_request_info.h"
+#include "macrx_abort_request_info.h"
+#include "rxpcu_ppdu_end_layout_info.h"
+#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 31
+
+struct rxpcu_ppdu_end_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t wb_timestamp_lower_32 : 32;
+ uint32_t wb_timestamp_upper_32 : 32;
+ uint32_t rx_antenna : 24,
+ tx_ht_vht_ack : 1,
+ unsupported_mu_nc : 1,
+ otp_txbf_disable : 1,
+ previous_tlv_corrupted : 1,
+ phyrx_abort_request_info_valid : 1,
+ macrx_abort_request_info_valid : 1,
+ reserved : 2;
+ uint32_t coex_bt_tx_from_start_of_rx : 1,
+ coex_bt_tx_after_start_of_rx : 1,
+ coex_wan_tx_from_start_of_rx : 1,
+ coex_wan_tx_after_start_of_rx : 1,
+ coex_wlan_tx_from_start_of_rx : 1,
+ coex_wlan_tx_after_start_of_rx : 1,
+ mpdu_delimiter_errors_seen : 1,
+ __reserved_g_0012 : 2,
+ dialog_token : 8,
+ follow_up_dialog_token : 8,
+ bb_captured_channel : 1,
+ bb_captured_reason : 3,
+ bb_captured_timeout : 1,
+ coex_uwb_tx_after_start_of_rx : 1,
+ coex_uwb_tx_from_start_of_rx : 1;
+ uint32_t before_mpdu_count_passing_fcs : 10,
+ before_mpdu_count_failing_fcs : 10,
+ after_mpdu_count_passing_fcs : 10,
+ reserved_4 : 2;
+ uint32_t after_mpdu_count_failing_fcs : 10,
+ reserved_5 : 22;
+ uint32_t phy_timestamp_tx_lower_32 : 32;
+ uint32_t phy_timestamp_tx_upper_32 : 32;
+ uint32_t bb_length : 16,
+ bb_data : 1,
+ reserved_8 : 3,
+ first_bt_broadcast_status_details : 12;
+ uint32_t rx_ppdu_duration : 24,
+ reserved_9 : 8;
+ uint32_t ast_index : 16,
+ ast_index_valid : 1,
+ reserved_10 : 3,
+ second_bt_broadcast_status_details : 12;
+ struct phyrx_abort_request_info phyrx_abort_request_info_details;
+ struct macrx_abort_request_info macrx_abort_request_info_details;
+ uint16_t pre_bt_broadcast_status_details : 12,
+ reserved_12a : 4;
+ uint32_t non_qos_sn_info_valid : 1,
+ rts_or_trig_protected_ppdu : 1,
+ rts_or_trig_prot_type : 2,
+ reserved_13a : 2,
+ non_qos_sn_highest : 12,
+ non_qos_sn_highest_retry_setting : 1,
+ non_qos_sn_lowest : 12,
+ non_qos_sn_lowest_retry_setting : 1;
+ uint32_t qos_sn_1_info_valid : 1,
+ reserved_14a : 1,
+ qos_sn_1_tid : 4,
+ qos_sn_1_highest : 12,
+ qos_sn_1_highest_retry_setting : 1,
+ qos_sn_1_lowest : 12,
+ qos_sn_1_lowest_retry_setting : 1;
+ uint32_t qos_sn_2_info_valid : 1,
+ reserved_15a : 1,
+ qos_sn_2_tid : 4,
+ qos_sn_2_highest : 12,
+ qos_sn_2_highest_retry_setting : 1,
+ qos_sn_2_lowest : 12,
+ qos_sn_2_lowest_retry_setting : 1;
+ struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details;
+ uint32_t corrupted_due_to_fifo_delay : 1,
+ qos_sn_1_more_frag_state : 1,
+ qos_sn_1_frag_num_state : 4,
+ qos_sn_2_more_frag_state : 1,
+ qos_sn_2_frag_num_state : 4,
+ rts_or_trig_prot_non_11a : 1,
+ rts_or_trig_prot_rate_mcs : 4,
+ rts_or_trig_prot_peer_addr_15_0 : 16;
+ uint32_t rts_or_trig_prot_peer_addr_47_16 : 32;
+ uint32_t rts_or_trig_rx_count : 32;
+ uint32_t cts_or_null_tx_count : 32;
+ uint32_t rx_ppdu_end_marker : 32;
+#else
+ uint32_t wb_timestamp_lower_32 : 32;
+ uint32_t wb_timestamp_upper_32 : 32;
+ uint32_t reserved : 2,
+ macrx_abort_request_info_valid : 1,
+ phyrx_abort_request_info_valid : 1,
+ previous_tlv_corrupted : 1,
+ otp_txbf_disable : 1,
+ unsupported_mu_nc : 1,
+ tx_ht_vht_ack : 1,
+ rx_antenna : 24;
+ uint32_t coex_uwb_tx_from_start_of_rx : 1,
+ coex_uwb_tx_after_start_of_rx : 1,
+ bb_captured_timeout : 1,
+ bb_captured_reason : 3,
+ bb_captured_channel : 1,
+ follow_up_dialog_token : 8,
+ dialog_token : 8,
+ __reserved_g_0012 : 2,
+ mpdu_delimiter_errors_seen : 1,
+ coex_wlan_tx_after_start_of_rx : 1,
+ coex_wlan_tx_from_start_of_rx : 1,
+ coex_wan_tx_after_start_of_rx : 1,
+ coex_wan_tx_from_start_of_rx : 1,
+ coex_bt_tx_after_start_of_rx : 1,
+ coex_bt_tx_from_start_of_rx : 1;
+ uint32_t reserved_4 : 2,
+ after_mpdu_count_passing_fcs : 10,
+ before_mpdu_count_failing_fcs : 10,
+ before_mpdu_count_passing_fcs : 10;
+ uint32_t reserved_5 : 22,
+ after_mpdu_count_failing_fcs : 10;
+ uint32_t phy_timestamp_tx_lower_32 : 32;
+ uint32_t phy_timestamp_tx_upper_32 : 32;
+ uint32_t first_bt_broadcast_status_details : 12,
+ reserved_8 : 3,
+ bb_data : 1,
+ bb_length : 16;
+ uint32_t reserved_9 : 8,
+ rx_ppdu_duration : 24;
+ uint32_t second_bt_broadcast_status_details : 12,
+ reserved_10 : 3,
+ ast_index_valid : 1,
+ ast_index : 16;
+ struct phyrx_abort_request_info phyrx_abort_request_info_details;
+ uint32_t reserved_12a : 4,
+ pre_bt_broadcast_status_details : 12;
+ struct macrx_abort_request_info macrx_abort_request_info_details;
+ uint32_t non_qos_sn_lowest_retry_setting : 1,
+ non_qos_sn_lowest : 12,
+ non_qos_sn_highest_retry_setting : 1,
+ non_qos_sn_highest : 12,
+ reserved_13a : 2,
+ rts_or_trig_prot_type : 2,
+ rts_or_trig_protected_ppdu : 1,
+ non_qos_sn_info_valid : 1;
+ uint32_t qos_sn_1_lowest_retry_setting : 1,
+ qos_sn_1_lowest : 12,
+ qos_sn_1_highest_retry_setting : 1,
+ qos_sn_1_highest : 12,
+ qos_sn_1_tid : 4,
+ reserved_14a : 1,
+ qos_sn_1_info_valid : 1;
+ uint32_t qos_sn_2_lowest_retry_setting : 1,
+ qos_sn_2_lowest : 12,
+ qos_sn_2_highest_retry_setting : 1,
+ qos_sn_2_highest : 12,
+ qos_sn_2_tid : 4,
+ reserved_15a : 1,
+ qos_sn_2_info_valid : 1;
+ struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details;
+ uint32_t rts_or_trig_prot_peer_addr_15_0 : 16,
+ rts_or_trig_prot_rate_mcs : 4,
+ rts_or_trig_prot_non_11a : 1,
+ qos_sn_2_frag_num_state : 4,
+ qos_sn_2_more_frag_state : 1,
+ qos_sn_1_frag_num_state : 4,
+ qos_sn_1_more_frag_state : 1,
+ corrupted_due_to_fifo_delay : 1;
+ uint32_t rts_or_trig_prot_peer_addr_47_16 : 32;
+ uint32_t rts_or_trig_rx_count : 32;
+ uint32_t cts_or_null_tx_count : 32;
+ uint32_t rx_ppdu_end_marker : 32;
+#endif
+};
+
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x00000000
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0xffffffff
+
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x00000004
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 0
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 31
+#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff
+
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23
+#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x00ffffff
+
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24
+#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x01000000
+
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25
+#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x02000000
+
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26
+#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x04000000
+
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27
+#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x08000000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000
+
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x20000000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_RESERVED_LSB 30
+#define RXPCU_PPDU_END_INFO_RESERVED_MSB 31
+#define RXPCU_PPDU_END_INFO_RESERVED_MASK 0xc0000000
+
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 0
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 0
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x00000001
+
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 1
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 1
+#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x00000002
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 2
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 2
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x00000004
+
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 3
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 3
+#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x00000008
+
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 4
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 4
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x00000010
+
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 5
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 5
+#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x00000020
+
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 6
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 6
+#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x00000040
+
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 9
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 16
+#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe00
+
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 17
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 24
+#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe0000
+
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 25
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 25
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x02000000
+
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 26
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 28
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c000000
+
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 29
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 29
+#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x20000000
+
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_LSB 30
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_MSB 30
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_MASK 0x40000000
+
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_LSB 31
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_MSB 31
+#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_MASK 0x80000000
+
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x000003ff
+
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000010
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19
+#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x000ffc00
+
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x3ff00000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x00000010
+#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30
+#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31
+#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0xc0000000
+
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000014
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 0
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 9
+#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff
+
+#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x00000014
+#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 10
+#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 31
+#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc00
+
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x00000018
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0xffffffff
+
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000001c
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 0
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 31
+#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff
+
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x00000020
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15
+#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x0000ffff
+
+#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x00000020
+#define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16
+#define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16
+#define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x00010000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x00000020
+#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17
+#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19
+#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x000e0000
+
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31
+#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000
+
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x00000024
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 0
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 23
+#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff
+
+#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x00000024
+#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 24
+#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 31
+#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff000000
+
+#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x00000028
+#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0
+#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15
+#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x0000ffff
+
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x00000028
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16
+#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x00010000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x00000028
+#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17
+#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19
+#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x000e0000
+
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31
+#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 7
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 8
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 9
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_LSB 10
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MSB 10
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MASK 0x00000400
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_LSB 11
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MSB 11
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MASK 0x00000800
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_LSB 12
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MSB 12
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MASK 0x00001000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_LSB 13
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MSB 13
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MASK 0x00002000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_LSB 14
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MSB 14
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MASK 0x00004000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 15
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x00008000
+
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 31
+#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000
+
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff
+
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15
+#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00
+
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000030
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27
+#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0fff0000
+
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x00000030
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31
+#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0xf0000000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x00000034
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 0
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 0
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x00000001
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_OFFSET 0x00000034
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_LSB 1
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MSB 1
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MASK 0x00000002
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_OFFSET 0x00000034
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_LSB 2
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MSB 3
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MASK 0x0000000c
+
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x00000034
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 4
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 5
+#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x00000030
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x00000034
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 6
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 17
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc0
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x00000034
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 18
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 18
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x00040000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x00000034
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 19
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 30
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff80000
+
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x00000034
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 31
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 31
+#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x80000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x00000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x00000001
+
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x00000038
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1
+#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x00000002
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x00000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x0000003c
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x00000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x0003ffc0
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x00000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x00040000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x00000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x7ff80000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x00000038
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x80000000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000003c
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 0
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 0
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x00000001
+
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000003c
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 1
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 1
+#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x00000002
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000003c
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 2
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 5
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000003c
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 6
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 17
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc0
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000003c
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 18
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 18
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x00040000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000003c
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 19
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 30
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff80000
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000003c
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 31
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 31
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x80000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x00000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x00000003
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x00000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x000000fc
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x00000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x00003f00
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x00000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x000fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x00000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x03f00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000040
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x00000044
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 5
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000044
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 11
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000044
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 12
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 17
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x00000044
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 18
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 23
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x00000044
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 24
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 30
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x00000044
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x80000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x00000048
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0xf0000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000004c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000004c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000004c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000004c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 21
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 27
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000004c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf0000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x00000050
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0xe0000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x00000054
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 6
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000054
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 14
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000054
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000054
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000054
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x00000054
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 25
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x00000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x000000ff
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x00000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x00ff0000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x00000058
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0xff000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000005c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 8
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 15
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff00
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000005c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 16
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 23
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000005c
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 24
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff000000
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x00000060
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0xffffffff
+
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x00000064
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 0
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 31
+#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff
+
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x00000068
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0
+#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x00000001
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x00000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x00000002
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x00000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5
+#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x0000003c
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x00000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x00000040
+
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x00000068
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10
+#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x00000780
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_OFFSET 0x00000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_LSB 11
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MSB 11
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MASK 0x00000800
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_OFFSET 0x00000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_LSB 12
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MSB 15
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MASK 0x0000f000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_OFFSET 0x00000068
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_LSB 16
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MSB 31
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MASK 0xffff0000
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_OFFSET 0x0000006c
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_LSB 0
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MSB 31
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MASK 0xffffffff
+
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_OFFSET 0x00000070
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_LSB 0
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MSB 31
+#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MASK 0xffffffff
+
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_OFFSET 0x00000074
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_LSB 0
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MSB 31
+#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MASK 0xffffffff
+
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x00000078
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 0
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 31
+#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rxpcu_ppdu_end_layout_info.h b/drivers/staging/fw-api/hw/peach/v1/rxpcu_ppdu_end_layout_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..9f8f00dd9d5bd3f1c2c1012b86b5f01a6cb5648d
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rxpcu_ppdu_end_layout_info.h
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_
+#define _RXPCU_PPDU_END_LAYOUT_INFO_H_
+
+#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10
+
+struct rxpcu_ppdu_end_layout_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t rssi_legacy_offset : 2,
+ l_sig_a_offset : 6,
+ l_sig_b_offset : 6,
+ ht_sig_offset : 6,
+ vht_sig_a_offset : 6,
+ repeat_l_sig_a_offset : 6;
+ uint32_t he_sig_a_su_offset : 6,
+ he_sig_a_mu_dl_offset : 6,
+ he_sig_a_mu_ul_offset : 6,
+ generic_u_sig_offset : 6,
+ rssi_ht_offset : 7,
+ reserved_1a : 1;
+ uint32_t vht_sig_b_su20_offset : 7,
+ vht_sig_b_su40_offset : 7,
+ vht_sig_b_su80_offset : 7,
+ vht_sig_b_su160_offset : 7,
+ reserved_2a : 4;
+ uint32_t vht_sig_b_mu20_offset : 7,
+ vht_sig_b_mu40_offset : 7,
+ vht_sig_b_mu80_offset : 7,
+ vht_sig_b_mu160_offset : 7,
+ reserved_3a : 4;
+ uint32_t he_sig_b1_mu_offset : 7,
+ he_sig_b2_mu_offset : 7,
+ he_sig_b2_ofdma_offset : 7,
+ first_generic_eht_sig_offset : 7,
+ multiple_generic_eht_sig_included : 1,
+ reserved_4a : 3;
+ uint32_t common_user_info_offset : 7,
+ first_debug_info_offset : 8,
+ multiple_debug_info_included : 1,
+ first_other_receive_info_offset : 8,
+ multiple_other_receive_info_included : 1,
+ reserved_5a : 7;
+ uint32_t data_done_offset : 8,
+ generated_cbf_details_offset : 8,
+ pkt_end_part1_offset : 8,
+ location_offset : 8;
+ uint32_t __reserved_g_0011 : 8,
+ pkt_end_offset : 8,
+ abort_request_ack_offset : 8,
+ reserved_7a : 8;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+#else
+ uint32_t repeat_l_sig_a_offset : 6,
+ vht_sig_a_offset : 6,
+ ht_sig_offset : 6,
+ l_sig_b_offset : 6,
+ l_sig_a_offset : 6,
+ rssi_legacy_offset : 2;
+ uint32_t reserved_1a : 1,
+ rssi_ht_offset : 7,
+ generic_u_sig_offset : 6,
+ he_sig_a_mu_ul_offset : 6,
+ he_sig_a_mu_dl_offset : 6,
+ he_sig_a_su_offset : 6;
+ uint32_t reserved_2a : 4,
+ vht_sig_b_su160_offset : 7,
+ vht_sig_b_su80_offset : 7,
+ vht_sig_b_su40_offset : 7,
+ vht_sig_b_su20_offset : 7;
+ uint32_t reserved_3a : 4,
+ vht_sig_b_mu160_offset : 7,
+ vht_sig_b_mu80_offset : 7,
+ vht_sig_b_mu40_offset : 7,
+ vht_sig_b_mu20_offset : 7;
+ uint32_t reserved_4a : 3,
+ multiple_generic_eht_sig_included : 1,
+ first_generic_eht_sig_offset : 7,
+ he_sig_b2_ofdma_offset : 7,
+ he_sig_b2_mu_offset : 7,
+ he_sig_b1_mu_offset : 7;
+ uint32_t reserved_5a : 7,
+ multiple_other_receive_info_included : 1,
+ first_other_receive_info_offset : 8,
+ multiple_debug_info_included : 1,
+ first_debug_info_offset : 8,
+ common_user_info_offset : 7;
+ uint32_t location_offset : 8,
+ pkt_end_part1_offset : 8,
+ generated_cbf_details_offset : 8,
+ data_done_offset : 8;
+ uint32_t reserved_7a : 8,
+ abort_request_ack_offset : 8,
+ pkt_end_offset : 8,
+ __reserved_g_0011 : 8;
+ uint32_t reserved_8a : 32;
+ uint32_t reserved_9a : 32;
+#endif
+};
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13
+#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19
+#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31
+#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30
+#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27
+#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20
+#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6
+#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23
+#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24
+#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7
+#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31
+#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15
+#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23
+#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff
+
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31
+#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/rxpt_classify_info.h b/drivers/staging/fw-api/hw/peach/v1/rxpt_classify_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..e87054cf2dfb853a84eb134fa945de5b82128e9b
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/rxpt_classify_info.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _RXPT_CLASSIFY_INFO_H_
+#define _RXPT_CLASSIFY_INFO_H_
+
+#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1
+
+struct rxpt_classify_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t reo_destination_indication : 5,
+ lmac_peer_id_msb : 2,
+ use_flow_id_toeplitz_clfy : 1,
+ pkt_selection_fp_ucast_data : 1,
+ pkt_selection_fp_mcast_data : 1,
+ pkt_selection_fp_1000 : 1,
+ rxdma0_source_ring_selection : 3,
+ rxdma0_destination_ring_selection : 3,
+ mcast_echo_drop_enable : 1,
+ wds_learning_detect_en : 1,
+ intrabss_check_en : 1,
+ use_ppe : 1,
+ ppe_routing_enable : 1,
+ cce_source_sel_en : 1,
+ reserved_0b : 9;
+#else
+ uint32_t reserved_0b : 9,
+ cce_source_sel_en : 1,
+ ppe_routing_enable : 1,
+ use_ppe : 1,
+ intrabss_check_en : 1,
+ wds_learning_detect_en : 1,
+ mcast_echo_drop_enable : 1,
+ rxdma0_destination_ring_selection : 3,
+ rxdma0_source_ring_selection : 3,
+ pkt_selection_fp_1000 : 1,
+ pkt_selection_fp_mcast_data : 1,
+ pkt_selection_fp_ucast_data : 1,
+ use_flow_id_toeplitz_clfy : 1,
+ lmac_peer_id_msb : 2,
+ reo_destination_indication : 5;
+#endif
+};
+
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB 0
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB 4
+#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB 5
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB 6
+#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK 0x00000060
+
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7
+#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
+
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB 8
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB 8
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
+
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB 9
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB 9
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
+
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB 10
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB 10
+#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK 0x00000400
+
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB 11
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB 13
+#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800
+
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB 14
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB 16
+#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000
+
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB 17
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB 17
+#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000
+
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB 18
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB 18
+#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK 0x00040000
+
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB 19
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB 19
+#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK 0x00080000
+
+#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_USE_PPE_LSB 20
+#define RXPT_CLASSIFY_INFO_USE_PPE_MSB 20
+#define RXPT_CLASSIFY_INFO_USE_PPE_MASK 0x00100000
+
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB 21
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB 21
+#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK 0x00200000
+
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_LSB 22
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MSB 22
+#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MASK 0x00400000
+
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB 23
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB 31
+#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK 0xff800000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/seq_hwio.h b/drivers/staging/fw-api/hw/peach/v1/seq_hwio.h
new file mode 100644
index 0000000000000000000000000000000000000000..576abae9ee69e8340f6a058f4e0fbc3f3ae55590
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/seq_hwio.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef __SEQ_H__
+#define __SEQ_H__
+
+#include "HALhwio.h"
+
+#define SEQ_INH(base, regtype, reg) \
+ SEQ_##regtype##_INH(base, reg)
+
+#define SEQ_INMH(base, regtype, reg, mask) \
+ SEQ_##regtype##_INMH(base, reg, mask)
+
+#define SEQ_INFH(base, regtype, reg, fld) \
+ (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld))
+
+#define SEQ_OUTH(base, regtype, reg, val) \
+ SEQ_##regtype##_OUTH(base, reg, val)
+
+#define SEQ_OUTMH(base, regtype, reg, mask, val) \
+ SEQ_##regtype##_OUTMH(base, reg, mask, val)
+
+#define SEQ_OUTFH(base, regtype, reg, fld, val) \
+ SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld))
+
+typedef enum {
+ SEC,
+ MS,
+ US,
+ NS
+} SEQ_TimeUnit;
+
+extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit);
+
+extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt);
+
+#endif
+
diff --git a/drivers/staging/fw-api/hw/peach/v1/tcl_data_cmd.h b/drivers/staging/fw-api/hw/peach/v1/tcl_data_cmd.h
new file mode 100644
index 0000000000000000000000000000000000000000..388b6dd7a30187b249c4c8d66db391545daefa6f
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tcl_data_cmd.h
@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TCL_DATA_CMD_H_
+#define _TCL_DATA_CMD_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_TCL_DATA_CMD 8
+
+struct tcl_data_cmd {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct buffer_addr_info buf_addr_info;
+ uint32_t tcl_cmd_type : 1,
+ buf_or_ext_desc_type : 1,
+ bank_id : 6,
+ tx_notify_frame : 3,
+ header_length_read_sel : 1,
+ buffer_timestamp : 19,
+ buffer_timestamp_valid : 1;
+ uint32_t reserved_3a : 16,
+ tcl_cmd_number : 16;
+ uint32_t data_length : 16,
+ ipv4_checksum_en : 1,
+ udp_over_ipv4_checksum_en : 1,
+ udp_over_ipv6_checksum_en : 1,
+ tcp_over_ipv4_checksum_en : 1,
+ tcp_over_ipv6_checksum_en : 1,
+ to_fw : 1,
+ reserved_4a : 1,
+ packet_offset : 9;
+ uint32_t hlos_tid_overwrite : 1,
+ flow_override_enable : 1,
+ who_classify_info_sel : 2,
+ hlos_tid : 4,
+ flow_override : 1,
+ pmac_id : 2,
+ msdu_color : 2,
+ reserved_5a : 11,
+ vdev_id : 8;
+ uint32_t search_index : 20,
+ cache_set_num : 4,
+ index_lookup_override : 1,
+ reserved_6a : 7;
+ uint32_t reserved_7a : 20,
+ ring_id : 8,
+ looping_count : 4;
+#else
+ struct buffer_addr_info buf_addr_info;
+ uint32_t buffer_timestamp_valid : 1,
+ buffer_timestamp : 19,
+ header_length_read_sel : 1,
+ tx_notify_frame : 3,
+ bank_id : 6,
+ buf_or_ext_desc_type : 1,
+ tcl_cmd_type : 1;
+ uint32_t tcl_cmd_number : 16,
+ reserved_3a : 16;
+ uint32_t packet_offset : 9,
+ reserved_4a : 1,
+ to_fw : 1,
+ tcp_over_ipv6_checksum_en : 1,
+ tcp_over_ipv4_checksum_en : 1,
+ udp_over_ipv6_checksum_en : 1,
+ udp_over_ipv4_checksum_en : 1,
+ ipv4_checksum_en : 1,
+ data_length : 16;
+ uint32_t vdev_id : 8,
+ reserved_5a : 11,
+ msdu_color : 2,
+ pmac_id : 2,
+ flow_override : 1,
+ hlos_tid : 4,
+ who_classify_info_sel : 2,
+ flow_override_enable : 1,
+ hlos_tid_overwrite : 1;
+ uint32_t reserved_6a : 7,
+ index_lookup_override : 1,
+ cache_set_num : 4,
+ search_index : 20;
+ uint32_t looping_count : 4,
+ ring_id : 8,
+ reserved_7a : 20;
+#endif
+};
+
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET 0x00000008
+#define TCL_DATA_CMD_TCL_CMD_TYPE_LSB 0
+#define TCL_DATA_CMD_TCL_CMD_TYPE_MSB 0
+#define TCL_DATA_CMD_TCL_CMD_TYPE_MASK 0x00000001
+
+#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008
+#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 1
+#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB 1
+#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000002
+
+#define TCL_DATA_CMD_BANK_ID_OFFSET 0x00000008
+#define TCL_DATA_CMD_BANK_ID_LSB 2
+#define TCL_DATA_CMD_BANK_ID_MSB 7
+#define TCL_DATA_CMD_BANK_ID_MASK 0x000000fc
+
+#define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET 0x00000008
+#define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB 8
+#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB 10
+#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK 0x00000700
+
+#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET 0x00000008
+#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB 11
+#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB 11
+#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK 0x00000800
+
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000008
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB 12
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB 30
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK 0x7ffff000
+
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000008
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB 31
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB 31
+#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x80000000
+
+#define TCL_DATA_CMD_RESERVED_3A_OFFSET 0x0000000c
+#define TCL_DATA_CMD_RESERVED_3A_LSB 0
+#define TCL_DATA_CMD_RESERVED_3A_MSB 15
+#define TCL_DATA_CMD_RESERVED_3A_MASK 0x0000ffff
+
+#define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET 0x0000000c
+#define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB 16
+#define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB 31
+#define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK 0xffff0000
+
+#define TCL_DATA_CMD_DATA_LENGTH_OFFSET 0x00000010
+#define TCL_DATA_CMD_DATA_LENGTH_LSB 0
+#define TCL_DATA_CMD_DATA_LENGTH_MSB 15
+#define TCL_DATA_CMD_DATA_LENGTH_MASK 0x0000ffff
+
+#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET 0x00000010
+#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB 16
+#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB 16
+#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK 0x00010000
+
+#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010
+#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17
+#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB 17
+#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000
+
+#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010
+#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18
+#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB 18
+#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000
+
+#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010
+#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19
+#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB 19
+#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000
+
+#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010
+#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20
+#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB 20
+#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000
+
+#define TCL_DATA_CMD_TO_FW_OFFSET 0x00000010
+#define TCL_DATA_CMD_TO_FW_LSB 21
+#define TCL_DATA_CMD_TO_FW_MSB 21
+#define TCL_DATA_CMD_TO_FW_MASK 0x00200000
+
+#define TCL_DATA_CMD_RESERVED_4A_OFFSET 0x00000010
+#define TCL_DATA_CMD_RESERVED_4A_LSB 22
+#define TCL_DATA_CMD_RESERVED_4A_MSB 22
+#define TCL_DATA_CMD_RESERVED_4A_MASK 0x00400000
+
+#define TCL_DATA_CMD_PACKET_OFFSET_OFFSET 0x00000010
+#define TCL_DATA_CMD_PACKET_OFFSET_LSB 23
+#define TCL_DATA_CMD_PACKET_OFFSET_MSB 31
+#define TCL_DATA_CMD_PACKET_OFFSET_MASK 0xff800000
+
+#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000014
+#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB 0
+#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB 0
+#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK 0x00000001
+
+#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000014
+#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB 1
+#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB 1
+#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00000002
+
+#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET 0x00000014
+#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB 2
+#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB 3
+#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK 0x0000000c
+
+#define TCL_DATA_CMD_HLOS_TID_OFFSET 0x00000014
+#define TCL_DATA_CMD_HLOS_TID_LSB 4
+#define TCL_DATA_CMD_HLOS_TID_MSB 7
+#define TCL_DATA_CMD_HLOS_TID_MASK 0x000000f0
+
+#define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET 0x00000014
+#define TCL_DATA_CMD_FLOW_OVERRIDE_LSB 8
+#define TCL_DATA_CMD_FLOW_OVERRIDE_MSB 8
+#define TCL_DATA_CMD_FLOW_OVERRIDE_MASK 0x00000100
+
+#define TCL_DATA_CMD_PMAC_ID_OFFSET 0x00000014
+#define TCL_DATA_CMD_PMAC_ID_LSB 9
+#define TCL_DATA_CMD_PMAC_ID_MSB 10
+#define TCL_DATA_CMD_PMAC_ID_MASK 0x00000600
+
+#define TCL_DATA_CMD_MSDU_COLOR_OFFSET 0x00000014
+#define TCL_DATA_CMD_MSDU_COLOR_LSB 11
+#define TCL_DATA_CMD_MSDU_COLOR_MSB 12
+#define TCL_DATA_CMD_MSDU_COLOR_MASK 0x00001800
+
+#define TCL_DATA_CMD_RESERVED_5A_OFFSET 0x00000014
+#define TCL_DATA_CMD_RESERVED_5A_LSB 13
+#define TCL_DATA_CMD_RESERVED_5A_MSB 23
+#define TCL_DATA_CMD_RESERVED_5A_MASK 0x00ffe000
+
+#define TCL_DATA_CMD_VDEV_ID_OFFSET 0x00000014
+#define TCL_DATA_CMD_VDEV_ID_LSB 24
+#define TCL_DATA_CMD_VDEV_ID_MSB 31
+#define TCL_DATA_CMD_VDEV_ID_MASK 0xff000000
+
+#define TCL_DATA_CMD_SEARCH_INDEX_OFFSET 0x00000018
+#define TCL_DATA_CMD_SEARCH_INDEX_LSB 0
+#define TCL_DATA_CMD_SEARCH_INDEX_MSB 19
+#define TCL_DATA_CMD_SEARCH_INDEX_MASK 0x000fffff
+
+#define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET 0x00000018
+#define TCL_DATA_CMD_CACHE_SET_NUM_LSB 20
+#define TCL_DATA_CMD_CACHE_SET_NUM_MSB 23
+#define TCL_DATA_CMD_CACHE_SET_NUM_MASK 0x00f00000
+
+#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET 0x00000018
+#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB 24
+#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB 24
+#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK 0x01000000
+
+#define TCL_DATA_CMD_RESERVED_6A_OFFSET 0x00000018
+#define TCL_DATA_CMD_RESERVED_6A_LSB 25
+#define TCL_DATA_CMD_RESERVED_6A_MSB 31
+#define TCL_DATA_CMD_RESERVED_6A_MASK 0xfe000000
+
+#define TCL_DATA_CMD_RESERVED_7A_OFFSET 0x0000001c
+#define TCL_DATA_CMD_RESERVED_7A_LSB 0
+#define TCL_DATA_CMD_RESERVED_7A_MSB 19
+#define TCL_DATA_CMD_RESERVED_7A_MASK 0x000fffff
+
+#define TCL_DATA_CMD_RING_ID_OFFSET 0x0000001c
+#define TCL_DATA_CMD_RING_ID_LSB 20
+#define TCL_DATA_CMD_RING_ID_MSB 27
+#define TCL_DATA_CMD_RING_ID_MASK 0x0ff00000
+
+#define TCL_DATA_CMD_LOOPING_COUNT_OFFSET 0x0000001c
+#define TCL_DATA_CMD_LOOPING_COUNT_LSB 28
+#define TCL_DATA_CMD_LOOPING_COUNT_MSB 31
+#define TCL_DATA_CMD_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tcl_gse_cmd.h b/drivers/staging/fw-api/hw/peach/v1/tcl_gse_cmd.h
new file mode 100644
index 0000000000000000000000000000000000000000..9ab07f469049f5f59bf9dc0b4cadb98a76352211
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tcl_gse_cmd.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TCL_GSE_CMD_H_
+#define _TCL_GSE_CMD_H_
+
+#define NUM_OF_DWORDS_TCL_GSE_CMD 8
+
+struct tcl_gse_cmd {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t control_buffer_addr_31_0 : 32;
+ uint32_t control_buffer_addr_39_32 : 8,
+ gse_ctrl : 4,
+ gse_sel : 1,
+ status_destination_ring_id : 1,
+ swap : 1,
+ index_search_en : 1,
+ cache_set_num : 4,
+ reserved_1a : 12;
+ uint32_t tcl_cmd_type : 1,
+ reserved_2a : 31;
+ uint32_t cmd_meta_data_31_0 : 32;
+ uint32_t cmd_meta_data_63_32 : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 20,
+ ring_id : 8,
+ looping_count : 4;
+#else
+ uint32_t control_buffer_addr_31_0 : 32;
+ uint32_t reserved_1a : 12,
+ cache_set_num : 4,
+ index_search_en : 1,
+ swap : 1,
+ status_destination_ring_id : 1,
+ gse_sel : 1,
+ gse_ctrl : 4,
+ control_buffer_addr_39_32 : 8;
+ uint32_t reserved_2a : 31,
+ tcl_cmd_type : 1;
+ uint32_t cmd_meta_data_31_0 : 32;
+ uint32_t cmd_meta_data_63_32 : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t looping_count : 4,
+ ring_id : 8,
+ reserved_7a : 20;
+#endif
+};
+
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7
+#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004
+#define TCL_GSE_CMD_GSE_CTRL_LSB 8
+#define TCL_GSE_CMD_GSE_CTRL_MSB 11
+#define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00
+
+#define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004
+#define TCL_GSE_CMD_GSE_SEL_LSB 12
+#define TCL_GSE_CMD_GSE_SEL_MSB 12
+#define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000
+
+#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004
+#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13
+#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13
+#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000
+
+#define TCL_GSE_CMD_SWAP_OFFSET 0x00000004
+#define TCL_GSE_CMD_SWAP_LSB 14
+#define TCL_GSE_CMD_SWAP_MSB 14
+#define TCL_GSE_CMD_SWAP_MASK 0x00004000
+
+#define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004
+#define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15
+#define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15
+#define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000
+
+#define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004
+#define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16
+#define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19
+#define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000
+
+#define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004
+#define TCL_GSE_CMD_RESERVED_1A_LSB 20
+#define TCL_GSE_CMD_RESERVED_1A_MSB 31
+#define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000
+
+#define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008
+#define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0
+#define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0
+#define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001
+
+#define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008
+#define TCL_GSE_CMD_RESERVED_2A_LSB 1
+#define TCL_GSE_CMD_RESERVED_2A_MSB 31
+#define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe
+
+#define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c
+#define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0
+#define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31
+#define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff
+
+#define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010
+#define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0
+#define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31
+#define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff
+
+#define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014
+#define TCL_GSE_CMD_RESERVED_5A_LSB 0
+#define TCL_GSE_CMD_RESERVED_5A_MSB 31
+#define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff
+
+#define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018
+#define TCL_GSE_CMD_RESERVED_6A_LSB 0
+#define TCL_GSE_CMD_RESERVED_6A_MSB 31
+#define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff
+
+#define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c
+#define TCL_GSE_CMD_RESERVED_7A_LSB 0
+#define TCL_GSE_CMD_RESERVED_7A_MSB 19
+#define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff
+
+#define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c
+#define TCL_GSE_CMD_RING_ID_LSB 20
+#define TCL_GSE_CMD_RING_ID_MSB 27
+#define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000
+
+#define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c
+#define TCL_GSE_CMD_LOOPING_COUNT_LSB 28
+#define TCL_GSE_CMD_LOOPING_COUNT_MSB 31
+#define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tcl_status_ring.h b/drivers/staging/fw-api/hw/peach/v1/tcl_status_ring.h
new file mode 100644
index 0000000000000000000000000000000000000000..8930533a442e9121dee12821b9ddce01b452eacb
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tcl_status_ring.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TCL_STATUS_RING_H_
+#define _TCL_STATUS_RING_H_
+
+#define NUM_OF_DWORDS_TCL_STATUS_RING 8
+
+struct tcl_status_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t gse_ctrl : 4,
+ ase_fse_sel : 1,
+ cache_op_res : 2,
+ index_search_en : 1,
+ msdu_cnt_n : 24;
+ uint32_t msdu_byte_cnt_n : 32;
+ uint32_t msdu_timestmp_n : 32;
+ uint32_t cmd_meta_data_31_0 : 32;
+ uint32_t cmd_meta_data_63_32 : 32;
+ uint32_t hash_indx_val : 20,
+ cache_set_num : 4,
+ reserved_5a : 8;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 20,
+ ring_id : 8,
+ looping_count : 4;
+#else
+ uint32_t msdu_cnt_n : 24,
+ index_search_en : 1,
+ cache_op_res : 2,
+ ase_fse_sel : 1,
+ gse_ctrl : 4;
+ uint32_t msdu_byte_cnt_n : 32;
+ uint32_t msdu_timestmp_n : 32;
+ uint32_t cmd_meta_data_31_0 : 32;
+ uint32_t cmd_meta_data_63_32 : 32;
+ uint32_t reserved_5a : 8,
+ cache_set_num : 4,
+ hash_indx_val : 20;
+ uint32_t reserved_6a : 32;
+ uint32_t looping_count : 4,
+ ring_id : 8,
+ reserved_7a : 20;
+#endif
+};
+
+#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000
+#define TCL_STATUS_RING_GSE_CTRL_LSB 0
+#define TCL_STATUS_RING_GSE_CTRL_MSB 3
+#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f
+
+#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000
+#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4
+#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4
+#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010
+
+#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000
+#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5
+#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6
+#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060
+
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7
+#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080
+
+#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000
+#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8
+#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31
+#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00
+
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31
+#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff
+
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31
+#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff
+
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31
+#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff
+
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31
+#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff
+
+#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014
+#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0
+#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19
+#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff
+
+#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014
+#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20
+#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23
+#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000
+
+#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014
+#define TCL_STATUS_RING_RESERVED_5A_LSB 24
+#define TCL_STATUS_RING_RESERVED_5A_MSB 31
+#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000
+
+#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018
+#define TCL_STATUS_RING_RESERVED_6A_LSB 0
+#define TCL_STATUS_RING_RESERVED_6A_MSB 31
+#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff
+
+#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c
+#define TCL_STATUS_RING_RESERVED_7A_LSB 0
+#define TCL_STATUS_RING_RESERVED_7A_MSB 19
+#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff
+
+#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c
+#define TCL_STATUS_RING_RING_ID_LSB 20
+#define TCL_STATUS_RING_RING_ID_MSB 27
+#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000
+
+#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c
+#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28
+#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31
+#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tlv_hdr.h b/drivers/staging/fw-api/hw/peach/v1/tlv_hdr.h
new file mode 100644
index 0000000000000000000000000000000000000000..6d25ff3047dcd4eda89e5583d950a856404ac4c4
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tlv_hdr.h
@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TLV_HDR_H_
+#define _TLV_HDR_H_
+
+#define _TLV_USERID_WIDTH_ 6
+#define _TLV_DATA_WIDTH_ 32
+#define _TLV_TAG_WIDTH_ 9
+
+#define _TLV_MRV_EN_LEN_WIDTH_ 9
+#define _TLV_MRV_DIS_LEN_WIDTH_ 12
+
+#define _TLV_16_DATA_WIDTH_ 16
+#define _TLV_16_TAG_WIDTH_ 5
+#define _TLV_16_LEN_WIDTH_ 4
+#define _TLV_CTAG_WIDTH_ 5
+#define _TLV_44_DATA_WIDTH_ 44
+#define _TLV_64_DATA_WIDTH_ 64
+#define _TLV_76_DATA_WIDTH_ 64
+#define _TLV_CDATA_WIDTH_ 32
+#define _TLV_CDATA_76_WIDTH_ 64
+
+struct tlv_usr_16_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint16_t tlv_cflg_reserved : 1,
+ tlv_tag : _TLV_16_TAG_WIDTH_,
+ tlv_len : _TLV_16_LEN_WIDTH_,
+ tlv_usrid : _TLV_USERID_WIDTH_;
+#else
+ uint16_t tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_len : _TLV_16_LEN_WIDTH_,
+ tlv_tag : _TLV_16_TAG_WIDTH_,
+ tlv_cflg_reserved : 1;
+#endif
+};
+
+struct tlv_16_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint16_t tlv_cflg_reserved : 1,
+ tlv_len : _TLV_16_LEN_WIDTH_,
+ tlv_tag : _TLV_16_TAG_WIDTH_,
+ tlv_reserved : 6;
+#else
+ uint16_t tlv_reserved : 6,
+ tlv_tag : _TLV_16_TAG_WIDTH_,
+ tlv_len : _TLV_16_LEN_WIDTH_,
+ tlv_cflg_reserved : 1;
+#endif
+};
+
+struct tlv_mac_usr_32_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv_cflg_reserved : 1,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_src_linkid : 3,
+ tlv_mrv : 1,
+ tlv_usrid : _TLV_USERID_WIDTH_;
+#else
+ uint32_t tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_mrv : 1,
+ tlv_src_linkid : 3,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_cflg_reserved : 1;
+#endif
+};
+
+struct tlv_mac_32_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv_cflg_reserved : 1,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_src_linkid : 3,
+ tlv_mrv : 1,
+ tlv_reserved : 6;
+#else
+ uint32_t tlv_reserved : 6,
+ tlv_mrv : 1,
+ tlv_src_linkid : 3,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_cflg_reserved : 1;
+#endif
+};
+
+struct tlv_mac_usr_64_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint64_t tlv_cflg_reserved : 1,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_src_linkid : 3,
+ tlv_mrv : 1,
+ tlv_usrid : _TLV_USERID_WIDTH_,
+#else
+ uint64_t tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_mrv : 1,
+ tlv_src_linkid : 3,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_cflg_reserved : 1,
+#endif
+ tlv_reserved : 32;
+};
+
+struct tlv_mac_64_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint64_t tlv_cflg_reserved : 1,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_src_linkid : 3,
+ tlv_mrv : 1,
+ tlv_reserved : 38;
+#else
+ uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_,
+ tlv_mrv : 1,
+ tlv_src_linkid : 3,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_cflg_reserved : 1,
+ tlv_reserved : 32;
+#endif
+};
+
+struct tlv_mac_usr_44_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint64_t tlv_compression : 1,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_src_linkid : 3,
+ tlv_mrv : 1,
+ tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_reserved : 10,
+ pad_44to64_bit : 22;
+#else
+ uint64_t tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_mrv : 1,
+ tlv_src_linkid : 3,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_compression : 1,
+ pad_44to64_bit : 22,
+ tlv_reserved : 10;
+#endif
+};
+
+struct tlv_mac_44_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint64_t tlv_compression : 1,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_src_linkid : 3,
+ tlv_mrv : 1,
+ tlv_reserved : 16,
+ pad_44to64_bit : 22;
+#else
+ uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_,
+ tlv_mrv : 1,
+ tlv_src_linkid : 3,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_compression : 1,
+ pad_44to64_bit : 22,
+ tlv_reserved : 10;
+#endif
+};
+
+struct tlv_mac_usr_76_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint64_t tlv_compression : 1,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_src_linkid : 3,
+ tlv_mrv : 1,
+ tlv_usrid : _TLV_USERID_WIDTH_,
+#else
+ uint64_t tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_mrv : 1,
+ tlv_src_linkid : 3,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_compression : 1,
+#endif
+ tlv_reserved : 32;
+ uint64_t pad_64to128_bit : 64;
+};
+
+struct tlv_mac_76_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint64_t tlv_compression : 1,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_src_linkid : 3,
+ tlv_mrv : 1,
+ tlv_reserved : 38;
+#else
+ uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_,
+ tlv_mrv : 1,
+ tlv_src_linkid : 3,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_compression : 1,
+ tlv_reserved : 32;
+#endif
+ uint64_t pad_64to128_bit : 64;
+};
+
+struct tlv_usr_c_44_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint64_t tlv_compression : 1,
+ tlv_ctag : _TLV_CTAG_WIDTH_,
+ tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_cdata : _TLV_CDATA_WIDTH_,
+ pad_44to64_bit : 20;
+#else
+ uint64_t tlv_cdata_lower_20 : 20,
+ tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_ctag : _TLV_CTAG_WIDTH_,
+ tlv_compression : 1,
+ pad_44to64_bit : 20,
+ tlv_cdata_upper_12 : 12;
+#endif
+};
+
+struct tlv_usr_c_76_tlword_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint64_t tlv_compression : 1,
+ tlv_ctag : _TLV_CTAG_WIDTH_,
+ tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_cdata_lower_52 : 52;
+ uint64_t tlv_cdata_upper_12 : 12,
+ pad_76to128_bit : 52;
+#else
+ uint64_t tlv_cdata_lower_20 : 20,
+ tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_ctag : _TLV_CTAG_WIDTH_,
+ tlv_compression : 1,
+ tlv_cdata_middle_32 : 32;
+ uint64_t pad_76to96_bit : 20,
+ tlv_cdata_upper_12 : 12,
+ pad_96to128_bit : 32;
+#endif
+};
+
+struct tlv_usr_32_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv_cflg_reserved : 1,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_src_linkid : 3,
+ tlv_mrv : 1,
+ tlv_usrid : _TLV_USERID_WIDTH_;
+#else
+ uint32_t tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_mrv : 1,
+ tlv_src_linkid : 3,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_cflg_reserved : 1;
+#endif
+};
+
+struct tlv_32_hdr {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv_cflg_reserved : 1,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_src_linkid : 3,
+ tlv_mrv : 1,
+ tlv_reserved : 6;
+#else
+ uint32_t tlv_reserved : 6,
+ tlv_mrv : 1,
+ tlv_src_linkid : 3,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_cflg_reserved : 1;
+#endif
+};
+
+struct tlv_mlo_usr_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv_cflg_reserved : 1,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_len : _TLV_MRV_EN_LEN_WIDTH_,
+ tlv_dst_linkid : 3,
+ tlv_src_linkid : 3,
+ tlv_mrv : 1,
+ tlv_usrid : _TLV_USERID_WIDTH_;
+#else
+ uint32_t tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_mrv : 1,
+ tlv_src_linkid : 3,
+ tlv_dst_linkid : 3,
+ tlv_len : _TLV_MRV_EN_LEN_WIDTH_,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_cflg_reserved : 1;
+#endif
+ uint32_t pad_32to64_bit : 32;
+};
+
+struct tlv_mlo_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv_cflg_reserved : 1,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_len : _TLV_MRV_EN_LEN_WIDTH_,
+ tlv_dst_linkid : 3,
+ tlv_src_linkid : 3,
+ tlv_mrv : 1,
+ tlv_reserved : _TLV_USERID_WIDTH_;
+#else
+ uint32_t tlv_reserved : _TLV_USERID_WIDTH_,
+ tlv_mrv : 1,
+ tlv_src_linkid : 3,
+ tlv_dst_linkid : 3,
+ tlv_len : _TLV_MRV_EN_LEN_WIDTH_,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_cflg_reserved : 1;
+#endif
+ uint32_t pad_32to64_bit : 32;
+};
+
+struct tlv_mac_usr_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv_cflg_reserved : 1,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_src_linkid : 3,
+ tlv_mrv : 1,
+ tlv_usrid : _TLV_USERID_WIDTH_;
+#else
+ uint32_t tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_mrv : 1,
+ tlv_src_linkid : 3,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_cflg_reserved : 1;
+#endif
+ uint32_t pad_32to64_bit : 32;
+};
+
+struct tlv_mac_64_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv_cflg_reserved : 1,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_src_linkid : 3,
+ tlv_mrv : 1,
+ tlv_reserved : _TLV_USERID_WIDTH_;
+#else
+ uint32_t tlv_reserved : _TLV_USERID_WIDTH_,
+ tlv_mrv : 1,
+ tlv_src_linkid : 3,
+ tlv_len : _TLV_MRV_DIS_LEN_WIDTH_,
+ tlv_tag : _TLV_TAG_WIDTH_,
+ tlv_cflg_reserved : 1;
+#endif
+ uint32_t pad_32to64_bit : 32;
+};
+
+struct tlv_usr_c_44_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv_compression : 1,
+ tlv_ctag : _TLV_CTAG_WIDTH_,
+ tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_cdata_lower_20 : 20;
+ uint32_t tlv_cdata_upper_12 : 12,
+ pad_44to64_bit : 20;
+#else
+ uint32_t tlv_cdata_lower_20 : 20,
+ tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_ctag : _TLV_CTAG_WIDTH_,
+ tlv_compression : 1;
+ uint32_t pad_44to64_bit : 20,
+ tlv_cdata_upper_12 : 12;
+#endif
+};
+
+struct tlv_usr_c_76_tlw32_t {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tlv_compression : 1,
+ tlv_ctag : _TLV_CTAG_WIDTH_,
+ tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_cdata_lower_20 : 20;
+ uint32_t tlv_cdata_middle_32 : 32;
+ uint32_t tlv_cdata_upper_12 : 12,
+ pad_76to96_bit : 20;
+ uint32_t pad_96to128_bit : 32;
+#else
+ uint32_t tlv_cdata_lower_20 : 20,
+ tlv_usrid : _TLV_USERID_WIDTH_,
+ tlv_ctag : _TLV_CTAG_WIDTH_,
+ tlv_compression : 1;
+ uint32_t tlv_cdata_middle_32 : 32;
+ uint32_t pad_76to96_bit : 20,
+ tlv_cdata_upper_12 : 12;
+ uint32_t pad_96to128_bit : 32;
+#endif
+};
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tlv_tag_def.h b/drivers/staging/fw-api/hw/peach/v1/tlv_tag_def.h
new file mode 100644
index 0000000000000000000000000000000000000000..bbbd5f376f446210a625f5572195d2410e1ca4ba
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tlv_tag_def.h
@@ -0,0 +1,510 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TLV_TAG_DEF_
+#define _TLV_TAG_DEF_
+
+typedef enum tlv_tag_def {
+ WIFIMACTX_CBF_START_E = 0 ,
+ WIFIPHYRX_DATA_E = 1 ,
+ WIFIPHYRX_CBF_DATA_RESP_E = 2 ,
+ WIFIPHYRX_ABORT_REQUEST_E = 3 ,
+ WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 ,
+ WIFIMACTX_DATA_RESP_E = 5 ,
+ WIFIMACTX_CBF_DATA_E = 6 ,
+ WIFIMACTX_CBF_DONE_E = 7 ,
+ WIFIPHYRX_LMR_DATA_RESP_E = 8 ,
+ WIFIRXPCU_TO_UCODE_START_E = 9 ,
+ WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 ,
+ WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 ,
+ WIFIRXPCU_TO_UCODE_FCS_STATUS_E = 12 ,
+ WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 ,
+ WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 ,
+ WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 ,
+ WIFIRXPCU_TO_UCODE_END_E = 16 ,
+ WIFIPHYRX_RSSI_LEGACY_20MHZ_E = 28 ,
+ WIFIPHYRX_NC_ABORT_REQUEST_E = 29 ,
+ WIFIPHYRX_PKT_END_20MHZ_E = 30 ,
+ WIFIPHYRX_NC_DATA_E = 31 ,
+ WIFIMACRX_CBF_READ_REQUEST_E = 32 ,
+ WIFIMACRX_CBF_DATA_REQUEST_E = 33 ,
+ WIFIMACRX_EXPECT_NDP_RECEPTION_E = 34 ,
+ WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 35 ,
+ WIFIMACRX_NDP_TIMEOUT_E = 36 ,
+ WIFIMACRX_ABORT_ACK_E = 37 ,
+ WIFIMACRX_REQ_IMPLICIT_FB_E = 38 ,
+ WIFIMACRX_CHAIN_MASK_E = 39 ,
+ WIFIMACRX_NAP_USER_E = 40 ,
+ WIFIMACRX_ABORT_REQUEST_E = 41 ,
+ WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 42 ,
+ WIFIPHYTX_ABORT_ACK_E = 43 ,
+ WIFIPHYTX_ABORT_REQUEST_E = 44 ,
+ WIFIPHYTX_PKT_END_E = 45 ,
+ WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 46 ,
+ WIFIPHYTX_REQUEST_CTRL_INFO_E = 47 ,
+ WIFIPHYTX_DATA_REQUEST_E = 48 ,
+ WIFIPHYTX_BF_CV_LOADING_DONE_E = 49 ,
+ WIFIPHYTX_NAP_ACK_E = 50 ,
+ WIFIPHYTX_NAP_DONE_E = 51 ,
+ WIFIPHYTX_OFF_ACK_E = 52 ,
+ WIFIPHYTX_ON_ACK_E = 53 ,
+ WIFIPHYTX_SYNTH_OFF_ACK_E = 54 ,
+ WIFIPHYTX_DEBUG16_E = 55 ,
+ WIFIMACTX_ABORT_REQUEST_E = 56 ,
+ WIFIMACTX_ABORT_ACK_E = 57 ,
+ WIFIMACTX_PKT_END_E = 58 ,
+ WIFIMACTX_PRE_PHY_DESC_E = 59 ,
+ WIFIMACTX_BF_PARAMS_COMMON_E = 60 ,
+ WIFIMACTX_BF_PARAMS_PER_USER_E = 61 ,
+ WIFIMACTX_PREFETCH_CV_E = 62 ,
+ WIFIMACTX_USER_DESC_COMMON_E = 63 ,
+ WIFIMACTX_USER_DESC_PER_USER_E = 64 ,
+ WIFIEXAMPLE_USER_TLV_16_E = 65 ,
+ WIFIEXAMPLE_TLV_16_E = 66 ,
+ WIFIMACTX_PHY_OFF_E = 67 ,
+ WIFIMACTX_PHY_ON_E = 68 ,
+ WIFIMACTX_SYNTH_OFF_E = 69 ,
+ WIFIMACTX_EXPECT_CBF_COMMON_E = 70 ,
+ WIFIMACTX_EXPECT_CBF_PER_USER_E = 71 ,
+ WIFIMACTX_PHY_DESC_E = 72 ,
+ WIFIMACTX_L_SIG_A_E = 73 ,
+ WIFIMACTX_L_SIG_B_E = 74 ,
+ WIFIMACTX_HT_SIG_E = 75 ,
+ WIFIMACTX_VHT_SIG_A_E = 76 ,
+ WIFIMACTX_VHT_SIG_B_SU20_E = 77 ,
+ WIFIMACTX_VHT_SIG_B_SU40_E = 78 ,
+ WIFIMACTX_VHT_SIG_B_SU80_E = 79 ,
+ WIFIMACTX_VHT_SIG_B_SU160_E = 80 ,
+ WIFIMACTX_VHT_SIG_B_MU20_E = 81 ,
+ WIFIMACTX_VHT_SIG_B_MU40_E = 82 ,
+ WIFIMACTX_VHT_SIG_B_MU80_E = 83 ,
+ WIFIMACTX_VHT_SIG_B_MU160_E = 84 ,
+ WIFIMACTX_SERVICE_E = 85 ,
+ WIFIMACTX_HE_SIG_A_SU_E = 86 ,
+ WIFIMACTX_HE_SIG_A_MU_DL_E = 87 ,
+ WIFIMACTX_HE_SIG_A_MU_UL_E = 88 ,
+ WIFIMACTX_HE_SIG_B1_MU_E = 89 ,
+ WIFIMACTX_HE_SIG_B2_MU_E = 90 ,
+ WIFIMACTX_HE_SIG_B2_OFDMA_E = 91 ,
+ WIFIMACTX_DELETE_CV_E = 92 ,
+ WIFIMACTX_MU_UPLINK_COMMON_E = 93 ,
+ WIFIMACTX_MU_UPLINK_USER_SETUP_E = 94 ,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_E = 95 ,
+ WIFIMACTX_PHY_NAP_E = 96 ,
+ WIFIMACTX_DEBUG_E = 97 ,
+ WIFIPHYRX_ABORT_ACK_E = 98 ,
+ WIFIPHYRX_GENERATED_CBF_DETAILS_E = 99 ,
+ WIFIPHYRX_RSSI_LEGACY_E = 100 ,
+ WIFIPHYRX_RSSI_HT_E = 101 ,
+ WIFIPHYRX_USER_INFO_E = 102 ,
+ WIFIPHYRX_PKT_END_E = 103 ,
+ WIFIPHYRX_DEBUG_E = 104 ,
+ WIFIPHYRX_CBF_TRANSFER_DONE_E = 105 ,
+ WIFIPHYRX_CBF_TRANSFER_ABORT_E = 106 ,
+ WIFIPHYRX_L_SIG_A_E = 107 ,
+ WIFIPHYRX_L_SIG_B_E = 108 ,
+ WIFIPHYRX_HT_SIG_E = 109 ,
+ WIFIPHYRX_VHT_SIG_A_E = 110 ,
+ WIFIPHYRX_VHT_SIG_B_SU20_E = 111 ,
+ WIFIPHYRX_VHT_SIG_B_SU40_E = 112 ,
+ WIFIPHYRX_VHT_SIG_B_SU80_E = 113 ,
+ WIFIPHYRX_VHT_SIG_B_SU160_E = 114 ,
+ WIFIPHYRX_VHT_SIG_B_MU20_E = 115 ,
+ WIFIPHYRX_VHT_SIG_B_MU40_E = 116 ,
+ WIFIPHYRX_VHT_SIG_B_MU80_E = 117 ,
+ WIFIPHYRX_VHT_SIG_B_MU160_E = 118 ,
+ WIFIPHYRX_HE_SIG_A_SU_E = 119 ,
+ WIFIPHYRX_HE_SIG_A_MU_DL_E = 120 ,
+ WIFIPHYRX_HE_SIG_A_MU_UL_E = 121 ,
+ WIFIPHYRX_HE_SIG_B1_MU_E = 122 ,
+ WIFIPHYRX_HE_SIG_B2_MU_E = 123 ,
+ WIFIPHYRX_HE_SIG_B2_OFDMA_E = 124 ,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_E = 125 ,
+ WIFIPHYRX_COMMON_USER_INFO_E = 126 ,
+ WIFIPHYRX_DATA_DONE_E = 127 ,
+ WIFICOEX_TX_REQ_E = 128 ,
+ WIFIDUMMY_E = 129 ,
+ WIFIEXAMPLE_TLV_32_NAME_E = 130 ,
+ WIFIMPDU_LIMIT_E = 131 ,
+ WIFINA_LENGTH_END_E = 132 ,
+ WIFIOLE_BUF_STATUS_E = 133 ,
+ WIFIPCU_PPDU_SETUP_DONE_E = 134 ,
+ WIFIPCU_PPDU_SETUP_END_E = 135 ,
+ WIFIPCU_PPDU_SETUP_INIT_E = 136 ,
+ WIFIPCU_PPDU_SETUP_START_E = 137 ,
+ WIFIPDG_FES_SETUP_E = 138 ,
+ WIFIPDG_RESPONSE_E = 139 ,
+ WIFIPDG_TX_REQ_E = 140 ,
+ WIFISCH_WAIT_INSTR_E = 141 ,
+ WIFIMACTX_SWITCH_TO_MAIN_E = 142 ,
+ WIFIPHYTX_LINK_STATE_E = 143 ,
+ WIFIAUX_PPDU_END_E = 144 ,
+ WIFITQM_GEN_MPDU_LENGTH_LIST_E = 145 ,
+ WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 146 ,
+ WIFITQM_GEN_MPDUS_E = 147 ,
+ WIFITQM_GEN_MPDUS_STATUS_E = 148 ,
+ WIFITQM_REMOVE_MPDU_E = 149 ,
+ WIFITQM_REMOVE_MPDU_STATUS_E = 150 ,
+ WIFITQM_REMOVE_MSDU_E = 151 ,
+ WIFITQM_REMOVE_MSDU_STATUS_E = 152 ,
+ WIFITQM_UPDATE_TX_MPDU_COUNT_E = 153 ,
+ WIFITQM_WRITE_CMD_E = 154 ,
+ WIFIOFDMA_TRIGGER_DETAILS_E = 155 ,
+ WIFITX_DATA_E = 156 ,
+ WIFITX_FES_SETUP_E = 157 ,
+ WIFIRX_PACKET_E = 158 ,
+ WIFIEXPECTED_RESPONSE_E = 159 ,
+ WIFITX_MPDU_END_E = 160 ,
+ WIFITX_MPDU_START_E = 161 ,
+ WIFITX_MSDU_END_E = 162 ,
+ WIFITX_MSDU_START_E = 163 ,
+ WIFITX_SW_MODE_SETUP_E = 164 ,
+ WIFITXPCU_BUFFER_STATUS_E = 165 ,
+ WIFITXPCU_USER_BUFFER_STATUS_E = 166 ,
+ WIFIDATA_TO_TIME_CONFIG_E = 167 ,
+ WIFIEXAMPLE_USER_TLV_32_E = 168 ,
+ WIFIMPDU_INFO_E = 169 ,
+ WIFIPDG_USER_SETUP_E = 170 ,
+ WIFITX_11AH_SETUP_E = 171 ,
+ WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 172 ,
+ WIFITX_PEER_ENTRY_E = 173 ,
+ WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 174 ,
+ WIFIEXAMPLE_USER_TLV_44_E = 175 ,
+ WIFITX_FLUSH_E = 176 ,
+ WIFITX_FLUSH_REQ_E = 177 ,
+ WIFITQM_WRITE_CMD_STATUS_E = 178 ,
+ WIFITQM_GET_MPDU_QUEUE_STATS_E = 179 ,
+ WIFITQM_GET_MSDU_FLOW_STATS_E = 180 ,
+ WIFIEXAMPLE_USER_CTLV_44_E = 181 ,
+ WIFITX_FES_STATUS_START_E = 182 ,
+ WIFITX_FES_STATUS_USER_PPDU_E = 183 ,
+ WIFITX_FES_STATUS_USER_RESPONSE_E = 184 ,
+ WIFITX_FES_STATUS_END_E = 185 ,
+ WIFIRX_TRIG_INFO_E = 186 ,
+ WIFIRXPCU_TX_SETUP_CLEAR_E = 187 ,
+ WIFIRX_FRAME_BITMAP_REQ_E = 188 ,
+ WIFIRX_FRAME_BITMAP_ACK_E = 189 ,
+ WIFICOEX_RX_STATUS_E = 190 ,
+ WIFIRX_START_PARAM_E = 191 ,
+ WIFIRX_PPDU_START_E = 192 ,
+ WIFIRX_PPDU_END_E = 193 ,
+ WIFIRX_MPDU_START_E = 194 ,
+ WIFIRX_MPDU_END_E = 195 ,
+ WIFIRX_MSDU_START_E = 196 ,
+ WIFIRX_MSDU_END_E = 197 ,
+ WIFIRX_ATTENTION_E = 198 ,
+ WIFIRECEIVED_RESPONSE_INFO_E = 199 ,
+ WIFIRX_PHY_SLEEP_E = 200 ,
+ WIFIRX_HEADER_E = 201 ,
+ WIFIRX_PEER_ENTRY_E = 202 ,
+ WIFIRX_FLUSH_E = 203 ,
+ WIFIRX_RESPONSE_REQUIRED_INFO_E = 204 ,
+ WIFIRX_FRAMELESS_BAR_DETAILS_E = 205 ,
+ WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 206 ,
+ WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 207 ,
+ WIFITX_CBF_INFO_E = 208 ,
+ WIFIPCU_PPDU_SETUP_USER_E = 209 ,
+ WIFIRX_MPDU_PCU_START_E = 210 ,
+ WIFIRX_PM_INFO_E = 211 ,
+ WIFIRX_USER_PPDU_END_E = 212 ,
+ WIFIRX_PRE_PPDU_START_E = 213 ,
+ WIFIRX_PREAMBLE_E = 214 ,
+ WIFITX_FES_SETUP_COMPLETE_E = 215 ,
+ WIFITX_LAST_MPDU_FETCHED_E = 216 ,
+ WIFITXDMA_STOP_REQUEST_E = 217 ,
+ WIFIRXPCU_SETUP_E = 218 ,
+ WIFIRXPCU_USER_SETUP_E = 219 ,
+ WIFITX_FES_STATUS_ACK_OR_BA_E = 220 ,
+ WIFITQM_ACKED_MPDU_E = 221 ,
+ WIFICOEX_TX_RESP_E = 222 ,
+ WIFICOEX_TX_STATUS_E = 223 ,
+ WIFIMACTX_COEX_PHY_CTRL_E = 224 ,
+ WIFICOEX_STATUS_BROADCAST_E = 225 ,
+ WIFIRESPONSE_START_STATUS_E = 226 ,
+ WIFIRESPONSE_END_STATUS_E = 227 ,
+ WIFICRYPTO_STATUS_E = 228 ,
+ WIFIRECEIVED_TRIGGER_INFO_E = 229 ,
+ WIFICOEX_TX_STOP_CTRL_E = 230 ,
+ WIFIRX_PPDU_ACK_REPORT_E = 231 ,
+ WIFIRX_PPDU_NO_ACK_REPORT_E = 232 ,
+ WIFISCH_COEX_STATUS_E = 233 ,
+ WIFISCHEDULER_COMMAND_STATUS_E = 234 ,
+ WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 235 ,
+ WIFITX_FES_STATUS_PROT_E = 236 ,
+ WIFITX_FES_STATUS_START_PPDU_E = 237 ,
+ WIFITX_FES_STATUS_START_PROT_E = 238 ,
+ WIFITXPCU_PHYTX_DEBUG32_E = 239 ,
+ WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 240 ,
+ WIFITX_MPDU_COUNT_TRANSFER_END_E = 241 ,
+ WIFIWHO_ANCHOR_OFFSET_E = 242 ,
+ WIFIWHO_ANCHOR_VALUE_E = 243 ,
+ WIFIWHO_CCE_INFO_E = 244 ,
+ WIFIWHO_COMMIT_E = 245 ,
+ WIFIWHO_COMMIT_DONE_E = 246 ,
+ WIFIWHO_FLUSH_E = 247 ,
+ WIFIWHO_L2_LLC_E = 248 ,
+ WIFIWHO_L2_PAYLOAD_E = 249 ,
+ WIFIWHO_L3_CHECKSUM_E = 250 ,
+ WIFIWHO_L3_INFO_E = 251 ,
+ WIFIWHO_L4_CHECKSUM_E = 252 ,
+ WIFIWHO_L4_INFO_E = 253 ,
+ WIFIWHO_MSDU_E = 254 ,
+ WIFIWHO_MSDU_MISC_E = 255 ,
+ WIFIWHO_PACKET_DATA_E = 256 ,
+ WIFIWHO_PACKET_HDR_E = 257 ,
+ WIFIWHO_PPDU_END_E = 258 ,
+ WIFIWHO_PPDU_START_E = 259 ,
+ WIFIWHO_TSO_E = 260 ,
+ WIFIWHO_WMAC_HEADER_PV0_E = 261 ,
+ WIFIWHO_WMAC_HEADER_PV1_E = 262 ,
+ WIFIWHO_WMAC_IV_E = 263 ,
+ WIFIMPDU_INFO_END_E = 264 ,
+ WIFIMPDU_INFO_BITMAP_E = 265 ,
+ WIFITX_QUEUE_EXTENSION_E = 266 ,
+ WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 267 ,
+ WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 268 ,
+ WIFITQM_ACKED_MPDU_STATUS_E = 269 ,
+ WIFITQM_ADD_MSDU_STATUS_E = 270 ,
+ WIFITQM_LIST_GEN_DONE_E = 271 ,
+ WIFIWHO_TERMINATE_E = 272 ,
+ WIFITX_LAST_MPDU_END_E = 273 ,
+ WIFITX_CV_DATA_E = 274 ,
+ WIFIPPDU_TX_END_E = 275 ,
+ WIFIPROT_TX_END_E = 276 ,
+ WIFIMPDU_INFO_GLOBAL_END_E = 277 ,
+ WIFITQM_SCH_INSTR_GLOBAL_END_E = 278 ,
+ WIFIRX_PPDU_END_USER_STATS_E = 279 ,
+ WIFIRX_PPDU_END_USER_STATS_EXT_E = 280 ,
+ WIFIREO_GET_QUEUE_STATS_E = 281 ,
+ WIFIREO_FLUSH_QUEUE_E = 282 ,
+ WIFIREO_FLUSH_CACHE_E = 283 ,
+ WIFIREO_UNBLOCK_CACHE_E = 284 ,
+ WIFIREO_GET_QUEUE_STATS_STATUS_E = 285 ,
+ WIFIREO_FLUSH_QUEUE_STATUS_E = 286 ,
+ WIFIREO_FLUSH_CACHE_STATUS_E = 287 ,
+ WIFIREO_UNBLOCK_CACHE_STATUS_E = 288 ,
+ WIFITQM_FLUSH_CACHE_E = 289 ,
+ WIFITQM_UNBLOCK_CACHE_E = 290 ,
+ WIFITQM_FLUSH_CACHE_STATUS_E = 291 ,
+ WIFITQM_UNBLOCK_CACHE_STATUS_E = 292 ,
+ WIFIRX_PPDU_END_STATUS_DONE_E = 293 ,
+ WIFIRX_STATUS_BUFFER_DONE_E = 294 ,
+ WIFISCHEDULER_MLO_SW_MSG_STATUS_E = 295 ,
+ WIFISCHEDULER_TXOP_DURATION_TRIGGER_E = 296 ,
+ WIFITX_DATA_SYNC_E = 297 ,
+ WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 298 ,
+ WIFITQM_GET_MPDU_HEAD_INFO_E = 299 ,
+ WIFITQM_SYNC_CMD_E = 300 ,
+ WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 301 ,
+ WIFITQM_SYNC_CMD_STATUS_E = 302 ,
+ WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 303 ,
+ WIFIREO_FLUSH_TIMEOUT_LIST_E = 305 ,
+ WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 306 ,
+ WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 307 ,
+ WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 308 ,
+ WIFIEXAMPLE_USER_TLV_32_NAME_E = 309 ,
+ WIFIRX_PPDU_START_USER_INFO_E = 310 ,
+ WIFIRX_RING_MASK_E = 311 ,
+ WIFICOEX_MAC_NAP_E = 312 ,
+ WIFIRXPCU_PPDU_END_INFO_E = 313 ,
+ WIFIWHO_MESH_CONTROL_E = 314 ,
+ WIFIPDG_SW_MODE_BW_START_E = 315 ,
+ WIFIPDG_SW_MODE_BW_END_E = 316 ,
+ WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 317 ,
+ WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 318 ,
+ WIFISCHEDULER_END_E = 319 ,
+ WIFIRX_PPDU_START_DROPPED_E = 320 ,
+ WIFIRX_PPDU_END_DROPPED_E = 321 ,
+ WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 322 ,
+ WIFIRX_MPDU_START_DROPPED_E = 323 ,
+ WIFIRX_MSDU_START_DROPPED_E = 324 ,
+ WIFIRX_MSDU_END_DROPPED_E = 325 ,
+ WIFIRX_MPDU_END_DROPPED_E = 326 ,
+ WIFIRX_ATTENTION_DROPPED_E = 327 ,
+ WIFITXPCU_USER_SETUP_E = 328 ,
+ WIFIRXPCU_USER_SETUP_EXT_E = 329 ,
+ WIFICMD_PART_0_END_E = 330 ,
+ WIFIMACTX_SYNTH_ON_E = 331 ,
+ WIFISCH_CRITICAL_TLV_REFERENCE_E = 332 ,
+ WIFITQM_MPDU_GLOBAL_START_E = 333 ,
+ WIFIEXAMPLE_TLV_32_E = 334 ,
+ WIFITQM_UPDATE_TX_MSDU_FLOW_E = 335 ,
+ WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 336 ,
+ WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 337 ,
+ WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 338 ,
+ WIFIREO_UPDATE_RX_REO_QUEUE_E = 339 ,
+ WIFITQM_2_SCH_MPDU_AVAILABLE_E = 341 ,
+ WIFIPDG_TRIG_RESPONSE_E = 342 ,
+ WIFITRIGGER_RESPONSE_TX_DONE_E = 343 ,
+ WIFIABORT_FROM_PHYRX_DETAILS_E = 344 ,
+ WIFISCH_TQM_CMD_WRAPPER_E = 345 ,
+ WIFIMPDUS_AVAILABLE_E = 346 ,
+ WIFIRECEIVED_RESPONSE_INFO_PART2_E = 347 ,
+ WIFIPHYRX_TX_START_TIMING_E = 348 ,
+ WIFITXPCU_PREAMBLE_DONE_E = 349 ,
+ WIFINDP_PREAMBLE_DONE_E = 350 ,
+ WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 351 ,
+ WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 352 ,
+ WIFIMACTX_CLEAR_PREV_TX_INFO_E = 353 ,
+ WIFITX_PUNCTURE_SETUP_E = 354 ,
+ WIFIR2R_STATUS_END_E = 355 ,
+ WIFIMACTX_PREFETCH_CV_COMMON_E = 356 ,
+ WIFIEND_OF_FLUSH_MARKER_E = 357 ,
+ WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 358 ,
+ WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 359 ,
+ WIFIRECEIVED_RESPONSE_USER_7_0_E = 360 ,
+ WIFIRECEIVED_RESPONSE_USER_15_8_E = 361 ,
+ WIFIRECEIVED_RESPONSE_USER_23_16_E = 362 ,
+ WIFIRECEIVED_RESPONSE_USER_31_24_E = 363 ,
+ WIFIRECEIVED_RESPONSE_USER_36_32_E = 364 ,
+ WIFITX_LOOPBACK_SETUP_E = 365 ,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 366 ,
+ WIFISCH_WAIT_INSTR_TX_PATH_E = 367 ,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 368 ,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 369 ,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 370 ,
+ WIFITX_WUR_DATA_E = 371 ,
+ WIFIRX_PPDU_END_START_E = 372 ,
+ WIFIRX_PPDU_END_MIDDLE_E = 373 ,
+ WIFIRX_PPDU_END_LAST_E = 374 ,
+ WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 375 ,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 376 ,
+ WIFISRP_INFO_E = 377 ,
+ WIFIOBSS_SR_INFO_E = 378 ,
+ WIFISCHEDULER_SW_MSG_STATUS_E = 379 ,
+ WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 380 ,
+ WIFIRXPCU_SETUP_COMPLETE_E = 381 ,
+ WIFIMACTX_MCC_SWITCH_E = 382 ,
+ WIFIMACTX_MCC_SWITCH_BACK_E = 383 ,
+ WIFIPHYTX_MCC_SWITCH_ACK_E = 384 ,
+ WIFIPHYTX_MCC_SWITCH_BACK_ACK_E = 385 ,
+ WIFIPHYTX_EMLSR_PRE_SWITCH_ACK_E = 386 ,
+ WIFILMR_TX_END_E = 389 ,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 390 ,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 391 ,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 392 ,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 393 ,
+ WIFISCH_TLV_WRAPPER_E = 394 ,
+ WIFISCHEDULER_STATUS_WRAPPER_E = 395 ,
+ WIFIMPDU_INFO_6X_E = 396 ,
+ WIFIMACTX___RESERVED_G_0013 = 397 ,
+ WIFIMACTX_U_SIG_EHT_SU_MU_E = 398 ,
+ WIFIMACTX_U_SIG_EHT_TB_E = 399 ,
+ WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E = 400 ,
+ WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E = 401 ,
+ WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E = 402 ,
+ WIFIPHYRX_U_SIG_EHT_SU_MU_E = 403 ,
+ WIFIPHYRX_U_SIG_EHT_TB_E = 404 ,
+ WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E = 405 ,
+ WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 406 ,
+ WIFITX_PUNCTURE_6PATTERNS_SETUP_E = 407 ,
+ WIFIMACRX_LMR_READ_REQUEST_E = 408 ,
+ WIFIMACRX_LMR_DATA_REQUEST_E = 409 ,
+ WIFIPHYRX_LMR_TRANSFER_DONE_E = 410 ,
+ WIFIPHYRX_LMR_TRANSFER_ABORT_E = 411 ,
+ WIFIPHYRX_LMR_READ_REQUEST_ACK_E = 412 ,
+ WIFIMACRX_SECURE_LTF_SEQ_PTR_E = 413 ,
+ WIFIPHYRX_USER_INFO_MU_UL_E = 414 ,
+ WIFIMPDU_QUEUE_OVERVIEW_E = 415 ,
+ WIFISCHEDULER_NAV_INFO_E = 416 ,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 417 ,
+ WIFILMR_PEER_ENTRY_E = 418 ,
+ WIFILMR_MPDU_START_E = 419 ,
+ WIFILMR_DATA_E = 420 ,
+ WIFILMR_MPDU_END_E = 421 ,
+ WIFIREO_GET_QUEUE_1K_STATS_STATUS_E = 422 ,
+ WIFIRX_FRAME_1K_BITMAP_ACK_E = 423 ,
+ WIFITX_FES_STATUS_1K_BA_E = 424 ,
+ WIFITQM_ACKED_1K_MPDU_E = 425 ,
+ WIFIMACRX_INBSS_OBSS_IND_E = 426 ,
+ WIFIPHYRX_LOCATION_E = 427 ,
+ WIFIMLO_TX_NOTIFICATION_SU_E = 428 ,
+ WIFIMLO_TX_NOTIFICATION_MU_E = 429 ,
+ WIFIMLO_TX_REQ_SU_E = 430 ,
+ WIFIMLO_TX_REQ_MU_E = 431 ,
+ WIFIMLO_TX_RESP_E = 432 ,
+ WIFIMLO_RX_NOTIFICATION_E = 433 ,
+ WIFIMLO_BKOFF_TRUNC_REQ_E = 434 ,
+ WIFIMLO_TBTT_NOTIFICATION_E = 435 ,
+ WIFIMLO_MESSAGE_E = 436 ,
+ WIFIMLO_TS_SYNC_MSG_E = 437 ,
+ WIFIMLO_FES_SETUP_E = 438 ,
+ WIFIMLO_PDG_FES_SETUP_SU_E = 439 ,
+ WIFIMLO_PDG_FES_SETUP_MU_E = 440 ,
+ WIFIMPDU_INFO_1K_BITMAP_E = 441 ,
+ WIFIMON_BUFFER_ADDR_E = 442 ,
+ WIFITX_FRAG_STATE_E = 443 ,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 444 ,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 445 ,
+ WIFIMACTX_EHT_SIG_USR_OFDMA_E = 446 ,
+ WIFIPHYRX_EHT_SIG_CMN_PUNC_E = 448 ,
+ WIFIPHYRX_EHT_SIG_CMN_OFDMA_E = 450 ,
+ WIFIPHYRX_EHT_SIG_USR_OFDMA_E = 454 ,
+ WIFIPHYRX_PKT_END_PART1_E = 456 ,
+ WIFIMACTX_EXPECT_NDP_RECEPTION_E = 457 ,
+ WIFIMACTX_SECURE_LTF_SEQ_PTR_E = 458 ,
+ WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E = 460 ,
+ WIFIPHYRX___RESERVED_G_0014 = 461 ,
+ WIFIPHYTX_LOCATION_E = 462 ,
+ WIFIPHYTX___RESERVED_G_0014 = 463 ,
+ WIFIMACTX_EHT_SIG_USR_SU_E = 466 ,
+ WIFIMACTX_EHT_SIG_USR_MU_MIMO_E = 467 ,
+ WIFIPHYRX_EHT_SIG_USR_SU_E = 468 ,
+ WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E = 469 ,
+ WIFIPHYRX_GENERIC_U_SIG_E = 470 ,
+ WIFIPHYRX_GENERIC_EHT_SIG_E = 471 ,
+ WIFIOVERWRITE_RESP_START_E = 472 ,
+ WIFIOVERWRITE_RESP_PREAMBLE_INFO_E = 473 ,
+ WIFIOVERWRITE_RESP_FRAME_INFO_E = 474 ,
+ WIFIOVERWRITE_RESP_END_E = 475 ,
+ WIFIRXPCU_EARLY_RX_INDICATION_E = 476 ,
+ WIFIMON_DROP_E = 477 ,
+ WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E = 478 ,
+ WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 479 ,
+ WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E = 480 ,
+ WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 481 ,
+ WIFIMACTX_PREFETCH_CV_DMA_E = 482 ,
+ WIFIMACTX_PREFETCH_CV_PER_USER_E = 483 ,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 484 ,
+ WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E = 485 ,
+ WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E = 486 ,
+ WIFIRANGING_USER_DETAILS_E = 487 ,
+ WIFIPHYTX_CV_CORR_STATUS_E = 488 ,
+ WIFIPHYTX_CV_CORR_COMMON_E = 489 ,
+ WIFIPHYTX_CV_CORR_USER_E = 490 ,
+ WIFIMACTX_CV_CORR_COMMON_E = 491 ,
+ WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E = 492 ,
+ WIFIBW_PUNCTURE_EVAL_WRAPPER_E = 493 ,
+ WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E = 494 ,
+ WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E = 495 ,
+ WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E = 496 ,
+ WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 497 ,
+ WIFIRX_PPDU_END_USER_STATS_EXT2_E = 498 ,
+ WIFIFW2SW_MON_E = 499 ,
+ WIFIWSI_DIRECT_MESSAGE_E = 500 ,
+ WIFIMACTX_EMLSR_PRE_SWITCH_E = 501 ,
+ WIFIMACTX_EMLSR_SWITCH_E = 502 ,
+ WIFIMACTX_EMLSR_SWITCH_BACK_E = 503 ,
+ WIFIPHYTX_EMLSR_SWITCH_ACK_E = 504 ,
+ WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E = 505 ,
+ WIFISPARE_REUSE_TAG_0_E = 506 ,
+ WIFISPARE_REUSE_TAG_1_E = 507 ,
+ WIFISPARE_REUSE_TAG_2_E = 508 ,
+ WIFISPARE_REUSE_TAG_3_E = 509
+} tlv_tag_def__e;
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_cbf_info.h b/drivers/staging/fw-api/hw/peach/v1/tx_cbf_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..704e096b629c63902faa5de702d593a8e8f85422
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_cbf_info.h
@@ -0,0 +1,458 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_CBF_INFO_H_
+#define _TX_CBF_INFO_H_
+
+#define NUM_OF_DWORDS_TX_CBF_INFO 15
+
+struct tx_cbf_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t sw_peer_id : 16,
+ pre_cbf_duration : 16;
+ uint32_t brpoll_info_valid : 1,
+ trigger_brpoll_info_valid : 1,
+ npda_info_11ac_valid : 1,
+ npda_info_11ax_valid : 1,
+ dot11ax_su_extended : 1,
+ bandwidth : 3,
+ brpoll_info : 8,
+ cbf_response_table_base_index : 8,
+ peer_index : 3,
+ pkt_type : 4,
+ txop_duration_all_ones : 1;
+ uint32_t trigger_brpoll_common_info_15_0 : 16,
+ trigger_brpoll_common_info_31_16 : 16;
+ uint32_t trigger_brpoll_user_info_15_0 : 16,
+ trigger_brpoll_user_info_31_16 : 16;
+ uint32_t addr1_31_0 : 32;
+ uint32_t addr1_47_32 : 16,
+ addr2_15_0 : 16;
+ uint32_t addr2_47_16 : 32;
+ uint32_t addr3_31_0 : 32;
+ uint32_t addr3_47_32 : 16,
+ sta_partial_aid : 11,
+ reserved_8a : 4,
+ cbf_resp_pwr_mgmt : 1;
+ uint32_t group_id : 6,
+ rssi_comb : 8,
+ reserved_9a : 2,
+ vht_ndpa_sta_info : 16;
+ uint32_t he_eht_sta_info_15_0 : 16,
+ he_eht_sta_info_31_16 : 16;
+ uint32_t dot11ax_received_format_indication : 1,
+ dot11ax_received_dl_ul_flag : 1,
+ dot11ax_received_bss_color_id : 6,
+ dot11ax_received_spatial_reuse : 4,
+ dot11ax_received_cp_size : 2,
+ dot11ax_received_ltf_size : 2,
+ dot11ax_received_coding : 1,
+ dot11ax_received_dcm : 1,
+ dot11ax_received_doppler_indication : 1,
+ dot11ax_received_ext_ru_size : 4,
+ dot11ax_dl_ul_flag : 1,
+ reserved_11a : 8;
+ uint32_t sw_response_frame_length : 16,
+ sw_response_tlv_from_crypto : 1,
+ wait_sifs_config_valid : 1,
+ wait_sifs : 2,
+ __reserved_g_0005 : 1,
+ secure : 1,
+ tb___reserved_g_0005_response_required : 2,
+ emlsr_main_tlv_if : 1,
+ reserved_12a : 1,
+ u_sig_puncture_pattern_encoding : 6;
+ uint32_t dot11be_puncture_bitmap : 16,
+ dot11be_response : 1,
+ punctured_response : 1,
+ npda_info_11be_valid : 1,
+ eht_duplicate_mode : 2,
+ reserved_13a : 11;
+ uint32_t eht_sta_info_39_32 : 8,
+ reserved_14a : 24;
+#else
+ uint32_t pre_cbf_duration : 16,
+ sw_peer_id : 16;
+ uint32_t txop_duration_all_ones : 1,
+ pkt_type : 4,
+ peer_index : 3,
+ cbf_response_table_base_index : 8,
+ brpoll_info : 8,
+ bandwidth : 3,
+ dot11ax_su_extended : 1,
+ npda_info_11ax_valid : 1,
+ npda_info_11ac_valid : 1,
+ trigger_brpoll_info_valid : 1,
+ brpoll_info_valid : 1;
+ uint32_t trigger_brpoll_common_info_31_16 : 16,
+ trigger_brpoll_common_info_15_0 : 16;
+ uint32_t trigger_brpoll_user_info_31_16 : 16,
+ trigger_brpoll_user_info_15_0 : 16;
+ uint32_t addr1_31_0 : 32;
+ uint32_t addr2_15_0 : 16,
+ addr1_47_32 : 16;
+ uint32_t addr2_47_16 : 32;
+ uint32_t addr3_31_0 : 32;
+ uint32_t cbf_resp_pwr_mgmt : 1,
+ reserved_8a : 4,
+ sta_partial_aid : 11,
+ addr3_47_32 : 16;
+ uint32_t vht_ndpa_sta_info : 16,
+ reserved_9a : 2,
+ rssi_comb : 8,
+ group_id : 6;
+ uint32_t he_eht_sta_info_31_16 : 16,
+ he_eht_sta_info_15_0 : 16;
+ uint32_t reserved_11a : 8,
+ dot11ax_dl_ul_flag : 1,
+ dot11ax_received_ext_ru_size : 4,
+ dot11ax_received_doppler_indication : 1,
+ dot11ax_received_dcm : 1,
+ dot11ax_received_coding : 1,
+ dot11ax_received_ltf_size : 2,
+ dot11ax_received_cp_size : 2,
+ dot11ax_received_spatial_reuse : 4,
+ dot11ax_received_bss_color_id : 6,
+ dot11ax_received_dl_ul_flag : 1,
+ dot11ax_received_format_indication : 1;
+ uint32_t u_sig_puncture_pattern_encoding : 6,
+ reserved_12a : 1,
+ emlsr_main_tlv_if : 1,
+ tb___reserved_g_0005_response_required : 2,
+ secure : 1,
+ __reserved_g_0005 : 1,
+ wait_sifs : 2,
+ wait_sifs_config_valid : 1,
+ sw_response_tlv_from_crypto : 1,
+ sw_response_frame_length : 16;
+ uint32_t reserved_13a : 11,
+ eht_duplicate_mode : 2,
+ npda_info_11be_valid : 1,
+ punctured_response : 1,
+ dot11be_response : 1,
+ dot11be_puncture_bitmap : 16;
+ uint32_t reserved_14a : 24,
+ eht_sta_info_39_32 : 8;
+#endif
+};
+
+#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x00000000
+#define TX_CBF_INFO_SW_PEER_ID_LSB 0
+#define TX_CBF_INFO_SW_PEER_ID_MSB 15
+#define TX_CBF_INFO_SW_PEER_ID_MASK 0x0000ffff
+
+#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x00000000
+#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16
+#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31
+#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0xffff0000
+
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x00000004
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 0
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 0
+#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x00000001
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x00000004
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 1
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 1
+#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x00000002
+
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x00000004
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 2
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 2
+#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x00000004
+
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x00000004
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 3
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 3
+#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x00000008
+
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 4
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 4
+#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x00000010
+
+#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x00000004
+#define TX_CBF_INFO_BANDWIDTH_LSB 5
+#define TX_CBF_INFO_BANDWIDTH_MSB 7
+#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e0
+
+#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x00000004
+#define TX_CBF_INFO_BRPOLL_INFO_LSB 8
+#define TX_CBF_INFO_BRPOLL_INFO_MSB 15
+#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff00
+
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x00000004
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 16
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 23
+#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff0000
+
+#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x00000004
+#define TX_CBF_INFO_PEER_INDEX_LSB 24
+#define TX_CBF_INFO_PEER_INDEX_MSB 26
+#define TX_CBF_INFO_PEER_INDEX_MASK 0x07000000
+
+#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x00000004
+#define TX_CBF_INFO_PKT_TYPE_LSB 27
+#define TX_CBF_INFO_PKT_TYPE_MSB 30
+#define TX_CBF_INFO_PKT_TYPE_MASK 0x78000000
+
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x00000004
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 31
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 31
+#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x80000000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x00000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x0000ffff
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x00000008
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31
+#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0xffff0000
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000c
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 0
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 15
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff
+
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000c
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 16
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 31
+#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff0000
+
+#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x00000010
+#define TX_CBF_INFO_ADDR1_31_0_LSB 0
+#define TX_CBF_INFO_ADDR1_31_0_MSB 31
+#define TX_CBF_INFO_ADDR1_31_0_MASK 0xffffffff
+
+#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x00000014
+#define TX_CBF_INFO_ADDR1_47_32_LSB 0
+#define TX_CBF_INFO_ADDR1_47_32_MSB 15
+#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff
+
+#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x00000014
+#define TX_CBF_INFO_ADDR2_15_0_LSB 16
+#define TX_CBF_INFO_ADDR2_15_0_MSB 31
+#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff0000
+
+#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x00000018
+#define TX_CBF_INFO_ADDR2_47_16_LSB 0
+#define TX_CBF_INFO_ADDR2_47_16_MSB 31
+#define TX_CBF_INFO_ADDR2_47_16_MASK 0xffffffff
+
+#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000001c
+#define TX_CBF_INFO_ADDR3_31_0_LSB 0
+#define TX_CBF_INFO_ADDR3_31_0_MSB 31
+#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff
+
+#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x00000020
+#define TX_CBF_INFO_ADDR3_47_32_LSB 0
+#define TX_CBF_INFO_ADDR3_47_32_MSB 15
+#define TX_CBF_INFO_ADDR3_47_32_MASK 0x0000ffff
+
+#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x00000020
+#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16
+#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26
+#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x07ff0000
+
+#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x00000020
+#define TX_CBF_INFO_RESERVED_8A_LSB 27
+#define TX_CBF_INFO_RESERVED_8A_MSB 30
+#define TX_CBF_INFO_RESERVED_8A_MASK 0x78000000
+
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x00000020
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31
+#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x80000000
+
+#define TX_CBF_INFO_GROUP_ID_OFFSET 0x00000024
+#define TX_CBF_INFO_GROUP_ID_LSB 0
+#define TX_CBF_INFO_GROUP_ID_MSB 5
+#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f
+
+#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x00000024
+#define TX_CBF_INFO_RSSI_COMB_LSB 6
+#define TX_CBF_INFO_RSSI_COMB_MSB 13
+#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc0
+
+#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x00000024
+#define TX_CBF_INFO_RESERVED_9A_LSB 14
+#define TX_CBF_INFO_RESERVED_9A_MSB 15
+#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c000
+
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x00000024
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 16
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 31
+#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff0000
+
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x00000028
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15
+#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x0000ffff
+
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x00000028
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31
+#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0xffff0000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 0
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 0
+#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x00000001
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 1
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 1
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x00000002
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 2
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 7
+#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 8
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 11
+#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f00
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 12
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 13
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x00003000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 14
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 15
+#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 16
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 16
+#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x00010000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 17
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 17
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x00020000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 18
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 18
+#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x00040000
+
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000002c
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 19
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 22
+#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x00780000
+
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000002c
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 23
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 23
+#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x00800000
+
+#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000002c
+#define TX_CBF_INFO_RESERVED_11A_LSB 24
+#define TX_CBF_INFO_RESERVED_11A_MSB 31
+#define TX_CBF_INFO_RESERVED_11A_MASK 0xff000000
+
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x00000030
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15
+#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff
+
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x00000030
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16
+#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x00010000
+
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x00000030
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17
+#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x00020000
+
+#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x00000030
+#define TX_CBF_INFO_WAIT_SIFS_LSB 18
+#define TX_CBF_INFO_WAIT_SIFS_MSB 19
+#define TX_CBF_INFO_WAIT_SIFS_MASK 0x000c0000
+
+#define TX_CBF_INFO_SECURE_OFFSET 0x00000030
+#define TX_CBF_INFO_SECURE_LSB 21
+#define TX_CBF_INFO_SECURE_MSB 21
+#define TX_CBF_INFO_SECURE_MASK 0x00200000
+
+#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x00000030
+#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 22
+#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 23
+#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x00c00000
+
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x00000030
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_LSB 24
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MSB 24
+#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MASK 0x01000000
+
+#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x00000030
+#define TX_CBF_INFO_RESERVED_12A_LSB 25
+#define TX_CBF_INFO_RESERVED_12A_MSB 25
+#define TX_CBF_INFO_RESERVED_12A_MASK 0x02000000
+
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000030
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
+#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
+
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x00000034
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 0
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 15
+#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff
+
+#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x00000034
+#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 16
+#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 16
+#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x00010000
+
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x00000034
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 17
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 17
+#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x00020000
+
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x00000034
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 18
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 18
+#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x00040000
+
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x00000034
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 19
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 20
+#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x00180000
+
+#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x00000034
+#define TX_CBF_INFO_RESERVED_13A_LSB 21
+#define TX_CBF_INFO_RESERVED_13A_MSB 31
+#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe00000
+
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x00000038
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7
+#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x000000ff
+
+#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x00000038
+#define TX_CBF_INFO_RESERVED_14A_LSB 8
+#define TX_CBF_INFO_RESERVED_14A_MSB 31
+#define TX_CBF_INFO_RESERVED_14A_MASK 0xffffff00
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_setup.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_setup.h
new file mode 100644
index 0000000000000000000000000000000000000000..c141ea42f74895e3b05a053d35b5a5eb7caa004d
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_setup.h
@@ -0,0 +1,511 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_SETUP_H_
+#define _TX_FES_SETUP_H_
+
+#define NUM_OF_DWORDS_TX_FES_SETUP 10
+
+struct tx_fes_setup {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t schedule_id : 32;
+ uint32_t fes_in_11ax_trigger_response_config : 1,
+ bo_based_tid_aggregation_limit : 4,
+ __reserved_g_0005 : 1,
+ expect_i2r_lmr : 1,
+ transmit_start_reason : 3,
+ use_alt_power_sr : 1,
+ static_2_pwr_mode_status : 1,
+ obss_srg_opport_transmit_status : 1,
+ srp_based_transmit_status : 1,
+ obss_pd_based_transmit_status : 1,
+ puncture_from_all_allowed_modes : 1,
+ schedule_cmd_ring_id : 5,
+ fes_control_mode : 2,
+ number_of_users : 6,
+ mu_type : 1,
+ ofdma_triggered_response : 1,
+ response_to_response_cmd : 1;
+ uint32_t schedule_try : 4,
+ ndp_frame : 2,
+ txbf : 1,
+ allow_txop_exceed_in_1st_pkt : 1,
+ ignore_bw_available : 1,
+ ignore_tbtt : 1,
+ static_bandwidth : 3,
+ set_txop_duration_all_ones : 1,
+ transmission_contains_mu_rts : 1,
+ bw_restricted_frames_embedded : 1,
+ ast_index : 16;
+ uint32_t cv_id : 8,
+ trigger_resp_txpdu_ppdu_boundary : 2,
+ rxpcu_setup_complete_present : 1,
+ rbo_must_have_data_user_limit : 4,
+ mu_ndp : 1,
+ bf_type : 2,
+ cbf_nc_index_mask : 1,
+ cbf_nc_index : 3,
+ cbf_nr_index_mask : 1,
+ cbf_nr_index : 3,
+ secure___reserved_g_0005_ista : 1,
+ ndpa : 1,
+ wait_sifs : 2,
+ cbf_feedback_type_mask : 1,
+ cbf_feedback_type : 1;
+ uint32_t cbf_sounding_token : 6,
+ cbf_sounding_token_mask : 1,
+ cbf_bw_mask : 1,
+ cbf_bw : 3,
+ use_static_bw : 1,
+ coex_nack_count : 5,
+ sch_tx_burst_ongoing : 1,
+ gen_tqm_update_mpdu_count_tlv : 1,
+ rts_tx_over___reserved_g_0016 : 1,
+ reserved_4a : 3,
+ optimal_bw_retry_count : 4,
+ fes_continuation_ratio_threshold : 5;
+ uint32_t transmit_cca_bitmap : 32;
+ uint32_t tb___reserved_g_0005 : 1,
+ __reserved_g_0005_trigger_subtype : 4,
+ min_cts2self_count : 4,
+ max_cts2self_count : 4,
+ wifi_radar_enable : 1,
+ reserved_6a : 1,
+ wait_for_chksum_done : 1,
+ reserved_6b : 15,
+ enable_hw_qos_null : 1;
+ uint32_t monitor_override_sta_31_0 : 32;
+ uint32_t monitor_override_sta_36_32 : 5,
+ enable_qos_null_switch_for_eosp : 1,
+ reserved_8a : 26;
+ uint32_t fw2sw_info : 32;
+#else
+ uint32_t schedule_id : 32;
+ uint32_t response_to_response_cmd : 1,
+ ofdma_triggered_response : 1,
+ mu_type : 1,
+ number_of_users : 6,
+ fes_control_mode : 2,
+ schedule_cmd_ring_id : 5,
+ puncture_from_all_allowed_modes : 1,
+ obss_pd_based_transmit_status : 1,
+ srp_based_transmit_status : 1,
+ obss_srg_opport_transmit_status : 1,
+ static_2_pwr_mode_status : 1,
+ use_alt_power_sr : 1,
+ transmit_start_reason : 3,
+ expect_i2r_lmr : 1,
+ __reserved_g_0005 : 1,
+ bo_based_tid_aggregation_limit : 4,
+ fes_in_11ax_trigger_response_config : 1;
+ uint32_t ast_index : 16,
+ bw_restricted_frames_embedded : 1,
+ transmission_contains_mu_rts : 1,
+ set_txop_duration_all_ones : 1,
+ static_bandwidth : 3,
+ ignore_tbtt : 1,
+ ignore_bw_available : 1,
+ allow_txop_exceed_in_1st_pkt : 1,
+ txbf : 1,
+ ndp_frame : 2,
+ schedule_try : 4;
+ uint32_t cbf_feedback_type : 1,
+ cbf_feedback_type_mask : 1,
+ wait_sifs : 2,
+ ndpa : 1,
+ secure___reserved_g_0005_ista : 1,
+ cbf_nr_index : 3,
+ cbf_nr_index_mask : 1,
+ cbf_nc_index : 3,
+ cbf_nc_index_mask : 1,
+ bf_type : 2,
+ mu_ndp : 1,
+ rbo_must_have_data_user_limit : 4,
+ rxpcu_setup_complete_present : 1,
+ trigger_resp_txpdu_ppdu_boundary : 2,
+ cv_id : 8;
+ uint32_t fes_continuation_ratio_threshold : 5,
+ optimal_bw_retry_count : 4,
+ reserved_4a : 3,
+ rts_tx_over___reserved_g_0016 : 1,
+ gen_tqm_update_mpdu_count_tlv : 1,
+ sch_tx_burst_ongoing : 1,
+ coex_nack_count : 5,
+ use_static_bw : 1,
+ cbf_bw : 3,
+ cbf_bw_mask : 1,
+ cbf_sounding_token_mask : 1,
+ cbf_sounding_token : 6;
+ uint32_t transmit_cca_bitmap : 32;
+ uint32_t enable_hw_qos_null : 1,
+ reserved_6b : 15,
+ wait_for_chksum_done : 1,
+ reserved_6a : 1,
+ wifi_radar_enable : 1,
+ max_cts2self_count : 4,
+ min_cts2self_count : 4,
+ __reserved_g_0005_trigger_subtype : 4,
+ tb___reserved_g_0005 : 1;
+ uint32_t monitor_override_sta_31_0 : 32;
+ uint32_t reserved_8a : 26,
+ enable_qos_null_switch_for_eosp : 1,
+ monitor_override_sta_36_32 : 5;
+ uint32_t fw2sw_info : 32;
+#endif
+};
+
+#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x00000000
+#define TX_FES_SETUP_SCHEDULE_ID_LSB 0
+#define TX_FES_SETUP_SCHEDULE_ID_MSB 31
+#define TX_FES_SETUP_SCHEDULE_ID_MASK 0xffffffff
+
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x00000004
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 0
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 0
+#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x00000001
+
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x00000004
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 1
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 4
+#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e
+
+#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x00000004
+#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 6
+#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 6
+#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x00000040
+
+#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x00000004
+#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 7
+#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 9
+#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x00000380
+
+#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x00000004
+#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 10
+#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 10
+#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x00000400
+
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x00000004
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 11
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 11
+#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x00000800
+
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x00000004
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 12
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 12
+#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x00001000
+
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x00000004
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 13
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 13
+#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x00002000
+
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x00000004
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 14
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 14
+#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x00004000
+
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x00000004
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 15
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 15
+#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x00008000
+
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x00000004
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 16
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 20
+#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f0000
+
+#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x00000004
+#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 21
+#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 22
+#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x00600000
+
+#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x00000004
+#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 23
+#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 28
+#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f800000
+
+#define TX_FES_SETUP_MU_TYPE_OFFSET 0x00000004
+#define TX_FES_SETUP_MU_TYPE_LSB 29
+#define TX_FES_SETUP_MU_TYPE_MSB 29
+#define TX_FES_SETUP_MU_TYPE_MASK 0x20000000
+
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x00000004
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 30
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 30
+#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x40000000
+
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x00000004
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 31
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 31
+#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x80000000
+
+#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x00000008
+#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0
+#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3
+#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x0000000f
+
+#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x00000008
+#define TX_FES_SETUP_NDP_FRAME_LSB 4
+#define TX_FES_SETUP_NDP_FRAME_MSB 5
+#define TX_FES_SETUP_NDP_FRAME_MASK 0x00000030
+
+#define TX_FES_SETUP_TXBF_OFFSET 0x00000008
+#define TX_FES_SETUP_TXBF_LSB 6
+#define TX_FES_SETUP_TXBF_MSB 6
+#define TX_FES_SETUP_TXBF_MASK 0x00000040
+
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x00000008
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7
+#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x00000080
+
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x00000008
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8
+#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x00000100
+
+#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x00000008
+#define TX_FES_SETUP_IGNORE_TBTT_LSB 9
+#define TX_FES_SETUP_IGNORE_TBTT_MSB 9
+#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x00000200
+
+#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x00000008
+#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10
+#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12
+#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x00001c00
+
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x00000008
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13
+#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x00002000
+
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x00000008
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14
+#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x00004000
+
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x00000008
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15
+#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x00008000
+
+#define TX_FES_SETUP_AST_INDEX_OFFSET 0x00000008
+#define TX_FES_SETUP_AST_INDEX_LSB 16
+#define TX_FES_SETUP_AST_INDEX_MSB 31
+#define TX_FES_SETUP_AST_INDEX_MASK 0xffff0000
+
+#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000c
+#define TX_FES_SETUP_CV_ID_LSB 0
+#define TX_FES_SETUP_CV_ID_MSB 7
+#define TX_FES_SETUP_CV_ID_MASK 0x000000ff
+
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000c
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 8
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 9
+#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x00000300
+
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000c
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 10
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 10
+#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x00000400
+
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000c
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 11
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 14
+#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x00007800
+
+#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000c
+#define TX_FES_SETUP_MU_NDP_LSB 15
+#define TX_FES_SETUP_MU_NDP_MSB 15
+#define TX_FES_SETUP_MU_NDP_MASK 0x00008000
+
+#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000c
+#define TX_FES_SETUP_BF_TYPE_LSB 16
+#define TX_FES_SETUP_BF_TYPE_MSB 17
+#define TX_FES_SETUP_BF_TYPE_MASK 0x00030000
+
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000c
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 18
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 18
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x00040000
+
+#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000c
+#define TX_FES_SETUP_CBF_NC_INDEX_LSB 19
+#define TX_FES_SETUP_CBF_NC_INDEX_MSB 21
+#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x00380000
+
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000c
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 22
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 22
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x00400000
+
+#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000c
+#define TX_FES_SETUP_CBF_NR_INDEX_LSB 23
+#define TX_FES_SETUP_CBF_NR_INDEX_MSB 25
+#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x03800000
+
+#define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000c
+#define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 26
+#define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 26
+#define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x04000000
+
+#define TX_FES_SETUP_NDPA_OFFSET 0x0000000c
+#define TX_FES_SETUP_NDPA_LSB 27
+#define TX_FES_SETUP_NDPA_MSB 27
+#define TX_FES_SETUP_NDPA_MASK 0x08000000
+
+#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000c
+#define TX_FES_SETUP_WAIT_SIFS_LSB 28
+#define TX_FES_SETUP_WAIT_SIFS_MSB 29
+#define TX_FES_SETUP_WAIT_SIFS_MASK 0x30000000
+
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000c
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 30
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 30
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x40000000
+
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000c
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 31
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 31
+#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x80000000
+
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x00000010
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x0000003f
+
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x00000010
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6
+#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x00000040
+
+#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x00000010
+#define TX_FES_SETUP_CBF_BW_MASK_LSB 7
+#define TX_FES_SETUP_CBF_BW_MASK_MSB 7
+#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x00000080
+
+#define TX_FES_SETUP_CBF_BW_OFFSET 0x00000010
+#define TX_FES_SETUP_CBF_BW_LSB 8
+#define TX_FES_SETUP_CBF_BW_MSB 10
+#define TX_FES_SETUP_CBF_BW_MASK 0x00000700
+
+#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x00000010
+#define TX_FES_SETUP_USE_STATIC_BW_LSB 11
+#define TX_FES_SETUP_USE_STATIC_BW_MSB 11
+#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x00000800
+
+#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x00000010
+#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12
+#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16
+#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x0001f000
+
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x00000010
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17
+#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x00020000
+
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x00000010
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18
+#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x00040000
+
+#define TX_FES_SETUP_RESERVED_4A_OFFSET 0x00000010
+#define TX_FES_SETUP_RESERVED_4A_LSB 20
+#define TX_FES_SETUP_RESERVED_4A_MSB 22
+#define TX_FES_SETUP_RESERVED_4A_MASK 0x00700000
+
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x00000010
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26
+#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x07800000
+
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x00000010
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31
+#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0xf8000000
+
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x00000014
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 0
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 31
+#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff
+
+#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000018
+#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1
+#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4
+#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x0000001e
+
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x00000018
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8
+#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x000001e0
+
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x00000018
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12
+#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x00001e00
+
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x00000018
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13
+#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x00002000
+
+#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x00000018
+#define TX_FES_SETUP_RESERVED_6A_LSB 14
+#define TX_FES_SETUP_RESERVED_6A_MSB 14
+#define TX_FES_SETUP_RESERVED_6A_MASK 0x00004000
+
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET 0x00000018
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB 15
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB 15
+#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK 0x00008000
+
+#define TX_FES_SETUP_RESERVED_6B_OFFSET 0x00000018
+#define TX_FES_SETUP_RESERVED_6B_LSB 16
+#define TX_FES_SETUP_RESERVED_6B_MSB 30
+#define TX_FES_SETUP_RESERVED_6B_MASK 0x7fff0000
+
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET 0x00000018
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB 31
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB 31
+#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK 0x80000000
+
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000001c
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 0
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 31
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff
+
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x00000020
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4
+#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x0000001f
+
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET 0x00000020
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB 5
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB 5
+#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK 0x00000020
+
+#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x00000020
+#define TX_FES_SETUP_RESERVED_8A_LSB 6
+#define TX_FES_SETUP_RESERVED_8A_MSB 31
+#define TX_FES_SETUP_RESERVED_8A_MASK 0xffffffc0
+
+#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x00000024
+#define TX_FES_SETUP_FW2SW_INFO_LSB 0
+#define TX_FES_SETUP_FW2SW_INFO_MSB 31
+#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_1k_ba.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_1k_ba.h
new file mode 100644
index 0000000000000000000000000000000000000000..7b391758e361204fb3f49aecb1ad7af6a9f72b44
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_1k_ba.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_1K_BA_H_
+#define _TX_FES_STATUS_1K_BA_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34
+
+struct tx_fes_status_1k_ba {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t ack_ba_status_type : 1,
+ ba_type : 1,
+ ba_tid : 4,
+ unexpected_ack_or_ba : 1,
+ response_timeout : 1,
+ ack_frame_rssi : 8,
+ ssn : 12,
+ reserved_0b : 4;
+ uint32_t sw_peer_id : 16,
+ reserved_1a : 16;
+ uint32_t ba_bitmap_31_0 : 32;
+ uint32_t ba_bitmap_63_32 : 32;
+ uint32_t ba_bitmap_95_64 : 32;
+ uint32_t ba_bitmap_127_96 : 32;
+ uint32_t ba_bitmap_159_128 : 32;
+ uint32_t ba_bitmap_191_160 : 32;
+ uint32_t ba_bitmap_223_192 : 32;
+ uint32_t ba_bitmap_255_224 : 32;
+ uint32_t ba_bitmap_287_256 : 32;
+ uint32_t ba_bitmap_319_288 : 32;
+ uint32_t ba_bitmap_351_320 : 32;
+ uint32_t ba_bitmap_383_352 : 32;
+ uint32_t ba_bitmap_415_384 : 32;
+ uint32_t ba_bitmap_447_416 : 32;
+ uint32_t ba_bitmap_479_448 : 32;
+ uint32_t ba_bitmap_511_480 : 32;
+ uint32_t ba_bitmap_543_512 : 32;
+ uint32_t ba_bitmap_575_544 : 32;
+ uint32_t ba_bitmap_607_576 : 32;
+ uint32_t ba_bitmap_639_608 : 32;
+ uint32_t ba_bitmap_671_640 : 32;
+ uint32_t ba_bitmap_703_672 : 32;
+ uint32_t ba_bitmap_735_704 : 32;
+ uint32_t ba_bitmap_767_736 : 32;
+ uint32_t ba_bitmap_799_768 : 32;
+ uint32_t ba_bitmap_831_800 : 32;
+ uint32_t ba_bitmap_863_832 : 32;
+ uint32_t ba_bitmap_895_864 : 32;
+ uint32_t ba_bitmap_927_896 : 32;
+ uint32_t ba_bitmap_959_928 : 32;
+ uint32_t ba_bitmap_991_960 : 32;
+ uint32_t ba_bitmap_1023_992 : 32;
+#else
+ uint32_t reserved_0b : 4,
+ ssn : 12,
+ ack_frame_rssi : 8,
+ response_timeout : 1,
+ unexpected_ack_or_ba : 1,
+ ba_tid : 4,
+ ba_type : 1,
+ ack_ba_status_type : 1;
+ uint32_t reserved_1a : 16,
+ sw_peer_id : 16;
+ uint32_t ba_bitmap_31_0 : 32;
+ uint32_t ba_bitmap_63_32 : 32;
+ uint32_t ba_bitmap_95_64 : 32;
+ uint32_t ba_bitmap_127_96 : 32;
+ uint32_t ba_bitmap_159_128 : 32;
+ uint32_t ba_bitmap_191_160 : 32;
+ uint32_t ba_bitmap_223_192 : 32;
+ uint32_t ba_bitmap_255_224 : 32;
+ uint32_t ba_bitmap_287_256 : 32;
+ uint32_t ba_bitmap_319_288 : 32;
+ uint32_t ba_bitmap_351_320 : 32;
+ uint32_t ba_bitmap_383_352 : 32;
+ uint32_t ba_bitmap_415_384 : 32;
+ uint32_t ba_bitmap_447_416 : 32;
+ uint32_t ba_bitmap_479_448 : 32;
+ uint32_t ba_bitmap_511_480 : 32;
+ uint32_t ba_bitmap_543_512 : 32;
+ uint32_t ba_bitmap_575_544 : 32;
+ uint32_t ba_bitmap_607_576 : 32;
+ uint32_t ba_bitmap_639_608 : 32;
+ uint32_t ba_bitmap_671_640 : 32;
+ uint32_t ba_bitmap_703_672 : 32;
+ uint32_t ba_bitmap_735_704 : 32;
+ uint32_t ba_bitmap_767_736 : 32;
+ uint32_t ba_bitmap_799_768 : 32;
+ uint32_t ba_bitmap_831_800 : 32;
+ uint32_t ba_bitmap_863_832 : 32;
+ uint32_t ba_bitmap_895_864 : 32;
+ uint32_t ba_bitmap_927_896 : 32;
+ uint32_t ba_bitmap_959_928 : 32;
+ uint32_t ba_bitmap_991_960 : 32;
+ uint32_t ba_bitmap_1023_992 : 32;
+#endif
+};
+
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x00000000
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0
+#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x00000001
+
+#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x00000000
+#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1
+#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1
+#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x00000002
+
+#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x00000000
+#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2
+#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5
+#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x0000003c
+
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x00000000
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6
+#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x00000040
+
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x00000000
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7
+#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x00000080
+
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x00000000
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15
+#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x0000ff00
+
+#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x00000000
+#define TX_FES_STATUS_1K_BA_SSN_LSB 16
+#define TX_FES_STATUS_1K_BA_SSN_MSB 27
+#define TX_FES_STATUS_1K_BA_SSN_MASK 0x0fff0000
+
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x00000000
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31
+#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0xf0000000
+
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x00000004
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 0
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 15
+#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff
+
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x00000004
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 16
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 31
+#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff0000
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x00000008
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x00000010
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x00000014
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x00000018
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000001c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x00000020
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x00000024
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x00000028
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000002c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x00000030
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x00000034
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x00000038
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000003c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x00000040
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x00000044
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x00000048
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000004c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x00000050
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x00000054
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x00000058
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000005c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x00000060
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x00000064
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x00000068
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000006c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x00000070
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x00000074
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x00000078
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000007c
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x00000080
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0xffffffff
+
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x00000084
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 0
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 31
+#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_ack_or_ba.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_ack_or_ba.h
new file mode 100644
index 0000000000000000000000000000000000000000..582cc09ba72a1add9055d0775bb52b63a56210ea
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_ack_or_ba.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_ACK_OR_BA_H_
+#define _TX_FES_STATUS_ACK_OR_BA_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10
+
+struct tx_fes_status_ack_or_ba {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t ack_ba_status_type : 1,
+ ba_type : 1,
+ ba_tid : 4,
+ unexpected_ack_or_ba : 1,
+ response_timeout : 1,
+ ack_frame_rssi : 8,
+ ssn : 12,
+ reserved_0b : 4;
+ uint32_t sw_peer_id : 16,
+ reserved_1a : 16;
+ uint32_t ba_bitmap_31_0 : 32;
+ uint32_t ba_bitmap_63_32 : 32;
+ uint32_t ba_bitmap_95_64 : 32;
+ uint32_t ba_bitmap_127_96 : 32;
+ uint32_t ba_bitmap_159_128 : 32;
+ uint32_t ba_bitmap_191_160 : 32;
+ uint32_t ba_bitmap_223_192 : 32;
+ uint32_t ba_bitmap_255_224 : 32;
+#else
+ uint32_t reserved_0b : 4,
+ ssn : 12,
+ ack_frame_rssi : 8,
+ response_timeout : 1,
+ unexpected_ack_or_ba : 1,
+ ba_tid : 4,
+ ba_type : 1,
+ ack_ba_status_type : 1;
+ uint32_t reserved_1a : 16,
+ sw_peer_id : 16;
+ uint32_t ba_bitmap_31_0 : 32;
+ uint32_t ba_bitmap_63_32 : 32;
+ uint32_t ba_bitmap_95_64 : 32;
+ uint32_t ba_bitmap_127_96 : 32;
+ uint32_t ba_bitmap_159_128 : 32;
+ uint32_t ba_bitmap_191_160 : 32;
+ uint32_t ba_bitmap_223_192 : 32;
+ uint32_t ba_bitmap_255_224 : 32;
+#endif
+};
+
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0
+#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x00000001
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1
+#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x00000002
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5
+#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x0000003c
+
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6
+#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x00000040
+
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7
+#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x00000080
+
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15
+#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x0000ff00
+
+#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16
+#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27
+#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x0fff0000
+
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x00000000
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0xf0000000
+
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x00000004
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 0
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 15
+#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff
+
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x00000004
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 16
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 31
+#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff0000
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x00000008
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0xffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000c
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x00000010
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0xffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x00000014
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x00000018
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0xffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000001c
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x00000020
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0xffffffff
+
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x00000024
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 0
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 31
+#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_end.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_end.h
new file mode 100644
index 0000000000000000000000000000000000000000..eea99f35e3333cae30af3205873b1de9b023bca8
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_end.h
@@ -0,0 +1,649 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_END_H_
+#define _TX_FES_STATUS_END_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_TX_FES_STATUS_END 11
+
+struct tx_fes_status_end {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t prot_coex_bt_tx_while_wlan_tx : 1,
+ prot_coex_bt_tx_while_wlan_rx : 1,
+ prot_coex_wan_tx_while_wlan_tx : 1,
+ prot_coex_wan_tx_while_wlan_rx : 1,
+ prot_coex_wlan_tx_while_wlan_tx : 1,
+ prot_coex_wlan_tx_while_wlan_rx : 1,
+ coex_bt_tx_while_wlan_tx : 1,
+ coex_bt_tx_while_wlan_rx : 1,
+ coex_wan_tx_while_wlan_tx : 1,
+ coex_wan_tx_while_wlan_rx : 1,
+ coex_wlan_tx_while_wlan_tx : 1,
+ coex_wlan_tx_while_wlan_rx : 1,
+ global_data_underflow_warning : 1,
+ global_fes_transmit_result : 4,
+ cbf_bw_received_valid : 1,
+ cbf_bw_received : 3,
+ actual_received_ack_type : 4,
+ sta_response_count : 6,
+ more_data_received : 1;
+ struct phytx_abort_request_info phytx_abort_request_info_details;
+ uint16_t reserved_after_struct16 : 4,
+ brp_info_valid : 1,
+ qos_null_switch_done_for_eosp : 1,
+ reserved_1a : 5,
+ phytx_pkt_end_info_valid : 1,
+ phytx_abort_request_info_valid : 1,
+ fes_in_11ax_trigger_response_config : 1,
+ null_delim_inserted_before_mpdus : 1,
+ only_null_delim_sent : 1;
+ uint32_t terminate___reserved_g_0005_sequence : 1,
+ reserved_2b : 5,
+ response_type : 5,
+ r2r_end_status_to_follow : 1,
+ reserved_5a : 3,
+ prot_coex_lte_tx_while_wlan_tx : 1,
+ prot_coex_lte_tx_while_wlan_rx : 1,
+ reserved_2c : 15;
+ uint32_t beamform_masked_user_bitmap_15_0 : 16,
+ beamform_masked_user_bitmap_31_16 : 16;
+ uint32_t cbf_segment_request_mask : 8,
+ cbf_segment_sent_mask : 8,
+ highest_achieved_data_null_ratio : 5,
+ use_alt_power_sr : 1,
+ static_2_pwr_mode_status : 1,
+ obss_srg_opport_transmit_status : 1,
+ srp_based_transmit_status : 1,
+ obss_pd_based_transmit_status : 1,
+ beamform_masked_user_bitmap_36_32 : 5,
+ pdg_mpdu_ready : 1;
+ uint32_t pdg_mpdu_count : 16,
+ pdg_est_mpdu_tx_count : 16;
+ uint32_t pdg_overview_length : 24,
+ txop_duration : 7,
+ pdg_dropped_mpdu_warning : 1;
+ uint32_t packet_extension_a_factor : 2,
+ packet_extension_pe_disambiguity : 1,
+ packet_extension : 3,
+ fec_type : 1,
+ stbc : 1,
+ num_data_symbols : 16,
+ ru_size : 4,
+ reserved_17a : 4;
+ uint32_t num_ltf_symbols : 3,
+ ltf_size : 2,
+ cp_setting : 2,
+ reserved_18a : 5,
+ dcm : 1,
+ ldpc_extra_symbol : 1,
+ force_extra_symbol : 1,
+ reserved_18b : 1,
+ tx_pwr_shared : 8,
+ tx_pwr_unshared : 8;
+ uint32_t __reserved_g_0005_active_user_map : 16,
+ __reserved_g_0005_sent_dummy_tx : 1,
+ __reserved_g_0005_ftm_frame_sent : 1,
+ coex_uwb_tx_while_wlan_tx : 1,
+ coex_uwb_tx_while_wlan_rx : 1,
+ prot_coex_uwb_tx_while_wlan_tx : 1,
+ prot_coex_uwb_tx_while_wlan_rx : 1,
+ coex_lte_tx_while_wlan_tx : 1,
+ coex_lte_tx_while_wlan_rx : 1,
+ cv_corr_status : 8;
+ uint32_t current_tx_duration : 16,
+ reserved_21a : 4,
+ hw_qos_null_bitmap : 8,
+ hw_qos_null_setup_missing : 1,
+ reserved_21b : 3;
+#else
+ uint32_t more_data_received : 1,
+ sta_response_count : 6,
+ actual_received_ack_type : 4,
+ cbf_bw_received : 3,
+ cbf_bw_received_valid : 1,
+ global_fes_transmit_result : 4,
+ global_data_underflow_warning : 1,
+ coex_wlan_tx_while_wlan_rx : 1,
+ coex_wlan_tx_while_wlan_tx : 1,
+ coex_wan_tx_while_wlan_rx : 1,
+ coex_wan_tx_while_wlan_tx : 1,
+ coex_bt_tx_while_wlan_rx : 1,
+ coex_bt_tx_while_wlan_tx : 1,
+ prot_coex_wlan_tx_while_wlan_rx : 1,
+ prot_coex_wlan_tx_while_wlan_tx : 1,
+ prot_coex_wan_tx_while_wlan_rx : 1,
+ prot_coex_wan_tx_while_wlan_tx : 1,
+ prot_coex_bt_tx_while_wlan_rx : 1,
+ prot_coex_bt_tx_while_wlan_tx : 1;
+ uint32_t only_null_delim_sent : 1,
+ null_delim_inserted_before_mpdus : 1,
+ fes_in_11ax_trigger_response_config : 1,
+ phytx_abort_request_info_valid : 1,
+ phytx_pkt_end_info_valid : 1,
+ reserved_1a : 5,
+ qos_null_switch_done_for_eosp : 1,
+ brp_info_valid : 1,
+ reserved_after_struct16 : 4;
+ struct phytx_abort_request_info phytx_abort_request_info_details;
+ uint32_t reserved_2c : 15,
+ prot_coex_lte_tx_while_wlan_rx : 1,
+ prot_coex_lte_tx_while_wlan_tx : 1,
+ reserved_5a : 3,
+ r2r_end_status_to_follow : 1,
+ response_type : 5,
+ reserved_2b : 5,
+ terminate___reserved_g_0005_sequence : 1;
+ uint32_t beamform_masked_user_bitmap_31_16 : 16,
+ beamform_masked_user_bitmap_15_0 : 16;
+ uint32_t pdg_mpdu_ready : 1,
+ beamform_masked_user_bitmap_36_32 : 5,
+ obss_pd_based_transmit_status : 1,
+ srp_based_transmit_status : 1,
+ obss_srg_opport_transmit_status : 1,
+ static_2_pwr_mode_status : 1,
+ use_alt_power_sr : 1,
+ highest_achieved_data_null_ratio : 5,
+ cbf_segment_sent_mask : 8,
+ cbf_segment_request_mask : 8;
+ uint32_t pdg_est_mpdu_tx_count : 16,
+ pdg_mpdu_count : 16;
+ uint32_t pdg_dropped_mpdu_warning : 1,
+ txop_duration : 7,
+ pdg_overview_length : 24;
+ uint32_t reserved_17a : 4,
+ ru_size : 4,
+ num_data_symbols : 16,
+ stbc : 1,
+ fec_type : 1,
+ packet_extension : 3,
+ packet_extension_pe_disambiguity : 1,
+ packet_extension_a_factor : 2;
+ uint32_t tx_pwr_unshared : 8,
+ tx_pwr_shared : 8,
+ reserved_18b : 1,
+ force_extra_symbol : 1,
+ ldpc_extra_symbol : 1,
+ dcm : 1,
+ reserved_18a : 5,
+ cp_setting : 2,
+ ltf_size : 2,
+ num_ltf_symbols : 3;
+ uint32_t cv_corr_status : 8,
+ coex_lte_tx_while_wlan_rx : 1,
+ coex_lte_tx_while_wlan_tx : 1,
+ prot_coex_uwb_tx_while_wlan_rx : 1,
+ prot_coex_uwb_tx_while_wlan_tx : 1,
+ coex_uwb_tx_while_wlan_rx : 1,
+ coex_uwb_tx_while_wlan_tx : 1,
+ __reserved_g_0005_ftm_frame_sent : 1,
+ __reserved_g_0005_sent_dummy_tx : 1,
+ __reserved_g_0005_active_user_map : 16;
+ uint32_t reserved_21b : 3,
+ hw_qos_null_setup_missing : 1,
+ hw_qos_null_bitmap : 8,
+ reserved_21a : 4,
+ current_tx_duration : 16;
+#endif
+};
+
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x00000000
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB 0
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB 0
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x00000001
+
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x00000000
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB 1
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB 1
+#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x00000002
+
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB 2
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB 2
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x00000004
+
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB 3
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB 3
+#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x00000008
+
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 4
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 4
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x00000010
+
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 5
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 5
+#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x00000020
+
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x00000000
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB 6
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB 6
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x00000040
+
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x00000000
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB 7
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB 7
+#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x00000080
+
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB 8
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB 8
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x00000100
+
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB 9
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB 9
+#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x00000200
+
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 10
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 10
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x00000400
+
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 11
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 11
+#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x00000800
+
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x00000000
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12
+#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x00001000
+
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x00000000
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16
+#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x0001e000
+
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x00000000
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x00020000
+
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x00000000
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20
+#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x001c0000
+
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x00000000
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24
+#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x01e00000
+
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x00000000
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30
+#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x7e000000
+
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_OFFSET 0x00000000
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_LSB 31
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MSB 31
+#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MASK 0x80000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000004
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000004
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000
+
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x00000004
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 16
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 19
+#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f0000
+
+#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x00000004
+#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 20
+#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 20
+#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x00100000
+
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_OFFSET 0x00000004
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_LSB 21
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MSB 21
+#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MASK 0x00200000
+
+#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x00000004
+#define TX_FES_STATUS_END_RESERVED_1A_LSB 22
+#define TX_FES_STATUS_END_RESERVED_1A_MSB 26
+#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07c00000
+
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x00000004
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 27
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 27
+#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x08000000
+
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000004
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 28
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 28
+#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000
+
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x00000004
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 29
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 29
+#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x20000000
+
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x00000004
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 30
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 30
+#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x40000000
+
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x00000004
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 31
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 31
+#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x80000000
+
+#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET 0x00000008
+#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB 0
+#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB 0
+#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK 0x00000001
+
+#define TX_FES_STATUS_END_RESERVED_2B_OFFSET 0x00000008
+#define TX_FES_STATUS_END_RESERVED_2B_LSB 1
+#define TX_FES_STATUS_END_RESERVED_2B_MSB 5
+#define TX_FES_STATUS_END_RESERVED_2B_MASK 0x0000003e
+
+#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x00000008
+#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 6
+#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 10
+#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x000007c0
+
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x00000008
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 11
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 11
+#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x00000800
+
+#define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x00000008
+#define TX_FES_STATUS_END_RESERVED_5A_LSB 12
+#define TX_FES_STATUS_END_RESERVED_5A_MSB 14
+#define TX_FES_STATUS_END_RESERVED_5A_MASK 0x00007000
+
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET 0x00000008
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_LSB 15
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_MSB 15
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_MASK 0x00008000
+
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_OFFSET 0x00000008
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_LSB 16
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_MSB 16
+#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_MASK 0x00010000
+
+#define TX_FES_STATUS_END_RESERVED_2C_OFFSET 0x00000008
+#define TX_FES_STATUS_END_RESERVED_2C_LSB 17
+#define TX_FES_STATUS_END_RESERVED_2C_MSB 31
+#define TX_FES_STATUS_END_RESERVED_2C_MASK 0xfffe0000
+
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000c
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff
+
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000c
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 16
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 31
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0xffff0000
+
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x00000010
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 0
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 7
+#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x000000ff
+
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x00000010
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 8
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 15
+#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x0000ff00
+
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x00000010
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 16
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 20
+#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x001f0000
+
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x00000010
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 21
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 21
+#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x00200000
+
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x00000010
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 22
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 22
+#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x00400000
+
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x00000010
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 23
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 23
+#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x00800000
+
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x00000010
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 24
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 24
+#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x01000000
+
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x00000010
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 25
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 25
+#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x02000000
+
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000010
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 26
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 30
+#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x7c000000
+
+#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x00000010
+#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 31
+#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 31
+#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x80000000
+
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x00000014
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 0
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 15
+#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x0000ffff
+
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x00000014
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 16
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 31
+#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0xffff0000
+
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x00000018
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 0
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 23
+#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x00ffffff
+
+#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x00000018
+#define TX_FES_STATUS_END_TXOP_DURATION_LSB 24
+#define TX_FES_STATUS_END_TXOP_DURATION_MSB 30
+#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x7f000000
+
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x00000018
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 31
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 31
+#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x80000000
+
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000001c
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 0
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 1
+#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x00000003
+
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000001c
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2
+#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000004
+
+#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000001c
+#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 3
+#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 5
+#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x00000038
+
+#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000001c
+#define TX_FES_STATUS_END_FEC_TYPE_LSB 6
+#define TX_FES_STATUS_END_FEC_TYPE_MSB 6
+#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x00000040
+
+#define TX_FES_STATUS_END_STBC_OFFSET 0x0000001c
+#define TX_FES_STATUS_END_STBC_LSB 7
+#define TX_FES_STATUS_END_STBC_MSB 7
+#define TX_FES_STATUS_END_STBC_MASK 0x00000080
+
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000001c
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 8
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 23
+#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x00ffff00
+
+#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000001c
+#define TX_FES_STATUS_END_RU_SIZE_LSB 24
+#define TX_FES_STATUS_END_RU_SIZE_MSB 27
+#define TX_FES_STATUS_END_RU_SIZE_MASK 0x0f000000
+
+#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000001c
+#define TX_FES_STATUS_END_RESERVED_17A_LSB 28
+#define TX_FES_STATUS_END_RESERVED_17A_MSB 31
+#define TX_FES_STATUS_END_RESERVED_17A_MASK 0xf0000000
+
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x00000020
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 0
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 2
+#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x00000007
+
+#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x00000020
+#define TX_FES_STATUS_END_LTF_SIZE_LSB 3
+#define TX_FES_STATUS_END_LTF_SIZE_MSB 4
+#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x00000018
+
+#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x00000020
+#define TX_FES_STATUS_END_CP_SETTING_LSB 5
+#define TX_FES_STATUS_END_CP_SETTING_MSB 6
+#define TX_FES_STATUS_END_CP_SETTING_MASK 0x00000060
+
+#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x00000020
+#define TX_FES_STATUS_END_RESERVED_18A_LSB 7
+#define TX_FES_STATUS_END_RESERVED_18A_MSB 11
+#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x00000f80
+
+#define TX_FES_STATUS_END_DCM_OFFSET 0x00000020
+#define TX_FES_STATUS_END_DCM_LSB 12
+#define TX_FES_STATUS_END_DCM_MSB 12
+#define TX_FES_STATUS_END_DCM_MASK 0x00001000
+
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x00000020
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 13
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 13
+#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x00002000
+
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x00000020
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 14
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 14
+#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x00004000
+
+#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x00000020
+#define TX_FES_STATUS_END_RESERVED_18B_LSB 15
+#define TX_FES_STATUS_END_RESERVED_18B_MSB 15
+#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x00008000
+
+#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x00000020
+#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 16
+#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 23
+#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x00ff0000
+
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x00000020
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 24
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 31
+#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0xff000000
+
+#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET 0x00000024
+#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB 0
+#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB 15
+#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK 0x0000ffff
+
+#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET 0x00000024
+#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB 16
+#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB 16
+#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK 0x00010000
+
+#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET 0x00000024
+#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB 17
+#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB 17
+#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK 0x00020000
+
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET 0x00000024
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_LSB 18
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_MSB 18
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_MASK 0x00040000
+
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_OFFSET 0x00000024
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_LSB 19
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_MSB 19
+#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_MASK 0x00080000
+
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET 0x00000024
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_LSB 20
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_MSB 20
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_MASK 0x00100000
+
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_OFFSET 0x00000024
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_LSB 21
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_MSB 21
+#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_MASK 0x00200000
+
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET 0x00000024
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_LSB 22
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_MSB 22
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_MASK 0x00400000
+
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_OFFSET 0x00000024
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_LSB 23
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_MSB 23
+#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_MASK 0x00800000
+
+#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x00000024
+#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 24
+#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 31
+#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0xff000000
+
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x00000028
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 0
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 15
+#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x0000ffff
+
+#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x00000028
+#define TX_FES_STATUS_END_RESERVED_21A_LSB 16
+#define TX_FES_STATUS_END_RESERVED_21A_MSB 19
+#define TX_FES_STATUS_END_RESERVED_21A_MASK 0x000f0000
+
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_OFFSET 0x00000028
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_LSB 20
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MSB 27
+#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MASK 0x0ff00000
+
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_OFFSET 0x00000028
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_LSB 28
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MSB 28
+#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MASK 0x10000000
+
+#define TX_FES_STATUS_END_RESERVED_21B_OFFSET 0x00000028
+#define TX_FES_STATUS_END_RESERVED_21B_LSB 29
+#define TX_FES_STATUS_END_RESERVED_21B_MSB 31
+#define TX_FES_STATUS_END_RESERVED_21B_MASK 0xe0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_prot.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_prot.h
new file mode 100644
index 0000000000000000000000000000000000000000..b595140a53bf7d5c95001307b4d441e68f9719c1
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_prot.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_PROT_H_
+#define _TX_FES_STATUS_PROT_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 3
+
+struct tx_fes_status_prot {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t success : 1,
+ phytx_pkt_end_info_valid : 1,
+ phytx_abort_request_info_valid : 1,
+ reserved_0 : 20,
+ pkt_type : 4,
+ dot11ax_su_extended : 1,
+ rate_mcs : 4;
+ uint32_t frame_type : 2,
+ frame_subtype : 4,
+ rx_pwr_mgmt : 1,
+ status : 1,
+ duration_field : 16,
+ reserved_1a : 2,
+ agc_cbw : 3,
+ service_cbw : 3;
+ struct phytx_abort_request_info phytx_abort_request_info_details;
+ uint16_t reserved_2a : 16;
+#else
+ uint32_t rate_mcs : 4,
+ dot11ax_su_extended : 1,
+ pkt_type : 4,
+ reserved_0 : 20,
+ phytx_abort_request_info_valid : 1,
+ phytx_pkt_end_info_valid : 1,
+ success : 1;
+ uint32_t service_cbw : 3,
+ agc_cbw : 3,
+ reserved_1a : 2,
+ duration_field : 16,
+ status : 1,
+ rx_pwr_mgmt : 1,
+ frame_subtype : 4,
+ frame_type : 2;
+ uint32_t reserved_2a : 16;
+ struct phytx_abort_request_info phytx_abort_request_info_details;
+#endif
+};
+
+#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x00000000
+#define TX_FES_STATUS_PROT_SUCCESS_LSB 0
+#define TX_FES_STATUS_PROT_SUCCESS_MSB 0
+#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x00000001
+
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x00000000
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1
+#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x00000002
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000000
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x00000004
+
+#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x00000000
+#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3
+#define TX_FES_STATUS_PROT_RESERVED_0_MSB 22
+#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x007ffff8
+
+#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x00000000
+#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23
+#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26
+#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x07800000
+
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x00000000
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27
+#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x08000000
+
+#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x00000000
+#define TX_FES_STATUS_PROT_RATE_MCS_LSB 28
+#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31
+#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0xf0000000
+
+#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x00000004
+#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 0
+#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 1
+#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x00000003
+
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x00000004
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 2
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 5
+#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c
+
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x00000004
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 6
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 6
+#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x00000040
+
+#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x00000004
+#define TX_FES_STATUS_PROT_STATUS_LSB 7
+#define TX_FES_STATUS_PROT_STATUS_MSB 7
+#define TX_FES_STATUS_PROT_STATUS_MASK 0x00000080
+
+#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x00000004
+#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 8
+#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 23
+#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff00
+
+#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x00000004
+#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 24
+#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 25
+#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x03000000
+
+#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x00000004
+#define TX_FES_STATUS_PROT_AGC_CBW_LSB 26
+#define TX_FES_STATUS_PROT_AGC_CBW_MSB 28
+#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c000000
+
+#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x00000004
+#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 29
+#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 31
+#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe0000000
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000008
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000008
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00
+
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000008
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15
+#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000
+
+#define TX_FES_STATUS_PROT_RESERVED_2A_OFFSET 0x00000008
+#define TX_FES_STATUS_PROT_RESERVED_2A_LSB 16
+#define TX_FES_STATUS_PROT_RESERVED_2A_MSB 31
+#define TX_FES_STATUS_PROT_RESERVED_2A_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start.h
new file mode 100644
index 0000000000000000000000000000000000000000..b8704980b17813ab8a247c7ef6aa1569e23e536b
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_START_H_
+#define _TX_FES_STATUS_START_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_START 4
+
+struct tx_fes_status_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t schedule_id : 32;
+ uint32_t reserved_1a : 8,
+ transmit_start_reason : 3,
+ disabled_user_bitmap_36_32 : 5,
+ schedule_cmd_ring_id : 5,
+ fes_control_mode : 2,
+ schedule_try : 4,
+ medium_prot_type : 3,
+ reserved_1b : 2;
+ uint32_t optimal_bw_try_count : 4,
+ number_of_users : 7,
+ coex_nack_count : 5,
+ cca_ed0 : 16;
+ uint32_t disabled_user_bitmap_31_0 : 32;
+#else
+ uint32_t schedule_id : 32;
+ uint32_t reserved_1b : 2,
+ medium_prot_type : 3,
+ schedule_try : 4,
+ fes_control_mode : 2,
+ schedule_cmd_ring_id : 5,
+ disabled_user_bitmap_36_32 : 5,
+ transmit_start_reason : 3,
+ reserved_1a : 8;
+ uint32_t cca_ed0 : 16,
+ coex_nack_count : 5,
+ number_of_users : 7,
+ optimal_bw_try_count : 4;
+ uint32_t disabled_user_bitmap_31_0 : 32;
+#endif
+};
+
+#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x00000000
+#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0
+#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31
+#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0xffffffff
+
+#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x00000004
+#define TX_FES_STATUS_START_RESERVED_1A_LSB 0
+#define TX_FES_STATUS_START_RESERVED_1A_MSB 7
+#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff
+
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x00000004
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 8
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 10
+#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x00000700
+
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x00000004
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 11
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 15
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f800
+
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x00000004
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 16
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 20
+#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f0000
+
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x00000004
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 21
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 22
+#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x00600000
+
+#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x00000004
+#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 23
+#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 26
+#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x07800000
+
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x00000004
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 27
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 29
+#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x38000000
+
+#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x00000004
+#define TX_FES_STATUS_START_RESERVED_1B_LSB 30
+#define TX_FES_STATUS_START_RESERVED_1B_MSB 31
+#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc0000000
+
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x00000008
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3
+#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x0000000f
+
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x00000008
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10
+#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x000007f0
+
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x00000008
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15
+#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x0000f800
+
+#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x00000008
+#define TX_FES_STATUS_START_CCA_ED0_LSB 16
+#define TX_FES_STATUS_START_CCA_ED0_MSB 31
+#define TX_FES_STATUS_START_CCA_ED0_MASK 0xffff0000
+
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 0
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 31
+#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start_ppdu.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start_ppdu.h
new file mode 100644
index 0000000000000000000000000000000000000000..21fbf64bae9c70c8d8398163e55ae092f9330b54
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start_ppdu.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_START_PPDU_H_
+#define _TX_FES_STATUS_START_PPDU_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 4
+
+struct tx_fes_status_start_ppdu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t ppdu_timestamp_lower_32 : 32;
+ uint32_t ppdu_timestamp_upper_32 : 32;
+ uint32_t subband_mask : 16,
+ ndp_frame : 2,
+ reserved_2b : 2,
+ coex_based_tx_bw : 3,
+ coex_based_ant_mask : 8,
+ reserved_2c : 1;
+ uint32_t coex_based_tx_pwr_shared_ant : 8,
+ coex_based_tx_pwr_ant : 8,
+ concurrent_bt_tx : 1,
+ concurrent_wlan_tx : 1,
+ concurrent_wan_tx : 1,
+ concurrent_wan_rx : 1,
+ coex_pwr_reduction_bt : 1,
+ coex_pwr_reduction_wlan : 1,
+ coex_pwr_reduction_wan : 1,
+ coex_result_alt_based : 1,
+ request_packet_bw : 3,
+ response_type : 5;
+#else
+ uint32_t ppdu_timestamp_lower_32 : 32;
+ uint32_t ppdu_timestamp_upper_32 : 32;
+ uint32_t reserved_2c : 1,
+ coex_based_ant_mask : 8,
+ coex_based_tx_bw : 3,
+ reserved_2b : 2,
+ ndp_frame : 2,
+ subband_mask : 16;
+ uint32_t response_type : 5,
+ request_packet_bw : 3,
+ coex_result_alt_based : 1,
+ coex_pwr_reduction_wan : 1,
+ coex_pwr_reduction_wlan : 1,
+ coex_pwr_reduction_bt : 1,
+ concurrent_wan_rx : 1,
+ concurrent_wan_tx : 1,
+ concurrent_wlan_tx : 1,
+ concurrent_bt_tx : 1,
+ coex_based_tx_pwr_ant : 8,
+ coex_based_tx_pwr_shared_ant : 8;
+#endif
+};
+
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x00000000
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0xffffffff
+
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x00000004
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 0
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 31
+#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff
+
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x00000008
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15
+#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x0000ffff
+
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x00000008
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 17
+#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x00030000
+
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x00000008
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 18
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19
+#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x000c0000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x00000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x00700000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x00000008
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x7f800000
+
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x00000008
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31
+#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x80000000
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 0
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 7
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff
+
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 8
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 15
+#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff00
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 16
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 16
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x00010000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 17
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 17
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x00020000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 18
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 18
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x00040000
+
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 19
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 19
+#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x00080000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 20
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 20
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x00100000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 21
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 21
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x00200000
+
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 22
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 22
+#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x00400000
+
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 23
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 23
+#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x00800000
+
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 24
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 26
+#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x07000000
+
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 27
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 31
+#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf8000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start_prot.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start_prot.h
new file mode 100644
index 0000000000000000000000000000000000000000..4e3bbe0004a5eedef1df5a9dc05d8ddbbfb43a72
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_start_prot.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_START_PROT_H_
+#define _TX_FES_STATUS_START_PROT_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 4
+
+struct tx_fes_status_start_prot {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t prot_timestamp_lower_32 : 32;
+ uint32_t prot_timestamp_upper_32 : 32;
+ uint32_t subband_mask : 16,
+ reserved_2b : 4,
+ prot_coex_based_tx_bw : 3,
+ prot_coex_based_ant_mask : 8,
+ prot_coex_result_alt_based : 1;
+ uint32_t prot_coex_tx_pwr_shared_ant : 8,
+ prot_coex_tx_pwr_ant : 8,
+ prot_concurrent_bt_tx : 1,
+ prot_concurrent_wlan_tx : 1,
+ prot_concurrent_wan_tx : 1,
+ prot_concurrent_wan_rx : 1,
+ prot_coex_pwr_reduction_bt : 1,
+ prot_coex_pwr_reduction_wlan : 1,
+ prot_coex_pwr_reduction_wan : 1,
+ prot_request_packet_bw : 3,
+ response_type : 5,
+ reserved_3a : 1;
+#else
+ uint32_t prot_timestamp_lower_32 : 32;
+ uint32_t prot_timestamp_upper_32 : 32;
+ uint32_t prot_coex_result_alt_based : 1,
+ prot_coex_based_ant_mask : 8,
+ prot_coex_based_tx_bw : 3,
+ reserved_2b : 4,
+ subband_mask : 16;
+ uint32_t reserved_3a : 1,
+ response_type : 5,
+ prot_request_packet_bw : 3,
+ prot_coex_pwr_reduction_wan : 1,
+ prot_coex_pwr_reduction_wlan : 1,
+ prot_coex_pwr_reduction_bt : 1,
+ prot_concurrent_wan_rx : 1,
+ prot_concurrent_wan_tx : 1,
+ prot_concurrent_wlan_tx : 1,
+ prot_concurrent_bt_tx : 1,
+ prot_coex_tx_pwr_ant : 8,
+ prot_coex_tx_pwr_shared_ant : 8;
+#endif
+};
+
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x00000000
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0xffffffff
+
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x00000004
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 0
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 31
+#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff
+
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x00000008
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15
+#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x0000ffff
+
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x00000008
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19
+#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x000f0000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x00000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x00700000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x00000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30
+#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x7f800000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x00000008
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31
+#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x80000000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 0
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 7
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 8
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 15
+#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff00
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 16
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 16
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x00010000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 17
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 17
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x00020000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 18
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 18
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x00040000
+
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 19
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 19
+#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x00080000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 20
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 20
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x00100000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 21
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 21
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x00200000
+
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 22
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 22
+#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x00400000
+
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 23
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 25
+#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x03800000
+
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 26
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 30
+#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c000000
+
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000c
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 31
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 31
+#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_user_ppdu.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_user_ppdu.h
new file mode 100644
index 0000000000000000000000000000000000000000..a18815551738b0510edaad983001caeb6faa47be
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_user_ppdu.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_USER_PPDU_H_
+#define _TX_FES_STATUS_USER_PPDU_H_
+
+#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6
+
+struct tx_fes_status_user_ppdu {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t underflow_mpdu_count : 9,
+ data_underflow_warning : 2,
+ bw_drop_underflow_warning : 1,
+ qc_eosp_setting : 1,
+ fc_more_data_setting : 1,
+ fc_pwr_mgt_setting : 1,
+ mpdu_tx_count : 9,
+ user_blocked : 1,
+ pre_trig_response_delim_count : 7;
+ uint32_t underflow_byte_count : 16,
+ coex_abort_mpdu_count_valid : 1,
+ coex_abort_mpdu_count : 9,
+ transmitted_tid : 4,
+ txdma_dropped_mpdu_warning : 1,
+ reserved_1 : 1;
+ uint32_t duration : 16,
+ num_eof_delim_added : 16;
+ uint32_t psdu_octet : 24,
+ qos_buf_state : 8;
+ uint32_t num_null_delim_added : 22,
+ reserved_4a : 2,
+ cv_corr_user_valid_in_phy : 1,
+ nss : 3,
+ mcs : 4;
+ uint32_t ht_control : 32;
+#else
+ uint32_t pre_trig_response_delim_count : 7,
+ user_blocked : 1,
+ mpdu_tx_count : 9,
+ fc_pwr_mgt_setting : 1,
+ fc_more_data_setting : 1,
+ qc_eosp_setting : 1,
+ bw_drop_underflow_warning : 1,
+ data_underflow_warning : 2,
+ underflow_mpdu_count : 9;
+ uint32_t reserved_1 : 1,
+ txdma_dropped_mpdu_warning : 1,
+ transmitted_tid : 4,
+ coex_abort_mpdu_count : 9,
+ coex_abort_mpdu_count_valid : 1,
+ underflow_byte_count : 16;
+ uint32_t num_eof_delim_added : 16,
+ duration : 16;
+ uint32_t qos_buf_state : 8,
+ psdu_octet : 24;
+ uint32_t mcs : 4,
+ nss : 3,
+ cv_corr_user_valid_in_phy : 1,
+ reserved_4a : 2,
+ num_null_delim_added : 22;
+ uint32_t ht_control : 32;
+#endif
+};
+
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x00000000
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x000001ff
+
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x00000000
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10
+#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x00000600
+
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x00000000
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11
+#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x00000800
+
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x00000000
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12
+#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x00001000
+
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x00000000
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 13
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 13
+#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x00002000
+
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x00000000
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 14
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 14
+#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x00004000
+
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x00000000
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 15
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23
+#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x00ff8000
+
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x00000000
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24
+#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x01000000
+
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x00000000
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31
+#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0xfe000000
+
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x00000004
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 0
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 15
+#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff
+
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x00000004
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 16
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 16
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x00010000
+
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x00000004
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 17
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 25
+#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe0000
+
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x00000004
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 26
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 29
+#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c000000
+
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x00000004
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 30
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 30
+#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x40000000
+
+#define TX_FES_STATUS_USER_PPDU_RESERVED_1_OFFSET 0x00000004
+#define TX_FES_STATUS_USER_PPDU_RESERVED_1_LSB 31
+#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MSB 31
+#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MASK 0x80000000
+
+#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x00000008
+#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0
+#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15
+#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x0000ffff
+
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x00000008
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31
+#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0xffff0000
+
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000c
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 0
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 23
+#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff
+
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000c
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 24
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 31
+#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff000000
+
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x00000010
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21
+#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x003fffff
+
+#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_OFFSET 0x00000010
+#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_LSB 22
+#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MSB 23
+#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MASK 0x00c00000
+
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x00000010
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 24
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 24
+#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x01000000
+
+#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x00000010
+#define TX_FES_STATUS_USER_PPDU_NSS_LSB 25
+#define TX_FES_STATUS_USER_PPDU_NSS_MSB 27
+#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x0e000000
+
+#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x00000010
+#define TX_FES_STATUS_USER_PPDU_MCS_LSB 28
+#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31
+#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0xf0000000
+
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x00000014
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 0
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 31
+#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_user_response.h b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_user_response.h
new file mode 100644
index 0000000000000000000000000000000000000000..f1255bdb12b3501abd310fd9b0bbd3a15da637c4
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_fes_status_user_response.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FES_STATUS_USER_RESPONSE_H_
+#define _TX_FES_STATUS_USER_RESPONSE_H_
+
+#include "phytx_abort_request_info.h"
+#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2
+
+struct tx_fes_status_user_response {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t fes_transmit_result : 4,
+ reserved_0 : 28;
+ struct phytx_abort_request_info phytx_abort_request_info_details;
+ uint16_t reserved_after_struct16 : 16;
+#else
+ uint32_t reserved_0 : 28,
+ fes_transmit_result : 4;
+ uint32_t reserved_after_struct16 : 16;
+ struct phytx_abort_request_info phytx_abort_request_info_details;
+#endif
+};
+
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x00000000
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3
+#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x0000000f
+
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x00000000
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 31
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0xfffffff0
+
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff
+
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000004
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00
+
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000004
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15
+#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000
+
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x00000004
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 16
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 31
+#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_flush_req.h b/drivers/staging/fw-api/hw/peach/v1/tx_flush_req.h
new file mode 100644
index 0000000000000000000000000000000000000000..1ee52b57ad220b97d68cdb7dd4ab9b773582da90
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_flush_req.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_FLUSH_REQ_H_
+#define _TX_FLUSH_REQ_H_
+
+#define NUM_OF_DWORDS_TX_FLUSH_REQ 1
+
+struct tx_flush_req {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t flush_req_reason : 8,
+ phytx_abort_reason : 8,
+ flush_req_user_number_or_link_id : 6,
+ mlo_abort_reason : 5,
+ reserved_0a : 5;
+#else
+ uint32_t reserved_0a : 5,
+ mlo_abort_reason : 5,
+ flush_req_user_number_or_link_id : 6,
+ phytx_abort_reason : 8,
+ flush_req_reason : 8;
+#endif
+};
+
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x00000000
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7
+#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x000000ff
+
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x00000000
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15
+#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x0000ff00
+
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x00000000
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21
+#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x003f0000
+
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x00000000
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26
+#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x07c00000
+
+#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x00000000
+#define TX_FLUSH_REQ_RESERVED_0A_LSB 27
+#define TX_FLUSH_REQ_RESERVED_0A_MSB 31
+#define TX_FLUSH_REQ_RESERVED_0A_MASK 0xf8000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_mpdu_start.h b/drivers/staging/fw-api/hw/peach/v1/tx_mpdu_start.h
new file mode 100644
index 0000000000000000000000000000000000000000..aa7bebca07adfdfcc144f1d8a6c2f72aa34bd5b9
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_mpdu_start.h
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_MPDU_START_H_
+#define _TX_MPDU_START_H_
+
+#define NUM_OF_DWORDS_TX_MPDU_START 9
+
+struct tx_mpdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t mpdu_length : 14,
+ frame_not_from_tqm : 1,
+ vht_control_present : 1,
+ mpdu_header_length : 8,
+ retry_count : 7,
+ wds : 1;
+ uint32_t pn_31_0 : 32;
+ uint32_t pn_47_32 : 16,
+ mpdu_sequence_number : 12,
+ raw_already_encrypted : 1,
+ frame_type : 2,
+ txdma_dropped_mpdu_warning : 1;
+ uint32_t iv_byte_0 : 8,
+ iv_byte_1 : 8,
+ iv_byte_2 : 8,
+ iv_byte_3 : 8;
+ uint32_t iv_byte_4 : 8,
+ iv_byte_5 : 8,
+ iv_byte_6 : 8,
+ iv_byte_7 : 8;
+ uint32_t iv_byte_8 : 8,
+ iv_byte_9 : 8,
+ iv_byte_10 : 8,
+ iv_byte_11 : 8;
+ uint32_t iv_byte_12 : 8,
+ iv_byte_13 : 8,
+ iv_byte_14 : 8,
+ iv_byte_15 : 8;
+ uint32_t iv_byte_16 : 8,
+ iv_byte_17 : 8,
+ iv_len : 5,
+ icv_len : 5,
+ vht_control_offset : 6;
+ uint32_t mpdu_type : 1,
+ transmit_bw_restriction : 1,
+ allowed_transmit_bw : 4,
+ tx_notify_frame : 3,
+ reserved_8a : 23;
+#else
+ uint32_t wds : 1,
+ retry_count : 7,
+ mpdu_header_length : 8,
+ vht_control_present : 1,
+ frame_not_from_tqm : 1,
+ mpdu_length : 14;
+ uint32_t pn_31_0 : 32;
+ uint32_t txdma_dropped_mpdu_warning : 1,
+ frame_type : 2,
+ raw_already_encrypted : 1,
+ mpdu_sequence_number : 12,
+ pn_47_32 : 16;
+ uint32_t iv_byte_3 : 8,
+ iv_byte_2 : 8,
+ iv_byte_1 : 8,
+ iv_byte_0 : 8;
+ uint32_t iv_byte_7 : 8,
+ iv_byte_6 : 8,
+ iv_byte_5 : 8,
+ iv_byte_4 : 8;
+ uint32_t iv_byte_11 : 8,
+ iv_byte_10 : 8,
+ iv_byte_9 : 8,
+ iv_byte_8 : 8;
+ uint32_t iv_byte_15 : 8,
+ iv_byte_14 : 8,
+ iv_byte_13 : 8,
+ iv_byte_12 : 8;
+ uint32_t vht_control_offset : 6,
+ icv_len : 5,
+ iv_len : 5,
+ iv_byte_17 : 8,
+ iv_byte_16 : 8;
+ uint32_t reserved_8a : 23,
+ tx_notify_frame : 3,
+ allowed_transmit_bw : 4,
+ transmit_bw_restriction : 1,
+ mpdu_type : 1;
+#endif
+};
+
+#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x00000000
+#define TX_MPDU_START_MPDU_LENGTH_LSB 0
+#define TX_MPDU_START_MPDU_LENGTH_MSB 13
+#define TX_MPDU_START_MPDU_LENGTH_MASK 0x00003fff
+
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x00000000
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14
+#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x00004000
+
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x00000000
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15
+#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x00008000
+
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x00000000
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23
+#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x00ff0000
+
+#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x00000000
+#define TX_MPDU_START_RETRY_COUNT_LSB 24
+#define TX_MPDU_START_RETRY_COUNT_MSB 30
+#define TX_MPDU_START_RETRY_COUNT_MASK 0x7f000000
+
+#define TX_MPDU_START_WDS_OFFSET 0x00000000
+#define TX_MPDU_START_WDS_LSB 31
+#define TX_MPDU_START_WDS_MSB 31
+#define TX_MPDU_START_WDS_MASK 0x80000000
+
+#define TX_MPDU_START_PN_31_0_OFFSET 0x00000004
+#define TX_MPDU_START_PN_31_0_LSB 0
+#define TX_MPDU_START_PN_31_0_MSB 31
+#define TX_MPDU_START_PN_31_0_MASK 0xffffffff
+
+#define TX_MPDU_START_PN_47_32_OFFSET 0x00000008
+#define TX_MPDU_START_PN_47_32_LSB 0
+#define TX_MPDU_START_PN_47_32_MSB 15
+#define TX_MPDU_START_PN_47_32_MASK 0x0000ffff
+
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27
+#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x0fff0000
+
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x00000008
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28
+#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x10000000
+
+#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x00000008
+#define TX_MPDU_START_FRAME_TYPE_LSB 29
+#define TX_MPDU_START_FRAME_TYPE_MSB 30
+#define TX_MPDU_START_FRAME_TYPE_MASK 0x60000000
+
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x00000008
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31
+#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x80000000
+
+#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000c
+#define TX_MPDU_START_IV_BYTE_0_LSB 0
+#define TX_MPDU_START_IV_BYTE_0_MSB 7
+#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff
+
+#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000c
+#define TX_MPDU_START_IV_BYTE_1_LSB 8
+#define TX_MPDU_START_IV_BYTE_1_MSB 15
+#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff00
+
+#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000c
+#define TX_MPDU_START_IV_BYTE_2_LSB 16
+#define TX_MPDU_START_IV_BYTE_2_MSB 23
+#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff0000
+
+#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000c
+#define TX_MPDU_START_IV_BYTE_3_LSB 24
+#define TX_MPDU_START_IV_BYTE_3_MSB 31
+#define TX_MPDU_START_IV_BYTE_3_MASK 0xff000000
+
+#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x00000010
+#define TX_MPDU_START_IV_BYTE_4_LSB 0
+#define TX_MPDU_START_IV_BYTE_4_MSB 7
+#define TX_MPDU_START_IV_BYTE_4_MASK 0x000000ff
+
+#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x00000010
+#define TX_MPDU_START_IV_BYTE_5_LSB 8
+#define TX_MPDU_START_IV_BYTE_5_MSB 15
+#define TX_MPDU_START_IV_BYTE_5_MASK 0x0000ff00
+
+#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x00000010
+#define TX_MPDU_START_IV_BYTE_6_LSB 16
+#define TX_MPDU_START_IV_BYTE_6_MSB 23
+#define TX_MPDU_START_IV_BYTE_6_MASK 0x00ff0000
+
+#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x00000010
+#define TX_MPDU_START_IV_BYTE_7_LSB 24
+#define TX_MPDU_START_IV_BYTE_7_MSB 31
+#define TX_MPDU_START_IV_BYTE_7_MASK 0xff000000
+
+#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x00000014
+#define TX_MPDU_START_IV_BYTE_8_LSB 0
+#define TX_MPDU_START_IV_BYTE_8_MSB 7
+#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff
+
+#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x00000014
+#define TX_MPDU_START_IV_BYTE_9_LSB 8
+#define TX_MPDU_START_IV_BYTE_9_MSB 15
+#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff00
+
+#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x00000014
+#define TX_MPDU_START_IV_BYTE_10_LSB 16
+#define TX_MPDU_START_IV_BYTE_10_MSB 23
+#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff0000
+
+#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x00000014
+#define TX_MPDU_START_IV_BYTE_11_LSB 24
+#define TX_MPDU_START_IV_BYTE_11_MSB 31
+#define TX_MPDU_START_IV_BYTE_11_MASK 0xff000000
+
+#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x00000018
+#define TX_MPDU_START_IV_BYTE_12_LSB 0
+#define TX_MPDU_START_IV_BYTE_12_MSB 7
+#define TX_MPDU_START_IV_BYTE_12_MASK 0x000000ff
+
+#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x00000018
+#define TX_MPDU_START_IV_BYTE_13_LSB 8
+#define TX_MPDU_START_IV_BYTE_13_MSB 15
+#define TX_MPDU_START_IV_BYTE_13_MASK 0x0000ff00
+
+#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x00000018
+#define TX_MPDU_START_IV_BYTE_14_LSB 16
+#define TX_MPDU_START_IV_BYTE_14_MSB 23
+#define TX_MPDU_START_IV_BYTE_14_MASK 0x00ff0000
+
+#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x00000018
+#define TX_MPDU_START_IV_BYTE_15_LSB 24
+#define TX_MPDU_START_IV_BYTE_15_MSB 31
+#define TX_MPDU_START_IV_BYTE_15_MASK 0xff000000
+
+#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000001c
+#define TX_MPDU_START_IV_BYTE_16_LSB 0
+#define TX_MPDU_START_IV_BYTE_16_MSB 7
+#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff
+
+#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000001c
+#define TX_MPDU_START_IV_BYTE_17_LSB 8
+#define TX_MPDU_START_IV_BYTE_17_MSB 15
+#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff00
+
+#define TX_MPDU_START_IV_LEN_OFFSET 0x0000001c
+#define TX_MPDU_START_IV_LEN_LSB 16
+#define TX_MPDU_START_IV_LEN_MSB 20
+#define TX_MPDU_START_IV_LEN_MASK 0x001f0000
+
+#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000001c
+#define TX_MPDU_START_ICV_LEN_LSB 21
+#define TX_MPDU_START_ICV_LEN_MSB 25
+#define TX_MPDU_START_ICV_LEN_MASK 0x03e00000
+
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000001c
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 26
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 31
+#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc000000
+
+#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x00000020
+#define TX_MPDU_START_MPDU_TYPE_LSB 0
+#define TX_MPDU_START_MPDU_TYPE_MSB 0
+#define TX_MPDU_START_MPDU_TYPE_MASK 0x00000001
+
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x00000020
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1
+#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x00000002
+
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x00000020
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5
+#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x0000003c
+
+#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x00000020
+#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6
+#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8
+#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x000001c0
+
+#define TX_MPDU_START_RESERVED_8A_OFFSET 0x00000020
+#define TX_MPDU_START_RESERVED_8A_LSB 9
+#define TX_MPDU_START_RESERVED_8A_MSB 31
+#define TX_MPDU_START_RESERVED_8A_MASK 0xfffffe00
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_msdu_extension.h b/drivers/staging/fw-api/hw/peach/v1/tx_msdu_extension.h
new file mode 100644
index 0000000000000000000000000000000000000000..6bceb28ed8381d22bd09a9da9d4923808221afd5
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_msdu_extension.h
@@ -0,0 +1,372 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_MSDU_EXTENSION_H_
+#define _TX_MSDU_EXTENSION_H_
+
+#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
+
+struct tx_msdu_extension {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tso_enable : 1,
+ reserved_0a : 6,
+ tcp_flag : 9,
+ tcp_flag_mask : 9,
+ reserved_0b : 7;
+ uint32_t l2_length : 16,
+ ip_length : 16;
+ uint32_t tcp_seq_number : 32;
+ uint32_t ip_identification : 16,
+ udp_length : 16;
+ uint32_t checksum_offset : 14,
+ partial_checksum_en : 1,
+ reserved_4a : 1,
+ payload_start_offset : 14,
+ reserved_4b : 2;
+ uint32_t payload_end_offset : 14,
+ reserved_5a : 2,
+ wds : 1,
+ reserved_5b : 15;
+ uint32_t buf0_ptr_31_0 : 32;
+ uint32_t buf0_ptr_39_32 : 8,
+ extn_override : 1,
+ encap_type : 2,
+ encrypt_type : 4,
+ tqm_no_drop : 1,
+ buf0_len : 16;
+ uint32_t buf1_ptr_31_0 : 32;
+ uint32_t buf1_ptr_39_32 : 8,
+ epd : 1,
+ mesh_enable : 2,
+ reserved_9a : 5,
+ buf1_len : 16;
+ uint32_t buf2_ptr_31_0 : 32;
+ uint32_t buf2_ptr_39_32 : 8,
+ dscp_tid_table_num : 6,
+ reserved_11a : 2,
+ buf2_len : 16;
+ uint32_t buf3_ptr_31_0 : 32;
+ uint32_t buf3_ptr_39_32 : 8,
+ reserved_13a : 8,
+ buf3_len : 16;
+ uint32_t buf4_ptr_31_0 : 32;
+ uint32_t buf4_ptr_39_32 : 8,
+ reserved_15a : 8,
+ buf4_len : 16;
+ uint32_t buf5_ptr_31_0 : 32;
+ uint32_t buf5_ptr_39_32 : 8,
+ reserved_17a : 8,
+ buf5_len : 16;
+#else
+ uint32_t reserved_0b : 7,
+ tcp_flag_mask : 9,
+ tcp_flag : 9,
+ reserved_0a : 6,
+ tso_enable : 1;
+ uint32_t ip_length : 16,
+ l2_length : 16;
+ uint32_t tcp_seq_number : 32;
+ uint32_t udp_length : 16,
+ ip_identification : 16;
+ uint32_t reserved_4b : 2,
+ payload_start_offset : 14,
+ reserved_4a : 1,
+ partial_checksum_en : 1,
+ checksum_offset : 14;
+ uint32_t reserved_5b : 15,
+ wds : 1,
+ reserved_5a : 2,
+ payload_end_offset : 14;
+ uint32_t buf0_ptr_31_0 : 32;
+ uint32_t buf0_len : 16,
+ tqm_no_drop : 1,
+ encrypt_type : 4,
+ encap_type : 2,
+ extn_override : 1,
+ buf0_ptr_39_32 : 8;
+ uint32_t buf1_ptr_31_0 : 32;
+ uint32_t buf1_len : 16,
+ reserved_9a : 5,
+ mesh_enable : 2,
+ epd : 1,
+ buf1_ptr_39_32 : 8;
+ uint32_t buf2_ptr_31_0 : 32;
+ uint32_t buf2_len : 16,
+ reserved_11a : 2,
+ dscp_tid_table_num : 6,
+ buf2_ptr_39_32 : 8;
+ uint32_t buf3_ptr_31_0 : 32;
+ uint32_t buf3_len : 16,
+ reserved_13a : 8,
+ buf3_ptr_39_32 : 8;
+ uint32_t buf4_ptr_31_0 : 32;
+ uint32_t buf4_len : 16,
+ reserved_15a : 8,
+ buf4_ptr_39_32 : 8;
+ uint32_t buf5_ptr_31_0 : 32;
+ uint32_t buf5_len : 16,
+ reserved_17a : 8,
+ buf5_ptr_39_32 : 8;
+#endif
+};
+
+#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000
+#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0
+#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0
+#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001
+
+#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000
+#define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1
+#define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6
+#define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e
+
+#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000
+#define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7
+#define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80
+
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24
+#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000
+
+#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000
+#define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25
+#define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31
+#define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000
+
+#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004
+#define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0
+#define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15
+#define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff
+
+#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004
+#define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16
+#define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31
+#define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000
+
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31
+#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff
+
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15
+#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff
+
+#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c
+#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16
+#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31
+#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000
+
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13
+#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff
+
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14
+#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000
+
+#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010
+#define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15
+#define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15
+#define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000
+
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29
+#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000
+
+#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010
+#define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30
+#define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31
+#define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000
+
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13
+#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff
+
+#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014
+#define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14
+#define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15
+#define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000
+
+#define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014
+#define TX_MSDU_EXTENSION_WDS_LSB 16
+#define TX_MSDU_EXTENSION_WDS_MSB 16
+#define TX_MSDU_EXTENSION_WDS_MASK 0x00010000
+
+#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014
+#define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17
+#define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31
+#define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000
+
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31
+#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7
+#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff
+
+#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_OFFSET 0x0000001c
+#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_LSB 8
+#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MSB 8
+#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MASK 0x00000100
+
+#define TX_MSDU_EXTENSION_ENCAP_TYPE_OFFSET 0x0000001c
+#define TX_MSDU_EXTENSION_ENCAP_TYPE_LSB 9
+#define TX_MSDU_EXTENSION_ENCAP_TYPE_MSB 10
+#define TX_MSDU_EXTENSION_ENCAP_TYPE_MASK 0x00000600
+
+#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_OFFSET 0x0000001c
+#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_LSB 11
+#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MSB 14
+#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MASK 0x00007800
+
+#define TX_MSDU_EXTENSION_TQM_NO_DROP_OFFSET 0x0000001c
+#define TX_MSDU_EXTENSION_TQM_NO_DROP_LSB 15
+#define TX_MSDU_EXTENSION_TQM_NO_DROP_MSB 15
+#define TX_MSDU_EXTENSION_TQM_NO_DROP_MASK 0x00008000
+
+#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c
+#define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16
+#define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31
+#define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31
+#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7
+#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff
+
+#define TX_MSDU_EXTENSION_EPD_OFFSET 0x00000024
+#define TX_MSDU_EXTENSION_EPD_LSB 8
+#define TX_MSDU_EXTENSION_EPD_MSB 8
+#define TX_MSDU_EXTENSION_EPD_MASK 0x00000100
+
+#define TX_MSDU_EXTENSION_MESH_ENABLE_OFFSET 0x00000024
+#define TX_MSDU_EXTENSION_MESH_ENABLE_LSB 9
+#define TX_MSDU_EXTENSION_MESH_ENABLE_MSB 10
+#define TX_MSDU_EXTENSION_MESH_ENABLE_MASK 0x00000600
+
+#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024
+#define TX_MSDU_EXTENSION_RESERVED_9A_LSB 11
+#define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15
+#define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000f800
+
+#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024
+#define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16
+#define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31
+#define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31
+#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7
+#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff
+
+#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_OFFSET 0x0000002c
+#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_LSB 8
+#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MSB 13
+#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MASK 0x00003f00
+
+#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c
+#define TX_MSDU_EXTENSION_RESERVED_11A_LSB 14
+#define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15
+#define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000c000
+
+#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c
+#define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16
+#define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31
+#define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31
+#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7
+#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034
+#define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8
+#define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15
+#define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034
+#define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16
+#define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31
+#define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31
+#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7
+#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c
+#define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8
+#define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15
+#define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c
+#define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16
+#define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31
+#define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000
+
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31
+#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff
+
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7
+#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff
+
+#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044
+#define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8
+#define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15
+#define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00
+
+#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044
+#define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16
+#define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31
+#define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_msdu_start.h b/drivers/staging/fw-api/hw/peach/v1/tx_msdu_start.h
new file mode 100644
index 0000000000000000000000000000000000000000..3b9e5b1c2c2f27e56b8ae7c1e8eda7a71bbf7195
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_msdu_start.h
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_MSDU_START_H_
+#define _TX_MSDU_START_H_
+
+#define NUM_OF_DWORDS_TX_MSDU_START 7
+
+struct tx_msdu_start {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t msdu_len : 14,
+ first_msdu : 1,
+ last_msdu : 1,
+ encap_type : 2,
+ epd_en : 1,
+ da_sa_present : 2,
+ ipv4_checksum_en : 1,
+ udp_over_ipv4_checksum_en : 1,
+ udp_over_ipv6_checksum_en : 1,
+ tcp_over_ipv4_checksum_en : 1,
+ tcp_over_ipv6_checksum_en : 1,
+ dummy_msdu_delimitation : 1,
+ reserved_0a : 5;
+ uint32_t tso_enable : 1,
+ reserved_1a : 6,
+ tcp_flag : 9,
+ tcp_flag_mask : 9,
+ mesh_enable : 1,
+ reserved_1b : 6;
+ uint32_t l2_length : 16,
+ ip_length : 16;
+ uint32_t tcp_seq_number : 32;
+ uint32_t ip_identification : 16,
+ checksum_offset : 13,
+ partial_checksum_en : 1,
+ reserved_4 : 2;
+ uint32_t payload_start_offset : 14,
+ reserved_5a : 2,
+ payload_end_offset : 14,
+ reserved_5b : 2;
+ uint32_t udp_length : 16,
+ reserved_6 : 16;
+#else
+ uint32_t reserved_0a : 5,
+ dummy_msdu_delimitation : 1,
+ tcp_over_ipv6_checksum_en : 1,
+ tcp_over_ipv4_checksum_en : 1,
+ udp_over_ipv6_checksum_en : 1,
+ udp_over_ipv4_checksum_en : 1,
+ ipv4_checksum_en : 1,
+ da_sa_present : 2,
+ epd_en : 1,
+ encap_type : 2,
+ last_msdu : 1,
+ first_msdu : 1,
+ msdu_len : 14;
+ uint32_t reserved_1b : 6,
+ mesh_enable : 1,
+ tcp_flag_mask : 9,
+ tcp_flag : 9,
+ reserved_1a : 6,
+ tso_enable : 1;
+ uint32_t ip_length : 16,
+ l2_length : 16;
+ uint32_t tcp_seq_number : 32;
+ uint32_t reserved_4 : 2,
+ partial_checksum_en : 1,
+ checksum_offset : 13,
+ ip_identification : 16;
+ uint32_t reserved_5b : 2,
+ payload_end_offset : 14,
+ reserved_5a : 2,
+ payload_start_offset : 14;
+ uint32_t reserved_6 : 16,
+ udp_length : 16;
+#endif
+};
+
+#define TX_MSDU_START_MSDU_LEN_OFFSET 0x00000000
+#define TX_MSDU_START_MSDU_LEN_LSB 0
+#define TX_MSDU_START_MSDU_LEN_MSB 13
+#define TX_MSDU_START_MSDU_LEN_MASK 0x00003fff
+
+#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x00000000
+#define TX_MSDU_START_FIRST_MSDU_LSB 14
+#define TX_MSDU_START_FIRST_MSDU_MSB 14
+#define TX_MSDU_START_FIRST_MSDU_MASK 0x00004000
+
+#define TX_MSDU_START_LAST_MSDU_OFFSET 0x00000000
+#define TX_MSDU_START_LAST_MSDU_LSB 15
+#define TX_MSDU_START_LAST_MSDU_MSB 15
+#define TX_MSDU_START_LAST_MSDU_MASK 0x00008000
+
+#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x00000000
+#define TX_MSDU_START_ENCAP_TYPE_LSB 16
+#define TX_MSDU_START_ENCAP_TYPE_MSB 17
+#define TX_MSDU_START_ENCAP_TYPE_MASK 0x00030000
+
+#define TX_MSDU_START_EPD_EN_OFFSET 0x00000000
+#define TX_MSDU_START_EPD_EN_LSB 18
+#define TX_MSDU_START_EPD_EN_MSB 18
+#define TX_MSDU_START_EPD_EN_MASK 0x00040000
+
+#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x00000000
+#define TX_MSDU_START_DA_SA_PRESENT_LSB 19
+#define TX_MSDU_START_DA_SA_PRESENT_MSB 20
+#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x00180000
+
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x00000000
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21
+#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x00200000
+
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22
+#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00400000
+
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23
+#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00800000
+
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24
+#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x01000000
+
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25
+#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x02000000
+
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x00000000
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26
+#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x04000000
+
+#define TX_MSDU_START_RESERVED_0A_OFFSET 0x00000000
+#define TX_MSDU_START_RESERVED_0A_LSB 27
+#define TX_MSDU_START_RESERVED_0A_MSB 31
+#define TX_MSDU_START_RESERVED_0A_MASK 0xf8000000
+
+#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x00000004
+#define TX_MSDU_START_TSO_ENABLE_LSB 0
+#define TX_MSDU_START_TSO_ENABLE_MSB 0
+#define TX_MSDU_START_TSO_ENABLE_MASK 0x00000001
+
+#define TX_MSDU_START_RESERVED_1A_OFFSET 0x00000004
+#define TX_MSDU_START_RESERVED_1A_LSB 1
+#define TX_MSDU_START_RESERVED_1A_MSB 6
+#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e
+
+#define TX_MSDU_START_TCP_FLAG_OFFSET 0x00000004
+#define TX_MSDU_START_TCP_FLAG_LSB 7
+#define TX_MSDU_START_TCP_FLAG_MSB 15
+#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff80
+
+#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x00000004
+#define TX_MSDU_START_TCP_FLAG_MASK_LSB 16
+#define TX_MSDU_START_TCP_FLAG_MASK_MSB 24
+#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff0000
+
+#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x00000004
+#define TX_MSDU_START_MESH_ENABLE_LSB 25
+#define TX_MSDU_START_MESH_ENABLE_MSB 25
+#define TX_MSDU_START_MESH_ENABLE_MASK 0x02000000
+
+#define TX_MSDU_START_RESERVED_1B_OFFSET 0x00000004
+#define TX_MSDU_START_RESERVED_1B_LSB 26
+#define TX_MSDU_START_RESERVED_1B_MSB 31
+#define TX_MSDU_START_RESERVED_1B_MASK 0xfc000000
+
+#define TX_MSDU_START_L2_LENGTH_OFFSET 0x00000008
+#define TX_MSDU_START_L2_LENGTH_LSB 0
+#define TX_MSDU_START_L2_LENGTH_MSB 15
+#define TX_MSDU_START_L2_LENGTH_MASK 0x0000ffff
+
+#define TX_MSDU_START_IP_LENGTH_OFFSET 0x00000008
+#define TX_MSDU_START_IP_LENGTH_LSB 16
+#define TX_MSDU_START_IP_LENGTH_MSB 31
+#define TX_MSDU_START_IP_LENGTH_MASK 0xffff0000
+
+#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000c
+#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 0
+#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 31
+#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff
+
+#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x00000010
+#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0
+#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15
+#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x0000ffff
+
+#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x00000010
+#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16
+#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28
+#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x1fff0000
+
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29
+#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x20000000
+
+#define TX_MSDU_START_RESERVED_4_OFFSET 0x00000010
+#define TX_MSDU_START_RESERVED_4_LSB 30
+#define TX_MSDU_START_RESERVED_4_MSB 31
+#define TX_MSDU_START_RESERVED_4_MASK 0xc0000000
+
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x00000014
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 0
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 13
+#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff
+
+#define TX_MSDU_START_RESERVED_5A_OFFSET 0x00000014
+#define TX_MSDU_START_RESERVED_5A_LSB 14
+#define TX_MSDU_START_RESERVED_5A_MSB 15
+#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c000
+
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x00000014
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 16
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 29
+#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff0000
+
+#define TX_MSDU_START_RESERVED_5B_OFFSET 0x00000014
+#define TX_MSDU_START_RESERVED_5B_LSB 30
+#define TX_MSDU_START_RESERVED_5B_MSB 31
+#define TX_MSDU_START_RESERVED_5B_MASK 0xc0000000
+
+#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x00000018
+#define TX_MSDU_START_UDP_LENGTH_LSB 0
+#define TX_MSDU_START_UDP_LENGTH_MSB 15
+#define TX_MSDU_START_UDP_LENGTH_MASK 0x0000ffff
+
+#define TX_MSDU_START_RESERVED_6_OFFSET 0x00000018
+#define TX_MSDU_START_RESERVED_6_LSB 16
+#define TX_MSDU_START_RESERVED_6_MSB 31
+#define TX_MSDU_START_RESERVED_6_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_peer_entry.h b/drivers/staging/fw-api/hw/peach/v1/tx_peer_entry.h
new file mode 100644
index 0000000000000000000000000000000000000000..4011563b7f7b0bf3300368b48b804a5b9a448079
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_peer_entry.h
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_PEER_ENTRY_H_
+#define _TX_PEER_ENTRY_H_
+
+#define NUM_OF_DWORDS_TX_PEER_ENTRY 18
+
+struct tx_peer_entry {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t mac_addr_a_31_0 : 32;
+ uint32_t mac_addr_a_47_32 : 16,
+ mac_addr_b_15_0 : 16;
+ uint32_t mac_addr_b_47_16 : 32;
+ uint32_t use_ad_b : 1,
+ strip_insert_vlan_inner : 1,
+ strip_insert_vlan_outer : 1,
+ vlan_llc_mode : 1,
+ key_type : 4,
+ a_msdu_wds_ad3_ad4 : 3,
+ ignore_hard_filters : 1,
+ ignore_soft_filters : 1,
+ epd_output : 1,
+ wds : 1,
+ insert_or_strip : 1,
+ sw_filter_id : 16;
+ uint32_t temporal_key_31_0 : 32;
+ uint32_t temporal_key_63_32 : 32;
+ uint32_t temporal_key_95_64 : 32;
+ uint32_t temporal_key_127_96 : 32;
+ uint32_t temporal_key_159_128 : 32;
+ uint32_t temporal_key_191_160 : 32;
+ uint32_t temporal_key_223_192 : 32;
+ uint32_t temporal_key_255_224 : 32;
+ uint32_t sta_partial_aid : 11,
+ transmit_vif : 4,
+ block_this_user : 1,
+ mesh_amsdu_mode : 2,
+ use_qos_alt_mute_mask : 1,
+ dl_ul_direction : 1,
+ reserved_12 : 12;
+ uint32_t insert_vlan_outer_tci : 16,
+ insert_vlan_inner_tci : 16;
+ uint32_t __reserved_g_0007 : 32;
+ uint32_t __reserved_g_0008 : 16,
+ __reserved_g_0009 : 16;
+ uint32_t __reserved_g_0010 : 32;
+ uint32_t multi_link_addr_crypto_enable : 1,
+ reserved_17a : 15,
+ sw_peer_id : 16;
+#else
+ uint32_t mac_addr_a_31_0 : 32;
+ uint32_t mac_addr_b_15_0 : 16,
+ mac_addr_a_47_32 : 16;
+ uint32_t mac_addr_b_47_16 : 32;
+ uint32_t sw_filter_id : 16,
+ insert_or_strip : 1,
+ wds : 1,
+ epd_output : 1,
+ ignore_soft_filters : 1,
+ ignore_hard_filters : 1,
+ a_msdu_wds_ad3_ad4 : 3,
+ key_type : 4,
+ vlan_llc_mode : 1,
+ strip_insert_vlan_outer : 1,
+ strip_insert_vlan_inner : 1,
+ use_ad_b : 1;
+ uint32_t temporal_key_31_0 : 32;
+ uint32_t temporal_key_63_32 : 32;
+ uint32_t temporal_key_95_64 : 32;
+ uint32_t temporal_key_127_96 : 32;
+ uint32_t temporal_key_159_128 : 32;
+ uint32_t temporal_key_191_160 : 32;
+ uint32_t temporal_key_223_192 : 32;
+ uint32_t temporal_key_255_224 : 32;
+ uint32_t reserved_12 : 12,
+ dl_ul_direction : 1,
+ use_qos_alt_mute_mask : 1,
+ mesh_amsdu_mode : 2,
+ block_this_user : 1,
+ transmit_vif : 4,
+ sta_partial_aid : 11;
+ uint32_t insert_vlan_inner_tci : 16,
+ insert_vlan_outer_tci : 16;
+ uint32_t __reserved_g_0007 : 32;
+ uint32_t __reserved_g_0009 : 16,
+ __reserved_g_0008 : 16;
+ uint32_t __reserved_g_0010 : 32;
+ uint32_t sw_peer_id : 16,
+ reserved_17a : 15,
+ multi_link_addr_crypto_enable : 1;
+#endif
+};
+
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x00000000
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31
+#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0xffffffff
+
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x00000004
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 0
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 15
+#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff
+
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x00000004
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 16
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 31
+#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff0000
+
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x00000008
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31
+#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0xffffffff
+
+#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000c
+#define TX_PEER_ENTRY_USE_AD_B_LSB 0
+#define TX_PEER_ENTRY_USE_AD_B_MSB 0
+#define TX_PEER_ENTRY_USE_AD_B_MASK 0x00000001
+
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000c
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 1
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 1
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x00000002
+
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000c
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 2
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 2
+#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x00000004
+
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000c
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 3
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 3
+#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x00000008
+
+#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000c
+#define TX_PEER_ENTRY_KEY_TYPE_LSB 4
+#define TX_PEER_ENTRY_KEY_TYPE_MSB 7
+#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f0
+
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000c
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 8
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 10
+#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x00000700
+
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000c
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 11
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 11
+#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x00000800
+
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000c
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 12
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 12
+#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x00001000
+
+#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000c
+#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 13
+#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 13
+#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x00002000
+
+#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000c
+#define TX_PEER_ENTRY_WDS_LSB 14
+#define TX_PEER_ENTRY_WDS_MSB 14
+#define TX_PEER_ENTRY_WDS_MASK 0x00004000
+
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000c
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 15
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 15
+#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x00008000
+
+#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000c
+#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 16
+#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 31
+#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff0000
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x00000010
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0xffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x00000014
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x00000018
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0xffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000001c
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x00000020
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0xffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x00000024
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x00000028
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0xffffffff
+
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000002c
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 0
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 31
+#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff
+
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x00000030
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10
+#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x000007ff
+
+#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x00000030
+#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11
+#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14
+#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x00007800
+
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x00000030
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15
+#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x00008000
+
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x00000030
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17
+#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x00030000
+
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x00000030
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18
+#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x00040000
+
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x00000030
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19
+#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x00080000
+
+#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x00000030
+#define TX_PEER_ENTRY_RESERVED_12_LSB 20
+#define TX_PEER_ENTRY_RESERVED_12_MSB 31
+#define TX_PEER_ENTRY_RESERVED_12_MASK 0xfff00000
+
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x00000034
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 0
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 15
+#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff
+
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x00000034
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 16
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 31
+#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff0000
+
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x00000044
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 0
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 0
+#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x00000001
+
+#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x00000044
+#define TX_PEER_ENTRY_RESERVED_17A_LSB 1
+#define TX_PEER_ENTRY_RESERVED_17A_MSB 15
+#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe
+
+#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x00000044
+#define TX_PEER_ENTRY_SW_PEER_ID_LSB 16
+#define TX_PEER_ENTRY_SW_PEER_ID_MSB 31
+#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_queue_extension.h b/drivers/staging/fw-api/hw/peach/v1/tx_queue_extension.h
new file mode 100644
index 0000000000000000000000000000000000000000..7b0d123d544bbd6f8e7b86f80e7b7ceed528b8be
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_queue_extension.h
@@ -0,0 +1,316 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_QUEUE_EXTENSION_H_
+#define _TX_QUEUE_EXTENSION_H_
+
+#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14
+
+struct tx_queue_extension {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t frame_ctl : 16,
+ qos_ctl : 16;
+ uint32_t ampdu_flag : 1,
+ tx_notify_no_htc_override : 1,
+ reserved_1a : 7,
+ checksum_tso_disable_for_frag : 1,
+ key_id : 8,
+ qos_buf_state_overwrite : 1,
+ buf_state_sta_id : 1,
+ buf_state_source : 1,
+ ht_control_overwrite_enable : 1,
+ ht_control_overwrite_source : 4,
+ reserved_1b : 6;
+ uint32_t ul_headroom_insertion_enable : 1,
+ ul_headroom_offset : 5,
+ bqrp_insertion_enable : 1,
+ bqrp_offset : 5,
+ ul_headroom_rsvd_7_6 : 2,
+ bqr_rsvd_9_8 : 2,
+ base_pn_63_48 : 16;
+ uint32_t base_pn_95_64 : 32;
+ uint32_t base_pn_127_96 : 32;
+ uint32_t ht_control_field_bw20 : 32;
+ uint32_t ht_control_field_bw40 : 32;
+ uint32_t ht_control_field_bw80 : 32;
+ uint32_t ht_control_field_bw160 : 32;
+ uint32_t ht_control_overwrite_mask : 32;
+ uint32_t cas_control_info : 8,
+ cas_offset : 5,
+ cas_insertion_enable : 1,
+ reserved_10a : 2,
+ ht_control_overwrite_source_for_srp : 4,
+ ht_control_overwrite_source_for_bsrp : 4,
+ reserved_10b : 6,
+ mpdu_hdr_len_override_en : 1,
+ bar_ssn_overwrite_enable : 1;
+ uint32_t bar_ssn_offset : 12,
+ mpdu_hdr_len_override_val : 9,
+ reserved_11a : 11;
+ uint32_t ht_control_field_bw320 : 32;
+ uint32_t fw2sw_info : 32;
+#else
+ uint32_t qos_ctl : 16,
+ frame_ctl : 16;
+ uint32_t reserved_1b : 6,
+ ht_control_overwrite_source : 4,
+ ht_control_overwrite_enable : 1,
+ buf_state_source : 1,
+ buf_state_sta_id : 1,
+ qos_buf_state_overwrite : 1,
+ key_id : 8,
+ checksum_tso_disable_for_frag : 1,
+ reserved_1a : 7,
+ tx_notify_no_htc_override : 1,
+ ampdu_flag : 1;
+ uint32_t base_pn_63_48 : 16,
+ bqr_rsvd_9_8 : 2,
+ ul_headroom_rsvd_7_6 : 2,
+ bqrp_offset : 5,
+ bqrp_insertion_enable : 1,
+ ul_headroom_offset : 5,
+ ul_headroom_insertion_enable : 1;
+ uint32_t base_pn_95_64 : 32;
+ uint32_t base_pn_127_96 : 32;
+ uint32_t ht_control_field_bw20 : 32;
+ uint32_t ht_control_field_bw40 : 32;
+ uint32_t ht_control_field_bw80 : 32;
+ uint32_t ht_control_field_bw160 : 32;
+ uint32_t ht_control_overwrite_mask : 32;
+ uint32_t bar_ssn_overwrite_enable : 1,
+ mpdu_hdr_len_override_en : 1,
+ reserved_10b : 6,
+ ht_control_overwrite_source_for_bsrp : 4,
+ ht_control_overwrite_source_for_srp : 4,
+ reserved_10a : 2,
+ cas_insertion_enable : 1,
+ cas_offset : 5,
+ cas_control_info : 8;
+ uint32_t reserved_11a : 11,
+ mpdu_hdr_len_override_val : 9,
+ bar_ssn_offset : 12;
+ uint32_t ht_control_field_bw320 : 32;
+ uint32_t fw2sw_info : 32;
+#endif
+};
+
+#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x00000000
+#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0
+#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15
+#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x0000ffff
+
+#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x00000000
+#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16
+#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31
+#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0xffff0000
+
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x00000004
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 0
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 0
+#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x00000001
+
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x00000004
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 1
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 1
+#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x00000002
+
+#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x00000004
+#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 2
+#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 8
+#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc
+
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x00000004
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 9
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 9
+#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x00000200
+
+#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x00000004
+#define TX_QUEUE_EXTENSION_KEY_ID_LSB 10
+#define TX_QUEUE_EXTENSION_KEY_ID_MSB 17
+#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc00
+
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x00000004
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 18
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 18
+#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x00040000
+
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x00000004
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 19
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 19
+#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x00080000
+
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x00000004
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 20
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 20
+#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x00100000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x00000004
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 21
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 21
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x00200000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x00000004
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 22
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 25
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c00000
+
+#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x00000004
+#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 26
+#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 31
+#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc000000
+
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x00000008
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x00000001
+
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x00000008
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x0000003e
+
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x00000008
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6
+#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x00000040
+
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x00000008
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11
+#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x00000f80
+
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x00000008
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13
+#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x00003000
+
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x00000008
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15
+#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x0000c000
+
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x00000008
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31
+#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0xffff0000
+
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000c
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 0
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 31
+#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff
+
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x00000010
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31
+#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0xffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x00000014
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x00000018
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0xffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000001c
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x00000020
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0xffffffff
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x00000024
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff
+
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x00000028
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7
+#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x000000ff
+
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x00000028
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12
+#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x00001f00
+
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x00000028
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13
+#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x00002000
+
+#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x00000028
+#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14
+#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15
+#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x0000c000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x00000028
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x000f0000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x00000028
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23
+#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x00f00000
+
+#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x00000028
+#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24
+#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29
+#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x3f000000
+
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x00000028
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x40000000
+
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x00000028
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31
+#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x80000000
+
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000002c
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 0
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 11
+#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff
+
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000002c
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 12
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 20
+#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff000
+
+#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000002c
+#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 21
+#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 31
+#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe00000
+
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x00000030
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31
+#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0xffffffff
+
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x00000034
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 0
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 31
+#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_rate_stats_info.h b/drivers/staging/fw-api/hw/peach/v1/tx_rate_stats_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..4f311a2d6ea9fc6d85c7c1cb4bf467f192af45d5
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_rate_stats_info.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_RATE_STATS_INFO_H_
+#define _TX_RATE_STATS_INFO_H_
+
+#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2
+
+struct tx_rate_stats_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t tx_rate_stats_info_valid : 1,
+ transmit_bw : 3,
+ transmit_pkt_type : 4,
+ transmit_stbc : 1,
+ transmit_ldpc : 1,
+ transmit_sgi : 2,
+ transmit_mcs : 4,
+ ofdma_transmission : 1,
+ tones_in_ru : 12,
+ transmit_nss : 3;
+ uint32_t ppdu_transmission_tsf : 32;
+#else
+ uint32_t transmit_nss : 3,
+ tones_in_ru : 12,
+ ofdma_transmission : 1,
+ transmit_mcs : 4,
+ transmit_sgi : 2,
+ transmit_ldpc : 1,
+ transmit_stbc : 1,
+ transmit_pkt_type : 4,
+ transmit_bw : 3,
+ tx_rate_stats_info_valid : 1;
+ uint32_t ppdu_transmission_tsf : 32;
+#endif
+};
+
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0
+#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001
+
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3
+#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e
+
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7
+#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0
+
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8
+#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100
+
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9
+#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200
+
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11
+#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00
+
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 15
+#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0000f000
+
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 16
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 16
+#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00010000
+
+#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 17
+#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28
+#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1ffe0000
+
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB 29
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB 31
+#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK 0xe0000000
+
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31
+#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/tx_raw_or_native_frame_setup.h b/drivers/staging/fw-api/hw/peach/v1/tx_raw_or_native_frame_setup.h
new file mode 100644
index 0000000000000000000000000000000000000000..468ff4919f5a6cc6f985281a08f335ac050900c1
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/tx_raw_or_native_frame_setup.h
@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_
+#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_
+
+#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2
+
+struct tx_raw_or_native_frame_setup {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t fc_to_ds_mask : 1,
+ fc_from_ds_mask : 1,
+ fc_more_frag_mask : 1,
+ fc_retry_mask : 1,
+ fc_pwr_mgt_mask : 1,
+ fc_more_data_mask : 1,
+ fc_prot_frame_mask : 1,
+ fc_order_mask : 1,
+ duration_field_mask : 1,
+ sequence_control_mask : 1,
+ qc_tid_mask : 1,
+ qc_eosp_mask : 1,
+ qc_ack_policy_mask : 1,
+ qc_amsdu_mask : 1,
+ reserved_0a : 1,
+ qc_15to8_mask : 1,
+ iv_mask : 1,
+ fc_to_ds_setting : 1,
+ fc_from_ds_setting : 1,
+ fc_more_frag_setting : 1,
+ fc_retry_setting : 2,
+ fc_pwr_mgt_setting : 1,
+ fc_more_data_setting : 2,
+ fc_prot_frame_setting : 2,
+ fc_order_setting : 1,
+ qc_tid_setting : 4;
+ uint32_t qc_eosp_setting : 2,
+ qc_ack_policy_setting : 2,
+ qc_amsdu_setting : 1,
+ qc_15to8_setting : 8,
+ mlo_addr_override : 1,
+ mlo_ignore_addr3_override : 1,
+ sequence_control_source : 1,
+ fragment_number : 4,
+ sequence_number : 12;
+#else
+ uint32_t qc_tid_setting : 4,
+ fc_order_setting : 1,
+ fc_prot_frame_setting : 2,
+ fc_more_data_setting : 2,
+ fc_pwr_mgt_setting : 1,
+ fc_retry_setting : 2,
+ fc_more_frag_setting : 1,
+ fc_from_ds_setting : 1,
+ fc_to_ds_setting : 1,
+ iv_mask : 1,
+ qc_15to8_mask : 1,
+ reserved_0a : 1,
+ qc_amsdu_mask : 1,
+ qc_ack_policy_mask : 1,
+ qc_eosp_mask : 1,
+ qc_tid_mask : 1,
+ sequence_control_mask : 1,
+ duration_field_mask : 1,
+ fc_order_mask : 1,
+ fc_prot_frame_mask : 1,
+ fc_more_data_mask : 1,
+ fc_pwr_mgt_mask : 1,
+ fc_retry_mask : 1,
+ fc_more_frag_mask : 1,
+ fc_from_ds_mask : 1,
+ fc_to_ds_mask : 1;
+ uint32_t sequence_number : 12,
+ fragment_number : 4,
+ sequence_control_source : 1,
+ mlo_ignore_addr3_override : 1,
+ mlo_addr_override : 1,
+ qc_15to8_setting : 8,
+ qc_amsdu_setting : 1,
+ qc_ack_policy_setting : 2,
+ qc_eosp_setting : 2;
+#endif
+};
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x00000001
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x00000002
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x00000004
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x00000008
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x00000010
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x00000020
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x00000040
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x00000080
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x00000100
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x00000200
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x00000400
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x00000800
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x00001000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x00002000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x00004000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x00008000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x00010000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x00020000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x00040000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x00080000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x00300000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x00400000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x01800000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x06000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x08000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x00000000
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0xf0000000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 0
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 1
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x00000003
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 2
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 3
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 4
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 4
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x00000010
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 5
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 12
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe0
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 13
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 13
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x00002000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 14
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 14
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x00004000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 15
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 15
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x00008000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 16
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 19
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f0000
+
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x00000004
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 20
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 31
+#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff00000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/txpcu_buffer_basics.h b/drivers/staging/fw-api/hw/peach/v1/txpcu_buffer_basics.h
new file mode 100644
index 0000000000000000000000000000000000000000..236c1b83af92cbba62b3ba5156e2ccf973e68754
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/txpcu_buffer_basics.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TXPCU_BUFFER_BASICS_H_
+#define _TXPCU_BUFFER_BASICS_H_
+
+#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1
+
+struct txpcu_buffer_basics {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t available_memory : 8,
+ partial_tx_data_tlv_count : 8,
+ tx_data_tlv_count : 16;
+#else
+ uint32_t tx_data_tlv_count : 16,
+ partial_tx_data_tlv_count : 8,
+ available_memory : 8;
+#endif
+};
+
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7
+#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff
+
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15
+#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00
+
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31
+#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/txpcu_buffer_status.h b/drivers/staging/fw-api/hw/peach/v1/txpcu_buffer_status.h
new file mode 100644
index 0000000000000000000000000000000000000000..f9d49adf23a235a5949accea441744bbc96eb1fc
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/txpcu_buffer_status.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TXPCU_BUFFER_STATUS_H_
+#define _TXPCU_BUFFER_STATUS_H_
+
+#include "txpcu_buffer_basics.h"
+#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2
+
+struct txpcu_buffer_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct txpcu_buffer_basics txpcu_basix_buffer_info;
+ uint32_t reserved : 15,
+ msdu_end : 1,
+ tx_data_sync_value : 16;
+#else
+ struct txpcu_buffer_basics txpcu_basix_buffer_info;
+ uint32_t tx_data_sync_value : 16,
+ msdu_end : 1,
+ reserved : 15;
+#endif
+};
+
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x00000000
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x000000ff
+
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00
+
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x00000000
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31
+#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0xffff0000
+
+#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x00000004
+#define TXPCU_BUFFER_STATUS_RESERVED_LSB 0
+#define TXPCU_BUFFER_STATUS_RESERVED_MSB 14
+#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff
+
+#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x00000004
+#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 15
+#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 15
+#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x00008000
+
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x00000004
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 16
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 31
+#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/txpcu_user_buffer_status.h b/drivers/staging/fw-api/hw/peach/v1/txpcu_user_buffer_status.h
new file mode 100644
index 0000000000000000000000000000000000000000..f6d6f049fcc5a89e08eb338897848aa39b2526e4
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/txpcu_user_buffer_status.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _TXPCU_USER_BUFFER_STATUS_H_
+#define _TXPCU_USER_BUFFER_STATUS_H_
+
+#include "txpcu_buffer_basics.h"
+#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2
+
+struct txpcu_user_buffer_status {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct txpcu_buffer_basics txpcu_basic_buffer_info;
+ uint32_t stored_word_count_user : 14,
+ reserved_1a : 1,
+ msdu_end : 1,
+ tx_data_sync_value : 16;
+#else
+ struct txpcu_buffer_basics txpcu_basic_buffer_info;
+ uint32_t tx_data_sync_value : 16,
+ msdu_end : 1,
+ reserved_1a : 1,
+ stored_word_count_user : 14;
+#endif
+};
+
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x00000000
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x000000ff
+
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00
+
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x00000000
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31
+#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0xffff0000
+
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x00000004
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 0
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 13
+#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff
+
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x00000004
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 14
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 14
+#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x00004000
+
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x00000004
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 15
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 15
+#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x00008000
+
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x00000004
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 16
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 31
+#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/u_sig_eht_su_mu_info.h b/drivers/staging/fw-api/hw/peach/v1/u_sig_eht_su_mu_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..9e2f1616e31fd7c9e4dcb6c2d80aef0c3a95ae61
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/u_sig_eht_su_mu_info.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _U_SIG_EHT_SU_MU_INFO_H_
+#define _U_SIG_EHT_SU_MU_INFO_H_
+
+#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2
+
+struct u_sig_eht_su_mu_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t phy_version : 3,
+ transmit_bw : 3,
+ dl_ul_flag : 1,
+ bss_color_id : 6,
+ txop_duration : 7,
+ disregard_0a : 5,
+ validate_0b : 1,
+ reserved_0c : 6;
+ uint32_t eht_ppdu_sig_cmn_type : 2,
+ validate_1a : 1,
+ punctured_channel_information : 5,
+ validate_1b : 1,
+ mcs_of_eht_sig : 2,
+ num_eht_sig_symbols : 5,
+ crc : 4,
+ tail : 6,
+ dot11ax_su_extended : 1,
+ reserved_1d : 3,
+ rx_ndp : 1,
+ rx_integrity_check_passed : 1;
+#else
+ uint32_t reserved_0c : 6,
+ validate_0b : 1,
+ disregard_0a : 5,
+ txop_duration : 7,
+ bss_color_id : 6,
+ dl_ul_flag : 1,
+ transmit_bw : 3,
+ phy_version : 3;
+ uint32_t rx_integrity_check_passed : 1,
+ rx_ndp : 1,
+ reserved_1d : 3,
+ dot11ax_su_extended : 1,
+ tail : 6,
+ crc : 4,
+ num_eht_sig_symbols : 5,
+ mcs_of_eht_sig : 2,
+ validate_1b : 1,
+ punctured_channel_information : 5,
+ validate_1a : 1,
+ eht_ppdu_sig_cmn_type : 2;
+#endif
+};
+
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2
+#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007
+
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5
+#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038
+
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6
+#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040
+
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12
+#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80
+
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19
+#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000
+
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24
+#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000
+
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000
+
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1
+#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004
+
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7
+#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8
+
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8
+#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100
+
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10
+#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600
+
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15
+#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800
+
+#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004
+#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16
+#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19
+#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000
+
+#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004
+#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20
+#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25
+#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000
+
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26
+#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000
+
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29
+#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000
+
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30
+#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000
+
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/u_sig_eht_tb_info.h b/drivers/staging/fw-api/hw/peach/v1/u_sig_eht_tb_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..1240c159f708d2a1f5500820483a5c4b760f48f4
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/u_sig_eht_tb_info.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _U_SIG_EHT_TB_INFO_H_
+#define _U_SIG_EHT_TB_INFO_H_
+
+#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2
+
+struct u_sig_eht_tb_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t phy_version : 3,
+ transmit_bw : 3,
+ dl_ul_flag : 1,
+ bss_color_id : 6,
+ txop_duration : 7,
+ disregard_0a : 6,
+ reserved_0c : 6;
+ uint32_t eht_ppdu_sig_cmn_type : 2,
+ validate_1a : 1,
+ spatial_reuse : 8,
+ disregard_1b : 5,
+ crc : 4,
+ tail : 6,
+ reserved_1c : 5,
+ rx_integrity_check_passed : 1;
+#else
+ uint32_t reserved_0c : 6,
+ disregard_0a : 6,
+ txop_duration : 7,
+ bss_color_id : 6,
+ dl_ul_flag : 1,
+ transmit_bw : 3,
+ phy_version : 3;
+ uint32_t rx_integrity_check_passed : 1,
+ reserved_1c : 5,
+ tail : 6,
+ crc : 4,
+ disregard_1b : 5,
+ spatial_reuse : 8,
+ validate_1a : 1,
+ eht_ppdu_sig_cmn_type : 2;
+#endif
+};
+
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2
+#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007
+
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5
+#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038
+
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6
+#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040
+
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12
+#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80
+
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19
+#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000
+
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25
+#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000
+
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31
+#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000
+
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1
+#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003
+
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2
+#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004
+
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10
+#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8
+
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15
+#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800
+
+#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004
+#define U_SIG_EHT_TB_INFO_CRC_LSB 16
+#define U_SIG_EHT_TB_INFO_CRC_MSB 19
+#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000
+
+#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004
+#define U_SIG_EHT_TB_INFO_TAIL_LSB 20
+#define U_SIG_EHT_TB_INFO_TAIL_MSB 25
+#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000
+
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30
+#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000
+
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/unallocated_ru_160_info.h b/drivers/staging/fw-api/hw/peach/v1/unallocated_ru_160_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..da3c52bfc2170fa110cc7dd02fc866e2e35ed2aa
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/unallocated_ru_160_info.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _UNALLOCATED_RU_160_INFO_H_
+#define _UNALLOCATED_RU_160_INFO_H_
+
+#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1
+
+struct unallocated_ru_160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t subband80_0_cc0 : 8,
+ subband80_0_cc1 : 8,
+ subband80_1_cc0 : 8,
+ subband80_1_cc1 : 8;
+#else
+ uint32_t subband80_1_cc1 : 8,
+ subband80_1_cc0 : 8,
+ subband80_0_cc1 : 8,
+ subband80_0_cc0 : 8;
+#endif
+};
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000
+
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31
+#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/uniform_descriptor_header.h b/drivers/staging/fw-api/hw/peach/v1/uniform_descriptor_header.h
new file mode 100644
index 0000000000000000000000000000000000000000..efe58926b91fcb6716bb43103f6d42e44f2eb12c
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/uniform_descriptor_header.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
+#define _UNIFORM_DESCRIPTOR_HEADER_H_
+
+#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1
+
+struct uniform_descriptor_header {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t owner : 4,
+ buffer_type : 4,
+ tx_mpdu_queue_number : 20,
+ reserved_0a : 4;
+#else
+ uint32_t reserved_0a : 4,
+ tx_mpdu_queue_number : 20,
+ buffer_type : 4,
+ owner : 4;
+#endif
+};
+
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3
+#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
+
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7
+#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
+
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27
+#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00
+
+/* RESERVED is overlapping with TX_MPDU_QUEUE_NUMBER
+ * TX_MPDU_QUEUE_NUMBER valid on in Buffer_type is any of Transmit_MPDU_*_descriptor
+ * Where as RESERVED is only used for debugging in REO_QUEUE_Descr reo_queue_desc
+ */
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31
+#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/uniform_reo_cmd_header.h b/drivers/staging/fw-api/hw/peach/v1/uniform_reo_cmd_header.h
new file mode 100644
index 0000000000000000000000000000000000000000..e9139b54e9b23cb627090e4b350070a3264f39ee
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/uniform_reo_cmd_header.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _UNIFORM_REO_CMD_HEADER_H_
+#define _UNIFORM_REO_CMD_HEADER_H_
+
+#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1
+
+struct uniform_reo_cmd_header {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t reo_cmd_number : 16,
+ reo_status_required : 1,
+ reserved_0a : 15;
+#else
+ uint32_t reserved_0a : 15,
+ reo_status_required : 1,
+ reo_cmd_number : 16;
+#endif
+};
+
+#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MSB 15
+#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16
+#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_LSB 17
+#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MSB 31
+#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/uniform_reo_status_header.h b/drivers/staging/fw-api/hw/peach/v1/uniform_reo_status_header.h
new file mode 100644
index 0000000000000000000000000000000000000000..988ba6e05ec05884d544bbd8a9eb28f236ed86b4
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/uniform_reo_status_header.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _UNIFORM_REO_STATUS_HEADER_H_
+#define _UNIFORM_REO_STATUS_HEADER_H_
+
+#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2
+
+struct uniform_reo_status_header {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t reo_status_number : 16,
+ cmd_execution_time : 10,
+ reo_cmd_execution_status : 2,
+ reserved_0a : 4;
+ uint32_t timestamp : 32;
+#else
+ uint32_t reserved_0a : 4,
+ reo_cmd_execution_status : 2,
+ cmd_execution_time : 10,
+ reo_status_number : 16;
+ uint32_t timestamp : 32;
+#endif
+};
+
+#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15
+#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25
+#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27
+#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_LSB 28
+#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MSB 31
+#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_LSB 0
+#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MSB 31
+#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_a_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_a_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..6b20f8f904f831655dd77c975f6c2236b7bc4233
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_a_info.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_A_INFO_H_
+#define _VHT_SIG_A_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2
+
+struct vht_sig_a_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t bandwidth : 2,
+ vhta_reserved_0 : 1,
+ stbc : 1,
+ group_id : 6,
+ n_sts : 12,
+ txop_ps_not_allowed : 1,
+ vhta_reserved_0b : 1,
+ reserved_0 : 8;
+ uint32_t gi_setting : 2,
+ su_mu_coding : 1,
+ ldpc_extra_symbol : 1,
+ mcs : 4,
+ beamformed : 1,
+ vhta_reserved_1 : 1,
+ crc : 8,
+ tail : 6,
+ reserved_1 : 7,
+ rx_integrity_check_passed : 1;
+#else
+ uint32_t reserved_0 : 8,
+ vhta_reserved_0b : 1,
+ txop_ps_not_allowed : 1,
+ n_sts : 12,
+ group_id : 6,
+ stbc : 1,
+ vhta_reserved_0 : 1,
+ bandwidth : 2;
+ uint32_t rx_integrity_check_passed : 1,
+ reserved_1 : 7,
+ tail : 6,
+ crc : 8,
+ vhta_reserved_1 : 1,
+ beamformed : 1,
+ mcs : 4,
+ ldpc_extra_symbol : 1,
+ su_mu_coding : 1,
+ gi_setting : 2;
+#endif
+};
+
+#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_BANDWIDTH_LSB 0
+#define VHT_SIG_A_INFO_BANDWIDTH_MSB 1
+#define VHT_SIG_A_INFO_BANDWIDTH_MASK 0x00000003
+
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB 2
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB 2
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK 0x00000004
+
+#define VHT_SIG_A_INFO_STBC_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_STBC_LSB 3
+#define VHT_SIG_A_INFO_STBC_MSB 3
+#define VHT_SIG_A_INFO_STBC_MASK 0x00000008
+
+#define VHT_SIG_A_INFO_GROUP_ID_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_GROUP_ID_LSB 4
+#define VHT_SIG_A_INFO_GROUP_ID_MSB 9
+#define VHT_SIG_A_INFO_GROUP_ID_MASK 0x000003f0
+
+#define VHT_SIG_A_INFO_N_STS_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_N_STS_LSB 10
+#define VHT_SIG_A_INFO_N_STS_MSB 21
+#define VHT_SIG_A_INFO_N_STS_MASK 0x003ffc00
+
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB 22
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB 22
+#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK 0x00400000
+
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB 23
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB 23
+#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK 0x00800000
+
+#define VHT_SIG_A_INFO_RESERVED_0_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_RESERVED_0_LSB 24
+#define VHT_SIG_A_INFO_RESERVED_0_MSB 31
+#define VHT_SIG_A_INFO_RESERVED_0_MASK 0xff000000
+
+#define VHT_SIG_A_INFO_GI_SETTING_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_GI_SETTING_LSB 0
+#define VHT_SIG_A_INFO_GI_SETTING_MSB 1
+#define VHT_SIG_A_INFO_GI_SETTING_MASK 0x00000003
+
+#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_SU_MU_CODING_LSB 2
+#define VHT_SIG_A_INFO_SU_MU_CODING_MSB 2
+#define VHT_SIG_A_INFO_SU_MU_CODING_MASK 0x00000004
+
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB 3
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB 3
+#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000008
+
+#define VHT_SIG_A_INFO_MCS_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_MCS_LSB 4
+#define VHT_SIG_A_INFO_MCS_MSB 7
+#define VHT_SIG_A_INFO_MCS_MASK 0x000000f0
+
+#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_BEAMFORMED_LSB 8
+#define VHT_SIG_A_INFO_BEAMFORMED_MSB 8
+#define VHT_SIG_A_INFO_BEAMFORMED_MASK 0x00000100
+
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB 9
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB 9
+#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK 0x00000200
+
+#define VHT_SIG_A_INFO_CRC_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_CRC_LSB 10
+#define VHT_SIG_A_INFO_CRC_MSB 17
+#define VHT_SIG_A_INFO_CRC_MASK 0x0003fc00
+
+#define VHT_SIG_A_INFO_TAIL_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_TAIL_LSB 18
+#define VHT_SIG_A_INFO_TAIL_MSB 23
+#define VHT_SIG_A_INFO_TAIL_MASK 0x00fc0000
+
+#define VHT_SIG_A_INFO_RESERVED_1_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_RESERVED_1_LSB 24
+#define VHT_SIG_A_INFO_RESERVED_1_MSB 30
+#define VHT_SIG_A_INFO_RESERVED_1_MASK 0x7f000000
+
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
+#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu160_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu160_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..6709a5e3c87d2a10e48608c664b110389d0b467b
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu160_info.h
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_MU160_INFO_H_
+#define _VHT_SIG_B_MU160_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8
+
+struct vht_sig_b_mu160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t length : 19,
+ mcs : 4,
+ tail : 6,
+ reserved_0 : 3;
+ uint32_t length_copy_a : 19,
+ mcs_copy_a : 4,
+ tail_copy_a : 6,
+ reserved_1 : 3;
+ uint32_t length_copy_b : 19,
+ mcs_copy_b : 4,
+ tail_copy_b : 6,
+ reserved_2 : 3;
+ uint32_t length_copy_c : 19,
+ mcs_copy_c : 4,
+ tail_copy_c : 6,
+ reserved_3 : 3;
+ uint32_t length_copy_d : 19,
+ mcs_copy_d : 4,
+ tail_copy_d : 6,
+ reserved_4 : 3;
+ uint32_t length_copy_e : 19,
+ mcs_copy_e : 4,
+ tail_copy_e : 6,
+ reserved_5 : 3;
+ uint32_t length_copy_f : 19,
+ mcs_copy_f : 4,
+ tail_copy_f : 6,
+ mu_user_number : 3;
+ uint32_t length_copy_g : 19,
+ mcs_copy_g : 4,
+ tail_copy_g : 6,
+ reserved_7 : 3;
+#else
+ uint32_t reserved_0 : 3,
+ tail : 6,
+ mcs : 4,
+ length : 19;
+ uint32_t reserved_1 : 3,
+ tail_copy_a : 6,
+ mcs_copy_a : 4,
+ length_copy_a : 19;
+ uint32_t reserved_2 : 3,
+ tail_copy_b : 6,
+ mcs_copy_b : 4,
+ length_copy_b : 19;
+ uint32_t reserved_3 : 3,
+ tail_copy_c : 6,
+ mcs_copy_c : 4,
+ length_copy_c : 19;
+ uint32_t reserved_4 : 3,
+ tail_copy_d : 6,
+ mcs_copy_d : 4,
+ length_copy_d : 19;
+ uint32_t reserved_5 : 3,
+ tail_copy_e : 6,
+ mcs_copy_e : 4,
+ length_copy_e : 19;
+ uint32_t mu_user_number : 3,
+ tail_copy_f : 6,
+ mcs_copy_f : 4,
+ length_copy_f : 19;
+ uint32_t reserved_7 : 3,
+ tail_copy_g : 6,
+ mcs_copy_g : 4,
+ length_copy_g : 19;
+#endif
+};
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000
+#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0
+#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18
+#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000
+#define VHT_SIG_B_MU160_INFO_MCS_LSB 19
+#define VHT_SIG_B_MU160_INFO_MCS_MSB 22
+#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000
+#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23
+#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28
+#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31
+#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31
+#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31
+#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31
+#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31
+#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31
+#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31
+#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000
+
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18
+#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff
+
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22
+#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000
+
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28
+#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000
+
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31
+#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu20_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu20_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..3af2601c4424cf49959f9d4cba44c363a48e3d16
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu20_info.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_MU20_INFO_H_
+#define _VHT_SIG_B_MU20_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1
+
+struct vht_sig_b_mu20_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t length : 16,
+ mcs : 4,
+ tail : 6,
+ mu_user_number : 3,
+ reserved_0 : 3;
+#else
+ uint32_t reserved_0 : 3,
+ mu_user_number : 3,
+ tail : 6,
+ mcs : 4,
+ length : 16;
+#endif
+};
+
+#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000
+#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0
+#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15
+#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff
+
+#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000
+#define VHT_SIG_B_MU20_INFO_MCS_LSB 16
+#define VHT_SIG_B_MU20_INFO_MCS_MSB 19
+#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000
+
+#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000
+#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20
+#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25
+#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000
+
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28
+#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000
+
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31
+#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu40_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu40_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..565c9bd78fe09ff6389b65afbe3eda9cfac59f20
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu40_info.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_MU40_INFO_H_
+#define _VHT_SIG_B_MU40_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2
+
+struct vht_sig_b_mu40_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t length : 17,
+ mcs : 4,
+ tail : 6,
+ reserved_0 : 2,
+ mu_user_number : 3;
+ uint32_t length_copy : 17,
+ mcs_copy : 4,
+ tail_copy : 6,
+ reserved_1 : 5;
+#else
+ uint32_t mu_user_number : 3,
+ reserved_0 : 2,
+ tail : 6,
+ mcs : 4,
+ length : 17;
+ uint32_t reserved_1 : 5,
+ tail_copy : 6,
+ mcs_copy : 4,
+ length_copy : 17;
+#endif
+};
+
+#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000
+#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0
+#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16
+#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff
+
+#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000
+#define VHT_SIG_B_MU40_INFO_MCS_LSB 17
+#define VHT_SIG_B_MU40_INFO_MCS_MSB 20
+#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000
+
+#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000
+#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21
+#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26
+#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000
+
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28
+#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000
+
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31
+#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000
+
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16
+#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff
+
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20
+#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000
+
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26
+#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000
+
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31
+#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu80_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu80_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..5ede34ec87a45b24ccdf53b115cacc84a43793c8
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_mu80_info.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_MU80_INFO_H_
+#define _VHT_SIG_B_MU80_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4
+
+struct vht_sig_b_mu80_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t length : 19,
+ mcs : 4,
+ tail : 6,
+ reserved_0 : 3;
+ uint32_t length_copy_a : 19,
+ mcs_copy_a : 4,
+ tail_copy_a : 6,
+ reserved_1 : 3;
+ uint32_t length_copy_b : 19,
+ mcs_copy_b : 4,
+ tail_copy_b : 6,
+ mu_user_number : 3;
+ uint32_t length_copy_c : 19,
+ mcs_copy_c : 4,
+ tail_copy_c : 6,
+ reserved_3 : 3;
+#else
+ uint32_t reserved_0 : 3,
+ tail : 6,
+ mcs : 4,
+ length : 19;
+ uint32_t reserved_1 : 3,
+ tail_copy_a : 6,
+ mcs_copy_a : 4,
+ length_copy_a : 19;
+ uint32_t mu_user_number : 3,
+ tail_copy_b : 6,
+ mcs_copy_b : 4,
+ length_copy_b : 19;
+ uint32_t reserved_3 : 3,
+ tail_copy_c : 6,
+ mcs_copy_c : 4,
+ length_copy_c : 19;
+#endif
+};
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000
+#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0
+#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18
+#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000
+#define VHT_SIG_B_MU80_INFO_MCS_LSB 19
+#define VHT_SIG_B_MU80_INFO_MCS_MSB 22
+#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000
+#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23
+#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28
+#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31
+#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31
+#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31
+#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000
+
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18
+#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff
+
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22
+#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000
+
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28
+#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000
+
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31
+#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su160_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su160_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..53e8156dc9377795b30e0983ac353b5650624de7
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su160_info.h
@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_SU160_INFO_H_
+#define _VHT_SIG_B_SU160_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8
+
+struct vht_sig_b_su160_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t length : 21,
+ vhtb_reserved : 2,
+ tail : 6,
+ reserved_0 : 2,
+ rx_ndp : 1;
+ uint32_t length_copy_a : 21,
+ vhtb_reserved_copy_a : 2,
+ tail_copy_a : 6,
+ reserved_1 : 2,
+ rx_ndp_copy_a : 1;
+ uint32_t length_copy_b : 21,
+ vhtb_reserved_copy_b : 2,
+ tail_copy_b : 6,
+ reserved_2 : 2,
+ rx_ndp_copy_b : 1;
+ uint32_t length_copy_c : 21,
+ vhtb_reserved_copy_c : 2,
+ tail_copy_c : 6,
+ reserved_3 : 2,
+ rx_ndp_copy_c : 1;
+ uint32_t length_copy_d : 21,
+ vhtb_reserved_copy_d : 2,
+ tail_copy_d : 6,
+ reserved_4 : 2,
+ rx_ndp_copy_d : 1;
+ uint32_t length_copy_e : 21,
+ vhtb_reserved_copy_e : 2,
+ tail_copy_e : 6,
+ reserved_5 : 2,
+ rx_ndp_copy_e : 1;
+ uint32_t length_copy_f : 21,
+ vhtb_reserved_copy_f : 2,
+ tail_copy_f : 6,
+ reserved_6 : 2,
+ rx_ndp_copy_f : 1;
+ uint32_t length_copy_g : 21,
+ vhtb_reserved_copy_g : 2,
+ tail_copy_g : 6,
+ reserved_7 : 2,
+ rx_ndp_copy_g : 1;
+#else
+ uint32_t rx_ndp : 1,
+ reserved_0 : 2,
+ tail : 6,
+ vhtb_reserved : 2,
+ length : 21;
+ uint32_t rx_ndp_copy_a : 1,
+ reserved_1 : 2,
+ tail_copy_a : 6,
+ vhtb_reserved_copy_a : 2,
+ length_copy_a : 21;
+ uint32_t rx_ndp_copy_b : 1,
+ reserved_2 : 2,
+ tail_copy_b : 6,
+ vhtb_reserved_copy_b : 2,
+ length_copy_b : 21;
+ uint32_t rx_ndp_copy_c : 1,
+ reserved_3 : 2,
+ tail_copy_c : 6,
+ vhtb_reserved_copy_c : 2,
+ length_copy_c : 21;
+ uint32_t rx_ndp_copy_d : 1,
+ reserved_4 : 2,
+ tail_copy_d : 6,
+ vhtb_reserved_copy_d : 2,
+ length_copy_d : 21;
+ uint32_t rx_ndp_copy_e : 1,
+ reserved_5 : 2,
+ tail_copy_e : 6,
+ vhtb_reserved_copy_e : 2,
+ length_copy_e : 21;
+ uint32_t rx_ndp_copy_f : 1,
+ reserved_6 : 2,
+ tail_copy_f : 6,
+ vhtb_reserved_copy_f : 2,
+ length_copy_f : 21;
+ uint32_t rx_ndp_copy_g : 1,
+ reserved_7 : 2,
+ tail_copy_g : 6,
+ vhtb_reserved_copy_g : 2,
+ length_copy_g : 21;
+#endif
+};
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000
+#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0
+#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20
+#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000
+#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23
+#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28
+#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30
+#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000
+#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30
+#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30
+#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30
+#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30
+#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30
+#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30
+#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000
+
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20
+#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff
+
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22
+#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000
+
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28
+#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000
+
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30
+#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000
+
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31
+#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su20_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su20_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..1343f424b763b19ed639d8fe081540a6bfe23a46
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su20_info.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_SU20_INFO_H_
+#define _VHT_SIG_B_SU20_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1
+
+struct vht_sig_b_su20_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t length : 17,
+ vhtb_reserved : 3,
+ tail : 6,
+ reserved : 5,
+ rx_ndp : 1;
+#else
+ uint32_t rx_ndp : 1,
+ reserved : 5,
+ tail : 6,
+ vhtb_reserved : 3,
+ length : 17;
+#endif
+};
+
+#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000
+#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0
+#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16
+#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff
+
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19
+#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000
+
+#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000
+#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20
+#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25
+#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000
+
+#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000
+#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26
+#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30
+#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000
+
+#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000
+#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31
+#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31
+#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su40_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su40_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..1f0049317179977772b94eb4c12c7849a9c9d020
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su40_info.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_SU40_INFO_H_
+#define _VHT_SIG_B_SU40_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2
+
+struct vht_sig_b_su40_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t length : 19,
+ vhtb_reserved : 2,
+ tail : 6,
+ reserved : 4,
+ rx_ndp : 1;
+ uint32_t length_copy : 19,
+ vhtb_reserved_copy : 2,
+ tail_copy : 6,
+ reserved_copy : 4,
+ rx_ndp_copy : 1;
+#else
+ uint32_t rx_ndp : 1,
+ reserved : 4,
+ tail : 6,
+ vhtb_reserved : 2,
+ length : 19;
+ uint32_t rx_ndp_copy : 1,
+ reserved_copy : 4,
+ tail_copy : 6,
+ vhtb_reserved_copy : 2,
+ length_copy : 19;
+#endif
+};
+
+#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000
+#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0
+#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18
+#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff
+
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000
+
+#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000
+#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21
+#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26
+#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000
+
+#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000
+#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27
+#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30
+#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000
+
+#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000
+#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000
+
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18
+#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff
+
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20
+#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000
+
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26
+#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000
+
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30
+#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000
+
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31
+#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su80_info.h b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su80_info.h
new file mode 100644
index 0000000000000000000000000000000000000000..ac47150f808834207476cfd3622563fe550536d7
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/vht_sig_b_su80_info.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _VHT_SIG_B_SU80_INFO_H_
+#define _VHT_SIG_B_SU80_INFO_H_
+
+#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4
+
+struct vht_sig_b_su80_info {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t length : 21,
+ vhtb_reserved : 2,
+ tail : 6,
+ reserved_0 : 2,
+ rx_ndp : 1;
+ uint32_t length_copy_a : 21,
+ vhtb_reserved_copy_a : 2,
+ tail_copy_a : 6,
+ reserved_1 : 2,
+ rx_ndp_copy_a : 1;
+ uint32_t length_copy_b : 21,
+ vhtb_reserved_copy_b : 2,
+ tail_copy_b : 6,
+ reserved_2 : 2,
+ rx_ndp_copy_b : 1;
+ uint32_t length_copy_c : 21,
+ vhtb_reserved_copy_c : 2,
+ tail_copy_c : 6,
+ reserved_3 : 2,
+ rx_ndp_copy_c : 1;
+#else
+ uint32_t rx_ndp : 1,
+ reserved_0 : 2,
+ tail : 6,
+ vhtb_reserved : 2,
+ length : 21;
+ uint32_t rx_ndp_copy_a : 1,
+ reserved_1 : 2,
+ tail_copy_a : 6,
+ vhtb_reserved_copy_a : 2,
+ length_copy_a : 21;
+ uint32_t rx_ndp_copy_b : 1,
+ reserved_2 : 2,
+ tail_copy_b : 6,
+ vhtb_reserved_copy_b : 2,
+ length_copy_b : 21;
+ uint32_t rx_ndp_copy_c : 1,
+ reserved_3 : 2,
+ tail_copy_c : 6,
+ vhtb_reserved_copy_c : 2,
+ length_copy_c : 21;
+#endif
+};
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000
+#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0
+#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20
+#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000
+#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23
+#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28
+#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30
+#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000
+#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30
+#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30
+#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000
+
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20
+#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff
+
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22
+#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000
+
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28
+#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000
+
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30
+#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000
+
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31
+#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/wbm2sw_completion_ring_rx.h b/drivers/staging/fw-api/hw/peach/v1/wbm2sw_completion_ring_rx.h
new file mode 100644
index 0000000000000000000000000000000000000000..f88a753bfbd2bf6140ce9b0de1eb1dbf6ff3fe81
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/wbm2sw_completion_ring_rx.h
@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _WBM2SW_COMPLETION_RING_RX_H_
+#define _WBM2SW_COMPLETION_RING_RX_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_mpdu_desc_info.h"
+#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8
+
+struct wbm2sw_completion_ring_rx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t buffer_virt_addr_31_0 : 32;
+ uint32_t buffer_virt_addr_63_32 : 32;
+ uint32_t release_source_module : 3,
+ bm_action : 3,
+ buffer_or_desc_type : 3,
+ return_buffer_manager : 4,
+ reserved_2a : 2,
+ cache_id : 1,
+ cookie_conversion_status : 1,
+ rxdma_push_reason : 2,
+ rxdma_error_code : 5,
+ reo_push_reason : 2,
+ reo_error_code : 5,
+ wbm_internal_error : 1;
+ struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+ struct rx_msdu_desc_info rx_msdu_desc_info_details;
+ uint32_t buffer_phys_addr_31_0 : 32;
+ uint32_t buffer_phys_addr_39_32 : 8,
+ sw_buffer_cookie : 20,
+ looping_count : 4;
+#else
+ uint32_t buffer_virt_addr_31_0 : 32;
+ uint32_t buffer_virt_addr_63_32 : 32;
+ uint32_t wbm_internal_error : 1,
+ reo_error_code : 5,
+ reo_push_reason : 2,
+ rxdma_error_code : 5,
+ rxdma_push_reason : 2,
+ cookie_conversion_status : 1,
+ cache_id : 1,
+ reserved_2a : 2,
+ return_buffer_manager : 4,
+ buffer_or_desc_type : 3,
+ bm_action : 3,
+ release_source_module : 3;
+ struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+ struct rx_msdu_desc_info rx_msdu_desc_info_details;
+ uint32_t buffer_phys_addr_31_0 : 32;
+ uint32_t looping_count : 4,
+ sw_buffer_cookie : 20,
+ buffer_phys_addr_39_32 : 8;
+#endif
+};
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2
+#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007
+
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5
+#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0
+
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12
+#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00
+
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14
+#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000
+
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15
+#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000
+
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16
+#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000
+
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000
+
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23
+#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000
+
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25
+#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000
+
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30
+#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000
+
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31
+#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
+#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
+
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
+#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff
+
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7
+#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff
+
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27
+#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00
+
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31
+#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/wbm2sw_completion_ring_tx.h b/drivers/staging/fw-api/hw/peach/v1/wbm2sw_completion_ring_tx.h
new file mode 100644
index 0000000000000000000000000000000000000000..713cd8f04669f8d9caef456ca3210fec84cf256e
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/wbm2sw_completion_ring_tx.h
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _WBM2SW_COMPLETION_RING_TX_H_
+#define _WBM2SW_COMPLETION_RING_TX_H_
+
+#include "tx_rate_stats_info.h"
+#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8
+
+struct wbm2sw_completion_ring_tx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ uint32_t buffer_virt_addr_31_0 : 32;
+ uint32_t buffer_virt_addr_63_32 : 32;
+ uint32_t release_source_module : 3,
+ cache_id : 1,
+ reserved_2a : 2,
+ buffer_or_desc_type : 3,
+ return_buffer_manager : 4,
+ tqm_release_reason : 4,
+ rbm_override_valid : 1,
+ sw_buffer_cookie_11_0 : 12,
+ cookie_conversion_status : 1,
+ wbm_internal_error : 1;
+ uint32_t tqm_status_number : 24,
+ transmit_count : 7,
+ sw_release_details_valid : 1;
+ uint32_t ack_frame_rssi : 8,
+ first_msdu : 1,
+ last_msdu : 1,
+ fw_tx_notify_frame : 3,
+ buffer_timestamp : 19;
+ struct tx_rate_stats_info tx_rate_stats;
+ uint32_t sw_peer_id : 16,
+ tid : 4,
+ sw_buffer_cookie_19_12 : 8,
+ looping_count : 4;
+#else
+ uint32_t buffer_virt_addr_31_0 : 32;
+ uint32_t buffer_virt_addr_63_32 : 32;
+ uint32_t wbm_internal_error : 1,
+ cookie_conversion_status : 1,
+ sw_buffer_cookie_11_0 : 12,
+ rbm_override_valid : 1,
+ tqm_release_reason : 4,
+ return_buffer_manager : 4,
+ buffer_or_desc_type : 3,
+ reserved_2a : 2,
+ cache_id : 1,
+ release_source_module : 3;
+ uint32_t sw_release_details_valid : 1,
+ transmit_count : 7,
+ tqm_status_number : 24;
+ uint32_t buffer_timestamp : 19,
+ fw_tx_notify_frame : 3,
+ last_msdu : 1,
+ first_msdu : 1,
+ ack_frame_rssi : 8;
+ struct tx_rate_stats_info tx_rate_stats;
+ uint32_t looping_count : 4,
+ sw_buffer_cookie_19_12 : 8,
+ tid : 4,
+ sw_peer_id : 16;
+#endif
+};
+
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB 0
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB 31
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
+
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB 0
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB 31
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
+
+#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB 0
+#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB 2
+#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007
+
+#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB 3
+#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB 3
+#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK 0x00000008
+
+#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB 4
+#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB 5
+#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK 0x00000030
+
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0
+
+#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB 9
+#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB 12
+#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK 0x00001e00
+
+#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB 13
+#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB 16
+#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000
+
+#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB 17
+#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB 17
+#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000
+
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB 18
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB 29
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000
+
+#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30
+#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30
+#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000
+
+#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008
+#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB 31
+#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB 31
+#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000
+
+#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB 0
+#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB 23
+#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff
+
+#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB 24
+#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB 30
+#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000
+
+#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c
+#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31
+#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31
+#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000
+
+#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010
+#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB 0
+#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB 7
+#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff
+
+#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET 0x00000010
+#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB 8
+#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB 8
+#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK 0x00000100
+
+#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET 0x00000010
+#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB 9
+#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB 9
+#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK 0x00000200
+
+#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010
+#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10
+#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12
+#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00
+
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB 13
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB 31
+#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000
+
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31
+#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff
+
+#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET 0x0000001c
+#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB 0
+#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB 15
+#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK 0x0000ffff
+
+#define WBM2SW_COMPLETION_RING_TX_TID_OFFSET 0x0000001c
+#define WBM2SW_COMPLETION_RING_TX_TID_LSB 16
+#define WBM2SW_COMPLETION_RING_TX_TID_MSB 19
+#define WBM2SW_COMPLETION_RING_TX_TID_MASK 0x000f0000
+
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB 20
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB 27
+#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000
+
+#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c
+#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB 28
+#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB 31
+#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/wbm_buffer_ring.h b/drivers/staging/fw-api/hw/peach/v1/wbm_buffer_ring.h
new file mode 100644
index 0000000000000000000000000000000000000000..eb472a7841e2ce1fdc6748420a04e7abcd18c7ca
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/wbm_buffer_ring.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _WBM_BUFFER_RING_H_
+#define _WBM_BUFFER_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_BUFFER_RING 2
+
+struct wbm_buffer_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct buffer_addr_info buf_addr_info;
+#else
+ struct buffer_addr_info buf_addr_info;
+#endif
+};
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/wbm_link_descriptor_ring.h b/drivers/staging/fw-api/hw/peach/v1/wbm_link_descriptor_ring.h
new file mode 100644
index 0000000000000000000000000000000000000000..96e225e81c7fb547bfabc8ab1a3070d1c1924ccf
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/wbm_link_descriptor_ring.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _WBM_LINK_DESCRIPTOR_RING_H_
+#define _WBM_LINK_DESCRIPTOR_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2
+
+struct wbm_link_descriptor_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct buffer_addr_info desc_addr_info;
+#else
+ struct buffer_addr_info desc_addr_info;
+#endif
+};
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring.h b/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring.h
new file mode 100644
index 0000000000000000000000000000000000000000..06978a0b66d8d485975a3bbe7e71bc4957982bbf
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _WBM_RELEASE_RING_H_
+#define _WBM_RELEASE_RING_H_
+
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_RELEASE_RING 8
+
+struct wbm_release_ring {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct buffer_addr_info released_buff_or_desc_addr_info;
+ uint32_t release_source_module : 3,
+ reserved_2a : 3,
+ buffer_or_desc_type : 3,
+ reserved_2b : 22,
+ wbm_internal_error : 1;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 28,
+ looping_count : 4;
+#else
+ struct buffer_addr_info released_buff_or_desc_addr_info;
+ uint32_t wbm_internal_error : 1,
+ reserved_2b : 22,
+ buffer_or_desc_type : 3,
+ reserved_2a : 3,
+ release_source_module : 3;
+ uint32_t reserved_3a : 32;
+ uint32_t reserved_4a : 32;
+ uint32_t reserved_5a : 32;
+ uint32_t reserved_6a : 32;
+ uint32_t looping_count : 4,
+ reserved_7a : 28;
+#endif
+};
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2
+#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007
+
+#define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008
+#define WBM_RELEASE_RING_RESERVED_2A_LSB 3
+#define WBM_RELEASE_RING_RESERVED_2A_MSB 5
+#define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038
+
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8
+#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0
+
+#define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008
+#define WBM_RELEASE_RING_RESERVED_2B_LSB 9
+#define WBM_RELEASE_RING_RESERVED_2B_MSB 30
+#define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00
+
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31
+#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000
+
+#define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_RESERVED_3A_LSB 0
+#define WBM_RELEASE_RING_RESERVED_3A_MSB 31
+#define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010
+#define WBM_RELEASE_RING_RESERVED_4A_LSB 0
+#define WBM_RELEASE_RING_RESERVED_4A_MSB 31
+#define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RESERVED_5A_LSB 0
+#define WBM_RELEASE_RING_RESERVED_5A_MSB 31
+#define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018
+#define WBM_RELEASE_RING_RESERVED_6A_LSB 0
+#define WBM_RELEASE_RING_RESERVED_6A_MSB 31
+#define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff
+
+#define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_RESERVED_7A_LSB 0
+#define WBM_RELEASE_RING_RESERVED_7A_MSB 27
+#define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff
+
+#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28
+#define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31
+#define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring_rx.h b/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring_rx.h
new file mode 100644
index 0000000000000000000000000000000000000000..dd3c0d39f317ae162010c0bbef7bbcb43b9a5f3a
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring_rx.h
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _WBM_RELEASE_RING_RX_H_
+#define _WBM_RELEASE_RING_RX_H_
+
+#include "rx_msdu_desc_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 8
+
+struct wbm_release_ring_rx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct buffer_addr_info released_buff_or_desc_addr_info;
+ uint32_t release_source_module : 3,
+ bm_action : 3,
+ buffer_or_desc_type : 3,
+ first_msdu_index : 4,
+ reserved_2a : 2,
+ cache_id : 1,
+ cookie_conversion_status : 1,
+ rxdma_push_reason : 2,
+ rxdma_error_code : 5,
+ reo_push_reason : 2,
+ reo_error_code : 5,
+ wbm_internal_error : 1;
+ struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+ struct rx_msdu_desc_info rx_msdu_desc_info_details;
+ uint32_t reserved_6a : 32;
+ uint32_t reserved_7a : 20,
+ ring_id : 8,
+ looping_count : 4;
+#else
+ struct buffer_addr_info released_buff_or_desc_addr_info;
+ uint32_t wbm_internal_error : 1,
+ reo_error_code : 5,
+ reo_push_reason : 2,
+ rxdma_error_code : 5,
+ rxdma_push_reason : 2,
+ cookie_conversion_status : 1,
+ cache_id : 1,
+ reserved_2a : 2,
+ first_msdu_index : 4,
+ buffer_or_desc_type : 3,
+ bm_action : 3,
+ release_source_module : 3;
+ struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+ struct rx_msdu_desc_info rx_msdu_desc_info_details;
+ uint32_t reserved_6a : 32;
+ uint32_t looping_count : 4,
+ ring_id : 8,
+ reserved_7a : 20;
+#endif
+};
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2
+#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007
+
+#define WBM_RELEASE_RING_RX_BM_ACTION_OFFSET 0x00000008
+#define WBM_RELEASE_RING_RX_BM_ACTION_LSB 3
+#define WBM_RELEASE_RING_RX_BM_ACTION_MSB 5
+#define WBM_RELEASE_RING_RX_BM_ACTION_MASK 0x00000038
+
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8
+#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0
+
+#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_OFFSET 0x00000008
+#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_LSB 9
+#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MSB 12
+#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MASK 0x00001e00
+
+#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008
+#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 13
+#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 14
+#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x00006000
+
+#define WBM_RELEASE_RING_RX_CACHE_ID_OFFSET 0x00000008
+#define WBM_RELEASE_RING_RX_CACHE_ID_LSB 15
+#define WBM_RELEASE_RING_RX_CACHE_ID_MSB 15
+#define WBM_RELEASE_RING_RX_CACHE_ID_MASK 0x00008000
+
+#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008
+#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16
+#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16
+#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000
+
+#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008
+#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_LSB 17
+#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MSB 18
+#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000
+
+#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_LSB 19
+#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MSB 23
+#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000
+
+#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008
+#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_LSB 24
+#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MSB 25
+#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MASK 0x03000000
+
+#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_LSB 26
+#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MSB 30
+#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MASK 0x7c000000
+
+#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008
+#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_LSB 31
+#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MSB 31
+#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000
+
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31
+#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000
+
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30
+#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000
+
+#define WBM_RELEASE_RING_RX_RESERVED_6A_OFFSET 0x00000018
+#define WBM_RELEASE_RING_RX_RESERVED_6A_LSB 0
+#define WBM_RELEASE_RING_RX_RESERVED_6A_MSB 31
+#define WBM_RELEASE_RING_RX_RESERVED_6A_MASK 0xffffffff
+
+#define WBM_RELEASE_RING_RX_RESERVED_7A_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_RX_RESERVED_7A_LSB 0
+#define WBM_RELEASE_RING_RX_RESERVED_7A_MSB 19
+#define WBM_RELEASE_RING_RX_RESERVED_7A_MASK 0x000fffff
+
+#define WBM_RELEASE_RING_RX_RING_ID_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_RX_RING_ID_LSB 20
+#define WBM_RELEASE_RING_RX_RING_ID_MSB 27
+#define WBM_RELEASE_RING_RX_RING_ID_MASK 0x0ff00000
+
+#define WBM_RELEASE_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_RX_LOOPING_COUNT_LSB 28
+#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MSB 31
+#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring_tx.h b/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring_tx.h
new file mode 100644
index 0000000000000000000000000000000000000000..283568ff81a8c3fdc1ae9aee0e8a427b514b1a96
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/wbm_release_ring_tx.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef _WBM_RELEASE_RING_TX_H_
+#define _WBM_RELEASE_RING_TX_H_
+
+#include "tx_rate_stats_info.h"
+#include "buffer_addr_info.h"
+#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 8
+
+struct wbm_release_ring_tx {
+#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
+ struct buffer_addr_info released_buff_or_desc_addr_info;
+ uint32_t release_source_module : 3,
+ bm_action : 3,
+ buffer_or_desc_type : 3,
+ first_msdu_index : 4,
+ tqm_release_reason : 4,
+ rbm_override_valid : 1,
+ rbm_override : 4,
+ reserved_2a : 7,
+ cache_id : 1,
+ cookie_conversion_status : 1,
+ wbm_internal_error : 1;
+ uint32_t tqm_status_number : 24,
+ transmit_count : 7,
+ sw_release_details_valid : 1;
+ uint32_t ack_frame_rssi : 8,
+ first_msdu : 1,
+ last_msdu : 1,
+ fw_tx_notify_frame : 3,
+ buffer_timestamp : 19;
+ struct tx_rate_stats_info tx_rate_stats;
+ uint32_t sw_peer_id : 16,
+ tid : 4,
+ tqm_status_number_31_24 : 8,
+ looping_count : 4;
+#else
+ struct buffer_addr_info released_buff_or_desc_addr_info;
+ uint32_t wbm_internal_error : 1,
+ cookie_conversion_status : 1,
+ cache_id : 1,
+ reserved_2a : 7,
+ rbm_override : 4,
+ rbm_override_valid : 1,
+ tqm_release_reason : 4,
+ first_msdu_index : 4,
+ buffer_or_desc_type : 3,
+ bm_action : 3,
+ release_source_module : 3;
+ uint32_t sw_release_details_valid : 1,
+ transmit_count : 7,
+ tqm_status_number : 24;
+ uint32_t buffer_timestamp : 19,
+ fw_tx_notify_frame : 3,
+ last_msdu : 1,
+ first_msdu : 1,
+ ack_frame_rssi : 8;
+ struct tx_rate_stats_info tx_rate_stats;
+ uint32_t looping_count : 4,
+ tqm_status_number_31_24 : 8,
+ tid : 4,
+ sw_peer_id : 16;
+#endif
+};
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00
+
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31
+#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000
+
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2
+#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007
+
+#define WBM_RELEASE_RING_TX_BM_ACTION_OFFSET 0x00000008
+#define WBM_RELEASE_RING_TX_BM_ACTION_LSB 3
+#define WBM_RELEASE_RING_TX_BM_ACTION_MSB 5
+#define WBM_RELEASE_RING_TX_BM_ACTION_MASK 0x00000038
+
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8
+#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0
+
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_OFFSET 0x00000008
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_LSB 9
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MSB 12
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MASK 0x00001e00
+
+#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008
+#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_LSB 13
+#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MSB 16
+#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000
+
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_LSB 17
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MSB 17
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000
+
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_LSB 18
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MSB 21
+#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MASK 0x003c0000
+
+#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008
+#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 22
+#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 28
+#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0x1fc00000
+
+#define WBM_RELEASE_RING_TX_CACHE_ID_OFFSET 0x00000008
+#define WBM_RELEASE_RING_TX_CACHE_ID_LSB 29
+#define WBM_RELEASE_RING_TX_CACHE_ID_MSB 29
+#define WBM_RELEASE_RING_TX_CACHE_ID_MASK 0x20000000
+
+#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008
+#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30
+#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30
+#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000
+
+#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008
+#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_LSB 31
+#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MSB 31
+#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000
+
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 23
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff
+
+#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_LSB 24
+#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MSB 30
+#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000
+
+#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31
+#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31
+#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000
+
+#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010
+#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_LSB 0
+#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MSB 7
+#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff
+
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_OFFSET 0x00000010
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_LSB 8
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_MSB 8
+#define WBM_RELEASE_RING_TX_FIRST_MSDU_MASK 0x00000100
+
+#define WBM_RELEASE_RING_TX_LAST_MSDU_OFFSET 0x00000010
+#define WBM_RELEASE_RING_TX_LAST_MSDU_LSB 9
+#define WBM_RELEASE_RING_TX_LAST_MSDU_MSB 9
+#define WBM_RELEASE_RING_TX_LAST_MSDU_MASK 0x00000200
+
+#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010
+#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10
+#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12
+#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00
+
+#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010
+#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_LSB 13
+#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MSB 31
+#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000
+
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31
+#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff
+
+#define WBM_RELEASE_RING_TX_SW_PEER_ID_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_TX_SW_PEER_ID_LSB 0
+#define WBM_RELEASE_RING_TX_SW_PEER_ID_MSB 15
+#define WBM_RELEASE_RING_TX_SW_PEER_ID_MASK 0x0000ffff
+
+#define WBM_RELEASE_RING_TX_TID_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_TX_TID_LSB 16
+#define WBM_RELEASE_RING_TX_TID_MSB 19
+#define WBM_RELEASE_RING_TX_TID_MASK 0x000f0000
+
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_LSB 20
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MSB 27
+#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MASK 0x0ff00000
+
+#define WBM_RELEASE_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_TX_LOOPING_COUNT_LSB 28
+#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MSB 31
+#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MASK 0xf0000000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/wcss_seq_hwiobase.h b/drivers/staging/fw-api/hw/peach/v1/wcss_seq_hwiobase.h
new file mode 100644
index 0000000000000000000000000000000000000000..12ae566501284dd2232f2c607af0c090216083a5
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/wcss_seq_hwiobase.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef __WCSS_SEQ_HWIOBASE_H__
+#define __WCSS_SEQ_HWIOBASE_H__
+
+#define WCSS_CFGBUS_BASE 0x00008000
+#define WCSS_CFGBUS_BASE_SIZE 0x00008000
+#define WCSS_CFGBUS_BASE_PHYS 0x00008000
+
+#define UMAC_NOC_BASE 0x00140000
+#define UMAC_NOC_BASE_SIZE 0x00004400
+#define UMAC_NOC_BASE_PHYS 0x00140000
+
+#define PHYA0_BASE 0x00300000
+#define PHYA0_BASE_SIZE 0x00300000
+#define PHYA0_BASE_PHYS 0x00300000
+
+#define PHYA1_BASE 0x00600000
+#define PHYA1_BASE_SIZE 0x00300000
+#define PHYA1_BASE_PHYS 0x00600000
+
+#define DMAC_BASE 0x00900000
+#define DMAC_BASE_SIZE 0x00080000
+#define DMAC_BASE_PHYS 0x00900000
+
+#define UMAC_BASE 0x00a00000
+#define UMAC_BASE_SIZE 0x0004d000
+#define UMAC_BASE_PHYS 0x00a00000
+
+#define PMAC0_BASE 0x00a80000
+#define PMAC0_BASE_SIZE 0x00040000
+#define PMAC0_BASE_PHYS 0x00a80000
+
+#define PMAC1_BASE 0x00ac0000
+#define PMAC1_BASE_SIZE 0x00040000
+#define PMAC1_BASE_PHYS 0x00ac0000
+
+#define WFSS_AMCSS_BASE 0x00b00000
+#define WFSS_AMCSS_BASE_SIZE 0x00040000
+#define WFSS_AMCSS_BASE_PHYS 0x00b00000
+
+#define CXC_BASE 0x00b40000
+#define CXC_BASE_SIZE 0x00010000
+#define CXC_BASE_PHYS 0x00b40000
+
+#define WFSS_PMM_BASE 0x00b50000
+#define WFSS_PMM_BASE_SIZE 0x00002401
+#define WFSS_PMM_BASE_PHYS 0x00b50000
+
+#define WFSS_CC_BASE 0x00b60000
+#define WFSS_CC_BASE_SIZE 0x00008000
+#define WFSS_CC_BASE_PHYS 0x00b60000
+
+#define WCMN_CORE_BASE 0x00b68000
+#define WCMN_CORE_BASE_SIZE 0x000008a9
+#define WCMN_CORE_BASE_PHYS 0x00b68000
+
+#define WIFI_CFGBUS_APB_TSLV_BASE 0x00b6b000
+#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE 0x00001000
+#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS 0x00b6b000
+
+#define WFSS_CFGBUS_BASE 0x00b6c000
+#define WFSS_CFGBUS_BASE_SIZE 0x000000a0
+#define WFSS_CFGBUS_BASE_PHYS 0x00b6c000
+
+#define WIFI_CFGBUS_AHB_TSLV_BASE 0x00b6d000
+#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE 0x00001000
+#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS 0x00b6d000
+
+#define UMAC_ACMT_BASE 0x00b6e000
+#define UMAC_ACMT_BASE_SIZE 0x00001000
+#define UMAC_ACMT_BASE_PHYS 0x00b6e000
+
+#define WCSS_CC_BASE 0x00b80000
+#define WCSS_CC_BASE_SIZE 0x00010000
+#define WCSS_CC_BASE_PHYS 0x00b80000
+
+#define PMM_TOP_BASE 0x00b90000
+#define PMM_TOP_BASE_SIZE 0x00010000
+#define PMM_TOP_BASE_PHYS 0x00b90000
+
+#define WCSS_TOP_CMN_BASE 0x00ba0000
+#define WCSS_TOP_CMN_BASE_SIZE 0x00004000
+#define WCSS_TOP_CMN_BASE_PHYS 0x00ba0000
+
+#define MSIP_BASE 0x00bb0000
+#define MSIP_BASE_SIZE 0x00010000
+#define MSIP_BASE_PHYS 0x00bb0000
+
+#define DBG_BASE 0x01000000
+#define DBG_BASE_SIZE 0x00100000
+#define DBG_BASE_PHYS 0x01000000
+
+#define Q6SS_WLAN_BASE 0x01100000
+#define Q6SS_WLAN_BASE_SIZE 0x00100000
+#define Q6SS_WLAN_BASE_PHYS 0x01100000
+
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/wcss_seq_hwioreg_umac.h b/drivers/staging/fw-api/hw/peach/v1/wcss_seq_hwioreg_umac.h
new file mode 100644
index 0000000000000000000000000000000000000000..70f00a5642055bef59e1bf288c831c6bfe349287
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/wcss_seq_hwioreg_umac.h
@@ -0,0 +1,2269 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#ifndef __WCSS_SEQ_HWIOREG_UMAC_H__
+#define __WCSS_SEQ_HWIOREG_UMAC_H__
+
+#include "seq_hwio.h"
+#include "wcss_seq_hwiobase.h"
+#ifdef SCALE_INCLUDES
+#include "HALhwio.h"
+#else
+#include "msmhwio.h"
+#endif
+
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x) ((x) + 0xa0)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x) ((x) + 0xa0)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS (0xa0)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK 0x7
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR 0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK 0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR 0x3
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x) \
+ in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x))
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m) \
+ in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v) \
+ out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x))
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK 0x7
+#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT 0
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x) ((x) + 0xa4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x) ((x) + 0xa4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS (0xa4)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK 0x1ffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR 0x00001ffe
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK 0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR 0x3
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x) \
+ in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v) \
+ out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK 0x1ffe000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT 13
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK 0x1ffe
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT 1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK 0x1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT 0
+
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK 0x1000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT 12
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK 0x800
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT 11
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK 0x400
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT 10
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK 0x200
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT 9
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x) ((x) + 0xd8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x) ((x) + 0xd8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS (0xd8)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK 0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR 0x00000000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK 0xffffffff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR 0x1
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x) \
+ in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x))
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m) \
+ in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK 0xff000000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT 24
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK 0xff0000
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT 16
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK 0xff00
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT 8
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK 0xff
+#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT 0
+
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n) ((base) + 0X1A4 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n) ((base) + 0X1A4 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n) (0X1A4 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK 0xfff
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn 3
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR 0x00000000
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK 0xffffffff
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR 0x1
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n) \
+ in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK)
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask) \
+ in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK 0xfff
+#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT 0
+
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x) ((x) + 0x1c4)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_PHYS(x) ((x) + 0x1c4)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OFFS (0x1c4)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_RMSK 0x3
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR 0x00000000
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR_RMSK 0xffffffff
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ATTR 0x3
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x) \
+ in_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x))
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_INM(x, m) \
+ in_dword_masked(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x), m)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUT(x, v) \
+ out_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),v)
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x))
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_BMSK 0x2
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_SHFT 1
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_BMSK 0x1
+#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_SHFT 0
+
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X508 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X508 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n) (0X508 + (0x4*(n)))
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK 0xffffffff
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn 63
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR 0x00000000
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR 0x1
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n) \
+ in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK)
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask) \
+ in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff
+#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT 0
+
+#define WBM_REG_REG_BASE (UMAC_BASE + 0x00034000)
+#define HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x40)
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x44)
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff
+#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0
+
+#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x7c)
+#define HWIO_WBM_R0_WBM_CFG_2_ADDR(x) ((x) + 0x90)
+#define HWIO_WBM_R0_WBM_CFG_2_PHYS(x) ((x) + 0x90)
+#define HWIO_WBM_R0_WBM_CFG_2_OFFS (0x90)
+#define HWIO_WBM_R0_WBM_CFG_2_RMSK 0x4b
+#define HWIO_WBM_R0_WBM_CFG_2_POR 0x00000040
+#define HWIO_WBM_R0_WBM_CFG_2_POR_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_CFG_2_ATTR 0x3
+#define HWIO_WBM_R0_WBM_CFG_2_IN(x) \
+ in_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x))
+#define HWIO_WBM_R0_WBM_CFG_2_INM(x, m) \
+ in_dword_masked(HWIO_WBM_R0_WBM_CFG_2_ADDR(x), m)
+#define HWIO_WBM_R0_WBM_CFG_2_OUT(x, v) \
+ out_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),v)
+#define HWIO_WBM_R0_WBM_CFG_2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),m,v,HWIO_WBM_R0_WBM_CFG_2_IN(x))
+#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK 0x40
+#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_SHFT 6
+#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_BMSK 0x8
+#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_SHFT 3
+#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_BMSK 0x2
+#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_SHFT 1
+#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_BMSK 0x1
+#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_SHFT 0
+
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x) ((x) + 0x94)
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_BMSK 0x100
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_SHFT 8
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_BMSK 0x80
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_SHFT 7
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_BMSK 0x40
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_SHFT 6
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_BMSK 0x20
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_SHFT 5
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_BMSK 0x10
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_SHFT 4
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_BMSK 0x8
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_SHFT 3
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_BMSK 0x4
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_SHFT 2
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_BMSK 0x2
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_SHFT 1
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_BMSK 0x1
+#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_SHFT 0
+
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) ((x) + 0x240)
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x7fc
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 2
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x2
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 1
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) ((x) + 0x244)
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 16
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0xffff
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) ((x) + 0x250)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) ((x) + 0x254)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 8
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0xff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0x260)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) ((x) + 0x264)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x1fff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0x270)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) ((x) + 0x274)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x1fff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 8
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) ((x) + 0x27c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x37c)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xd3c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) ((x) + 0xd4c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xe08)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xe80)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x1408)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x1408)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x1408)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \
+ in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \
+ in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \
+ out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0
+
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x140c)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x140c)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x140c)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \
+ in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \
+ in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \
+ out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff
+#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0
+
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x1410)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x1410)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x1410)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \
+ in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \
+ in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \
+ out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0
+
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x1414)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x1414)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x1414)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \
+ in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \
+ in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \
+ out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff
+#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0
+
+#define HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1418)
+#define HWIO_WBM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1418)
+#define HWIO_WBM_R0_LPM_FW_CTRL_OFFS (0x1418)
+#define HWIO_WBM_R0_LPM_FW_CTRL_RMSK 0x3f
+#define HWIO_WBM_R0_LPM_FW_CTRL_POR 0x00000000
+#define HWIO_WBM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WBM_R0_LPM_FW_CTRL_ATTR 0x3
+#define HWIO_WBM_R0_LPM_FW_CTRL_IN(x) \
+ in_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_WBM_R0_LPM_FW_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_WBM_R0_LPM_FW_CTRL_OUT(x, v) \
+ out_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_WBM_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_WBM_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_BMSK 0x20
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_SHFT 5
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_BMSK 0x10
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_SHFT 4
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1
+#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0
+
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x) ((x) + 0x141c)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_PHYS(x) ((x) + 0x141c)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OFFS (0x141c)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RMSK 0xffffffff
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR 0x00000000
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ATTR 0x3
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x) \
+ in_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x))
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x), m)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUT(x, v) \
+ out_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),v)
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x))
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_BMSK 0xffe00000
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_SHFT 21
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_BMSK 0x1f0000
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_SHFT 16
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_BMSK 0xf800
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_SHFT 11
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_BMSK 0x7c0
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_SHFT 6
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_BMSK 0x3e
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_SHFT 1
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_BMSK 0x1
+#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_SHFT 0
+
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2030)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2030)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2030)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x3ff
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \
+ in_dword(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_BMSK 0x200
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_SHFT 9
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_BMSK 0x100
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_SHFT 8
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7
+#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0
+
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2034 + (0x4*(n)))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2034 + (0x4*(n)))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2034 + (0x4*(n)))
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_MAXn 255
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR 0x00000000
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ATTR 0x1
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INI(base,n) \
+ in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK)
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \
+ in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff
+#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0
+
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3010)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) ((x) + 0x30b8)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x) ((x) + 0x30c8)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x30d0)
+#define REO_REG_REG_BASE (UMAC_BASE + 0x00038000)
+#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0)
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x8
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 3
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x4
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 2
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x) ((x) + 0x14)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x) ((x) + 0x14)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS (0x14)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK 0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR 0x76543210
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR 0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x) \
+ in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v) \
+ out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK 0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT 28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK 0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT 24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK 0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT 20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK 0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT 16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK 0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT 12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK 0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT 8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK 0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT 4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK 0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT 0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x) ((x) + 0x18)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x) ((x) + 0x18)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS (0x18)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK 0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR 0x66666a98
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR 0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x) \
+ in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v) \
+ out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK 0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT 28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK 0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT 24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK 0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT 20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK 0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT 16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK 0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT 12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK 0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT 8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK 0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT 4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK 0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT 0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x) ((x) + 0x1c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x) ((x) + 0x1c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS (0x1c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK 0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR 0x66666666
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR 0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x) \
+ in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v) \
+ out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK 0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT 28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK 0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT 24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK 0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT 20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK 0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT 16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK 0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT 12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK 0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT 8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK 0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT 4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK 0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT 0
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x) ((x) + 0x20)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x) ((x) + 0x20)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS (0x20)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK 0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR 0x66666666
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR 0x3
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x) \
+ in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v) \
+ out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x))
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK 0xf0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT 28
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK 0xf000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT 24
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK 0xf00000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT 20
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK 0xf0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT 16
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK 0xf000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT 12
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK 0xf00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT 8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK 0xf0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT 4
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK 0xf
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT 0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) ((x) + 0x38)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 28
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0xf000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0xf00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0xf0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0xf000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0xf00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0xf0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0xf
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) ((x) + 0x3c)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x) ((x) + 0x40)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x) ((x) + 0x40)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS (0x40)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK 0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR 0x55555555
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR 0x3
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x) \
+ in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v) \
+ out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK 0xf0000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT 28
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK 0xf000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT 24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK 0xf00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT 20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK 0xf0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT 16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK 0xf000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT 12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK 0xf00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT 8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK 0xf0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT 4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK 0xf
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT 0
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x) ((x) + 0x44)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x) ((x) + 0x44)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS (0x44)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK 0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR 0x55555555
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR 0x3
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x) \
+ in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v) \
+ out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x))
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK 0xf0000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT 28
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK 0xf000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT 24
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK 0xf00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT 20
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK 0xf0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT 16
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK 0xf000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT 12
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK 0xf00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT 8
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK 0xf0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT 4
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK 0xf
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT 0
+
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x) ((x) + 0x48)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x) ((x) + 0x48)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS (0x48)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK 0x1ffff
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR 0x00000000
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR 0x3
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x) \
+ in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x))
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v) \
+ out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v)
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x))
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK 0x1ffff
+#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT 0
+
+#define HWIO_REO_R0_PN_IN_DEST_ADDR(x) ((x) + 0x68)
+#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x6c)
+#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x70)
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK 0x100000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT 20
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK 0x80000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT 19
+#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00
+#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8
+#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff
+#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) ((x) + 0x2a8)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 8
+#define HWIO_REO_R0_REO_CMD_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_REO_R0_REO_CMD_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x320)
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8
+#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_REO_R0_SW2REO1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_REO_R0_SW2REO1_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) ((x) + 0x500)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) ((x) + 0x504)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8
+#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x508)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x510)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x514)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x518)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x524)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x548)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x54c)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x550)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x574)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f
+#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x554)
+#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x558)
+#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x55c)
+#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x560)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x578)
+#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0x8c0)
+#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00
+#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT 8
+#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0xaa0)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_REO_R0_MISC_CFG_ADDR(x) ((x) + 0xb24)
+#define HWIO_REO_R0_MISC_CFG_PHYS(x) ((x) + 0xb24)
+#define HWIO_REO_R0_MISC_CFG_OFFS (0xb24)
+#define HWIO_REO_R0_MISC_CFG_RMSK 0x1
+#define HWIO_REO_R0_MISC_CFG_POR 0x00000000
+#define HWIO_REO_R0_MISC_CFG_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_MISC_CFG_ATTR 0x3
+#define HWIO_REO_R0_MISC_CFG_IN(x) \
+ in_dword(HWIO_REO_R0_MISC_CFG_ADDR(x))
+#define HWIO_REO_R0_MISC_CFG_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_MISC_CFG_ADDR(x), m)
+#define HWIO_REO_R0_MISC_CFG_OUT(x, v) \
+ out_dword(HWIO_REO_R0_MISC_CFG_ADDR(x),v)
+#define HWIO_REO_R0_MISC_CFG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_IN(x))
+#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_BMSK 0x1
+#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_SHFT 0
+
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x) ((x) + 0xb28)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x) ((x) + 0xb28)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS (0xb28)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK 0x1ff
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR 0x0000002d
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR 0x3
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x) \
+ in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x))
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v) \
+ out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v)
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x))
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK 0x1fe
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT 1
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK 0x1
+#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT 0
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) ((x) + 0xb2c)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) ((x) + 0xb30)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) ((x) + 0xb34)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) ((x) + 0xb38)
+#define HWIO_REO_R0_MISC_CTL_ADDR(x) ((x) + 0xba0)
+#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK 0x1e00000
+#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT 21
+#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x1e0000
+#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 17
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xd78)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xd78)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xd78)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \
+ in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \
+ out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd7c)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd7c)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xd7c)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \
+ in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \
+ out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff
+#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xd80)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xd80)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xd80)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \
+ in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \
+ out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0
+
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd84)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd84)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xd84)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \
+ in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \
+ out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff
+#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0
+
+#define HWIO_REO_R0_CREDIT_ADDR(x) ((x) + 0xd88)
+#define HWIO_REO_R0_CREDIT_PHYS(x) ((x) + 0xd88)
+#define HWIO_REO_R0_CREDIT_OFFS (0xd88)
+#define HWIO_REO_R0_CREDIT_RMSK 0xffffffff
+#define HWIO_REO_R0_CREDIT_POR 0x00000000
+#define HWIO_REO_R0_CREDIT_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_CREDIT_ATTR 0x3
+#define HWIO_REO_R0_CREDIT_IN(x) \
+ in_dword(HWIO_REO_R0_CREDIT_ADDR(x))
+#define HWIO_REO_R0_CREDIT_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_CREDIT_ADDR(x), m)
+#define HWIO_REO_R0_CREDIT_OUT(x, v) \
+ out_dword(HWIO_REO_R0_CREDIT_ADDR(x),v)
+#define HWIO_REO_R0_CREDIT_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_CREDIT_ADDR(x),m,v,HWIO_REO_R0_CREDIT_IN(x))
+#define HWIO_REO_R0_CREDIT_VAL_BMSK 0xffffffff
+#define HWIO_REO_R0_CREDIT_VAL_SHFT 0
+
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x) ((x) + 0xd8c)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_PHYS(x) ((x) + 0xd8c)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OFFS (0xd8c)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_RMSK 0x7
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR 0x00000002
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ATTR 0x3
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x) \
+ in_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x))
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x), m)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUT(x, v) \
+ out_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),v)
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),m,v,HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x))
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_BMSK 0x7
+#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_SHFT 0
+
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x) ((x) + 0xd90)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_PHYS(x) ((x) + 0xd90)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_OFFS (0xd90)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR 0x00000000
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ATTR 0x1
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_IN(x) \
+ in_dword(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x))
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x), m)
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_BMSK 0xffffffff
+#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_SHFT 0
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_BMSK 0x2000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_SHFT 13
+#define HWIO_REO_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0xdbc)
+#define HWIO_REO_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0xdbc)
+#define HWIO_REO_R0_LPM_FW_CTRL_OFFS (0xdbc)
+#define HWIO_REO_R0_LPM_FW_CTRL_RMSK 0x7
+#define HWIO_REO_R0_LPM_FW_CTRL_POR 0x00000000
+#define HWIO_REO_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff
+#define HWIO_REO_R0_LPM_FW_CTRL_ATTR 0x3
+#define HWIO_REO_R0_LPM_FW_CTRL_IN(x) \
+ in_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_REO_R0_LPM_FW_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_REO_R0_LPM_FW_CTRL_OUT(x, v) \
+ out_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_REO_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_REO_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1
+#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x2054)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x2054)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x2054)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \
+ in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x))
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \
+ in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2058)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2058)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2058)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \
+ in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x))
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \
+ in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x) ((x) + 0x205c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x) ((x) + 0x205c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS (0x205c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK 0xff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR 0x00000000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR 0x2
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v) \
+ out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK 0xff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT 0
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x) ((x) + 0x2060)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x) ((x) + 0x2060)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS (0x2060)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR 0x00000000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR 0x2
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v) \
+ out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT 0
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x) ((x) + 0x2064)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x) ((x) + 0x2064)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS (0x2064)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR 0x00000000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR 0x3
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x) \
+ in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x))
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m) \
+ in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v) \
+ out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x))
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK 0xffff0000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT 16
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK 0xfff0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT 4
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK 0x8
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT 3
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK 0x4
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT 2
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK 0x2
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT 1
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK 0x1
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT 0
+
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x) ((x) + 0x20c0)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x) ((x) + 0x20c0)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS (0x20c0)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK 0x3f
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR 0x00000000
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK 0xffffffff
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR 0x1
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x) \
+ in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x))
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m)
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK 0x20
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT 5
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK 0x10
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT 4
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK 0x8
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT 3
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK 0x4
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT 2
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK 0x2
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT 1
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK 0x1
+#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT 0
+
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x) ((x) + 0x20c4)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x) ((x) + 0x20c4)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS (0x20c4)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK 0xffffffff
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR 0x00000000
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK 0xffffffff
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR 0x3
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x) \
+ in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x))
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m) \
+ in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v) \
+ out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v)
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x))
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK 0xffffffff
+#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT 0
+
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x20cc)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x20cc)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x20cc)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_IN(x) \
+ in_dword(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7
+#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0
+
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X20D0 + (0x4*(n)))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X20D0 + (0x4*(n)))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X20D0 + (0x4*(n)))
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_MAXn 255
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR 0x00000000
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ATTR 0x1
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INI(base,n) \
+ in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK)
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \
+ in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff
+#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0
+
+#define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) ((x) + 0x3020)
+#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) ((x) + 0x3028)
+#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) ((x) + 0x3048)
+#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) ((x) + 0x304c)
+#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) ((x) + 0x3050)
+#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x) ((x) + 0x3088)
+#define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) ((x) + 0x30a8)
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_BMSK 0x80
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_SHFT 7
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_BMSK 0x40
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_SHFT 6
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_BMSK 0x20
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_SHFT 5
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_BMSK 0x10
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_SHFT 4
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_BMSK 0x8
+#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_SHFT 3
+#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x3f4)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x3f4)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x3f4)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \
+ in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \
+ out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x3f8)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x3f8)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x3f8)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \
+ in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \
+ out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x3fc)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x3fc)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x3fc)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \
+ in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \
+ out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0
+
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x400)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x400)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x400)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \
+ in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \
+ out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff
+#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0
+
+#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK 0x80000000
+#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT 31
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_BMSK 0x8000
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_SHFT 15
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_BMSK 0x4000
+#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_SHFT 14
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK 0x2000
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT 13
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK 0x1000
+#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT 12
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK 0x800
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT 11
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK 0x400
+#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT 10
+#define HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x480)
+#define HWIO_TQM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x480)
+#define HWIO_TQM_R0_LPM_FW_CTRL_OFFS (0x480)
+#define HWIO_TQM_R0_LPM_FW_CTRL_RMSK 0xf
+#define HWIO_TQM_R0_LPM_FW_CTRL_POR 0x00000000
+#define HWIO_TQM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff
+#define HWIO_TQM_R0_LPM_FW_CTRL_ATTR 0x3
+#define HWIO_TQM_R0_LPM_FW_CTRL_IN(x) \
+ in_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_TQM_R0_LPM_FW_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_TQM_R0_LPM_FW_CTRL_OUT(x, v) \
+ out_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_TQM_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TQM_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1
+#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0
+
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x) ((x) + 0x484)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_PHYS(x) ((x) + 0x484)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_OFFS (0x484)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_RMSK 0x3
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR 0x00000000
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR_RMSK 0xffffffff
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_ATTR 0x3
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x) \
+ in_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x))
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x), m)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUT(x, v) \
+ out_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),v)
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x))
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_BMSK 0x2
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_SHFT 1
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_BMSK 0x1
+#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_SHFT 0
+
+#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_BMSK 0x20000000
+#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_SHFT 29
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x) ((x) + 0x508)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x) ((x) + 0x508)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS (0x508)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK 0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR 0x00000000
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK 0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR 0x3
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x) \
+ in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v) \
+ out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v)
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK 0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT 0
+
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x) ((x) + 0x50c)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x) ((x) + 0x50c)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS (0x50c)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK 0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR 0x00000000
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK 0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR 0x3
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x) \
+ in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v) \
+ out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK 0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT 0
+
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x) ((x) + 0x510)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x) ((x) + 0x510)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS (0x510)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK 0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR 0x00000000
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK 0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR 0x3
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x) \
+ in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v) \
+ out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v)
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x))
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK 0xffffffff
+#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT 0
+
+#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x) ((x) + 0x51c)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x) ((x) + 0x51c)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS (0x51c)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK 0xfff
+#define HWIO_TQM_R0_WATCHDOG_SRNG_POR 0x00000710
+#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK 0xffffffff
+#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR 0x3
+#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x) \
+ in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x))
+#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v) \
+ out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v)
+#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x))
+#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK 0xfff
+#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT 0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x204c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x204c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x204c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \
+ in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2050)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2050)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2050)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \
+ in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x) ((x) + 0x2054)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x) ((x) + 0x2054)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS (0x2054)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK 0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR 0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK 0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR 0x2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v) \
+ out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK 0xff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT 0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x) ((x) + 0x2058)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x) ((x) + 0x2058)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS (0x2058)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK 0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR 0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK 0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR 0x2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v) \
+ out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT 0
+
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x) ((x) + 0x205c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x) ((x) + 0x205c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS (0x205c)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK 0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR 0x00000000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK 0xffffffff
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR 0x3
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x) \
+ in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v) \
+ out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v)
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x))
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK 0xffff0000
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT 16
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK 0xfff0
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT 4
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK 0x8
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT 3
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK 0x4
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT 2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK 0x2
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT 1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK 0x1
+#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT 0
+
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x) ((x) + 0x2060)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_PHYS(x) ((x) + 0x2060)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_OFFS (0x2060)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_RMSK 0x1ffff
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR 0x00000000
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR_RMSK 0xffffffff
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_ATTR 0x3
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x) \
+ in_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x))
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x), m)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUT(x, v) \
+ out_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),v)
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x))
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff
+#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_SHFT 0
+
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x) ((x) + 0x2064)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_PHYS(x) ((x) + 0x2064)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OFFS (0x2064)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_RMSK 0x1ffff
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR 0x00000000
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR_RMSK 0xffffffff
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ATTR 0x3
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x) \
+ in_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x))
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x), m)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUT(x, v) \
+ out_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),v)
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x))
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff
+#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_SHFT 0
+
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x) ((x) + 0x2068)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_PHYS(x) ((x) + 0x2068)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_OFFS (0x2068)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_RMSK 0x1ffff
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR 0x00000000
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR_RMSK 0xffffffff
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_ATTR 0x3
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x) \
+ in_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x))
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x), m)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUT(x, v) \
+ out_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),v)
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x))
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff
+#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_SHFT 0
+
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x) ((x) + 0x206c)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_PHYS(x) ((x) + 0x206c)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_OFFS (0x206c)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_RMSK 0xf
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR 0x00000000
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ATTR 0x1
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_IN(x) \
+ in_dword(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x))
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x), m)
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_BMSK 0x8
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_SHFT 3
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_BMSK 0x4
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_SHFT 2
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_BMSK 0x2
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_SHFT 1
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_BMSK 0x1
+#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_SHFT 0
+
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x) ((x) + 0x2070)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_PHYS(x) ((x) + 0x2070)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_OFFS (0x2070)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_RMSK 0xffffffff
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR 0x00000000
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR_RMSK 0xffffffff
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ATTR 0x1
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_IN(x) \
+ in_dword(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x))
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x), m)
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_BMSK 0xffffffff
+#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_SHFT 0
+
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x) ((x) + 0x2074)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_PHYS(x) ((x) + 0x2074)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_OFFS (0x2074)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_RMSK 0xffffffff
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR 0x00000000
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR_RMSK 0xffffffff
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ATTR 0x1
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_IN(x) \
+ in_dword(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x))
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x), m)
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_BMSK 0xffffffff
+#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_SHFT 0
+
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2078)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2078)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2078)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0xff
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \
+ in_dword(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7
+#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0
+
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2114 + (0x4*(n)))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2114 + (0x4*(n)))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2114 + (0x4*(n)))
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_MAXn 127
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR 0x00000000
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ATTR 0x1
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INI(base,n) \
+ in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK)
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \
+ in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff
+#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0
+
+#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_BMSK 0x80
+#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_SHFT 7
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x800000
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 23
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x400000
+#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 22
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000
+#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000
+#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80
+#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20
+#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000
+#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x800000
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 23
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x400000
+#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 22
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000
+#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000
+#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80
+#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20
+#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000
+#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16
+#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK 0x40
+#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT 6
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x) ((x) + 0x168)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x) ((x) + 0x168)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS (0x168)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK 0xf
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR 0x0000000a
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK 0xffffffff
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR 0x3
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x) \
+ in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x))
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m) \
+ in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v) \
+ out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v)
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x))
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK 0xf
+#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT 0
+
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x16c)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x16c)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_OFFS (0x16c)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_RMSK 0x1f
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR 0x00000000
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_ATTR 0x3
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x) \
+ in_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUT(x, v) \
+ out_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_BMSK 0x10
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_SHFT 4
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_BMSK 0x8
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_SHFT 3
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_BMSK 0x4
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_SHFT 2
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_BMSK 0x2
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_SHFT 1
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1
+#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0
+
+#define HWIO_UMCMN_R0_LINK_ID_ADDR(x) ((x) + 0x170)
+#define HWIO_UMCMN_R0_LINK_ID_PHYS(x) ((x) + 0x170)
+#define HWIO_UMCMN_R0_LINK_ID_OFFS (0x170)
+#define HWIO_UMCMN_R0_LINK_ID_RMSK 0xffff
+#define HWIO_UMCMN_R0_LINK_ID_POR 0x000052c8
+#define HWIO_UMCMN_R0_LINK_ID_POR_RMSK 0xffffffff
+#define HWIO_UMCMN_R0_LINK_ID_ATTR 0x3
+#define HWIO_UMCMN_R0_LINK_ID_IN(x) \
+ in_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x))
+#define HWIO_UMCMN_R0_LINK_ID_INM(x, m) \
+ in_dword_masked(HWIO_UMCMN_R0_LINK_ID_ADDR(x), m)
+#define HWIO_UMCMN_R0_LINK_ID_OUT(x, v) \
+ out_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x),v)
+#define HWIO_UMCMN_R0_LINK_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_UMCMN_R0_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_LINK_ID_IN(x))
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_BMSK 0x80
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_SHFT 7
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_BMSK 0x40
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_SHFT 6
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_BMSK 0x38
+#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_SHFT 3
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_BMSK 0x7
+#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_SHFT 0
+
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK 0x4000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT 14
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK 0x2000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT 13
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK 0x1000
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT 12
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK 0x800
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT 11
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK 0x400
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT 10
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK 0x200
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT 9
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK 0x100
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT 8
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK 0x80
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT 7
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK 0x40
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT 6
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK 0x20
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT 5
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK 0x10
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT 4
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK 0x8
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT 3
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK 0x4
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT 2
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK 0x2
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT 1
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK 0x1
+#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT 0
+
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x) ((x) + 0x184)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_PHYS(x) ((x) + 0x184)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OFFS (0x184)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_RMSK 0x1
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR 0x00000000
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR_RMSK 0xffffffff
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ATTR 0x3
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x) \
+ in_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x))
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_INM(x, m) \
+ in_dword_masked(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x), m)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUT(x, v) \
+ out_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),v)
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x))
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_BMSK 0x1
+#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_SHFT 0
+
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x) ((x) + 0x188)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_PHYS(x) ((x) + 0x188)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OFFS (0x188)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_RMSK 0x1ffff
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR 0x00000000
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR_RMSK 0xffffffff
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ATTR 0x3
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x) \
+ in_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x))
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_INM(x, m) \
+ in_dword_masked(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x), m)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUT(x, v) \
+ out_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),v)
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),m,v,HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x))
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_BMSK 0x1fe00
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_SHFT 9
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_BMSK 0x1fe
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_SHFT 1
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_BMSK 0x1
+#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_SHFT 0
+
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2010)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2010)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2010)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x1ff
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_IN(x) \
+ in_dword(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_BMSK 0x100
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_SHFT 8
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_BMSK 0x80
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_SHFT 7
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_BMSK 0x40
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_SHFT 6
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_BMSK 0x20
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_SHFT 5
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7
+#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0
+
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n) ((base) + 0X2014 + (0x4*(n)))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_PHYS(base,n) ((base) + 0X2014 + (0x4*(n)))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OFFS(n) (0X2014 + (0x4*(n)))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK 0xffffffff
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_MAXn 7
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR 0x00000000
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR_RMSK 0xffffffff
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ATTR 0x3
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n) \
+ in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK)
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INMI(base,n,mask) \
+ in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), mask)
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTI(base,n,val) \
+ out_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),val)
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTMI(base,n,mask,val) \
+ out_dword_masked_ns(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),mask,val,HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n))
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_BMSK 0xffffffff
+#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_SHFT 0
+
+#define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) ((x) + 0x20)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23
+#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK 0x8000000
+#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT 27
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n) ((base) + 0X8C + (0x4*(n)))
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT 17
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT 15
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT 14
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT 12
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT 11
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT 10
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT 9
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT 8
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT 7
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT 3
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT 1
+#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT 0
+
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n) ((base) + 0X240 + (0x4*(n)))
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff
+#define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) ((x) + 0x6c0)
+#define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0xffffff
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 21
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 18
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 15
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 12
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 9
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 6
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 3
+#define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) ((x) + 0x6e8)
+#define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0xef
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK 0x800000
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT 23
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_BMSK 0x10
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_SHFT 4
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK 0x8
+#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT 3
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x) ((x) + 0x8b4)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_PHYS(x) ((x) + 0x8b4)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_OFFS (0x8b4)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_RMSK 0x3
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR 0x00000000
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR_RMSK 0xffffffff
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_ATTR 0x3
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x) \
+ in_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x))
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_INM(x, m) \
+ in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x), m)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUT(x, v) \
+ out_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),v)
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x))
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_BMSK 0x2
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_SHFT 1
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_BMSK 0x1
+#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_SHFT 0
+
+#define HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x914)
+#define HWIO_TCL_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x914)
+#define HWIO_TCL_R0_LPM_FW_CTRL_OFFS (0x914)
+#define HWIO_TCL_R0_LPM_FW_CTRL_RMSK 0x7
+#define HWIO_TCL_R0_LPM_FW_CTRL_POR 0x00000000
+#define HWIO_TCL_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff
+#define HWIO_TCL_R0_LPM_FW_CTRL_ATTR 0x3
+#define HWIO_TCL_R0_LPM_FW_CTRL_IN(x) \
+ in_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x))
+#define HWIO_TCL_R0_LPM_FW_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x), m)
+#define HWIO_TCL_R0_LPM_FW_CTRL_OUT(x, v) \
+ out_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),v)
+#define HWIO_TCL_R0_LPM_FW_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TCL_R0_LPM_FW_CTRL_IN(x))
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1
+#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0x918)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0x91c)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) ((x) + 0x920)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) ((x) + 0x928)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x934)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x938)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x948)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x94c)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x960)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x964)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0x968)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) ((x) + 0x990)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x) ((x) + 0xb70)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT 8
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) ((x) + 0xd50)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 8
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xedc)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xedc)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xedc)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \
+ in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \
+ in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \
+ out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0
+
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xee0)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xee0)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xee0)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \
+ in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \
+ in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \
+ out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff
+#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0
+
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xee4)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xee4)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xee4)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \
+ in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \
+ in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \
+ out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0
+
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xee8)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xee8)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xee8)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \
+ in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \
+ in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \
+ out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v)
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x))
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff
+#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0
+
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x1000)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x1000)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x1000)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_IN(x) \
+ in_dword(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x))
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m)
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7
+#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0
+
+#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x20000
+#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 17
+#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x20000
+#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 17
+#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x1030)
+#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x1030)
+#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS (0x1030)
+#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK 0x1ff
+#define HWIO_TCL_R1_TESTBUS_CTRL_POR 0x00000000
+#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR 0x3
+#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x) \
+ in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x))
+#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m)
+#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v) \
+ out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v)
+#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x))
+#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x100
+#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 8
+#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK 0xc0
+#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT 6
+#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK 0x3f
+#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT 0
+
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X1034 + (0x4*(n)))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X1034 + (0x4*(n)))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X1034 + (0x4*(n)))
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn 511
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR 0x00000000
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR 0x1
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n) \
+ in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK)
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \
+ in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask)
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff
+#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0
+
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) ((x) + 0x2000)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) ((x) + 0x2004)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) ((x) + 0x2008)
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x) ((x) + 0x2028)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) ((x) + 0x2048)
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_NOPX_BMSK 0x80000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_NOPX_SHFT 19
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWSLVERR_BMSK 0x40000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWSLVERR_SHFT 18
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWDECERR_BMSK 0x20000
+#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWDECERR_SHFT 17
+#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000
+#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24
+#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000
+#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24
+#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000
+#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24
+#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000
+#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24
+#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000
+#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24
+#endif
diff --git a/drivers/staging/fw-api/hw/peach/v1/wcss_version.h b/drivers/staging/fw-api/hw/peach/v1/wcss_version.h
new file mode 100644
index 0000000000000000000000000000000000000000..a07cff096e51347421c86b8cbc1ad7ee2b65d897
--- /dev/null
+++ b/drivers/staging/fw-api/hw/peach/v1/wcss_version.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#define WCSS_VERSION 2544
diff --git a/drivers/target/target_core_device.c b/drivers/target/target_core_device.c
index 1b381519c16492cec667512e8bb73a4cf5244dfe..a23dcbe79e14ad8612949dcc09c5e9a45ac5b302 100644
--- a/drivers/target/target_core_device.c
+++ b/drivers/target/target_core_device.c
@@ -881,7 +881,6 @@ sector_t target_to_linux_sector(struct se_device *dev, sector_t lb)
EXPORT_SYMBOL(target_to_linux_sector);
struct devices_idr_iter {
- struct config_item *prev_item;
int (*fn)(struct se_device *dev, void *data);
void *data;
};
@@ -891,11 +890,9 @@ static int target_devices_idr_iter(int id, void *p, void *data)
{
struct devices_idr_iter *iter = data;
struct se_device *dev = p;
+ struct config_item *item;
int ret;
- config_item_put(iter->prev_item);
- iter->prev_item = NULL;
-
/*
* We add the device early to the idr, so it can be used
* by backend modules during configuration. We do not want
@@ -905,12 +902,13 @@ static int target_devices_idr_iter(int id, void *p, void *data)
if (!target_dev_configured(dev))
return 0;
- iter->prev_item = config_item_get_unless_zero(&dev->dev_group.cg_item);
- if (!iter->prev_item)
+ item = config_item_get_unless_zero(&dev->dev_group.cg_item);
+ if (!item)
return 0;
mutex_unlock(&device_mutex);
ret = iter->fn(dev, iter->data);
+ config_item_put(item);
mutex_lock(&device_mutex);
return ret;
@@ -933,7 +931,6 @@ int target_for_each_device(int (*fn)(struct se_device *dev, void *data),
mutex_lock(&device_mutex);
ret = idr_for_each(&devices_idr, target_devices_idr_iter, &iter);
mutex_unlock(&device_mutex);
- config_item_put(iter.prev_item);
return ret;
}
diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
index 86c520195afe336ea5dd85808d54ea2ea5ee85b8..2fac047a27139cbab9eb04e419516f1365609e85 100644
--- a/drivers/tty/serial/8250/8250_port.c
+++ b/drivers/tty/serial/8250/8250_port.c
@@ -1910,7 +1910,10 @@ int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
skip_rx = true;
if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
- if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
+ struct irq_data *d;
+
+ d = irq_get_irq_data(port->irq);
+ if (d && irqd_is_wakeup_set(d))
pm_wakeup_event(tport->tty->dev, 0);
if (!up->dma || handle_rx_dma(up, iir))
status = serial8250_rx_chars(up, status);
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index f2625266dc0ed401d962a89b87aeab45bdf0ad61..619b88326c4ee4415a72fdee4611cf950907a23c 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -153,6 +153,10 @@ int usb_device_supports_lpm(struct usb_device *udev)
if (udev->quirks & USB_QUIRK_NO_LPM)
return 0;
+ /* Skip if the device BOS descriptor couldn't be read */
+ if (!udev->bos)
+ return 0;
+
/* USB 2.1 (and greater) devices indicate LPM support through
* their USB 2.0 Extended Capabilities BOS descriptor.
*/
@@ -329,6 +333,10 @@ static void usb_set_lpm_parameters(struct usb_device *udev)
if (!udev->lpm_capable || udev->speed < USB_SPEED_SUPER)
return;
+ /* Skip if the device BOS descriptor couldn't be read */
+ if (!udev->bos)
+ return;
+
hub = usb_hub_to_struct_hub(udev->parent);
/* It doesn't take time to transition the roothub into U0, since it
* doesn't have an upstream link.
@@ -2656,7 +2664,8 @@ int usb_authorize_device(struct usb_device *usb_dev)
}
/*
- * Return 1 if port speed is SuperSpeedPlus, 0 otherwise
+ * Return 1 if port speed is SuperSpeedPlus, 0 otherwise or if the
+ * capability couldn't be checked.
* check it from the link protocol field of the current speed ID attribute.
* current speed ID is got from ext port status request. Sublink speed attribute
* table is returned with the hub BOS SSP device capability descriptor
@@ -2666,8 +2675,12 @@ static int port_speed_is_ssp(struct usb_device *hdev, int speed_id)
int ssa_count;
u32 ss_attr;
int i;
- struct usb_ssp_cap_descriptor *ssp_cap = hdev->bos->ssp_cap;
+ struct usb_ssp_cap_descriptor *ssp_cap;
+ if (!hdev->bos)
+ return 0;
+
+ ssp_cap = hdev->bos->ssp_cap;
if (!ssp_cap)
return 0;
@@ -4072,8 +4085,15 @@ static void usb_enable_link_state(struct usb_hcd *hcd, struct usb_device *udev,
enum usb3_link_state state)
{
int timeout, ret;
- __u8 u1_mel = udev->bos->ss_cap->bU1devExitLat;
- __le16 u2_mel = udev->bos->ss_cap->bU2DevExitLat;
+ __u8 u1_mel;
+ __le16 u2_mel;
+
+ /* Skip if the device BOS descriptor couldn't be read */
+ if (!udev->bos)
+ return;
+
+ u1_mel = udev->bos->ss_cap->bU1devExitLat;
+ u2_mel = udev->bos->ss_cap->bU2DevExitLat;
/* If the device says it doesn't have *any* exit latency to come out of
* U1 or U2, it's probably lying. Assume it doesn't implement that link
diff --git a/drivers/usb/core/hub.h b/drivers/usb/core/hub.h
index df3aa0b69188fb9b4837d6f1e602532b38b0a4d8..d1845e5ff7006d09d25f329dead619b8f0fbe472 100644
--- a/drivers/usb/core/hub.h
+++ b/drivers/usb/core/hub.h
@@ -139,7 +139,7 @@ static inline int hub_is_superspeedplus(struct usb_device *hdev)
{
return (hdev->descriptor.bDeviceProtocol == USB_HUB_PR_SS &&
le16_to_cpu(hdev->descriptor.bcdUSB) >= 0x0310 &&
- hdev->bos->ssp_cap);
+ hdev->bos && hdev->bos->ssp_cap);
}
static inline unsigned hub_power_on_good_delay(struct usb_hub *hub)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index bac4573b872747b82f33035aeae77a0c46c69cb3..a46eb14416d68675363fdee6327068cd0c578274 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -241,9 +241,46 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
* XHCI driver will reset the host block. If dwc3 was configured for
* host-only mode or current role is host, then we can return early.
*/
- if (dwc->dr_mode == USB_DR_MODE_HOST || dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
+ if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
return 0;
+ /*
+ * If the dr_mode is host and the dwc->current_dr_role is not the
+ * corresponding DWC3_GCTL_PRTCAP_HOST, then the dwc3_core_init_mode
+ * isn't executed yet. Ensure the phy is ready before the controller
+ * updates the GCTL.PRTCAPDIR or other settings by soft-resetting
+ * the phy.
+ *
+ * Note: GUSB3PIPECTL[n] and GUSB2PHYCFG[n] are port settings where n
+ * is port index. If this is a multiport host, then we need to reset
+ * all active ports.
+ */
+ if (dwc->dr_mode == USB_DR_MODE_HOST) {
+ u32 usb3_port;
+ u32 usb2_port;
+
+ usb3_port = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
+ usb3_port |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
+ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);
+
+ usb2_port = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
+ usb2_port |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);
+
+ /* Small delay for phy reset assertion */
+ usleep_range(1000, 2000);
+
+ usb3_port &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
+ dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port);
+
+ usb2_port &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
+ dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port);
+
+ /* Wait for clock synchronization */
+ msleep(50);
+ return 0;
+ }
+
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg |= DWC3_DCTL_CSFTRST;
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
index cd8126d286763b107232a69358588f580426d75a..3f0e42d76983aa17c91e6e05659702a6f220b5e8 100644
--- a/drivers/usb/dwc3/dwc3-msm.c
+++ b/drivers/usb/dwc3/dwc3-msm.c
@@ -2006,6 +2006,24 @@ static void dwc3_gsi_event_buf_alloc(struct dwc3 *dwc)
}
}
+static void dwc3_msm_modify_pipectl(struct dwc3 *dwc, bool set)
+{
+ struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent);
+ u32 reg;
+
+ reg = dwc3_msm_read_reg(mdwc->base, DWC3_GUSB3PIPECTL(0));
+
+ if (set) {
+ if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
+ (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
+ reg |= DWC3_GUSB3PIPECTL_SUSPHY;
+ } else {
+ reg &= ~(DWC3_GUSB3PIPECTL_SUSPHY);
+ }
+
+ dwc3_msm_write_reg(mdwc->base, DWC3_GUSB3PIPECTL(0), reg);
+}
+
static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event,
unsigned int value)
{
@@ -2071,6 +2089,9 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event,
break;
case DWC3_CONTROLLER_CONNDONE_EVENT:
dev_dbg(mdwc->dev, "DWC3_CONTROLLER_CONNDONE_EVENT received\n");
+
+ dwc3_msm_modify_pipectl(dwc, true);
+
/*
* Add power event if the dbm indicates coming out of L1 by
* interrupt
@@ -2195,6 +2216,13 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event,
break;
case DWC3_CONTROLLER_NOTIFY_CLEAR_DB:
dev_dbg(mdwc->dev, "DWC3_CONTROLLER_NOTIFY_CLEAR_DB\n");
+
+ /*
+ * Clear the susphy bit here to ensure it is not set during
+ * the course of controller initialisation process.
+ */
+ dwc3_msm_modify_pipectl(dwc, false);
+
if (!mdwc->gsi_ev_buff)
break;
@@ -2267,15 +2295,6 @@ static void dwc3_msm_power_collapse_por(struct dwc3_msm *mdwc)
dev_err(mdwc->dev, "%s: dwc3_core init failed (%d)\n",
__func__, ret);
- /* Get initial P3 status and enable IN_P3 event */
- if (dwc3_is_usb31(dwc))
- val = dwc3_msm_read_reg_field(mdwc->base,
- DWC31_LINK_GDBGLTSSM,
- DWC3_GDBGLTSSM_LINKSTATE_MASK);
- else
- val = dwc3_msm_read_reg_field(mdwc->base,
- DWC3_GDBGLTSSM, DWC3_GDBGLTSSM_LINKSTATE_MASK);
- atomic_set(&mdwc->in_p3, val == DWC3_LINK_STATE_U3);
dwc3_msm_write_reg_field(mdwc->base, PWR_EVNT_IRQ_MASK_REG,
PWR_EVNT_POWERDOWN_IN_P3_MASK, 1);
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index aa4e95f45a8a40fd35b365c6f3d2201858b43791..8e78c4f4565803b11c180a6cd67adb858d792fb5 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -2499,8 +2499,11 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
/* prevent pending bh to run later */
flush_work(&dwc->bh_work);
- if (is_on)
- dwc3_device_core_soft_reset(dwc);
+ if (is_on) {
+ ret = dwc3_device_core_soft_reset(dwc);
+ if (ret != 0)
+ goto done;
+ }
spin_lock_irqsave(&dwc->lock, flags);
if (dwc->ep0state != EP0_SETUP_PHASE)
@@ -2529,6 +2532,7 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
}
enable_irq(dwc->irq);
+done:
pm_runtime_mark_last_busy(dwc->dev);
pm_runtime_put_autosuspend(dwc->dev);
dbg_event(0xFF, "Pullup put",
diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c
index c27a39fdcc4818778fb99e59cb02347f9fa2f9eb..a7c34ec7ffa0ac3a788b67d7179c28eb57543f39 100644
--- a/drivers/usb/gadget/function/f_ncm.c
+++ b/drivers/usb/gadget/function/f_ncm.c
@@ -1180,7 +1180,8 @@ static int ncm_unwrap_ntb(struct gether *port,
struct sk_buff_head *list)
{
struct f_ncm *ncm = func_to_ncm(&port->func);
- __le16 *tmp = (void *) skb->data;
+ unsigned char *ntb_ptr = skb->data;
+ __le16 *tmp;
unsigned index, index2;
int ndp_index;
unsigned dg_len, dg_len2;
@@ -1193,6 +1194,10 @@ static int ncm_unwrap_ntb(struct gether *port,
const struct ndp_parser_opts *opts = ncm->parser_opts;
unsigned crc_len = ncm->is_crc ? sizeof(uint32_t) : 0;
int dgram_counter;
+ int to_process = skb->len;
+
+parse_ntb:
+ tmp = (__le16 *)ntb_ptr;
/* dwSignature */
if (get_unaligned_le32(tmp) != opts->nth_sign) {
@@ -1239,7 +1244,7 @@ static int ncm_unwrap_ntb(struct gether *port,
* walk through NDP
* dwSignature
*/
- tmp = (void *)(skb->data + ndp_index);
+ tmp = (__le16 *)(ntb_ptr + ndp_index);
if (get_unaligned_le32(tmp) != ncm->ndp_sign) {
INFO(port->func.config->cdev, "Wrong NDP SIGN\n");
goto err;
@@ -1296,11 +1301,11 @@ static int ncm_unwrap_ntb(struct gether *port,
if (ncm->is_crc) {
uint32_t crc, crc2;
- crc = get_unaligned_le32(skb->data +
+ crc = get_unaligned_le32(ntb_ptr +
index + dg_len -
crc_len);
crc2 = ~crc32_le(~0,
- skb->data + index,
+ ntb_ptr + index,
dg_len - crc_len);
if (crc != crc2) {
INFO(port->func.config->cdev,
@@ -1327,7 +1332,7 @@ static int ncm_unwrap_ntb(struct gether *port,
dg_len - crc_len);
if (skb2 == NULL)
goto err;
- skb_put_data(skb2, skb->data + index,
+ skb_put_data(skb2, ntb_ptr + index,
dg_len - crc_len);
skb_queue_tail(list, skb2);
@@ -1340,10 +1345,17 @@ static int ncm_unwrap_ntb(struct gether *port,
} while (ndp_len > 2 * (opts->dgram_item_len * 2));
} while (ndp_index);
- dev_consume_skb_any(skb);
-
VDBG(port->func.config->cdev,
"Parsed NTB with %d frames\n", dgram_counter);
+
+ to_process -= block_len;
+ if (to_process != 0) {
+ ntb_ptr = (unsigned char *)(ntb_ptr + block_len);
+ goto parse_ntb;
+ }
+
+ dev_consume_skb_any(skb);
+
return 0;
err:
skb_queue_purge(list);
diff --git a/drivers/usb/gadget/udc/udc-xilinx.c b/drivers/usb/gadget/udc/udc-xilinx.c
index 72f1bc6a680e37d7f29431325550f1c3fa29e7ff..5b73a2aecf7ae07fc7d19f9eb548b8db6148e2ca 100644
--- a/drivers/usb/gadget/udc/udc-xilinx.c
+++ b/drivers/usb/gadget/udc/udc-xilinx.c
@@ -496,11 +496,13 @@ static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req,
/* Get the Buffer address and copy the transmit data.*/
eprambase = (u32 __force *)(udc->addr + ep->rambase);
if (ep->is_in) {
- memcpy(eprambase, bufferptr, bytestosend);
+ memcpy_toio((void __iomem *)eprambase, bufferptr,
+ bytestosend);
udc->write_fn(udc->addr, ep->offset +
XUSB_EP_BUF0COUNT_OFFSET, bufferlen);
} else {
- memcpy(bufferptr, eprambase, bytestosend);
+ memcpy_toio((void __iomem *)bufferptr, eprambase,
+ bytestosend);
}
/*
* Enable the buffer for transmission.
@@ -514,11 +516,13 @@ static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req,
eprambase = (u32 __force *)(udc->addr + ep->rambase +
ep->ep_usb.maxpacket);
if (ep->is_in) {
- memcpy(eprambase, bufferptr, bytestosend);
+ memcpy_toio((void __iomem *)eprambase, bufferptr,
+ bytestosend);
udc->write_fn(udc->addr, ep->offset +
XUSB_EP_BUF1COUNT_OFFSET, bufferlen);
} else {
- memcpy(bufferptr, eprambase, bytestosend);
+ memcpy_toio((void __iomem *)bufferptr, eprambase,
+ bytestosend);
}
/*
* Enable the buffer for transmission.
@@ -1020,7 +1024,7 @@ static int __xudc_ep0_queue(struct xusb_ep *ep0, struct xusb_req *req)
udc->addr);
length = req->usb_req.actual = min_t(u32, length,
EP0_MAX_PACKET);
- memcpy(corebuf, req->usb_req.buf, length);
+ memcpy_toio((void __iomem *)corebuf, req->usb_req.buf, length);
udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, length);
udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
} else {
@@ -1746,7 +1750,7 @@ static void xudc_handle_setup(struct xusb_udc *udc)
/* Load up the chapter 9 command buffer.*/
ep0rambase = (u32 __force *) (udc->addr + XUSB_SETUP_PKT_ADDR_OFFSET);
- memcpy(&setup, ep0rambase, 8);
+ memcpy_toio((void __iomem *)&setup, ep0rambase, 8);
udc->setup = setup;
udc->setup.wValue = cpu_to_le16(setup.wValue);
@@ -1833,7 +1837,7 @@ static void xudc_ep0_out(struct xusb_udc *udc)
(ep0->rambase << 2));
buffer = req->usb_req.buf + req->usb_req.actual;
req->usb_req.actual = req->usb_req.actual + bytes_to_rx;
- memcpy(buffer, ep0rambase, bytes_to_rx);
+ memcpy_toio((void __iomem *)buffer, ep0rambase, bytes_to_rx);
if (req->usb_req.length == req->usb_req.actual) {
/* Data transfer completed get ready for Status stage */
@@ -1909,7 +1913,7 @@ static void xudc_ep0_in(struct xusb_udc *udc)
(ep0->rambase << 2));
buffer = req->usb_req.buf + req->usb_req.actual;
req->usb_req.actual = req->usb_req.actual + length;
- memcpy(ep0rambase, buffer, length);
+ memcpy_toio((void __iomem *)ep0rambase, buffer, length);
}
udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, count);
udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 8371e9b9a822cbddd7983c2e7e1bc604e13ec249..46b0d8a304535da463b92f513cf2d58f902562cd 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -689,7 +689,7 @@ static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
struct xhci_ring *ring, struct xhci_td *td)
{
- struct device *dev = xhci_to_hcd(xhci)->self.controller;
+ struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
struct xhci_segment *seg = td->bounce_seg;
struct urb *urb = td->urb;
size_t len;
@@ -3199,7 +3199,7 @@ static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
u32 *trb_buff_len, struct xhci_segment *seg)
{
- struct device *dev = xhci_to_hcd(xhci)->self.controller;
+ struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
unsigned int unalign;
unsigned int max_pkt;
u32 new_buff_len;
diff --git a/drivers/usb/musb/musb_debugfs.c b/drivers/usb/musb/musb_debugfs.c
index 0c6204add616167a2be0e139823c0c82aa2b6a59..1efd5ce48f893ce4843394251afaa89812fda133 100644
--- a/drivers/usb/musb/musb_debugfs.c
+++ b/drivers/usb/musb/musb_debugfs.c
@@ -39,7 +39,7 @@ static const struct musb_register_map musb_regmap[] = {
{ "IntrUsbE", MUSB_INTRUSBE, 8 },
{ "DevCtl", MUSB_DEVCTL, 8 },
{ "VControl", 0x68, 32 },
- { "HWVers", 0x69, 16 },
+ { "HWVers", MUSB_HWVERS, 16 },
{ "LinkInfo", MUSB_LINKINFO, 8 },
{ "VPLen", MUSB_VPLEN, 8 },
{ "HS_EOF1", MUSB_HS_EOF1, 8 },
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index a1c4fc56d429dbeb5bbe4f0d48afda92b250f244..1e50efc5869c1a1d9c4c14acbe5a2e2886879871 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -321,10 +321,16 @@ static void musb_advance_schedule(struct musb *musb, struct urb *urb,
musb_giveback(musb, urb, status);
qh->is_ready = ready;
+ /*
+ * musb->lock had been unlocked in musb_giveback, so qh may
+ * be freed, need to get it again
+ */
+ qh = musb_ep_get_qh(hw_ep, is_in);
+
/* reclaim resources (and bandwidth) ASAP; deschedule it, and
* invalidate qh as soon as list_empty(&hep->urb_list)
*/
- if (list_empty(&qh->hep->urb_list)) {
+ if (qh && list_empty(&qh->hep->urb_list)) {
struct list_head *head;
struct dma_controller *dma = musb->dma_controller;
@@ -2398,6 +2404,7 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
* and its URB list has emptied, recycle this qh.
*/
if (ready && list_empty(&qh->hep->urb_list)) {
+ musb_ep_set_qh(qh->hw_ep, is_in, NULL);
qh->hep->hcpriv = NULL;
list_del(&qh->ring);
kfree(qh);
diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index a4787fcf6ba9c664760aeb727fa00af2943cbd63..7fab049e790ff04ca43b7eb3b309e96a3899e4cf 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -203,6 +203,9 @@ static void option_instat_callback(struct urb *urb);
#define DELL_PRODUCT_5829E_ESIM 0x81e4
#define DELL_PRODUCT_5829E 0x81e6
+#define DELL_PRODUCT_FM101R 0x8213
+#define DELL_PRODUCT_FM101R_ESIM 0x8215
+
#define KYOCERA_VENDOR_ID 0x0c88
#define KYOCERA_PRODUCT_KPC650 0x17da
#define KYOCERA_PRODUCT_KPC680 0x180a
@@ -1108,6 +1111,8 @@ static const struct usb_device_id option_ids[] = {
.driver_info = RSVD(0) | RSVD(6) },
{ USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5829E_ESIM),
.driver_info = RSVD(0) | RSVD(6) },
+ { USB_DEVICE_INTERFACE_CLASS(DELL_VENDOR_ID, DELL_PRODUCT_FM101R, 0xff) },
+ { USB_DEVICE_INTERFACE_CLASS(DELL_VENDOR_ID, DELL_PRODUCT_FM101R_ESIM, 0xff) },
{ USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_E100A) }, /* ADU-E100, ADU-310 */
{ USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_500A) },
{ USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_620UW) },
@@ -1290,6 +1295,7 @@ static const struct usb_device_id option_ids[] = {
.driver_info = NCTRL(0) | RSVD(3) },
{ USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1033, 0xff), /* Telit LE910C1-EUX (ECM) */
.driver_info = NCTRL(0) },
+ { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1035, 0xff) }, /* Telit LE910C4-WWX (ECM) */
{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_LE922_USBCFG0),
.driver_info = RSVD(0) | RSVD(1) | NCTRL(2) | RSVD(3) },
{ USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_LE922_USBCFG1),
@@ -2262,6 +2268,7 @@ static const struct usb_device_id option_ids[] = {
{ USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1406, 0xff) }, /* GosunCn GM500 ECM/NCM */
{ USB_DEVICE_AND_INTERFACE_INFO(OPPO_VENDOR_ID, OPPO_PRODUCT_R11, 0xff, 0xff, 0x30) },
{ USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0xff, 0x30) },
+ { USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0xff, 0x40) },
{ USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0, 0) },
{ USB_DEVICE_AND_INTERFACE_INFO(UNISOC_VENDOR_ID, TOZED_PRODUCT_LT70C, 0xff, 0, 0) },
{ } /* Terminating entry */
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index 06ecf8e52c25e179845b42a3aab89178d36bb219..9ccb6da2778307e9c0e009669b9110241af3eb1f 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -2085,7 +2085,7 @@ config FB_COBALT
config FB_SH7760
bool "SH7760/SH7763/SH7720/SH7721 LCDC support"
- depends on FB && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763 \
+ depends on FB=y && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763 \
|| CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721)
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c
index 347f0389b0899d4183021254203e0a0938600267..5ec52032117a7cf093bae7ca305293b30e6a5559 100644
--- a/drivers/watchdog/iTCO_wdt.c
+++ b/drivers/watchdog/iTCO_wdt.c
@@ -401,6 +401,20 @@ static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
return time_left;
}
+/* Returns true if the watchdog was running */
+static bool iTCO_wdt_set_running(struct iTCO_wdt_private *p)
+{
+ u16 val;
+
+ /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled */
+ val = inw(TCO1_CNT(p));
+ if (!(val & BIT(11))) {
+ set_bit(WDOG_HW_RUNNING, &p->wddev.status);
+ return true;
+ }
+ return false;
+}
+
/*
* Kernel Interfaces
*/
@@ -476,9 +490,6 @@ static int iTCO_wdt_probe(struct platform_device *pdev)
return -ENODEV; /* Cannot reset NO_REBOOT bit */
}
- /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
- p->update_no_reboot_bit(p->no_reboot_priv, true);
-
/* The TCO logic uses the TCO_EN bit in the SMI_EN register */
if (!devm_request_region(dev, p->smi_res->start,
resource_size(p->smi_res),
@@ -537,8 +548,13 @@ static int iTCO_wdt_probe(struct platform_device *pdev)
watchdog_set_drvdata(&p->wddev, p);
platform_set_drvdata(pdev, p);
- /* Make sure the watchdog is not running */
- iTCO_wdt_stop(&p->wddev);
+ if (!iTCO_wdt_set_running(p)) {
+ /*
+ * If the watchdog was not running set NO_REBOOT now to
+ * prevent later reboots.
+ */
+ p->update_no_reboot_bit(p->no_reboot_priv, true);
+ }
/* Check that the heartbeat value is within it's range;
if not reset to the default */
diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c
index b6b3131cb079f9e23ef4e1a32c55be187a679cab..960666aba12bf2ceb6e028759fd93e8d9504e95a 100644
--- a/drivers/xen/events/events_base.c
+++ b/drivers/xen/events/events_base.c
@@ -82,23 +82,13 @@ const struct evtchn_ops *evtchn_ops;
*/
static DEFINE_MUTEX(irq_mapping_update_lock);
-/*
- * Lock protecting event handling loop against removing event channels.
- * Adding of event channels is no issue as the associated IRQ becomes active
- * only after everything is setup (before request_[threaded_]irq() the handler
- * can't be entered for an event, as the event channel will be unmasked only
- * then).
- */
-static DEFINE_RWLOCK(evtchn_rwlock);
-
/*
* Lock hierarchy:
*
* irq_mapping_update_lock
- * evtchn_rwlock
- * IRQ-desc lock
- * percpu eoi_list_lock
- * irq_info->lock
+ * IRQ-desc lock
+ * percpu eoi_list_lock
+ * irq_info->lock
*/
static LIST_HEAD(xen_irq_list_head);
@@ -213,6 +203,22 @@ static void set_info_for_irq(unsigned int irq, struct irq_info *info)
irq_set_chip_data(irq, info);
}
+static void delayed_free_irq(struct work_struct *work)
+{
+ struct irq_info *info = container_of(to_rcu_work(work), struct irq_info,
+ rwork);
+ unsigned int irq = info->irq;
+
+ /* Remove the info pointer only now, with no potential users left. */
+ set_info_for_irq(irq, NULL);
+
+ kfree(info);
+
+ /* Legacy IRQ descriptors are managed by the arch. */
+ if (irq >= nr_legacy_irqs())
+ irq_free_desc(irq);
+}
+
/* Constructors for packed IRQ information. */
static int xen_irq_info_common_setup(struct irq_info *info,
unsigned irq,
@@ -547,33 +553,36 @@ static void xen_irq_lateeoi_worker(struct work_struct *work)
eoi = container_of(to_delayed_work(work), struct lateeoi_work, delayed);
- read_lock_irqsave(&evtchn_rwlock, flags);
+ rcu_read_lock();
while (true) {
- spin_lock(&eoi->eoi_list_lock);
+ spin_lock_irqsave(&eoi->eoi_list_lock, flags);
info = list_first_entry_or_null(&eoi->eoi_list, struct irq_info,
eoi_list);
- if (info == NULL || now < info->eoi_time) {
- spin_unlock(&eoi->eoi_list_lock);
+ if (info == NULL)
+ break;
+
+ if (now < info->eoi_time) {
+ mod_delayed_work_on(info->eoi_cpu, system_wq,
+ &eoi->delayed,
+ info->eoi_time - now);
break;
}
list_del_init(&info->eoi_list);
- spin_unlock(&eoi->eoi_list_lock);
+ spin_unlock_irqrestore(&eoi->eoi_list_lock, flags);
info->eoi_time = 0;
xen_irq_lateeoi_locked(info, false);
}
- if (info)
- mod_delayed_work_on(info->eoi_cpu, system_wq,
- &eoi->delayed, info->eoi_time - now);
+ spin_unlock_irqrestore(&eoi->eoi_list_lock, flags);
- read_unlock_irqrestore(&evtchn_rwlock, flags);
+ rcu_read_unlock();
}
static void xen_cpu_init_eoi(unsigned int cpu)
@@ -588,16 +597,15 @@ static void xen_cpu_init_eoi(unsigned int cpu)
void xen_irq_lateeoi(unsigned int irq, unsigned int eoi_flags)
{
struct irq_info *info;
- unsigned long flags;
- read_lock_irqsave(&evtchn_rwlock, flags);
+ rcu_read_lock();
info = info_for_irq(irq);
if (info)
xen_irq_lateeoi_locked(info, eoi_flags & XEN_EOI_FLAG_SPURIOUS);
- read_unlock_irqrestore(&evtchn_rwlock, flags);
+ rcu_read_unlock();
}
EXPORT_SYMBOL_GPL(xen_irq_lateeoi);
@@ -616,6 +624,7 @@ static void xen_irq_init(unsigned irq)
info->type = IRQT_UNBOUND;
info->refcnt = -1;
+ INIT_RCU_WORK(&info->rwork, delayed_free_irq);
set_info_for_irq(irq, info);
@@ -668,31 +677,18 @@ static int __must_check xen_allocate_irq_gsi(unsigned gsi)
static void xen_free_irq(unsigned irq)
{
struct irq_info *info = info_for_irq(irq);
- unsigned long flags;
if (WARN_ON(!info))
return;
- write_lock_irqsave(&evtchn_rwlock, flags);
-
if (!list_empty(&info->eoi_list))
lateeoi_list_del(info);
list_del(&info->list);
- set_info_for_irq(irq, NULL);
-
WARN_ON(info->refcnt > 0);
- write_unlock_irqrestore(&evtchn_rwlock, flags);
-
- kfree(info);
-
- /* Legacy IRQ descriptors are managed by the arch. */
- if (irq < nr_legacy_irqs())
- return;
-
- irq_free_desc(irq);
+ queue_rcu_work(system_wq, &info->rwork);
}
static void xen_evtchn_close(unsigned int port)
@@ -1603,7 +1599,14 @@ static void __xen_evtchn_do_upcall(void)
unsigned count;
struct evtchn_loop_ctrl ctrl = { 0 };
- read_lock(&evtchn_rwlock);
+ /*
+ * When closing an event channel the associated IRQ must not be freed
+ * until all cpus have left the event handling loop. This is ensured
+ * by taking the rcu_read_lock() while handling events, as freeing of
+ * the IRQ is handled via queue_rcu_work() _after_ closing the event
+ * channel.
+ */
+ rcu_read_lock();
do {
vcpu_info->evtchn_upcall_pending = 0;
@@ -1620,7 +1623,7 @@ static void __xen_evtchn_do_upcall(void)
} while (count != 1 || vcpu_info->evtchn_upcall_pending);
out:
- read_unlock(&evtchn_rwlock);
+ rcu_read_unlock();
/*
* Increment irq_epoch only now to defer EOIs only for
diff --git a/drivers/xen/events/events_internal.h b/drivers/xen/events/events_internal.h
index cc37b711491cef0838a56be7de378d5f2d87dc2f..1d9d9e6f1dee19cba6a3499834b36460a465fa46 100644
--- a/drivers/xen/events/events_internal.h
+++ b/drivers/xen/events/events_internal.h
@@ -8,6 +8,7 @@
*/
#ifndef __EVENTS_INTERNAL_H__
#define __EVENTS_INTERNAL_H__
+#include
/* Interrupt types. */
enum xen_irq_type {
@@ -33,6 +34,7 @@ enum xen_irq_type {
struct irq_info {
struct list_head list;
struct list_head eoi_list;
+ struct rcu_work rwork;
short refcnt;
short spurious_cnt;
short type; /* type */
diff --git a/fs/binfmt_elf_fdpic.c b/fs/binfmt_elf_fdpic.c
index 64d0b838085d37d7b1d48198ab6a301354fd06c9..a7c2efcd0a4a31751b90bf0263dc359c2f2113f8 100644
--- a/fs/binfmt_elf_fdpic.c
+++ b/fs/binfmt_elf_fdpic.c
@@ -349,10 +349,9 @@ static int load_elf_fdpic_binary(struct linux_binprm *bprm)
/* there's now no turning back... the old userspace image is dead,
* defunct, deceased, etc.
*/
+ SET_PERSONALITY(exec_params.hdr);
if (elf_check_fdpic(&exec_params.hdr))
- set_personality(PER_LINUX_FDPIC);
- else
- set_personality(PER_LINUX);
+ current->personality |= PER_LINUX_FDPIC;
if (elf_read_implies_exec(&exec_params.hdr, executable_stack))
current->personality |= READ_IMPLIES_EXEC;
diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c
index bb05b0a82c8ba7ea5b233c2c8e3f6b0e7dfa70ae..902ab00bfd7ab931602cbf1864133469f4abefee 100644
--- a/fs/btrfs/extent-tree.c
+++ b/fs/btrfs/extent-tree.c
@@ -2327,12 +2327,12 @@ static int run_delayed_tree_ref(struct btrfs_trans_handle *trans,
parent = ref->parent;
ref_root = ref->root;
- if (node->ref_mod != 1) {
+ if (unlikely(node->ref_mod != 1)) {
btrfs_err(trans->fs_info,
- "btree block(%llu) has %d references rather than 1: action %d ref_root %llu parent %llu",
+ "btree block %llu has %d references rather than 1: action %d ref_root %llu parent %llu",
node->bytenr, node->ref_mod, node->action, ref_root,
parent);
- return -EIO;
+ return -EUCLEAN;
}
if (node->action == BTRFS_ADD_DELAYED_REF && insert_reserved) {
BUG_ON(!extent_op || !extent_op->update_flags);
diff --git a/fs/btrfs/ioctl.c b/fs/btrfs/ioctl.c
index f009d585e72f825cda7b605a6fba986fe51fce3d..e3f18edc1afee5c6e9d85d0bf485ccdadf63c181 100644
--- a/fs/btrfs/ioctl.c
+++ b/fs/btrfs/ioctl.c
@@ -4526,7 +4526,7 @@ static void get_block_group_info(struct list_head *groups_list,
static long btrfs_ioctl_space_info(struct btrfs_fs_info *fs_info,
void __user *arg)
{
- struct btrfs_ioctl_space_args space_args;
+ struct btrfs_ioctl_space_args space_args = { 0 };
struct btrfs_ioctl_space_info space;
struct btrfs_ioctl_space_info *dest;
struct btrfs_ioctl_space_info *dest_orig;
@@ -5884,7 +5884,7 @@ static int _btrfs_ioctl_send(struct file *file, void __user *argp, bool compat)
if (compat) {
#if defined(CONFIG_64BIT) && defined(CONFIG_COMPAT)
- struct btrfs_ioctl_send_args_32 args32;
+ struct btrfs_ioctl_send_args_32 args32 = { 0 };
ret = copy_from_user(&args32, argp, sizeof(args32));
if (ret)
diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c
index 521f6c2091ad15e20e18fdac0a66bd2552d56f44..a595439518519a57095ee138e60a9ea903a9895e 100644
--- a/fs/btrfs/super.c
+++ b/fs/btrfs/super.c
@@ -2196,7 +2196,7 @@ static int btrfs_statfs(struct dentry *dentry, struct kstatfs *buf)
* calculated f_bavail.
*/
if (!mixed && block_rsv->space_info->full &&
- total_free_meta - thresh < block_rsv->size)
+ (total_free_meta < thresh || total_free_meta - thresh < block_rsv->size))
buf->f_bavail = 0;
buf->f_type = BTRFS_SUPER_MAGIC;
diff --git a/fs/btrfs/tree-log.c b/fs/btrfs/tree-log.c
index 0fe32c567ed74c1f8bd6a69f786081e3d8781962..23ec766eeb0a376629185e43094a03f9d25c0eb1 100644
--- a/fs/btrfs/tree-log.c
+++ b/fs/btrfs/tree-log.c
@@ -4236,7 +4236,7 @@ static int btrfs_log_prealloc_extents(struct btrfs_trans_handle *trans,
struct extent_buffer *leaf;
int slot;
int ins_nr = 0;
- int start_slot;
+ int start_slot = 0;
int ret;
if (!(inode->flags & BTRFS_INODE_PREALLOC))
diff --git a/fs/ceph/inode.c b/fs/ceph/inode.c
index 5f041fede7aa93075926c2c90e5e93f2e536f58e..d6f181e3c1acd0446edcc977293ea14c4a6077aa 100644
--- a/fs/ceph/inode.c
+++ b/fs/ceph/inode.c
@@ -631,9 +631,7 @@ int ceph_fill_file_size(struct inode *inode, int issued,
ci->i_truncate_seq = truncate_seq;
/* the MDS should have revoked these caps */
- WARN_ON_ONCE(issued & (CEPH_CAP_FILE_EXCL |
- CEPH_CAP_FILE_RD |
- CEPH_CAP_FILE_WR |
+ WARN_ON_ONCE(issued & (CEPH_CAP_FILE_RD |
CEPH_CAP_FILE_LAZYIO));
/*
* If we hold relevant caps, or in the case where we're
diff --git a/fs/ext4/ext4.h b/fs/ext4/ext4.h
index 4f38a2b84344ffd8d673e30e573c0ea3ba78cb10..57abebbc7308676a2dc74393a1497f407731d119 100644
--- a/fs/ext4/ext4.h
+++ b/fs/ext4/ext4.h
@@ -1507,7 +1507,7 @@ struct ext4_sb_info {
struct task_struct *s_mmp_tsk;
/* record the last minlen when FITRIM is called. */
- atomic_t s_last_trim_minblks;
+ unsigned long s_last_trim_minblks;
/* Reference to checksum algorithm driver via cryptoapi */
struct crypto_shash *s_chksum_driver;
diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c
index 7692c12b85285eade0516e9d30061b45ebe180c6..fb2f255c48e814e86ac156462714cd18b0b8853c 100644
--- a/fs/ext4/mballoc.c
+++ b/fs/ext4/mballoc.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include
#ifdef CONFIG_EXT4_DEBUG
@@ -5149,19 +5150,19 @@ int ext4_group_add_blocks(handle_t *handle, struct super_block *sb,
* @sb: super block for the file system
* @start: starting block of the free extent in the alloc. group
* @count: number of blocks to TRIM
- * @group: alloc. group we are working with
* @e4b: ext4 buddy for the group
*
* Trim "count" blocks starting at "start" in the "group". To assure that no
* one will allocate those blocks, mark it as used in buddy bitmap. This must
* be called with under the group lock.
*/
-static int ext4_trim_extent(struct super_block *sb, int start, int count,
- ext4_group_t group, struct ext4_buddy *e4b)
+static int ext4_trim_extent(struct super_block *sb,
+ int start, int count, struct ext4_buddy *e4b)
__releases(bitlock)
__acquires(bitlock)
{
struct ext4_free_extent ex;
+ ext4_group_t group = e4b->bd_group;
int ret = 0;
trace_ext4_trim_extent(sb, group, start, count);
@@ -5184,6 +5185,71 @@ __acquires(bitlock)
return ret;
}
+static ext4_grpblk_t ext4_last_grp_cluster(struct super_block *sb,
+ ext4_group_t grp)
+{
+ if (grp < ext4_get_groups_count(sb))
+ return EXT4_CLUSTERS_PER_GROUP(sb) - 1;
+ return (ext4_blocks_count(EXT4_SB(sb)->s_es) -
+ ext4_group_first_block_no(sb, grp) - 1) >>
+ EXT4_CLUSTER_BITS(sb);
+}
+
+static bool ext4_trim_interrupted(void)
+{
+ return fatal_signal_pending(current) || freezing(current);
+}
+
+static int ext4_try_to_trim_range(struct super_block *sb,
+ struct ext4_buddy *e4b, ext4_grpblk_t start,
+ ext4_grpblk_t max, ext4_grpblk_t minblocks)
+{
+ ext4_grpblk_t next, count, free_count;
+ bool set_trimmed = false;
+ void *bitmap;
+
+ bitmap = e4b->bd_bitmap;
+ if (start == 0 && max >= ext4_last_grp_cluster(sb, e4b->bd_group))
+ set_trimmed = true;
+ start = max(e4b->bd_info->bb_first_free, start);
+ count = 0;
+ free_count = 0;
+
+ while (start <= max) {
+ start = mb_find_next_zero_bit(bitmap, max + 1, start);
+ if (start > max)
+ break;
+ next = mb_find_next_bit(bitmap, max + 1, start);
+
+ if ((next - start) >= minblocks) {
+ int ret = ext4_trim_extent(sb, start, next - start, e4b);
+
+ if (ret && ret != -EOPNOTSUPP)
+ return count;
+ count += next - start;
+ }
+ free_count += next - start;
+ start = next + 1;
+
+ if (ext4_trim_interrupted())
+ return count;
+
+ if (need_resched()) {
+ ext4_unlock_group(sb, e4b->bd_group);
+ cond_resched();
+ ext4_lock_group(sb, e4b->bd_group);
+ }
+
+ if ((e4b->bd_info->bb_free - free_count) < minblocks)
+ break;
+ }
+
+ if (set_trimmed)
+ EXT4_MB_GRP_SET_TRIMMED(e4b->bd_info);
+
+ return count;
+}
+
/**
* ext4_trim_all_free -- function to trim all free space in alloc. group
* @sb: super block for file system
@@ -5207,10 +5273,8 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group,
ext4_grpblk_t start, ext4_grpblk_t max,
ext4_grpblk_t minblocks)
{
- void *bitmap;
- ext4_grpblk_t next, count = 0, free_count = 0;
struct ext4_buddy e4b;
- int ret = 0;
+ int ret;
trace_ext4_trim_all_free(sb, group, start, max);
@@ -5220,58 +5284,20 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group,
ret, group);
return ret;
}
- bitmap = e4b.bd_bitmap;
ext4_lock_group(sb, group);
- if (EXT4_MB_GRP_WAS_TRIMMED(e4b.bd_info) &&
- minblocks >= atomic_read(&EXT4_SB(sb)->s_last_trim_minblks))
- goto out;
-
- start = (e4b.bd_info->bb_first_free > start) ?
- e4b.bd_info->bb_first_free : start;
-
- while (start <= max) {
- start = mb_find_next_zero_bit(bitmap, max + 1, start);
- if (start > max)
- break;
- next = mb_find_next_bit(bitmap, max + 1, start);
-
- if ((next - start) >= minblocks) {
- ret = ext4_trim_extent(sb, start,
- next - start, group, &e4b);
- if (ret && ret != -EOPNOTSUPP)
- break;
- ret = 0;
- count += next - start;
- }
- free_count += next - start;
- start = next + 1;
-
- if (fatal_signal_pending(current)) {
- count = -ERESTARTSYS;
- break;
- }
-
- if (need_resched()) {
- ext4_unlock_group(sb, group);
- cond_resched();
- ext4_lock_group(sb, group);
- }
- if ((e4b.bd_info->bb_free - free_count) < minblocks)
- break;
- }
+ if (!EXT4_MB_GRP_WAS_TRIMMED(e4b.bd_info) ||
+ minblocks < EXT4_SB(sb)->s_last_trim_minblks)
+ ret = ext4_try_to_trim_range(sb, &e4b, start, max, minblocks);
+ else
+ ret = 0;
- if (!ret) {
- ret = count;
- EXT4_MB_GRP_SET_TRIMMED(e4b.bd_info);
- }
-out:
ext4_unlock_group(sb, group);
ext4_mb_unload_buddy(&e4b);
ext4_debug("trimmed %d blocks in the group %d\n",
- count, group);
+ ret, group);
return ret;
}
@@ -5316,7 +5342,7 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
if (minlen > EXT4_CLUSTERS_PER_GROUP(sb))
goto out;
}
- if (end >= max_blks)
+ if (end >= max_blks - 1)
end = max_blks - 1;
if (end <= first_data_blk)
goto out;
@@ -5333,6 +5359,8 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
end = EXT4_CLUSTERS_PER_GROUP(sb) - 1;
for (group = first_group; group <= last_group; group++) {
+ if (ext4_trim_interrupted())
+ break;
grp = ext4_get_group_info(sb, group);
/* We only do this if the grp has never been initialized */
if (unlikely(EXT4_MB_GRP_NEED_INIT(grp))) {
@@ -5349,10 +5377,9 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
*/
if (group == last_group)
end = last_cluster;
-
if (grp->bb_free >= minlen) {
cnt = ext4_trim_all_free(sb, group, first_cluster,
- end, minlen);
+ end, minlen);
if (cnt < 0) {
ret = cnt;
break;
@@ -5368,7 +5395,7 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range)
}
if (!ret)
- atomic_set(&EXT4_SB(sb)->s_last_trim_minblks, minlen);
+ EXT4_SB(sb)->s_last_trim_minblks = minlen;
out:
range->len = EXT4_C2B(EXT4_SB(sb), trimmed) << sb->s_blocksize_bits;
@@ -5397,8 +5424,7 @@ ext4_mballoc_query_range(
ext4_lock_group(sb, group);
- start = (e4b.bd_info->bb_first_free > start) ?
- e4b.bd_info->bb_first_free : start;
+ start = max(e4b.bd_info->bb_first_free, start);
if (end >= EXT4_CLUSTERS_PER_GROUP(sb))
end = EXT4_CLUSTERS_PER_GROUP(sb) - 1;
diff --git a/fs/ext4/namei.c b/fs/ext4/namei.c
index fbb9321ca876c846a9d638994039528a26c71efd..e53f09dfb0bf3221aad93351ba83b03007428014 100644
--- a/fs/ext4/namei.c
+++ b/fs/ext4/namei.c
@@ -325,17 +325,17 @@ static struct ext4_dir_entry_tail *get_dirent_tail(struct inode *inode,
struct ext4_dir_entry *de)
{
struct ext4_dir_entry_tail *t;
+ int blocksize = EXT4_BLOCK_SIZE(inode->i_sb);
#ifdef PARANOID
struct ext4_dir_entry *d, *top;
d = de;
top = (struct ext4_dir_entry *)(((void *)de) +
- (EXT4_BLOCK_SIZE(inode->i_sb) -
- sizeof(struct ext4_dir_entry_tail)));
- while (d < top && d->rec_len)
+ (blocksize - sizeof(struct ext4_dir_entry_tail)));
+ while (d < top && ext4_rec_len_from_disk(d->rec_len, blocksize))
d = (struct ext4_dir_entry *)(((void *)d) +
- le16_to_cpu(d->rec_len));
+ ext4_rec_len_from_disk(d->rec_len, blocksize));
if (d != top)
return NULL;
@@ -346,7 +346,8 @@ static struct ext4_dir_entry_tail *get_dirent_tail(struct inode *inode,
#endif
if (t->det_reserved_zero1 ||
- le16_to_cpu(t->det_rec_len) != sizeof(struct ext4_dir_entry_tail) ||
+ (ext4_rec_len_from_disk(t->det_rec_len, blocksize) !=
+ sizeof(struct ext4_dir_entry_tail)) ||
t->det_reserved_zero2 ||
t->det_reserved_ft != EXT4_FT_DIR_CSUM)
return NULL;
@@ -428,13 +429,14 @@ static struct dx_countlimit *get_dx_countlimit(struct inode *inode,
struct ext4_dir_entry *dp;
struct dx_root_info *root;
int count_offset;
+ int blocksize = EXT4_BLOCK_SIZE(inode->i_sb);
+ unsigned int rlen = ext4_rec_len_from_disk(dirent->rec_len, blocksize);
- if (le16_to_cpu(dirent->rec_len) == EXT4_BLOCK_SIZE(inode->i_sb))
+ if (rlen == blocksize)
count_offset = 8;
- else if (le16_to_cpu(dirent->rec_len) == 12) {
+ else if (rlen == 12) {
dp = (struct ext4_dir_entry *)(((void *)dirent) + 12);
- if (le16_to_cpu(dp->rec_len) !=
- EXT4_BLOCK_SIZE(inode->i_sb) - 12)
+ if (ext4_rec_len_from_disk(dp->rec_len, blocksize) != blocksize - 12)
return NULL;
root = (struct dx_root_info *)(((void *)dp + 12));
if (root->reserved_zero ||
@@ -1285,6 +1287,7 @@ static int dx_make_map(struct inode *dir, struct buffer_head *bh,
unsigned int buflen = bh->b_size;
char *base = bh->b_data;
struct dx_hash_info h = *hinfo;
+ int blocksize = EXT4_BLOCK_SIZE(dir->i_sb);
if (ext4_has_metadata_csum(dir->i_sb))
buflen -= sizeof(struct ext4_dir_entry_tail);
@@ -1301,11 +1304,12 @@ static int dx_make_map(struct inode *dir, struct buffer_head *bh,
map_tail--;
map_tail->hash = h.hash;
map_tail->offs = ((char *) de - base)>>2;
- map_tail->size = le16_to_cpu(de->rec_len);
+ map_tail->size = ext4_rec_len_from_disk(de->rec_len,
+ blocksize);
count++;
cond_resched();
}
- de = ext4_next_entry(de, dir->i_sb->s_blocksize);
+ de = ext4_next_entry(de, blocksize);
}
return count;
}
diff --git a/fs/fuse/Makefile b/fs/fuse/Makefile
index 60da84a86dabdb2e00d2725481631db385985054..9b0821548ab43e09c1652b25b62c6ff5cdfa4d28 100644
--- a/fs/fuse/Makefile
+++ b/fs/fuse/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_FUSE_FS) += fuse.o
obj-$(CONFIG_CUSE) += cuse.o
fuse-objs := dev.o dir.o file.o inode.o control.o xattr.o acl.o
+fuse-objs += passthrough.o
diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c
index 39b11571bcef76461ca594d1eef81f6000b2b32d..a047a7f62f8fd3a019b3fc91f5ae9276f19bdf52 100644
--- a/fs/fuse/dev.c
+++ b/fs/fuse/dev.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
MODULE_ALIAS_MISCDEV(FUSE_MINOR);
MODULE_ALIAS("devname:fuse");
@@ -487,7 +488,9 @@ static void request_wait_answer(struct fuse_conn *fc, struct fuse_req *req)
* Either request is already in userspace, or it was forced.
* Wait it out.
*/
- wait_event(req->waitq, test_bit(FR_FINISHED, &req->flags));
+ while (!test_bit(FR_FINISHED, &req->flags))
+ wait_event_freezable(req->waitq,
+ test_bit(FR_FINISHED, &req->flags));
}
static void __fuse_request_send(struct fuse_conn *fc, struct fuse_req *req)
@@ -2290,37 +2293,50 @@ static int fuse_device_clone(struct fuse_conn *fc, struct file *new)
static long fuse_dev_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
- int err = -ENOTTY;
+ int res;
+ int oldfd;
+ struct fuse_dev *fud = NULL;
- if (cmd == FUSE_DEV_IOC_CLONE) {
- int oldfd;
-
- err = -EFAULT;
- if (!get_user(oldfd, (__u32 __user *) arg)) {
+ switch (cmd) {
+ case FUSE_DEV_IOC_CLONE:
+ res = -EFAULT;
+ if (!get_user(oldfd, (__u32 __user *)arg)) {
struct file *old = fget(oldfd);
- err = -EINVAL;
+ res = -EINVAL;
if (old) {
- struct fuse_dev *fud = NULL;
-
/*
* Check against file->f_op because CUSE
* uses the same ioctl handler.
*/
if (old->f_op == file->f_op &&
- old->f_cred->user_ns == file->f_cred->user_ns)
+ old->f_cred->user_ns ==
+ file->f_cred->user_ns)
fud = fuse_get_dev(old);
if (fud) {
mutex_lock(&fuse_mutex);
- err = fuse_device_clone(fud->fc, file);
+ res = fuse_device_clone(fud->fc, file);
mutex_unlock(&fuse_mutex);
}
fput(old);
}
}
+ break;
+ case FUSE_DEV_IOC_PASSTHROUGH_OPEN:
+ res = -EFAULT;
+ if (!get_user(oldfd, (__u32 __user *)arg)) {
+ res = -EINVAL;
+ fud = fuse_get_dev(file);
+ if (fud)
+ res = fuse_passthrough_open(fud, oldfd);
+ }
+ break;
+ default:
+ res = -ENOTTY;
+ break;
}
- return err;
+ return res;
}
const struct file_operations fuse_dev_operations = {
diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c
index 6b25788ab9bce914bc59c90ea780155bf8e0291b..cdb3a70224120c186d4684e289a44b06be339e89 100644
--- a/fs/fuse/dir.c
+++ b/fs/fuse/dir.c
@@ -296,7 +296,7 @@ static void fuse_dentry_canonical_path(const struct path *path,
char *path_name;
int err;
- path_name = (char *)__get_free_page(GFP_KERNEL);
+ path_name = (char *)get_zeroed_page(GFP_KERNEL);
if (!path_name)
goto default_path;
@@ -508,6 +508,7 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry,
ff->fh = outopen.fh;
ff->nodeid = outentry.nodeid;
ff->open_flags = outopen.open_flags;
+ fuse_passthrough_setup(fc, ff, &outopen);
inode = fuse_iget(dir->i_sb, outentry.nodeid, outentry.generation,
&outentry.attr, entry_attr_timeout(&outentry), 0);
if (!inode) {
diff --git a/fs/fuse/file.c b/fs/fuse/file.c
index 549979a0bb9dda4239d2962bda0c60669fc74568..82a46db963be0ba71563bf681d6223ad40ac1ca0 100644
--- a/fs/fuse/file.c
+++ b/fs/fuse/file.c
@@ -136,7 +136,7 @@ int fuse_do_open(struct fuse_conn *fc, u64 nodeid, struct file *file,
if (!err) {
ff->fh = outarg.fh;
ff->open_flags = outarg.open_flags;
-
+ fuse_passthrough_setup(fc, ff, &outarg);
} else if (err != -ENOSYS || isdir) {
fuse_file_free(ff);
return err;
@@ -264,6 +264,8 @@ void fuse_release_common(struct file *file, bool isdir)
struct fuse_req *req = ff->reserved_req;
int opcode = isdir ? FUSE_RELEASEDIR : FUSE_RELEASE;
+ fuse_passthrough_release(&ff->passthrough);
+
fuse_prepare_release(ff, file->f_flags, opcode);
if (ff->flock) {
@@ -933,6 +935,7 @@ static ssize_t fuse_file_read_iter(struct kiocb *iocb, struct iov_iter *to)
{
struct inode *inode = iocb->ki_filp->f_mapping->host;
struct fuse_conn *fc = get_fuse_conn(inode);
+ struct fuse_file *ff = iocb->ki_filp->private_data;
if (fuse_is_bad(inode))
return -EIO;
@@ -950,6 +953,8 @@ static ssize_t fuse_file_read_iter(struct kiocb *iocb, struct iov_iter *to)
return err;
}
+ if (ff->passthrough.filp)
+ return fuse_passthrough_read_iter(iocb, to);
return generic_file_read_iter(iocb, to);
}
@@ -1193,6 +1198,10 @@ static ssize_t fuse_file_write_iter(struct kiocb *iocb, struct iov_iter *from)
struct inode *inode = mapping->host;
ssize_t err;
loff_t endbyte = 0;
+ struct fuse_file *ff = file->private_data;
+
+ if (ff->passthrough.filp)
+ return fuse_passthrough_write_iter(iocb, from);
if (fuse_is_bad(inode))
return -EIO;
@@ -2108,6 +2117,11 @@ static const struct vm_operations_struct fuse_file_vm_ops = {
static int fuse_file_mmap(struct file *file, struct vm_area_struct *vma)
{
+ struct fuse_file *ff = file->private_data;
+
+ if (ff->passthrough.filp)
+ return fuse_passthrough_mmap(file, vma);
+
if ((vma->vm_flags & VM_SHARED) && (vma->vm_flags & VM_MAYWRITE))
fuse_link_write_file(file);
diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h
index 3704ae529737e239054f49fb3eabfcdd6d183773..9edd2e68fcd86d35eae62d09ccb2f390efe97254 100644
--- a/fs/fuse/fuse_i.h
+++ b/fs/fuse/fuse_i.h
@@ -124,6 +124,17 @@ enum {
struct fuse_conn;
+/**
+ * Reference to lower filesystem file for read/write operations handled in
+ * passthrough mode.
+ * This struct also tracks the credentials to be used for handling read/write
+ * operations.
+ */
+struct fuse_passthrough {
+ struct file *filp;
+ struct cred *cred;
+};
+
/** FUSE specific file data */
struct fuse_file {
/** Fuse connection for this file */
@@ -150,6 +161,9 @@ struct fuse_file {
/** Entry on inode's write_files list */
struct list_head write_entry;
+ /** Container for data related to the passthrough functionality */
+ struct fuse_passthrough passthrough;
+
/** RB node to be linked on fuse_conn->polled_files */
struct rb_node polled_node;
@@ -650,6 +664,9 @@ struct fuse_conn {
/** Allow other than the mounter user to access the filesystem ? */
unsigned allow_other:1;
+ /** Passthrough mode for read/write IO */
+ unsigned int passthrough:1;
+
/** The number of requests waiting for completion */
atomic_t num_waiting;
@@ -688,6 +705,12 @@ struct fuse_conn {
/** List of device instances belonging to this connection */
struct list_head devices;
+
+ /** IDR for passthrough requests */
+ struct idr passthrough_req;
+
+ /** Protects passthrough_req */
+ spinlock_t passthrough_req_lock;
};
static inline struct fuse_conn *get_fuse_conn_super(struct super_block *sb)
@@ -1019,4 +1042,13 @@ struct posix_acl;
struct posix_acl *fuse_get_acl(struct inode *inode, int type);
int fuse_set_acl(struct inode *inode, struct posix_acl *acl, int type);
+/* passthrough.c */
+int fuse_passthrough_open(struct fuse_dev *fud, u32 lower_fd);
+int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff,
+ struct fuse_open_out *openarg);
+void fuse_passthrough_release(struct fuse_passthrough *passthrough);
+ssize_t fuse_passthrough_read_iter(struct kiocb *iocb, struct iov_iter *to);
+ssize_t fuse_passthrough_write_iter(struct kiocb *iocb, struct iov_iter *from);
+ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma);
+
#endif /* _FS_FUSE_I_H */
diff --git a/fs/fuse/inode.c b/fs/fuse/inode.c
index 57208ff9ccc8bfa1df9f83848a58e586ff472096..9754c437dc601ba647cf80f93ffffa764d19b91f 100644
--- a/fs/fuse/inode.c
+++ b/fs/fuse/inode.c
@@ -615,6 +615,7 @@ void fuse_conn_init(struct fuse_conn *fc, struct user_namespace *user_ns)
{
memset(fc, 0, sizeof(*fc));
spin_lock_init(&fc->lock);
+ spin_lock_init(&fc->passthrough_req_lock);
init_rwsem(&fc->killsb);
refcount_set(&fc->count, 1);
atomic_set(&fc->dev_count, 1);
@@ -624,6 +625,7 @@ void fuse_conn_init(struct fuse_conn *fc, struct user_namespace *user_ns)
INIT_LIST_HEAD(&fc->bg_queue);
INIT_LIST_HEAD(&fc->entry);
INIT_LIST_HEAD(&fc->devices);
+ idr_init(&fc->passthrough_req);
atomic_set(&fc->num_waiting, 0);
fc->max_background = FUSE_DEFAULT_MAX_BACKGROUND;
fc->congestion_threshold = FUSE_DEFAULT_CONGESTION_THRESHOLD;
@@ -936,6 +938,12 @@ static void process_init_reply(struct fuse_conn *fc, struct fuse_req *req)
}
if (arg->flags & FUSE_ABORT_ERROR)
fc->abort_err = 1;
+ if (arg->flags & FUSE_PASSTHROUGH) {
+ fc->passthrough = 1;
+ /* Prevent further stacking */
+ fc->sb->s_stack_depth =
+ FILESYSTEM_MAX_STACK_DEPTH;
+ }
} else {
ra_pages = fc->max_read / PAGE_SIZE;
fc->no_lock = 1;
@@ -967,7 +975,7 @@ static void fuse_send_init(struct fuse_conn *fc, struct fuse_req *req)
FUSE_DO_READDIRPLUS | FUSE_READDIRPLUS_AUTO | FUSE_ASYNC_DIO |
FUSE_WRITEBACK_CACHE | FUSE_NO_OPEN_SUPPORT |
FUSE_PARALLEL_DIROPS | FUSE_HANDLE_KILLPRIV | FUSE_POSIX_ACL |
- FUSE_ABORT_ERROR;
+ FUSE_ABORT_ERROR | FUSE_PASSTHROUGH;
req->in.h.opcode = FUSE_INIT;
req->in.numargs = 1;
req->in.args[0].size = sizeof(*arg);
@@ -983,9 +991,21 @@ static void fuse_send_init(struct fuse_conn *fc, struct fuse_req *req)
fuse_request_send_background(fc, req);
}
+static int free_fuse_passthrough(int id, void *p, void *data)
+{
+ struct fuse_passthrough *passthrough = (struct fuse_passthrough *)p;
+
+ fuse_passthrough_release(passthrough);
+ kfree(p);
+
+ return 0;
+}
+
static void fuse_free_conn(struct fuse_conn *fc)
{
WARN_ON(!list_empty(&fc->devices));
+ idr_for_each(&fc->passthrough_req, free_fuse_passthrough, NULL);
+ idr_destroy(&fc->passthrough_req);
kfree_rcu(fc, rcu);
}
diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c
new file mode 100644
index 0000000000000000000000000000000000000000..f344f917d0377889eea25b4dc048ff853e277711
--- /dev/null
+++ b/fs/fuse/passthrough.c
@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "fuse_i.h"
+
+#include
+#include
+#include
+#include
+
+#define PASSTHROUGH_IOCB_MASK \
+ (IOCB_APPEND | IOCB_DSYNC | IOCB_HIPRI | IOCB_NOWAIT | IOCB_SYNC)
+
+struct fuse_aio_req {
+ struct kiocb iocb;
+ struct kiocb *iocb_fuse;
+};
+
+static inline void kiocb_clone(struct kiocb *kiocb, struct kiocb *kiocb_src,
+ struct file *filp)
+{
+ *kiocb = (struct kiocb){
+ .ki_filp = filp,
+ .ki_flags = kiocb_src->ki_flags,
+ .ki_hint = kiocb_src->ki_hint,
+ .ki_ioprio = kiocb_src->ki_ioprio,
+ .ki_pos = kiocb_src->ki_pos,
+ };
+}
+
+static void fuse_file_accessed(struct file *dst_file, struct file *src_file)
+{
+ struct inode *dst_inode;
+ struct inode *src_inode;
+
+ if (dst_file->f_flags & O_NOATIME)
+ return;
+
+ dst_inode = file_inode(dst_file);
+ src_inode = file_inode(src_file);
+
+ if ((!timespec64_equal(&dst_inode->i_mtime, &src_inode->i_mtime) ||
+ !timespec64_equal(&dst_inode->i_ctime, &src_inode->i_ctime))) {
+ dst_inode->i_mtime = src_inode->i_mtime;
+ dst_inode->i_ctime = src_inode->i_ctime;
+ }
+
+ touch_atime(&dst_file->f_path);
+}
+
+static void fuse_copyattr(struct file *dst_file, struct file *src_file)
+{
+ struct inode *dst = file_inode(dst_file);
+ struct inode *src = file_inode(src_file);
+
+ dst->i_atime = src->i_atime;
+ dst->i_mtime = src->i_mtime;
+ dst->i_ctime = src->i_ctime;
+ i_size_write(dst, i_size_read(src));
+}
+
+static void fuse_aio_cleanup_handler(struct fuse_aio_req *aio_req)
+{
+ struct kiocb *iocb = &aio_req->iocb;
+ struct kiocb *iocb_fuse = aio_req->iocb_fuse;
+
+ if (iocb->ki_flags & IOCB_WRITE) {
+ __sb_writers_acquired(file_inode(iocb->ki_filp)->i_sb,
+ SB_FREEZE_WRITE);
+ file_end_write(iocb->ki_filp);
+ fuse_copyattr(iocb_fuse->ki_filp, iocb->ki_filp);
+ }
+
+ iocb_fuse->ki_pos = iocb->ki_pos;
+ kfree(aio_req);
+}
+
+static void fuse_aio_rw_complete(struct kiocb *iocb, long res, long res2)
+{
+ struct fuse_aio_req *aio_req =
+ container_of(iocb, struct fuse_aio_req, iocb);
+ struct kiocb *iocb_fuse = aio_req->iocb_fuse;
+
+ fuse_aio_cleanup_handler(aio_req);
+ iocb_fuse->ki_complete(iocb_fuse, res, res2);
+}
+
+ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse,
+ struct iov_iter *iter)
+{
+ ssize_t ret;
+ const struct cred *old_cred;
+ struct file *fuse_filp = iocb_fuse->ki_filp;
+ struct fuse_file *ff = fuse_filp->private_data;
+ struct file *passthrough_filp = ff->passthrough.filp;
+
+ if (!iov_iter_count(iter))
+ return 0;
+
+ old_cred = override_creds(ff->passthrough.cred);
+ if (is_sync_kiocb(iocb_fuse)) {
+ ret = vfs_iter_read(passthrough_filp, iter, &iocb_fuse->ki_pos,
+ iocb_to_rw_flags(iocb_fuse->ki_flags,
+ PASSTHROUGH_IOCB_MASK));
+ } else {
+ struct fuse_aio_req *aio_req;
+
+ aio_req = kmalloc(sizeof(struct fuse_aio_req), GFP_KERNEL);
+ if (!aio_req) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ aio_req->iocb_fuse = iocb_fuse;
+ kiocb_clone(&aio_req->iocb, iocb_fuse, passthrough_filp);
+ aio_req->iocb.ki_complete = fuse_aio_rw_complete;
+ ret = call_read_iter(passthrough_filp, &aio_req->iocb, iter);
+ if (ret != -EIOCBQUEUED)
+ fuse_aio_cleanup_handler(aio_req);
+ }
+out:
+ revert_creds(old_cred);
+
+ fuse_file_accessed(fuse_filp, passthrough_filp);
+
+ return ret;
+}
+
+ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse,
+ struct iov_iter *iter)
+{
+ ssize_t ret;
+ const struct cred *old_cred;
+ struct file *fuse_filp = iocb_fuse->ki_filp;
+ struct fuse_file *ff = fuse_filp->private_data;
+ struct inode *fuse_inode = file_inode(fuse_filp);
+ struct file *passthrough_filp = ff->passthrough.filp;
+ struct inode *passthrough_inode = file_inode(passthrough_filp);
+
+ if (!iov_iter_count(iter))
+ return 0;
+
+ inode_lock(fuse_inode);
+
+ fuse_copyattr(fuse_filp, passthrough_filp);
+
+ old_cred = override_creds(ff->passthrough.cred);
+ if (is_sync_kiocb(iocb_fuse)) {
+ file_start_write(passthrough_filp);
+ ret = vfs_iter_write(passthrough_filp, iter, &iocb_fuse->ki_pos,
+ iocb_to_rw_flags(iocb_fuse->ki_flags,
+ PASSTHROUGH_IOCB_MASK));
+ file_end_write(passthrough_filp);
+ if (ret > 0)
+ fuse_copyattr(fuse_filp, passthrough_filp);
+ } else {
+ struct fuse_aio_req *aio_req;
+
+ aio_req = kmalloc(sizeof(struct fuse_aio_req), GFP_KERNEL);
+ if (!aio_req) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ file_start_write(passthrough_filp);
+ __sb_writers_release(passthrough_inode->i_sb, SB_FREEZE_WRITE);
+
+ aio_req->iocb_fuse = iocb_fuse;
+ kiocb_clone(&aio_req->iocb, iocb_fuse, passthrough_filp);
+ aio_req->iocb.ki_complete = fuse_aio_rw_complete;
+ ret = call_write_iter(passthrough_filp, &aio_req->iocb, iter);
+ if (ret != -EIOCBQUEUED)
+ fuse_aio_cleanup_handler(aio_req);
+ }
+out:
+ revert_creds(old_cred);
+ inode_unlock(fuse_inode);
+
+ return ret;
+}
+
+ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma)
+{
+ int ret;
+ const struct cred *old_cred;
+ struct fuse_file *ff = file->private_data;
+ struct file *passthrough_filp = ff->passthrough.filp;
+
+ if (!passthrough_filp->f_op->mmap)
+ return -ENODEV;
+
+ if (WARN_ON(file != vma->vm_file))
+ return -EIO;
+
+ vma->vm_file = get_file(passthrough_filp);
+
+ old_cred = override_creds(ff->passthrough.cred);
+ ret = call_mmap(vma->vm_file, vma);
+ revert_creds(old_cred);
+
+ if (ret)
+ fput(passthrough_filp);
+ else
+ fput(file);
+
+ fuse_file_accessed(file, passthrough_filp);
+
+ return ret;
+}
+
+int fuse_passthrough_open(struct fuse_dev *fud, u32 lower_fd)
+{
+ int res;
+ struct file *passthrough_filp;
+ struct fuse_conn *fc = fud->fc;
+ struct inode *passthrough_inode;
+ struct super_block *passthrough_sb;
+ struct fuse_passthrough *passthrough;
+
+ if (!fc->passthrough)
+ return -EPERM;
+
+ passthrough_filp = fget(lower_fd);
+ if (!passthrough_filp) {
+ pr_err("FUSE: invalid file descriptor for passthrough.\n");
+ return -EBADF;
+ }
+
+ if (!passthrough_filp->f_op->read_iter ||
+ !passthrough_filp->f_op->write_iter) {
+ pr_err("FUSE: passthrough file misses file operations.\n");
+ res = -EBADF;
+ goto err_free_file;
+ }
+
+ passthrough_inode = file_inode(passthrough_filp);
+ passthrough_sb = passthrough_inode->i_sb;
+ if (passthrough_sb->s_stack_depth >= FILESYSTEM_MAX_STACK_DEPTH) {
+ pr_err("FUSE: fs stacking depth exceeded for passthrough\n");
+ res = -EINVAL;
+ goto err_free_file;
+ }
+
+ passthrough = kmalloc(sizeof(struct fuse_passthrough), GFP_KERNEL);
+ if (!passthrough) {
+ res = -ENOMEM;
+ goto err_free_file;
+ }
+
+ passthrough->filp = passthrough_filp;
+ passthrough->cred = prepare_creds();
+
+ idr_preload(GFP_KERNEL);
+ spin_lock(&fc->passthrough_req_lock);
+ res = idr_alloc(&fc->passthrough_req, passthrough, 1, 0, GFP_ATOMIC);
+ spin_unlock(&fc->passthrough_req_lock);
+ idr_preload_end();
+
+ if (res > 0)
+ return res;
+
+ fuse_passthrough_release(passthrough);
+ kfree(passthrough);
+
+err_free_file:
+ fput(passthrough_filp);
+
+ return res;
+}
+
+int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff,
+ struct fuse_open_out *openarg)
+{
+ struct fuse_passthrough *passthrough;
+ int passthrough_fh = openarg->passthrough_fh;
+
+ if (!fc->passthrough)
+ return -EPERM;
+
+ /* Default case, passthrough is not requested */
+ if (passthrough_fh <= 0)
+ return -EINVAL;
+
+ spin_lock(&fc->passthrough_req_lock);
+ passthrough = idr_remove(&fc->passthrough_req, passthrough_fh);
+ spin_unlock(&fc->passthrough_req_lock);
+
+ if (!passthrough)
+ return -EINVAL;
+
+ ff->passthrough = *passthrough;
+ kfree(passthrough);
+
+ return 0;
+}
+
+void fuse_passthrough_release(struct fuse_passthrough *passthrough)
+{
+ if (passthrough->filp) {
+ fput(passthrough->filp);
+ passthrough->filp = NULL;
+ }
+ if (passthrough->cred) {
+ put_cred(passthrough->cred);
+ passthrough->cred = NULL;
+ }
+}
diff --git a/fs/nfs/flexfilelayout/flexfilelayout.c b/fs/nfs/flexfilelayout/flexfilelayout.c
index fee421da219757f3109c2b26849c1086beb418bb..bb10f2b21cc1d47985e20cc2b59b2f1252497171 100644
--- a/fs/nfs/flexfilelayout/flexfilelayout.c
+++ b/fs/nfs/flexfilelayout/flexfilelayout.c
@@ -1189,6 +1189,7 @@ static void ff_layout_io_track_ds_error(struct pnfs_layout_segment *lseg,
case -EPFNOSUPPORT:
case -EPROTONOSUPPORT:
case -EOPNOTSUPP:
+ case -EINVAL:
case -ECONNREFUSED:
case -ECONNRESET:
case -EHOSTDOWN:
diff --git a/fs/nilfs2/gcinode.c b/fs/nilfs2/gcinode.c
index 114774ac2185ac3455fc06a544623a2786f977f4..cef46650102e755442c886257693ed13f67c588f 100644
--- a/fs/nilfs2/gcinode.c
+++ b/fs/nilfs2/gcinode.c
@@ -73,10 +73,8 @@ int nilfs_gccache_submit_read_data(struct inode *inode, sector_t blkoff,
struct the_nilfs *nilfs = inode->i_sb->s_fs_info;
err = nilfs_dat_translate(nilfs->ns_dat, vbn, &pbn);
- if (unlikely(err)) { /* -EIO, -ENOMEM, -ENOENT */
- brelse(bh);
+ if (unlikely(err)) /* -EIO, -ENOMEM, -ENOENT */
goto failed;
- }
}
lock_buffer(bh);
@@ -102,6 +100,8 @@ int nilfs_gccache_submit_read_data(struct inode *inode, sector_t blkoff,
failed:
unlock_page(bh->b_page);
put_page(bh->b_page);
+ if (unlikely(err))
+ brelse(bh);
return err;
}
diff --git a/fs/overlayfs/copy_up.c b/fs/overlayfs/copy_up.c
index fa0c9e11b4b7bf72dd4a6b1c513d9060830d43c3..bda5d2015a59991cf07fe07b30d531abd6017146 100644
--- a/fs/overlayfs/copy_up.c
+++ b/fs/overlayfs/copy_up.c
@@ -195,7 +195,7 @@ static int ovl_set_timestamps(struct dentry *upperdentry, struct kstat *stat)
{
struct iattr attr = {
.ia_valid =
- ATTR_ATIME | ATTR_MTIME | ATTR_ATIME_SET | ATTR_MTIME_SET,
+ ATTR_ATIME | ATTR_MTIME | ATTR_ATIME_SET | ATTR_MTIME_SET | ATTR_CTIME,
.ia_atime = stat->atime,
.ia_mtime = stat->mtime,
};
diff --git a/fs/overlayfs/file.c b/fs/overlayfs/file.c
index 818a8ee4357b242cc593a7a555e7bf79117eb2d8..7e22ae7a83bc359884b4710b8d3123de4ec42159 100644
--- a/fs/overlayfs/file.c
+++ b/fs/overlayfs/file.c
@@ -14,6 +14,8 @@
#include
#include "overlayfs.h"
+#define OVL_IOCB_MASK (IOCB_DSYNC | IOCB_HIPRI | IOCB_NOWAIT | IOCB_SYNC)
+
static char ovl_whatisit(struct inode *inode, struct inode *realinode)
{
if (realinode != ovl_inode_upper(inode))
@@ -213,23 +215,6 @@ static void ovl_file_accessed(struct file *file)
touch_atime(&file->f_path);
}
-static rwf_t ovl_iocb_to_rwf(struct kiocb *iocb)
-{
- int ifl = iocb->ki_flags;
- rwf_t flags = 0;
-
- if (ifl & IOCB_NOWAIT)
- flags |= RWF_NOWAIT;
- if (ifl & IOCB_HIPRI)
- flags |= RWF_HIPRI;
- if (ifl & IOCB_DSYNC)
- flags |= RWF_DSYNC;
- if (ifl & IOCB_SYNC)
- flags |= RWF_SYNC;
-
- return flags;
-}
-
static ssize_t ovl_read_iter(struct kiocb *iocb, struct iov_iter *iter)
{
struct file *file = iocb->ki_filp;
@@ -246,7 +231,7 @@ static ssize_t ovl_read_iter(struct kiocb *iocb, struct iov_iter *iter)
old_cred = ovl_override_creds(file_inode(file)->i_sb);
ret = vfs_iter_read(real.file, iter, &iocb->ki_pos,
- ovl_iocb_to_rwf(iocb));
+ iocb_to_rw_flags(iocb->ki_flags, OVL_IOCB_MASK));
ovl_revert_creds(old_cred);
ovl_file_accessed(file);
@@ -281,7 +266,7 @@ static ssize_t ovl_write_iter(struct kiocb *iocb, struct iov_iter *iter)
old_cred = ovl_override_creds(file_inode(file)->i_sb);
file_start_write(real.file);
ret = vfs_iter_write(real.file, iter, &iocb->ki_pos,
- ovl_iocb_to_rwf(iocb));
+ iocb_to_rw_flags(iocb->ki_flags, OVL_IOCB_MASK));
file_end_write(real.file);
ovl_revert_creds(old_cred);
diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c
index 25bd1fdaebac30e0acc69ab353cc0698ea50a835..190aee02bd6c6090b8f436082439adc8e56042b0 100644
--- a/fs/quota/dquot.c
+++ b/fs/quota/dquot.c
@@ -231,19 +231,18 @@ static void put_quota_format(struct quota_format_type *fmt)
* All dquots are placed to the end of inuse_list when first created, and this
* list is used for invalidate operation, which must look at every dquot.
*
- * When the last reference of a dquot will be dropped, the dquot will be
- * added to releasing_dquots. We'd then queue work item which would call
+ * When the last reference of a dquot is dropped, the dquot is added to
+ * releasing_dquots. We'll then queue work item which will call
* synchronize_srcu() and after that perform the final cleanup of all the
- * dquots on the list. Both releasing_dquots and free_dquots use the
- * dq_free list_head in the dquot struct. When a dquot is removed from
- * releasing_dquots, a reference count is always subtracted, and if
- * dq_count == 0 at that point, the dquot will be added to the free_dquots.
+ * dquots on the list. Each cleaned up dquot is moved to free_dquots list.
+ * Both releasing_dquots and free_dquots use the dq_free list_head in the dquot
+ * struct.
*
- * Unused dquots (dq_count == 0) are added to the free_dquots list when freed,
- * and this list is searched whenever we need an available dquot. Dquots are
- * removed from the list as soon as they are used again, and
- * dqstats.free_dquots gives the number of dquots on the list. When
- * dquot is invalidated it's completely released from memory.
+ * Unused and cleaned up dquots are in the free_dquots list and this list is
+ * searched whenever we need an available dquot. Dquots are removed from the
+ * list as soon as they are used again and dqstats.free_dquots gives the number
+ * of dquots on the list. When dquot is invalidated it's completely released
+ * from memory.
*
* Dirty dquots are added to the dqi_dirty_list of quota_info when mark
* dirtied, and this list is searched when writing dirty dquots back to
@@ -321,6 +320,7 @@ static inline void put_dquot_last(struct dquot *dquot)
static inline void put_releasing_dquots(struct dquot *dquot)
{
list_add_tail(&dquot->dq_free, &releasing_dquots);
+ set_bit(DQ_RELEASING_B, &dquot->dq_flags);
}
static inline void remove_free_dquot(struct dquot *dquot)
@@ -328,8 +328,10 @@ static inline void remove_free_dquot(struct dquot *dquot)
if (list_empty(&dquot->dq_free))
return;
list_del_init(&dquot->dq_free);
- if (!atomic_read(&dquot->dq_count))
+ if (!test_bit(DQ_RELEASING_B, &dquot->dq_flags))
dqstats_dec(DQST_FREE_DQUOTS);
+ else
+ clear_bit(DQ_RELEASING_B, &dquot->dq_flags);
}
static inline void put_inuse(struct dquot *dquot)
@@ -571,12 +573,6 @@ static void invalidate_dquots(struct super_block *sb, int type)
continue;
/* Wait for dquot users */
if (atomic_read(&dquot->dq_count)) {
- /* dquot in releasing_dquots, flush and retry */
- if (!list_empty(&dquot->dq_free)) {
- spin_unlock(&dq_list_lock);
- goto restart;
- }
-
atomic_inc(&dquot->dq_count);
spin_unlock(&dq_list_lock);
/*
@@ -595,6 +591,15 @@ static void invalidate_dquots(struct super_block *sb, int type)
* restart. */
goto restart;
}
+ /*
+ * The last user already dropped its reference but dquot didn't
+ * get fully cleaned up yet. Restart the scan which flushes the
+ * work cleaning up released dquots.
+ */
+ if (test_bit(DQ_RELEASING_B, &dquot->dq_flags)) {
+ spin_unlock(&dq_list_lock);
+ goto restart;
+ }
/*
* Quota now has no users and it has been written on last
* dqput()
@@ -686,6 +691,13 @@ int dquot_writeback_dquots(struct super_block *sb, int type)
dq_dirty);
WARN_ON(!dquot_active(dquot));
+ /* If the dquot is releasing we should not touch it */
+ if (test_bit(DQ_RELEASING_B, &dquot->dq_flags)) {
+ spin_unlock(&dq_list_lock);
+ flush_delayed_work("a_release_work);
+ spin_lock(&dq_list_lock);
+ continue;
+ }
/* Now we have active dquot from which someone is
* holding reference so we can safely just increase
@@ -799,18 +811,18 @@ static void quota_release_workfn(struct work_struct *work)
/* Exchange the list head to avoid livelock. */
list_replace_init(&releasing_dquots, &rls_head);
spin_unlock(&dq_list_lock);
+ synchronize_srcu(&dquot_srcu);
restart:
- synchronize_srcu(&dquot_srcu);
spin_lock(&dq_list_lock);
while (!list_empty(&rls_head)) {
dquot = list_first_entry(&rls_head, struct dquot, dq_free);
- /* Dquot got used again? */
- if (atomic_read(&dquot->dq_count) > 1) {
- remove_free_dquot(dquot);
- atomic_dec(&dquot->dq_count);
- continue;
- }
+ WARN_ON_ONCE(atomic_read(&dquot->dq_count));
+ /*
+ * Note that DQ_RELEASING_B protects us from racing with
+ * invalidate_dquots() calls so we are safe to work with the
+ * dquot even after we drop dq_list_lock.
+ */
if (dquot_dirty(dquot)) {
spin_unlock(&dq_list_lock);
/* Commit dquot before releasing */
@@ -824,7 +836,6 @@ static void quota_release_workfn(struct work_struct *work)
}
/* Dquot is inactive and clean, now move it to free list */
remove_free_dquot(dquot);
- atomic_dec(&dquot->dq_count);
put_dquot_last(dquot);
}
spin_unlock(&dq_list_lock);
@@ -865,6 +876,7 @@ void dqput(struct dquot *dquot)
BUG_ON(!list_empty(&dquot->dq_free));
#endif
put_releasing_dquots(dquot);
+ atomic_dec(&dquot->dq_count);
spin_unlock(&dq_list_lock);
queue_delayed_work(system_unbound_wq, "a_release_work, 1);
}
@@ -953,7 +965,7 @@ struct dquot *dqget(struct super_block *sb, struct kqid qid)
dqstats_inc(DQST_LOOKUPS);
}
/* Wait for dq_lock - after this we know that either dquot_release() is
- * already finished or it will be canceled due to dq_count > 1 test */
+ * already finished or it will be canceled due to dq_count > 0 test */
wait_on_dquot(dquot);
/* Read the dquot / allocate space in quota file */
if (!dquot_active(dquot)) {
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 82f98e167f243c3206910ba9547de58772c121b2..44405fc70f17e503aa63d791ca94c30d684e70b4 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -299,14 +299,20 @@ enum rw_hint {
WRITE_LIFE_EXTREME = RWH_WRITE_LIFE_EXTREME,
};
-#define IOCB_EVENTFD (1 << 0)
-#define IOCB_APPEND (1 << 1)
-#define IOCB_DIRECT (1 << 2)
-#define IOCB_HIPRI (1 << 3)
-#define IOCB_DSYNC (1 << 4)
-#define IOCB_SYNC (1 << 5)
-#define IOCB_WRITE (1 << 6)
-#define IOCB_NOWAIT (1 << 7)
+/* Match RWF_* bits to IOCB bits */
+#define IOCB_HIPRI (__force int) RWF_HIPRI
+#define IOCB_DSYNC (__force int) RWF_DSYNC
+#define IOCB_SYNC (__force int) RWF_SYNC
+#define IOCB_NOWAIT (__force int) RWF_NOWAIT
+#define IOCB_APPEND (__force int) RWF_APPEND
+
+/* non-RWF related bits - start at 16 */
+#define IOCB_EVENTFD (1 << 16)
+#define IOCB_DIRECT (1 << 17)
+#define IOCB_WRITE (1 << 18)
+/* iocb->ki_waitq is valid */
+#define IOCB_WAITQ (1 << 19)
+#define IOCB_NOIO (1 << 20)
struct kiocb {
struct file *ki_filp;
@@ -3401,25 +3407,34 @@ static inline int iocb_flags(struct file *file)
static inline int kiocb_set_rw_flags(struct kiocb *ki, rwf_t flags)
{
+ int kiocb_flags = 0;
+
+ /* make sure there's no overlap between RWF and private IOCB flags */
+ BUILD_BUG_ON((__force int)RWF_SUPPORTED & IOCB_EVENTFD);
+
+ if (!flags)
+ return 0;
if (unlikely(flags & ~RWF_SUPPORTED))
return -EOPNOTSUPP;
if (flags & RWF_NOWAIT) {
if (!(ki->ki_filp->f_mode & FMODE_NOWAIT))
return -EOPNOTSUPP;
- ki->ki_flags |= IOCB_NOWAIT;
+ kiocb_flags |= IOCB_NOIO;
}
- if (flags & RWF_HIPRI)
- ki->ki_flags |= IOCB_HIPRI;
- if (flags & RWF_DSYNC)
- ki->ki_flags |= IOCB_DSYNC;
+ kiocb_flags |= (__force int)(flags & RWF_SUPPORTED);
if (flags & RWF_SYNC)
- ki->ki_flags |= (IOCB_DSYNC | IOCB_SYNC);
- if (flags & RWF_APPEND)
- ki->ki_flags |= IOCB_APPEND;
+ kiocb_flags |= IOCB_DSYNC;
+
+ ki->ki_flags |= kiocb_flags;
return 0;
}
+static inline rwf_t iocb_to_rw_flags(int ifl, int iocb_mask)
+{
+ return ifl & iocb_mask;
+}
+
static inline ino_t parent_ino(struct dentry *dentry)
{
ino_t res;
diff --git a/include/linux/if_team.h b/include/linux/if_team.h
index ac42da56f7a28f375dbc50887fee19eaf97c2327..fd32538ae705ec1cef6de566bcb498ea170d9941 100644
--- a/include/linux/if_team.h
+++ b/include/linux/if_team.h
@@ -196,6 +196,8 @@ struct team {
struct net_device *dev; /* associated netdevice */
struct team_pcpu_stats __percpu *pcpu_stats;
+ const struct header_ops *header_ops_cache;
+
struct mutex lock; /* used for overall locking, e.g. port lists write */
/*
diff --git a/include/linux/indirect_call_wrapper.h b/include/linux/indirect_call_wrapper.h
new file mode 100644
index 0000000000000000000000000000000000000000..7c8b7f4948af5690c67402cf8bf818856fff8e0c
--- /dev/null
+++ b/include/linux/indirect_call_wrapper.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _LINUX_INDIRECT_CALL_WRAPPER_H
+#define _LINUX_INDIRECT_CALL_WRAPPER_H
+
+#ifdef CONFIG_RETPOLINE
+
+/*
+ * INDIRECT_CALL_$NR - wrapper for indirect calls with $NR known builtin
+ * @f: function pointer
+ * @f$NR: builtin functions names, up to $NR of them
+ * @__VA_ARGS__: arguments for @f
+ *
+ * Avoid retpoline overhead for known builtin, checking @f vs each of them and
+ * eventually invoking directly the builtin function. The functions are check
+ * in the given order. Fallback to the indirect call.
+ */
+#define INDIRECT_CALL_1(f, f1, ...) \
+ ({ \
+ likely(f == f1) ? f1(__VA_ARGS__) : f(__VA_ARGS__); \
+ })
+#define INDIRECT_CALL_2(f, f2, f1, ...) \
+ ({ \
+ likely(f == f2) ? f2(__VA_ARGS__) : \
+ INDIRECT_CALL_1(f, f1, __VA_ARGS__); \
+ })
+
+#define INDIRECT_CALLABLE_DECLARE(f) f
+#define INDIRECT_CALLABLE_SCOPE
+
+#else
+#define INDIRECT_CALL_1(f, name, ...) f(__VA_ARGS__)
+#define INDIRECT_CALL_2(f, name, ...) f(__VA_ARGS__)
+#define INDIRECT_CALLABLE_DECLARE(f)
+#define INDIRECT_CALLABLE_SCOPE static
+#endif
+
+/*
+ * We can use INDIRECT_CALL_$NR for ipv6 related functions only if ipv6 is
+ * builtin, this macro simplify dealing with indirect calls with only ipv4/ipv6
+ * alternatives
+ */
+#if IS_BUILTIN(CONFIG_IPV6)
+#define INDIRECT_CALL_INET(f, f2, f1, ...) \
+ INDIRECT_CALL_2(f, f2, f1, __VA_ARGS__)
+#elif IS_ENABLED(CONFIG_INET)
+#define INDIRECT_CALL_INET(f, f2, f1, ...) INDIRECT_CALL_1(f, f1, __VA_ARGS__)
+#else
+#define INDIRECT_CALL_INET(f, f2, f1, ...) f(__VA_ARGS__)
+#endif
+
+#endif
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 73cd0182452c4462e0f571450edb6993efbb8b42..361a52e418f7815a985e1c1995c7e0c557e1ed67 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -278,6 +278,10 @@ enum {
ATA_HOST_PARALLEL_SCAN = (1 << 2), /* Ports on this host can be scanned in parallel */
ATA_HOST_IGNORE_ATA = (1 << 3), /* Ignore ATA devices on this host. */
+ ATA_HOST_NO_PART = (1 << 4), /* Host does not support partial */
+ ATA_HOST_NO_SSC = (1 << 5), /* Host does not support slumber */
+ ATA_HOST_NO_DEVSLP = (1 << 6), /* Host does not support devslp */
+
/* bits 24:31 of host->flags are reserved for LLD specific flags */
/* various lengths of time */
@@ -311,7 +315,7 @@ enum {
* advised to wait only for the following duration before
* doing SRST.
*/
- ATA_TMOUT_PMP_SRST_WAIT = 5000,
+ ATA_TMOUT_PMP_SRST_WAIT = 10000,
/* When the LPM policy is set to ATA_LPM_MAX_POWER, there might
* be a spurious PHY event, so ignore the first PHY event that
diff --git a/include/linux/mcb.h b/include/linux/mcb.h
index b1a0ad9d23b3070ffb3fd5a8adc07d6330e96739..8052e5f20630ae739ed7ae519564416a20d8de21 100644
--- a/include/linux/mcb.h
+++ b/include/linux/mcb.h
@@ -66,7 +66,6 @@ static inline struct mcb_bus *to_mcb_bus(struct device *dev)
struct mcb_device {
struct device dev;
struct mcb_bus *bus;
- bool is_added;
struct mcb_driver *driver;
u16 id;
int inst;
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index 90d8bbf068269bfd55f48f97ff218dfb21f16c93..1beafdd15b813609a9a8279edc078e3c787a0245 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -3698,7 +3698,7 @@ static __always_inline int ____dev_forward_skb(struct net_device *dev,
return NET_RX_DROP;
}
- skb_scrub_packet(skb, true);
+ skb_scrub_packet(skb, !net_eq(dev_net(dev), dev_net(skb->dev)));
skb->priority = 0;
return 0;
}
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 3bbe2453e402236cf797f7dc262a8b650fa9ad52..fc9ceace2931f27d95b14446def27f7f3c129fc6 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -597,6 +597,9 @@ struct perf_event {
/* The cumulative AND of all event_caps for events in this group. */
int group_caps;
+#ifndef __GENKSYMS__ /* ANDROID Bug: 307236803 to keep the crc preserved */
+ unsigned int group_generation;
+#endif
struct perf_event *group_leader;
struct pmu *pmu;
void *pmu_private;
diff --git a/include/linux/quota.h b/include/linux/quota.h
index 3088ac929e56260c443f6a276b2e2e5e5a8b923e..17a67cf0d1093bee6f4dcf5137ce34392b5736cf 100644
--- a/include/linux/quota.h
+++ b/include/linux/quota.h
@@ -285,7 +285,9 @@ static inline void dqstats_dec(unsigned int type)
#define DQ_FAKE_B 3 /* no limits only usage */
#define DQ_READ_B 4 /* dquot was read into memory */
#define DQ_ACTIVE_B 5 /* dquot is active (dquot_release not called) */
-#define DQ_LASTSET_B 6 /* Following 6 bits (see QIF_) are reserved\
+#define DQ_RELEASING_B 6 /* dquot is in releasing_dquots list waiting
+ * to be cleaned up */
+#define DQ_LASTSET_B 7 /* Following 6 bits (see QIF_) are reserved\
* for the mask of entries set via SETQUOTA\
* quotactl. They are set under dq_data_lock\
* and the quota format handling dquot can\
diff --git a/include/linux/quotaops.h b/include/linux/quotaops.h
index ec10897f7f60c2e4902946b4006a7f3f13e548b5..844b5836d11d6ca99f35833a10bd2307fd345699 100644
--- a/include/linux/quotaops.h
+++ b/include/linux/quotaops.h
@@ -59,7 +59,7 @@ static inline bool dquot_is_busy(struct dquot *dquot)
{
if (test_bit(DQ_MOD_B, &dquot->dq_flags))
return true;
- if (atomic_read(&dquot->dq_count) > 1)
+ if (atomic_read(&dquot->dq_count) > 0)
return true;
return false;
}
diff --git a/include/net/tcp.h b/include/net/tcp.h
index 8b1a811d6510729ddf4bb1598e60c6b85477c599..0870335c11d96749214831b28ca4458ebfa44826 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -141,6 +141,9 @@ void tcp_time_wait(struct sock *sk, int state, int timeo);
#define TCP_RTO_MAX ((unsigned)(120*HZ))
#define TCP_RTO_MIN ((unsigned)(HZ/5))
#define TCP_TIMEOUT_MIN (2U) /* Min timeout for TCP timers in jiffies */
+
+#define TCP_TIMEOUT_MIN_US (2*USEC_PER_MSEC) /* Min TCP timeout in microsecs */
+
#define TCP_TIMEOUT_INIT ((unsigned)(1*HZ)) /* RFC6298 2.1 initial RTO value */
#define TCP_TIMEOUT_FALLBACK ((unsigned)(3*HZ)) /* RFC 1122 initial RTO value, now
* used as a fallback RTO for the
@@ -362,12 +365,14 @@ extern int tcp_proc_delayed_ack_control(struct ctl_table *table, int write,
void __user *buffer, size_t *length,
loff_t *ppos);
-static inline void tcp_dec_quickack_mode(struct sock *sk,
- const unsigned int pkts)
+static inline void tcp_dec_quickack_mode(struct sock *sk)
{
struct inet_connection_sock *icsk = inet_csk(sk);
if (icsk->icsk_ack.quick) {
+ /* How many ACKs S/ACKing new data have we sent? */
+ const unsigned int pkts = inet_csk_ack_scheduled(sk) ? 1 : 0;
+
if (pkts >= icsk->icsk_ack.quick) {
icsk->icsk_ack.quick = 0;
/* Leaving quickack mode we deflate ATO. */
diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h
index 8b9fb412fbe567b906d8471e013294b1b241598c..17cff15efcdf9612261825942c68353948751e47 100644
--- a/include/uapi/linux/bpf.h
+++ b/include/uapi/linux/bpf.h
@@ -695,7 +695,9 @@ union bpf_attr {
* performed again, if the helper is used in combination with
* direct packet access.
* Return
- * 0 on success, or a negative error in case of failure.
+ * 0 on success, or a negative error in case of failure. Positive
+ * error indicates a potential drop or congestion in the target
+ * device. The particular positive error codes are not defined.
*
* u64 bpf_get_current_pid_tgid(void)
* Return
diff --git a/include/uapi/linux/fuse.h b/include/uapi/linux/fuse.h
index 24af4edfc98c2d822df109e70f09c04980e1d155..7210b489c629ee4d0be09b24da79a8b8e8eb148b 100644
--- a/include/uapi/linux/fuse.h
+++ b/include/uapi/linux/fuse.h
@@ -274,6 +274,7 @@ struct fuse_file_lock {
#define FUSE_HANDLE_KILLPRIV (1 << 19)
#define FUSE_POSIX_ACL (1 << 20)
#define FUSE_ABORT_ERROR (1 << 21)
+#define FUSE_PASSTHROUGH (1 << 31)
/**
* CUSE INIT request/reply flags
@@ -506,7 +507,7 @@ struct fuse_create_in {
struct fuse_open_out {
uint64_t fh;
uint32_t open_flags;
- uint32_t padding;
+ uint32_t passthrough_fh;
};
struct fuse_release_in {
@@ -782,7 +783,11 @@ struct fuse_notify_retrieve_in {
};
/* Device ioctls: */
-#define FUSE_DEV_IOC_CLONE _IOR(229, 0, uint32_t)
+#define FUSE_DEV_IOC_MAGIC 229
+#define FUSE_DEV_IOC_CLONE _IOR(FUSE_DEV_IOC_MAGIC, 0, uint32_t)
+/* 127 is reserved for the V1 interface implementation in Android (deprecated) */
+/* 126 is reserved for the V2 interface implementation in Android */
+#define FUSE_DEV_IOC_PASSTHROUGH_OPEN _IOW(FUSE_DEV_IOC_MAGIC, 126, __u32)
struct fuse_lseek_in {
uint64_t fh;
diff --git a/kernel/cgroup/cgroup-v1.c b/kernel/cgroup/cgroup-v1.c
index 6677a2f5f1c2886d82d556521e8cae4c7954aa5f..26fd0118a5ba906a3996bf0dfb129cddd7ab3547 100644
--- a/kernel/cgroup/cgroup-v1.c
+++ b/kernel/cgroup/cgroup-v1.c
@@ -382,10 +382,9 @@ static int pidlist_array_load(struct cgroup *cgrp, enum cgroup_filetype type,
}
css_task_iter_end(&it);
length = n;
- /* now sort & (if procs) strip out duplicates */
+ /* now sort & strip out duplicates (tgids or recycled thread PIDs) */
sort(array, length, sizeof(pid_t), cmppid, NULL);
- if (type == CGROUP_FILE_PROCS)
- length = pidlist_uniq(array, length);
+ length = pidlist_uniq(array, length);
l = cgroup_pidlist_find_create(cgrp, type);
if (!l) {
diff --git a/kernel/events/core.c b/kernel/events/core.c
index f68ff0d4bf79bb0d17fd18c62e52dd353b6daf58..e90f45c9835877d1f10fe3f3182b7fc98a57c7c0 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -1876,6 +1876,7 @@ static void perf_group_attach(struct perf_event *event)
list_add_tail(&event->sibling_list, &group_leader->sibling_list);
group_leader->nr_siblings++;
+ group_leader->group_generation++;
perf_event__header_size(group_leader);
@@ -1946,6 +1947,7 @@ static void perf_group_detach(struct perf_event *event)
if (event->group_leader != event) {
list_del_init(&event->sibling_list);
event->group_leader->nr_siblings--;
+ event->group_leader->group_generation++;
if (event->shared)
event->group_leader = event;
@@ -4894,7 +4896,7 @@ static int __perf_read_group_add(struct perf_event *leader,
u64 read_format, u64 *values)
{
struct perf_event_context *ctx = leader->ctx;
- struct perf_event *sub;
+ struct perf_event *sub, *parent;
unsigned long flags;
int n = 1; /* skip @nr */
int ret;
@@ -4904,6 +4906,33 @@ static int __perf_read_group_add(struct perf_event *leader,
return ret;
raw_spin_lock_irqsave(&ctx->lock, flags);
+ /*
+ * Verify the grouping between the parent and child (inherited)
+ * events is still in tact.
+ *
+ * Specifically:
+ * - leader->ctx->lock pins leader->sibling_list
+ * - parent->child_mutex pins parent->child_list
+ * - parent->ctx->mutex pins parent->sibling_list
+ *
+ * Because parent->ctx != leader->ctx (and child_list nests inside
+ * ctx->mutex), group destruction is not atomic between children, also
+ * see perf_event_release_kernel(). Additionally, parent can grow the
+ * group.
+ *
+ * Therefore it is possible to have parent and child groups in a
+ * different configuration and summing over such a beast makes no sense
+ * what so ever.
+ *
+ * Reject this.
+ */
+ parent = leader->parent;
+ if (parent &&
+ (parent->group_generation != leader->group_generation ||
+ parent->nr_siblings != leader->nr_siblings)) {
+ ret = -ECHILD;
+ goto unlock;
+ }
/*
* Since we co-schedule groups, {enabled,running} times of siblings
@@ -4933,8 +4962,9 @@ static int __perf_read_group_add(struct perf_event *leader,
values[n++] = primary_event_id(sub);
}
+unlock:
raw_spin_unlock_irqrestore(&ctx->lock, flags);
- return 0;
+ return ret;
}
static int perf_read_group(struct perf_event *event,
@@ -4953,10 +4983,6 @@ static int perf_read_group(struct perf_event *event,
values[0] = 1 + leader->nr_siblings;
- /*
- * By locking the child_mutex of the leader we effectively
- * lock the child list of all siblings.. XXX explain how.
- */
mutex_lock(&leader->child_mutex);
ret = __perf_read_group_add(leader, read_format, values);
@@ -11903,6 +11929,7 @@ static int inherit_group(struct perf_event *parent_event,
if (IS_ERR(child_ctr))
return PTR_ERR(child_ctr);
}
+ leader->group_generation = parent_event->group_generation;
return 0;
}
diff --git a/kernel/sched/idle.c b/kernel/sched/idle.c
index aa67df67dd71c302dac8b959bf9569fe538fa1ba..684827bddfa2ad94d017d86b82a23365e2849f2e 100644
--- a/kernel/sched/idle.c
+++ b/kernel/sched/idle.c
@@ -54,18 +54,19 @@ __setup("hlt", cpu_idle_nopoll_setup);
static noinline int __cpuidle cpu_idle_poll(void)
{
+ trace_cpu_idle(0, smp_processor_id());
+ stop_critical_timings();
rcu_idle_enter();
- trace_cpu_idle_rcuidle(0, smp_processor_id());
local_irq_enable();
- stop_critical_timings();
while (!tif_need_resched() &&
- (cpu_idle_force_poll || tick_check_broadcast_expired() ||
+ (cpu_idle_force_poll || tick_check_broadcast_expired() ||
is_reserved(smp_processor_id())))
cpu_relax();
- start_critical_timings();
- trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
+
rcu_idle_exit();
+ start_critical_timings();
+ trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
return 1;
}
@@ -92,7 +93,9 @@ void __cpuidle default_idle_call(void)
local_irq_enable();
} else {
stop_critical_timings();
+ rcu_idle_enter();
arch_cpu_idle();
+ rcu_idle_exit();
start_critical_timings();
}
}
@@ -150,7 +153,6 @@ static void cpuidle_idle_call(void)
if (cpuidle_not_available(drv, dev)) {
tick_nohz_idle_stop_tick();
- rcu_idle_enter();
default_idle_call();
goto exit_idle;
@@ -168,19 +170,15 @@ static void cpuidle_idle_call(void)
if (idle_should_enter_s2idle() || dev->use_deepest_state) {
if (idle_should_enter_s2idle()) {
- rcu_idle_enter();
entered_state = cpuidle_enter_s2idle(drv, dev);
if (entered_state > 0) {
local_irq_enable();
goto exit_idle;
}
-
- rcu_idle_exit();
}
tick_nohz_idle_stop_tick();
- rcu_idle_enter();
next_state = cpuidle_find_deepest_state(drv, dev);
call_cpuidle(drv, dev, next_state);
@@ -197,8 +195,6 @@ static void cpuidle_idle_call(void)
else
tick_nohz_idle_retain_tick();
- rcu_idle_enter();
-
entered_state = call_cpuidle(drv, dev, next_state);
/*
* Give the governor an opportunity to reflect on the outcome
@@ -214,8 +210,6 @@ static void cpuidle_idle_call(void)
*/
if (WARN_ON_ONCE(irqs_disabled()))
local_irq_enable();
-
- rcu_idle_exit();
}
/*
diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c
index c8a7de7a1d635eec564738989cc5d6ba7e8c5fb9..320aa60664dc9593a8a20b56b1f60e245e7420a5 100644
--- a/kernel/trace/ring_buffer.c
+++ b/kernel/trace/ring_buffer.c
@@ -1753,6 +1753,8 @@ int ring_buffer_resize(struct ring_buffer *buffer, unsigned long size,
err = -ENOMEM;
goto out_err;
}
+
+ cond_resched();
}
get_online_cpus();
diff --git a/kernel/trace/trace_events.c b/kernel/trace/trace_events.c
index aff8bbc0d08fdb7014cbf6ff51dbe950ee6d2692..67da4a589ff6796ff11aa25ad0db256bc335f34b 100644
--- a/kernel/trace/trace_events.c
+++ b/kernel/trace/trace_events.c
@@ -2242,6 +2242,7 @@ void trace_event_eval_update(struct trace_eval_map **map, int len)
update_event_printk(call, map[i]);
}
}
+ cond_resched();
}
up_write(&trace_event_sem);
}
diff --git a/kernel/workqueue.c b/kernel/workqueue.c
index eb1103585c01ff084c076d0d141898578d3673d5..2ffaea97b510244a4cf3480f7d18463b5d58c4c6 100644
--- a/kernel/workqueue.c
+++ b/kernel/workqueue.c
@@ -5134,9 +5134,13 @@ static int workqueue_apply_unbound_cpumask(void)
list_for_each_entry(wq, &workqueues, list) {
if (!(wq->flags & WQ_UNBOUND))
continue;
+
/* creating multiple pwqs breaks ordering guarantee */
- if (wq->flags & __WQ_ORDERED)
- continue;
+ if (!list_empty(&wq->pwqs)) {
+ if (wq->flags & __WQ_ORDERED_EXPLICIT)
+ continue;
+ wq->flags &= ~__WQ_ORDERED;
+ }
ctx = apply_wqattrs_prepare(wq, wq->unbound_attrs);
if (!ctx) {
diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c
index 1b50e4ef2c6833c7b8b2d34982b08d2460ae3a96..b876e97b61c9246155a0b9237667edf263178ebd 100644
--- a/net/bluetooth/hci_conn.c
+++ b/net/bluetooth/hci_conn.c
@@ -1204,6 +1204,15 @@ struct hci_conn *hci_connect_acl(struct hci_dev *hdev, bdaddr_t *dst,
return ERR_PTR(-EOPNOTSUPP);
}
+ /* Reject outgoing connection to device with same BD ADDR against
+ * CVE-2020-26555
+ */
+ if (!bacmp(&hdev->bdaddr, dst)) {
+ bt_dev_dbg(hdev, "Reject connection with same BD_ADDR %pMR\n",
+ dst);
+ return ERR_PTR(-ECONNREFUSED);
+ }
+
acl = hci_conn_hash_lookup_ba(hdev, ACL_LINK, dst);
if (!acl) {
acl = hci_conn_add(hdev, ACL_LINK, dst, HCI_ROLE_MASTER);
@@ -1379,34 +1388,41 @@ int hci_conn_security(struct hci_conn *conn, __u8 sec_level, __u8 auth_type,
if (!test_bit(HCI_CONN_AUTH, &conn->flags))
goto auth;
- /* An authenticated FIPS approved combination key has sufficient
- * security for security level 4. */
- if (conn->key_type == HCI_LK_AUTH_COMBINATION_P256 &&
- sec_level == BT_SECURITY_FIPS)
- goto encrypt;
-
- /* An authenticated combination key has sufficient security for
- security level 3. */
- if ((conn->key_type == HCI_LK_AUTH_COMBINATION_P192 ||
- conn->key_type == HCI_LK_AUTH_COMBINATION_P256) &&
- sec_level == BT_SECURITY_HIGH)
- goto encrypt;
-
- /* An unauthenticated combination key has sufficient security for
- security level 1 and 2. */
- if ((conn->key_type == HCI_LK_UNAUTH_COMBINATION_P192 ||
- conn->key_type == HCI_LK_UNAUTH_COMBINATION_P256) &&
- (sec_level == BT_SECURITY_MEDIUM || sec_level == BT_SECURITY_LOW))
- goto encrypt;
-
- /* A combination key has always sufficient security for the security
- levels 1 or 2. High security level requires the combination key
- is generated using maximum PIN code length (16).
- For pre 2.1 units. */
- if (conn->key_type == HCI_LK_COMBINATION &&
- (sec_level == BT_SECURITY_MEDIUM || sec_level == BT_SECURITY_LOW ||
- conn->pin_length == 16))
- goto encrypt;
+ switch (conn->key_type) {
+ case HCI_LK_AUTH_COMBINATION_P256:
+ /* An authenticated FIPS approved combination key has
+ * sufficient security for security level 4 or lower.
+ */
+ if (sec_level <= BT_SECURITY_FIPS)
+ goto encrypt;
+ break;
+ case HCI_LK_AUTH_COMBINATION_P192:
+ /* An authenticated combination key has sufficient security for
+ * security level 3 or lower.
+ */
+ if (sec_level <= BT_SECURITY_HIGH)
+ goto encrypt;
+ break;
+ case HCI_LK_UNAUTH_COMBINATION_P192:
+ case HCI_LK_UNAUTH_COMBINATION_P256:
+ /* An unauthenticated combination key has sufficient security
+ * for security level 2 or lower.
+ */
+ if (sec_level <= BT_SECURITY_MEDIUM)
+ goto encrypt;
+ break;
+ case HCI_LK_COMBINATION:
+ /* A combination key has always sufficient security for the
+ * security levels 2 or lower. High security level requires the
+ * combination key is generated using maximum PIN code length
+ * (16). For pre 2.1 units.
+ */
+ if (sec_level <= BT_SECURITY_MEDIUM || conn->pin_length == 16)
+ goto encrypt;
+ break;
+ default:
+ break;
+ }
auth:
if (test_bit(HCI_CONN_ENCRYPT_PEND, &conn->flags))
diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
index dd7bf437d88e0a7af0da586e74bdb7b75ed45298..8b59f7808628a2871d6d951ba167993119cf0c28 100644
--- a/net/bluetooth/hci_event.c
+++ b/net/bluetooth/hci_event.c
@@ -25,6 +25,8 @@
/* Bluetooth HCI event handling. */
#include
+#include
+#include
#include
#include
@@ -2510,6 +2512,16 @@ static void hci_conn_request_evt(struct hci_dev *hdev, struct sk_buff *skb)
BT_DBG("%s bdaddr %pMR type 0x%x", hdev->name, &ev->bdaddr,
ev->link_type);
+ /* Reject incoming connection from device with same BD ADDR against
+ * CVE-2020-26555
+ */
+ if (hdev && !bacmp(&hdev->bdaddr, &ev->bdaddr)) {
+ bt_dev_dbg(hdev, "Reject connection with same BD_ADDR %pMR\n",
+ &ev->bdaddr);
+ hci_reject_conn(hdev, &ev->bdaddr);
+ return;
+ }
+
mask |= hci_proto_connect_ind(hdev, &ev->bdaddr, ev->link_type,
&flags);
@@ -3816,6 +3828,15 @@ static void hci_link_key_notify_evt(struct hci_dev *hdev, struct sk_buff *skb)
if (!conn)
goto unlock;
+ /* Ignore NULL link key against CVE-2020-26555 */
+ if (!crypto_memneq(ev->link_key, ZERO_KEY, HCI_LINK_KEY_SIZE)) {
+ bt_dev_dbg(hdev, "Ignore NULL link key (ZERO KEY) for %pMR",
+ &ev->bdaddr);
+ hci_disconnect(conn, HCI_ERROR_AUTH_FAILURE);
+ hci_conn_drop(conn);
+ goto unlock;
+ }
+
hci_conn_hold(conn);
conn->disc_timeout = HCI_DISCONN_TIMEOUT;
hci_conn_drop(conn);
@@ -4294,8 +4315,8 @@ static u8 bredr_oob_data_present(struct hci_conn *conn)
* available, then do not declare that OOB data is
* present.
*/
- if (!memcmp(data->rand256, ZERO_KEY, 16) ||
- !memcmp(data->hash256, ZERO_KEY, 16))
+ if (!crypto_memneq(data->rand256, ZERO_KEY, 16) ||
+ !crypto_memneq(data->hash256, ZERO_KEY, 16))
return 0x00;
return 0x02;
@@ -4305,8 +4326,8 @@ static u8 bredr_oob_data_present(struct hci_conn *conn)
* not supported by the hardware, then check that if
* P-192 data values are present.
*/
- if (!memcmp(data->rand192, ZERO_KEY, 16) ||
- !memcmp(data->hash192, ZERO_KEY, 16))
+ if (!crypto_memneq(data->rand192, ZERO_KEY, 16) ||
+ !crypto_memneq(data->hash192, ZERO_KEY, 16))
return 0x00;
return 0x01;
@@ -4322,7 +4343,7 @@ static void hci_io_capa_request_evt(struct hci_dev *hdev, struct sk_buff *skb)
hci_dev_lock(hdev);
conn = hci_conn_hash_lookup_ba(hdev, ACL_LINK, &ev->bdaddr);
- if (!conn)
+ if (!conn || !hci_conn_ssp_enabled(conn))
goto unlock;
hci_conn_hold(conn);
@@ -4557,7 +4578,7 @@ static void hci_simple_pair_complete_evt(struct hci_dev *hdev,
hci_dev_lock(hdev);
conn = hci_conn_hash_lookup_ba(hdev, ACL_LINK, &ev->bdaddr);
- if (!conn)
+ if (!conn || !hci_conn_ssp_enabled(conn))
goto unlock;
/* Reset the authentication requirement to unknown */
diff --git a/net/bluetooth/hci_sock.c b/net/bluetooth/hci_sock.c
index 182c3c5b83858fbb57878921ea75f920b42a9059..a7e5bca9f7e4d602f194314cbe357d00b831e652 100644
--- a/net/bluetooth/hci_sock.c
+++ b/net/bluetooth/hci_sock.c
@@ -430,7 +430,8 @@ static struct sk_buff *create_monitor_event(struct hci_dev *hdev, int event)
ni->type = hdev->dev_type;
ni->bus = hdev->bus;
bacpy(&ni->bdaddr, &hdev->bdaddr);
- memcpy(ni->name, hdev->name, 8);
+ memcpy_and_pad(ni->name, sizeof(ni->name), hdev->name,
+ strnlen(hdev->name, sizeof(ni->name)), '\0');
opcode = cpu_to_le16(HCI_MON_NEW_INDEX);
break;
diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c
index 21bd37ec5511c0507cf9aa77f0f0a7d7a9e83306..7fd18e10755ec1fefc54f37e282d6c80c7ff6d44 100644
--- a/net/ceph/messenger.c
+++ b/net/ceph/messenger.c
@@ -462,7 +462,7 @@ static void set_sock_callbacks(struct socket *sock,
*/
static int ceph_tcp_connect(struct ceph_connection *con)
{
- struct sockaddr_storage *paddr = &con->peer_addr.in_addr;
+ struct sockaddr_storage ss = con->peer_addr.in_addr; /* align */
struct socket *sock;
unsigned int noio_flag;
int ret;
@@ -471,7 +471,7 @@ static int ceph_tcp_connect(struct ceph_connection *con)
/* sock_create_kern() allocates with GFP_KERNEL */
noio_flag = memalloc_noio_save();
- ret = sock_create_kern(read_pnet(&con->msgr->net), paddr->ss_family,
+ ret = sock_create_kern(read_pnet(&con->msgr->net), ss.ss_family,
SOCK_STREAM, IPPROTO_TCP, &sock);
memalloc_noio_restore(noio_flag);
if (ret)
@@ -487,8 +487,8 @@ static int ceph_tcp_connect(struct ceph_connection *con)
dout("connect %s\n", ceph_pr_addr(&con->peer_addr.in_addr));
con_sock_state_connecting(con);
- ret = sock->ops->connect(sock, (struct sockaddr *)paddr, sizeof(*paddr),
- O_NONBLOCK);
+ ret = kernel_connect(sock, (struct sockaddr *)&ss, sizeof(ss),
+ O_NONBLOCK);
if (ret == -EINPROGRESS) {
dout("connect %s EINPROGRESS sk_state = %u\n",
ceph_pr_addr(&con->peer_addr.in_addr),
@@ -1824,14 +1824,15 @@ static int verify_hello(struct ceph_connection *con)
return 0;
}
-static bool addr_is_blank(struct sockaddr_storage *ss)
+static bool addr_is_blank(struct ceph_entity_addr *addr)
{
- struct in_addr *addr = &((struct sockaddr_in *)ss)->sin_addr;
- struct in6_addr *addr6 = &((struct sockaddr_in6 *)ss)->sin6_addr;
+ struct sockaddr_storage ss = addr->in_addr; /* align */
+ struct in_addr *addr4 = &((struct sockaddr_in *)&ss)->sin_addr;
+ struct in6_addr *addr6 = &((struct sockaddr_in6 *)&ss)->sin6_addr;
- switch (ss->ss_family) {
+ switch (ss.ss_family) {
case AF_INET:
- return addr->s_addr == htonl(INADDR_ANY);
+ return addr4->s_addr == htonl(INADDR_ANY);
case AF_INET6:
return ipv6_addr_any(addr6);
default:
@@ -1839,25 +1840,25 @@ static bool addr_is_blank(struct sockaddr_storage *ss)
}
}
-static int addr_port(struct sockaddr_storage *ss)
+static int addr_port(struct ceph_entity_addr *addr)
{
- switch (ss->ss_family) {
+ switch (get_unaligned(&addr->in_addr.ss_family)) {
case AF_INET:
- return ntohs(((struct sockaddr_in *)ss)->sin_port);
+ return ntohs(get_unaligned(&((struct sockaddr_in *)&addr->in_addr)->sin_port));
case AF_INET6:
- return ntohs(((struct sockaddr_in6 *)ss)->sin6_port);
+ return ntohs(get_unaligned(&((struct sockaddr_in6 *)&addr->in_addr)->sin6_port));
}
return 0;
}
-static void addr_set_port(struct sockaddr_storage *ss, int p)
+static void addr_set_port(struct ceph_entity_addr *addr, int p)
{
- switch (ss->ss_family) {
+ switch (get_unaligned(&addr->in_addr.ss_family)) {
case AF_INET:
- ((struct sockaddr_in *)ss)->sin_port = htons(p);
+ put_unaligned(htons(p), &((struct sockaddr_in *)&addr->in_addr)->sin_port);
break;
case AF_INET6:
- ((struct sockaddr_in6 *)ss)->sin6_port = htons(p);
+ put_unaligned(htons(p), &((struct sockaddr_in6 *)&addr->in_addr)->sin6_port);
break;
}
}
@@ -1865,21 +1866,18 @@ static void addr_set_port(struct sockaddr_storage *ss, int p)
/*
* Unlike other *_pton function semantics, zero indicates success.
*/
-static int ceph_pton(const char *str, size_t len, struct sockaddr_storage *ss,
+static int ceph_pton(const char *str, size_t len, struct ceph_entity_addr *addr,
char delim, const char **ipend)
{
- struct sockaddr_in *in4 = (struct sockaddr_in *) ss;
- struct sockaddr_in6 *in6 = (struct sockaddr_in6 *) ss;
-
- memset(ss, 0, sizeof(*ss));
+ memset(&addr->in_addr, 0, sizeof(addr->in_addr));
- if (in4_pton(str, len, (u8 *)&in4->sin_addr.s_addr, delim, ipend)) {
- ss->ss_family = AF_INET;
+ if (in4_pton(str, len, (u8 *)&((struct sockaddr_in *)&addr->in_addr)->sin_addr.s_addr, delim, ipend)) {
+ put_unaligned(AF_INET, &addr->in_addr.ss_family);
return 0;
}
- if (in6_pton(str, len, (u8 *)&in6->sin6_addr.s6_addr, delim, ipend)) {
- ss->ss_family = AF_INET6;
+ if (in6_pton(str, len, (u8 *)&((struct sockaddr_in6 *)&addr->in_addr)->sin6_addr.s6_addr, delim, ipend)) {
+ put_unaligned(AF_INET6, &addr->in_addr.ss_family);
return 0;
}
@@ -1891,7 +1889,7 @@ static int ceph_pton(const char *str, size_t len, struct sockaddr_storage *ss,
*/
#ifdef CONFIG_CEPH_LIB_USE_DNS_RESOLVER
static int ceph_dns_resolve_name(const char *name, size_t namelen,
- struct sockaddr_storage *ss, char delim, const char **ipend)
+ struct ceph_entity_addr *addr, char delim, const char **ipend)
{
const char *end, *delim_p;
char *colon_p, *ip_addr = NULL;
@@ -1920,7 +1918,7 @@ static int ceph_dns_resolve_name(const char *name, size_t namelen,
/* do dns_resolve upcall */
ip_len = dns_query(NULL, name, end - name, NULL, &ip_addr, NULL);
if (ip_len > 0)
- ret = ceph_pton(ip_addr, ip_len, ss, -1, NULL);
+ ret = ceph_pton(ip_addr, ip_len, addr, -1, NULL);
else
ret = -ESRCH;
@@ -1929,13 +1927,13 @@ static int ceph_dns_resolve_name(const char *name, size_t namelen,
*ipend = end;
pr_info("resolve '%.*s' (ret=%d): %s\n", (int)(end - name), name,
- ret, ret ? "failed" : ceph_pr_addr(ss));
+ ret, ret ? "failed" : ceph_pr_addr(&addr->in_addr));
return ret;
}
#else
static inline int ceph_dns_resolve_name(const char *name, size_t namelen,
- struct sockaddr_storage *ss, char delim, const char **ipend)
+ struct ceph_entity_addr *addr, char delim, const char **ipend)
{
return -EINVAL;
}
@@ -1946,13 +1944,13 @@ static inline int ceph_dns_resolve_name(const char *name, size_t namelen,
* then try to extract a hostname to resolve using userspace DNS upcall.
*/
static int ceph_parse_server_name(const char *name, size_t namelen,
- struct sockaddr_storage *ss, char delim, const char **ipend)
+ struct ceph_entity_addr *addr, char delim, const char **ipend)
{
int ret;
- ret = ceph_pton(name, namelen, ss, delim, ipend);
+ ret = ceph_pton(name, namelen, addr, delim, ipend);
if (ret)
- ret = ceph_dns_resolve_name(name, namelen, ss, delim, ipend);
+ ret = ceph_dns_resolve_name(name, namelen, addr, delim, ipend);
return ret;
}
@@ -1971,7 +1969,6 @@ int ceph_parse_ips(const char *c, const char *end,
dout("parse_ips on '%.*s'\n", (int)(end-c), c);
for (i = 0; i < max_count; i++) {
const char *ipend;
- struct sockaddr_storage *ss = &addr[i].in_addr;
int port;
char delim = ',';
@@ -1980,7 +1977,7 @@ int ceph_parse_ips(const char *c, const char *end,
p++;
}
- ret = ceph_parse_server_name(p, end - p, ss, delim, &ipend);
+ ret = ceph_parse_server_name(p, end - p, &addr[i], delim, &ipend);
if (ret)
goto bad;
ret = -EINVAL;
@@ -2011,9 +2008,9 @@ int ceph_parse_ips(const char *c, const char *end,
port = CEPH_MON_PORT;
}
- addr_set_port(ss, port);
+ addr_set_port(&addr[i], port);
- dout("parse_ips got %s\n", ceph_pr_addr(ss));
+ dout("parse_ips got %s\n", ceph_pr_addr(&addr[i].in_addr));
if (p == end)
break;
@@ -2052,7 +2049,7 @@ static int process_banner(struct ceph_connection *con)
*/
if (memcmp(&con->peer_addr, &con->actual_peer_addr,
sizeof(con->peer_addr)) != 0 &&
- !(addr_is_blank(&con->actual_peer_addr.in_addr) &&
+ !(addr_is_blank(&con->actual_peer_addr) &&
con->actual_peer_addr.nonce == con->peer_addr.nonce)) {
pr_warn("wrong peer, want %s/%d, got %s/%d\n",
ceph_pr_addr(&con->peer_addr.in_addr),
@@ -2066,13 +2063,13 @@ static int process_banner(struct ceph_connection *con)
/*
* did we learn our address?
*/
- if (addr_is_blank(&con->msgr->inst.addr.in_addr)) {
- int port = addr_port(&con->msgr->inst.addr.in_addr);
+ if (addr_is_blank(&con->msgr->inst.addr)) {
+ int port = addr_port(&con->msgr->inst.addr);
memcpy(&con->msgr->inst.addr.in_addr,
&con->peer_addr_for_me.in_addr,
sizeof(con->peer_addr_for_me.in_addr));
- addr_set_port(&con->msgr->inst.addr.in_addr, port);
+ addr_set_port(&con->msgr->inst.addr, port);
encode_my_addr(con->msgr);
dout("process_banner learned my addr is %s\n",
ceph_pr_addr(&con->msgr->inst.addr.in_addr));
diff --git a/net/core/pktgen.c b/net/core/pktgen.c
index 3714cd9e3111f57aefbecb5d0829e4f77c72a41a..3ade60ec45128779215230270fd5023fee2477d7 100644
--- a/net/core/pktgen.c
+++ b/net/core/pktgen.c
@@ -651,19 +651,19 @@ static int pktgen_if_show(struct seq_file *seq, void *v)
seq_puts(seq, " Flags: ");
for (i = 0; i < NR_PKT_FLAGS; i++) {
- if (i == F_FLOW_SEQ)
+ if (i == FLOW_SEQ_SHIFT)
if (!pkt_dev->cflows)
continue;
- if (pkt_dev->flags & (1 << i))
+ if (pkt_dev->flags & (1 << i)) {
seq_printf(seq, "%s ", pkt_flag_names[i]);
- else if (i == F_FLOW_SEQ)
- seq_puts(seq, "FLOW_RND ");
-
#ifdef CONFIG_XFRM
- if (i == F_IPSEC && pkt_dev->spi)
- seq_printf(seq, "spi:%u", pkt_dev->spi);
+ if (i == IPSEC_SHIFT && pkt_dev->spi)
+ seq_printf(seq, "spi:%u ", pkt_dev->spi);
#endif
+ } else if (i == FLOW_SEQ_SHIFT) {
+ seq_puts(seq, "FLOW_RND ");
+ }
}
seq_puts(seq, "\n");
diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c
index 794db633f1c905319ac4e7f115e4a5c28e4c608e..0d3f724da78ba23c9667bf56d387e002f7995e57 100644
--- a/net/core/rtnetlink.c
+++ b/net/core/rtnetlink.c
@@ -2702,10 +2702,7 @@ static int rtnl_setlink(struct sk_buff *skb, struct nlmsghdr *nlh,
ifm = nlmsg_data(nlh);
if (ifm->ifi_index > 0)
dev = __dev_get_by_index(net, ifm->ifi_index);
- else if (ifm->ifi_index < 0) {
- NL_SET_ERR_MSG(extack, "ifindex can't be negative");
- return -EINVAL;
- } else if (tb[IFLA_IFNAME])
+ else if (tb[IFLA_IFNAME])
dev = __dev_get_by_name(net, ifname);
else
goto errout;
@@ -2973,9 +2970,12 @@ static int rtnl_newlink(struct sk_buff *skb, struct nlmsghdr *nlh,
ifname[0] = '\0';
ifm = nlmsg_data(nlh);
- if (ifm->ifi_index > 0)
+ if (ifm->ifi_index > 0) {
dev = __dev_get_by_index(net, ifm->ifi_index);
- else {
+ } else if (ifm->ifi_index < 0) {
+ NL_SET_ERR_MSG(extack, "ifindex can't be negative");
+ return -EINVAL;
+ } else {
if (ifname[0])
dev = __dev_get_by_name(net, ifname);
else
diff --git a/net/dccp/ipv4.c b/net/dccp/ipv4.c
index b2fc9ef7708f27abf2cef06959cfd02c540b4bdb..892fbd1f650da6a1359fbb5c8bd7aca6936026ea 100644
--- a/net/dccp/ipv4.c
+++ b/net/dccp/ipv4.c
@@ -247,13 +247,8 @@ static void dccp_v4_err(struct sk_buff *skb, u32 info)
int err;
struct net *net = dev_net(skb->dev);
- /* For the first __dccp_basic_hdr_len() check, we only need dh->dccph_x,
- * which is in byte 7 of the dccp header.
- * Our caller (icmp_socket_deliver()) already pulled 8 bytes for us.
- *
- * Later on, we want to access the sequence number fields, which are
- * beyond 8 bytes, so we have to pskb_may_pull() ourselves.
- */
+ if (!pskb_may_pull(skb, offset + sizeof(*dh)))
+ return;
dh = (struct dccp_hdr *)(skb->data + offset);
if (!pskb_may_pull(skb, offset + __dccp_basic_hdr_len(dh)))
return;
diff --git a/net/dccp/ipv6.c b/net/dccp/ipv6.c
index f8d8caa967b11066ae4d245b307577e2d3b067e8..9b8c6cf0e5eee4eea40083940695906270a4baf5 100644
--- a/net/dccp/ipv6.c
+++ b/net/dccp/ipv6.c
@@ -80,13 +80,8 @@ static void dccp_v6_err(struct sk_buff *skb, struct inet6_skb_parm *opt,
__u64 seq;
struct net *net = dev_net(skb->dev);
- /* For the first __dccp_basic_hdr_len() check, we only need dh->dccph_x,
- * which is in byte 7 of the dccp header.
- * Our caller (icmpv6_notify()) already pulled 8 bytes for us.
- *
- * Later on, we want to access the sequence number fields, which are
- * beyond 8 bytes, so we have to pskb_may_pull() ourselves.
- */
+ if (!pskb_may_pull(skb, offset + sizeof(*dh)))
+ return;
dh = (struct dccp_hdr *)(skb->data + offset);
if (!pskb_may_pull(skb, offset + __dccp_basic_hdr_len(dh)))
return;
diff --git a/net/ipv4/esp4.c b/net/ipv4/esp4.c
index 203569500b91468ee957716446dccd7a448879bb..24cd5c9c78392124e81817124f0e7a2e989051e3 100644
--- a/net/ipv4/esp4.c
+++ b/net/ipv4/esp4.c
@@ -565,7 +565,9 @@ static inline int esp_remove_trailer(struct sk_buff *skb)
skb->csum = csum_block_sub(skb->csum, csumdiff,
skb->len - trimlen);
}
- pskb_trim(skb, skb->len - trimlen);
+ ret = pskb_trim(skb, skb->len - trimlen);
+ if (unlikely(ret))
+ return ret;
ret = nexthdr[1];
diff --git a/net/ipv4/route.c b/net/ipv4/route.c
index 57e2316529d00529848ec9f3d9a4a9da904ba0bb..9753d07bfc0bf1d4bb15835bf649b001362617f8 100644
--- a/net/ipv4/route.c
+++ b/net/ipv4/route.c
@@ -1215,6 +1215,7 @@ static struct dst_entry *ipv4_dst_check(struct dst_entry *dst, u32 cookie)
static void ipv4_send_dest_unreach(struct sk_buff *skb)
{
+ struct net_device *dev;
struct ip_options opt;
int res;
@@ -1232,7 +1233,8 @@ static void ipv4_send_dest_unreach(struct sk_buff *skb)
opt.optlen = ip_hdr(skb)->ihl * 4 - sizeof(struct iphdr);
rcu_read_lock();
- res = __ip_options_compile(dev_net(skb->dev), &opt, skb, NULL);
+ dev = skb->dev ? skb->dev : skb_rtable(skb)->dst.dev;
+ res = __ip_options_compile(dev_net(dev), &opt, skb, NULL);
rcu_read_unlock();
if (res)
diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c
index 3156739acb87cd495d3f9f60cfaaa70e1c956c17..4ad989df2aaecb1a5f6a872945ac3a98a77f472f 100644
--- a/net/ipv4/tcp_input.c
+++ b/net/ipv4/tcp_input.c
@@ -172,6 +172,19 @@ static void tcp_measure_rcv_mss(struct sock *sk, const struct sk_buff *skb)
if (unlikely(len > icsk->icsk_ack.rcv_mss +
MAX_TCP_OPTION_SPACE))
tcp_gro_dev_warn(sk, skb, len);
+ /* If the skb has a len of exactly 1*MSS and has the PSH bit
+ * set then it is likely the end of an application write. So
+ * more data may not be arriving soon, and yet the data sender
+ * may be waiting for an ACK if cwnd-bound or using TX zero
+ * copy. So we set ICSK_ACK_PUSHED here so that
+ * tcp_cleanup_rbuf() will send an ACK immediately if the app
+ * reads all of the data and is not ping-pong. If len > MSS
+ * then this logic does not matter (and does not hurt) because
+ * tcp_cleanup_rbuf() will always ACK immediately if the app
+ * reads data and there is more than an MSS of unACKed data.
+ */
+ if (TCP_SKB_CB(skb)->tcp_flags & TCPHDR_PSH)
+ icsk->icsk_ack.pending |= ICSK_ACK_PUSHED;
} else {
/* Otherwise, we make more careful check taking into account,
* that SACKs block is variable.
diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
index 293c8cd3adfad0057ddbf8a21b22d5216c05a039..c5fdbfc43e87ed91f3bc992baded5c2283618981 100644
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
@@ -164,8 +164,7 @@ static void tcp_event_data_sent(struct tcp_sock *tp,
}
/* Account for an ACK we sent. */
-static inline void tcp_event_ack_sent(struct sock *sk, unsigned int pkts,
- u32 rcv_nxt)
+static inline void tcp_event_ack_sent(struct sock *sk, u32 rcv_nxt)
{
struct tcp_sock *tp = tcp_sk(sk);
@@ -179,7 +178,7 @@ static inline void tcp_event_ack_sent(struct sock *sk, unsigned int pkts,
if (unlikely(rcv_nxt != tp->rcv_nxt))
return; /* Special ACK sent by DCTCP to reflect ECN */
- tcp_dec_quickack_mode(sk, pkts);
+ tcp_dec_quickack_mode(sk);
inet_csk_clear_xmit_timer(sk, ICSK_TIME_DACK);
}
@@ -1139,7 +1138,7 @@ static int __tcp_transmit_skb(struct sock *sk, struct sk_buff *skb,
icsk->icsk_af_ops->send_check(sk, skb);
if (likely(tcb->tcp_flags & TCPHDR_ACK))
- tcp_event_ack_sent(sk, tcp_skb_pcount(skb), rcv_nxt);
+ tcp_event_ack_sent(sk, rcv_nxt);
if (skb->len != tcp_header_size) {
tcp_event_data_sent(tp, sk);
@@ -2224,6 +2223,18 @@ static int tcp_mtu_probe(struct sock *sk)
return -1;
}
+static bool tcp_rtx_queue_empty_or_single_skb(const struct sock *sk)
+{
+ const struct rb_node *node = sk->tcp_rtx_queue.rb_node;
+
+ /* No skb in the rtx queue. */
+ if (!node)
+ return true;
+
+ /* Only one skb in rtx queue. */
+ return !node->rb_left && !node->rb_right;
+}
+
/* TCP Small Queues :
* Control number of packets in qdisc/devices to two packets / or ~1 ms.
* (These limits are doubled for retransmits)
@@ -2246,12 +2257,12 @@ static bool tcp_small_queue_check(struct sock *sk, const struct sk_buff *skb,
limit <<= factor;
if (refcount_read(&sk->sk_wmem_alloc) > limit) {
- /* Always send skb if rtx queue is empty.
+ /* Always send skb if rtx queue is empty or has one skb.
* No need to wait for TX completion to call us back,
* after softirq/tasklet schedule.
* This helps when TX completions are delayed too much.
*/
- if (tcp_rtx_queue_empty(sk))
+ if (tcp_rtx_queue_empty_or_single_skb(sk))
return false;
set_bit(TSQ_THROTTLED, &sk->sk_tsq_flags);
@@ -2453,7 +2464,7 @@ bool tcp_schedule_loss_probe(struct sock *sk, bool advancing_rto)
{
struct inet_connection_sock *icsk = inet_csk(sk);
struct tcp_sock *tp = tcp_sk(sk);
- u32 timeout, rto_delta_us;
+ u32 timeout, timeout_us, rto_delta_us;
int early_retrans;
/* Don't do any loss probe on a Fast Open connection before 3WHS
@@ -2477,11 +2488,12 @@ bool tcp_schedule_loss_probe(struct sock *sk, bool advancing_rto)
* sample is available then probe after TCP_TIMEOUT_INIT.
*/
if (tp->srtt_us) {
- timeout = usecs_to_jiffies(tp->srtt_us >> 2);
+ timeout_us = tp->srtt_us >> 2;
if (tp->packets_out == 1)
- timeout += TCP_RTO_MIN;
+ timeout_us += tcp_rto_min_us(sk);
else
- timeout += TCP_TIMEOUT_MIN;
+ timeout_us += TCP_TIMEOUT_MIN_US;
+ timeout = usecs_to_jiffies(timeout_us);
} else {
timeout = TCP_TIMEOUT_INIT;
}
diff --git a/net/ipv4/tcp_recovery.c b/net/ipv4/tcp_recovery.c
index 61969bb9395c71844703674e6382a3af559c5c1a..844ff390f7263ec061559d5ebd1396b59dae7fa6 100644
--- a/net/ipv4/tcp_recovery.c
+++ b/net/ipv4/tcp_recovery.c
@@ -122,7 +122,7 @@ bool tcp_rack_mark_lost(struct sock *sk)
tp->rack.advanced = 0;
tcp_rack_detect_loss(sk, &timeout);
if (timeout) {
- timeout = usecs_to_jiffies(timeout) + TCP_TIMEOUT_MIN;
+ timeout = usecs_to_jiffies(timeout + TCP_TIMEOUT_MIN_US);
inet_csk_reset_xmit_timer(sk, ICSK_TIME_REO_TIMEOUT,
timeout, inet_csk(sk)->icsk_rto);
}
diff --git a/net/ipv6/esp6.c b/net/ipv6/esp6.c
index d847ffbe974519d943b6d8b19f39ce229c80188c..6529e46ad09147ab8300e2b9ec02cd68471903a4 100644
--- a/net/ipv6/esp6.c
+++ b/net/ipv6/esp6.c
@@ -517,7 +517,9 @@ static inline int esp_remove_trailer(struct sk_buff *skb)
skb->csum = csum_block_sub(skb->csum, csumdiff,
skb->len - trimlen);
}
- pskb_trim(skb, skb->len - trimlen);
+ ret = pskb_trim(skb, skb->len - trimlen);
+ if (unlikely(ret))
+ return ret;
ret = nexthdr[1];
diff --git a/net/ipv6/xfrm6_policy.c b/net/ipv6/xfrm6_policy.c
index 1925fb91e514a27ae81ee421bdb4475e8dc16f77..a1dfe4f5ed3a482ed8f4b31ba4433459075b5a7d 100644
--- a/net/ipv6/xfrm6_policy.c
+++ b/net/ipv6/xfrm6_policy.c
@@ -243,11 +243,11 @@ static void xfrm6_dst_destroy(struct dst_entry *dst)
{
struct xfrm_dst *xdst = (struct xfrm_dst *)dst;
- if (likely(xdst->u.rt6.rt6i_idev))
- in6_dev_put(xdst->u.rt6.rt6i_idev);
dst_destroy_metrics_generic(dst);
if (xdst->u.rt6.rt6i_uncached_list)
rt6_uncached_list_del(&xdst->u.rt6);
+ if (likely(xdst->u.rt6.rt6i_idev))
+ in6_dev_put(xdst->u.rt6.rt6i_idev);
xfrm_dst_destroy(xdst);
}
diff --git a/net/l2tp/l2tp_ip6.c b/net/l2tp/l2tp_ip6.c
index f3f0b4b7c386338ecca831bf28868a2d1e3ece86..7342344d99a9707bbea694d9b7a943769951d93e 100644
--- a/net/l2tp/l2tp_ip6.c
+++ b/net/l2tp/l2tp_ip6.c
@@ -525,7 +525,6 @@ static int l2tp_ip6_sendmsg(struct sock *sk, struct msghdr *msg, size_t len)
*/
if (len > INT_MAX - transhdrlen)
return -EMSGSIZE;
- ulen = len + transhdrlen;
/* Mirror BSD error message compatibility */
if (msg->msg_flags & MSG_OOB)
@@ -649,6 +648,7 @@ static int l2tp_ip6_sendmsg(struct sock *sk, struct msghdr *msg, size_t len)
back_from_confirm:
lock_sock(sk);
+ ulen = len + skb_queue_empty(&sk->sk_write_queue) ? transhdrlen : 0;
err = ip6_append_data(sk, ip_generic_getfrag, msg,
ulen, transhdrlen, &ipc6,
&fl6, (struct rt6_info *)dst,
diff --git a/net/mac80211/tx.c b/net/mac80211/tx.c
index 3de260b0df7164b76b5a640ae7966153bfd49fe0..89f6b64cac21c5de60df9ec12192b77e01c08a49 100644
--- a/net/mac80211/tx.c
+++ b/net/mac80211/tx.c
@@ -655,7 +655,8 @@ ieee80211_tx_h_select_key(struct ieee80211_tx_data *tx)
}
if (unlikely(tx->key && tx->key->flags & KEY_FLAG_TAINTED &&
- !ieee80211_is_deauth(hdr->frame_control)))
+ !ieee80211_is_deauth(hdr->frame_control)) &&
+ tx->skb->protocol != tx->sdata->control_port_protocol)
return TX_DROP;
if (!skip_hw && tx->key &&
diff --git a/net/netfilter/ipvs/ip_vs_sync.c b/net/netfilter/ipvs/ip_vs_sync.c
index f6af13c16cf57cb5a311477531360256831436bc..c133ce825c2dd1fd4e7cd6866e47fe84ec33ac0d 100644
--- a/net/netfilter/ipvs/ip_vs_sync.c
+++ b/net/netfilter/ipvs/ip_vs_sync.c
@@ -1444,7 +1444,7 @@ static int bind_mcastif_addr(struct socket *sock, struct net_device *dev)
sin.sin_addr.s_addr = addr;
sin.sin_port = 0;
- return sock->ops->bind(sock, (struct sockaddr*)&sin, sizeof(sin));
+ return kernel_bind(sock, (struct sockaddr *)&sin, sizeof(sin));
}
static void get_mcast_sockaddr(union ipvs_sockaddr *sa, int *salen,
@@ -1510,8 +1510,8 @@ static int make_send_sock(struct netns_ipvs *ipvs, int id,
}
get_mcast_sockaddr(&mcast_addr, &salen, &ipvs->mcfg, id);
- result = sock->ops->connect(sock, (struct sockaddr *) &mcast_addr,
- salen, 0);
+ result = kernel_connect(sock, (struct sockaddr *)&mcast_addr,
+ salen, 0);
if (result < 0) {
pr_err("Error connecting to the multicast addr\n");
goto error;
@@ -1551,7 +1551,7 @@ static int make_receive_sock(struct netns_ipvs *ipvs, int id,
get_mcast_sockaddr(&mcast_addr, &salen, &ipvs->bcfg, id);
sock->sk->sk_bound_dev_if = dev->ifindex;
- result = sock->ops->bind(sock, (struct sockaddr *)&mcast_addr, salen);
+ result = kernel_bind(sock, (struct sockaddr *)&mcast_addr, salen);
if (result < 0) {
pr_err("Error binding to the multicast addr\n");
goto error;
diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c
index 0ff8f1006c6b92e307b1e1d998e9e76664aae91a..3e3044116289638e9ee4b142123a91b5cda30f4e 100644
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
@@ -993,8 +993,7 @@ static int nft_flush_table(struct nft_ctx *ctx)
if (!nft_is_active_next(ctx->net, set))
continue;
- if (nft_set_is_anonymous(set) &&
- !list_empty(&set->bindings))
+ if (nft_set_is_anonymous(set))
continue;
err = nft_delset(ctx, set);
@@ -4902,8 +4901,10 @@ static int nf_tables_delsetelem(struct net *net, struct sock *nlsk,
if (IS_ERR(set))
return PTR_ERR(set);
- if (!list_empty(&set->bindings) &&
- (set->flags & (NFT_SET_CONSTANT | NFT_SET_ANONYMOUS)))
+ if (nft_set_is_anonymous(set))
+ return -EOPNOTSUPP;
+
+ if (!list_empty(&set->bindings) && (set->flags & NFT_SET_CONSTANT))
return -EBUSY;
if (nla[NFTA_SET_ELEM_LIST_ELEMENTS] == NULL) {
diff --git a/net/netfilter/nft_payload.c b/net/netfilter/nft_payload.c
index 77cfd5182784ffb3a2c7fd5afb455e73683bc450..0ef51c81ec94cf79a9fd58c849f3532070b7cf2e 100644
--- a/net/netfilter/nft_payload.c
+++ b/net/netfilter/nft_payload.c
@@ -84,7 +84,7 @@ static void nft_payload_eval(const struct nft_expr *expr,
switch (priv->base) {
case NFT_PAYLOAD_LL_HEADER:
- if (!skb_mac_header_was_set(skb))
+ if (!skb_mac_header_was_set(skb) || skb_mac_header_len(skb) == 0)
goto err;
if (skb_vlan_tag_present(skb)) {
diff --git a/net/netfilter/nft_set_rbtree.c b/net/netfilter/nft_set_rbtree.c
index 78a0f428378703128b8b3106bb23fa2e45a28194..9c7ec2ec1fcfea416674d5be70c0848ab95b117f 100644
--- a/net/netfilter/nft_set_rbtree.c
+++ b/net/netfilter/nft_set_rbtree.c
@@ -326,6 +326,8 @@ static void *nft_rbtree_deactivate(const struct net *net,
nft_rbtree_interval_end(this)) {
parent = parent->rb_right;
continue;
+ } else if (nft_set_elem_expired(&rbe->ext)) {
+ break;
} else if (!nft_set_elem_active(&rbe->ext, genmask)) {
parent = parent->rb_left;
continue;
diff --git a/net/nfc/llcp_core.c b/net/nfc/llcp_core.c
index bdc1a9d0965afe1bd60f0f15723d33286e689759..c30b28465e6449a35bde60cd8bf159e530159020 100644
--- a/net/nfc/llcp_core.c
+++ b/net/nfc/llcp_core.c
@@ -216,17 +216,13 @@ static struct nfc_llcp_sock *nfc_llcp_sock_get(struct nfc_llcp_local *local,
if (tmp_sock->ssap == ssap && tmp_sock->dsap == dsap) {
llcp_sock = tmp_sock;
+ sock_hold(&llcp_sock->sk);
break;
}
}
read_unlock(&local->sockets.lock);
- if (llcp_sock == NULL)
- return NULL;
-
- sock_hold(&llcp_sock->sk);
-
return llcp_sock;
}
@@ -338,7 +334,8 @@ static int nfc_llcp_wks_sap(const char *service_name, size_t service_name_len)
static
struct nfc_llcp_sock *nfc_llcp_sock_from_sn(struct nfc_llcp_local *local,
- const u8 *sn, size_t sn_len)
+ const u8 *sn, size_t sn_len,
+ bool needref)
{
struct sock *sk;
struct nfc_llcp_sock *llcp_sock, *tmp_sock;
@@ -374,6 +371,8 @@ struct nfc_llcp_sock *nfc_llcp_sock_from_sn(struct nfc_llcp_local *local,
if (memcmp(sn, tmp_sock->service_name, sn_len) == 0) {
llcp_sock = tmp_sock;
+ if (needref)
+ sock_hold(&llcp_sock->sk);
break;
}
}
@@ -415,7 +414,8 @@ u8 nfc_llcp_get_sdp_ssap(struct nfc_llcp_local *local,
* to this service name.
*/
if (nfc_llcp_sock_from_sn(local, sock->service_name,
- sock->service_name_len) != NULL) {
+ sock->service_name_len,
+ false) != NULL) {
mutex_unlock(&local->sdp_lock);
return LLCP_SAP_MAX;
@@ -816,16 +816,7 @@ static struct nfc_llcp_sock *nfc_llcp_connecting_sock_get(struct nfc_llcp_local
static struct nfc_llcp_sock *nfc_llcp_sock_get_sn(struct nfc_llcp_local *local,
const u8 *sn, size_t sn_len)
{
- struct nfc_llcp_sock *llcp_sock;
-
- llcp_sock = nfc_llcp_sock_from_sn(local, sn, sn_len);
-
- if (llcp_sock == NULL)
- return NULL;
-
- sock_hold(&llcp_sock->sk);
-
- return llcp_sock;
+ return nfc_llcp_sock_from_sn(local, sn, sn_len, true);
}
static const u8 *nfc_llcp_connect_sn(const struct sk_buff *skb, size_t *sn_len)
@@ -1290,7 +1281,8 @@ static void nfc_llcp_recv_snl(struct nfc_llcp_local *local,
}
llcp_sock = nfc_llcp_sock_from_sn(local, service_name,
- service_name_len);
+ service_name_len,
+ true);
if (!llcp_sock) {
sap = 0;
goto add_snl;
@@ -1310,6 +1302,7 @@ static void nfc_llcp_recv_snl(struct nfc_llcp_local *local,
if (sap == LLCP_SAP_MAX) {
sap = 0;
+ nfc_llcp_sock_put(llcp_sock);
goto add_snl;
}
@@ -1327,6 +1320,7 @@ static void nfc_llcp_recv_snl(struct nfc_llcp_local *local,
pr_debug("%p %d\n", llcp_sock, sap);
+ nfc_llcp_sock_put(llcp_sock);
add_snl:
sdp = nfc_llcp_build_sdres_tlv(tid, sap);
if (sdp == NULL)
diff --git a/net/nfc/nci/core.c b/net/nfc/nci/core.c
index 66608e6c5b0ec4236f5aedf3ad613cbb5bc443c9..33723d843e4727bc2437cbc971f1a4735d754422 100644
--- a/net/nfc/nci/core.c
+++ b/net/nfc/nci/core.c
@@ -906,6 +906,11 @@ static int nci_activate_target(struct nfc_dev *nfc_dev,
return -EINVAL;
}
+ if (protocol >= NFC_PROTO_MAX) {
+ pr_err("the requested nfc protocol is invalid\n");
+ return -EINVAL;
+ }
+
if (!(nci_target->supported_protocols & (1 << protocol))) {
pr_err("target does not support the requested protocol 0x%x\n",
protocol);
diff --git a/net/nfc/nci/spi.c b/net/nfc/nci/spi.c
index 452f4c16b7a9a032f278c9c8541e4c646b3efc84..d2de7fc226f04f9d5a2446ec8054c6718e16e049 100644
--- a/net/nfc/nci/spi.c
+++ b/net/nfc/nci/spi.c
@@ -163,6 +163,8 @@ static int send_acknowledge(struct nci_spi *nspi, u8 acknowledge)
int ret;
skb = nci_skb_alloc(nspi->ndev, 0, GFP_KERNEL);
+ if (!skb)
+ return -ENOMEM;
/* add the NCI SPI header to the start of the buffer */
hdr = skb_push(skb, NCI_SPI_HDR_LEN);
diff --git a/net/rds/tcp_connect.c b/net/rds/tcp_connect.c
index 008f50fb25dd24f572aba43a8d9c58e9c7bd8cea..63efe60fda1fe5a79a9c4e8863b3871d1dc5a623 100644
--- a/net/rds/tcp_connect.c
+++ b/net/rds/tcp_connect.c
@@ -141,7 +141,7 @@ int rds_tcp_conn_path_connect(struct rds_conn_path *cp)
addrlen = sizeof(sin);
}
- ret = sock->ops->bind(sock, addr, addrlen);
+ ret = kernel_bind(sock, addr, addrlen);
if (ret) {
rdsdebug("bind failed with %d at address %pI6c\n",
ret, &conn->c_laddr);
@@ -169,7 +169,7 @@ int rds_tcp_conn_path_connect(struct rds_conn_path *cp)
* own the socket
*/
rds_tcp_set_callbacks(sock, cp);
- ret = sock->ops->connect(sock, addr, addrlen, O_NONBLOCK);
+ ret = kernel_connect(sock, addr, addrlen, O_NONBLOCK);
rdsdebug("connect to address %pI6c returned %d\n", &conn->c_faddr, ret);
if (ret == -EINPROGRESS)
diff --git a/net/rds/tcp_listen.c b/net/rds/tcp_listen.c
index 0d095d3f5feecfdfddb9e58574a548ec4936c193..37f4a8ca3ac8788449bf53fbc9c0322bc668463a 100644
--- a/net/rds/tcp_listen.c
+++ b/net/rds/tcp_listen.c
@@ -332,7 +332,7 @@ struct socket *rds_tcp_listen_init(struct net *net, bool isv6)
addr_len = sizeof(*sin);
}
- ret = sock->ops->bind(sock, (struct sockaddr *)&ss, addr_len);
+ ret = kernel_bind(sock, (struct sockaddr *)&ss, addr_len);
if (ret < 0) {
rdsdebug("could not bind %s listener socket: %d\n",
isv6 ? "IPv6" : "IPv4", ret);
diff --git a/net/rfkill/rfkill-gpio.c b/net/rfkill/rfkill-gpio.c
index 0f846585225431c6ae903bd8308884729c99bb3c..af0842744fc8117f72c1e4ac6816ba8fe5129dc5 100644
--- a/net/rfkill/rfkill-gpio.c
+++ b/net/rfkill/rfkill-gpio.c
@@ -112,13 +112,13 @@ static int rfkill_gpio_probe(struct platform_device *pdev)
rfkill->clk = devm_clk_get(&pdev->dev, NULL);
- gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
+ gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_ASIS);
if (IS_ERR(gpio))
return PTR_ERR(gpio);
rfkill->reset_gpio = gpio;
- gpio = devm_gpiod_get_optional(&pdev->dev, "shutdown", GPIOD_OUT_LOW);
+ gpio = devm_gpiod_get_optional(&pdev->dev, "shutdown", GPIOD_ASIS);
if (IS_ERR(gpio))
return PTR_ERR(gpio);
diff --git a/net/sched/sch_hfsc.c b/net/sched/sch_hfsc.c
index fa3d2fd4990cec2b14ca7674b9bddfe2cde12bf0..e71443623d679e797c215b06e12611b84ec8ff28 100644
--- a/net/sched/sch_hfsc.c
+++ b/net/sched/sch_hfsc.c
@@ -913,6 +913,14 @@ hfsc_change_usc(struct hfsc_class *cl, struct tc_service_curve *usc,
cl->cl_flags |= HFSC_USC;
}
+static void
+hfsc_upgrade_rt(struct hfsc_class *cl)
+{
+ cl->cl_fsc = cl->cl_rsc;
+ rtsc_init(&cl->cl_virtual, &cl->cl_fsc, cl->cl_vt, cl->cl_total);
+ cl->cl_flags |= HFSC_FSC;
+}
+
static const struct nla_policy hfsc_policy[TCA_HFSC_MAX + 1] = {
[TCA_HFSC_RSC] = { .len = sizeof(struct tc_service_curve) },
[TCA_HFSC_FSC] = { .len = sizeof(struct tc_service_curve) },
@@ -1021,10 +1029,6 @@ hfsc_change_class(struct Qdisc *sch, u32 classid, u32 parentid,
if (parent == NULL)
return -ENOENT;
}
- if (!(parent->cl_flags & HFSC_FSC) && parent != &q->root) {
- NL_SET_ERR_MSG(extack, "Invalid parent - parent class must have FSC");
- return -EINVAL;
- }
if (classid == 0 || TC_H_MAJ(classid ^ sch->handle) != 0)
return -EINVAL;
@@ -1077,6 +1081,12 @@ hfsc_change_class(struct Qdisc *sch, u32 classid, u32 parentid,
cl->cf_tree = RB_ROOT;
sch_tree_lock(sch);
+ /* Check if the inner class is a misconfigured 'rt' */
+ if (!(parent->cl_flags & HFSC_FSC) && parent != &q->root) {
+ NL_SET_ERR_MSG(extack,
+ "Forced curve change on parent 'rt' to 'sc'");
+ hfsc_upgrade_rt(parent);
+ }
qdisc_class_hash_insert(&q->clhash, &cl->cl_common);
list_add_tail(&cl->siblings, &parent->children);
if (parent->level == 0)
diff --git a/net/sctp/associola.c b/net/sctp/associola.c
index d17708800652a38b442b162cff4435470013554b..78c1429d1301c63b009e2856e356d0b6d6e3c8e1 100644
--- a/net/sctp/associola.c
+++ b/net/sctp/associola.c
@@ -1181,8 +1181,7 @@ int sctp_assoc_update(struct sctp_association *asoc,
/* Add any peer addresses from the new association. */
list_for_each_entry(trans, &new->peer.transport_addr_list,
transports)
- if (!sctp_assoc_lookup_paddr(asoc, &trans->ipaddr) &&
- !sctp_assoc_add_peer(asoc, &trans->ipaddr,
+ if (!sctp_assoc_add_peer(asoc, &trans->ipaddr,
GFP_ATOMIC, trans->state))
return -ENOMEM;
diff --git a/net/sctp/socket.c b/net/sctp/socket.c
index 432dccd3750647a8dbca7f10b7b057b33b7ee748..f954d3c8876db0b2bbce73df24f88e53875c6e61 100644
--- a/net/sctp/socket.c
+++ b/net/sctp/socket.c
@@ -2578,6 +2578,7 @@ static int sctp_apply_peer_addr_params(struct sctp_paddrparams *params,
if (trans) {
trans->hbinterval =
msecs_to_jiffies(params->spp_hbinterval);
+ sctp_transport_reset_hb_timer(trans);
} else if (asoc) {
asoc->hbinterval =
msecs_to_jiffies(params->spp_hbinterval);
diff --git a/net/socket.c b/net/socket.c
index 07b1738c3f9f6af7faea243f896789c9674fa790..eb39001809ac67dcf38412ebe758a2e6e33e0522 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -90,6 +90,7 @@
#include
#include
#include
+#include
#include
#include
@@ -108,6 +109,13 @@
#include
#include
+/* proto_ops for ipv4 and ipv6 use the same {recv,send}msg function */
+#if IS_ENABLED(CONFIG_INET)
+#define INDIRECT_CALL_INET4(f, f1, ...) INDIRECT_CALL_1(f, f1, __VA_ARGS__)
+#else
+#define INDIRECT_CALL_INET4(f, f1, ...) f(__VA_ARGS__)
+#endif
+
#ifdef CONFIG_NET_RX_BUSY_POLL
unsigned int sysctl_net_busy_read __read_mostly;
unsigned int sysctl_net_busy_poll __read_mostly;
@@ -647,29 +655,48 @@ void __sock_tx_timestamp(__u16 tsflags, __u8 *tx_flags)
}
EXPORT_SYMBOL(__sock_tx_timestamp);
-/**
- * sock_sendmsg - send a message through @sock
- * @sock: socket
- * @msg: message to send
- *
- * Sends @msg through @sock, passing through LSM.
- * Returns the number of bytes sent, or an error code.
- */
-
+INDIRECT_CALLABLE_DECLARE(int inet_sendmsg(struct socket *, struct msghdr *,
+ size_t));
static inline int sock_sendmsg_nosec(struct socket *sock, struct msghdr *msg)
{
- int ret = sock->ops->sendmsg(sock, msg, msg_data_left(msg));
+ int ret = INDIRECT_CALL_INET4(sock->ops->sendmsg, inet_sendmsg, sock,
+ msg, msg_data_left(msg));
BUG_ON(ret == -EIOCBQUEUED);
return ret;
}
-int sock_sendmsg(struct socket *sock, struct msghdr *msg)
+static int __sock_sendmsg(struct socket *sock, struct msghdr *msg)
{
int err = security_socket_sendmsg(sock, msg,
msg_data_left(msg));
return err ?: sock_sendmsg_nosec(sock, msg);
}
+
+/**
+ * sock_sendmsg - send a message through @sock
+ * @sock: socket
+ * @msg: message to send
+ *
+ * Sends @msg through @sock, passing through LSM.
+ * Returns the number of bytes sent, or an error code.
+ */
+int sock_sendmsg(struct socket *sock, struct msghdr *msg)
+{
+ struct sockaddr_storage *save_addr = (struct sockaddr_storage *)msg->msg_name;
+ struct sockaddr_storage address;
+ int ret;
+
+ if (msg->msg_name) {
+ memcpy(&address, msg->msg_name, msg->msg_namelen);
+ msg->msg_name = &address;
+ }
+
+ ret = __sock_sendmsg(sock, msg);
+ msg->msg_name = save_addr;
+
+ return ret;
+}
EXPORT_SYMBOL(sock_sendmsg);
/**
@@ -853,6 +880,15 @@ void __sock_recv_ts_and_drops(struct msghdr *msg, struct sock *sk,
}
EXPORT_SYMBOL_GPL(__sock_recv_ts_and_drops);
+INDIRECT_CALLABLE_DECLARE(int inet_recvmsg(struct socket *, struct msghdr *,
+ size_t , int ));
+static inline int sock_recvmsg_nosec(struct socket *sock, struct msghdr *msg,
+ int flags)
+{
+ return INDIRECT_CALL_INET4(sock->ops->recvmsg, inet_recvmsg, sock, msg,
+ msg_data_left(msg), flags);
+}
+
/**
* sock_recvmsg - receive a message from @sock
* @sock: socket
@@ -862,13 +898,6 @@ EXPORT_SYMBOL_GPL(__sock_recv_ts_and_drops);
* Receives @msg from @sock, passing through LSM. Returns the total number
* of bytes received, or an error.
*/
-
-static inline int sock_recvmsg_nosec(struct socket *sock, struct msghdr *msg,
- int flags)
-{
- return sock->ops->recvmsg(sock, msg, msg_data_left(msg), flags);
-}
-
int sock_recvmsg(struct socket *sock, struct msghdr *msg, int flags)
{
int err = security_socket_recvmsg(sock, msg, msg_data_left(msg), flags);
@@ -973,7 +1002,7 @@ static ssize_t sock_write_iter(struct kiocb *iocb, struct iov_iter *from)
if (sock->type == SOCK_SEQPACKET)
msg.msg_flags |= MSG_EOR;
- res = sock_sendmsg(sock, &msg);
+ res = __sock_sendmsg(sock, &msg);
*from = msg.msg_iter;
return res;
}
@@ -1918,7 +1947,7 @@ int __sys_sendto(int fd, void __user *buff, size_t len, unsigned int flags,
if (sock->file->f_flags & O_NONBLOCK)
flags |= MSG_DONTWAIT;
msg.msg_flags = flags;
- err = sock_sendmsg(sock, &msg);
+ err = __sock_sendmsg(sock, &msg);
out_put:
fput_light(sock->file, fput_needed);
@@ -2247,7 +2276,7 @@ static int ___sys_sendmsg(struct socket *sock, struct user_msghdr __user *msg,
err = sock_sendmsg_nosec(sock, msg_sys);
goto out_freectl;
}
- err = sock_sendmsg(sock, msg_sys);
+ err = __sock_sendmsg(sock, msg_sys);
/*
* If this is sendmmsg() and sending to current destination address was
* successful, remember it.
@@ -3421,7 +3450,11 @@ static long compat_sock_ioctl(struct file *file, unsigned int cmd,
int kernel_bind(struct socket *sock, struct sockaddr *addr, int addrlen)
{
- return sock->ops->bind(sock, addr, addrlen);
+ struct sockaddr_storage address;
+
+ memcpy(&address, addr, addrlen);
+
+ return sock->ops->bind(sock, (struct sockaddr *)&address, addrlen);
}
EXPORT_SYMBOL(kernel_bind);
diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c
index 8f01cc67bfbec3c0fde244e8ee3e9406aa19b2a1..f7b545416ff6850e8c208e352573d5e0b2819217 100644
--- a/net/wireless/nl80211.c
+++ b/net/wireless/nl80211.c
@@ -6655,7 +6655,7 @@ static int nl80211_update_mesh_config(struct sk_buff *skb,
struct cfg80211_registered_device *rdev = info->user_ptr[0];
struct net_device *dev = info->user_ptr[1];
struct wireless_dev *wdev = dev->ieee80211_ptr;
- struct mesh_config cfg;
+ struct mesh_config cfg = {};
u32 mask;
int err;
diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c
index 7f40b6aab689b6deaa2272e318b36c0fed26900d..90868df7865e3b522842f76902dba6943eafcb43 100644
--- a/scripts/mod/file2alias.c
+++ b/scripts/mod/file2alias.c
@@ -1395,7 +1395,7 @@ void handle_moddevtable(struct module *mod, struct elf_info *info,
/* First handle the "special" cases */
if (sym_is(name, namelen, "usb"))
do_usb_table(symval, sym->st_size, mod);
- if (sym_is(name, namelen, "of"))
+ else if (sym_is(name, namelen, "of"))
do_of_table(symval, sym->st_size, mod);
else if (sym_is(name, namelen, "pnp"))
do_pnp_device_entry(symval, sym->st_size, mod);
diff --git a/security/smack/smack.h b/security/smack/smack.h
index f7db791fb5660ad14479af3d4b48e104d8bc37ed..62aa4bc25426c4e2d96bae57c27a69d8d6878be8 100644
--- a/security/smack/smack.h
+++ b/security/smack/smack.h
@@ -120,6 +120,7 @@ struct inode_smack {
struct task_smack {
struct smack_known *smk_task; /* label for access control */
struct smack_known *smk_forked; /* label when forked */
+ struct smack_known *smk_transmuted;/* label when transmuted */
struct list_head smk_rules; /* per task access rules */
struct mutex smk_rules_lock; /* lock for the rules */
struct list_head smk_relabel; /* transit allowed labels */
diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c
index 4f65d953fe318165f824cc9a779f23621baad5de..266eb8ca3381863427670dbdab4ab593ab6a1c5b 100644
--- a/security/smack/smack_lsm.c
+++ b/security/smack/smack_lsm.c
@@ -1032,8 +1032,9 @@ static int smack_inode_init_security(struct inode *inode, struct inode *dir,
const struct qstr *qstr, const char **name,
void **value, size_t *len)
{
+ struct task_smack *tsp = current_security();
struct inode_smack *issp = inode->i_security;
- struct smack_known *skp = smk_of_current();
+ struct smack_known *skp = smk_of_task(tsp);
struct smack_known *isp = smk_of_inode(inode);
struct smack_known *dsp = smk_of_inode(dir);
int may;
@@ -1042,20 +1043,34 @@ static int smack_inode_init_security(struct inode *inode, struct inode *dir,
*name = XATTR_SMACK_SUFFIX;
if (value && len) {
- rcu_read_lock();
- may = smk_access_entry(skp->smk_known, dsp->smk_known,
- &skp->smk_rules);
- rcu_read_unlock();
+ /*
+ * If equal, transmuting already occurred in
+ * smack_dentry_create_files_as(). No need to check again.
+ */
+ if (tsp->smk_task != tsp->smk_transmuted) {
+ rcu_read_lock();
+ may = smk_access_entry(skp->smk_known, dsp->smk_known,
+ &skp->smk_rules);
+ rcu_read_unlock();
+ }
/*
- * If the access rule allows transmutation and
- * the directory requests transmutation then
- * by all means transmute.
+ * In addition to having smk_task equal to smk_transmuted,
+ * if the access rule allows transmutation and the directory
+ * requests transmutation then by all means transmute.
* Mark the inode as changed.
*/
- if (may > 0 && ((may & MAY_TRANSMUTE) != 0) &&
- smk_inode_transmutable(dir)) {
- isp = dsp;
+ if ((tsp->smk_task == tsp->smk_transmuted) ||
+ (may > 0 && ((may & MAY_TRANSMUTE) != 0) &&
+ smk_inode_transmutable(dir))) {
+ /*
+ * The caller of smack_dentry_create_files_as()
+ * should have overridden the current cred, so the
+ * inode label was already set correctly in
+ * smack_inode_alloc_security().
+ */
+ if (tsp->smk_task != tsp->smk_transmuted)
+ isp = dsp;
issp->smk_flags |= SMK_INODE_CHANGED;
}
@@ -1490,10 +1505,19 @@ static int smack_inode_getsecurity(struct inode *inode,
struct super_block *sbp;
struct inode *ip = (struct inode *)inode;
struct smack_known *isp;
+ struct inode_smack *ispp;
+ size_t label_len;
+ char *label = NULL;
- if (strcmp(name, XATTR_SMACK_SUFFIX) == 0)
+ if (strcmp(name, XATTR_SMACK_SUFFIX) == 0) {
isp = smk_of_inode(inode);
- else {
+ } else if (strcmp(name, XATTR_SMACK_TRANSMUTE) == 0) {
+ ispp = inode->i_security;
+ if (ispp->smk_flags & SMK_INODE_TRANSMUTE)
+ label = TRANS_TRUE;
+ else
+ label = "";
+ } else {
/*
* The rest of the Smack xattrs are only on sockets.
*/
@@ -1515,13 +1539,18 @@ static int smack_inode_getsecurity(struct inode *inode,
return -EOPNOTSUPP;
}
+ if (!label)
+ label = isp->smk_known;
+
+ label_len = strlen(label);
+
if (alloc) {
- *buffer = kstrdup(isp->smk_known, GFP_KERNEL);
+ *buffer = kstrdup(label, GFP_KERNEL);
if (*buffer == NULL)
return -ENOMEM;
}
- return strlen(isp->smk_known);
+ return label_len;
}
@@ -4612,7 +4641,7 @@ static int smack_inode_copy_up(struct dentry *dentry, struct cred **new)
/*
* Get label from overlay inode and set it in create_sid
*/
- isp = d_inode(dentry->d_parent)->i_security;
+ isp = d_inode(dentry)->i_security;
skp = isp->smk_inode;
tsp->smk_task = skp;
*new = new_creds;
@@ -4663,8 +4692,10 @@ static int smack_dentry_create_files_as(struct dentry *dentry, int mode,
* providing access is transmuting use the containing
* directory label instead of the process label.
*/
- if (may > 0 && (may & MAY_TRANSMUTE))
+ if (may > 0 && (may & MAY_TRANSMUTE)) {
ntsp->smk_task = isp->smk_inode;
+ ntsp->smk_transmuted = ntsp->smk_task;
+ }
}
return 0;
}
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 40d596248fab8204eb899a303a603784751dfa00..aaca36250dda642960e410647dcde0a0ab614aae 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -2364,6 +2364,7 @@ static struct snd_pci_quirk power_save_blacklist[] = {
SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0),
/* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */
SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0),
+ SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0),
/* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */
SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0),
/* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */
diff --git a/sound/soc/pxa/pxa-ssp.c b/sound/soc/pxa/pxa-ssp.c
index 69033e1a84e6ad52ef7c01b395af3a8f48a91c15..49481dadb9230873e9d02089aa016724b9877312 100644
--- a/sound/soc/pxa/pxa-ssp.c
+++ b/sound/soc/pxa/pxa-ssp.c
@@ -795,7 +795,7 @@ static int pxa_ssp_probe(struct snd_soc_dai *dai)
if (IS_ERR(priv->extclk)) {
ret = PTR_ERR(priv->extclk);
if (ret == -EPROBE_DEFER)
- return ret;
+ goto err_priv;
priv->extclk = NULL;
}
diff --git a/techpack/audio/asoc/msm-audio-effects-q6-v2.c b/techpack/audio/asoc/msm-audio-effects-q6-v2.c
index db3bd87ebc0e237101a9b89141bf3c0116d8bfbe..f415e699fb433aca2001a2fe144b585906a2ab97 100644
--- a/techpack/audio/asoc/msm-audio-effects-q6-v2.c
+++ b/techpack/audio/asoc/msm-audio-effects-q6-v2.c
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include
@@ -1002,6 +1003,14 @@ int msm_audio_effects_pbe_handler(struct audio_client *ac,
pbe->config.reserved =
GET_NEXT(values, param_max_offset, rc);
+ if ((pbe->config.bandpass_filter_order > 3) ||
+ (pbe->config.bandpass_filter_order < 1)) {
+ pr_err("%s: Invalid BPF order\n",
+ __func__);
+ rc = -EINVAL;
+ goto invalid_config;
+ }
+
p_coeffs = &pbe->config.p1LowPassCoeffs[0];
lpf_len = (pbe->config.xover_filter_order == 3) ? 10 : 5;
hpf_len = (pbe->config.xover_filter_order == 3) ? 10 : 5;
diff --git a/techpack/audio/asoc/msm-lsm-client.c b/techpack/audio/asoc/msm-lsm-client.c
index 43b8dab7cda5063a5002a8109253d1616dc59cb7..f4a8dbdce4fd209418eeec5093af4e9d33515260 100644
--- a/techpack/audio/asoc/msm-lsm-client.c
+++ b/techpack/audio/asoc/msm-lsm-client.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include
#include
@@ -2430,6 +2431,15 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream,
err = -EFAULT;
goto done;
}
+
+ if (temp_p_info.param_size > 0 &&
+ ((INT_MAX - sizeof(temp_p_info)) <
+ temp_p_info.param_size)) {
+ pr_err("%s: Integer overflow\n", __func__);
+ err = -EINVAL;
+ goto done;
+ }
+
size = sizeof(temp_p_info) + temp_p_info.param_size;
p_info = kzalloc(size, GFP_KERNEL);
diff --git a/techpack/audio/dsp/msm_audio_ion.c b/techpack/audio/dsp/msm_audio_ion.c
index 5bcac6aec2cafeff99d7cff367d35d2682fa97c9..e97d35194b509cdcb2cde7ba02445f81db0bb140 100644
--- a/techpack/audio/dsp/msm_audio_ion.c
+++ b/techpack/audio/dsp/msm_audio_ion.c
@@ -1,7 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2019, 2020, The Linux Foundation. All rights reserved.
- *
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
diff --git a/techpack/audio/dsp/q6afe.c b/techpack/audio/dsp/q6afe.c
index b59c82dec17c4fbea08001632df42b4917105ea8..52b06aa77ee465effbbbaa08b12d64b2c6740c84 100644
--- a/techpack/audio/dsp/q6afe.c
+++ b/techpack/audio/dsp/q6afe.c
@@ -10182,6 +10182,7 @@ static int afe_spv4_get_calib_data(
struct param_hdr_v3 param_hdr;
int port = SLIMBUS_4_TX;
int ret = -EINVAL;
+ uint32_t th_vi_ca_state;
if (!calib_resp) {
pr_err("%s: Invalid params\n", __func__);
@@ -10203,6 +10204,12 @@ static int afe_spv4_get_calib_data(
__func__, port, param_hdr.param_id, ret);
goto get_params_fail;
}
+ th_vi_ca_state = this_afe.spv4_calib_data.res_cfg.th_vi_ca_state;
+ if (th_vi_ca_state < FBSP_INCORRECT_OP_MODE ||
+ th_vi_ca_state > MAX_FBSP_STATE) {
+ pr_err("%s: invalid fbsp state %d\n", __func__, th_vi_ca_state);
+ goto get_params_fail;
+ }
memcpy(&calib_resp->res_cfg, &this_afe.spv4_calib_data.res_cfg,
sizeof(this_afe.calib_data.res_cfg));
pr_info("%s: state %s resistance %d %d\n", __func__,
@@ -10221,6 +10228,7 @@ int afe_spk_prot_get_calib_data(struct afe_spkr_prot_get_vi_calib *calib_resp)
struct param_hdr_v3 param_hdr;
int port = SLIMBUS_4_TX;
int ret = -EINVAL;
+ uint32_t th_vi_ca_state;
if (!calib_resp) {
pr_err("%s: Invalid params\n", __func__);
@@ -10242,6 +10250,12 @@ int afe_spk_prot_get_calib_data(struct afe_spkr_prot_get_vi_calib *calib_resp)
__func__, port, param_hdr.param_id, ret);
goto get_params_fail;
}
+ th_vi_ca_state = this_afe.calib_data.res_cfg.th_vi_ca_state;
+ if (th_vi_ca_state < FBSP_INCORRECT_OP_MODE ||
+ th_vi_ca_state > MAX_FBSP_STATE) {
+ pr_err("%s: invalid fbsp state %d\n", __func__, th_vi_ca_state);
+ goto get_params_fail;
+ }
memcpy(&calib_resp->res_cfg, &this_afe.calib_data.res_cfg,
sizeof(this_afe.calib_data.res_cfg));
pr_info("%s: state %s resistance %d %d\n", __func__,
diff --git a/techpack/audio/dsp/q6asm.c b/techpack/audio/dsp/q6asm.c
index 88f3acf6261879263990eaf19668affa1c9db0b4..2dc8ddec0f2956fcb821780f5bb70b67b5c8c1cd 100644
--- a/techpack/audio/dsp/q6asm.c
+++ b/techpack/audio/dsp/q6asm.c
@@ -2405,7 +2405,16 @@ static int32_t q6asm_callback(struct apr_client_data *data, void *priv)
__func__, data->payload_size);
break;
case ASM_SESSION_CMDRSP_GET_MTMX_STRTR_PARAMS_V2:
- q6asm_process_mtmx_get_param_rsp(ac, (void *) payload);
+ payload_size = sizeof(struct asm_mtmx_strtr_get_params_cmdrsp);
+ if (data->payload_size < payload_size) {
+ pr_err("%s: insufficient payload size = %d\n",
+ __func__, data->payload_size);
+ spin_unlock_irqrestore(
+ &(session[session_id].session_lock), flags);
+ return -EINVAL;
+ }
+ q6asm_process_mtmx_get_param_rsp(ac,
+ (struct asm_mtmx_strtr_get_params_cmdrsp *) payload);
break;
case ASM_STREAM_PP_EVENT:
case ASM_STREAM_CMD_ENCDEC_EVENTS:
diff --git a/techpack/video/msm/vidc/hfi_iris2.c b/techpack/video/msm/vidc/hfi_iris2.c
index 179fb2abaefbf4f8b70fca5c7afe32c7cb9f9ecc..0f16e9b0044fe588b4d527b5ef2cea7acb4a4401 100644
--- a/techpack/video/msm/vidc/hfi_iris2.c
+++ b/techpack/video/msm/vidc/hfi_iris2.c
@@ -2,6 +2,7 @@
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
*/
+#include
#include "msm_vidc_debug.h"
#include "hfi_common.h"
@@ -167,9 +168,9 @@ void __setup_ucregion_memory_map_iris2(struct venus_hfi_device *device, u32 sid)
(u32)device->qdss.align_device_addr, sid);
/* update queues vaddr for debug purpose */
__write_register(device, CPU_CS_VCICMDARG0_IRIS2,
- (u32)device->iface_q_table.align_virtual_addr, sid);
+ (u32)((uintptr_t)device->iface_q_table.align_virtual_addr & UINT_MAX), sid);
__write_register(device, CPU_CS_VCICMDARG1_IRIS2,
- (u32)((u64)device->iface_q_table.align_virtual_addr >> 32),
+ (u32)((uintptr_t)device->iface_q_table.align_virtual_addr >> 32),
sid);
}
diff --git a/techpack/video/msm/vidc/msm_venc.c b/techpack/video/msm/vidc/msm_venc.c
index 2e71b924a58f30cf233debd72039c6a80846ddaa..69c26c565e021b14f06a6ca76742dfcae3c2d5a3 100644
--- a/techpack/video/msm/vidc/msm_venc.c
+++ b/techpack/video/msm/vidc/msm_venc.c
@@ -4628,6 +4628,13 @@ int handle_all_intra_restrictions(struct msm_vidc_inst *inst)
fps_max = capability->cap[CAP_ALLINTRA_MAX_FPS].max;
s_vpr_h(inst->sid, "%s: rc_type %u, fps %u, fps_max %u\n",
__func__, inst->rc_type, n_fps, fps_max);
+ if (inst->all_intra && n_fps > fps_max) {
+ inst->clk_data.frame_rate = fps_max << 16;
+ n_fps = fps_max;
+ s_vpr_h(inst->sid,
+ "%s:cap2 frame rate to %u for allintra encoding",
+ __func__, inst->clk_data.frame_rate >> 16);
+ }
if ((inst->rc_type != V4L2_MPEG_VIDEO_BITRATE_MODE_VBR &&
inst->rc_type != RATE_CONTROL_OFF &&
inst->rc_type != RATE_CONTROL_LOSSLESS) ||
diff --git a/techpack/video/msm/vidc/msm_vidc_common.c b/techpack/video/msm/vidc/msm_vidc_common.c
index 9872a3e058009cca0763c68f2e58b4510652590d..3e968fc92deffd95932546e996b47dfe9d7900c2 100644
--- a/techpack/video/msm/vidc/msm_vidc_common.c
+++ b/techpack/video/msm/vidc/msm_vidc_common.c
@@ -5818,7 +5818,7 @@ static int msm_vidc_check_mbpf_supported(struct msm_vidc_inst *inst)
if (mbpf > core->resources.max_mbpf) {
msm_vidc_print_running_insts(inst->core);
- return -EBUSY;
+ return -ENOMEM;
}
return 0;
@@ -5915,7 +5915,7 @@ int msm_comm_check_memory_supported(struct msm_vidc_inst *vidc_inst)
"%s: video mem overshoot - reached %llu MB, max_limit %llu MB\n",
__func__, total_mem_size >> 20, memory_limit_mbytes);
msm_comm_print_insts_info(core);
- return -EBUSY;
+ return -ENOMEM;
}
if (!is_secure_session(vidc_inst)) {
@@ -5930,7 +5930,7 @@ int msm_comm_check_memory_supported(struct msm_vidc_inst *vidc_inst)
"%s: insufficient device addr space, required %llu, available %llu\n",
__func__, non_sec_mem_size, non_sec_cb_size);
msm_comm_print_insts_info(core);
- return -EINVAL;
+ return -ENOMEM;
}
}
diff --git a/tools/include/uapi/linux/bpf.h b/tools/include/uapi/linux/bpf.h
index 8658af518bdab4093baa386c2becd772c89a16db..0fe33356c251913f2c88526e61975a1235f67222 100644
--- a/tools/include/uapi/linux/bpf.h
+++ b/tools/include/uapi/linux/bpf.h
@@ -693,7 +693,9 @@ union bpf_attr {
* performed again, if the helper is used in combination with
* direct packet access.
* Return
- * 0 on success, or a negative error in case of failure.
+ * 0 on success, or a negative error in case of failure. Positive
+ * error indicates a potential drop or congestion in the target
+ * device. The particular positive error codes are not defined.
*
* u64 bpf_get_current_pid_tgid(void)
* Return
diff --git a/tools/power/cpupower/Makefile b/tools/power/cpupower/Makefile
index 1dd5f4fcffd53f375ba00479bfed37d867399c4a..392906c8d3a62a0a4273ec09246dcdaeee5f50dd 100644
--- a/tools/power/cpupower/Makefile
+++ b/tools/power/cpupower/Makefile
@@ -278,14 +278,14 @@ clean:
$(MAKE) -C bench O=$(OUTPUT) clean
-install-lib:
+install-lib: libcpupower
$(INSTALL) -d $(DESTDIR)${libdir}
$(CP) $(OUTPUT)libcpupower.so* $(DESTDIR)${libdir}/
$(INSTALL) -d $(DESTDIR)${includedir}
$(INSTALL_DATA) lib/cpufreq.h $(DESTDIR)${includedir}/cpufreq.h
$(INSTALL_DATA) lib/cpuidle.h $(DESTDIR)${includedir}/cpuidle.h
-install-tools:
+install-tools: $(OUTPUT)cpupower
$(INSTALL) -d $(DESTDIR)${bindir}
$(INSTALL_PROGRAM) $(OUTPUT)cpupower $(DESTDIR)${bindir}
@@ -299,14 +299,14 @@ install-man:
$(INSTALL_DATA) -D man/cpupower-info.1 $(DESTDIR)${mandir}/man1/cpupower-info.1
$(INSTALL_DATA) -D man/cpupower-monitor.1 $(DESTDIR)${mandir}/man1/cpupower-monitor.1
-install-gmo:
+install-gmo: create-gmo
$(INSTALL) -d $(DESTDIR)${localedir}
for HLANG in $(LANGUAGES); do \
echo '$(INSTALL_DATA) -D $(OUTPUT)po/$$HLANG.gmo $(DESTDIR)${localedir}/$$HLANG/LC_MESSAGES/cpupower.mo'; \
$(INSTALL_DATA) -D $(OUTPUT)po/$$HLANG.gmo $(DESTDIR)${localedir}/$$HLANG/LC_MESSAGES/cpupower.mo; \
done;
-install-bench:
+install-bench: compile-bench
@#DESTDIR must be set from outside to survive
@sbindir=$(sbindir) bindir=$(bindir) docdir=$(docdir) confdir=$(confdir) $(MAKE) -C bench O=$(OUTPUT) install
diff --git a/tools/power/cpupower/bench/Makefile b/tools/power/cpupower/bench/Makefile
index f68b4bc5527397f285cb1b7bedcf5347ebca52cf..d9d9923af85c2e60ca9b2161fd93867df3346d1b 100644
--- a/tools/power/cpupower/bench/Makefile
+++ b/tools/power/cpupower/bench/Makefile
@@ -27,7 +27,7 @@ $(OUTPUT)cpufreq-bench: $(OBJS)
all: $(OUTPUT)cpufreq-bench
-install:
+install: $(OUTPUT)cpufreq-bench
mkdir -p $(DESTDIR)/$(sbindir)
mkdir -p $(DESTDIR)/$(bindir)
mkdir -p $(DESTDIR)/$(docdir)
diff --git a/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc b/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc
index 4fa0f79144f4abbf96ea294443a4c726d6296ee1..9473934a573a102fffd9b45ca07a89075bbb6516 100644
--- a/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc
+++ b/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc
@@ -43,7 +43,7 @@ instance_read() {
instance_set() {
while :; do
- echo 1 > foo/events/sched/sched_switch
+ echo 1 > foo/events/sched/sched_switch/enable
done 2> /dev/null
}
diff --git a/tools/testing/selftests/net/tls.c b/tools/testing/selftests/net/tls.c
index 7549d39ccafff21dcf28f7ee7bb54efedacbb3e9..92adfe4df4e6d1938bb7a489ee495f940d065363 100644
--- a/tools/testing/selftests/net/tls.c
+++ b/tools/testing/selftests/net/tls.c
@@ -199,11 +199,12 @@ TEST_F(tls, sendmsg_large)
msg.msg_iov = &vec;
msg.msg_iovlen = 1;
- EXPECT_EQ(sendmsg(self->cfd, &msg, 0), send_len);
+ EXPECT_EQ(sendmsg(self->fd, &msg, 0), send_len);
}
- while (recvs++ < sends)
- EXPECT_NE(recv(self->fd, mem, send_len, 0), -1);
+ while (recvs++ < sends) {
+ EXPECT_NE(recv(self->cfd, mem, send_len, 0), -1);
+ }
free(mem);
}
@@ -231,9 +232,9 @@ TEST_F(tls, sendmsg_multiple)
msg.msg_iov = vec;
msg.msg_iovlen = iov_len;
- EXPECT_EQ(sendmsg(self->cfd, &msg, 0), total_len);
+ EXPECT_EQ(sendmsg(self->fd, &msg, 0), total_len);
buf = malloc(total_len);
- EXPECT_NE(recv(self->fd, buf, total_len, 0), -1);
+ EXPECT_NE(recv(self->cfd, buf, total_len, 0), -1);
for (i = 0; i < iov_len; i++) {
EXPECT_EQ(memcmp(test_strs[i], buf + len_cmp,
strlen(test_strs[i])),