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Commit 8eabaf54 authored by Kent Russell's avatar Kent Russell Committed by Oded Gabbay
Browse files

drm/amdkfd: Clean up KFD style errors and warnings v2 



Using checkpatch.pl -f <file> showed a number of style issues. This
patch addresses as many of them as possible. Some long lines have been
left for readability, but attempts to minimize them have been made.

v2: Broke long lines in gfx_v7 get_fw_version

Signed-off-by: default avatarKent Russell <kent.russell@amd.com>
Signed-off-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarOded Gabbay <oded.gabbay@gmail.com>
parent 438e29a2

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+2 −2
Original line number Diff line number Diff line
@@ -28,14 +28,14 @@ 
#include <linux/module.h>



const struct kgd2kfd_calls *kgd2kfd;

bool (*kgd2kfd_init_p)(unsigned, const struct kgd2kfd_calls**);

bool (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**);



int amdgpu_amdkfd_init(void)

{

	int ret;



#if defined(CONFIG_HSA_AMD_MODULE)

	int (*kgd2kfd_init_p)(unsigned, const struct kgd2kfd_calls**);

	int (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**);



	kgd2kfd_init_p = symbol_request(kgd2kfd_init);

drivers/gpu/drm/amd/amdkfd/kfd_chardev.c

+4 −2
Original line number Diff line number Diff line
@@ -782,7 +782,8 @@ static int kfd_ioctl_get_process_apertures(struct file *filp, 
				"scratch_limit %llX\n", pdd->scratch_limit);



			args->num_of_nodes++;

		} while ((pdd = kfd_get_next_process_device_data(p, pdd)) != NULL &&

		} while ((pdd = kfd_get_next_process_device_data(p, pdd)) !=

				NULL &&

				(args->num_of_nodes < NUM_OF_SUPPORTED_GPUS));

	}
@@ -848,7 +849,8 @@ static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p, 
}



#define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \

	[_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, .cmd_drv = 0, .name = #ioctl}

	[_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \

			    .cmd_drv = 0, .name = #ioctl}



/** Ioctl table */

static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {

drivers/gpu/drm/amd/amdkfd/kfd_dbgdev.c

+4 −3
Original line number Diff line number Diff line
@@ -810,7 +810,8 @@ int dbgdev_wave_reset_wavefronts(struct kfd_dev *dev, struct kfd_process *p) 


	/* Scan all registers in the range ATC_VMID8_PASID_MAPPING ..

	 * ATC_VMID15_PASID_MAPPING

	 * to check which VMID the current process is mapped to. */

	 * to check which VMID the current process is mapped to.

	 */



	for (vmid = first_vmid_to_scan; vmid <= last_vmid_to_scan; vmid++) {

		if (dev->kfd2kgd->get_atc_vmid_pasid_mapping_valid

drivers/gpu/drm/amd/amdkfd/kfd_dbgmgr.h

+13 −14
Original line number Diff line number Diff line
@@ -33,10 +33,8 @@ enum HSA_DBG_WAVEOP { 
	HSA_DBG_WAVEOP_HALT = 1,   /* Halts a wavefront */

	HSA_DBG_WAVEOP_RESUME = 2, /* Resumes a wavefront */

	HSA_DBG_WAVEOP_KILL = 3,   /* Kills a wavefront */

	HSA_DBG_WAVEOP_DEBUG = 4,	/* Causes wavefront to enter

						debug mode		*/

	HSA_DBG_WAVEOP_TRAP = 5,	/* Causes wavefront to take

						a trap			*/

	HSA_DBG_WAVEOP_DEBUG = 4,  /* Causes wavefront to enter dbg mode */

	HSA_DBG_WAVEOP_TRAP = 5,   /* Causes wavefront to take a trap */

	HSA_DBG_NUM_WAVEOP = 5,

	HSA_DBG_MAX_WAVEOP = 0xFFFFFFFF

};
@@ -81,15 +79,13 @@ struct HsaDbgWaveMsgAMDGen2 { 
			uint32_t UserData:8;	/* user data */

			uint32_t ShaderArray:1;	/* Shader array */

			uint32_t Priv:1;	/* Privileged */

			uint32_t Reserved0:4;	/* This field is reserved,

						   should be 0 */

			uint32_t Reserved0:4;	/* Reserved, should be 0 */

			uint32_t WaveId:4;	/* wave id */

			uint32_t SIMD:2;	/* SIMD id */

			uint32_t HSACU:4;	/* Compute unit */

			uint32_t ShaderEngine:2;/* Shader engine */

			uint32_t MessageType:2;	/* see HSA_DBG_WAVEMSG_TYPE */

			uint32_t Reserved1:4;	/* This field is reserved,

						   should be 0 */

			uint32_t Reserved1:4;	/* Reserved, should be 0 */

		} ui32;

		uint32_t Value;

	};
@@ -121,20 +117,23 @@ struct HsaDbgWaveMessage { 
 * in the user mode instruction stream. The OS scheduler event is typically

 * associated and signaled by an interrupt issued by the GPU, but other HSA

 * system interrupt conditions from other HW (e.g. IOMMUv2) may be surfaced

 * by the KFD by this mechanism, too. */

 * by the KFD by this mechanism, too.

 */



/* these are the new definitions for events */

enum HSA_EVENTTYPE {

	HSA_EVENTTYPE_SIGNAL = 0,	/* user-mode generated GPU signal */

	HSA_EVENTTYPE_NODECHANGE = 1,	/* HSA node change (attach/detach) */

	HSA_EVENTTYPE_DEVICESTATECHANGE = 2,	/* HSA device state change

						   (start/stop) */

						 * (start/stop)

						 */

	HSA_EVENTTYPE_HW_EXCEPTION = 3,	/* GPU shader exception event */

	HSA_EVENTTYPE_SYSTEM_EVENT = 4,	/* GPU SYSCALL with parameter info */

	HSA_EVENTTYPE_DEBUG_EVENT = 5,	/* GPU signal for debugging */

	HSA_EVENTTYPE_PROFILE_EVENT = 6,/* GPU signal for profiling */

	HSA_EVENTTYPE_QUEUE_EVENT = 7,	/* GPU signal queue idle state

					   (EOP pm4) */

					 * (EOP pm4)

					 */

	/* ...  */

	HSA_EVENTTYPE_MAXID,

	HSA_EVENTTYPE_TYPE_SIZE = 0xFFFFFFFF

drivers/gpu/drm/amd/amdkfd/kfd_device.c

+3 −2
Original line number Diff line number Diff line
@@ -155,12 +155,13 @@ static bool device_iommu_pasid_init(struct kfd_dev *kfd) 
		dev_err(kfd_device, "error required iommu flags ats(%i), pri(%i), pasid(%i)\n",

		       (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_ATS_SUP) != 0,

		       (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_PRI_SUP) != 0,

		       (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_PASID_SUP) != 0);

		       (iommu_info.flags & AMD_IOMMU_DEVICE_FLAG_PASID_SUP)

									!= 0);

		return false;

	}



	pasid_limit = min_t(unsigned int,

			(unsigned int)1 << kfd->device_info->max_pasid_bits,

			(unsigned int)(1 << kfd->device_info->max_pasid_bits),

			iommu_info.max_pasids);

	/*

	 * last pasid is used for kernel queues doorbells