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Commit 8e9fc800 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powrplay: delete code no longer in use on Polaris. 



Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6391b6ab

drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c

+0 −13
Original line number Diff line number Diff line
@@ -98,19 +98,6 @@ 
#define PCIE_BUS_CLK                10000

#define TCLK                        (PCIE_BUS_CLK / 10)





static const uint16_t polaris10_clock_stretcher_lookup_table[2][4] =

{ {600, 1050, 3, 0}, {600, 1050, 6, 1} };



/*  [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */

static const uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] =

{ { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },

  { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };



/*  [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */

static const uint8_t polaris10_clock_stretch_amount_conversion[2][6] =

{ {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };



/** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */

enum DPM_EVENT_SRC {

	DPM_EVENT_SRC_ANALOG = 0,