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Commit 8e504bcc authored by Yongqiang Sun's avatar Yongqiang Sun Committed by Alex Deucher
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drm/amd/display: Disable plane right after disconnected 



HDR display playing video underflow is observed when switching
to full screen due to program a lower watermark right after unlock otg.

Instead of disable plane in next flip coming, if there is a
plane disconnected, after otg unlock wait for mpcc idle and disable
the plane, then program watermark. So there is enough warter mark to make
sure current frame data pass through.

Signed-off-by: default avatarYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9168a586

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+2 −1
Original line number Diff line number Diff line
@@ -2297,7 +2297,7 @@ static void dcn10_apply_ctx_for_surface( 
			pipe_ctx->plane_state->update_flags.bits.full_update)

			program_water_mark = true;



		if (removed_pipe[i] && num_planes == 0)

		if (removed_pipe[i])

			dcn10_disable_plane(dc, old_pipe_ctx);

	}
@@ -2306,6 +2306,7 @@ static void dcn10_apply_ctx_for_surface( 
			/* pstate stuck check after watermark update */

			dcn10_verify_allow_pstate_change_high(dc);

		}



		/* watermark is for all pipes */

		hubbub1_program_watermarks(dc->res_pool->hubbub,

				&context->bw.dcn.watermarks, ref_clk_mhz);