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Commit 8e4cb9aa authored by Tomi Valkeinen's avatar Tomi Valkeinen Committed by Paul Walmsley
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ARM: AM43xx: fix dpll init in bypass mode 



On AM43xx, if a PLL is in bypass at kernel init, the code in
omap2_get_dpll_rate() will not realize this and will try to calculate
the clock rate using the multiplier and the divider, resulting in
errors.

omap2_init_dpll_parent() has similar issue.

Add the missing soc_is_am43xx() check to make the code work on AM43xx.

Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: default avatarSathya Prakash M R <sathyap@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent c6c56697

arch/arm/mach-omap2/clkt_dpll.c

+2 −2
Original line number Diff line number Diff line
@@ -209,7 +209,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) 
		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||

		    v == OMAP3XXX_EN_DPLL_FRBYPASS)

			return 1;

	} else if (soc_is_am33xx() || cpu_is_omap44xx()) {

	} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {

		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||

		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||

		    v == OMAP4XXX_EN_DPLL_MNBYPASS)
@@ -255,7 +255,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) 
		if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||

		    v == OMAP3XXX_EN_DPLL_FRBYPASS)

			return __clk_get_rate(dd->clk_bypass);

	} else if (soc_is_am33xx() || cpu_is_omap44xx()) {

	} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) {

		if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||

		    v == OMAP4XXX_EN_DPLL_FRBYPASS ||

		    v == OMAP4XXX_EN_DPLL_MNBYPASS)