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Commit 8e2dadb3 authored by spuligil's avatar spuligil
Browse files

fw-api: CL 22436998 - update fw common interface files

Change-Id: Ib7219c83ec963397cacbc8cab74957a8e531b908
WMI: add WOW_NACK_STATUS defs; HTC: add MetaData hdr field
CRs-Fixed: 2262693
parent e5ccbe20
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+6 −2
Original line number Diff line number Diff line
@@ -166,12 +166,16 @@ typedef PREPACK struct _HTC_FRAME_HDR{
/* base message ID header */
typedef PREPACK struct {
    A_UINT32 MessageID: 16,
             reserved : 16;
             MetaData:   8,
             reserved:   8;
} POSTPACK HTC_UNKNOWN_MSG;

#define HTC_UNKNOWN_MSG_MESSAGEID_LSB                 0
#define HTC_UNKNOWN_MSG_MESSAGEID_MASK                0x0000ffff
#define HTC_UNKNOWN_MSG_MESSAGEID_OFFSET              0x00000000
#define HTC_UNKNOWN_MSG_METADATA_LSB                  16
#define HTC_UNKNOWN_MSG_METADATA_MASK                 0X00ff0000
#define HTC_UNKNOWN_MSG_METADATA_OFFSET               0x00000000

/* HTC ready message
 * direction : target-to-host  */
+48 −6
Original line number Diff line number Diff line
@@ -23023,6 +23023,48 @@ typedef enum {
    WMI_WOW_RESUME_FLAG_TX_DATA          = 0x00000001, /* TX data pending to be sent in resume */
} WMI_WOW_RESUME_FLAG_ENUM;
/* wow nack reason codes */
typedef enum {
    /* WoW error due to unnkown reason */
    WMI_WOW_NON_ACK_REASON_UNKNOWN = 0,
    /* WoW error due to TX failure */
    WMI_WOW_NON_ACK_REASON_TX = 1,
    /* WoW error due to some data blocked */
    WMI_WOW_NON_ACK_REASON_IS_BLOCK = 2,
    /* WoW error in WFA mode */
    WMI_WOW_NON_ACK_REASON_NOT_ALLOW = 3,
    /* WoW error mac operation fail */
    WMI_WOW_NON_ACK_REASON_HW_FAIL = 4,
    /* WoW error due to timeout */
    WMI_WOW_NON_ACK_REASON_TIMEOUT = 5,
    /* WoW error due to RTT or CFR capture active */
    WMI_WOW_NON_ACK_REASON_RTT_DMA = 6,
    /* WoW error due to roam module holding lock */
    WMI_WOW_NON_ACK_REASON_ROAM = 7,
    /* WoW error remote peer not sleeping */
    WMI_WOW_NON_ACK_REASON_PEER_ACTIVE = 8,
    /* WoW error due to WoW entry defer failed */
    WMI_WOW_NON_ACK_REASON_DEFER_FAILURE = 9,
    /* WoW error due to WoW entry defer timeout */
    WMI_WOW_NON_ACK_REASON_DEFER_TIMEOUT = 10,
    /* WoW error due to FATAL event */
    WMI_WOW_NON_ACK_REASON_FATAL_EVENT = 11,
    /* WoW error if close to TBTT */
    WMI_WOW_NON_ACK_REASON_CLOSE_TO_TBTT = 12,
} WMI_WOW_NACK_STATUS;
typedef struct {
    A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wow_hostwakeup_from_sleep_cmd_fixed_param  */
    /* reserved0:
@@ -41432,16 +41474,16 @@ typedef struct {
#define WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 1, 1, value)
/* Bit 66: 20Mhz-only limited capabilities support */
#define WMI_EHTCAP_20MHZ_ONLY_CAPS_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 2, 1)
#define WMI_EHTCAP_20MHZ_ONLY_CAPS_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 2, 1, value)
#define WMI_EHTCAP_PHY_20MHZ_ONLY_CAPS_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 2, 1)
#define WMI_EHTCAP_PHY_20MHZ_ONLY_CAPS_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 2, 1, value)
/* Bit 67: 20Mhz-only triggered MU beamforming full BW feedback and DL MU-MIMO */
#define WMI_EHTCAP_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 3, 1)
#define WMI_EHTCAP_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 3, 1, value)
#define WMI_EHTCAP_PHY_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 3, 1)
#define WMI_EHTCAP_PHY_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 3, 1, value)
/* Bit 68: 20Mhz-only M-RU support */
#define WMI_EHTCAP_20MHZ_ONLY_MRU_SUPP_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 4, 1)
#define WMI_EHTCAP_20MHZ_ONLY_MRU_SUPP_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 4, 1, value)
#define WMI_EHTCAP_PHY_20MHZ_ONLY_MRU_SUPP_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 4, 1)
#define WMI_EHTCAP_PHY_20MHZ_ONLY_MRU_SUPP_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 4, 1, value)
/* Bits 69-71: reserved */
+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@
#define __WMI_VER_MINOR_    0
/** WMI revision number has to be incremented when there is a
 *  change that may or may not break compatibility. */
#define __WMI_REVISION_ 1317
#define __WMI_REVISION_ 1318

/** The Version Namespace should not be normally changed. Only
 *  host and firmware of the same WMI namespace will work