Commit 8e1c3aa3 authored Sep 30, 2015 by Geert Uytterhoeven Committed by Simon Horman Feb 17, 2016

arm64: dts: r8a7795: Add CA53 L2 cache-controller node



Add a device node for the Cortex-A53 L2 cache-controller.

The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

parent a528b4bf

arch/arm64/boot/dts/renesas/r8a7795.dtsi

+6 −0

Original line number	Diff line number	Diff line
		@@ -72,6 +72,12 @@
		cache-level = <2>;
		};

		L2_CA53: cache-controller@1 {
		compatible = "cache";
		cache-unified;
		cache-level = <2>;
		};

		extal_clk: extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;