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Commit 8da6fe2a authored by Jianbo Liu's avatar Jianbo Liu Committed by Saeed Mahameed
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net/mlx5: Add core support for double vlan push/pop steering action



As newer firmware supports double push/pop in a single FTE, we add
core bits and extend vlan action logic for it.

Signed-off-by: default avatarJianbo Liu <jianbol@mellanox.com>
Reviewed-by: default avatarOr Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent 5e022dd3
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+2 −0
Original line number Diff line number Diff line
@@ -138,6 +138,8 @@ TRACE_EVENT(mlx5_fs_del_fg,
	{MLX5_FLOW_CONTEXT_ACTION_MOD_HDR,	 "MOD_HDR"},\
	{MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH,	 "VLAN_PUSH"},\
	{MLX5_FLOW_CONTEXT_ACTION_VLAN_POP,	 "VLAN_POP"},\
	{MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2,	 "VLAN_PUSH_2"},\
	{MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2,	 "VLAN_POP_2"},\
	{MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO, "NEXT_PRIO"}

TRACE_EVENT(mlx5_fs_set_fte,
+3 −3
Original line number Diff line number Diff line
@@ -70,9 +70,9 @@ mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
		flow_act.action &= ~(MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
				     MLX5_FLOW_CONTEXT_ACTION_VLAN_POP);
	else if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH) {
		flow_act.vlan.ethtype = ntohs(attr->vlan_proto);
		flow_act.vlan.vid = attr->vlan_vid;
		flow_act.vlan.prio = attr->vlan_prio;
		flow_act.vlan[0].ethtype = ntohs(attr->vlan_proto);
		flow_act.vlan[0].vid = attr->vlan_vid;
		flow_act.vlan[0].prio = attr->vlan_prio;
	}

	if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
+9 −3
Original line number Diff line number Diff line
@@ -349,9 +349,15 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev,

	vlan = MLX5_ADDR_OF(flow_context, in_flow_context, push_vlan);

	MLX5_SET(vlan, vlan, ethtype, fte->action.vlan.ethtype);
	MLX5_SET(vlan, vlan, vid, fte->action.vlan.vid);
	MLX5_SET(vlan, vlan, prio, fte->action.vlan.prio);
	MLX5_SET(vlan, vlan, ethtype, fte->action.vlan[0].ethtype);
	MLX5_SET(vlan, vlan, vid, fte->action.vlan[0].vid);
	MLX5_SET(vlan, vlan, prio, fte->action.vlan[0].prio);

	vlan = MLX5_ADDR_OF(flow_context, in_flow_context, push_vlan_2);

	MLX5_SET(vlan, vlan, ethtype, fte->action.vlan[1].ethtype);
	MLX5_SET(vlan, vlan, vid, fte->action.vlan[1].vid);
	MLX5_SET(vlan, vlan, prio, fte->action.vlan[1].prio);

	in_match_value = MLX5_ADDR_OF(flow_context, in_flow_context,
				      match_value);
+3 −1
Original line number Diff line number Diff line
@@ -1464,7 +1464,9 @@ static bool check_conflicting_actions(u32 action1, u32 action2)
			     MLX5_FLOW_CONTEXT_ACTION_DECAP |
			     MLX5_FLOW_CONTEXT_ACTION_MOD_HDR  |
			     MLX5_FLOW_CONTEXT_ACTION_VLAN_POP |
			     MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH))
			     MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH |
			     MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 |
			     MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2))
		return true;

	return false;
+3 −1
Original line number Diff line number Diff line
@@ -152,6 +152,8 @@ struct mlx5_fs_vlan {
        u8  prio;
};

#define MLX5_FS_VLAN_DEPTH	2

struct mlx5_flow_act {
	u32 action;
	bool has_flow_tag;
@@ -159,7 +161,7 @@ struct mlx5_flow_act {
	u32 encap_id;
	u32 modify_id;
	uintptr_t esp_id;
	struct mlx5_fs_vlan vlan;
	struct mlx5_fs_vlan vlan[MLX5_FS_VLAN_DEPTH];
	struct ib_counters *counters;
};

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