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Commit 8d404c4c authored by Christoffer Dall's avatar Christoffer Dall Committed by Marc Zyngier
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KVM: arm64: Rewrite system register accessors to read/write functions 



Currently we access the system registers array via the vcpu_sys_reg()
macro.  However, we are about to change the behavior to some times
modify the register file directly, so let's change this to two
primitives:

 * Accessor macros vcpu_write_sys_reg() and vcpu_read_sys_reg()
 * Direct array access macro __vcpu_sys_reg()

The accessor macros should be used in places where the code needs to
access the currently loaded VCPU's state as observed by the guest.  For
example, when trapping on cache related registers, a write to a system
register should go directly to the VCPU version of the register.

The direct array access macro can be used in places where the VCPU is
known to never be running (for example userspace access) or for
registers which are never context switched (for example all the PMU
system registers).

This rewrites all users of vcpu_sys_regs to one of the macros described
above.

No functional change.

Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Reviewed-by: default avatarAndrew Jones <drjones@redhat.com>
Signed-off-by: default avatarChristoffer Dall <cdall@cs.columbia.edu>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 52f6c4f0

arch/arm64/include/asm/kvm_emulate.h

+8 −5
Original line number Diff line number Diff line
@@ -290,15 +290,18 @@ static inline int kvm_vcpu_sys_get_rt(struct kvm_vcpu *vcpu) 


static inline unsigned long kvm_vcpu_get_mpidr_aff(struct kvm_vcpu *vcpu)

{

	return vcpu_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;

	return vcpu_read_sys_reg(vcpu, MPIDR_EL1) & MPIDR_HWID_BITMASK;

}



static inline void kvm_vcpu_set_be(struct kvm_vcpu *vcpu)

{

	if (vcpu_mode_is_32bit(vcpu))

	if (vcpu_mode_is_32bit(vcpu)) {

		*vcpu_cpsr(vcpu) |= COMPAT_PSR_E_BIT;

	else

		vcpu_sys_reg(vcpu, SCTLR_EL1) |= (1 << 25);

	} else {

		u64 sctlr = vcpu_read_sys_reg(vcpu, SCTLR_EL1);

		sctlr |= (1 << 25);

		vcpu_write_sys_reg(vcpu, SCTLR_EL1, sctlr);

	}

}



static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu)
@@ -306,7 +309,7 @@ static inline bool kvm_vcpu_is_be(struct kvm_vcpu *vcpu) 
	if (vcpu_mode_is_32bit(vcpu))

		return !!(*vcpu_cpsr(vcpu) & COMPAT_PSR_E_BIT);



	return !!(vcpu_sys_reg(vcpu, SCTLR_EL1) & (1 << 25));

	return !!(vcpu_read_sys_reg(vcpu, SCTLR_EL1) & (1 << 25));

}



static inline unsigned long vcpu_data_guest_to_host(struct kvm_vcpu *vcpu,

arch/arm64/include/asm/kvm_host.h

+12 −1
Original line number Diff line number Diff line
@@ -287,7 +287,18 @@ struct kvm_vcpu_arch { 
};



#define vcpu_gp_regs(v)		(&(v)->arch.ctxt.gp_regs)

#define vcpu_sys_reg(v,r)	((v)->arch.ctxt.sys_regs[(r)])



/*

 * Only use __vcpu_sys_reg if you know you want the memory backed version of a

 * register, and not the one most recently accessed by a running VCPU.  For

 * example, for userspace access or for system registers that are never context

 * switched, but only emulated.

 */

#define __vcpu_sys_reg(v,r)	((v)->arch.ctxt.sys_regs[(r)])



#define vcpu_read_sys_reg(v,r)	__vcpu_sys_reg(v,r)

#define vcpu_write_sys_reg(v,n,r)	do { __vcpu_sys_reg(v,r) = n; } while (0)



/*

 * CP14 and CP15 live in the same array, as they are backed by the

 * same system registers.

arch/arm64/include/asm/kvm_mmu.h

+1 −1
Original line number Diff line number Diff line
@@ -249,7 +249,7 @@ struct kvm; 


static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)

{

	return (vcpu_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;

	return (vcpu_read_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;

}



static inline void __clean_dcache_guest_page(kvm_pfn_t pfn, unsigned long size)

arch/arm64/kvm/debug.c

+19 −9
Original line number Diff line number Diff line
@@ -46,7 +46,9 @@ static DEFINE_PER_CPU(u32, mdcr_el2); 
 */

static void save_guest_debug_regs(struct kvm_vcpu *vcpu)

{

	vcpu->arch.guest_debug_preserved.mdscr_el1 = vcpu_sys_reg(vcpu, MDSCR_EL1);

	u64 val = vcpu_read_sys_reg(vcpu, MDSCR_EL1);



	vcpu->arch.guest_debug_preserved.mdscr_el1 = val;



	trace_kvm_arm_set_dreg32("Saved MDSCR_EL1",

				vcpu->arch.guest_debug_preserved.mdscr_el1);
@@ -54,10 +56,12 @@ static void save_guest_debug_regs(struct kvm_vcpu *vcpu) 


static void restore_guest_debug_regs(struct kvm_vcpu *vcpu)

{

	vcpu_sys_reg(vcpu, MDSCR_EL1) = vcpu->arch.guest_debug_preserved.mdscr_el1;

	u64 val = vcpu->arch.guest_debug_preserved.mdscr_el1;



	vcpu_write_sys_reg(vcpu, val, MDSCR_EL1);



	trace_kvm_arm_set_dreg32("Restored MDSCR_EL1",

				vcpu_sys_reg(vcpu, MDSCR_EL1));

				vcpu_read_sys_reg(vcpu, MDSCR_EL1));

}



/**
@@ -108,6 +112,7 @@ void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu) 
void kvm_arm_setup_debug(struct kvm_vcpu *vcpu)

{

	bool trap_debug = !(vcpu->arch.debug_flags & KVM_ARM64_DEBUG_DIRTY);

	unsigned long mdscr;



	trace_kvm_arm_setup_debug(vcpu, vcpu->guest_debug);
@@ -152,9 +157,13 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) 
		 */

		if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {

			*vcpu_cpsr(vcpu) |=  DBG_SPSR_SS;

			vcpu_sys_reg(vcpu, MDSCR_EL1) |= DBG_MDSCR_SS;

			mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1);

			mdscr |= DBG_MDSCR_SS;

			vcpu_write_sys_reg(vcpu, mdscr, MDSCR_EL1);

		} else {

			vcpu_sys_reg(vcpu, MDSCR_EL1) &= ~DBG_MDSCR_SS;

			mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1);

			mdscr &= ~DBG_MDSCR_SS;

			vcpu_write_sys_reg(vcpu, mdscr, MDSCR_EL1);

		}



		trace_kvm_arm_set_dreg32("SPSR_EL2", *vcpu_cpsr(vcpu));
@@ -170,7 +179,9 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) 
		 */

		if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW) {

			/* Enable breakpoints/watchpoints */

			vcpu_sys_reg(vcpu, MDSCR_EL1) |= DBG_MDSCR_MDE;

			mdscr = vcpu_read_sys_reg(vcpu, MDSCR_EL1);

			mdscr |= DBG_MDSCR_MDE;

			vcpu_write_sys_reg(vcpu, mdscr, MDSCR_EL1);



			vcpu->arch.debug_ptr = &vcpu->arch.external_debug_state;

			vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
@@ -194,12 +205,11 @@ void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) 
		vcpu->arch.mdcr_el2 |= MDCR_EL2_TDA;



	/* If KDE or MDE are set, perform a full save/restore cycle. */

	if ((vcpu_sys_reg(vcpu, MDSCR_EL1) & DBG_MDSCR_KDE) ||

	    (vcpu_sys_reg(vcpu, MDSCR_EL1) & DBG_MDSCR_MDE))

	if (vcpu_read_sys_reg(vcpu, MDSCR_EL1) & (DBG_MDSCR_KDE | DBG_MDSCR_MDE))

		vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;



	trace_kvm_arm_set_dreg32("MDCR_EL2", vcpu->arch.mdcr_el2);

	trace_kvm_arm_set_dreg32("MDSCR_EL1", vcpu_sys_reg(vcpu, MDSCR_EL1));

	trace_kvm_arm_set_dreg32("MDSCR_EL1", vcpu_read_sys_reg(vcpu, MDSCR_EL1));

}



void kvm_arm_clear_debug(struct kvm_vcpu *vcpu)

arch/arm64/kvm/inject_fault.c

+4 −4
Original line number Diff line number Diff line
@@ -58,7 +58,7 @@ static u64 get_except_vector(struct kvm_vcpu *vcpu, enum exception_type type) 
		exc_offset = LOWER_EL_AArch32_VECTOR;

	}



	return vcpu_sys_reg(vcpu, VBAR_EL1) + exc_offset + type;

	return vcpu_read_sys_reg(vcpu, VBAR_EL1) + exc_offset + type;

}



static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
@@ -73,7 +73,7 @@ static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr 
	*vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;

	*vcpu_spsr(vcpu) = cpsr;



	vcpu_sys_reg(vcpu, FAR_EL1) = addr;

	vcpu_write_sys_reg(vcpu, addr, FAR_EL1);



	/*

	 * Build an {i,d}abort, depending on the level and the
@@ -94,7 +94,7 @@ static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr 
	if (!is_iabt)

		esr |= ESR_ELx_EC_DABT_LOW << ESR_ELx_EC_SHIFT;



	vcpu_sys_reg(vcpu, ESR_EL1) = esr | ESR_ELx_FSC_EXTABT;

	vcpu_write_sys_reg(vcpu, esr | ESR_ELx_FSC_EXTABT, ESR_EL1);

}



static void inject_undef64(struct kvm_vcpu *vcpu)
@@ -115,7 +115,7 @@ static void inject_undef64(struct kvm_vcpu *vcpu) 
	if (kvm_vcpu_trap_il_is32bit(vcpu))

		esr |= ESR_ELx_IL;



	vcpu_sys_reg(vcpu, ESR_EL1) = esr;

	vcpu_write_sys_reg(vcpu, esr, ESR_EL1);

}



/**