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Commit 8d2b6f6b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'for-linus' of git://github.com/stffrdhrn/linux 

Pull OpenRISC fixes from Stafford Horne:
 "Two fixes for issues which were breaking OpenRISC boot:

   - Fix bug in __pte_free_tlb() exposed in 4.18 by Matthew Wilcox's
     page table flag addition.

   - Fix issue booting on real hardware if delay slot detection
     emulation is disabled"

* tag 'for-linus' of git://github.com/stffrdhrn/linux:
  openrisc: entry: Fix delay slot exception detection
  openrisc: Call destructor during __pte_free_tlb
parents 4e33d7d4 ae15a41a

arch/openrisc/include/asm/pgalloc.h

+5 −1
Original line number Diff line number Diff line
@@ -98,8 +98,12 @@ static inline void pte_free(struct mm_struct *mm, struct page *pte) 
	__free_page(pte);

}



#define __pte_free_tlb(tlb, pte, addr)	\

do {					\

	pgtable_page_dtor(pte);		\

	tlb_remove_page((tlb), (pte));	\

} while (0)



#define __pte_free_tlb(tlb, pte, addr) tlb_remove_page((tlb), (pte))

#define pmd_pgtable(pmd) pmd_page(pmd)



#define check_pgt_cache()          do { } while (0)

arch/openrisc/kernel/entry.S

+1 −7
Original line number Diff line number Diff line
@@ -277,12 +277,6 @@ EXCEPTION_ENTRY(_data_page_fault_handler) 
	l.addi  r3,r1,0                    // pt_regs

	/* r4 set be EXCEPTION_HANDLE */   // effective address of fault



	/*

	 * __PHX__: TODO

	 *

	 * all this can be written much simpler. look at

	 * DTLB miss handler in the CONFIG_GUARD_PROTECTED_CORE part

	 */

#ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX

	l.lwz   r6,PT_PC(r3)               // address of an offending insn

	l.lwz   r6,0(r6)                   // instruction that caused pf
@@ -314,7 +308,7 @@ EXCEPTION_ENTRY(_data_page_fault_handler) 


#else



	l.lwz   r6,PT_SR(r3)               // SR

	l.mfspr r6,r0,SPR_SR               // SR

	l.andi  r6,r6,SPR_SR_DSX           // check for delay slot exception

	l.sfne  r6,r0                      // exception happened in delay slot

	l.bnf   7f

arch/openrisc/kernel/head.S

+6 −3
Original line number Diff line number Diff line
@@ -210,8 +210,7 @@ 
 *	 r4  - EEAR     exception EA

 *	 r10 - current	pointing to current_thread_info struct

 *	 r12 - syscall  0, since we didn't come from syscall

 *	 r13 - temp	it actually contains new SR, not needed anymore

 *	 r31 - handler	address of the handler we'll jump to

 *	 r30 - handler	address of the handler we'll jump to

 *

 *	 handler has to save remaining registers to the exception

 *	 ksp frame *before* tainting them!
@@ -244,6 +243,7 @@ 
	/* r1 is KSP, r30 is __pa(KSP) */			;\

	tophys  (r30,r1)					;\

	l.sw    PT_GPR12(r30),r12				;\

	/* r4 use for tmp before EA */				;\

	l.mfspr r12,r0,SPR_EPCR_BASE				;\

	l.sw    PT_PC(r30),r12					;\

	l.mfspr r12,r0,SPR_ESR_BASE				;\
@@ -263,7 +263,10 @@ 
	/* r12 == 1 if we come from syscall */			;\

	CLEAR_GPR(r12)						;\

	/* ----- turn on MMU ----- */				;\

	l.ori	r30,r0,(EXCEPTION_SR)				;\

	/* Carry DSX into exception SR */			;\

	l.mfspr r30,r0,SPR_SR					;\

	l.andi	r30,r30,SPR_SR_DSX				;\

	l.ori	r30,r30,(EXCEPTION_SR)				;\

	l.mtspr	r0,r30,SPR_ESR_BASE				;\

	/* r30:	EA address of handler */			;\

	LOAD_SYMBOL_2_GPR(r30,handler)				;\

arch/openrisc/kernel/traps.c

+1 −1
Original line number Diff line number Diff line
@@ -300,7 +300,7 @@ static inline int in_delay_slot(struct pt_regs *regs) 
		return 0;

	}

#else

	return regs->sr & SPR_SR_DSX;

	return mfspr(SPR_SR) & SPR_SR_DSX;

#endif

}