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Commit 8c4fe709 authored by Andi Kleen's avatar Andi Kleen Committed by Ingo Molnar
Browse files

perf/x86/intel: Use 0x11 as extra reg test value 



The next patch adds a new perf extra register where 0x1ff is not a valid
value. Use 0x11 instead.

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1435707205-6676-3-git-send-email-andi@firstfloor.org


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 47732d88

arch/x86/kernel/cpu/perf_event_intel.c

+1 −1
Original line number Diff line number Diff line
@@ -3579,7 +3579,7 @@ __init int intel_pmu_init(void) 
	 */

	if (x86_pmu.extra_regs) {

		for (er = x86_pmu.extra_regs; er->msr; er++) {

			er->extra_msr_access = check_msr(er->msr, 0x1ffUL);

			er->extra_msr_access = check_msr(er->msr, 0x11UL);

			/* Disable LBR select mapping */

			if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)

				x86_pmu.lbr_sel_map = NULL;