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Commit 8c3166f5 authored by kiran.padwal@smartplayin.com's avatar kiran.padwal@smartplayin.com Committed by Kumar Gala
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ARM: DT: apq8064: Add i2c device nodes 



This patch adds i2c pinctrl DT node for IFC6410 board.  It also adds
 necessary DT support for i2c eeprom which is present on IFC6410.

Signed-off-by: default avatarKiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: default avatarKumar Gala <galak@codeaurora.org>
parent 0be5fef1

arch/arm/boot/dts/qcom-apq8064-ifc6410.dts

+27 −0
Original line number Diff line number Diff line
@@ -5,6 +5,33 @@ 
	compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";



	soc {

		pinctrl@800000 {

			i2c1_pins: i2c1 {

				mux {

					pins = "gpio20", "gpio21";

					function = "gsbi1";

				};

			};

		};



		gsbi@12440000 {

			status = "okay";

			qcom,mode = <GSBI_PROT_I2C>;



			i2c@12460000 {

				status = "okay";

				clock-frequency = <200000>;

				pinctrl-0 = <&i2c1_pins>;

				pinctrl-names = "default";



				eeprom: eeprom@52 {

					compatible = "atmel,24c128";

					reg = <0x52>;

					pagesize = <32>;

				};

			};

		};



		gsbi@16600000 {

			status = "ok";

			qcom,mode = <GSBI_PROT_I2C_UART>;

arch/arm/boot/dts/qcom-apq8064.dtsi

+42 −0
Original line number Diff line number Diff line
@@ -163,6 +163,48 @@ 
			regulator;

		};



		gsbi1: gsbi@12440000 {

			status = "disabled";

			compatible = "qcom,gsbi-v1.0.0";

			reg = <0x12440000 0x100>;

			clocks = <&gcc GSBI1_H_CLK>;

			clock-names = "iface";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			i2c1: i2c@12460000 {

				compatible = "qcom,i2c-qup-v1.1.1";

				reg = <0x12460000 0x1000>;

				interrupts = <0 194 IRQ_TYPE_NONE>;

				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;

				clock-names = "core", "iface";

				#address-cells = <1>;

				#size-cells = <0>;

			};

		};



		gsbi2: gsbi@12480000 {

			status = "disabled";

			compatible = "qcom,gsbi-v1.0.0";

			reg = <0x12480000 0x100>;

			clocks = <&gcc GSBI2_H_CLK>;

			clock-names = "iface";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			i2c2: i2c@124a0000 {

				compatible = "qcom,i2c-qup-v1.1.1";

				reg = <0x124a0000 0x1000>;

				interrupts = <0 196 IRQ_TYPE_NONE>;

				clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;

				clock-names = "core", "iface";

				#address-cells = <1>;

				#size-cells = <0>;

			};

		};



		gsbi7: gsbi@16600000 {

			status = "disabled";

			compatible = "qcom,gsbi-v1.0.0";