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Commit 8be06289 authored by Akira Takeuchi's avatar Akira Takeuchi Committed by David Howells
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MN10300: Cache: Implement SMP global cache flushing 



Implement SMP global cache flushing for MN10300.  This will be used by the AM34
which is SMP capable.

Signed-off-by: default avatarAkira Takeuchi <takeuchi.akr@jp.panasonic.com>
Signed-off-by: default avatarKiyoshi Owada <owada.kiyoshi@jp.panasonic.com>
Signed-off-by: default avatarDavid Howells <dhowells@redhat.com>
parent b478491f

arch/mn10300/mm/Kconfig.cache

+1 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ choice 


config MN10300_CACHE_MANAGE_BY_TAG

	bool "Use the cache tag registers directly"

	depends on !(SMP && MN10300_CACHE_WTHRU)



config MN10300_CACHE_MANAGE_BY_REG

	bool "Flush areas by way of automatic purge registers (AM34 only)"

arch/mn10300/mm/Makefile

+3 −0
Original line number Diff line number Diff line
@@ -2,7 +2,10 @@ 
# Makefile for the MN10300-specific memory management code

#



cache-smp-wback-$(CONFIG_MN10300_CACHE_WBACK) := cache-smp-flush.o



cacheflush-y	:= cache.o

cacheflush-$(CONFIG_SMP) += cache-smp.o cache-smp-inv.o $(cache-smp-wback-y)

cacheflush-$(CONFIG_MN10300_CACHE_INV_ICACHE) += cache-inv-icache.o

cacheflush-$(CONFIG_MN10300_CACHE_FLUSH_ICACHE) += cache-flush-icache.o

cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_TAG) += cache-inv-by-tag.o

arch/mn10300/mm/cache-flush-icache.c

+27 −9
Original line number Diff line number Diff line
@@ -11,6 +11,9 @@ 
#include <linux/module.h>

#include <linux/mm.h>

#include <asm/cacheflush.h>

#include <asm/smp.h>

#include "cache-smp.h"



/**

 * flush_icache_page - Flush a page from the dcache and invalidate the icache

 * @vma: The VMA the page is part of.
@@ -22,9 +25,15 @@ 
void flush_icache_page(struct vm_area_struct *vma, struct page *page)

{

	unsigned long start = page_to_phys(page);

	unsigned long flags;



	flags = smp_lock_cache();



	mn10300_dcache_flush_page(start);

	mn10300_icache_inv_page(start);

	mn10300_local_dcache_flush_page(start);

	mn10300_local_icache_inv_page(start);



	smp_cache_call(SMP_IDCACHE_INV_FLUSH_RANGE, start, start + PAGE_SIZE);

	smp_unlock_cache(flags);

}

EXPORT_SYMBOL(flush_icache_page);
@@ -82,8 +91,9 @@ static void flush_icache_page_range(unsigned long start, unsigned long end) 


	/* flush the dcache and invalidate the icache coverage on that

	 * region */

	mn10300_dcache_flush_range2(addr + off, size);

	mn10300_icache_inv_range2(addr + off, size);

	mn10300_local_dcache_flush_range2(addr + off, size);

	mn10300_local_icache_inv_range2(addr + off, size);

	smp_cache_call(SMP_IDCACHE_INV_FLUSH_RANGE, start, end);

}



/**
@@ -98,28 +108,32 @@ static void flush_icache_page_range(unsigned long start, unsigned long end) 
void flush_icache_range(unsigned long start, unsigned long end)

{

	unsigned long start_page, end_page;

	unsigned long flags;



	flags = smp_lock_cache();



	if (end > 0x80000000UL) {

		/* addresses above 0xa0000000 do not go through the cache */

		if (end > 0xa0000000UL) {

			end = 0xa0000000UL;

			if (start >= end)

				return;

				goto done;

		}



		/* kernel addresses between 0x80000000 and 0x9fffffff do not

		 * require page tables, so we just map such addresses

		 * directly */

		start_page = (start >= 0x80000000UL) ? start : 0x80000000UL;

		mn10300_dcache_flush_range(start_page, end);

		mn10300_icache_inv_range(start_page, end);

		mn10300_local_dcache_flush_range(start_page, end);

		mn10300_local_icache_inv_range(start_page, end);

		smp_cache_call(SMP_IDCACHE_INV_FLUSH_RANGE, start_page, end);

		if (start_page == start)

			return;

			goto done;

		end = start_page;

	}



	start_page = start & PAGE_MASK;

	end_page = end & PAGE_MASK;

	end_page = (end - 1) & PAGE_MASK;



	if (start_page == end_page) {

		/* the first and last bytes are on the same page */
@@ -132,6 +146,10 @@ void flush_icache_range(unsigned long start, unsigned long end) 
		/* more than 2 pages; just flush the entire cache */

		mn10300_dcache_flush();

		mn10300_icache_inv();

		smp_cache_call(SMP_IDCACHE_INV_FLUSH, 0, 0);

	}



done:

	smp_unlock_cache(flags);

}

EXPORT_SYMBOL(flush_icache_range);

arch/mn10300/mm/cache-inv-icache.c

+16 −6
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@ 
#include <linux/module.h>

#include <linux/mm.h>

#include <asm/cacheflush.h>

#include <asm/smp.h>

#include "cache-smp.h"



/**

 * flush_icache_page_range - Flush dcache and invalidate icache for part of a
@@ -66,7 +68,8 @@ static void flush_icache_page_range(unsigned long start, unsigned long end) 
	addr = page_to_phys(page);



	/* invalidate the icache coverage on that region */

	mn10300_icache_inv_range2(addr + off, size);

	mn10300_local_icache_inv_range2(addr + off, size);

	smp_cache_call(SMP_ICACHE_INV_FLUSH_RANGE, start, end);

}



/**
@@ -81,28 +84,31 @@ static void flush_icache_page_range(unsigned long start, unsigned long end) 
void flush_icache_range(unsigned long start, unsigned long end)

{

	unsigned long start_page, end_page;

	unsigned long flags;



	flags = smp_lock_cache();



	if (end > 0x80000000UL) {

		/* addresses above 0xa0000000 do not go through the cache */

		if (end > 0xa0000000UL) {

			end = 0xa0000000UL;

			if (start >= end)

				return;

				goto done;

		}



		/* kernel addresses between 0x80000000 and 0x9fffffff do not

		 * require page tables, so we just map such addresses

		 * directly */

		start_page = (start >= 0x80000000UL) ? start : 0x80000000UL;

		mn10300_dcache_flush_range(start_page, end);

		mn10300_icache_inv_range(start_page, end);

		smp_cache_call(SMP_ICACHE_INV_FLUSH_RANGE, start, end);

		if (start_page == start)

			return;

			goto done;

		end = start_page;

	}



	start_page = start & PAGE_MASK;

	end_page = end & PAGE_MASK;

	end_page = (end - 1) & PAGE_MASK;



	if (start_page == end_page) {

		/* the first and last bytes are on the same page */
@@ -113,7 +119,11 @@ void flush_icache_range(unsigned long start, unsigned long end) 
		flush_icache_page_range(end_page, end);

	} else {

		/* more than 2 pages; just flush the entire cache */

		mn10300_icache_inv();

		mn10300_local_icache_inv();

		smp_cache_call(SMP_ICACHE_INV, 0, 0);

	}



done:

	smp_unlock_cache(flags);

}

EXPORT_SYMBOL(flush_icache_range);

arch/mn10300/mm/cache-smp-flush.c

0 → 100644
+156 −0
Original line number Diff line number Diff line 
/* Functions for global dcache flush when writeback caching in SMP

 *

 * Copyright (C) 2010 Red Hat, Inc. All Rights Reserved.

 * Written by David Howells (dhowells@redhat.com)

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public Licence

 * as published by the Free Software Foundation; either version

 * 2 of the Licence, or (at your option) any later version.

 */

#include <linux/mm.h>

#include <asm/cacheflush.h>

#include "cache-smp.h"



/**

 * mn10300_dcache_flush - Globally flush data cache

 *

 * Flush the data cache on all CPUs.

 */

void mn10300_dcache_flush(void)

{

	unsigned long flags;



	flags = smp_lock_cache();

	mn10300_local_dcache_flush();

	smp_cache_call(SMP_DCACHE_FLUSH, 0, 0);

	smp_unlock_cache(flags);

}



/**

 * mn10300_dcache_flush_page - Globally flush a page of data cache

 * @start: The address of the page of memory to be flushed.

 *

 * Flush a range of addresses in the data cache on all CPUs covering

 * the page that includes the given address.

 */

void mn10300_dcache_flush_page(unsigned long start)

{

	unsigned long flags;



	start &= ~(PAGE_SIZE-1);



	flags = smp_lock_cache();

	mn10300_local_dcache_flush_page(start);

	smp_cache_call(SMP_DCACHE_FLUSH_RANGE, start, start + PAGE_SIZE);

	smp_unlock_cache(flags);

}



/**

 * mn10300_dcache_flush_range - Globally flush range of data cache

 * @start: The start address of the region to be flushed.

 * @end: The end address of the region to be flushed.

 *

 * Flush a range of addresses in the data cache on all CPUs, between start and

 * end-1 inclusive.

 */

void mn10300_dcache_flush_range(unsigned long start, unsigned long end)

{

	unsigned long flags;



	flags = smp_lock_cache();

	mn10300_local_dcache_flush_range(start, end);

	smp_cache_call(SMP_DCACHE_FLUSH_RANGE, start, end);

	smp_unlock_cache(flags);

}



/**

 * mn10300_dcache_flush_range2 - Globally flush range of data cache

 * @start: The start address of the region to be flushed.

 * @size: The size of the region to be flushed.

 *

 * Flush a range of addresses in the data cache on all CPUs, between start and

 * start+size-1 inclusive.

 */

void mn10300_dcache_flush_range2(unsigned long start, unsigned long size)

{

	unsigned long flags;



	flags = smp_lock_cache();

	mn10300_local_dcache_flush_range2(start, size);

	smp_cache_call(SMP_DCACHE_FLUSH_RANGE, start, start + size);

	smp_unlock_cache(flags);

}



/**

 * mn10300_dcache_flush_inv - Globally flush and invalidate data cache

 *

 * Flush and invalidate the data cache on all CPUs.

 */

void mn10300_dcache_flush_inv(void)

{

	unsigned long flags;



	flags = smp_lock_cache();

	mn10300_local_dcache_flush_inv();

	smp_cache_call(SMP_DCACHE_FLUSH_INV, 0, 0);

	smp_unlock_cache(flags);

}



/**

 * mn10300_dcache_flush_inv_page - Globally flush and invalidate a page of data

 *	cache

 * @start: The address of the page of memory to be flushed and invalidated.

 *

 * Flush and invalidate a range of addresses in the data cache on all CPUs

 * covering the page that includes the given address.

 */

void mn10300_dcache_flush_inv_page(unsigned long start)

{

	unsigned long flags;



	start &= ~(PAGE_SIZE-1);



	flags = smp_lock_cache();

	mn10300_local_dcache_flush_inv_page(start);

	smp_cache_call(SMP_DCACHE_FLUSH_INV_RANGE, start, start + PAGE_SIZE);

	smp_unlock_cache(flags);

}



/**

 * mn10300_dcache_flush_inv_range - Globally flush and invalidate range of data

 *	cache

 * @start: The start address of the region to be flushed and invalidated.

 * @end: The end address of the region to be flushed and invalidated.

 *

 * Flush and invalidate a range of addresses in the data cache on all CPUs,

 * between start and end-1 inclusive.

 */

void mn10300_dcache_flush_inv_range(unsigned long start, unsigned long end)

{

	unsigned long flags;



	flags = smp_lock_cache();

	mn10300_local_dcache_flush_inv_range(start, end);

	smp_cache_call(SMP_DCACHE_FLUSH_INV_RANGE, start, end);

	smp_unlock_cache(flags);

}



/**

 * mn10300_dcache_flush_inv_range2 - Globally flush and invalidate range of data

 *	cache

 * @start: The start address of the region to be flushed and invalidated.

 * @size: The size of the region to be flushed and invalidated.

 *

 * Flush and invalidate a range of addresses in the data cache on all CPUs,

 * between start and start+size-1 inclusive.

 */

void mn10300_dcache_flush_inv_range2(unsigned long start, unsigned long size)

{

	unsigned long flags;



	flags = smp_lock_cache();

	mn10300_local_dcache_flush_inv_range2(start, size);

	smp_cache_call(SMP_DCACHE_FLUSH_INV_RANGE, start, start + size);

	smp_unlock_cache(flags);

}