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Commit 8bb3fdd6 authored by Heiko Carstens's avatar Heiko Carstens Committed by Martin Schwidefsky
Browse files

s390: rename psw_bits enums 



The address space enums that must be used when modifying the address
space part of a psw with the psw_bits() macro can easily be confused
with the psw defines that are used to mask and compare directly the
mask part of a psw.
We have e.g. PSW_AS_PRIMARY vs PSW_ASC_PRIMARY.

To avoid confusion rename the PSW_AS_* enums to PSW_BITS_AS_*.

In addition also rename the PSW_AMODE_* enums, so they also follow the
same naming scheme: PSW_BITS_AMODE_*.

Signed-off-by: default avatarHeiko Carstens <heiko.carstens@de.ibm.com>
Signed-off-by: default avatarMartin Schwidefsky <schwidefsky@de.ibm.com>
parent 60c49701

arch/s390/include/asm/ptrace.h

+7 −7
Original line number Diff line number Diff line
@@ -46,16 +46,16 @@ struct psw_bits { 
};



enum {

	PSW_AMODE_24BIT = 0,

	PSW_AMODE_31BIT = 1,

	PSW_AMODE_64BIT = 3

	PSW_BITS_AMODE_24BIT = 0,

	PSW_BITS_AMODE_31BIT = 1,

	PSW_BITS_AMODE_64BIT = 3

};



enum {

	PSW_AS_PRIMARY	 = 0,

	PSW_AS_ACCREG	 = 1,

	PSW_AS_SECONDARY = 2,

	PSW_AS_HOME	 = 3

	PSW_BITS_AS_PRIMARY	= 0,

	PSW_BITS_AS_ACCREG	= 1,

	PSW_BITS_AS_SECONDARY	= 2,

	PSW_BITS_AS_HOME	= 3

};



#define psw_bits(__psw) (*({			\

arch/s390/kernel/uprobes.c

+4 −4
Original line number Diff line number Diff line
@@ -27,9 +27,9 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, 


int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)

{

	if (psw_bits(regs->psw).eaba == PSW_AMODE_24BIT)

	if (psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT)

		return -EINVAL;

	if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_AMODE_31BIT)

	if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT)

		return -EINVAL;

	clear_pt_regs_flag(regs, PIF_PER_TRAP);

	auprobe->saved_per = psw_bits(regs->psw).r;
@@ -372,8 +372,8 @@ static void handle_insn_ril(struct arch_uprobe *auprobe, struct pt_regs *regs) 


bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)

{

	if ((psw_bits(regs->psw).eaba == PSW_AMODE_24BIT) ||

	    ((psw_bits(regs->psw).eaba == PSW_AMODE_31BIT) &&

	if ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT) ||

	    ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT) &&

	     !is_compat_task())) {

		regs->psw.addr = __rewind_psw(regs->psw, UPROBE_SWBP_INSN_SIZE);

		do_report_trap(regs, SIGILL, ILL_ILLADR, NULL);

arch/s390/kvm/gaccess.c

+6 −6
Original line number Diff line number Diff line
@@ -557,20 +557,20 @@ static int get_vcpu_asce(struct kvm_vcpu *vcpu, union asce *asce, 
		return 0;

	}



	if (mode == GACC_IFETCH)

		psw.as = psw.as == PSW_AS_HOME ? PSW_AS_HOME : PSW_AS_PRIMARY;

	if ((mode == GACC_IFETCH) && (psw.as != PSW_BITS_AS_HOME))

		psw.as = PSW_BITS_AS_PRIMARY;



	switch (psw.as) {

	case PSW_AS_PRIMARY:

	case PSW_BITS_AS_PRIMARY:

		asce->val = vcpu->arch.sie_block->gcr[1];

		return 0;

	case PSW_AS_SECONDARY:

	case PSW_BITS_AS_SECONDARY:

		asce->val = vcpu->arch.sie_block->gcr[7];

		return 0;

	case PSW_AS_HOME:

	case PSW_BITS_AS_HOME:

		asce->val = vcpu->arch.sie_block->gcr[13];

		return 0;

	case PSW_AS_ACCREG:

	case PSW_BITS_AS_ACCREG:

		rc = ar_translation(vcpu, asce, ar, mode);

		if (rc > 0)

			return trans_exc(vcpu, rc, ga, ar, mode, PROT_TYPE_ALC);

arch/s390/kvm/gaccess.h

+2 −2
Original line number Diff line number Diff line
@@ -57,9 +57,9 @@ static inline unsigned long kvm_s390_logical_to_effective(struct kvm_vcpu *vcpu, 
{

	psw_t *psw = &vcpu->arch.sie_block->gpsw;



	if (psw_bits(*psw).eaba == PSW_AMODE_64BIT)

	if (psw_bits(*psw).eaba == PSW_BITS_AMODE_64BIT)

		return ga;

	if (psw_bits(*psw).eaba == PSW_AMODE_31BIT)

	if (psw_bits(*psw).eaba == PSW_BITS_AMODE_31BIT)

		return ga & ((1UL << 31) - 1);

	return ga & ((1UL << 24) - 1);

}

arch/s390/kvm/guestdbg.c

+3 −3
Original line number Diff line number Diff line
@@ -613,7 +613,7 @@ int kvm_s390_handle_per_event(struct kvm_vcpu *vcpu) 
		 * instruction. Check primary and home space-switch-event

		 * controls. (theoretically home -> home produced no event)

		 */

		if (((new_as == PSW_AS_HOME) ^ old_as_is_home(vcpu)) &&

		if (((new_as == PSW_BITS_AS_HOME) ^ old_as_is_home(vcpu)) &&

		    (pssec(vcpu) || hssec(vcpu)))

			vcpu->arch.sie_block->iprcc = PGM_SPACE_SWITCH;
@@ -621,7 +621,7 @@ int kvm_s390_handle_per_event(struct kvm_vcpu *vcpu) 
		 * PT, PTI, PR, PC instruction operate on primary AS only. Check

		 * if the primary-space-switch-event control was or got set.

		 */

		if (new_as == PSW_AS_PRIMARY && !old_as_is_home(vcpu) &&

		if (new_as == PSW_BITS_AS_PRIMARY && !old_as_is_home(vcpu) &&

		    (pssec(vcpu) || old_ssec(vcpu)))

			vcpu->arch.sie_block->iprcc = PGM_SPACE_SWITCH;

	}