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Commit 8aef8d92 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: mdss: Update VCO Clk enums for mdss-dsi-28lpm"

parents 3e8c23e9 1878b40d

drivers/clk/qcom/mdss/mdss-dsi-pll-28lpm.c

+5 −5
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 
#include <linux/kernel.h>

#include <linux/err.h>

#include <linux/delay.h>

#include <dt-bindings/clock/mdss-28nm-pll-clk.h>

#include <dt-bindings/clock/mdss-28nm-pll-clk-legacy.h>



#include "mdss-pll.h"

#include "mdss-dsi-pll.h"
@@ -388,13 +388,13 @@ static struct clk_regmap_div dsi1pll_pclk_src = { 
};



static struct clk_hw *mdss_dsi_pllcc_28lpm[] = {

	[VCO_CLK_0] = &dsi0pll_vco_clk.hw,

	[VCOCLK_0] = &dsi0pll_vco_clk.hw,

	[ANALOG_POSTDIV_0_CLK] = &dsi0pll_analog_postdiv.clkr.hw,

	[INDIRECT_PATH_SRC_0_CLK] = &dsi0pll_indirect_path_src.hw,

	[BYTECLK_SRC_MUX_0_CLK] = &dsi0pll_byteclk_src_mux.clkr.hw,

	[BYTECLK_SRC_0_CLK] = &dsi0pll_byteclk_src.hw,

	[PCLK_SRC_0_CLK] = &dsi0pll_pclk_src.clkr.hw,

	[VCO_CLK_1] = &dsi1pll_vco_clk.hw,

	[VCOCLK_1] = &dsi1pll_vco_clk.hw,

	[ANALOG_POSTDIV_1_CLK] = &dsi1pll_analog_postdiv.clkr.hw,

	[INDIRECT_PATH_SRC_1_CLK] = &dsi1pll_indirect_path_src.hw,

	[BYTECLK_SRC_MUX_1_CLK] = &dsi1pll_byteclk_src_mux.clkr.hw,
@@ -486,7 +486,7 @@ int dsi_pll_clock_register_28lpm(struct platform_device *pdev, 
		dsi0pll_pclk_src.clkr.regmap = rmap;



		dsi0pll_vco_clk.priv = pll_res;

		for (i = VCO_CLK_0; i <= PCLK_SRC_0_CLK; i++) {

		for (i = VCOCLK_0; i <= PCLK_SRC_0_CLK; i++) {

			clk = devm_clk_register(&pdev->dev,

						mdss_dsi_pllcc_28lpm[i]);

			if (IS_ERR(clk)) {
@@ -531,7 +531,7 @@ int dsi_pll_clock_register_28lpm(struct platform_device *pdev, 
		dsi1pll_pclk_src.clkr.regmap = rmap;



		dsi1pll_vco_clk.priv = pll_res;

		for (i = VCO_CLK_1; i <= PCLK_SRC_1_CLK; i++) {

		for (i = VCOCLK_1; i <= PCLK_SRC_1_CLK; i++) {

			clk = devm_clk_register(&pdev->dev,

						mdss_dsi_pllcc_28lpm[i]);

			if (IS_ERR(clk)) {

include/dt-bindings/clock/mdss-28nm-pll-clk-legacy.h

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+31 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2016-2019, 2021 The Linux Foundation. All rights reserved.

 */



#ifndef __MDSS_28NM_PLL_CLK_LEGACY_H

#define __MDSS_28NM_PLL_CLK_LEGACY_H



/* DSI PLL clocks */

#define VCOCLK_0		0

#define ANALOG_POSTDIV_0_CLK	1

#define INDIRECT_PATH_SRC_0_CLK	2

#define BYTECLK_SRC_MUX_0_CLK	3

#define BYTECLK_SRC_0_CLK	4

#define PCLK_SRC_0_CLK		5

#define VCOCLK_1		6

#define ANALOG_POSTDIV_1_CLK	7

#define INDIRECT_PATH_SRC_1_CLK	8

#define BYTECLK_SRC_MUX_1_CLK	9

#define BYTECLK_SRC_1_CLK	10

#define PCLK_SRC_1_CLK		11



/* HDMI PLL clocks */

#define HDMI_VCO_CLK			0

#define HDMI_VCO_DIVIDED_1_CLK_SRC	1

#define HDMI_VCO_DIVIDED_TWO_CLK_SRC	2

#define HDMI_VCO_DIVIDED_FOUR_CLK_SRC	3

#define HDMI_VCO_DIVIDED_SIX_CLK_SRC	4

#define HDMI_PCLK_SRC_MUX		5

#define HDMI_PCLK_SRC			6

#endif