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Commit 8a421804 authored by Nirmal Abraham's avatar Nirmal Abraham
Browse files

clk: qcom: mdss: update mdss-dsi-28lpm clk names 



Update byte and pxl clk names in mdss-dsi-pll-28lpm to
match with those defined in gcc-sdm429w. Update the
compatibility string for mdss-dsi-pll-28lpm.

Change-Id: I74675ebee5674b1b0512dddcbc548cee224c7800
Signed-off-by: default avatarNirmal Abraham <nabrah@codeaurora.org>
parent 112597fd

drivers/clk/qcom/mdss/mdss-dsi-pll-28lpm.c

+6 −6
Original line number Diff line number Diff line
@@ -211,7 +211,7 @@ static struct dsi_pll_vco_clk dsi0pll_vco_clk = { 
	.lpfr_lut = lpfr_lut_struct,

	.hw.init = &(struct clk_init_data){

			.name = "dsi0pll_vco_clk",

			.parent_names = (const char *[]){"cxo"},

			.parent_names = (const char *[]){"bi_tcxo"},

			.num_parents = 1,

			.ops = &clk_ops_vco_28lpm,

			.flags = CLK_GET_RATE_NOCACHE,
@@ -236,7 +236,7 @@ static struct dsi_pll_vco_clk dsi1pll_vco_clk = { 
	.lpfr_lut = lpfr_lut_struct,

	.hw.init = &(struct clk_init_data){

			.name = "dsi1pll_vco_clk",

			.parent_names = (const char *[]){"cxo"},

			.parent_names = (const char *[]){"bi_tcxo"},

			.num_parents = 1,

			.ops = &clk_ops_vco_28lpm,

			.flags = CLK_GET_RATE_NOCACHE,
@@ -335,7 +335,7 @@ static struct clk_fixed_factor dsi0pll_byteclk_src = { 
	.div = 4,

	.mult = 1,

	.hw.init = &(struct clk_init_data){

		.name = "dsi0pll_byteclk_src",

		.name = "dsi0_phy_pll_out_byteclk",

		.parent_names = (const char *[]){

				"dsi0pll_byteclk_src_mux"},

		.num_parents = 1,
@@ -348,7 +348,7 @@ static struct clk_fixed_factor dsi1pll_byteclk_src = { 
	.div = 4,

	.mult = 1,

	.hw.init = &(struct clk_init_data){

		.name = "dsi1pll_byteclk_src",

		.name = "dsi1_phy_pll_out_byteclk",

		.parent_names = (const char *[]){

				"dsi1pll_byteclk_src_mux"},

		.num_parents = 1,
@@ -363,7 +363,7 @@ static struct clk_regmap_div dsi0pll_pclk_src = { 
	.width = 8,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi0pll_pclk_src",

			.name = "dsi0_phy_pll_out_dsiclk",

			.parent_names = (const char *[]){"dsi0pll_vco_clk"},

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,
@@ -378,7 +378,7 @@ static struct clk_regmap_div dsi1pll_pclk_src = { 
	.width = 8,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dsi1pll_pclk_src",

			.name = "dsi1_phy_pll_out_dsiclk",

			.parent_names = (const char *[]){"dsi1pll_vco_clk"},

			.num_parents = 1,

			.flags = CLK_GET_RATE_NOCACHE,

drivers/clk/qcom/mdss/mdss-pll.c

+1 −0
Original line number Diff line number Diff line
@@ -395,6 +395,7 @@ static const struct of_device_id mdss_pll_dt_match[] = { 
	{.compatible = "qcom,mdss_dsi_pll_sdm660"},

	{.compatible = "qcom,mdss_dp_pll_sdm660"},

	{.compatible = "qcom,mdss_dsi_pll_12nm"},

	{.compatible = "qcom,mdss_dsi_pll_28lpm"},

	{}

};