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Commit 8a3cf39b authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'amd-xgbe-net' 



Tom Lendacky says:

====================
amd-xgbe: AMD XGBE driver fixes 2014-08-29

The following series of patches includes fixes to the driver.

- Tx hardware queue flushing support dependent on hardware version
- Incorrect reported fifo size
- Proper mmd select in XPCS debugfs support
- Proper queue count for configuring Tx flow control

This patch series is based on net.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents e148e1bf 9fc69aff

drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c

+4 −4
Original line number Diff line number Diff line
@@ -272,7 +272,7 @@ static ssize_t xpcs_reg_value_read(struct file *filp, char __user *buffer, 
	struct xgbe_prv_data *pdata = filp->private_data;

	unsigned int value;



	value = pdata->hw_if.read_mmd_regs(pdata, pdata->debugfs_xpcs_mmd,

	value = XMDIO_READ(pdata, pdata->debugfs_xpcs_mmd,

			   pdata->debugfs_xpcs_reg);



	return xgbe_common_read(buffer, count, ppos, value);
@@ -290,8 +290,8 @@ static ssize_t xpcs_reg_value_write(struct file *filp, 
	if (len < 0)

		return len;



	pdata->hw_if.write_mmd_regs(pdata, pdata->debugfs_xpcs_mmd,

				    pdata->debugfs_xpcs_reg, value);

	XMDIO_WRITE(pdata, pdata->debugfs_xpcs_mmd, pdata->debugfs_xpcs_reg,

		    value);



	return len;

}

drivers/net/ethernet/amd/xgbe/xgbe-dev.c

+11 −4
Original line number Diff line number Diff line
@@ -348,7 +348,7 @@ static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) 


	/* Clear MAC flow control */

	max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;

	q_count = min_t(unsigned int, pdata->rx_q_count, max_q_count);

	q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);

	reg = MAC_Q0TFCR;

	for (i = 0; i < q_count; i++) {

		reg_val = XGMAC_IOREAD(pdata, reg);
@@ -373,7 +373,7 @@ static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) 


	/* Set MAC flow control */

	max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;

	q_count = min_t(unsigned int, pdata->rx_q_count, max_q_count);

	q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);

	reg = MAC_Q0TFCR;

	for (i = 0; i < q_count; i++) {

		reg_val = XGMAC_IOREAD(pdata, reg);
@@ -1633,6 +1633,9 @@ static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) 
{

	unsigned int i, count;



	if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)

		return 0;



	for (i = 0; i < pdata->tx_q_count; i++)

		XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
@@ -1703,8 +1706,8 @@ static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) 
	XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);

}



static unsigned int xgbe_calculate_per_queue_fifo(unsigned long fifo_size,

						  unsigned char queue_count)

static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size,

						  unsigned int queue_count)

{

	unsigned int q_fifo_size = 0;

	enum xgbe_mtl_fifo_size p_fifo = XGMAC_MTL_FIFO_SIZE_256;
@@ -1748,6 +1751,10 @@ static unsigned int xgbe_calculate_per_queue_fifo(unsigned long fifo_size, 
		q_fifo_size = XGBE_FIFO_SIZE_KB(256);

		break;

	}



	/* The configured value is not the actual amount of fifo RAM */

	q_fifo_size = min_t(unsigned int, XGBE_FIFO_MAX, q_fifo_size);



	q_fifo_size = q_fifo_size / queue_count;



	/* Set the queue fifo size programmable value */

drivers/net/ethernet/amd/xgbe/xgbe-drv.c

+2 −0
Original line number Diff line number Diff line
@@ -361,6 +361,8 @@ void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata) 


	memset(hw_feat, 0, sizeof(*hw_feat));



	hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);



	/* Hardware feature register 0 */

	hw_feat->gmii        = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);

	hw_feat->vlhash      = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);

drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c

+4 −3
Original line number Diff line number Diff line
@@ -361,15 +361,16 @@ static void xgbe_get_drvinfo(struct net_device *netdev, 
			     struct ethtool_drvinfo *drvinfo)

{

	struct xgbe_prv_data *pdata = netdev_priv(netdev);

	struct xgbe_hw_features *hw_feat = &pdata->hw_feat;



	strlcpy(drvinfo->driver, XGBE_DRV_NAME, sizeof(drvinfo->driver));

	strlcpy(drvinfo->version, XGBE_DRV_VERSION, sizeof(drvinfo->version));

	strlcpy(drvinfo->bus_info, dev_name(pdata->dev),

		sizeof(drvinfo->bus_info));

	snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "%d.%d.%d",

		 XGMAC_IOREAD_BITS(pdata, MAC_VR, USERVER),

		 XGMAC_IOREAD_BITS(pdata, MAC_VR, DEVID),

		 XGMAC_IOREAD_BITS(pdata, MAC_VR, SNPSVER));

		 XGMAC_GET_BITS(hw_feat->version, MAC_VR, USERVER),

		 XGMAC_GET_BITS(hw_feat->version, MAC_VR, DEVID),

		 XGMAC_GET_BITS(hw_feat->version, MAC_VR, SNPSVER));

	drvinfo->n_stats = XGBE_STATS_COUNT;

}

drivers/net/ethernet/amd/xgbe/xgbe.h

+4 −0
Original line number Diff line number Diff line
@@ -183,6 +183,7 @@ 
#define XGMAC_DRIVER_CONTEXT	1

#define XGMAC_IOCTL_CONTEXT	2



#define XGBE_FIFO_MAX		81920

#define XGBE_FIFO_SIZE_B(x)	(x)

#define XGBE_FIFO_SIZE_KB(x)	(x * 1024)
@@ -526,6 +527,9 @@ struct xgbe_desc_if { 
 * or configurations are present in the device.

 */

struct xgbe_hw_features {

	/* HW Version */

	unsigned int version;



	/* HW Feature Register0 */

	unsigned int gmii;		/* 1000 Mbps support */

	unsigned int vlhash;		/* VLAN Hash Filter */