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Commit 899f8095 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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clk: tegra: Add AHB DMA clock entry 



AHB DMA engine presents on Tegra20/30. Add missing clock entries, so that
driver for the AHB DMA controller could be implemented.

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 109eba2e

drivers/clk/tegra/clk-id.h

+1 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ enum clk_id { 
	tegra_clk_amx,

	tegra_clk_amx1,

	tegra_clk_apb2ape,

	tegra_clk_ahbdma,

	tegra_clk_apbdma,

	tegra_clk_apbif,

	tegra_clk_ape,

drivers/clk/tegra/clk-tegra-periph.c

+1 −0
Original line number Diff line number Diff line
@@ -807,6 +807,7 @@ static struct tegra_periph_init_data gate_clks[] = { 
	GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),

	GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),

	GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),

	GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),

	GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),

	GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),

	GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),

drivers/clk/tegra/clk-tegra20.c

+1 −0
Original line number Diff line number Diff line
@@ -522,6 +522,7 @@ static struct tegra_devclk devclks[] __initdata = { 
};



static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {

	[tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true },

	[tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },

	[tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },

	[tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },

drivers/clk/tegra/clk-tegra30.c

+1 −0
Original line number Diff line number Diff line
@@ -788,6 +788,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = { 
	[tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },

	[tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },

	[tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },

	[tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true },

	[tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },

	[tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },

	[tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },