Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 88de4598 authored by Christoph Hellwig's avatar Christoph Hellwig
Browse files

nvme-pci: clean up SMBSZ bit definitions 



Define the bit positions instead of macros using the magic values,
and move the expanded helpers to calculate the size and size unit into
the implementation C file.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Reviewed-by: default avatarKeith Busch <keith.busch@intel.com>
Reviewed-by: default avatarSagi Grimberg <sagi@grimberg.me>
Reviewed-by: default avatarLogan Gunthorpe <logang@deltatee.com>
parent f65efd6d

drivers/nvme/host/pci.c

+17 −6
Original line number Diff line number Diff line
@@ -1364,7 +1364,7 @@ static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 
static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,

				int qid, int depth)

{

	if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {

	if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {

		unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),

						      dev->ctrl.page_size);

		nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
@@ -1651,9 +1651,21 @@ static ssize_t nvme_cmb_show(struct device *dev, 
}

static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);



static u64 nvme_cmb_size_unit(struct nvme_dev *dev)

{

	u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;



	return 1ULL << (12 + 4 * szu);

}



static u32 nvme_cmb_size(struct nvme_dev *dev)

{

	return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;

}



static void nvme_map_cmb(struct nvme_dev *dev)

{

	u64 szu, size, offset;

	u64 size, offset;

	resource_size_t bar_size;

	struct pci_dev *pdev = to_pci_dev(dev->dev);

	int bar;
@@ -1666,9 +1678,8 @@ static void nvme_map_cmb(struct nvme_dev *dev) 
	if (!use_cmb_sqes)

		return;



	szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));

	size = szu * NVME_CMB_SZ(dev->cmbsz);

	offset = szu * NVME_CMB_OFST(dev->cmbloc);

	size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);

	offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);

	bar = NVME_CMB_BIR(dev->cmbloc);

	bar_size = pci_resource_len(pdev, bar);
@@ -1897,7 +1908,7 @@ static int nvme_setup_io_queues(struct nvme_dev *dev) 
	if (nr_io_queues == 0)

		return 0;



	if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {

	if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {

		result = nvme_cmb_qdepth(dev, nr_io_queues,

				sizeof(struct nvme_command));

		if (result > 0)

include/linux/nvme.h

+14 −8
Original line number Diff line number Diff line
@@ -124,14 +124,20 @@ enum { 


#define NVME_CMB_BIR(cmbloc)	((cmbloc) & 0x7)

#define NVME_CMB_OFST(cmbloc)	(((cmbloc) >> 12) & 0xfffff)

#define NVME_CMB_SZ(cmbsz)	(((cmbsz) >> 12) & 0xfffff)

#define NVME_CMB_SZU(cmbsz)	(((cmbsz) >> 8) & 0xf)



#define NVME_CMB_WDS(cmbsz)	((cmbsz) & 0x10)

#define NVME_CMB_RDS(cmbsz)	((cmbsz) & 0x8)

#define NVME_CMB_LISTS(cmbsz)	((cmbsz) & 0x4)

#define NVME_CMB_CQS(cmbsz)	((cmbsz) & 0x2)

#define NVME_CMB_SQS(cmbsz)	((cmbsz) & 0x1)



enum {

	NVME_CMBSZ_SQS		= 1 << 0,

	NVME_CMBSZ_CQS		= 1 << 1,

	NVME_CMBSZ_LISTS	= 1 << 2,

	NVME_CMBSZ_RDS		= 1 << 3,

	NVME_CMBSZ_WDS		= 1 << 4,



	NVME_CMBSZ_SZ_SHIFT	= 12,

	NVME_CMBSZ_SZ_MASK	= 0xfffff,



	NVME_CMBSZ_SZU_SHIFT	= 8,

	NVME_CMBSZ_SZU_MASK	= 0xf,

};



/*

 * Submission and Completion Queue Entry Sizes for the NVM command set.