Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 884020bf authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter
Browse files

drm/i915: Invalidate TLBs for the rings after a reset 



After any "soft gfx reset" we must manually invalidate the TLBs
associated with each ring. Empirically, it seems that a
suspend/resume or D3-D0 cycle count as a "soft reset". The symptom is
that the hardware would fail to note the new address for its status
page, and so it would continue to write the shadow registers and
breadcrumbs into the old physical address (now used by something
completely different, scary). Whereas the driver would read the new
status page and never see any progress, it would appear that the GPU
hung immediately upon resume.

Based on a patch by naresh kumar kachhi <naresh.kumar.kacchi@intel.com>

Reported-by: default avatarThiago Macieira <thiago@kde.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64725


Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Tested-by: default avatarThiago Macieira <thiago@kde.org>
Cc: stable@vger.kernel.org
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 63b66e5b

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -752,6 +752,8 @@ 
					will not assert AGPBUSY# and will only

					will not assert AGPBUSY# and will only

					be delivered when out of C3. */

					be delivered when out of C3. */

#define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */

#define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */

#define   INSTPM_TLB_INVALIDATE	(1<<9)

#define   INSTPM_SYNC_FLUSH	(1<<5)

#define ACTHD	        0x020c8

#define ACTHD	        0x020c8

#define FW_BLC		0x020d8

#define FW_BLC		0x020d8

#define FW_BLC2		0x020dc

#define FW_BLC2		0x020dc

drivers/gpu/drm/i915/intel_ringbuffer.c

+12 −0
Original line number Original line Diff line number Diff line
@@ -968,6 +968,18 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring) 




	I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);

	I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);

	POSTING_READ(mmio);

	POSTING_READ(mmio);



	/* Flush the TLB for this page */

	if (INTEL_INFO(dev)->gen >= 6) {

		u32 reg = RING_INSTPM(ring->mmio_base);

		I915_WRITE(reg,

			   _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |

					      INSTPM_SYNC_FLUSH));

		if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,

			     1000))

			DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",

				  ring->name);

	}

}

}





static int

static int