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Commit 87f761ec authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'qed-next' 



Yuval Mintz says:

====================
qed: Attention support patch series

Until now we've only enabled attention generation for the sake of
management firmware indications [required for link notifications].

This series enables [almost] all the attention sources of the HW,
currently for the sake of logging information relating to issues
experienced by HW. In future, infrastructure laid here would also be used
for the sake of the recovery process.

The first patch in the series is a semantic alignemnt of the code.
The later 3 patches incremently create said infrastructure and enrich
the logged information.
Notice #3 contains quite a bit of structures [consisting of ~1K lines]
that will eventually be removed and incorporated in the binary fw file.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 64d4e343 b4149dc7

drivers/net/ethernet/qlogic/qed/qed_dev.c

+5 −1
Original line number Diff line number Diff line
@@ -1011,13 +1011,17 @@ static void qed_hw_get_resc(struct qed_hwfn *p_hwfn) 
{

	u32 *resc_start = p_hwfn->hw_info.resc_start;

	u32 *resc_num = p_hwfn->hw_info.resc_num;

	struct qed_sb_cnt_info sb_cnt_info;

	int num_funcs, i;



	num_funcs = MAX_NUM_PFS_BB;



	memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));

	qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);



	resc_num[QED_SB] = min_t(u32,

				 (MAX_SB_PER_PATH_BB / num_funcs),

				 qed_int_get_num_sbs(p_hwfn, NULL));

				 sb_cnt_info.sb_cnt);

	resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs;

	resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs;

	resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs;

drivers/net/ethernet/qlogic/qed/qed_int.c

+2088 −107

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/qlogic/qed/qed_int.h

+3 −3
Original line number Diff line number Diff line
@@ -161,12 +161,12 @@ void qed_int_sp_dpc(unsigned long hwfn_cookie); 
 *        blocks configured for this funciton in the igu.

 *

 * @param p_hwfn

 * @param p_iov_blks - configured free blks for vfs

 * @param p_sb_cnt_info

 *

 * @return int - number of status blocks configured

 */

int qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,

			int *p_iov_blks);

void qed_int_get_num_sbs(struct qed_hwfn	*p_hwfn,

			 struct qed_sb_cnt_info *p_sb_cnt_info);



/**

 * @brief qed_int_disable_post_isr_release - performs the cleanup post ISR

drivers/net/ethernet/qlogic/qed/qed_main.c

+9 −6
Original line number Diff line number Diff line
@@ -634,15 +634,18 @@ static int qed_get_int_fp(struct qed_dev *cdev, struct qed_int_info *info) 
static int qed_slowpath_setup_int(struct qed_dev *cdev,

				  enum qed_int_mode int_mode)

{

	int rc, i;

	u8 num_vectors = 0;



	struct qed_sb_cnt_info sb_cnt_info;

	int rc;

	int i;

	memset(&cdev->int_params, 0, sizeof(struct qed_int_params));



	cdev->int_params.in.int_mode = int_mode;

	for_each_hwfn(cdev, i)

		num_vectors +=  qed_int_get_num_sbs(&cdev->hwfns[i], NULL) + 1;

	cdev->int_params.in.num_vectors = num_vectors;

	for_each_hwfn(cdev, i) {

		memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));

		qed_int_get_num_sbs(&cdev->hwfns[i], &sb_cnt_info);

		cdev->int_params.in.num_vectors += sb_cnt_info.sb_cnt;

		cdev->int_params.in.num_vectors++; /* slowpath */

	}



	/* We want a minimum of one slowpath and one fastpath vector per hwfn */

	cdev->int_params.in.min_msix_cnt = cdev->num_hwfns * 2;

drivers/net/ethernet/qlogic/qed/qed_reg_addr.h

+60 −0
Original line number Diff line number Diff line
@@ -127,8 +127,20 @@ 
	0x00c000UL

#define  DORQ_REG_IFEN \

	0x100040UL

#define DORQ_REG_DB_DROP_REASON \

	0x100a2cUL

#define DORQ_REG_DB_DROP_DETAILS \

	0x100a24UL

#define DORQ_REG_DB_DROP_DETAILS_ADDRESS \

	0x100a1cUL

#define  GRC_REG_TIMEOUT_EN \

	0x050404UL

#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \

	0x050054UL

#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \

	0x05004cUL

#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \

	0x050050UL

#define  IGU_REG_BLOCK_CONFIGURATION \

	0x180040UL

#define  MCM_REG_INIT \
@@ -155,6 +167,40 @@ 
	0x1100000UL

#define  PGLUE_B_REG_ADMIN_PER_PF_REGION	\

	0x2a9000UL

#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \

	0x2aa150UL

#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \

	0x2aa144UL

#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \

	0x2aa148UL

#define PGLUE_B_REG_TX_ERR_WR_DETAILS \

	0x2aa14cUL

#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \

	0x2aa154UL

#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \

	0x2aa158UL

#define PGLUE_B_REG_TX_ERR_RD_DETAILS \

	0x2aa15cUL

#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \

	0x2aa160UL

#define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \

	0x2aa164UL

#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \

	0x2aa54cUL

#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \

	0x2aa544UL

#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \

	0x2aa548UL

#define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \

	0x2aae74UL

#define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \

	0x2aae78UL

#define PGLUE_B_REG_VF_ILT_ERR_DETAILS \

	0x2aae7cUL

#define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \

	0x2aae80UL

#define PGLUE_B_REG_LATCHED_ERRORS_CLR \

	0x2aa3bcUL

#define  PRM_REG_DISABLE_PRM \

	0x230000UL

#define  PRS_REG_SOFT_RST \
@@ -171,6 +217,14 @@ 
	0x2a0040UL

#define  PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \

	0x29e050UL

#define PSWHST_REG_INCORRECT_ACCESS_VALID \

	0x2a0070UL

#define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \

	0x2a0074UL

#define PSWHST_REG_INCORRECT_ACCESS_DATA \

	0x2a0068UL

#define PSWHST_REG_INCORRECT_ACCESS_LENGTH \

	0x2a006cUL

#define  PSWRD_REG_DBG_SELECT \

	0x29c040UL

#define  PSWRD2_REG_CONF11 \
@@ -333,6 +387,8 @@ 
	0x180800UL

#define  MISC_REG_AEU_ENABLE1_IGU_OUT_0 \

	0x00849cUL

#define MISC_REG_AEU_AFTER_INVERT_1_IGU	\

	0x0087b4UL

#define  MISC_REG_AEU_MASK_ATTN_IGU \

	0x008494UL

#define  IGU_REG_CLEANUP_STATUS_0 \
@@ -363,6 +419,10 @@ 
		0x7 << 0)

#define  MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \

	0

#define MCP_REG_CPU_STATE \

	0xe05004UL

#define MCP_REG_CPU_EVENT_MASK \

	0xe05008UL

#define PGLUE_B_REG_PF_BAR0_SIZE \

	0x2aae60UL

#define PGLUE_B_REG_PF_BAR1_SIZE \