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Commit 8726e96f authored by Stephen Warren's avatar Stephen Warren
Browse files

ARM: ux500: convert timer suspend/resume to clock_event_device 



Move ux500's timer suspend/resume functions from struct sys_timer
ux500_timer into struct clock_event_device nmdk_clkevt. This
will allow the sys_timer suspend/resume fields to be removed, and
eventually lead to a complete removal of struct sys_timer.

Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
parent e3cbfb62

arch/arm/mach-ux500/timer.c

+0 −7
Original line number Diff line number Diff line
@@ -100,13 +100,6 @@ static void __init ux500_timer_init(void) 
	ux500_twd_init();

}



static void ux500_timer_reset(void)

{

	nmdk_clkevt_reset();

	nmdk_clksrc_reset();

}



struct sys_timer ux500_timer = {

	.init		= ux500_timer_init,

	.resume		= ux500_timer_reset,

};

drivers/clocksource/nomadik-mtu.c

+20 −13
Original line number Diff line number Diff line
@@ -134,12 +134,32 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode, 
	}

}



void nmdk_clksrc_reset(void)

{

	/* Disable */

	writel(0, mtu_base + MTU_CR(0));



	/* ClockSource: configure load and background-load, and fire it up */

	writel(nmdk_cycle, mtu_base + MTU_LR(0));

	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));



	writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,

	       mtu_base + MTU_CR(0));

}



static void nmdk_clkevt_resume(struct clock_event_device *cedev)

{

	nmdk_clkevt_reset();

	nmdk_clksrc_reset();

}



static struct clock_event_device nmdk_clkevt = {

	.name		= "mtu_1",

	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,

	.rating		= 200,

	.set_mode	= nmdk_clkevt_mode,

	.set_next_event	= nmdk_clkevt_next,

	.resume		= nmdk_clkevt_resume,

};



/*
@@ -161,19 +181,6 @@ static struct irqaction nmdk_timer_irq = { 
	.dev_id		= &nmdk_clkevt,

};



void nmdk_clksrc_reset(void)

{

	/* Disable */

	writel(0, mtu_base + MTU_CR(0));



	/* ClockSource: configure load and background-load, and fire it up */

	writel(nmdk_cycle, mtu_base + MTU_LR(0));

	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));



	writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,

	       mtu_base + MTU_CR(0));

}



void __init nmdk_timer_init(void __iomem *base, int irq)

{

	unsigned long rate;