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Commit 85fa532b authored by Mike Dyer's avatar Mike Dyer Committed by Mark Brown
Browse files

ASoC: wm8960: Fix PLL register writes 



Bit 9 of PLL2,3 and 4 is reserved as '0'. The 24bit fractional part
should be split across each register in 8bit chunks.

Signed-off-by: default avatarMike Dyer <mike.dyer@md-soft.co.uk>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
Cc: stable@vger.kernel.org
parent d4e4ab86

sound/soc/codecs/wm8960.c

+3 −3
Original line number Diff line number Diff line
@@ -857,9 +857,9 @@ static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, 
	if (pll_div.k) {

		reg |= 0x20;



		snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 18) & 0x3f);

		snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 9) & 0x1ff);

		snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0x1ff);

		snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff);

		snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff);

		snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff);

	}

	snd_soc_write(codec, WM8960_PLL1, reg);