clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs (85de143f) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/clk/qcom/clk-alpha-pll.c

+351 −11

Original line number	Diff line number	Diff line
		@@ -32,6 +32,7 @@
		# define PLL_LOCK_DET BIT(31)

		#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
		#define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
		#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
		#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])

		@@ -44,11 +45,14 @@
		# define PLL_VCO_MASK 0x3

		#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
		#define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])

		#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
		#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
		#define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
		#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
		#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
		#define PLL_TEST_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
		#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
		#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
		#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
		@@ -96,6 +100,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
		[PLL_OFF_OPMODE] = 0x2c,
		[PLL_OFF_FRAC] = 0x38,
		},
		[CLK_ALPHA_PLL_TYPE_LUCID] = {
		[PLL_OFF_L_VAL] = 0x04,
		[PLL_OFF_CAL_L_VAL] = 0x08,
		[PLL_OFF_USER_CTL] = 0x0c,
		[PLL_OFF_USER_CTL_U] = 0x10,
		[PLL_OFF_USER_CTL_U1] = 0x14,
		[PLL_OFF_CONFIG_CTL] = 0x18,
		[PLL_OFF_CONFIG_CTL_U] = 0x1c,
		[PLL_OFF_CONFIG_CTL_U1] = 0x20,
		[PLL_OFF_TEST_CTL] = 0x24,
		[PLL_OFF_TEST_CTL_U] = 0x28,
		[PLL_OFF_TEST_CTL_U1] = 0x2c,
		[PLL_OFF_STATUS] = 0x30,
		[PLL_OFF_OPMODE] = 0x38,
		[PLL_OFF_ALPHA_VAL] = 0x40,
		},
		};
		EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);

		@@ -114,11 +134,15 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
		#define PLL_HUAYRA_N_MASK 0xff
		#define PLL_HUAYRA_ALPHA_WIDTH 16

		#define FABIA_OPMODE_STANDBY 0x0
		#define FABIA_OPMODE_RUN 0x1
		#define PLL_OPMODE_STANDBY 0x0
		#define PLL_OPMODE_RUN 0x1

		#define PLL_OUT_MASK 0x7
		#define PLL_OUT_RATE_MARGIN 500

		#define FABIA_PLL_OUT_MASK 0x7
		#define FABIA_PLL_RATE_MARGIN 500
		/* LUCID PLL specific settings and offsets */
		#define LUCID_PLL_CAL_VAL 0x44
		#define LUCID_PCAL_DONE BIT(26)

		#define pll_alpha_width(p) \
		((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
		@@ -940,14 +964,14 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
		return ret;

		/* Skip If PLL is already running */
		if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL))
		if ((opmode_val & PLL_OPMODE_RUN) && (val & PLL_OUTCTRL))
		return 0;

		ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
		if (ret)
		return ret;

		ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
		ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_OPMODE_STANDBY);
		if (ret)
		return ret;

		@@ -956,7 +980,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
		if (ret)
		return ret;

		ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN);
		ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_OPMODE_RUN);
		if (ret)
		return ret;

		@@ -965,7 +989,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
		return ret;

		ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
		FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK);
		PLL_OUT_MASK, PLL_OUT_MASK);
		if (ret)
		return ret;

		@@ -995,13 +1019,13 @@ static void alpha_pll_fabia_disable(struct clk_hw *hw)
		return;

		/* Disable main outputs */
		ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK,
		ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK,
		0);
		if (ret)
		return;

		/* Place the PLL in STANDBY */
		regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
		regmap_write(regmap, PLL_OPMODE(pll), PLL_OPMODE_STANDBY);
		}

		static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
		@@ -1035,7 +1059,7 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
		* Due to limited number of bits for fractional rate programming, the
		* rounded up rate could be marginally higher than the requested rate.
		*/
		if (rrate > (rate + FABIA_PLL_RATE_MARGIN) \|\| rrate < rate) {
		if (rrate > (rate + PLL_OUT_RATE_MARGIN) \|\| rrate < rate) {
		pr_err("Call set rate on the PLL with rounded rates!\n");
		return -EINVAL;
		}
		@@ -1149,3 +1173,319 @@ const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
		.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
		};
		EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);

		static int lucid_pll_is_enabled(struct clk_alpha_pll *pll,
		struct regmap *regmap)
		{
		u32 mode_regval, opmode_regval;
		int ret;

		ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval);
		ret \|= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval);
		if (ret)
		return 0;

		return ((opmode_regval & PLL_OPMODE_RUN) &&
		(mode_regval & PLL_OUTCTRL));
		}

		int alpha_pll_lucid_configure(struct clk_alpha_pll pll, struct regmap regmap,
		const struct alpha_pll_config *config)
		{
		int ret;

		if (lucid_pll_is_enabled(pll, regmap)) {
		pr_warn("PLL is already enabled. Skipping configuration.\n");
		return 0;
		}

		/*
		* Disable the PLL if it's already been initialized. Not doing so might
		* lead to the PLL running with the old frequency configuration.
		*/
		if (pll->inited) {
		ret = regmap_update_bits(regmap, PLL_MODE(pll),
		PLL_RESET_N, 0);
		if (ret)
		return ret;
		}

		if (config->l)
		regmap_write(regmap, PLL_L_VAL(pll), config->l);

		regmap_write(regmap, PLL_CAL_L_VAL(pll), LUCID_PLL_CAL_VAL);

		if (config->alpha)
		regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
		if (config->config_ctl_val)
		regmap_write(regmap, PLL_CONFIG_CTL(pll),
		config->config_ctl_val);

		if (config->config_ctl_hi_val)
		regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
		config->config_ctl_hi_val);

		if (config->config_ctl_hi1_val)
		regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),
		config->config_ctl_hi1_val);

		if (config->post_div_mask)
		regmap_update_bits(regmap, PLL_USER_CTL(pll),
		config->post_div_mask, config->post_div_val);

		regmap_update_bits(regmap, PLL_MODE(pll),
		PLL_UPDATE_BYPASS,
		PLL_UPDATE_BYPASS);

		/* Disable PLL output */
		ret = regmap_update_bits(regmap, PLL_MODE(pll),
		PLL_OUTCTRL, 0);
		if (ret)
		return ret;

		/* Set operation mode to OFF */
		regmap_write(regmap, PLL_OPMODE(pll), PLL_OPMODE_STANDBY);

		/* PLL should be in OFF mode before continuing */
		wmb();

		/* Place the PLL in STANDBY mode */
		ret = regmap_update_bits(regmap, PLL_MODE(pll),
		PLL_RESET_N, PLL_RESET_N);
		if (ret)
		return ret;

		pll->inited = true;
		return 0;
		}

		static int alpha_pll_lucid_enable(struct clk_hw *hw)
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		u32 val;
		int ret;

		ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
		if (ret)
		return ret;

		/* If in FSM mode, just vote for it */
		if (val & PLL_VOTE_FSM_ENA) {
		ret = clk_enable_regmap(hw);
		if (ret)
		return ret;
		return wait_for_pll_enable_active(pll);
		}

		if (unlikely(!pll->inited)) {
		ret = alpha_pll_lucid_configure(pll, pll->clkr.regmap,
		pll->config);
		if (ret) {
		pr_err("Failed to configure %s\n", clk_hw_get_name(hw));
		return ret;
		}
		}

		/* Set operation mode to RUN */
		regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_OPMODE_RUN);

		ret = wait_for_pll_enable_lock(pll);
		if (ret)
		return ret;

		/* Enable the PLL outputs */
		ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
		PLL_OUT_MASK, PLL_OUT_MASK);
		if (ret)
		return ret;

		/* Enable the global PLL outputs */
		ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
		PLL_OUTCTRL, PLL_OUTCTRL);
		if (ret)
		return ret;

		/* Ensure that the write above goes through before returning. */
		mb();
		return ret;
		}

		static void alpha_pll_lucid_disable(struct clk_hw *hw)
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		u32 val;
		int ret;

		ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
		if (ret)
		return;

		/* If in FSM mode, just unvote it */
		if (val & PLL_VOTE_FSM_ENA) {
		clk_disable_regmap(hw);
		return;
		}

		/* Disable the global PLL output */
		ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
		PLL_OUTCTRL, 0);
		if (ret)
		return;

		/* Disable the PLL outputs */
		ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
		PLL_OUT_MASK, 0);
		if (ret)
		return;

		/* Place the PLL mode in STANDBY */
		regmap_write(pll->clkr.regmap, PLL_OPMODE(pll),
		PLL_OPMODE_STANDBY);

		regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N,
		PLL_RESET_N);
		}

		/*
		* The Lucid PLL requires a power-on self-calibration which happens when the
		* PLL comes out of reset. The calibration is performed at an output frequency
		* of ~1300 MHz which means that SW will have to vote on a voltage that's
		* equal to or greater than SVS_L1 on the corresponding rail. Since this is not
		* feasable to do in the atomic enable path, temporarily bring up the PLL here,
		* let it calibrate, and place it in standby before returning.
		*/
		static int alpha_pll_lucid_prepare(struct clk_hw *hw)
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		struct clk_hw *p;
		u32 regval;
		unsigned long prate;
		int ret;

		/* Return early if calibration is not needed. */
		regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &regval);
		if (regval & LUCID_PCAL_DONE)
		return 0;

		p = clk_hw_get_parent(hw);
		if (!p)
		return -EINVAL;

		prate = clk_hw_get_rate(p);
		if (!prate)
		return -EINVAL;

		ret = clk_vote_rate_vdd(hw->core, LUCID_PLL_CAL_VAL * prate);
		if (ret)
		return ret;

		ret = alpha_pll_lucid_enable(hw);
		if (ret)
		goto ret_path;

		alpha_pll_lucid_disable(hw);
		ret_path:
		clk_unvote_rate_vdd(hw->core, LUCID_PLL_CAL_VAL * prate);
		return 0;
		}

		static unsigned long
		alpha_pll_lucid_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		u32 l, frac;

		regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
		regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);

		return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_REG_16BIT_WIDTH);
		}

		static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long prate)
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		unsigned long rrate;
		u32 regval, l;
		u64 a;
		int ret;

		rrate = alpha_pll_round_rate(rate, prate, &l, &a,
		ALPHA_REG_16BIT_WIDTH);
		/*
		* Due to a limited number of bits for fractional rate programming, the
		* rounded up rate could be marginally higher than the requested rate.
		*/
		if (rrate > (rate + PLL_OUT_RATE_MARGIN) \|\| rrate < rate) {
		pr_err("Call set rate on the PLL with rounded rates!\n");
		return -EINVAL;
		}

		regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
		regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);

		/* Latch the PLL input */
		ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
		PLL_UPDATE, PLL_UPDATE);
		if (ret)
		return ret;

		/* Wait for 2 reference cycles before checking the ACK bit. */
		udelay(1);
		regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);
		if (!(regval & ALPHA_PLL_ACK_LATCH)) {
		WARN(1, "PLL latch failed. Output may be unstable!\n");
		return -EINVAL;
		}

		/* Return the latch input to 0 */
		ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
		PLL_UPDATE, 0);
		if (ret)
		return ret;

		if (clk_hw_is_enabled(hw)) {
		ret = wait_for_pll_enable_lock(pll);
		if (ret)
		return ret;
		}

		/* Wait for PLL output to stabilize */
		udelay(100);
		return 0;
		}

		static int alpha_pll_lucid_is_enabled(struct clk_hw *hw)
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

		return lucid_pll_is_enabled(pll, pll->clkr.regmap);
		}

		const struct clk_ops clk_alpha_pll_lucid_ops = {
		.prepare = alpha_pll_lucid_prepare,
		.enable = alpha_pll_lucid_enable,
		.disable = alpha_pll_lucid_disable,
		.is_enabled = alpha_pll_lucid_is_enabled,
		.recalc_rate = alpha_pll_lucid_recalc_rate,
		.round_rate = clk_alpha_pll_round_rate,
		.set_rate = alpha_pll_lucid_set_rate,
		.list_registers = clk_alpha_pll_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);

		const struct clk_ops clk_alpha_pll_fixed_lucid_ops = {
		.enable = alpha_pll_lucid_enable,
		.disable = alpha_pll_lucid_disable,
		.is_enabled = alpha_pll_lucid_is_enabled,
		.recalc_rate = alpha_pll_lucid_recalc_rate,
		.round_rate = clk_alpha_pll_round_rate,
		};
		EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_ops);

		const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
		.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
		.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
		.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
		};
		EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);

drivers/clk/qcom/clk-alpha-pll.h

+15 −1

Original line number	Diff line number	Diff line
		@@ -13,19 +13,24 @@ enum {
		CLK_ALPHA_PLL_TYPE_HUAYRA,
		CLK_ALPHA_PLL_TYPE_BRAMMO,
		CLK_ALPHA_PLL_TYPE_FABIA,
		CLK_ALPHA_PLL_TYPE_LUCID,
		CLK_ALPHA_PLL_TYPE_MAX,
		};

		enum {
		PLL_OFF_L_VAL,
		PLL_OFF_CAL_L_VAL,
		PLL_OFF_ALPHA_VAL,
		PLL_OFF_ALPHA_VAL_U,
		PLL_OFF_USER_CTL,
		PLL_OFF_USER_CTL_U,
		PLL_OFF_USER_CTL_U1,
		PLL_OFF_CONFIG_CTL,
		PLL_OFF_CONFIG_CTL_U,
		PLL_OFF_CONFIG_CTL_U1,
		PLL_OFF_TEST_CTL,
		PLL_OFF_TEST_CTL_U,
		PLL_OFF_TEST_CTL_U1,
		PLL_OFF_STATUS,
		PLL_OFF_OPMODE,
		PLL_OFF_FRAC,
		@@ -43,6 +48,7 @@ struct pll_vco {
		/**
		* struct clk_alpha_pll - phase locked loop (PLL)
		* @offset: base address of registers
		* @inited: flag that's set when the PLL is initialized
		* @vco_table: array of VCO settings
		* @regs: alpha pll register map (see @clk_alpha_pll_regs)
		* @clkr: regmap clock handle
		@@ -50,6 +56,8 @@ struct pll_vco {
		struct clk_alpha_pll {
		u32 offset;
		const u8 *regs;
		struct alpha_pll_config *config;
		bool inited;

		const struct pll_vco *vco_table;
		size_t num_vco;
		@@ -89,6 +97,7 @@ struct alpha_pll_config {
		u32 alpha_hi;
		u32 config_ctl_val;
		u32 config_ctl_hi_val;
		u32 config_ctl_hi1_val;
		u32 main_output_mask;
		u32 aux_output_mask;
		u32 aux2_output_mask;
		@@ -113,9 +122,14 @@ extern const struct clk_ops clk_alpha_pll_fabia_ops;
		extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
		extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;

		extern const struct clk_ops clk_alpha_pll_lucid_ops;
		extern const struct clk_ops clk_alpha_pll_fixed_lucid_ops;
		extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;

		void clk_alpha_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
		const struct alpha_pll_config *config);
		void clk_fabia_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
		const struct alpha_pll_config *config);

		int clk_lucid_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
		const struct alpha_pll_config *config);
		#endif