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Commit 85ba7b7d authored by Daniel Vetter's avatar Daniel Vetter
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Revert "drm/i915: Mask reserved bits in display/sprite address registers" 



This reverts commit 446f2545.

I've left the masking in the pageflip code since that seems to be some
useful piece of preemptive robustness.

Iirc I've merged this patch under the assumption that the BIOS leaves
some random gunk in the lower bits and gets unhappy if we trample on
them. We have quite a few case like this, so this made sense.

Now I've just learned that there's actual hardware features bits in
the low 12 bits, and the kernel needs to preserve them to allow a
userspace blob to do its job. Given Dave Airlie's clear stance on
userspace blob drivers I've quickly chatted with him and he doesn't
seem too happy. So let's revert this.

If there are indeed bits that we must preserve in this range then we
can ressurrect this patch, but with proper documentation for those
bits supplied. And we probably also need to think a bit about
interactions with our driver.

Cc: Armin Reese <armin.c.reese@intel.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Dave Airlie <airlied@linux.ie>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 232a6ee9

drivers/gpu/drm/i915/i915_reg.h

+0 −2
Original line number Diff line number Diff line
@@ -3578,8 +3578,6 @@ 
#define DISP_BASEADDR_MASK	(0xfffff000)

#define I915_LO_DISPBASE(val)	(val & ~DISP_BASEADDR_MASK)

#define I915_HI_DISPBASE(val)	(val & DISP_BASEADDR_MASK)

#define I915_MODIFY_DISPBASE(reg, gfx_addr) \

		(I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg))))



/* VBIOS flags */

#define SWF00			(dev_priv->info->display_mmio_offset + 0x71410)

drivers/gpu/drm/i915/intel_display.c

+4 −4
Original line number Diff line number Diff line
@@ -2114,7 +2114,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, 
		      fb->pitches[0]);

	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);

	if (INTEL_INFO(dev)->gen >= 4) {

		I915_MODIFY_DISPBASE(DSPSURF(plane),

		I915_WRITE(DSPSURF(plane),

			   i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);

		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);

		I915_WRITE(DSPLINOFF(plane), linear_offset);
@@ -2205,7 +2205,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc, 
		      i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,

		      fb->pitches[0]);

	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);

	I915_MODIFY_DISPBASE(DSPSURF(plane),

	I915_WRITE(DSPSURF(plane),

		   i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);

	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {

		I915_WRITE(DSPOFFSET(plane), (y << 16) | x);

drivers/gpu/drm/i915/intel_sprite.c

+9 −9
Original line number Diff line number Diff line
@@ -141,7 +141,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, 


	I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);

	I915_WRITE(SPCNTR(pipe, plane), sprctl);

	I915_MODIFY_DISPBASE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +

	I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +

		   sprsurf_offset);

	POSTING_READ(SPSURF(pipe, plane));

}
@@ -158,7 +158,7 @@ vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc) 
	I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &

		   ~SP_ENABLE);

	/* Activate double buffered register update */

	I915_MODIFY_DISPBASE(SPSURF(pipe, plane), 0);

	I915_WRITE(SPSURF(pipe, plane), 0);

	POSTING_READ(SPSURF(pipe, plane));



	intel_update_sprite_watermarks(dplane, crtc, 0, 0, false, false);
@@ -315,7 +315,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 
	if (intel_plane->can_scale)

		I915_WRITE(SPRSCALE(pipe), sprscale);

	I915_WRITE(SPRCTL(pipe), sprctl);

	I915_MODIFY_DISPBASE(SPRSURF(pipe),

	I915_WRITE(SPRSURF(pipe),

		   i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);

	POSTING_READ(SPRSURF(pipe));

}
@@ -333,7 +333,7 @@ ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) 
	if (intel_plane->can_scale)

		I915_WRITE(SPRSCALE(pipe), 0);

	/* Activate double buffered register update */

	I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);

	I915_WRITE(SPRSURF(pipe), 0);

	POSTING_READ(SPRSURF(pipe));



	/*
@@ -489,7 +489,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, 
	I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);

	I915_WRITE(DVSSCALE(pipe), dvsscale);

	I915_WRITE(DVSCNTR(pipe), dvscntr);

	I915_MODIFY_DISPBASE(DVSSURF(pipe),

	I915_WRITE(DVSSURF(pipe),

		   i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);

	POSTING_READ(DVSSURF(pipe));

}
@@ -506,7 +506,7 @@ ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc) 
	/* Disable the scaler */

	I915_WRITE(DVSSCALE(pipe), 0);

	/* Flush double buffered register updates */

	I915_MODIFY_DISPBASE(DVSSURF(pipe), 0);

	I915_WRITE(DVSSURF(pipe), 0);

	POSTING_READ(DVSSURF(pipe));



	/*