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Commit 85a09bf4 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-4.17' of... 

Merge tag 'phy-for-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy

 into usb-next

Kishon writes:

phy: for 4.17

 *) Add USB PHY driver for MDM6600 on Droid
 *) Add USB PHY driver for STM32 USB PHY Controller
 *) Add inno-usb2-phy driver for hi3798cv200 SoC
 *) Add combo phy driver (SATA/USB/PCIE) for HiSilicon STB SoCs
 *) Add USB3 PHY driver for Meson GXL and GXM
 *) Add support for R8A77965 Gen3 USB 2.0 PHY in phy-rcar-gen3-usb2 driver
 *) Add support for qualcomm QUSB2 V2 and QMP V3 USB3 PHY in phy-qcom-qusb2
    and phy-qcom-qmp PHY driver respectively
 *) Add support for runtime PM in phy-qcom-qusb2 and phy-qcom-qmp PHY drivers
 *) Add support for Allwinner R40 USB PHY in sun4i-usb PHY driver
 *) Add support in rockchip-typec PHY driver to make extcon optional and
    fallback to working in host mode if extcon is missing
 *) Add support in rockchip-typec PHY driver to mux PHYs connected to DP
 *) Add support to configure slew rate parameters in phy-mtk-tphy PHY driver
 *) Add workaround for missing Vbus det interrupts on Allwinner A23/A33
 *) Add USB speed related PHY modes in phy core
 *) Fix PHY 'structure' documentation
 *) Force rockchip-typec PHY to USB2 if DP-only mode is used
 *) Fix phy-qcom-qusb2 and phy-qcom-qmp PHY drivers to follow PHY reset and
    initialization sequence as per hardware programming manual
 *) Fix Marvell BG2CD SoC USB failure in phy-berlin-usb driver
 *) Minor fixes in lpc18xx-usb-otg, xusb-tegra210 and phy-rockchip-emmc PHY
    drivers

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parents a8f25c36 e7f4da4c

Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt

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Original line number Diff line number Diff line
@@ -74,6 +74,29 @@ Example: 
		reboot-offset = <0x4>;

	};



-----------------------------------------------------------------------

Hisilicon Hi3798CV200 Peripheral Controller



The Hi3798CV200 Peripheral Controller controls peripherals, queries

their status, and configures some functions of peripherals.



Required properties:

- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon"

  and "simple-mfd".

- reg: Register address and size of Peripheral Controller.

- #address-cells: Should be 1.

- #size-cells: Should be 1.



Examples:



	perictrl: peripheral-controller@8a20000 {

		compatible = "hisilicon,hi3798cv200-perictrl", "syscon",

			     "simple-mfd";

		reg = <0x8a20000 0x1000>;

		#address-cells = <1>;

		#size-cells = <1>;

	};



-----------------------------------------------------------------------

Hisilicon Hi6220 system controller

Documentation/devicetree/bindings/phy/meson-gxl-usb2-phy.txt

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@@ -6,6 +6,10 @@ Required properties: 
- #phys-cells:	must be 0 (see phy-bindings.txt in this directory)



Optional properties:

- clocks:	a phandle to the clock of this PHY

- clock-names:	must be "phy"

- resets:	a phandle to the reset line of this PHY

- reset-names:	must be "phy"

- phy-supply:	see phy-bindings.txt in this directory

Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt

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* Amlogic Meson GXL and GXM USB3 PHY and OTG detection binding



Required properties:

- compatible:	Should be "amlogic,meson-gxl-usb3-phy"

- #phys-cells:	must be 0 (see phy-bindings.txt in this directory)

- reg:		The base address and length of the registers

- interrupts:	the interrupt specifier for the OTG detection

- clocks:	phandles to the clocks for

		- the USB3 PHY

		- and peripheral mode/OTG detection

- clock-names:	must contain "phy" and "peripheral"

- resets:	phandle to the reset lines for:

		- the USB3 PHY and

		- peripheral mode/OTG detection

- reset-names:	must contain "phy" and "peripheral"



Optional properties:

- phy-supply:	see phy-bindings.txt in this directory





Example:

	usb3_phy0: phy@78080 {

		compatible = "amlogic,meson-gxl-usb3-phy";

		#phy-cells = <0>;

		reg = <0x0 0x78080 0x0 0x20>;

		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&clkc CLKID_USB_OTG>, <&clkc_AO CLKID_AO_CEC_32K>;

		clock-names = "phy", "peripheral";

		resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;

		reset-names = "phy", "peripheral";

	};

Documentation/devicetree/bindings/phy/phy-hi3798cv200-combphy.txt

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HiSilicon STB PCIE/SATA/USB3 PHY



Required properties:

- compatible: Should be "hisilicon,hi3798cv200-combphy"

- reg: Should be the address space for COMBPHY configuration and state

  registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and

  PERI_COMBPHY0_STATE for COMBPHY0 Hi3798CV200 SoC.

- #phy-cells: Should be 1.  The cell number is used to select the phy mode

  as defined in <dt-bindings/phy/phy.h>.

- clocks: The phandle to clock provider and clock specifier pair.

- resets: The phandle to reset controller and reset specifier pair.



Refer to phy/phy-bindings.txt for the generic PHY binding properties.



Optional properties:

- hisilicon,fixed-mode: If the phy device doesn't support mode select

  but a fixed mode setting, the property should be present to specify

  the particular mode.

- hisilicon,mode-select-bits: If the phy device support mode select,

  this property should be present to specify the register bits in

  peripheral controller, as a 3 integers tuple:

  <register_offset bit_shift bit_mask>.



Notes:

- Between hisilicon,fixed-mode and hisilicon,mode-select-bits, one and only

  one of them should be present.

- The device node should be a child of peripheral controller that contains

  COMBPHY configuration/state and PERI_CTRL register used to select PHY mode.

  Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller

  bindings.



Examples:



perictrl: peripheral-controller@8a20000 {

	compatible = "hisilicon,hi3798cv200-perictrl", "syscon",

		     "simple-mfd";

	reg = <0x8a20000 0x1000>;

	#address-cells = <1>;

	#size-cells = <1>;

	ranges = <0x0 0x8a20000 0x1000>;



	combphy0: phy@850 {

		compatible = "hisilicon,hi3798cv200-combphy";

		reg = <0x850 0x8>;

		#phy-cells = <1>;

		clocks = <&crg HISTB_COMBPHY0_CLK>;

		resets = <&crg 0x188 4>;

		hisilicon,fixed-mode = <PHY_TYPE_USB3>;

	};



	combphy1: phy@858 {

		compatible = "hisilicon,hi3798cv200-combphy";

		reg = <0x858 0x8>;

		#phy-cells = <1>;

		clocks = <&crg HISTB_COMBPHY1_CLK>;

		resets = <&crg 0x188 12>;

		hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;

	};

};

Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt

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Device tree bindings for HiSilicon INNO USB2 PHY



Required properties:

- compatible: Should be one of the following strings:

	"hisilicon,inno-usb2-phy",

	"hisilicon,hi3798cv200-usb2-phy".

- reg: Should be the address space for PHY configuration register in peripheral

  controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC.

- clocks: The phandle and clock specifier pair for INNO USB2 PHY device

  reference clock.

- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset

  signal.

- #address-cells: Must be 1.

- #size-cells: Must be 0.



The INNO USB2 PHY device should be a child node of peripheral controller that

contains the PHY configuration register, and each device suppports up to 2 PHY

ports which are represented as child nodes of INNO USB2 PHY device.



Required properties for PHY port node:

- reg: The PHY port instance number.

- #phy-cells: Defined by generic PHY bindings.  Must be 0.

- resets: The phandle and reset specifier pair for PHY port reset signal.



Refer to phy/phy-bindings.txt for the generic PHY binding properties



Example:



perictrl: peripheral-controller@8a20000 {

	compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd";

	reg = <0x8a20000 0x1000>;

	#address-cells = <1>;

	#size-cells = <1>;

	ranges = <0x0 0x8a20000 0x1000>;



	usb2_phy1: usb2-phy@120 {

		compatible = "hisilicon,hi3798cv200-usb2-phy";

		reg = <0x120 0x4>;

		clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;

		resets = <&crg 0xbc 4>;

		#address-cells = <1>;

		#size-cells = <0>;



		usb2_phy1_port0: phy@0 {

			reg = <0>;

			#phy-cells = <0>;

			resets = <&crg 0xbc 8>;

		};



		usb2_phy1_port1: phy@1 {

			reg = <1>;

			#phy-cells = <0>;

			resets = <&crg 0xbc 9>;

		};

	};



	usb2_phy2: usb2-phy@124 {

		compatible = "hisilicon,hi3798cv200-usb2-phy";

		reg = <0x124 0x4>;

		clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;

		resets = <&crg 0xbc 6>;

		#address-cells = <1>;

		#size-cells = <0>;



		usb2_phy2_port0: phy@0 {

			reg = <0>;

			#phy-cells = <0>;

			resets = <&crg 0xbc 10>;

		};

	};

};