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Commit 857d1a97 authored by Mark Rutland's avatar Mark Rutland Committed by Marc Zyngier
Browse files

arm64: KVM: set {v,}TCR_EL2 RES1 bits 



Currently we don't set the RES1 bits of TCR_EL2 and VTCR_EL2 when
configuring them, which could lead to unexpected behaviour when an
architectural meaning is defined for those bits.

Set the RES1 bits to avoid issues.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Suzuki Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 4ad9e16a

arch/arm64/include/asm/kvm_arm.h

+7 −3
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ 
			 SCTLR_EL2_SA | SCTLR_EL2_I)



/* TCR_EL2 Registers bits */

#define TCR_EL2_RES1	((1 << 31) | (1 << 23))

#define TCR_EL2_TBI	(1 << 20)

#define TCR_EL2_PS	(7 << 16)

#define TCR_EL2_PS_40B	(2 << 16)
@@ -106,9 +107,10 @@ 
#define TCR_EL2_MASK	(TCR_EL2_TG0 | TCR_EL2_SH0 | \

			 TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ)



#define TCR_EL2_FLAGS	(TCR_EL2_PS_40B)

#define TCR_EL2_FLAGS	(TCR_EL2_RES1 | TCR_EL2_PS_40B)



/* VTCR_EL2 Registers bits */

#define VTCR_EL2_RES1		(1 << 31)

#define VTCR_EL2_PS_MASK	(7 << 16)

#define VTCR_EL2_TG0_MASK	(1 << 14)

#define VTCR_EL2_TG0_4K		(0 << 14)
@@ -147,7 +149,8 @@ 
 */

#define VTCR_EL2_FLAGS		(VTCR_EL2_TG0_64K | VTCR_EL2_SH0_INNER | \

				 VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \

				 VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)

				 VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B | \

				 VTCR_EL2_RES1)

#define VTTBR_X		(38 - VTCR_EL2_T0SZ_40B)

#else

/*
@@ -158,7 +161,8 @@ 
 */

#define VTCR_EL2_FLAGS		(VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \

				 VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \

				 VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B)

				 VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B | \

				 VTCR_EL2_RES1)

#define VTTBR_X		(37 - VTCR_EL2_T0SZ_40B)

#endif